; -------------------------------------------------------------------------------- ; @Title: AM62Ax On-Chip Peripherals ; @Props: Released ; @Author: KRZ ; @Changelog: 2024-12-10 KRZ ; @Manufacturer: TI - Texas Instruments ; @Doc: Generated (TRACE32, build: 175251.), based on: AM62A.xml (CCS 20.0.0) ; @Core: Cortex-A53, Cortex-R5F, Cortex-M4F, C75x ; @Chip: AM62AX ; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: peram62ax.per 18764 2024-12-13 16:30:17Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 sif (CORENAME()=="C75X") AUTOINDENT.PUSH sif CORENAME()=="C71X"&&FILE.EXIST(~~/perc71x.per) tree.close "Core Registers (C71x)" INCLUDE ~~/perc71x.per tree.end elif CORENAME()=="C75X"&&FILE.EXIST(~~/perc75x.per) tree.close "Core Registers (C75x)" INCLUDE ~~/perc75x.per tree.end else tree.close "Core Registers (C7x)" base AVM:0x00000000 wgroup AVM:0x00++0 textline " Peripheral File Notification - " sif (CORENAME()=="C75X") button "show missing files" "DIALOG.MESSAGE ""Please check your installation for the possibly missing files: perc75x.per""" else button "show missing files" "DIALOG.MESSAGE ""Please check your installation for the possibly missing files: perc71x.per""" endif textline " ---------------------------------------------------------------" textline " The peripheral file for this SoC cannot be displayed. " textline " Possible reasons are: " textline " - it is missing in the local installation or under development " textline " - it is confidential " textline " " textline " As fallback only the core registers are shown. " textline " Please check www.lauterbach.com/scripts.html " textline " or contact support@lauterbach.com . " textline " " tree.end endif AUTOINDENT.POP endif sif (CORENAME()=="CORTEXM4F") tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited" bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15" bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,ARMv7-M" newline abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC24=Cortex-M4" bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif sif (CORENAME()=="CORTEXR5F") tree "Core Registers (Cortex-R5F)" AUTOINDENT.PUSH AUTOINDENT.OFF width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup.long c15:0x00++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" textline " " bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup.long c15:0x400--0x400 line.long 0x0 "MPUIR,MPU type register" hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions" bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated" rgroup.long c15:0x500++0x00 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system" textline " " hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2" hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1" hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0" textline " " rgroup.long c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " SL ,Number of Shareability levels implemented" "1,?..." bitfld.long 0x00 8.--11. " OS ,Outermost Shareability domain support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c15:0x020++0x00 line.long 0x00 "ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x120++0x00 line.long 0x00 "ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x220++0x00 line.long 0x00 "ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x320++0x00 line.long 0x00 "ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x420++0x00 line.long 0x00 "ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)" rgroup.long c15:0x0620++0x00 line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)" rgroup.long c15:0x0720++0x00 line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)" rgroup.long c15:0x010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." textline " " rgroup.long c15:0x210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c15:0x310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c15:0x02f++0x00 line.long 0x00 "BO1R,Build Options 1 Register" hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR ,Default high address for the TCM" bitfld.long 0x00 1. " FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented" textline " " bitfld.long 0x00 0. " PP_BUS_ECC ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented" group.long c15:0x12f++0x00 line.long 0x00 "BO2R,Build Options 2 Register" bitfld.long 0x00 31. " NUM_CPU ,Number of CPUs" "1,2" bitfld.long 0x00 30. " LOCK_STEP ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included" textline " " bitfld.long 0x00 29. " NO_ICACHE ,Indicate whether the CPU contains instruction cache" "Yes,No" bitfld.long 0x00 28. " NO_DCACHE ,Indicate whether the CPU contains data cache" "Yes,No" textline " " bitfld.long 0x00 26.--27. " ATCM_ES ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection" bitfld.long 0x00 23.--25. " BTCM_ES ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..." textline " " bitfld.long 0x00 23. " NO_IE ,Indicate whether the processor supports big-endian instructions" "Yes,No" bitfld.long 0x00 22. " NO_FPU ,Indicate whether the CPU contains a floating point unit" "Yes,No" textline " " bitfld.long 0x00 20.--21. " MPU_REGIONS ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions" bitfld.long 0x00 17.--19. " BREAK_POINTS ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 14.--16. " WATCH_POINTS ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " NO_A_TCM_INF ,Indicate whether the CPUs contain ATCM ports" "Yes,No" textline " " bitfld.long 0x00 12. " NO_B0_TCM_INF ,Indicate whether the CPUs contain B0TCM ports" "Yes,No" bitfld.long 0x00 11. " NO_B1_TCM_INF ,Indicate whether the CPUs contain B1TCM ports" "Yes,No" textline " " bitfld.long 0x00 10. " TCMBUSPARITY ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes" bitfld.long 0x00 9. " NO_SLAVE ,Indicate whether the CPU contains an AXI slave port" "Yes,No" textline " " bitfld.long 0x00 7.--8. " ICACHE_ES ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC" bitfld.long 0x00 5.--6. " DCACHE_ES ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..." textline " " bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No" bitfld.long 0x00 3. " AXI_BUS_ECC ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes" textline " " bitfld.long 0x00 2. " SL ,Indicate whether the processor has been built with split/lock logic" "No,Yes" bitfld.long 0x00 1. " AHB_PP ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes" textline " " bitfld.long 0x00 0. " MICRO_SCU ,Indicate whether the processor contain an ACP interface" "No,Yes" group.long c15:0x72f++0x00 line.long 0x00 "POR,Pin Options Register" bitfld.long 0x00 4. " DBGNOCLKSTOP ,Value of the DBGNOCLKSTOP pin" "Low,High" bitfld.long 0x00 3. " INTSYNCEN ,Value of the INTSYNCEN pin" "Low,High" textline " " bitfld.long 0x00 2. " IRQADDRVSYNCEN ,Value of the IRQADDRVSYNCEN pin" "Low,High" bitfld.long 0x00 1. " SLBTCMSB ,Value of the SLBTCMSBm pin" "Low,High" textline " " bitfld.long 0x00 0. " PARITYLEVEL ,Value of the PARITYLEVEL pin" "Low,High" tree.end width 0x8 tree "System Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x101++0x00 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable" bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable" bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable" bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" textline " " bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable" bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable" textline " " bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Enable,Disable" bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Enable,Disable" bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable" textline " " bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable" bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable" bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..." textline " " bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable" bitfld.long 0x00 13. " DLFO ,Disable linefill optimization in the AXI master" "Enable,Disable" bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable" textline " " bitfld.long 0x00 11. " DNCH ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable" bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced" bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced" textline " " bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced" bitfld.long 0x00 7. " SMOV ,sMOV disabled" "Enabled,Disabled" bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable" textline " " bitfld.long 0x00 3.--5. " CEC ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..." textline " " bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable" bitfld.long 0x00 1. " B0TCMECEN ,B0TCM external error enable" "Disable,Enable" bitfld.long 0x00 0. " ATCMECEN ,ATCM external error enable" "Disable,Enable" textline " " group.long c15:0x0f++0x00 line.long 0x00 "SACTLR,Secondary Auxiliary Control Register" bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable" bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable" bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable" bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable" bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable" textline " " bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable" bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate" bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate" bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate" bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate" bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable" bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable" textline " " bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable" bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable" textline " " group.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes" textline " " bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group.long c15:0x000b++0x00 line.long 0x00 "SPCR,Slave Port Control Register" bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only" bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled" tree.end width 0x8 tree "MPU Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x05++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x15++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x06++0x00 line.long 0x00 "DFAR,Data Fault Address Register" textline " " group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" textline " " group.long c15:0x0016++0x00 line.long 0x00 "RBAR,Region Base Address Register" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group.long c15:0x0216++0x00 line.long 0x00 "RSER,Region Size and Enable Register" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group.long c15:0x0416++0x00 line.long 0x00 "RACR,Region Access Control Register" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" group.long c15:0x0026++0x00 line.long 0x00 "MRNR,Memory Region Number Register" bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " group.long c15:0x010d++0x00 line.long 0x00 "CIDR,Context ID Register" group.long c15:0x20d++0x00 line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register" group.long c15:0x30d++0x00 line.long 0x00 "TIDRURO,User read only Thread and Process ID Register" group.long c15:0x40d++0x00 line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register" width 0x08 tree "MPU regions" group c15:0x0016++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RBAR0,Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RSER0,Region Size and Enable Register 0" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RACR0,Region Access Control Register 0" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RBAR1,Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RSER1,Region Size and Enable Register 1" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RACR1,Region Access Control Register 1" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RBAR2,Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RSER2,Region Size and Enable Register 2" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RACR2,Region Access Control Register 2" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RBAR3,Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RSER3,Region Size and Enable Register 3" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RACR3,Region Access Control Register 3" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RBAR4,Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RSER4,Region Size and Enable Register 4" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RACR4,Region Access Control Register 4" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RBAR5,Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RSER5,Region Size and Enable Register 5" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RACR5,Region Access Control Register 5" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RBAR6,Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RSER6,Region Size and Enable Register 6" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RACR6,Region Access Control Register 6" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RBAR7,Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RSER7,Region Size and Enable Register 7" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RACR7,Region Access Control Register 7" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RBAR8,Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RSER8,Region Size and Enable Register 8" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RACR8,Region Access Control Register 8" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RBAR9,Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RSER9,Region Size and Enable Register 9" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RACR9,Region Access Control Register 9" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RBAR10,Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RSER10,Region Size and Enable Register 10" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RACR10,Region Access Control Register 10" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RBAR11,Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RSER11,Region Size and Enable Register 11" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RACR11,Region Access Control Register 11" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RBAR12,Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RSER12,Region Size and Enable Register 12" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RACR12,Region Access Control Register 12" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RBAR13,Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RSER13,Region Size and Enable Register 13" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RACR13,Region Access Control Register 13" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RBAR14,Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RSER14,Region Size and Enable Register 14" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RACR14,Region Access Control Register 14" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RBAR15,Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RSER15,Region Size and Enable Register 15" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RACR15,Region Access Control Register 15" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " tree.end tree.end width 0x9 tree "TCM Control and Configuration" rgroup.long c15:0x200++0x00 line.long 0x00 "TCMTR,TCM Type Register" bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7" group.long c15:0x019++0x00 line.long 0x00 "BTCMRR,BTCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" group.long c15:0x119++0x00 line.long 0x00 "ATCMRR,ATCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" rgroup.long c15:0x29++0x00 line.long 0x00 "TCMSEL,TCM Selection Register" textline " " group.long c15:0x10f++0x00 line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x20f++0x00 line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x30f++0x00 line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" tree.end width 0xC tree "Cache Control and Configuration" rgroup.long c15:0x1100++0x00 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7" rgroup.long c15:0x1700++0x00 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets" hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity" textline " " bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7" group.long c15:0x2000++0x00 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Cache level to select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " IND ,Instruction or data or unified cache to use" "Data/unified,Instruction" group.long c15:0x03f++0x00 line.long 0x00 "CFLR,Correctable Fault Location Register" bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred" bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP" group.long c15:0x5f++0x00 line.long 0x00 "IADCR,Invalidate All Data Cache Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" group.long c15:0xef++0x00 line.long 0x00 "CSOR,Cache Size Override Register" bitfld.long 0x00 4.--7. " Dcache ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" bitfld.long 0x00 0.--3. " Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" tree.end width 12. tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x00 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable PMCCNTR when prohibited" "No,Yes" textline " " bitfld.long 0x00 4. " X ,Export enable" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock counter reset" "No action,Reset" bitfld.long 0x00 1. " P ,Event counter reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Enable" "Disabled,Enabled" group.long c15:0x1c9++0x00 line.long 0x00 "PMCNTENSET,Count Enable Set Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x0 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x0 "PMOVSR,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x0 "PMSWINC,Software Increment Register" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Event Type Selection Register" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected" group.long c15:0x02d9++0x00 line.long 0x00 "PMXEVCNTR,Event Count Register" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Counter Selection Register" bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Cycle Count Register" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "ESR0,Event Selection Register 0" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "PMCR0,Performance Monitor Count Register 0" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "ESR1,Event Selection Register 1" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "PMCR1,Performance Monitor Count Register 1" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "ESR2,Event Selection Register 2" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "PMCR2,Performance Monitor Count Register 2" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,User Enable Register" bitfld.long 0x00 0. " EN ,User mode access to performance monitor and validation registers" "Not allowed,Allowed" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Interrupt Enable Set Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" tree "Validation Registers" group.long c15:0x01f++0x00 line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x11f++0x00 line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x21f++0x00 line.long 0x00 "RESR,nVAL Reset Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x31f++0x00 line.long 0x00 "RESR,VAL Debug Request Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" group.long c15:0x41f++0x00 line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x51f++0x00 line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x61f++0x00 line.long 0x00 "RECR,nVAL Reset Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x71f++0x00 line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" tree.end tree.end width 11. width 18. tree "Debug Registers" tree "Processor Identifier Registers" rgroup.long c14:832.++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup.long c14:833.++0x00 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup.long c14:834.++0x00 line.long 0x00 "TCMTR,TCM Type Register" group.long c14:835.++0x00 line.long 0x00 "AMIDR,Alias of MIDR" rgroup.long c14:836.++0x00 line.long 0x00 "MPUTR,MPU Type Register" rgroup.long c14:837.++0x00 line.long 0x00 "MPIDR,Multiprocessor Affinity Register" group.long c14:838.++0x00 line.long 0x00 "AMIDR0,Alias of MIDR" group.long c14:839.++0x00 line.long 0x00 "AMIDR1,Alias of MIDR" rgroup.long c14:840.++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c14:841.++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c14:842.++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c14:843.++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c14:844.++0x00 line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c14:845.++0x00 line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c14:846.++0x00 line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c14:847.++0x00 line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c14:848.++0x00 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:849.++0x00 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c14:850.++0x00 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:851.++0x00 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c14:852.++0x00 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c14:853.++0x00 line.long 0x00 "ID_ISAR5,ISA Feature Register 5" tree.end width 15. tree "Coresight Management Registers" group.long c14:960.++0x00 line.long 0x00 "DBGITCTRL,Integration Mode Control Register" bitfld.long 0x00 0. " INTMODE ,Processor integration mode" "Normal,Integration" group.long c14:1000.++0x00 line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register" hexmask.long.byte 0x00 0.--7. 1. " CTS ,Claim tag set" group.long c14:1001.++0x00 line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register" hexmask.long.byte 0x00 0.--7. 1. " CTC ,Claim tag clear" wgroup.long c14:1004.++0x00 line.long 0x00 "DBGLAR,Lock Access Register" rgroup.long c14:1005.++0x00 line.long 0x00 "DBGLSR,Lock Status Register" bitfld.long 0x00 2. " 32BA ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes" textline " " bitfld.long 0x00 1. " LB ,Lock bit" "Not locked,Locked" bitfld.long 0x00 0. " LIB ,Lock implemented bit" "Not locked,Locked" rgroup.long c14:1006.++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register" bitfld.long 0x00 7. " SNDFI ,Secure non-invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 6. " SNDFE ,Secure non-invasive debug features enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SIDFI ,Secure invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 4. " SIDFE ,Secure invasive debug features enabled" "Disabled,Enabled" rgroup.long c14:1011.++0x00 line.long 0x00 "DBGDEVTYPE,Device Type Register" hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype" hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class" tree.end textline " " width 12. rgroup.long c14:0.++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version" textline " " bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High" bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Low,High" textline " " bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Low,High" bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Low,High" textline " " hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number" hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number" group.long c14:34.++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" textline " " bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" group.long c14:0x7++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 7. " FIQVCE_S ,FIQ vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IRQVCE_S ,IRQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. " DAVCE_S ,Data Abort vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PAVCE_S ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 2. " SVCVCE_S ,SVC vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " UIVCE_S ,Undefined instruction vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 0. " RVCE ,Reset vector catch enable" "Disabled,Enabled" hgroup.long c14:32.++0x0 hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register" in group.long c14:35.++0x00 line.long 0x0 "DTRTX,Host -> Target Data Transfer Register" hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data" group.long c14:10.++0x0 line.long 0x00 "DBGDSCCR,Debug State Cache Control Register" bitfld.long 0x00 2. " NWT ,Write through disable" "No,Yes" bitfld.long 0x00 1. " NIL ,L1 instruction cache line-fills disable" "No,Yes" textline " " bitfld.long 0x00 0. " NDL ,L1 data cache line-fills disable" "No,Yes" wgroup.long c14:33.++0x0 line.long 0x00 "DBGITR,Instruction Transfer Register" wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 4. " CMR ,Cancel memory requests" "Not cancel,Cancel" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" textline " " bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart" textline " " bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt" textline " " rgroup.long c14:193.++0x0 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented" group.long c14:196.++0x0 line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register" bitfld.long 0x00 2. " HCWR ,Hold core warm reset" "Not held,Held" textline " " bitfld.long 0x00 1. " CWRR ,Reset reguest" "Not requested,Requested" bitfld.long 0x00 0. " CORENPDRQ ,Core no powerdown request" "Power-down,Emulate" rgroup.long c14:197.++0x0 line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register" bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset" bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset" textline " " bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset" bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up" tree.end width 7. tree "Breakpoint Registers" group.long c14:64.++0x0 line.long 0x00 "BVR0,Breakpoint Value 0 Register" hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0" group.long c14:80.++0x0 line.long 0x00 "BCR0,Breakpoint Control 0 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:65.++0x0 line.long 0x00 "BVR1,Breakpoint Value 1 Register" hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1" group.long c14:81.++0x0 line.long 0x00 "BCR1,Breakpoint Control 1 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:66.++0x0 line.long 0x00 "BVR2,Breakpoint Value 2 Register" hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2" group.long c14:82.++0x0 line.long 0x00 "BCR2,Breakpoint Control 2 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:67.++0x0 line.long 0x00 "BVR3,Breakpoint Value 3 Register" hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3" group.long c14:83.++0x0 line.long 0x00 "BCR3,Breakpoint Control 3 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:68.++0x0 line.long 0x00 "BVR4,Breakpoint Value 4 Register" hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4" group.long c14:84.++0x0 line.long 0x00 "BCR4,Breakpoint Control 4 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:69.++0x0 line.long 0x00 "BVR5,Breakpoint Value 5 Register" hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5" group.long c14:85.++0x0 line.long 0x00 "BCR5,Breakpoint Control 5 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:70.++0x0 line.long 0x00 "BVR6,Breakpoint Value 6 Register" hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6" group.long c14:86.++0x0 line.long 0x00 "BCR6,Breakpoint Control 6 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:71.++0x0 line.long 0x00 "BVR7,Breakpoint Value 7 Register" hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7" group.long c14:87.++0x0 line.long 0x00 "BCR7,Breakpoint Control 7 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end tree "Watchpoint Control Registers" group.long c14:96.++0x0 line.long 0x00 "WVR0,Watchpoint Value 0 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:112.++0x0 line.long 0x00 "WCR0,Watchpoint Control 0 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:97.++0x0 line.long 0x00 "WVR1,Watchpoint Value 1 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:113.++0x0 line.long 0x00 "WCR1,Watchpoint Control 1 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:98.++0x0 line.long 0x00 "WVR2,Watchpoint Value 2 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:114.++0x0 line.long 0x00 "WCR2,Watchpoint Control 2 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:99.++0x0 line.long 0x00 "WVR3,Watchpoint Value 3 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:115.++0x0 line.long 0x00 "WCR3,Watchpoint Control 3 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:100.++0x0 line.long 0x00 "WVR4,Watchpoint Value 4 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:116.++0x0 line.long 0x00 "WCR4,Watchpoint Control 4 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:101.++0x0 line.long 0x00 "WVR5,Watchpoint Value 5 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:117.++0x0 line.long 0x00 "WCR5,Watchpoint Control 5 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:102.++0x0 line.long 0x00 "WVR6,Watchpoint Value 6 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:118.++0x0 line.long 0x00 "WCR6,Watchpoint Control 6 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:103.++0x0 line.long 0x00 "WVR7,Watchpoint Value 7 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:119.++0x0 line.long 0x00 "WCR7,Watchpoint Control 7 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:6.++0x0 line.long 0x00 "WFAR ,Watchpoint Fault Address Register" hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction" tree.end width 11. AUTOINDENT.POP tree.end endif sif (CORENAME()=="CORTEXA53") tree "Core Registers (Cortex-A53)" AUTOINDENT.PUSH AUTOINDENT.ON center tree tree.open "AArch64" tree "ID Registers" rgroup.quad spr:0x30000++0x0 line.quad 0x0 "MIDR_EL1,Main ID Register" hexmask.quad.byte 0x0 24.--31. 0x1 "IMPLEMENTER,Implementer code" bitfld.quad 0x0 20.--23. "VARIANT,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x0 16.--19. "ARCHITECTURE,Architecture" "Reserved,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme" newline hexmask.quad.word 0x0 4.--15. 0x1 "PARTNUM,Primary Part Number" bitfld.quad 0x0 0.--3. "REVISION,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x30005++0x00 line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register" bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" newline hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" bitfld.quad 0x00 0.--1. "CPU_ID,CPU ID" "1,2,3,4" elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30005++0x00 line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity level 3. Third highest level affinity field" newline bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" newline hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field" endif rgroup.quad SPR:0x30006++0x0 line.quad 0x0 "REVIDR_EL1,Revision ID Register" rgroup.quad SPR:0x30014++0x00 line.quad 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "INNERSHR,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.quad 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "AUXREG,Auxiliary Register Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.quad 0x00 12.--15. "SHARELVL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.quad 0x00 8.--11. "OUTERSHR,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.quad 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.quad SPR:0x30015++0x00 line.quad 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1" bitfld.quad 0x00 28.--31. "BPRED,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.quad 0x00 24.--27. "L1TSTCLN,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "L1UNI,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 16.--19. "L1HVD,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 12.--15. "L1UNISW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "L1HVDSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "L1UNIVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "L1HVDVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.quad SPR:0x30016++0x00 line.quad 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2" bitfld.quad 0x00 28.--31. "HWACCFLG,Hardware Access Flag Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "WFISTALL,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "MEMBARR,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "UNITLB,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "HVDTLB,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "LL1HVDRNG,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "L1HVDBG,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "L1HVDFG,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.quad SPR:0x30017++0x00 line.quad 0x00 "ID_MMFR3_EL1,Memory Model Feature Register 3" bitfld.quad 0x00 28.--31. "SUPERSEC,Supersection support" "Supported,?..." bitfld.quad 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.quad 0x00 20.--23. "COHWALK,Coherent walk" "Reserved,Supported,Reserved,?..." newline bitfld.quad 0x00 12.--15. "MAINTBCST,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BPMAINT,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "CMAINTSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "CMAINTVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.quad spr:0x30026++0x00 line.quad 0x00 "ID_MMFR4_EL1,Memory Model Feature Register 4" bitfld.quad 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "TGRAN4,4KB granule supported" "Supported,?..." bitfld.quad 0x00 24.--27. "TGRAN64,64KB granule supported" "Supported,?..." bitfld.quad 0x00 20.--23. "TGRAN16,16KB granule supported" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." newline bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "TGRAN4,4KB granule supported" "Supported,?..." bitfld.quad 0x00 24.--27. "TGRAN64,64KB granule supported" "Supported,?..." bitfld.quad 0x00 20.--23. "TGRAN16,16KB granule supported" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." newline bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..." endif if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30071++0x00 line.quad 0x00 "ID_AA64MMFR1_EL1,AArch64 Memory Model Feature Register 1" endif rgroup.quad SPR:0x30020++0x00 line.quad 0x00 "ID_ISAR0_EL1,Instruction Set Attribute Register 0" bitfld.quad 0x00 24.--27. "DIVIDE,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "DEBUG,Debug Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 16.--19. "COPROC,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "CMPBRANCH,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BITFIELD,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "BITCOUNT,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "SWAP,Swap Instructions Support" "Not supported,?..." rgroup.quad SPR:0x30021++0x00 line.quad 0x00 "ID_ISAR1_EL1,Instruction Set Attribute Register 1" bitfld.quad 0x00 28.--31. "JAZELLE,Jazelle instructions support" "Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "INTERWORK,Interwork instructions support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "IMMEDIATE,Immediate instructions support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "IFTHEN,If then instructions support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "EXTEND,Extend instructions support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "EXCEPT_AR,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "EXCEPT,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "ENDIAN,Endian Instructions Support" "Reserved,Supported,?..." rgroup.quad SPR:0x30022++0x00 line.quad 0x00 "ID_ISAR2_EL1,Instruction Set Attribute Register 2" bitfld.quad 0x00 28.--31. "REVERSAL,Reversal instructions support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "PSR_AR,PSR Instructions support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "MULTU,Advanced unsigned multiply instructions support" "Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "MULTS,Advanced signed multiply instructions support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "MULT,Multiply instructions support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "MULTIACCESSINT,Multi-access interruptible instructions support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "MEMHINT,Memory hint instructions support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "LOADSTORE,Load and store instructions support" "Reserved,Reserved,Supported,?..." rgroup.quad SPR:0x30023++0x00 line.quad 0x00 "ID_ISAR3_EL1,Instruction Set Attribute Register 3" bitfld.quad 0x00 28.--31. "T32EE,Thumb-EE Extensions Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "TRUENOP,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "T32COPY,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "TABBRANCH,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..." bitfld.quad 0x00 12.--15. "SYNCHPRIM,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "SVC,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "SIMD,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SATURATE,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.quad SPR:0x30024++0x00 line.quad 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4" bitfld.quad 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "PSR_M,PSR_M Instructions Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "SYNCHPRIM_FRAC,Synchronization Primitive instructions" "Supported,?..." newline bitfld.quad 0x00 16.--19. "BARRIER,Barrier Instructions support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SMC,SMC Instructions support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "WRITEBACK,Write-Back Instructions support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "WITHSHIFTS,With-Shift Instructions support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "UNPRIV,Unprivileged Instructions support" "Reserved,Reserved,Supported,?..." rgroup.quad SPR:0x30025++0x00 line.quad 0x00 "ID_ISAR5_EL1,Instruction Set Attribute Register 5" bitfld.quad 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.quad 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.quad 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30060++0x00 line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0" bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..." bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions are implemented" "Not implemented,Implemented,?..." bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions are implemented" "Not implemented,Implemented,?..." newline bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..." if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30061++0x00 line.quad 0x00 "ID_AA64ISAR1_EL1,AArch64 Instruction Set Attribute Register 1" endif rgroup.quad SPR:0x30010++0x00 line.quad 0x00 "ID_PFR0_EL1,Processor Feature Register 0" bitfld.quad 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.quad SPR:0x30011++0x00 line.quad 0x00 "ID_PFR1_EL1,Processor Feature Register 1" bitfld.quad 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." bitfld.quad 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "V,Virtualization Extensions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." bitfld.quad 0x00 4.--7. "S,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0" bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..." bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,?..." bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,?..." newline bitfld.quad 0x00 12.--15. "EL3,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 8.--11. "EL2,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 4.--7. "EL1,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." newline bitfld.quad 0x00 0.--3. "EL0,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0" bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..." bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.quad 0x00 12.--15. "EL3,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 8.--11. "EL2,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 4.--7. "EL1,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." newline bitfld.quad 0x00 0.--3. "EL0,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." endif if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30041++0x00 line.quad 0x00 "ID_AA64PFR1_EL1,AArch64 Processor Feature Register 1" endif if (CORENAME()=="CORTEXA57") rgroup.quad SPR:0x30012++0x00 line.quad 0x00 "ID_DFR0_EL1,Debug Feature Register 0" bitfld.quad 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "MPROFDBG,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.quad 0x00 16.--19. "MMAPTRC,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "COPTRC,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "MMAPDBG,Memory-Mapped Debug Model Support" "Not supported,?..." bitfld.quad 0x00 4.--7. "COPSDBG,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "COPDBG,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad SPR:0x30012++0x00 line.quad 0x00 "ID_DFR0_EL1,Debug Feature Register 0" bitfld.quad 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "MPROFDBG,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.quad 0x00 16.--19. "MMAPTRC,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "COPTRC,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.quad 0x00 4.--7. "COPSDBG,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "COPDBG,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." endif rgroup.quad spr:0x30050++0x00 line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0" bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,2,?..." bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,4,?..." bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." newline bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,Implemented,?..." bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..." bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented,?..." if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30051++0x00 line.quad 0x00 "ID_AA64DFR1_EL1,AArch64 Debug Feature Register 1" rgroup.quad spr:0x30054++0x00 line.quad 0x00 "ID_AA64AFR0_EL1,AArch64 Auxiliary Feature Register 0" rgroup.quad spr:0x30055++0x00 line.quad 0x00 "ID_AA64AFR1_EL1,AArch64 Auxiliary Feature Register 1" endif rgroup.quad SPR:0x30013++0x00 line.quad 0x00 "ID_AFR0_EL1,Auxiliary Feature Register 0" rgroup.quad SPR:0x31007++0x00 line.quad 0x00 "AIDR_EL1,Auxiliary ID Register" rgroup.quad SPR:0x33007++0x00 line.quad 0x00 "DCZID_EL0,Data Cache Zero ID" bitfld.quad 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited" bitfld.quad 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x30030++0x00 "Media and VFP Feature registers" line.quad 0x00 "MVFR0_EL1,Media and VFP Feature Register 0/EL1" bitfld.quad 0x00 28.--31. "FPROUND,Indicates the rounding modes supported by the floating-point hardware" "Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "FPSHVEC,Indicates the hardware support for floating-point short vectors" "Not supported,?..." bitfld.quad 0x00 20.--23. "FPSQRT,Indicates the hardware support for floating-point square root operations" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "FPDIVIDE,Indicates the hardware support for floating-point divide operations" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "FPTRAP,Indicates whether the floating-point hardware implementation supports exception trapping" "Not supported,?..." bitfld.quad 0x00 8.--11. "FPDP,Indicates the hardware support for floating-point double-precision operations" "Reserved,Reserved,VFPv3 or greater,?..." newline bitfld.quad 0x00 4.--7. "FPSP,Indicates the hardware support for floating-point single-precision operations" "Reserved,Reserved,VFPv3 or greater,?..." bitfld.quad 0x00 0.--3. "SIMDREG,Indicates support for the Advanced SIMD register bank" "Reserved,Reserved,32x64-bit,?..." rgroup.quad spr:0x30031++0x00 line.quad 0x00 "MVFR1_EL1,Media and VFP Feature Register 1/EL1" bitfld.quad 0x00 28.--31. "SIMDFMAC,Indicates whether Advanced SIMD or floating-point supports fused multiply accumulate operations" "Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "FPHP,Indicates whether floating-point supports half-precision floating-point conversion operations" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "SIMDHP,Indicates whether Advanced SIMD supports half-precision floating-point conversion operations" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "SIMDSP,Indicates whether Advanced SIMD supports single-precision floating-point operations" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SIMDINT,Indicates whether Advanced SIMD supports integer operations" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "SIMDLS,Indicates whether Advanced SIMD supports load/store instructions" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "FPDNAN,Indicates whether the floating-point hardware implementation supports only the Default NaN mode" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "FPFTZ,Indicates whether the floating-point hardware implementation supports only the Flush-to-Zero mode of operation" "Reserved,Supported,?..." rgroup.quad spr:0x30032++0x00 line.quad 0x00 "MVFR2_EL1,Media and VFP Feature Register 2/EL1" bitfld.quad 0x00 4.--7. "FPMISC,Indicates support for miscellaneous floating-point features. Supported = Selection/Conversion to Integer with Directed Rounding/Round to Integral Floating-point/MaxNum/MinNum" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SIMDMISC,Indicates support for miscellaneous Advanced SIMD features. Supported = Selection/Conversion to Integer with Directed Rounding/Round to Integral Floating-point/MaxNum/MinNum" "Reserved,Reserved,Reserved,Supported,?..." endif tree.end tree "System Control and Configuration" group.quad spr:0x36111++0x00 line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register" bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled" bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled" group.quad SPR:0x30100++0x0 line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)" bitfld.quad 0x0 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.quad 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.quad 0x0 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.quad 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.quad 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.quad 0x0 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.quad 0x0 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.quad 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x0 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.quad 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.quad 0x0 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.quad 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled" bitfld.quad 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.quad 0x0 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad SPR:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x0 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad SPR:0x36100++0x0 line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)" bitfld.quad 0x0 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" rgroup.quad SPR:0x30101++0x0 line.quad 0x00 "ACTLR_EL1,Auxiliary Control Register (EL1)" if (CORENAME()=="CORTEXA53") group.quad SPR:0x34101++0x0 line.quad 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)" bitfld.quad 0x00 6. "L2ACTLR_EL1,L2ACTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 5. "L2ECTLR_EL1,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 4. "L2CTLR_EL1,L2CTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 1. "CPUECTLR_EL1,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CPUACTLR_EL1,CPUACTLR write access control" "Disabled,Enabled" group.quad SPR:0x36101++0x0 line.quad 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)" bitfld.quad 0x00 6. "L2ACTLR_EL1,L2ACTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 5. "L2ECTLR_EL1,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 4. "L2CTLR_EL1,L2CTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 1. "CPUECTLR_EL1,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CPUACTLR_EL1,CPUACTLR write access control" "Disabled,Enabled" elif (CORENAME()=="CORTEXA57") group.quad SPR:0x34101++0x0 line.quad 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)" bitfld.quad 0x00 6. "L2ACTLR,L2ACTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 5. "L2ECTLR,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 4. "L2CTLR,L2CTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 1. "CPUECTLR,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CPUACTLR,CPUACTLR write access control" "Disabled,Enabled" group.quad SPR:0x36101++0x0 line.quad 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)" bitfld.quad 0x00 6. "L2ACTLR,L2ACTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 5. "L2ECTLR,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 4. "L2CTLR,L2CTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 1. "CPUECTLR,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CPUACTLR,CPUACTLR write access control" "Disabled,Enabled" endif group.quad SPR:0x30102++0x00 line.quad 0x00 "CPACR_EL1,Architectural Feature Access Control Register" bitfld.quad 0x00 28. "TTA,Causes access to the Trace functionality to trap to EL1 when executed from EL0 or EL1" "Disabled,?..." bitfld.quad 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "Trap all,Trap El0,Trap all,Not trapped" group.quad SPR:0x36110++0x0 line.quad 0x0 "SCR_EL3,Secure Configuration Register" bitfld.quad 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.quad 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.quad 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled" bitfld.quad 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64" newline bitfld.quad 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.quad 0x00 8. "HCE,Hypervisor Call enable" "No,Yes" newline bitfld.quad 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes" bitfld.quad 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" newline bitfld.quad 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.quad 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" newline bitfld.quad 0x00 0. "NS,Secure mode" "Secure,Non-secure" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" group.quad spr:0x30510++0x00 line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)" group.quad spr:0x30511++0x00 line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)" group.quad spr:0x34510++0x00 line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)" group.quad spr:0x34511++0x00 line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)" group.quad spr:0x36510++0x00 line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)" group.quad spr:0x36511++0x00 line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)" tree.open "Exception Syndrome Registers" if (CORENAME()=="CORTEXA57") if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.quad.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.quad.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" hexmask.quad.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000)) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" hexmask.quad.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined" elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.quad.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif elif (CORENAME()=="CORTEXA53") if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SES,System Error Source" "Processor,System,External," newline hexmask.quad.tbyte 0x00 0.--21. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" hexmask.quad.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.quad.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" hexmask.quad.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000)) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined" elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.quad.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000) group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif endif tree.end newline if (CORENAME()=="CORTEXA57") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif elif (CORENAME()=="CORTEXA53") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif endif group.quad spr:0x30600++0x00 line.quad 0x00 "FAR_EL1,Fault Address Register" group.quad spr:0x34600++0x00 line.quad 0x00 "FAR_EL2,Fault Address Register" group.quad spr:0x36600++0x00 line.quad 0x00 "FAR_EL3,Fault Address Register" group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" group.quad spr:0x30C00++0x00 line.quad 0x00 "VBAR_EL1,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address" group.quad spr:0x34C00++0x00 line.quad 0x00 "VBAR_EL2,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address" group.quad spr:0x36C00++0x00 line.quad 0x00 "VBAR_EL3,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x36C01++0x00 line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register" hexmask.quad.pbyte 0x00 2.--43. 0x1 "RVBA,Reset Vector Base Address" elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x36C01++0x00 line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register" hexmask.quad.pbyte 0x00 2.--39. 0x1 "RVBA,Reset Vector Base Address" endif rgroup.quad SPR:0x30C10++0x00 line.quad 0x00 "ISR_EL1,Interrupt Status Register" bitfld.quad 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.quad 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" newline bitfld.quad 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.quad SPR:0x36C02++0x00 line.quad 0x00 "RMR_EL3,Reset Management Register" bitfld.quad 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.quad 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x31F30++0x00 line.quad 0x00 "CBAR_EL1,Configuration Base Address Register" hexmask.quad.long 0x00 18.--43. 1. "PERIPHBASE[43:18],Periphbase[43:18]" elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x31F30++0x00 line.quad 0x00 "CBAR_EL1,Configuration Base Address Register" hexmask.quad.tbyte 0x00 18.--39. 1. "PERIPHBASE[39:18],Periphbase[39:18]" endif group.quad spr:0x30D01++0x00 line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register" hexmask.quad.long 0x00 0.--31. 1. "PROCID,Process identifier" group.quad spr:0x33D02++0x00 line.quad 0x00 "TPIDR_EL0,Software Thread ID Register" group.quad spr:0x33D03++0x00 line.quad 0x00 "TPIDRRO_EL0,Software Thread ID Register" group.quad spr:0x30D04++0x00 line.quad 0x00 "TPIDR_EL1,Software Thread ID Register" group.quad spr:0x34D02++0x00 line.quad 0x00 "TPIDR_EL2,Software Thread ID Register" group.quad spr:0x36D02++0x00 line.quad 0x00 "TPIDR_EL3,Software Thread ID Register" tree.end tree "Memory Management Unit" group.quad spr:0x30100++0x0 line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)" bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.quad 0x00 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x36100++0x0 line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x30200++0x00 line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x30201++0x00 line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)" bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..." newline bitfld.quad 0x00 30. "TG1,TTBR1_EL1 granule size" "4 KByte,64 KByte" bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB" newline bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)" bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,Reserved,4 KB,64 KB" bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 7. "EPD0,Translation table walk disable for translations using TTBR0" "Enabled,Disabled" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x34200++0x00 line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..." newline bitfld.quad 0x00 14. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x36200++0x00 line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..." newline bitfld.quad 0x00 14. "TGO,TTBR0_EL3 granule size" "4 KB,64 KB" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad SPR:0x34300++0x00 line.quad 0x00 "DACR32_EL2,Domain Access Control Register" bitfld.quad 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.quad 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.quad 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.quad 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.quad 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.quad 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.quad 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.quad 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.quad 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if (CORENAME()=="CORTEXA57") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif elif (CORENAME()=="CORTEXA53") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif endif rgroup.quad SPR:0x30510++0x00 line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)" rgroup.quad SPR:0x34510++0x00 line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)" rgroup.quad SPR:0x36510++0x00 line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)" rgroup.quad SPR:0x30511++0x00 line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)" rgroup.quad SPR:0x34511++0x00 line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)" rgroup.quad SPR:0x36511++0x00 line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)" if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device-not nGnRnE,?..." newline hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif (((per.q(spr:0x30740))&0x01)==0x00) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" newline hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" newline bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline bitfld.quad 0x00 1.--6. "FST,Fault status field" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Reserved,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,?..." newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif tree.open "Memory Attribute Indirection Registers" group.quad spr:0x30A20++0x00 line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" group.quad spr:0x34A20++0x00 line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" group.quad spr:0x36A20++0x00 line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" rgroup.quad spr:0x30A30++0x00 line.quad 0x00 "AMAIR_EL1,Memory Attribute Indirection Register (EL1)" rgroup.quad spr:0x34A30++0x00 line.quad 0x00 "AMAIR_EL2,Memory Attribute Indirection Register (EL2)" rgroup.quad spr:0x36A30++0x00 line.quad 0x00 "AMAIR_EL3,Memory Attribute Indirection Register (EL3)" tree.end newline group.quad SPR:0x30D01++0x00 line.quad 0x0 "CONTEXTIDR_EL1,Context ID Register" tree.end tree "Virtualization Extensions" group.quad SPR:0x34000++0x0 line.quad 0x0 "VPIDR_EL2,Virtualization Processor ID Register" hexmask.quad.byte 0x00 24.--31. 0x01 "IMPLEMENTER,Implementer code" bitfld.quad 0x00 20.--23. "VARIANT,Indicates the major revision of the product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "ARCHITECTURE,Architecture" "Reserved,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Defined by ID registers" newline hexmask.quad.word 0x00 4.--15. 1. "PARTNUM,Primary part number" bitfld.quad 0x00 0.--3. "REVISION,Indicates the minor revision of the product" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (CORENAME()=="CORTEXA57") group.quad spr:0x34005++0x00 line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register" bitfld.quad 0x00 30. "U,Indicates a uniprocessor system" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach" "Largely independent,Very interdependent" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Second highest level affinity field" hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Third highest level affinity field" bitfld.quad 0x00 0.--1. "CPU_ID,Indicates the core number in the Cortex-A57 device" "1,2,3,4" elif (CORENAME()=="CORTEXA53") group.quad spr:0x34005++0x00 line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register" bitfld.quad 0x00 30. "U,Indicates a uniprocessor system" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach" "Largely independent,?..." newline hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Second highest level affinity field" hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Third highest level affinity field" hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Lowest level affinity field" endif group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" if (CORENAME()=="CORTEXA57") group.quad SPR:0x34111++0x00 line.quad 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)" bitfld.quad 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" newline bitfld.quad 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" bitfld.quad 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.quad 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.quad 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (CORENAME()=="CORTEXA53") group.quad SPR:0x34111++0x00 line.quad 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)" bitfld.quad 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" newline bitfld.quad 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" bitfld.quad 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.quad 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.quad 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6" endif group.quad SPR:0x34112++0x00 line.quad 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)" bitfld.quad 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.quad 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad SPR:0x36131++0x00 line.quad 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)" bitfld.quad 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.quad 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" bitfld.quad 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" newline bitfld.quad 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes" bitfld.quad 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" group.quad SPR:0x36112++0x00 line.quad 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)" bitfld.quad 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.quad 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad SPR:0x34113++0x00 line.quad 0x00 "HSTR_EL2,Hypervisor System Trap Register" bitfld.quad 0x00 16. "TEEE,Trap ThumbEE" "Not supported,?..." bitfld.quad 0x00 15. "T15,Trap coprocessor primary register CRn = 15" "No effect,Trapped" bitfld.quad 0x00 13. "T13,Trap coprocessor primary register CRn = 13" "No effect,Trapped" newline bitfld.quad 0x00 12. "T12,Trap coprocessor primary register CRn = 12" "No effect,Trapped" bitfld.quad 0x00 11. "T11,Trap coprocessor primary register CRn = 11" "No effect,Trapped" bitfld.quad 0x00 10. "T10,Trap coprocessor primary register CRn = 10" "No effect,Trapped" newline bitfld.quad 0x00 9. "T9,Trap coprocessor primary register CRn = 9" "No effect,Trapped" bitfld.quad 0x00 8. "T8,Trap coprocessor primary register CRn = 8" "No effect,Trapped" bitfld.quad 0x00 7. "T7,Trap coprocessor primary register CRn = 7" "No effect,Trapped" newline bitfld.quad 0x00 6. "T6,Trap coprocessor primary register CRn = 6" "No effect,Trapped" bitfld.quad 0x00 5. "T5,Trap coprocessor primary register CRn = 5" "No effect,Trapped" bitfld.quad 0x00 3. "T3,Trap coprocessor primary register CRn = 3" "No effect,Trapped" newline bitfld.quad 0x00 2. "T2,Trap coprocessor primary register CRn = 2" "No effect,Trapped" bitfld.quad 0x00 1. "T1,Trap coprocessor primary register CRn = 1" "No effect,Trapped" bitfld.quad 0x00 0. "T0,Trap coprocessor primary register CRn = 0" "No effect,Trapped" rgroup.quad SPR:0x34117++0x00 line.quad 0x00 "HACR_EL2,Hypervisor Auxiliary Configuration Register" group.quad spr:0x34210++0x00 line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad SPR:0x34212++0x00 line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.quad 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..." bitfld.quad 0x00 14. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB" bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3" bitfld.quad 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.quad 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad SPR:0x34212++0x00 line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.quad 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,?..." bitfld.quad 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3" bitfld.quad 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.quad 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting IPA bits" tree.end tree "Cache Control and Configuration" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x33001++0x0 line.quad 0x0 "CTR_EL0,Cache Type Register" bitfld.quad 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.quad 0x0 14.--15. "L1IP,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.quad 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x33001++0x0 line.quad 0x0 "CTR_EL0,Cache Type Register" bitfld.quad 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.quad 0x0 14.--15. "L1IP,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.quad 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." endif group.quad SPR:0x32000++0x0 line.quad 0x0 "CSSELR_EL1,Cache Size Selection Register" bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" if (CORENAME()=="CORTEXA57") rgroup.quad SPR:0x31001++0x0 line.quad 0x0 "CLIDR_EL1,Cache Level ID Register" bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.quad 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." newline bitfld.quad 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." bitfld.quad 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.quad 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.quad 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." rgroup.quad SPR:0x31000++0x0 line.quad 0x0 "CCSIDR_EL1,Current Cache Size ID Register" bitfld.quad 0x00 31. "WT,Write-Through" "Not Supported,?..." bitfld.quad 0x00 30. "WB,Write-Back" "Not Supported,Supported" bitfld.quad 0x00 29. "RA,Read-Allocate" "Reserved,Supported" newline bitfld.quad 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" hexmask.quad.word 0x00 13.--27. 1. 1. "NUMSETS,Number of Sets" hexmask.quad.word 0x00 3.--12. 1. 1. "ASSOCIATIVITY,Associativity" newline bitfld.quad 0x00 0.--2. "LINESIZE,Line Size" "Reserved,Reserved,64 bytes,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad SPR:0x31001++0x0 line.quad 0x0 "CLIDR_EL1,Cache Level ID Register" bitfld.quad 0x00 30.--32. "ICB,Inner cache boundary" "Not disclosed,?..." bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.quad 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..." newline bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..." bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." rgroup.quad SPR:0x31000++0x0 line.quad 0x0 "CCSIDR_EL1,Current Cache Size ID Register" bitfld.quad 0x00 31. "WT,Write-Through" "Not Supported,?..." bitfld.quad 0x00 30. "WB,Write-Back" "Not Supported,Supported" bitfld.quad 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" newline bitfld.quad 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" hexmask.quad.word 0x00 13.--27. 1. 1. "NUMSETS,Number of Sets" hexmask.quad.word 0x00 3.--12. 1. 1. "ASSOCIATIVITY,Associativity" newline bitfld.quad 0x00 0.--2. "LINESIZE,Line Size" "1Reserved,Reserved,64 bytes,?..." endif tree "Level 1 memory system" if (CORENAME()=="CORTEXA57") group.quad SPR:0x30F10++0x00 line.quad 0x00 "DL1DATA0_EL1,Data L1 Data 0 Register" group.quad SPR:0x30F11++0x00 line.quad 0x00 "DL1DATA1_EL1,Data L1 Data 1 Register" group.quad SPR:0x30F12++0x00 line.quad 0x00 "DL1DATA2_EL1,Data L1 Data 2 Register" group.quad SPR:0x30F13++0x00 line.quad 0x00 "DL1DATA3_EL1,Data L1 Data 3 Register" group.quad SPR:0x30F00++0x00 line.quad 0x00 "IL1DATA0_EL1,Instruction L1 Data 0 Register" group.quad SPR:0x30F01++0x00 line.quad 0x00 "IL1DATA1_EL1,Instruction L1 Data 1 Register" group.quad SPR:0x30F02++0x00 line.quad 0x00 "IL1DATA2_EL1,Instruction L1 Data 2 Register" group.quad SPR:0x30F03++0x00 line.quad 0x00 "IL1DATA3_EL1,Instruction L1 Data 3 Register" group.quad spr:0x31F20++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" newline bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled" bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" newline bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" newline bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes" bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" newline bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" newline bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" newline bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" newline bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" newline bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" newline bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad spr:0x31F21++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines" bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines" newline bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..." bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..." elif (CORENAME()=="CORTEXA53") group.quad spr:0x31F20++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" bitfld.quad 0x00 44. "ENDCCASCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes" bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes" newline bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled" bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes" newline bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes" bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes" bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes" newline bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams" bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled" bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled" newline bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,8" bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes" bitfld.quad 0x00 6. "L1DEIEN,L1 D-cache data RAM error injection enable" "Disabled,Enabled" group.quad spr:0x31F21++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" endif if (CORENAME()=="CORTEXA57") group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address" elif (CORENAME()=="CORTEXA53") group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address" endif tree.end tree "Level 2 memory system" if (CORENAME()=="CORTEXA57") group.quad SPR:0x31B02++0x0 line.quad 0x00 "L2CTLR_EL1,L2 Control Register" bitfld.quad 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes" bitfld.quad 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" rbitfld.quad 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled" newline bitfld.quad 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" bitfld.quad 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled" rbitfld.quad 0x00 13. "L2AS,L2 arbitration slice" "Not presented,Presented" newline rbitfld.quad 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not presented,Presented" rbitfld.quad 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not presented,1,2,?..." bitfld.quad 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" newline bitfld.quad 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" rbitfld.quad 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle" bitfld.quad 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" group.quad SPR:0x31B03++0x0 line.quad 0x00 "L2ECTLR_EL1,L2 Extended Control Register" bitfld.quad 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.quad 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.quad 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad SPR:0x31F00++0x00 line.quad 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register" bitfld.quad 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" bitfld.quad 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" newline bitfld.quad 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" bitfld.quad 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes" bitfld.quad 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.quad 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled" bitfld.quad 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" bitfld.quad 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" newline bitfld.quad 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" bitfld.quad 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.quad 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" newline bitfld.quad 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" bitfld.quad 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" bitfld.quad 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" newline bitfld.quad 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" bitfld.quad 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" bitfld.quad 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" newline bitfld.quad 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" bitfld.quad 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" bitfld.quad 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" newline bitfld.quad 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" bitfld.quad 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" elif (CORENAME()=="CORTEXA53") group.quad SPR:0x31B02++0x0 line.quad 0x00 "L2CTLR_EL1,L2 Control Register" bitfld.quad 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" bitfld.quad 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled" rbitfld.quad 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" newline rbitfld.quad 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle" rbitfld.quad 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles" group.quad SPR:0x31B03++0x0 line.quad 0x00 "L2ECTLR_EL1,L2 Extended Control Register" bitfld.quad 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.quad 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.quad 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad SPR:0x31F00++0x00 line.quad 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register" bitfld.quad 0x00 30.--31. "L2VC,L2 Victim Control" "0,1,2,3" bitfld.quad 0x00 29. "L2DEIEN,L2 cache data RAM error injection enable" "Disabled,Enabled" bitfld.quad 0x00 24. "L2TEIEN,L2 cache tag RAM error injection enable." "Disabled,Enabled" newline bitfld.quad 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" bitfld.quad 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address" endif tree.end tree.end tree "System Performance Monitor" group.quad SPR:0x339C0++0x00 line.quad 0x0 "PMCR_EL0,Performance Monitor Control Register" hexmask.quad.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.quad.byte 0x00 16.--23. 1. "IDCODE,Identification code" bitfld.quad 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.quad 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.quad 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.quad 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.quad 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.quad 0x00 0. "E,All Counters Enable" "Disabled,Enabled" group.quad SPR:0x339C1++0x00 line.quad 0x00 "PMCNTENSET_EL0,Count Enable Set Register" bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.quad 0x00 30. "P30,Event Counter 30 enable bit" "Disabled,Enabled" bitfld.quad 0x00 29. "P29,Event Counter 29 enable bit" "Disabled,Enabled" bitfld.quad 0x00 28. "P28,Event Counter 28 enable bit" "Disabled,Enabled" newline bitfld.quad 0x00 27. "P27,Event Counter 27 enable bit" "Disabled,Enabled" bitfld.quad 0x00 26. "P26,Event Counter 26 enable bit" "Disabled,Enabled" bitfld.quad 0x00 25. "P25,Event Counter 25 enable bit" "Disabled,Enabled" bitfld.quad 0x00 24. "P24,Event Counter 24 enable bit" "Disabled,Enabled" newline bitfld.quad 0x00 23. "P23,Event Counter 23 enable bit" "Disabled,Enabled" bitfld.quad 0x00 22. "P22,Event Counter 22 enable bit" "Disabled,Enabled" bitfld.quad 0x00 21. "P21,Event Counter 21 enable bit" "Disabled,Enabled" bitfld.quad 0x00 20. "P20,Event Counter 20 enable bit" "Disabled,Enabled" newline bitfld.quad 0x00 19. "P19,Event Counter 19 enable bit" "Disabled,Enabled" bitfld.quad 0x00 18. "P18,Event Counter 18 enable bit" "Disabled,Enabled" bitfld.quad 0x00 17. "P17,Event Counter 17 enable bit" "Disabled,Enabled" bitfld.quad 0x00 16. "P16,Event Counter 16 enable bit" "Disabled,Enabled" newline bitfld.quad 0x00 15. "P15,Event Counter 15 enable bit" "Disabled,Enabled" bitfld.quad 0x00 14. "P14,Event Counter 14 enable bit" "Disabled,Enabled" bitfld.quad 0x00 13. "P13,Event Counter 13 enable bit" "Disabled,Enabled" bitfld.quad 0x00 12. "P12,Event Counter 12 enable bit" "Disabled,Enabled" newline bitfld.quad 0x00 11. "P11,Event Counter 11 enable bit" "Disabled,Enabled" bitfld.quad 0x00 10. "P10,Event Counter 10 enable bit" "Disabled,Enabled" bitfld.quad 0x00 9. "P9,Event Counter 9 enable bit" "Disabled,Enabled" bitfld.quad 0x00 8. "P8,Event Counter 8 enable bit" "Disabled,Enabled" newline bitfld.quad 0x00 7. "P7,Event Counter 7 enable bit" "Disabled,Enabled" bitfld.quad 0x00 6. "P6,Event Counter 6 enable bit" "Disabled,Enabled" bitfld.quad 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.quad 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" newline bitfld.quad 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" bitfld.quad 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.quad 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.quad SPR:0x339C2++0x00 line.quad 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register" bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.quad 0x00 30. "P30,Event Counter 30 clear bit" "Disabled,Enabled" eventfld.quad 0x00 29. "P29,Event Counter 29 clear bit" "Disabled,Enabled" eventfld.quad 0x00 28. "P28,Event Counter 28 clear bit" "Disabled,Enabled" newline eventfld.quad 0x00 27. "P27,Event Counter 27 clear bit" "Disabled,Enabled" eventfld.quad 0x00 26. "P26,Event Counter 26 clear bit" "Disabled,Enabled" eventfld.quad 0x00 25. "P25,Event Counter 25 clear bit" "Disabled,Enabled" eventfld.quad 0x00 24. "P24,Event Counter 24 clear bit" "Disabled,Enabled" newline eventfld.quad 0x00 23. "P23,Event Counter 23 clear bit" "Disabled,Enabled" eventfld.quad 0x00 22. "P22,Event Counter 22 clear bit" "Disabled,Enabled" eventfld.quad 0x00 21. "P21,Event Counter 21 clear bit" "Disabled,Enabled" eventfld.quad 0x00 20. "P20,Event Counter 20 clear bit" "Disabled,Enabled" newline eventfld.quad 0x00 19. "P19,Event Counter 19 clear bit" "Disabled,Enabled" eventfld.quad 0x00 18. "P18,Event Counter 18 clear bit" "Disabled,Enabled" eventfld.quad 0x00 17. "P17,Event Counter 17 clear bit" "Disabled,Enabled" eventfld.quad 0x00 16. "P16,Event Counter 16 clear bit" "Disabled,Enabled" newline eventfld.quad 0x00 15. "P15,Event Counter 15 clear bit" "Disabled,Enabled" eventfld.quad 0x00 14. "P14,Event Counter 14 clear bit" "Disabled,Enabled" eventfld.quad 0x00 13. "P13,Event Counter 13 clear bit" "Disabled,Enabled" eventfld.quad 0x00 12. "P12,Event Counter 12 clear bit" "Disabled,Enabled" newline eventfld.quad 0x00 11. "P11,Event Counter 11 clear bit" "Disabled,Enabled" eventfld.quad 0x00 10. "P10,Event Counter 10 clear bit" "Disabled,Enabled" eventfld.quad 0x00 9. "P9,Event Counter 9 clear bit" "Disabled,Enabled" eventfld.quad 0x00 8. "P8,Event Counter 8 clear bit" "Disabled,Enabled" newline eventfld.quad 0x00 7. "P7,Event Counter 7 clear bit" "Disabled,Enabled" eventfld.quad 0x00 6. "P6,Event Counter 6 clear bit" "Disabled,Enabled" eventfld.quad 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled" eventfld.quad 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled" newline eventfld.quad 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled" eventfld.quad 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled" eventfld.quad 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled" eventfld.quad 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled" group.quad SPR:0x339C3++0x00 line.quad 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register" bitfld.quad 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" eventfld.quad 0x00 30. "P30,Event Counter 30 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 29. "P29,Event Counter 29 clear bit" "Disabled,Enabled" eventfld.quad 0x00 28. "P28,Event Counter 28 overflow clear bit" "Disabled,Enabled" newline eventfld.quad 0x00 27. "P27,Event Counter 27 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 26. "P26,Event Counter 26 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 25. "P25,Event Counter 25 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 24. "P24,Event Counter 24 overflow clear bit" "Disabled,Enabled" newline eventfld.quad 0x00 23. "P23,Event Counter 23 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 22. "P22,Event Counter 22 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 21. "P21,Event Counter 21 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 20. "P20,Event Counter 20 overflow clear bit" "Disabled,Enabled" newline eventfld.quad 0x00 19. "P19,Event Counter 19 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 18. "P18,Event Counter 18 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 17. "P17,Event Counter 17 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 16. "P16,Event Counter 16 overflow clear bit" "Disabled,Enabled" newline eventfld.quad 0x00 15. "P15,Event Counter 15 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 14. "P14,Event Counter 14 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 13. "P13,Event Counter 13 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 12. "P12,Event Counter 12 overflow clear bit" "Disabled,Enabled" newline eventfld.quad 0x00 11. "P11,Event Counter 11 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 10. "P10,Event Counter 10 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 9. "P9,Event Counter 9 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 8. "P8,Event Counter 8 overflow clear bit" "Disabled,Enabled" newline eventfld.quad 0x00 7. "P7,Event Counter 7 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 6. "P6,Event Counter 6 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 5. "P5,Event Counter 5 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 4. "P4,Event Counter 4 overflow clear bit" "Disabled,Enabled" newline eventfld.quad 0x00 3. "P3,Event Counter 3 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 2. "P2,Event Counter 2 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 1. "P1,Event Counter 1 overflow clear bit" "Disabled,Enabled" eventfld.quad 0x00 0. "P0,Event Counter 0 overflow clear bit" "Disabled,Enabled" wgroup.quad SPR:0x339C4++0x00 line.quad 0x00 "PMSWINC_EL0,Performance Monitor Software Increment" bitfld.quad 0x00 30. "P30,Increment PMN30" "No action,Increment" bitfld.quad 0x00 29. "P29,Increment PMN29" "No action,Increment" bitfld.quad 0x00 28. "P28,Increment PMN28" "No action,Increment" bitfld.quad 0x00 27. "P27,Increment PMN27" "No action,Increment" newline bitfld.quad 0x00 26. "P26,Increment PMN26" "No action,Increment" bitfld.quad 0x00 25. "P25,Increment PMN25" "No action,Increment" bitfld.quad 0x00 24. "P24,Increment PMN24" "No action,Increment" bitfld.quad 0x00 23. "P23,Increment PMN23" "No action,Increment" newline bitfld.quad 0x00 22. "P22,Increment PMN22" "No action,Increment" bitfld.quad 0x00 21. "P21,Increment PMN21" "No action,Increment" bitfld.quad 0x00 20. "P20,Increment PMN20" "No action,Increment" bitfld.quad 0x00 19. "P19,Increment PMN19" "No action,Increment" newline bitfld.quad 0x00 18. "P18,Increment PMN18" "No action,Increment" bitfld.quad 0x00 17. "P17,Increment PMN17" "No action,Increment" bitfld.quad 0x00 16. "P16,Increment PMN16" "No action,Increment" bitfld.quad 0x00 15. "P15,Increment PMN15" "No action,Increment" newline bitfld.quad 0x00 14. "P14,Increment PMN14" "No action,Increment" bitfld.quad 0x00 13. "P13,Increment PMN13" "No action,Increment" bitfld.quad 0x00 12. "P12,Increment PMN12" "No action,Increment" bitfld.quad 0x00 11. "P11,Increment PMN11" "No action,Increment" newline bitfld.quad 0x00 10. "P10,Increment PMN10" "No action,Increment" bitfld.quad 0x00 9. "P9,Increment PMN9" "No action,Increment" bitfld.quad 0x00 8. "P8,Increment PMN8" "No action,Increment" bitfld.quad 0x00 7. "P7,Increment PMN7" "No action,Increment" newline bitfld.quad 0x00 6. "P6,Increment PMN6" "No action,Increment" bitfld.quad 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.quad 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.quad 0x00 3. "P3,Increment PMN3" "No action,Increment" newline bitfld.quad 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.quad 0x00 1. "P1,Increment PMN1" "No action,Increment" bitfld.quad 0x00 0. "P0,Increment PMN0" "No action,Increment" group.quad SPR:0x339C5++0x00 line.quad 0x00 "PMSELR_EL0,Performance Monitor Select Register" bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.open "Common Event Identification Registers" if (CORENAME()=="CORTEXA57") rgroup.quad SPR:0x339C6++0x0 line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.quad 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" bitfld.quad 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" bitfld.quad 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" newline bitfld.quad 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" bitfld.quad 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" newline bitfld.quad 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.quad 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.quad 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" newline bitfld.quad 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.quad 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.quad 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" newline bitfld.quad 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" bitfld.quad 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" newline bitfld.quad 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.quad 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.quad 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" newline bitfld.quad 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.quad 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.quad 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" newline bitfld.quad 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" bitfld.quad 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" bitfld.quad 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" newline bitfld.quad 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.quad 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" bitfld.quad 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" newline bitfld.quad 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" elif (CORENAME()=="CORTEXA53") rgroup.quad SPR:0x339C6++0x0 line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.quad 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented" bitfld.quad 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" bitfld.quad 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" newline bitfld.quad 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.quad 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" newline bitfld.quad 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" bitfld.quad 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.quad 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" newline bitfld.quad 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.quad 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.quad 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" newline bitfld.quad 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" bitfld.quad 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" newline bitfld.quad 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.quad 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" newline bitfld.quad 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.quad 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.quad 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" newline bitfld.quad 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.quad 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" bitfld.quad 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" newline bitfld.quad 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.quad 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.quad 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" newline bitfld.quad 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" bitfld.quad 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" bitfld.quad 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.quad 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" endif rgroup.quad SPR:0x339C7++0x0 line.quad 0x00 "PMCEID1_EL0,Common Event Identification Register 1" bitfld.quad 0x00 0. "EVENT32,Level 2 cache allocate" "Not implemented,Implemented" tree.end newline group.quad spr:0x339D0++0x00 line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register" group.quad SPR:0x339D1++0x00 line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register" group.quad SPR:0x339D2++0x00 line.quad 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register" group.quad SPR:0x339E0++0x00 line.quad 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register" bitfld.quad 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.quad 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled" bitfld.quad 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.quad 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.quad SPR:0x309E1++0x00 line.quad 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set" bitfld.quad 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled" bitfld.quad 0x00 30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.quad SPR:0x309E2++0x00 line.quad 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear" bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.quad 0x00 30. "P30,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 29. "P29,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 28. "P28,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.quad 0x00 27. "P27,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 26. "P26,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 25. "P25,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 24. "P24,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.quad 0x00 23. "P23,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 22. "P22,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 21. "P21,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 20. "P20,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.quad 0x00 19. "P19,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 18. "P18,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 17. "P17,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 16. "P16,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.quad 0x00 15. "P15,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 14. "P14,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 13. "P13,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 12. "P12,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.quad 0x00 11. "P11,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 10. "P10,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 9. "P9,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 8. "P8,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.quad 0x00 7. "P7,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 6. "P6,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.quad 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.quad 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled" group.quad SPR:0x339E3++0x00 line.quad 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register" group.quad SPR:(0x33E80+0x0)++0x00 line.quad 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0" group.quad SPR:(0x33EC0+0x0)++0x00 line.quad 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x1)++0x00 line.quad 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1" group.quad SPR:(0x33EC0+0x1)++0x00 line.quad 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x2)++0x00 line.quad 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2" group.quad SPR:(0x33EC0+0x2)++0x00 line.quad 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x3)++0x00 line.quad 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3" group.quad SPR:(0x33EC0+0x3)++0x00 line.quad 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x4)++0x00 line.quad 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4" group.quad SPR:(0x33EC0+0x4)++0x00 line.quad 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x5)++0x00 line.quad 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5" group.quad SPR:(0x33EC0+0x5)++0x00 line.quad 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:0x33EF7++0x00 line.quad 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.quad SPR:0x33E00++0x00 line.quad 0x00 "CNTFRQ_EL0,Counter Frequency Register" rgroup.quad spr:0x33E01++0x00 line.quad 0x00 "CNTPCT_EL0,Counter Physical Count Register" group.quad SPR:0x30E10++0x00 line.quad 0x00 "CNTKCTL_EL1,Timer PL1 Control Register" bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad SPR:0x33E20++0x00 line.quad 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue register" group.quad SPR:0x33E21++0x00 line.quad 0x00 "CNTP_CTL_EL0,Counter PL1 Physical Timer Control Register" bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad SPR:0x33E30++0x00 line.quad 0x00 "CNTV_TVAL_EL0,Counter PL1 Virtual Timer Value Register" group.quad SPR:0x33E31++0x00 line.quad 0x00 "CNTV_CTL_EL0,Counter PL1 Virtual Timer Control Register" bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E02++0x00 line.quad 0x00 "CNTVCT_EL0,Counter Virtual Count Register" group.quad spr:0x33E22++0x00 line.quad 0x00 "CNTP_CVAL_EL0,Counter PL1 Physical Compare Value Register" group.quad spr:0x33E32++0x00 line.quad 0x00 "CNTV_CVAL_EL0,Counter PL1 Virtual Compare Value Register" group.quad spr:0x34E03++0x00 line.quad 0x00 "CNTVOFF_EL2,Counter Virtual Offset Register" group.quad SPR:0x34E10++0x00 line.quad 0x00 "CNTHCTL_EL2,Counter Non-secure PL2 Control Register" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit is the trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad SPR:0x34E20++0x00 line.quad 0x00 "CNTHP_TVAL_EL2,Counter Non-secure PL2 Physical Timer Value Register" group.quad SPR:0x34E21++0x00 line.quad 0x00 "CNTHP_CTL_EL2,Counter Non-secure PL2 Physical Timer Control Register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x34E22++0x00 line.quad 0x00 "CNTHP_CVAL_EL2,Counter Non-secure PL2 Physical Compare Value Register" group.quad SPR:0x37E20++0x00 line.quad 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical SecureTimer TimerValue register" group.quad SPR:0x37E21++0x00 line.quad 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x37E22++0x00 line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch64 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.quad spr:0x30C84++0x00 line.quad 0x00 "ICC_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)" bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x30C90++0x00 line.quad 0x00 "ICC_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)" bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline if (((per.q(spr:0x30CB6))&0x10000000000)==0x00) wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.quad spr:0x30C83++0x00 line.quad 0x00 "ICC_BPR0_EL1,Interrupt Controller Binary Point Register 0" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" group.quad spr:0x30CC3++0x00 line.quad 0x00 "ICC_BPR1_EL1,Interrupt Controller Binary Point Register 1" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" group.quad spr:0x30CC4++0x00 line.quad 0x00 "ICC_CTLR_EL1,Interrupt Controller Control Register (EL1)" rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported" rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Zero,Non-zero" rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Controls whether the priority mask Register is used as a hint for interrupt distribution" "Disabled,Enabled" bitfld.quad 0x00 1. "EOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CBPR,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 interrupts" "Separate registers,Same Register" group.quad spr:0x36CC4++0x00 line.quad 0x00 "ICC_CTLR_EL3,Interrupt Controller Control Register (EL3)" rbitfld.quad 0x00 19. "ExtRange,Extended INTID range" "Not supported,Supported" rbitfld.quad 0x00 18. "RSS,Range Selector Support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported" newline rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop" bitfld.quad 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Priority drop/Deactivation,Priority drop" bitfld.quad 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Enabled,Disabled" newline bitfld.quad 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same Register" bitfld.quad 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same Register" if (((per.q(spr:0x30CC4))&0x3800)==0x00) wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" elif (((per.q(spr:0x30CC4))&0x3800)==0x800) wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" endif hgroup.quad spr:0x30C80++0x00 hide.quad 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0" in hgroup.quad spr:0x30CC0++0x00 hide.quad 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1" in newline group.quad SPR:0x30CC6++0x00 line.quad 0x00 "ICC_IGRPEN0_EL1,Interrupt Group Enable Register 0" bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad SPR:0x30CC7++0x00 line.quad 0x00 "ICC_IGRPEN1_EL1,Interrupt Group Enable Register 1 (EL1)" bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad SPR:0x36CC7++0x00 line.quad 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)" bitfld.quad 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.quad 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled" group.quad SPR:0x30460++0x00 line.quad 0x00 "ICC_PMR_EL1,Priority Mask Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.quad SPR:0x30CB3++0x00 line.quad 0x00 "ICC_RPR_EL1,Running Priority Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" if (((per.q(spr:0x30CB7))&0x10000000000)==0x00) wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated." else wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif if (((per.q(spr:0x30CB5))&0x10000000000)==0x00) wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.quad SPR:0x30CC5++0x00 line.quad 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad SPR:0x34C95++0x00 line.quad 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2" bitfld.quad 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad SPR:0x36CC5++0x00 line.quad 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3" bitfld.quad 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" tree.end tree "AArch64 Virtual Interface Control System Registers" tree.open "Hypervisor Active Priorities Registers" group.quad SPR:0x34C80++0x00 line.quad 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0" bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" if (CORENAME()=="CORTEXA53") group.quad SPR:0x34C90++0x00 line.quad 0x00 "ICH_AP1R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0" bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" endif tree.end newline rgroup.quad SPR:0x34CB3++0x00 line.quad 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register" bitfld.quad 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.quad 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.quad 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.quad SPR:0x34CB5++0x00 line.quad 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register" bitfld.quad 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.quad 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.quad 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.quad 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.quad SPR:0x34CB0++0x00 line.quad 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register" bitfld.quad 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." bitfld.quad 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.quad 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.quad 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.quad 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.quad 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" if (((d.q(spr:(0x34CC0+0x0)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((d.q(spr:(0x34CC0+0x1)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((d.q(spr:(0x34CC0+0x2)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((d.q(spr:(0x34CC0+0x3)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif rgroup.quad SPR:0x34CB2++0x00 line.quad 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register" bitfld.quad 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.quad 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.quad 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.quad 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.quad 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.quad 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.quad 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.quad 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.quad SPR:0x34CB7++0x00 line.quad 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register" hexmask.quad.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.quad 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.quad 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.quad 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.quad 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.quad 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.quad 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.quad 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.quad 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.quad SPR:0x34C94++0x00 line.quad 0x00 "ICH_VSEIR_EL2,Interrupt Controller Virtual System Error Interrupt Register" rgroup.quad SPR:0x34CB1++0x00 line.quad 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register" bitfld.quad 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.quad 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.quad 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.quad 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.quad 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.quad 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" rgroup.quad SPR:0x23010++0x00 line.quad 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register" bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" group.quad SPR:0x20020++0x00 line.quad 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable register" bitfld.quad 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled" bitfld.quad 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled" group.quad spr:0x23040++0x00 line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register" rgroup.quad SPR:0x23050++0x00 line.quad 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register" wgroup.quad SPR:0x23050++0x00 line.quad 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register" group.quad SPR:0x24070++0x00 line.quad 0x00 "DBGVCR32_EL2,Vector Catch Register" bitfld.quad 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Low,High" bitfld.quad 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Low,High" bitfld.quad 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Low,High" bitfld.quad 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Low,High" newline bitfld.quad 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Low,High" bitfld.quad 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Low,High" bitfld.quad 0x00 7. "SF,FIQ vector catch enable in Secure state" "Low,High" bitfld.quad 0x00 6. "SI,IRQ vector catch enable in Secure state" "Low,High" newline bitfld.quad 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Low,High" bitfld.quad 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Low,High" bitfld.quad 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Low,High" bitfld.quad 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Low,High" group.quad SPR:0x20002++0x00 line.quad 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register" group.quad SPR:0x20022++0x00 line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register" bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.quad 0x00 27. "RXO,Save/restore bit" "Low,High" bitfld.quad 0x00 26. "TXU,Save/restore bit" "Low,High" newline bitfld.quad 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3" bitfld.quad 0x00 21. "TDA,Save/restore bit" "Low,High" bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" bitfld.quad 0x00 14. "HDE,Save/restore bit" "Low,High" newline bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.quad 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled" bitfld.quad 0x00 6. "ERR,Save/restore bit" "Low,High" bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled" group.quad SPR:0x20032++0x00 line.quad 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register" group.quad SPR:0x20062++0x00 line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register" rgroup.quad spr:0x20100++0x00 line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register" hexmask.quad 0x00 12.--47. 0x1000 "ROMADDR,ROM base physical address" bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid" wgroup.quad SPR:0x20104++0x00 line.quad 0x00 "OSLAR_EL1,OS Lock Access Register" bitfld.quad 0x00 0. "OSLK,OS lock" "Unlock,Lock" rgroup.quad SPR:0x20114++0x00 line.quad 0x00 "OSLSR_EL1,OS Lock Status Register" bitfld.quad 0x00 2. "NTT,Not 32-bit access" "Low,High" bitfld.quad 0x00 1. "OSLK,OS lock status" "Not locked,Locked" bitfld.quad 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Impelemented,?..." group.quad SPR:0x20134++0x00 line.quad 0x00 "OSDLR_EL1,OS Double-lock Register" bitfld.quad 0x00 0. "DLK,OS double-lock control" "Not locked,Locked" group.quad SPR:0x20144++0x00 line.quad 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register" bitfld.quad 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes" group.quad SPR:0x20786++0x00 line.quad 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set" bitfld.quad 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.quad 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.quad 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set" bitfld.quad 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set" newline bitfld.quad 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.quad 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set" bitfld.quad 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.quad 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.quad SPR:0x20796++0x00 line.quad 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear" bitfld.quad 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.quad 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.quad 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" bitfld.quad 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" newline bitfld.quad 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.quad 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" bitfld.quad 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.quad 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.quad SPR:0x207E6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" group.quad SPR:0x33450++0x00 line.quad 0x00 "DSPSR_EL0,Debug Saved Processor Status Register" group.quad spr:0x33451++0x00 line.quad 0x00 "DLR_EL0,Debug Link Register" tree.end tree "Breakpoint Registers" if (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0" line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0" line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0" line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x0)++0x0 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1" line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1" line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1" line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x10)++0x0 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2" line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2" line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2" line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x20)++0x0 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3" line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3" line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3" line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x30)++0x0 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4" line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4" line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4" line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x40)++0x0 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5" line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5" line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5" line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x50)++0x0 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Watchpoint Control Registers" group.quad spr:(0x20006+0x0)++0x00 "Watchpoint 0" line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" group.quad spr:(0x20006+0x10)++0x00 "Watchpoint 1" line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" group.quad spr:(0x20006+0x20)++0x00 "Watchpoint 2" line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" group.quad spr:(0x20006+0x30)++0x00 "Watchpoint 3" line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree.end tree.open "AArch32" tree "ID Registers" rgroup.long c15:0x0000++0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code" bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8" newline hexmask.long.word 0x0 4.--15. 0x10 "PART,Primary Part Number" bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (CORENAME()=="CORTEXA57") rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." elif (CORENAME()=="CORTEXA53") rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." endif if corename()=="CORTEXA57" rgroup.long c15:0x0300++0x0 line.long 0x0 "TLBTR,TLB Type Register" endif if corename()=="CORTEXA57" rgroup.long c15:0x0500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." newline bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented" hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline bitfld.long 0x00 0.--1. "CPUID,Indicates the core number in the device" "1,2,3,4" elif corename()=="CORTEXA53" rgroup.long c15:0x0500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." newline bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,?..." hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field" endif rgroup.long c15:0x0600++0x0 line.long 0x0 "REVIDR,Revision ID Register" rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.long c15:0x0620++0x00 line.long 0x00 "ID_MMFR4,ID_MMFR4" bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented, implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5" bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." newline bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." if corename()=="CORTEXA57" rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." elif corename()=="CORTEXA53" rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." endif group.long c15:0x0310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" if corename()=="CORTEXA57" rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" newline bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" newline bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" newline bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" newline bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" newline bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" rgroup.long c15:0x7C9++0x0 line.long 0x00 "PMCEID1,Common Event Identification Register 1" elif corename()=="CORTEXA53" rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" newline bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" newline bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" newline bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" newline bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" newline bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" rgroup.long c15:0x7C9++0x0 line.long 0x00 "PMCEID1,Common Event Identification Register 1" bitfld.long 0x00 0. "EVENT32,L2D Cache Allocate" "Not implemented,Implemented" endif group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" tree.end tree "System Control and Configuration" if corename()=="CORTEXA57" if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,System Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" else group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" endif group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" newline bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled" newline bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" newline bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" newline bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes" newline bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" newline bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" newline bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" newline bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" newline bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" newline bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" newline bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" newline bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" newline bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" newline bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" newline bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" newline bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" newline bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad c15:0x110F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines" newline bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address" group.long c15:0x0101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" elif corename()=="CORTEXA53" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes" bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes" newline bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled" bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" newline bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes" bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes" newline bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes" bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes" newline bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams" bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled" newline bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled" bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes" group.quad c15:0x110F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address" group.long c15:0x0101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" endif if corename()=="CORTEXA57" group.long c15:0x0201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 28. "TRCDIS,Disable CP14 access to trace registers" "No,Yes" newline bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full" bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full" elif corename()=="CORTEXA53" group.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 only,Reserved,Full" newline bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 only,Reserved,Full" endif group.long c15:0x0011++0x0 line.long 0x00 "SCR,Secure Configuration Register" bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes" newline bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes" bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" newline bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" newline bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" newline bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure" group.long c15:0x0111++0x00 line.long 0x00 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted" group.long c15:0x0131++0x00 line.long 0x00 "SDCR,Secure Debug Control Register" bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" newline bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" newline bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" if corename()=="CORTEXA57" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" elif corename()=="CORTEXA53" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" endif rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" newline bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.long c15:0x020C++0x00 line.long 0x00 "RMR,Reset Management Register" bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64" group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" group.long c15:0x0115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" if corename()=="CORTEXA57" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Async. external,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Async. parity/on memory access,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/1st level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/1st level,Permission/1nd level,Sync. external/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..." endif elif corename()=="CORTEXA53" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX/STREX,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/section,Instruction cache maintenance,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/1st level,Permission/section,Sync. external/2nd level,Permission/2nd level,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..." endif endif if corename()=="CORTEXA57" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif elif corename()=="CORTEXA53" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif endif group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" if corename()=="CORTEXA57" rgroup.long c15:0x103F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]" hexmask.long.word 0x00 0.--11. 1. "PERIPHBASE[42:32],Periphbase[42:32]" elif corename()=="CORTEXA53" rgroup.long c15:0x103F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]" hexmask.long.byte 0x00 0.--7. 1. "PERIPHBASE[39:32],Periphbase[39:32]" endif group.long c15:0x000D++0x00 line.long 0x00 "FCSEIDR,FCSE Process ID register" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register" tree.end tree "Memory Management Unit" if corename()=="CORTEXA57" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled" if (((per.l(c15:0x0202))&0x80000000)==0x00000000) // MPIDR[31]==1 case is missing here for TTBR0 and TTBR1 group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. "IMP,Implementation" "Low,High" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTBA,Translation table base address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. "IMP,Implementation" "Low,High" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" else group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" endif if (((per.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes" newline bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes" bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7" else group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable" newline bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" newline bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes" bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected" newline bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" endif elif corename()=="CORTEXA53" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Register 0" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Register 1" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" newline bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes" bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected" newline bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" else group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long 0x00 7.--31. 0x80 "TTB0,Translation table base 0 address" bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long 0x00 7.--31. 0x80 "TTB1,Translation table base 1 address" bitfld.long 0x00 0. 6. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes" newline bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes" bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7" endif endif if corename()=="CORTEXA57" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" elif corename()=="CORTEXA53" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" group.long c15:0x0003++0x00 line.long 0x00 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" else group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" endif tree.open "Memory Attribute Indirection Registers" group.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" group.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x003A++0x00 line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" group.long c15:0x013A++0x00 line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 19. "NS1,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" bitfld.long 0x00 18. "NS0,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" newline bitfld.long 0x00 17. "DS1,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. "DS0,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" newline bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline endif tree.end newline if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" else group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier" hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier" endif tree.end tree "Virtualization Extensions" group.long c15:0x4000++0x0 line.long 0x00 "VPIDR,Virtualization Processor ID Register" group.long c15:0x4500++0x00 line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled" group.long c15:0x4101++0x00 line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" if corename()=="CORTEXA57" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" newline bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" newline bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" newline bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" newline bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" newline bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" newline bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" newline bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" newline bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3" newline bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "Not aborted,Aborted" newline bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed" newline bitfld.long 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" elif corename()=="CORTEXA53" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.long 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" newline bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" newline bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" newline bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" newline bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" newline bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3" bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" newline bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "No aborted,Aborted" bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 5. "AMO,A-bit Mask Override" "No override,Override" newline bitfld.long 0x00 4. "IMO,I-bit Mask Override" "No override,Override" bitfld.long 0x00 3. "FMO,F-bit Mask Override" "No override,Override" newline bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" newline bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" endif group.long c15:0x4411++0x00 line.long 0x00 "HCR2,Hypervisor Configuration Register 2" bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hypervisor Debug Control Register" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" newline bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register" bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 20. "TTA,Trap Trace Access" "Not trapped,?..." newline bitfld.long 0x0 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped" bitfld.long 0x0 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped" newline bitfld.long 0x0 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hypervisor System Trap Register" bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Disabled,Enabled" bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "Reserved,?..." newline hexmask.long.word 0x00 5.--13. 1. "T4_15,Trap to Hypervisor mode Non-secure priv 5 - 13" bitfld.long 0x00 0.--3. "T0_13,Trap to Hypervisor mode Non-secure priv 0 - 3," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x4711++0x00 line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register" if corename()=="CORTEXA57" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" elif corename()=="CORTEXA53" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" group.long c15:0x4212++0x00 line.long 0x00 "VTCR,Virtualization Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High" bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x4015++0x00 line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register" group.long c15:0x4115++0x00 line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Syndrome Register" group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register" group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to c15,Trapped MCRR/MRRC to c15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,Reserved,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline hexmask.long 0x00 0.--24. 1. "ISS,Instruction specific syndrome" group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register" hexmask.long 0x00 4.--31. 1. "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address" tree.open "Hypervisor Memory Attribute Indirection Registers" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" group.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" tree.end newline group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address" tree.end tree "Cache Control and Configuration" rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,PIPT" newline bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." if corename()=="CORTEXA57" rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." newline bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." elif corename()=="CORTEXA53" rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..." bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." endif rgroup.long c15:0x1700++0x0 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" newline bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" newline hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "16 bytes,32 bytes,64 bytes,128 bytes,?..." group.long c15:0x2000++0x0 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" tree "Level 1 memory system" if corename()=="CORTEXA57" group.long c15:0x001F++0x00 line.long 0x00 "DL1DATA0,Data L1 Data 0 Register" group.long c15:0x011F++0x00 line.long 0x00 "DL1DATA1,Data L1 Data 1 Register" group.long c15:0x021F++0x00 line.long 0x00 "DL1DATA2,Data L1 Data 2 Register" group.long c15:0x031F++0x00 line.long 0x00 "DL1DATA3,Data L1 Data 3 Register" group.long c15:0x000F++0x00 line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register" group.long c15:0x010F++0x00 line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register" group.long c15:0x020F++0x00 line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register" group.long c15:0x030F++0x00 line.long 0x00 "IL1DATA3,Instruction L1 Data 3 Register" wgroup.long c15:0x04F++0x00 line.long 0x00 "RAMINDEX,RAM Index Operation Register" elif corename()=="CORTEXA53" rgroup.long c15:0x300F++0x00 line.long 0x00 "CDBGDR0,Cache Debug Data Register 0" rgroup.long c15:0x310F++0x00 line.long 0x00 "CDBGDR1,Cache Debug Data Register 1" rgroup.long c15:0x320F++0x00 line.long 0x00 "CDBGDR2,Cache Debug Data Register 2" rgroup.long c15:0x330F++0x00 line.long 0x00 "CDBGDR3,Cache Debug Data Register 3" wgroup.long c15:0x302F++0x00 line.long 0x00 "CDBGDCT,Cache Debug Data Cache Tag Read Operation Register" wgroup.long c15:0x312F++0x00 line.long 0x00 "CDBGICT,Cache Debug Instruction Cache Tag Read Operation Register" wgroup.long c15:0x304F++0x00 line.long 0x00 "CDBGDCD,Cache Debug Cache Debug Data Cache Data Read Operation Register" wgroup.long c15:0x314F++0x00 line.long 0x00 "CDBGICD,Cache Debug Instruction Cache Data Read Operation Register" wgroup.long c15:0x324F++0x00 line.long 0x00 "CDBGTD,Cache Debug TLB Data Read Operation Register" endif tree.end tree "Level 2 memory system" if corename()=="CORTEXA57" group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes" bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4" newline rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Not supported,Supported" bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" newline bitfld.long 0x00 20. "DIECCE,Data in-line ECC enable" "Disabled,Enabled" rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present" newline rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present" rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1,2,Present" newline bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" newline rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle" bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" newline bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" newline bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" newline bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes" bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled" bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" newline bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" newline bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" newline bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" newline bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" newline bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" newline bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" newline bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" newline bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad c15:0x130F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" elif corename()=="CORTEXA53" group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4" bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled" newline rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle" newline rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles" group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" newline bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 30.--31. "L2VC,L2 victim Control" "0,1,2,3" bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" newline bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" group.quad c15:0x110F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address" endif tree.end tree.end tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x0 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" newline group.long c15:0x1c9++0x00 line.long 0x00 "PMNCNTENSET,Count Enable Set Register " bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 30. "P30,Event Counter 30 enable bit" "Disabled,Enabled" bitfld.long 0x00 29. "P29,Event Counter 29 enable bit" "Disabled,Enabled" bitfld.long 0x00 28. "P28,Event Counter 28 enable bit" "Disabled,Enabled" bitfld.long 0x00 27. "P27,Event Counter 27 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 26. "P26,Event Counter 26 enable bit" "Disabled,Enabled" bitfld.long 0x00 25. "P25,Event Counter 25 enable bit" "Disabled,Enabled" bitfld.long 0x00 24. "P24,Event Counter 24 enable bit" "Disabled,Enabled" bitfld.long 0x00 23. "P23,Event Counter 23 enable bit" "Disabled,Enabled" bitfld.long 0x00 22. "P22,Event Counter 22 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 21. "P21,Event Counter 21 enable bit" "Disabled,Enabled" bitfld.long 0x00 20. "P20,Event Counter 20 enable bit" "Disabled,Enabled" bitfld.long 0x00 19. "P19,Event Counter 19 enable bit" "Disabled,Enabled" bitfld.long 0x00 18. "P18,Event Counter 18 enable bit" "Disabled,Enabled" bitfld.long 0x00 17. "P17,Event Counter 17 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 16. "P16,Event Counter 16 enable bit" "Disabled,Enabled" bitfld.long 0x00 15. "P15,Event Counter 15 enable bit" "Disabled,Enabled" bitfld.long 0x00 14. "P14,Event Counter 14 enable bit" "Disabled,Enabled" bitfld.long 0x00 13. "P13,Event Counter 13 enable bit" "Disabled,Enabled" bitfld.long 0x00 12. "P12,Event Counter 12 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,Event Counter 11 enable bit" "Disabled,Enabled" bitfld.long 0x00 10. "P10,Event Counter 10 enable bit" "Disabled,Enabled" bitfld.long 0x00 9. "P9,Event Counter 9 enable bit" "Disabled,Enabled" bitfld.long 0x00 8. "P8,Event Counter 8 enable bit" "Disabled,Enabled" bitfld.long 0x00 7. "P7,Event Counter 7 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 6. "P6,Event Counter 6 enable bit" "Disabled,Enabled" bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x00 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Event Counter 30 clear bit" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Event Counter 29 clear bit " "Disabled,Enabled" eventfld.long 0x00 28. "P28,Event Counter 28 clear bit " "Disabled,Enabled" eventfld.long 0x00 27. "P27,Event Counter 27 clear bit " "Disabled,Enabled" newline eventfld.long 0x00 26. "P26,Event Counter 26 clear bit " "Disabled,Enabled" eventfld.long 0x00 25. "P25,Event Counter 25 clear bit " "Disabled,Enabled" eventfld.long 0x00 24. "P24,Event Counter 24 clear bit " "Disabled,Enabled" eventfld.long 0x00 23. "P23,Event Counter 23 clear bit " "Disabled,Enabled" eventfld.long 0x00 22. "P22,Event Counter 22 clear bit " "Disabled,Enabled" newline eventfld.long 0x00 21. "P21,Event Counter 21 clear bit " "Disabled,Enabled" eventfld.long 0x00 20. "P20,Event Counter 20 clear bit " "Disabled,Enabled" eventfld.long 0x00 19. "P19,Event Counter 19 clear bit " "Disabled,Enabled" eventfld.long 0x00 18. "P18,Event Counter 18 clear bit " "Disabled,Enabled" eventfld.long 0x00 17. "P17,Event Counter 17 clear bit " "Disabled,Enabled" newline eventfld.long 0x00 16. "P16,Event Counter 16 clear bit " "Disabled,Enabled" eventfld.long 0x00 15. "P15,Event Counter 15 clear bit" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Event Counter 14 clear bit" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Event Counter 13 clear bit" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Event Counter 12 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Event Counter 11 clear bit" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Event Counter 10 clear bit" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Event Counter 9 clear bit" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Event Counter 8 clear bit" "Disabled,Enabled" eventfld.long 0x00 7. "P7,Event Counter 7 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 6. "P6,Event Counter 6 clear bit" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled" eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register" eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" eventfld.long 0x00 30. "P30,PMN30 overflow" "No overflow,Overflow" eventfld.long 0x00 29. "P29,PMN29 overflow" "No overflow,Overflow" eventfld.long 0x00 28. "P28,PMN28 overflow" "No overflow,Overflow" eventfld.long 0x00 27. "P27,PMN27 overflow" "No overflow,Overflow" newline eventfld.long 0x00 26. "P26,PMN26 overflow" "No overflow,Overflow" eventfld.long 0x00 25. "P25,PMN25 overflow" "No overflow,Overflow" eventfld.long 0x00 24. "P24,PMN24 overflow" "No overflow,Overflow" eventfld.long 0x00 23. "P23,PMN23 overflow" "No overflow,Overflow" eventfld.long 0x00 22. "P22,PMN22 overflow" "No overflow,Overflow" newline eventfld.long 0x00 21. "P21,PMN21 overflow" "No overflow,Overflow" eventfld.long 0x00 20. "P20,PMN20 overflow" "No overflow,Overflow" eventfld.long 0x00 19. "P19,PMN19 overflow" "No overflow,Overflow" eventfld.long 0x00 18. "P18,PMN18 overflow" "No overflow,Overflow" eventfld.long 0x00 17. "P17,PMN17 overflow" "No overflow,Overflow" newline eventfld.long 0x00 16. "P16,PMN16 overflow" "No overflow,Overflow" eventfld.long 0x00 15. "P15,PMN15 overflow" "No overflow,Overflow" eventfld.long 0x00 14. "P14,PMN14 overflow" "No overflow,Overflow" eventfld.long 0x00 13. "P13,PMN13 overflow" "No overflow,Overflow" eventfld.long 0x00 12. "P12,PMN12 overflow" "No overflow,Overflow" newline eventfld.long 0x00 11. "P11,PMN11 overflow" "No overflow,Overflow" eventfld.long 0x00 10. "P10,PMN10 overflow" "No overflow,Overflow" eventfld.long 0x00 9. "P9,PMN9 overflow" "No overflow,Overflow" eventfld.long 0x00 8. "P8,PMN8 overflow" "No overflow,Overflow" eventfld.long 0x00 7. "P7,PMN7 overflow" "No overflow,Overflow" newline eventfld.long 0x00 6. "P6,PMN6 overflow" "No overflow,Overflow" eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow" eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow" eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow" newline eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x00 "PMSWINC,Performance Monitor Software Increment" bitfld.long 0x00 30. "P30,Increment PMN30" "No action,Increment" bitfld.long 0x00 29. "P29,Increment PMN29" "No action,Increment" bitfld.long 0x00 28. "P28,Increment PMN28" "No action,Increment" bitfld.long 0x00 27. "P27,Increment PMN27" "No action,Increment" bitfld.long 0x00 26. "P26,Increment PMN26" "No action,Increment" newline bitfld.long 0x00 25. "P25,Increment PMN25" "No action,Increment" bitfld.long 0x00 24. "P24,Increment PMN24" "No action,Increment" bitfld.long 0x00 23. "P23,Increment PMN23" "No action,Increment" bitfld.long 0x00 22. "P22,Increment PMN22" "No action,Increment" bitfld.long 0x00 21. "P21,Increment PMN21" "No action,Increment" newline bitfld.long 0x00 20. "P20,Increment PMN20" "No action,Increment" bitfld.long 0x00 19. "P19,Increment PMN19" "No action,Increment" bitfld.long 0x00 18. "P18,Increment PMN18" "No action,Increment" bitfld.long 0x00 17. "P17,Increment PMN17" "No action,Increment" bitfld.long 0x00 16. "P16,Increment PMN16" "No action,Increment" newline bitfld.long 0x00 15. "P15,Increment PMN15" "No action,Increment" bitfld.long 0x00 14. "P14,Increment PMN14" "No action,Increment" bitfld.long 0x00 13. "P13,Increment PMN13" "No action,Increment" bitfld.long 0x00 12. "P12,Increment PMN12" "No action,Increment" bitfld.long 0x00 11. "P11,Increment PMN11" "No action,Increment" newline bitfld.long 0x00 10. "P10,Increment PMN10" "No action,Increment" bitfld.long 0x00 9. "P9,Increment PMN9" "No action,Increment" bitfld.long 0x00 8. "P8,Increment PMN8" "No action,Increment" bitfld.long 0x00 7. "P7,Increment PMN7" "No action,Increment" bitfld.long 0x00 6. "P6,Increment PMN6" "No action,Increment" newline bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment" bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment" newline bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Monitor Select Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register" group.long c15:0x1d9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register" group.long c15:0x2d9++0x00 line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled" bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear" eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 27. "P27,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 26. "P26,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 23. "P23,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 21. "P21,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 19. "P19,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 16. "P16,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 15. "P15,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 7. "P7,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 6. "P6,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled" group.long c15:0x3e9++0x00 line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register" group.long c15:0x8E++0x00 line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0" group.long c15:(0x8E+0x40)++0x00 line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x18E++0x00 line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1" group.long c15:(0x18E+0x40)++0x00 line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x28E++0x00 line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2" group.long c15:(0x28E+0x40)++0x00 line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x38E++0x00 line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3" group.long c15:(0x38E+0x40)++0x00 line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x48E++0x00 line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4" group.long c15:(0x48E+0x40)++0x00 line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x58E++0x00 line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5" group.long c15:(0x58E+0x40)++0x00 line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x07FE++0x00 line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" rgroup.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer PL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register" group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch32 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.long c15:0x048C++0x00 line.long 0x00 "ICC_AP0R0,Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x009C++0x00 line.long 0x00 "ICC_AP1R0,Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline wgroup.quad c15:0x110C0++0x01 line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "SGIID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x038C++0x00 line.long 0x00 "ICC_BPR0,Binary Point Register 0" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x03CC++0x00 line.long 0x00 "ICC_BPR1,Binary Point Register 1" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x04CC++0x00 line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported" rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" newline bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1" group.long c15:0x64CC++0x00 line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3" rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported" newline rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled" bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled" bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled" newline bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register" bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register" if (((per.l(c15:0x4CC))&0x3800)==0x00) wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" elif (((per.l(c15:0x4CC))&0x3800)==0x800) wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" endif hgroup.long c15:0x008C++0x00 hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0" in hgroup.long c15:0x00CC++0x00 hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1" in group.long c15:0x06CC++0x00 line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x07CC++0x00 line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x0064++0x00 line.long 0x00 "ICC_PMR,Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.long c15:0x03BC++0x00 line.long 0x00 "ICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" wgroup.quad c15:0x120C0++0x01 line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" wgroup.quad c15:0x100C0++0x01 line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x05CC++0x00 line.long 0x00 "ICC_SRE,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" if corename()=="CORTEXA53" group.long c15:0x459C++0x00 line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" endif group.long c15:0x65CC++0x00 line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.long c15:0x67CC++0x00 line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable" bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled" tree.end tree "AArch32 Virtual Interface Control System Registers" tree.open "Hypervisor Active Priorities Registers" group.long c15:0x408C++0x00 line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x409C++0x00 line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline rgroup.long c15:0x43BC++0x00 line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.long c15:0x45BC++0x00 line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register" bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.long c15:0x40BC++0x00 line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" group.long c15:(0x40CC+0x0)++0x00 line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x100)++0x00 line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x200)++0x00 line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x300)++0x00 line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40EC+0x0)++0x00 line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x100)++0x00 line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x200)++0x00 line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x300)++0x00 line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" rgroup.long c15:0x42BC++0x00 line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register" bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.long c15:0x459C++0x00 line.long 0x00 "ICH_SRE,Hypervisor System Register" group.long c15:0x47BC++0x00 line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.long c15:0x449C++0x00 line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register" rgroup.long c15:0x41BC++0x00 line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" tree "Coresight Management Registers" if corename()=="CORTEXA57" rgroup.long c14:0x0000++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version" bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported" bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented" elif corename()=="CORTEXA53" rgroup.long c14:0x0000++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version" bitfld.long 0x0 15. "DEVID,Debug Device ID" "Low,High" bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported" newline bitfld.long 0x0 13. "PCSR,PC Sample register implemented" "Not implemented,Implemented" bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented" hexmask.long.byte 0x0 4.--7. 1. "VARIANT,Implementation-defined Variant Number" newline hexmask.long.byte 0x0 0.--3. 1. "REVISION,Implementation-defined Revision Number" endif rgroup.long c14:0x0060++0x0 line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register" group.long c14:0x0070++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" newline bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled" bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled" group.long c14:0x0020++0x00 line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register" bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled" group.long c14:0x0200++0x0 line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)" group.long c14:0x0220++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled" newline bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled" bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" newline bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled" bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled" newline bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." rgroup.long c14:0x0010++0x0 line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" newline bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." wgroup.long c14:0x0230++0x0 line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)" group.long c14:0x0050++0x0 line.long 0x00 "DBGDTRTXINT,Debug Transmit/Receive Register (Internal View)" group.long c14:0x0687++0x0 line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set" bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.long c14:0x0697++0x0 line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.long c14:0x06E7++0x0 line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 7. "SNDFI,Secure non-invasive debug features implementation" "No effect,Implemented" bitfld.long 0x00 6. "SNDE,Secure non-invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 5. "SIDFI,Secure invasive debug features implementation" "No effect,Implemented" newline bitfld.long 0x00 4. "SIDE,Secure invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 3. "NSNDFI,Non-secure non-invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNDE,Non-secure non-invasive debug enable" "0,1" newline bitfld.long 0x00 1. "NSIDFI,Non-secure invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 0. "NSIDE,Non-secure invasive debug enable" "0,1" rgroup.long c14:0x0707++0x0 line.long 0x0 "DBGDEVID2,Debug Device ID Register 2" rgroup.long c14:0x0717++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" "0,1,No offset,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c14:0x0727++0x00 line.long 0x00 "DBGDEVID,Debug Device ID Register 0" bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..." bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" "Not implemented,?..." bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..." newline bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..." bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented" newline bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..." tree.end newline rgroup.quad c14:0x10010++0x1 line.quad 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.quad.word 0x0 32.--47. 0x1 "ROMADDR,ROM physical address" hexmask.quad.tbyte 0x0 12.--31. 0x10 "ROMADDR,ROM physical address" bitfld.quad 0x0 1. "VALID1,ROM table address valid" "Not valid,Valid" newline bitfld.quad 0x0 0. "VALID0,ROM table address valid" "Not valid,Valid" rgroup.quad c14:0x10020++0x1 line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" wgroup.long c14:0x0401++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:0x0411++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required" bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked" bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..." if (((per.l(c14:0x0411))&0x2)==0x2) group.long c14:0x0260++0x00 line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" else hgroup.long c14:0x0260++0x00 hide.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" endif group.long c14:0x0431++0x00 line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register" bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked" group.long c14:0x0441++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Low,High" tree.end tree "Breakpoint Registers" if (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0" line.long 0x00 "DBGBVR0,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x0)++0x0 "Breakpoint 0" hide.long 0x00 "DBGBVR0,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0" line.long 0x00 "DBGBVR0,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x0)++0x0 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1" line.long 0x00 "DBGBVR1,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x10)++0x0 "Breakpoint 1" hide.long 0x00 "DBGBVR1,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1" line.long 0x00 "DBGBVR1,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x10)++0x0 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2" line.long 0x00 "DBGBVR2,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x20)++0x0 "Breakpoint 2" hide.long 0x00 "DBGBVR2,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2" line.long 0x00 "DBGBVR2,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x20)++0x0 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3" line.long 0x00 "DBGBVR3,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x30)++0x0 "Breakpoint 3" hide.long 0x00 "DBGBVR3,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3" line.long 0x00 "DBGBVR3,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x30)++0x0 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4" line.long 0x00 "DBGBVR4,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x40)++0x0 "Breakpoint 4" hide.long 0x00 "DBGBVR4,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4" line.long 0x00 "DBGBVR4,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x40)++0x0 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5" line.long 0x00 "DBGBVR5,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x50)++0x0 "Breakpoint 5" hide.long 0x00 "DBGBVR5,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5" line.long 0x00 "DBGBVR5,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x50)++0x0 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" group.long c14:0x0141++0x0 line.long 0x00 "DBGBXVR4,Debug Breakpoint Extended Value Register 4" hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value" group.long c14:0x0151++0x0 line.long 0x00 "DBGBXVR5,Debug Breakpoint Extended Value Register 5" hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value" tree.end tree "Watchpoint Control Registers" group.long c14:(0x0600+0x0)++0x00 "Breakpoint 0" line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" group.long c14:(0x0600+0x10)++0x00 "Breakpoint 1" line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" group.long c14:(0x0600+0x20)++0x00 "Breakpoint 2" line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" group.long c14:(0x0600+0x30)++0x00 "Breakpoint 3" line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree.end AUTOINDENT.OFF AUTOINDENT.POP tree.open "Interrupt Controller (GIC-500)" AUTOINDENT.PUSH AUTOINDENT.OFF base COMP.BASE("GICD",-1.) width 17. tree "Distributor Interface" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" bitfld.long 0x00 6. " DS ,Disable Security" "No,Yes" textline " " bitfld.long 0x00 5. " ARE_NS ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 4. " ARE_S ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 2. " ENABLEGRP1S ,Enable Secure Group 1 interrupts" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ENABLEGRP1NS ,Enable Secure Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" bitfld.long 0x00 4. " ARE_NS ,Affinity Routing Enable" "Reserved,Enabled" textline " " bitfld.long 0x00 1. " ENABLEGRP1A ,Enable Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" rbitfld.long 0x00 6. " DS ,Disable Security" "Reserved,Yes" textline " " bitfld.long 0x00 4. " ARE ,Affinity Routing Enable" "Reserved,Enabled" bitfld.long 0x00 1. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled" endif rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 25. " NO1N ,Indicates whether 1 of N SPI interrupts are supported" "Supported,Not supported" bitfld.long 0x00 24. " A3V ,Indicates whether the Distributor supports nonzero values of Affinity level 3" "Not supported,Supported" bitfld.long 0x00 19.--23. " IDBITS ,The number of interrupt identifier bits supported" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." textline " " bitfld.long 0x00 17. " LPIS ,Indicates whether the implementation supports LPIs" "Not supported,Supported" bitfld.long 0x00 16. " MBIS ,Indicates whether the implementation supports message-based interrupts by writing to Distributor registers" "Not supported,Supported" bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Reports the number of PEs that can be used when affinity routing is not enabled" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0.--4. " ITLN ,Indicates the maximum SPI INTID that the GIC implementation supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Reserved" rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x10000)==0x10000) wgroup.long 0x40++0x03 line.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" wgroup.long 0x48++0x03 line.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x50)) wgroup.long 0x50++0x03 line.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x50++0x03 hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Non-secure access)" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x58)) wgroup.long 0x58++0x03 line.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x58++0x03 hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Non-secure access)" endif else hgroup.long 0x40++0x03 hide.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register" hgroup.long 0x48++0x03 hide.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register" hgroup.long 0x50++0x03 hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register" hgroup.long 0x58++0x03 hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register" endif width 17. tree "Group Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0080)) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" else hgroup.long 0x0080++0x03 hide.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x84))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 (Secure Access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else hgroup.long 0x0084++0x03 hide.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x88))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 (Secure Access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else hgroup.long 0x0088++0x03 hide.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x8C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 (Secure Access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else hgroup.long 0x008C++0x03 hide.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x90))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 (Secure Access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else hgroup.long 0x0090++0x03 hide.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x94))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 (Secure Access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else hgroup.long 0x0094++0x03 hide.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x98))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 (Secure Access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else hgroup.long 0x0098++0x03 hide.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x9C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 (Secure Access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else hgroup.long 0x009C++0x03 hide.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 (Secure Access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else hgroup.long 0x00A0++0x03 hide.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 (Secure Access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else hgroup.long 0x00A4++0x03 hide.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure Access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else hgroup.long 0x00A8++0x03 hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xAC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure Access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else hgroup.long 0x00AC++0x03 hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure Access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else hgroup.long 0x00B0++0x03 hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure Access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else hgroup.long 0x00B4++0x03 hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure Access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else hgroup.long 0x00B8++0x03 hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xBC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure Access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else hgroup.long 0x00BC++0x03 hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure Access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else hgroup.long 0x00C0++0x03 hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure Access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else hgroup.long 0x00C4++0x03 hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure Access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else hgroup.long 0x00C8++0x03 hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xCC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure Access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else hgroup.long 0x00CC++0x03 hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure Access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else hgroup.long 0x00D0++0x03 hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure Access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else hgroup.long 0x00D4++0x03 hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure Access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else hgroup.long 0x00D8++0x03 hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xDC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure Access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else hgroup.long 0x00DC++0x03 hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure Access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else hgroup.long 0x00E0++0x03 hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure Access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else hgroup.long 0x00E4++0x03 hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure Access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else hgroup.long 0x00E8++0x03 hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure Access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else hgroup.long 0x00EC++0x03 hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure Access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else hgroup.long 0x00F0++0x03 hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure Access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else hgroup.long 0x00F4++0x03 hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure Access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else hgroup.long 0x00F8++0x03 hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" endif tree.end width 24. tree "Set/Clear Enable Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0100++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else hgroup.long 0x0104++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else hgroup.long 0x0108++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else hgroup.long 0x010C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else hgroup.long 0x0110++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else hgroup.long 0x0114++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else hgroup.long 0x0118++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else hgroup.long 0x011C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else hgroup.long 0x0120++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else hgroup.long 0x0124++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else hgroup.long 0x0128++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else hgroup.long 0x012C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else hgroup.long 0x0130++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else hgroup.long 0x0134++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else hgroup.long 0x0138++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else hgroup.long 0x013C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else hgroup.long 0x0140++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else hgroup.long 0x0144++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else hgroup.long 0x0148++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else hgroup.long 0x014C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else hgroup.long 0x0150++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else hgroup.long 0x0154++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else hgroup.long 0x0158++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else hgroup.long 0x015C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else hgroup.long 0x0160++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else hgroup.long 0x0164++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else hgroup.long 0x0168++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else hgroup.long 0x016C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else hgroup.long 0x0170++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else hgroup.long 0x0174++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else hgroup.long 0x0178++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" endif tree.end width 22. tree "Set/Clear Pending Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0200++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Not pending,Pending" else hgroup.long 0x0204++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Not pending,Pending" else hgroup.long 0x0208++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Not pending,Pending" else hgroup.long 0x020C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Not pending,Pending" else hgroup.long 0x0210++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Not pending,Pending" else hgroup.long 0x0214++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Not pending,Pending" else hgroup.long 0x0218++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Not pending,Pending" else hgroup.long 0x021C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Not pending,Pending" else hgroup.long 0x0220++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Not pending,Pending" else hgroup.long 0x0224++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Not pending,Pending" else hgroup.long 0x0228++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Not pending,Pending" else hgroup.long 0x022C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Not pending,Pending" else hgroup.long 0x0230++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Not pending,Pending" else hgroup.long 0x0234++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Not pending,Pending" else hgroup.long 0x0238++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Not pending,Pending" else hgroup.long 0x023C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Not pending,Pending" else hgroup.long 0x0240++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Not pending,Pending" else hgroup.long 0x0244++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Not pending,Pending" else hgroup.long 0x0248++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Not pending,Pending" else hgroup.long 0x024C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Not pending,Pending" else hgroup.long 0x0250++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Not pending,Pending" else hgroup.long 0x0254++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Not pending,Pending" else hgroup.long 0x0258++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Not pending,Pending" else hgroup.long 0x025C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Not pending,Pending" else hgroup.long 0x0260++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Not pending,Pending" else hgroup.long 0x0264++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Not pending,Pending" else hgroup.long 0x0268++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Not pending,Pending" else hgroup.long 0x026C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Not pending,Pending" else hgroup.long 0x0270++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Not pending,Pending" else hgroup.long 0x0274++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Not pending,Pending" else hgroup.long 0x0278++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" endif tree.end width 24. tree "Set/Clear Active Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0300++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0300++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active" else hgroup.long 0x0304++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active" else hgroup.long 0x0308++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active" else hgroup.long 0x030C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active" else hgroup.long 0x0310++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active" else hgroup.long 0x0314++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active" else hgroup.long 0x0318++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active" else hgroup.long 0x031C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active" else hgroup.long 0x0320++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active" else hgroup.long 0x0324++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active" else hgroup.long 0x0328++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active" else hgroup.long 0x032C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active" else hgroup.long 0x0330++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active" else hgroup.long 0x0334++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active" else hgroup.long 0x0338++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active" else hgroup.long 0x033C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE543 ,Set/Clear Active Bit 543" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE542 ,Set/Clear Active Bit 542" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE541 ,Set/Clear Active Bit 541" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE540 ,Set/Clear Active Bit 540" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE539 ,Set/Clear Active Bit 539" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE538 ,Set/Clear Active Bit 538" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE537 ,Set/Clear Active Bit 537" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE536 ,Set/Clear Active Bit 536" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE535 ,Set/Clear Active Bit 535" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE534 ,Set/Clear Active Bit 534" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE533 ,Set/Clear Active Bit 533" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE532 ,Set/Clear Active Bit 532" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE531 ,Set/Clear Active Bit 531" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE530 ,Set/Clear Active Bit 530" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE529 ,Set/Clear Active Bit 529" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE528 ,Set/Clear Active Bit 528" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE527 ,Set/Clear Active Bit 527" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE526 ,Set/Clear Active Bit 526" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE525 ,Set/Clear Active Bit 525" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE524 ,Set/Clear Active Bit 524" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE523 ,Set/Clear Active Bit 523" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE522 ,Set/Clear Active Bit 522" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE521 ,Set/Clear Active Bit 521" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE520 ,Set/Clear Active Bit 520" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE519 ,Set/Clear Active Bit 519" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE518 ,Set/Clear Active Bit 518" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE517 ,Set/Clear Active Bit 517" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE516 ,Set/Clear Active Bit 516" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE515 ,Set/Clear Active Bit 515" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE514 ,Set/Clear Active Bit 514" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE513 ,Set/Clear Active Bit 513" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE512 ,Set/Clear Active Bit 512" "Not active,Active" else hgroup.long 0x0340++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE575 ,Set/Clear Active Bit 575" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE574 ,Set/Clear Active Bit 574" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE573 ,Set/Clear Active Bit 573" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE572 ,Set/Clear Active Bit 572" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE571 ,Set/Clear Active Bit 571" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE570 ,Set/Clear Active Bit 570" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE569 ,Set/Clear Active Bit 569" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE568 ,Set/Clear Active Bit 568" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE567 ,Set/Clear Active Bit 567" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE566 ,Set/Clear Active Bit 566" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE565 ,Set/Clear Active Bit 565" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE564 ,Set/Clear Active Bit 564" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE563 ,Set/Clear Active Bit 563" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE562 ,Set/Clear Active Bit 562" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE561 ,Set/Clear Active Bit 561" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE560 ,Set/Clear Active Bit 560" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE559 ,Set/Clear Active Bit 559" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE558 ,Set/Clear Active Bit 558" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE557 ,Set/Clear Active Bit 557" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE556 ,Set/Clear Active Bit 556" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE555 ,Set/Clear Active Bit 555" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE554 ,Set/Clear Active Bit 554" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE553 ,Set/Clear Active Bit 553" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE552 ,Set/Clear Active Bit 552" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE551 ,Set/Clear Active Bit 551" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE550 ,Set/Clear Active Bit 550" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE549 ,Set/Clear Active Bit 549" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE548 ,Set/Clear Active Bit 548" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE547 ,Set/Clear Active Bit 547" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE546 ,Set/Clear Active Bit 546" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE545 ,Set/Clear Active Bit 545" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE544 ,Set/Clear Active Bit 544" "Not active,Active" else hgroup.long 0x0344++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE607 ,Set/Clear Active Bit 607" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE606 ,Set/Clear Active Bit 606" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE605 ,Set/Clear Active Bit 605" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE604 ,Set/Clear Active Bit 604" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE603 ,Set/Clear Active Bit 603" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE602 ,Set/Clear Active Bit 602" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE601 ,Set/Clear Active Bit 601" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE600 ,Set/Clear Active Bit 600" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE599 ,Set/Clear Active Bit 599" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE598 ,Set/Clear Active Bit 598" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE597 ,Set/Clear Active Bit 597" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE596 ,Set/Clear Active Bit 596" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE595 ,Set/Clear Active Bit 595" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE594 ,Set/Clear Active Bit 594" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE593 ,Set/Clear Active Bit 593" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE592 ,Set/Clear Active Bit 592" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE591 ,Set/Clear Active Bit 591" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE590 ,Set/Clear Active Bit 590" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE589 ,Set/Clear Active Bit 589" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE588 ,Set/Clear Active Bit 588" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE587 ,Set/Clear Active Bit 587" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE586 ,Set/Clear Active Bit 586" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE585 ,Set/Clear Active Bit 585" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE584 ,Set/Clear Active Bit 584" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE583 ,Set/Clear Active Bit 583" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE582 ,Set/Clear Active Bit 582" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE581 ,Set/Clear Active Bit 581" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE580 ,Set/Clear Active Bit 580" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE579 ,Set/Clear Active Bit 579" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE578 ,Set/Clear Active Bit 578" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE577 ,Set/Clear Active Bit 577" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE576 ,Set/Clear Active Bit 576" "Not active,Active" else hgroup.long 0x0348++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE639 ,Set/Clear Active Bit 639" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE638 ,Set/Clear Active Bit 638" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE637 ,Set/Clear Active Bit 637" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE636 ,Set/Clear Active Bit 636" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE635 ,Set/Clear Active Bit 635" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE634 ,Set/Clear Active Bit 634" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE633 ,Set/Clear Active Bit 633" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE632 ,Set/Clear Active Bit 632" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE631 ,Set/Clear Active Bit 631" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE630 ,Set/Clear Active Bit 630" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE629 ,Set/Clear Active Bit 629" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE628 ,Set/Clear Active Bit 628" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE627 ,Set/Clear Active Bit 627" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE626 ,Set/Clear Active Bit 626" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE625 ,Set/Clear Active Bit 625" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE624 ,Set/Clear Active Bit 624" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE623 ,Set/Clear Active Bit 623" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE622 ,Set/Clear Active Bit 622" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE621 ,Set/Clear Active Bit 621" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE620 ,Set/Clear Active Bit 620" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE619 ,Set/Clear Active Bit 619" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE618 ,Set/Clear Active Bit 618" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE617 ,Set/Clear Active Bit 617" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE616 ,Set/Clear Active Bit 616" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE615 ,Set/Clear Active Bit 615" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE614 ,Set/Clear Active Bit 614" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE613 ,Set/Clear Active Bit 613" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE612 ,Set/Clear Active Bit 612" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE611 ,Set/Clear Active Bit 611" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE610 ,Set/Clear Active Bit 610" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE609 ,Set/Clear Active Bit 609" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE608 ,Set/Clear Active Bit 608" "Not active,Active" else hgroup.long 0x034C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE671 ,Set/Clear Active Bit 671" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE670 ,Set/Clear Active Bit 670" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE669 ,Set/Clear Active Bit 669" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE668 ,Set/Clear Active Bit 668" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE667 ,Set/Clear Active Bit 667" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE666 ,Set/Clear Active Bit 666" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE665 ,Set/Clear Active Bit 665" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE664 ,Set/Clear Active Bit 664" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE663 ,Set/Clear Active Bit 663" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE662 ,Set/Clear Active Bit 662" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE661 ,Set/Clear Active Bit 661" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE660 ,Set/Clear Active Bit 660" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE659 ,Set/Clear Active Bit 659" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE658 ,Set/Clear Active Bit 658" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE657 ,Set/Clear Active Bit 657" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE656 ,Set/Clear Active Bit 656" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE655 ,Set/Clear Active Bit 655" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE654 ,Set/Clear Active Bit 654" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE653 ,Set/Clear Active Bit 653" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE652 ,Set/Clear Active Bit 652" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE651 ,Set/Clear Active Bit 651" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE650 ,Set/Clear Active Bit 650" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE649 ,Set/Clear Active Bit 649" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE648 ,Set/Clear Active Bit 648" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE647 ,Set/Clear Active Bit 647" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE646 ,Set/Clear Active Bit 646" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE645 ,Set/Clear Active Bit 645" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE644 ,Set/Clear Active Bit 644" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE643 ,Set/Clear Active Bit 643" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE642 ,Set/Clear Active Bit 642" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE641 ,Set/Clear Active Bit 641" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE640 ,Set/Clear Active Bit 640" "Not active,Active" else hgroup.long 0x0350++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE703 ,Set/Clear Active Bit 703" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE702 ,Set/Clear Active Bit 702" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE701 ,Set/Clear Active Bit 701" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE700 ,Set/Clear Active Bit 700" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE699 ,Set/Clear Active Bit 699" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE698 ,Set/Clear Active Bit 698" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE697 ,Set/Clear Active Bit 697" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE696 ,Set/Clear Active Bit 696" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE695 ,Set/Clear Active Bit 695" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE694 ,Set/Clear Active Bit 694" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE693 ,Set/Clear Active Bit 693" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE692 ,Set/Clear Active Bit 692" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE691 ,Set/Clear Active Bit 691" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE690 ,Set/Clear Active Bit 690" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE689 ,Set/Clear Active Bit 689" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE688 ,Set/Clear Active Bit 688" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE687 ,Set/Clear Active Bit 687" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE686 ,Set/Clear Active Bit 686" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE685 ,Set/Clear Active Bit 685" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE684 ,Set/Clear Active Bit 684" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE683 ,Set/Clear Active Bit 683" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE682 ,Set/Clear Active Bit 682" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE681 ,Set/Clear Active Bit 681" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE680 ,Set/Clear Active Bit 680" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE679 ,Set/Clear Active Bit 679" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE678 ,Set/Clear Active Bit 678" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE677 ,Set/Clear Active Bit 677" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE676 ,Set/Clear Active Bit 676" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE675 ,Set/Clear Active Bit 675" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE674 ,Set/Clear Active Bit 674" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE673 ,Set/Clear Active Bit 673" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE672 ,Set/Clear Active Bit 672" "Not active,Active" else hgroup.long 0x0354++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE735 ,Set/Clear Active Bit 735" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE734 ,Set/Clear Active Bit 734" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE733 ,Set/Clear Active Bit 733" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE732 ,Set/Clear Active Bit 732" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE731 ,Set/Clear Active Bit 731" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE730 ,Set/Clear Active Bit 730" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE729 ,Set/Clear Active Bit 729" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE728 ,Set/Clear Active Bit 728" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE727 ,Set/Clear Active Bit 727" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE726 ,Set/Clear Active Bit 726" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE725 ,Set/Clear Active Bit 725" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE724 ,Set/Clear Active Bit 724" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE723 ,Set/Clear Active Bit 723" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE722 ,Set/Clear Active Bit 722" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE721 ,Set/Clear Active Bit 721" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE720 ,Set/Clear Active Bit 720" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE719 ,Set/Clear Active Bit 719" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE718 ,Set/Clear Active Bit 718" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE717 ,Set/Clear Active Bit 717" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE716 ,Set/Clear Active Bit 716" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE715 ,Set/Clear Active Bit 715" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE714 ,Set/Clear Active Bit 714" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE713 ,Set/Clear Active Bit 713" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE712 ,Set/Clear Active Bit 712" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE711 ,Set/Clear Active Bit 711" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE710 ,Set/Clear Active Bit 710" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE709 ,Set/Clear Active Bit 709" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE708 ,Set/Clear Active Bit 708" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE707 ,Set/Clear Active Bit 707" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE706 ,Set/Clear Active Bit 706" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE705 ,Set/Clear Active Bit 705" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE704 ,Set/Clear Active Bit 704" "Not active,Active" else hgroup.long 0x0358++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE767 ,Set/Clear Active Bit 767" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE766 ,Set/Clear Active Bit 766" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE765 ,Set/Clear Active Bit 765" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE764 ,Set/Clear Active Bit 764" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE763 ,Set/Clear Active Bit 763" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE762 ,Set/Clear Active Bit 762" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE761 ,Set/Clear Active Bit 761" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE760 ,Set/Clear Active Bit 760" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE759 ,Set/Clear Active Bit 759" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE758 ,Set/Clear Active Bit 758" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE757 ,Set/Clear Active Bit 757" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE756 ,Set/Clear Active Bit 756" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE755 ,Set/Clear Active Bit 755" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE754 ,Set/Clear Active Bit 754" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE753 ,Set/Clear Active Bit 753" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE752 ,Set/Clear Active Bit 752" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE751 ,Set/Clear Active Bit 751" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE750 ,Set/Clear Active Bit 750" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE749 ,Set/Clear Active Bit 749" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE748 ,Set/Clear Active Bit 748" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE747 ,Set/Clear Active Bit 747" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE746 ,Set/Clear Active Bit 746" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE745 ,Set/Clear Active Bit 745" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE744 ,Set/Clear Active Bit 744" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE743 ,Set/Clear Active Bit 743" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE742 ,Set/Clear Active Bit 742" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE741 ,Set/Clear Active Bit 741" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE740 ,Set/Clear Active Bit 740" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE739 ,Set/Clear Active Bit 739" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE738 ,Set/Clear Active Bit 738" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE737 ,Set/Clear Active Bit 737" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE736 ,Set/Clear Active Bit 736" "Not active,Active" else hgroup.long 0x035C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE799 ,Set/Clear Active Bit 799" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE798 ,Set/Clear Active Bit 798" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE797 ,Set/Clear Active Bit 797" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE796 ,Set/Clear Active Bit 796" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE795 ,Set/Clear Active Bit 795" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE794 ,Set/Clear Active Bit 794" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE793 ,Set/Clear Active Bit 793" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE792 ,Set/Clear Active Bit 792" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE791 ,Set/Clear Active Bit 791" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE790 ,Set/Clear Active Bit 790" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE789 ,Set/Clear Active Bit 789" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE788 ,Set/Clear Active Bit 788" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE787 ,Set/Clear Active Bit 787" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE786 ,Set/Clear Active Bit 786" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE785 ,Set/Clear Active Bit 785" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE784 ,Set/Clear Active Bit 784" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE783 ,Set/Clear Active Bit 783" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE782 ,Set/Clear Active Bit 782" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE781 ,Set/Clear Active Bit 781" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE780 ,Set/Clear Active Bit 780" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE779 ,Set/Clear Active Bit 779" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE778 ,Set/Clear Active Bit 778" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE777 ,Set/Clear Active Bit 777" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE776 ,Set/Clear Active Bit 776" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE775 ,Set/Clear Active Bit 775" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE774 ,Set/Clear Active Bit 774" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE773 ,Set/Clear Active Bit 773" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE772 ,Set/Clear Active Bit 772" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE771 ,Set/Clear Active Bit 771" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE770 ,Set/Clear Active Bit 770" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE769 ,Set/Clear Active Bit 769" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE768 ,Set/Clear Active Bit 768" "Not active,Active" else hgroup.long 0x0360++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE831 ,Set/Clear Active Bit 831" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE830 ,Set/Clear Active Bit 830" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE829 ,Set/Clear Active Bit 829" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE828 ,Set/Clear Active Bit 828" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE827 ,Set/Clear Active Bit 827" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE826 ,Set/Clear Active Bit 826" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE825 ,Set/Clear Active Bit 825" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE824 ,Set/Clear Active Bit 824" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE823 ,Set/Clear Active Bit 823" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE822 ,Set/Clear Active Bit 822" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE821 ,Set/Clear Active Bit 821" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE820 ,Set/Clear Active Bit 820" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE819 ,Set/Clear Active Bit 819" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE818 ,Set/Clear Active Bit 818" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE817 ,Set/Clear Active Bit 817" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE816 ,Set/Clear Active Bit 816" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE815 ,Set/Clear Active Bit 815" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE814 ,Set/Clear Active Bit 814" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE813 ,Set/Clear Active Bit 813" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE812 ,Set/Clear Active Bit 812" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE811 ,Set/Clear Active Bit 811" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE810 ,Set/Clear Active Bit 810" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE809 ,Set/Clear Active Bit 809" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE808 ,Set/Clear Active Bit 808" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE807 ,Set/Clear Active Bit 807" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE806 ,Set/Clear Active Bit 806" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE805 ,Set/Clear Active Bit 805" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE804 ,Set/Clear Active Bit 804" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE803 ,Set/Clear Active Bit 803" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE802 ,Set/Clear Active Bit 802" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE801 ,Set/Clear Active Bit 801" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE800 ,Set/Clear Active Bit 800" "Not active,Active" else hgroup.long 0x0364++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE863 ,Set/Clear Active Bit 863" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE862 ,Set/Clear Active Bit 862" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE861 ,Set/Clear Active Bit 861" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE860 ,Set/Clear Active Bit 860" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE859 ,Set/Clear Active Bit 859" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE858 ,Set/Clear Active Bit 858" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE857 ,Set/Clear Active Bit 857" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE856 ,Set/Clear Active Bit 856" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE855 ,Set/Clear Active Bit 855" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE854 ,Set/Clear Active Bit 854" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE853 ,Set/Clear Active Bit 853" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE852 ,Set/Clear Active Bit 852" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE851 ,Set/Clear Active Bit 851" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE850 ,Set/Clear Active Bit 850" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE849 ,Set/Clear Active Bit 849" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE848 ,Set/Clear Active Bit 848" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE847 ,Set/Clear Active Bit 847" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE846 ,Set/Clear Active Bit 846" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE845 ,Set/Clear Active Bit 845" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE844 ,Set/Clear Active Bit 844" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE843 ,Set/Clear Active Bit 843" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE842 ,Set/Clear Active Bit 842" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE841 ,Set/Clear Active Bit 841" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE840 ,Set/Clear Active Bit 840" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE839 ,Set/Clear Active Bit 839" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE838 ,Set/Clear Active Bit 838" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE837 ,Set/Clear Active Bit 837" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE836 ,Set/Clear Active Bit 836" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE835 ,Set/Clear Active Bit 835" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE834 ,Set/Clear Active Bit 834" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE833 ,Set/Clear Active Bit 833" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE832 ,Set/Clear Active Bit 832" "Not active,Active" else hgroup.long 0x0368++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE895 ,Set/Clear Active Bit 895" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE894 ,Set/Clear Active Bit 894" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE893 ,Set/Clear Active Bit 893" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE892 ,Set/Clear Active Bit 892" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE891 ,Set/Clear Active Bit 891" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE890 ,Set/Clear Active Bit 890" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE889 ,Set/Clear Active Bit 889" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE888 ,Set/Clear Active Bit 888" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE887 ,Set/Clear Active Bit 887" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE886 ,Set/Clear Active Bit 886" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE885 ,Set/Clear Active Bit 885" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE884 ,Set/Clear Active Bit 884" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE883 ,Set/Clear Active Bit 883" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE882 ,Set/Clear Active Bit 882" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE881 ,Set/Clear Active Bit 881" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE880 ,Set/Clear Active Bit 880" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE879 ,Set/Clear Active Bit 879" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE878 ,Set/Clear Active Bit 878" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE877 ,Set/Clear Active Bit 877" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE876 ,Set/Clear Active Bit 876" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE875 ,Set/Clear Active Bit 875" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE874 ,Set/Clear Active Bit 874" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE873 ,Set/Clear Active Bit 873" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE872 ,Set/Clear Active Bit 872" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE871 ,Set/Clear Active Bit 871" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE870 ,Set/Clear Active Bit 870" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE869 ,Set/Clear Active Bit 869" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE868 ,Set/Clear Active Bit 868" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE867 ,Set/Clear Active Bit 867" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE866 ,Set/Clear Active Bit 866" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE865 ,Set/Clear Active Bit 865" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE864 ,Set/Clear Active Bit 864" "Not active,Active" else hgroup.long 0x036C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE927 ,Set/Clear Active Bit 927" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE926 ,Set/Clear Active Bit 926" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE925 ,Set/Clear Active Bit 925" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE924 ,Set/Clear Active Bit 924" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE923 ,Set/Clear Active Bit 923" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE922 ,Set/Clear Active Bit 922" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE921 ,Set/Clear Active Bit 921" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE920 ,Set/Clear Active Bit 920" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE919 ,Set/Clear Active Bit 919" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE918 ,Set/Clear Active Bit 918" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE917 ,Set/Clear Active Bit 917" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE916 ,Set/Clear Active Bit 916" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE915 ,Set/Clear Active Bit 915" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE914 ,Set/Clear Active Bit 914" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE913 ,Set/Clear Active Bit 913" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE912 ,Set/Clear Active Bit 912" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE911 ,Set/Clear Active Bit 911" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE910 ,Set/Clear Active Bit 910" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE909 ,Set/Clear Active Bit 909" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE908 ,Set/Clear Active Bit 908" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE907 ,Set/Clear Active Bit 907" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE906 ,Set/Clear Active Bit 906" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE905 ,Set/Clear Active Bit 905" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE904 ,Set/Clear Active Bit 904" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE903 ,Set/Clear Active Bit 903" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE902 ,Set/Clear Active Bit 902" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE901 ,Set/Clear Active Bit 901" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE900 ,Set/Clear Active Bit 900" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE899 ,Set/Clear Active Bit 899" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE898 ,Set/Clear Active Bit 898" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE897 ,Set/Clear Active Bit 897" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE896 ,Set/Clear Active Bit 896" "Not active,Active" else hgroup.long 0x0370++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE959 ,Set/Clear Active Bit 959" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE958 ,Set/Clear Active Bit 958" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE957 ,Set/Clear Active Bit 957" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE956 ,Set/Clear Active Bit 956" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE955 ,Set/Clear Active Bit 955" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE954 ,Set/Clear Active Bit 954" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE953 ,Set/Clear Active Bit 953" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE952 ,Set/Clear Active Bit 952" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE951 ,Set/Clear Active Bit 951" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE950 ,Set/Clear Active Bit 950" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE949 ,Set/Clear Active Bit 949" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE948 ,Set/Clear Active Bit 948" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE947 ,Set/Clear Active Bit 947" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE946 ,Set/Clear Active Bit 946" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE945 ,Set/Clear Active Bit 945" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE944 ,Set/Clear Active Bit 944" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE943 ,Set/Clear Active Bit 943" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE942 ,Set/Clear Active Bit 942" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE941 ,Set/Clear Active Bit 941" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE940 ,Set/Clear Active Bit 940" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE939 ,Set/Clear Active Bit 939" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE938 ,Set/Clear Active Bit 938" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE937 ,Set/Clear Active Bit 937" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE936 ,Set/Clear Active Bit 936" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE935 ,Set/Clear Active Bit 935" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE934 ,Set/Clear Active Bit 934" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE933 ,Set/Clear Active Bit 933" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE932 ,Set/Clear Active Bit 932" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE931 ,Set/Clear Active Bit 931" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE930 ,Set/Clear Active Bit 930" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE929 ,Set/Clear Active Bit 929" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE928 ,Set/Clear Active Bit 928" "Not active,Active" else hgroup.long 0x0374++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE991 ,Set/Clear Active Bit 991" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE990 ,Set/Clear Active Bit 990" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE989 ,Set/Clear Active Bit 989" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE988 ,Set/Clear Active Bit 988" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE987 ,Set/Clear Active Bit 987" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE986 ,Set/Clear Active Bit 986" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE985 ,Set/Clear Active Bit 985" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE984 ,Set/Clear Active Bit 984" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE983 ,Set/Clear Active Bit 983" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE982 ,Set/Clear Active Bit 982" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE981 ,Set/Clear Active Bit 981" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE980 ,Set/Clear Active Bit 980" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE979 ,Set/Clear Active Bit 979" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE978 ,Set/Clear Active Bit 978" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE977 ,Set/Clear Active Bit 977" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE976 ,Set/Clear Active Bit 976" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE975 ,Set/Clear Active Bit 975" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE974 ,Set/Clear Active Bit 974" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE973 ,Set/Clear Active Bit 973" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE972 ,Set/Clear Active Bit 972" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE971 ,Set/Clear Active Bit 971" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE970 ,Set/Clear Active Bit 970" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE969 ,Set/Clear Active Bit 969" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE968 ,Set/Clear Active Bit 968" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE967 ,Set/Clear Active Bit 967" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE966 ,Set/Clear Active Bit 966" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE965 ,Set/Clear Active Bit 965" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE964 ,Set/Clear Active Bit 964" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE963 ,Set/Clear Active Bit 963" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE962 ,Set/Clear Active Bit 962" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE961 ,Set/Clear Active Bit 961" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE960 ,Set/Clear Active Bit 960" "Not active,Active" else hgroup.long 0x0378++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" endif tree.end width 20. tree "Priority Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x400++0x03 hide.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hgroup.long 0x404++0x03 hide.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hgroup.long 0x408++0x03 hide.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hgroup.long 0x40C++0x03 hide.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hgroup.long 0x410++0x03 hide.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hgroup.long 0x414++0x03 hide.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hgroup.long 0x418++0x03 hide.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hgroup.long 0x41C++0x03 hide.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" else group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else hgroup.long 0x420++0x03 hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hgroup.long 0x424++0x03 hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hgroup.long 0x428++0x03 hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hgroup.long 0x42C++0x03 hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hgroup.long 0x430++0x03 hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hgroup.long 0x434++0x03 hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hgroup.long 0x438++0x03 hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hgroup.long 0x43C++0x03 hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else hgroup.long 0x440++0x03 hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hgroup.long 0x444++0x03 hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hgroup.long 0x448++0x03 hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hgroup.long 0x44C++0x03 hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hgroup.long 0x450++0x03 hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hgroup.long 0x454++0x03 hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hgroup.long 0x458++0x03 hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hgroup.long 0x45C++0x03 hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else hgroup.long 0x460++0x03 hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hgroup.long 0x464++0x03 hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hgroup.long 0x468++0x03 hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hgroup.long 0x46C++0x03 hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hgroup.long 0x470++0x03 hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hgroup.long 0x474++0x03 hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hgroup.long 0x478++0x03 hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hgroup.long 0x47C++0x03 hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else hgroup.long 0x480++0x03 hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hgroup.long 0x484++0x03 hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hgroup.long 0x488++0x03 hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hgroup.long 0x48C++0x03 hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hgroup.long 0x490++0x03 hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hgroup.long 0x494++0x03 hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hgroup.long 0x498++0x03 hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hgroup.long 0x49C++0x03 hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else hgroup.long 0x4A0++0x03 hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hgroup.long 0x4A4++0x03 hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hgroup.long 0x4A8++0x03 hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hgroup.long 0x4AC++0x03 hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hgroup.long 0x4B0++0x03 hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hgroup.long 0x4B4++0x03 hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hgroup.long 0x4B8++0x03 hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hgroup.long 0x4BC++0x03 hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else hgroup.long 0x4C0++0x03 hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hgroup.long 0x4C4++0x03 hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hgroup.long 0x4C8++0x03 hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hgroup.long 0x4CC++0x03 hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hgroup.long 0x4D0++0x03 hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hgroup.long 0x4D4++0x03 hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hgroup.long 0x4D8++0x03 hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hgroup.long 0x4DC++0x03 hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else hgroup.long 0x4E0++0x03 hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hgroup.long 0x4E4++0x03 hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hgroup.long 0x4E8++0x03 hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hgroup.long 0x4EC++0x03 hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hgroup.long 0x4F0++0x03 hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hgroup.long 0x4F4++0x03 hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hgroup.long 0x4F8++0x03 hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hgroup.long 0x4FC++0x03 hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else hgroup.long 0x500++0x03 hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hgroup.long 0x504++0x03 hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hgroup.long 0x508++0x03 hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hgroup.long 0x50C++0x03 hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hgroup.long 0x510++0x03 hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hgroup.long 0x514++0x03 hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hgroup.long 0x518++0x03 hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hgroup.long 0x51C++0x03 hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else hgroup.long 0x520++0x03 hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hgroup.long 0x524++0x03 hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hgroup.long 0x528++0x03 hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hgroup.long 0x52C++0x03 hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hgroup.long 0x530++0x03 hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hgroup.long 0x534++0x03 hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hgroup.long 0x538++0x03 hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hgroup.long 0x53C++0x03 hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else hgroup.long 0x540++0x03 hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hgroup.long 0x544++0x03 hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hgroup.long 0x548++0x03 hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hgroup.long 0x54C++0x03 hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hgroup.long 0x550++0x03 hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hgroup.long 0x554++0x03 hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hgroup.long 0x558++0x03 hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hgroup.long 0x55C++0x03 hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else hgroup.long 0x560++0x03 hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hgroup.long 0x564++0x03 hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hgroup.long 0x568++0x03 hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hgroup.long 0x56C++0x03 hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hgroup.long 0x570++0x03 hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hgroup.long 0x574++0x03 hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hgroup.long 0x578++0x03 hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hgroup.long 0x57C++0x03 hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else hgroup.long 0x580++0x03 hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hgroup.long 0x584++0x03 hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hgroup.long 0x588++0x03 hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hgroup.long 0x58C++0x03 hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hgroup.long 0x590++0x03 hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hgroup.long 0x594++0x03 hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hgroup.long 0x598++0x03 hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hgroup.long 0x59C++0x03 hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else hgroup.long 0x5A0++0x03 hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hgroup.long 0x5A4++0x03 hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hgroup.long 0x5A8++0x03 hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hgroup.long 0x5AC++0x03 hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hgroup.long 0x5B0++0x03 hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hgroup.long 0x5B4++0x03 hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hgroup.long 0x5B8++0x03 hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hgroup.long 0x5BC++0x03 hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else hgroup.long 0x5C0++0x03 hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hgroup.long 0x5C4++0x03 hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hgroup.long 0x5C8++0x03 hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hgroup.long 0x5CC++0x03 hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hgroup.long 0x5D0++0x03 hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hgroup.long 0x5D4++0x03 hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hgroup.long 0x5D8++0x03 hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hgroup.long 0x5DC++0x03 hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else hgroup.long 0x5E0++0x03 hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hgroup.long 0x5E4++0x03 hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hgroup.long 0x5E8++0x03 hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hgroup.long 0x5EC++0x03 hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hgroup.long 0x5F0++0x03 hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hgroup.long 0x5F4++0x03 hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hgroup.long 0x5F8++0x03 hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hgroup.long 0x5FC++0x03 hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else hgroup.long 0x600++0x03 hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hgroup.long 0x604++0x03 hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hgroup.long 0x608++0x03 hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hgroup.long 0x60C++0x03 hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hgroup.long 0x610++0x03 hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hgroup.long 0x614++0x03 hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hgroup.long 0x618++0x03 hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hgroup.long 0x61C++0x03 hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else hgroup.long 0x620++0x03 hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hgroup.long 0x624++0x03 hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hgroup.long 0x628++0x03 hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hgroup.long 0x62C++0x03 hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hgroup.long 0x630++0x03 hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hgroup.long 0x634++0x03 hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hgroup.long 0x638++0x03 hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hgroup.long 0x63C++0x03 hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else hgroup.long 0x640++0x03 hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hgroup.long 0x644++0x03 hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hgroup.long 0x648++0x03 hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hgroup.long 0x64C++0x03 hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hgroup.long 0x650++0x03 hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hgroup.long 0x654++0x03 hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hgroup.long 0x658++0x03 hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hgroup.long 0x65C++0x03 hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else hgroup.long 0x660++0x03 hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hgroup.long 0x664++0x03 hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hgroup.long 0x668++0x03 hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hgroup.long 0x66C++0x03 hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hgroup.long 0x670++0x03 hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hgroup.long 0x674++0x03 hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hgroup.long 0x678++0x03 hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hgroup.long 0x67C++0x03 hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else hgroup.long 0x680++0x03 hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hgroup.long 0x684++0x03 hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hgroup.long 0x688++0x03 hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hgroup.long 0x68C++0x03 hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hgroup.long 0x690++0x03 hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hgroup.long 0x694++0x03 hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hgroup.long 0x698++0x03 hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hgroup.long 0x69C++0x03 hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else hgroup.long 0x6A0++0x03 hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hgroup.long 0x6A4++0x03 hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hgroup.long 0x6A8++0x03 hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hgroup.long 0x6AC++0x03 hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hgroup.long 0x6B0++0x03 hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hgroup.long 0x6B4++0x03 hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hgroup.long 0x6B8++0x03 hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hgroup.long 0x6BC++0x03 hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else hgroup.long 0x6C0++0x03 hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hgroup.long 0x6C4++0x03 hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hgroup.long 0x6C8++0x03 hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hgroup.long 0x6CC++0x03 hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hgroup.long 0x6D0++0x03 hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hgroup.long 0x6D4++0x03 hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hgroup.long 0x6D8++0x03 hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hgroup.long 0x6DC++0x03 hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else hgroup.long 0x6E0++0x03 hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hgroup.long 0x6E4++0x03 hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hgroup.long 0x6E8++0x03 hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hgroup.long 0x6EC++0x03 hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hgroup.long 0x6F0++0x03 hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hgroup.long 0x6F4++0x03 hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hgroup.long 0x6F8++0x03 hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hgroup.long 0x6FC++0x03 hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else hgroup.long 0x700++0x03 hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hgroup.long 0x704++0x03 hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hgroup.long 0x708++0x03 hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hgroup.long 0x70C++0x03 hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hgroup.long 0x710++0x03 hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hgroup.long 0x714++0x03 hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hgroup.long 0x718++0x03 hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hgroup.long 0x71C++0x03 hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else hgroup.long 0x720++0x03 hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hgroup.long 0x724++0x03 hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hgroup.long 0x728++0x03 hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hgroup.long 0x72C++0x03 hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hgroup.long 0x730++0x03 hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hgroup.long 0x734++0x03 hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hgroup.long 0x738++0x03 hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hgroup.long 0x73C++0x03 hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else hgroup.long 0x740++0x03 hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hgroup.long 0x744++0x03 hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hgroup.long 0x748++0x03 hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hgroup.long 0x74C++0x03 hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hgroup.long 0x750++0x03 hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hgroup.long 0x754++0x03 hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hgroup.long 0x758++0x03 hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hgroup.long 0x75C++0x03 hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else hgroup.long 0x760++0x03 hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hgroup.long 0x764++0x03 hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hgroup.long 0x768++0x03 hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hgroup.long 0x76C++0x03 hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hgroup.long 0x770++0x03 hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hgroup.long 0x774++0x03 hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hgroup.long 0x778++0x03 hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hgroup.long 0x77C++0x03 hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else hgroup.long 0x780++0x03 hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hgroup.long 0x784++0x03 hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hgroup.long 0x788++0x03 hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hgroup.long 0x78C++0x03 hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hgroup.long 0x790++0x03 hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hgroup.long 0x794++0x03 hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hgroup.long 0x798++0x03 hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hgroup.long 0x79C++0x03 hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else hgroup.long 0x7A0++0x03 hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hgroup.long 0x7A4++0x03 hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hgroup.long 0x7A8++0x03 hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hgroup.long 0x7AC++0x03 hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hgroup.long 0x7B0++0x03 hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hgroup.long 0x7B4++0x03 hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hgroup.long 0x7B8++0x03 hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hgroup.long 0x7BC++0x03 hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else hgroup.long 0x7C0++0x03 hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hgroup.long 0x7C4++0x03 hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hgroup.long 0x7C8++0x03 hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hgroup.long 0x7CC++0x03 hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hgroup.long 0x7D0++0x03 hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hgroup.long 0x7D4++0x03 hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hgroup.long 0x7D8++0x03 hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hgroup.long 0x7DC++0x03 hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif tree.end width 19. tree "Interrupt Targets Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x000000E0)>0x1) hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif else hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif tree.end width 14. tree "Configuration Registers" rgroup.long 0xC00++0x03 line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SGI)" "Level,Edge" group.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (PPI)" "Level,Edge" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC08++0x03 hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" hgroup.long 0xC0C++0x03 hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC10++0x03 hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" hgroup.long 0xC14++0x03 hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC18++0x03 hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" hgroup.long 0xC1C++0x03 hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC20++0x03 hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" hgroup.long 0xC24++0x03 hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC28++0x03 hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" hgroup.long 0xC2C++0x03 hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC30++0x03 hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" hgroup.long 0xC34++0x03 hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC38++0x03 hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" hgroup.long 0xC3C++0x03 hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC40++0x03 hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" hgroup.long 0xC44++0x03 hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC48++0x03 hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" hgroup.long 0xC4C++0x03 hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC50++0x03 hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" hgroup.long 0xC54++0x03 hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC58++0x03 hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" hgroup.long 0xC5C++0x03 hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC60++0x03 hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" hgroup.long 0xC64++0x03 hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC68++0x03 hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" hgroup.long 0xC6C++0x03 hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC70++0x03 hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" hgroup.long 0xC74++0x03 hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC78++0x03 hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" hgroup.long 0xC7C++0x03 hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC80++0x03 hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" hgroup.long 0xC84++0x03 hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC88++0x03 hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" hgroup.long 0xC8C++0x03 hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC90++0x03 hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" hgroup.long 0xC94++0x03 hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC98++0x03 hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" hgroup.long 0xC9C++0x03 hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCA0++0x03 hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" hgroup.long 0xCA4++0x03 hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCA8++0x03 hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" hgroup.long 0xCAC++0x03 hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCB0++0x03 hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" hgroup.long 0xCB4++0x03 hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCB8++0x03 hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" hgroup.long 0xCBC++0x03 hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCC0++0x03 hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" hgroup.long 0xCC4++0x03 hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCC8++0x03 hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" hgroup.long 0xCCC++0x03 hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCD0++0x03 hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" hgroup.long 0xCD4++0x03 hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCD8++0x03 hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" hgroup.long 0xCDC++0x03 hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCE0++0x03 hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" hgroup.long 0xCE4++0x03 hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCE8++0x03 hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" hgroup.long 0xCEC++0x03 hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCF0++0x03 hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" hgroup.long 0xCF4++0x03 hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif tree.end width 17. tree "Interrupt Group Modifier Registers" hgroup.long 0x0D00++0x03 hide.long 0x0 "GICD_IGRPMODR0,Interrupt Group Modifier Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D00))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)) group.long 0x0D04++0x03 line.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1" bitfld.long 0x00 31. " GMB63 ,Group Modifier Bit 63" "0,1" bitfld.long 0x00 30. " GMB62 ,Group Modifier Bit 62" "0,1" bitfld.long 0x00 29. " GMB61 ,Group Modifier Bit 61" "0,1" textline " " bitfld.long 0x00 28. " GMB60 ,Group Modifier Bit 60" "0,1" bitfld.long 0x00 27. " GMB59 ,Group Modifier Bit 59" "0,1" bitfld.long 0x00 26. " GMB58 ,Group Modifier Bit 58" "0,1" textline " " bitfld.long 0x00 25. " GMB57 ,Group Modifier Bit 57" "0,1" bitfld.long 0x00 24. " GMB56 ,Group Modifier Bit 56" "0,1" bitfld.long 0x00 23. " GMB55 ,Group Modifier Bit 55" "0,1" textline " " bitfld.long 0x00 22. " GMB54 ,Group Modifier Bit 54" "0,1" bitfld.long 0x00 21. " GMB53 ,Group Modifier Bit 53" "0,1" bitfld.long 0x00 20. " GMB52 ,Group Modifier Bit 52" "0,1" textline " " bitfld.long 0x00 19. " GMB51 ,Group Modifier Bit 51" "0,1" bitfld.long 0x00 18. " GMB50 ,Group Modifier Bit 50" "0,1" bitfld.long 0x00 17. " GMB49 ,Group Modifier Bit 49" "0,1" textline " " bitfld.long 0x00 16. " GMB48 ,Group Modifier Bit 48" "0,1" bitfld.long 0x00 15. " GMB47 ,Group Modifier Bit 47" "0,1" bitfld.long 0x00 14. " GMB46 ,Group Modifier Bit 46" "0,1" textline " " bitfld.long 0x00 13. " GMB45 ,Group Modifier Bit 45" "0,1" bitfld.long 0x00 12. " GMB44 ,Group Modifier Bit 44" "0,1" bitfld.long 0x00 11. " GMB43 ,Group Modifier Bit 43" "0,1" textline " " bitfld.long 0x00 10. " GMB42 ,Group Modifier Bit 42" "0,1" bitfld.long 0x00 9. " GMB41 ,Group Modifier Bit 41" "0,1" bitfld.long 0x00 8. " GMB40 ,Group Modifier Bit 40" "0,1" textline " " bitfld.long 0x00 7. " GMB39 ,Group Modifier Bit 39" "0,1" bitfld.long 0x00 6. " GMB38 ,Group Modifier Bit 38" "0,1" bitfld.long 0x00 5. " GMB37 ,Group Modifier Bit 37" "0,1" textline " " bitfld.long 0x00 4. " GMB36 ,Group Modifier Bit 36" "0,1" bitfld.long 0x00 3. " GMB35 ,Group Modifier Bit 35" "0,1" bitfld.long 0x00 2. " GMB34 ,Group Modifier Bit 34" "0,1" textline " " bitfld.long 0x00 1. " GMB33 ,Group Modifier Bit 33" "0,1" bitfld.long 0x00 0. " GMB32 ,Group Modifier Bit 32" "0,1" else hgroup.long 0x0D04++0x03 hide.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D08))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)) group.long 0x0D08++0x03 line.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2" bitfld.long 0x00 31. " GMB95 ,Group Modifier Bit 95" "0,1" bitfld.long 0x00 30. " GMB94 ,Group Modifier Bit 94" "0,1" bitfld.long 0x00 29. " GMB93 ,Group Modifier Bit 93" "0,1" textline " " bitfld.long 0x00 28. " GMB92 ,Group Modifier Bit 92" "0,1" bitfld.long 0x00 27. " GMB91 ,Group Modifier Bit 91" "0,1" bitfld.long 0x00 26. " GMB90 ,Group Modifier Bit 90" "0,1" textline " " bitfld.long 0x00 25. " GMB89 ,Group Modifier Bit 89" "0,1" bitfld.long 0x00 24. " GMB88 ,Group Modifier Bit 88" "0,1" bitfld.long 0x00 23. " GMB87 ,Group Modifier Bit 87" "0,1" textline " " bitfld.long 0x00 22. " GMB86 ,Group Modifier Bit 86" "0,1" bitfld.long 0x00 21. " GMB85 ,Group Modifier Bit 85" "0,1" bitfld.long 0x00 20. " GMB84 ,Group Modifier Bit 84" "0,1" textline " " bitfld.long 0x00 19. " GMB83 ,Group Modifier Bit 83" "0,1" bitfld.long 0x00 18. " GMB82 ,Group Modifier Bit 82" "0,1" bitfld.long 0x00 17. " GMB81 ,Group Modifier Bit 81" "0,1" textline " " bitfld.long 0x00 16. " GMB80 ,Group Modifier Bit 80" "0,1" bitfld.long 0x00 15. " GMB79 ,Group Modifier Bit 79" "0,1" bitfld.long 0x00 14. " GMB78 ,Group Modifier Bit 78" "0,1" textline " " bitfld.long 0x00 13. " GMB77 ,Group Modifier Bit 77" "0,1" bitfld.long 0x00 12. " GMB76 ,Group Modifier Bit 76" "0,1" bitfld.long 0x00 11. " GMB75 ,Group Modifier Bit 75" "0,1" textline " " bitfld.long 0x00 10. " GMB74 ,Group Modifier Bit 74" "0,1" bitfld.long 0x00 9. " GMB73 ,Group Modifier Bit 73" "0,1" bitfld.long 0x00 8. " GMB72 ,Group Modifier Bit 72" "0,1" textline " " bitfld.long 0x00 7. " GMB71 ,Group Modifier Bit 71" "0,1" bitfld.long 0x00 6. " GMB70 ,Group Modifier Bit 70" "0,1" bitfld.long 0x00 5. " GMB69 ,Group Modifier Bit 69" "0,1" textline " " bitfld.long 0x00 4. " GMB68 ,Group Modifier Bit 68" "0,1" bitfld.long 0x00 3. " GMB67 ,Group Modifier Bit 67" "0,1" bitfld.long 0x00 2. " GMB66 ,Group Modifier Bit 66" "0,1" textline " " bitfld.long 0x00 1. " GMB65 ,Group Modifier Bit 65" "0,1" bitfld.long 0x00 0. " GMB64 ,Group Modifier Bit 64" "0,1" else hgroup.long 0x0D08++0x03 hide.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D0C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)) group.long 0x0D0C++0x03 line.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3" bitfld.long 0x00 31. " GMB127 ,Group Modifier Bit 127" "0,1" bitfld.long 0x00 30. " GMB126 ,Group Modifier Bit 126" "0,1" bitfld.long 0x00 29. " GMB125 ,Group Modifier Bit 125" "0,1" textline " " bitfld.long 0x00 28. " GMB124 ,Group Modifier Bit 124" "0,1" bitfld.long 0x00 27. " GMB123 ,Group Modifier Bit 123" "0,1" bitfld.long 0x00 26. " GMB122 ,Group Modifier Bit 122" "0,1" textline " " bitfld.long 0x00 25. " GMB121 ,Group Modifier Bit 121" "0,1" bitfld.long 0x00 24. " GMB120 ,Group Modifier Bit 120" "0,1" bitfld.long 0x00 23. " GMB119 ,Group Modifier Bit 119" "0,1" textline " " bitfld.long 0x00 22. " GMB118 ,Group Modifier Bit 118" "0,1" bitfld.long 0x00 21. " GMB117 ,Group Modifier Bit 117" "0,1" bitfld.long 0x00 20. " GMB116 ,Group Modifier Bit 116" "0,1" textline " " bitfld.long 0x00 19. " GMB115 ,Group Modifier Bit 115" "0,1" bitfld.long 0x00 18. " GMB114 ,Group Modifier Bit 114" "0,1" bitfld.long 0x00 17. " GMB113 ,Group Modifier Bit 113" "0,1" textline " " bitfld.long 0x00 16. " GMB112 ,Group Modifier Bit 112" "0,1" bitfld.long 0x00 15. " GMB111 ,Group Modifier Bit 111" "0,1" bitfld.long 0x00 14. " GMB110 ,Group Modifier Bit 110" "0,1" textline " " bitfld.long 0x00 13. " GMB109 ,Group Modifier Bit 109" "0,1" bitfld.long 0x00 12. " GMB108 ,Group Modifier Bit 108" "0,1" bitfld.long 0x00 11. " GMB107 ,Group Modifier Bit 107" "0,1" textline " " bitfld.long 0x00 10. " GMB106 ,Group Modifier Bit 106" "0,1" bitfld.long 0x00 9. " GMB105 ,Group Modifier Bit 105" "0,1" bitfld.long 0x00 8. " GMB104 ,Group Modifier Bit 104" "0,1" textline " " bitfld.long 0x00 7. " GMB103 ,Group Modifier Bit 103" "0,1" bitfld.long 0x00 6. " GMB102 ,Group Modifier Bit 102" "0,1" bitfld.long 0x00 5. " GMB101 ,Group Modifier Bit 101" "0,1" textline " " bitfld.long 0x00 4. " GMB100 ,Group Modifier Bit 100" "0,1" bitfld.long 0x00 3. " GMB99 ,Group Modifier Bit 99" "0,1" bitfld.long 0x00 2. " GMB98 ,Group Modifier Bit 98" "0,1" textline " " bitfld.long 0x00 1. " GMB97 ,Group Modifier Bit 97" "0,1" bitfld.long 0x00 0. " GMB96 ,Group Modifier Bit 96" "0,1" else hgroup.long 0x0D0C++0x03 hide.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D10))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)) group.long 0x0D10++0x03 line.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4" bitfld.long 0x00 31. " GMB159 ,Group Modifier Bit 159" "0,1" bitfld.long 0x00 30. " GMB158 ,Group Modifier Bit 158" "0,1" bitfld.long 0x00 29. " GMB157 ,Group Modifier Bit 157" "0,1" textline " " bitfld.long 0x00 28. " GMB156 ,Group Modifier Bit 156" "0,1" bitfld.long 0x00 27. " GMB155 ,Group Modifier Bit 155" "0,1" bitfld.long 0x00 26. " GMB154 ,Group Modifier Bit 154" "0,1" textline " " bitfld.long 0x00 25. " GMB153 ,Group Modifier Bit 153" "0,1" bitfld.long 0x00 24. " GMB152 ,Group Modifier Bit 152" "0,1" bitfld.long 0x00 23. " GMB151 ,Group Modifier Bit 151" "0,1" textline " " bitfld.long 0x00 22. " GMB150 ,Group Modifier Bit 150" "0,1" bitfld.long 0x00 21. " GMB149 ,Group Modifier Bit 149" "0,1" bitfld.long 0x00 20. " GMB148 ,Group Modifier Bit 148" "0,1" textline " " bitfld.long 0x00 19. " GMB147 ,Group Modifier Bit 147" "0,1" bitfld.long 0x00 18. " GMB146 ,Group Modifier Bit 146" "0,1" bitfld.long 0x00 17. " GMB145 ,Group Modifier Bit 145" "0,1" textline " " bitfld.long 0x00 16. " GMB144 ,Group Modifier Bit 144" "0,1" bitfld.long 0x00 15. " GMB143 ,Group Modifier Bit 143" "0,1" bitfld.long 0x00 14. " GMB142 ,Group Modifier Bit 142" "0,1" textline " " bitfld.long 0x00 13. " GMB141 ,Group Modifier Bit 141" "0,1" bitfld.long 0x00 12. " GMB140 ,Group Modifier Bit 140" "0,1" bitfld.long 0x00 11. " GMB139 ,Group Modifier Bit 139" "0,1" textline " " bitfld.long 0x00 10. " GMB138 ,Group Modifier Bit 138" "0,1" bitfld.long 0x00 9. " GMB137 ,Group Modifier Bit 137" "0,1" bitfld.long 0x00 8. " GMB136 ,Group Modifier Bit 136" "0,1" textline " " bitfld.long 0x00 7. " GMB135 ,Group Modifier Bit 135" "0,1" bitfld.long 0x00 6. " GMB134 ,Group Modifier Bit 134" "0,1" bitfld.long 0x00 5. " GMB133 ,Group Modifier Bit 133" "0,1" textline " " bitfld.long 0x00 4. " GMB132 ,Group Modifier Bit 132" "0,1" bitfld.long 0x00 3. " GMB131 ,Group Modifier Bit 131" "0,1" bitfld.long 0x00 2. " GMB130 ,Group Modifier Bit 130" "0,1" textline " " bitfld.long 0x00 1. " GMB129 ,Group Modifier Bit 129" "0,1" bitfld.long 0x00 0. " GMB128 ,Group Modifier Bit 128" "0,1" else hgroup.long 0x0D10++0x03 hide.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D14))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)) group.long 0x0D14++0x03 line.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5" bitfld.long 0x00 31. " GMB191 ,Group Modifier Bit 191" "0,1" bitfld.long 0x00 30. " GMB190 ,Group Modifier Bit 190" "0,1" bitfld.long 0x00 29. " GMB189 ,Group Modifier Bit 189" "0,1" textline " " bitfld.long 0x00 28. " GMB188 ,Group Modifier Bit 188" "0,1" bitfld.long 0x00 27. " GMB187 ,Group Modifier Bit 187" "0,1" bitfld.long 0x00 26. " GMB186 ,Group Modifier Bit 186" "0,1" textline " " bitfld.long 0x00 25. " GMB185 ,Group Modifier Bit 185" "0,1" bitfld.long 0x00 24. " GMB184 ,Group Modifier Bit 184" "0,1" bitfld.long 0x00 23. " GMB183 ,Group Modifier Bit 183" "0,1" textline " " bitfld.long 0x00 22. " GMB182 ,Group Modifier Bit 182" "0,1" bitfld.long 0x00 21. " GMB181 ,Group Modifier Bit 181" "0,1" bitfld.long 0x00 20. " GMB180 ,Group Modifier Bit 180" "0,1" textline " " bitfld.long 0x00 19. " GMB179 ,Group Modifier Bit 179" "0,1" bitfld.long 0x00 18. " GMB178 ,Group Modifier Bit 178" "0,1" bitfld.long 0x00 17. " GMB177 ,Group Modifier Bit 177" "0,1" textline " " bitfld.long 0x00 16. " GMB176 ,Group Modifier Bit 176" "0,1" bitfld.long 0x00 15. " GMB175 ,Group Modifier Bit 175" "0,1" bitfld.long 0x00 14. " GMB174 ,Group Modifier Bit 174" "0,1" textline " " bitfld.long 0x00 13. " GMB173 ,Group Modifier Bit 173" "0,1" bitfld.long 0x00 12. " GMB172 ,Group Modifier Bit 172" "0,1" bitfld.long 0x00 11. " GMB171 ,Group Modifier Bit 171" "0,1" textline " " bitfld.long 0x00 10. " GMB170 ,Group Modifier Bit 170" "0,1" bitfld.long 0x00 9. " GMB169 ,Group Modifier Bit 169" "0,1" bitfld.long 0x00 8. " GMB168 ,Group Modifier Bit 168" "0,1" textline " " bitfld.long 0x00 7. " GMB167 ,Group Modifier Bit 167" "0,1" bitfld.long 0x00 6. " GMB166 ,Group Modifier Bit 166" "0,1" bitfld.long 0x00 5. " GMB165 ,Group Modifier Bit 165" "0,1" textline " " bitfld.long 0x00 4. " GMB164 ,Group Modifier Bit 164" "0,1" bitfld.long 0x00 3. " GMB163 ,Group Modifier Bit 163" "0,1" bitfld.long 0x00 2. " GMB162 ,Group Modifier Bit 162" "0,1" textline " " bitfld.long 0x00 1. " GMB161 ,Group Modifier Bit 161" "0,1" bitfld.long 0x00 0. " GMB160 ,Group Modifier Bit 160" "0,1" else hgroup.long 0x0D14++0x03 hide.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D18))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)) group.long 0x0D18++0x03 line.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6" bitfld.long 0x00 31. " GMB223 ,Group Modifier Bit 223" "0,1" bitfld.long 0x00 30. " GMB222 ,Group Modifier Bit 222" "0,1" bitfld.long 0x00 29. " GMB221 ,Group Modifier Bit 221" "0,1" textline " " bitfld.long 0x00 28. " GMB220 ,Group Modifier Bit 220" "0,1" bitfld.long 0x00 27. " GMB219 ,Group Modifier Bit 219" "0,1" bitfld.long 0x00 26. " GMB218 ,Group Modifier Bit 218" "0,1" textline " " bitfld.long 0x00 25. " GMB217 ,Group Modifier Bit 217" "0,1" bitfld.long 0x00 24. " GMB216 ,Group Modifier Bit 216" "0,1" bitfld.long 0x00 23. " GMB215 ,Group Modifier Bit 215" "0,1" textline " " bitfld.long 0x00 22. " GMB214 ,Group Modifier Bit 214" "0,1" bitfld.long 0x00 21. " GMB213 ,Group Modifier Bit 213" "0,1" bitfld.long 0x00 20. " GMB212 ,Group Modifier Bit 212" "0,1" textline " " bitfld.long 0x00 19. " GMB211 ,Group Modifier Bit 211" "0,1" bitfld.long 0x00 18. " GMB210 ,Group Modifier Bit 210" "0,1" bitfld.long 0x00 17. " GMB209 ,Group Modifier Bit 209" "0,1" textline " " bitfld.long 0x00 16. " GMB208 ,Group Modifier Bit 208" "0,1" bitfld.long 0x00 15. " GMB207 ,Group Modifier Bit 207" "0,1" bitfld.long 0x00 14. " GMB206 ,Group Modifier Bit 206" "0,1" textline " " bitfld.long 0x00 13. " GMB205 ,Group Modifier Bit 205" "0,1" bitfld.long 0x00 12. " GMB204 ,Group Modifier Bit 204" "0,1" bitfld.long 0x00 11. " GMB203 ,Group Modifier Bit 203" "0,1" textline " " bitfld.long 0x00 10. " GMB202 ,Group Modifier Bit 202" "0,1" bitfld.long 0x00 9. " GMB201 ,Group Modifier Bit 201" "0,1" bitfld.long 0x00 8. " GMB200 ,Group Modifier Bit 200" "0,1" textline " " bitfld.long 0x00 7. " GMB199 ,Group Modifier Bit 199" "0,1" bitfld.long 0x00 6. " GMB198 ,Group Modifier Bit 198" "0,1" bitfld.long 0x00 5. " GMB197 ,Group Modifier Bit 197" "0,1" textline " " bitfld.long 0x00 4. " GMB196 ,Group Modifier Bit 196" "0,1" bitfld.long 0x00 3. " GMB195 ,Group Modifier Bit 195" "0,1" bitfld.long 0x00 2. " GMB194 ,Group Modifier Bit 194" "0,1" textline " " bitfld.long 0x00 1. " GMB193 ,Group Modifier Bit 193" "0,1" bitfld.long 0x00 0. " GMB192 ,Group Modifier Bit 192" "0,1" else hgroup.long 0x0D18++0x03 hide.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D1C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)) group.long 0x0D1C++0x03 line.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7" bitfld.long 0x00 31. " GMB255 ,Group Modifier Bit 255" "0,1" bitfld.long 0x00 30. " GMB254 ,Group Modifier Bit 254" "0,1" bitfld.long 0x00 29. " GMB253 ,Group Modifier Bit 253" "0,1" textline " " bitfld.long 0x00 28. " GMB252 ,Group Modifier Bit 252" "0,1" bitfld.long 0x00 27. " GMB251 ,Group Modifier Bit 251" "0,1" bitfld.long 0x00 26. " GMB250 ,Group Modifier Bit 250" "0,1" textline " " bitfld.long 0x00 25. " GMB249 ,Group Modifier Bit 249" "0,1" bitfld.long 0x00 24. " GMB248 ,Group Modifier Bit 248" "0,1" bitfld.long 0x00 23. " GMB247 ,Group Modifier Bit 247" "0,1" textline " " bitfld.long 0x00 22. " GMB246 ,Group Modifier Bit 246" "0,1" bitfld.long 0x00 21. " GMB245 ,Group Modifier Bit 245" "0,1" bitfld.long 0x00 20. " GMB244 ,Group Modifier Bit 244" "0,1" textline " " bitfld.long 0x00 19. " GMB243 ,Group Modifier Bit 243" "0,1" bitfld.long 0x00 18. " GMB242 ,Group Modifier Bit 242" "0,1" bitfld.long 0x00 17. " GMB241 ,Group Modifier Bit 241" "0,1" textline " " bitfld.long 0x00 16. " GMB240 ,Group Modifier Bit 240" "0,1" bitfld.long 0x00 15. " GMB239 ,Group Modifier Bit 239" "0,1" bitfld.long 0x00 14. " GMB238 ,Group Modifier Bit 238" "0,1" textline " " bitfld.long 0x00 13. " GMB237 ,Group Modifier Bit 237" "0,1" bitfld.long 0x00 12. " GMB236 ,Group Modifier Bit 236" "0,1" bitfld.long 0x00 11. " GMB235 ,Group Modifier Bit 235" "0,1" textline " " bitfld.long 0x00 10. " GMB234 ,Group Modifier Bit 234" "0,1" bitfld.long 0x00 9. " GMB233 ,Group Modifier Bit 233" "0,1" bitfld.long 0x00 8. " GMB232 ,Group Modifier Bit 232" "0,1" textline " " bitfld.long 0x00 7. " GMB231 ,Group Modifier Bit 231" "0,1" bitfld.long 0x00 6. " GMB230 ,Group Modifier Bit 230" "0,1" bitfld.long 0x00 5. " GMB229 ,Group Modifier Bit 229" "0,1" textline " " bitfld.long 0x00 4. " GMB228 ,Group Modifier Bit 228" "0,1" bitfld.long 0x00 3. " GMB227 ,Group Modifier Bit 227" "0,1" bitfld.long 0x00 2. " GMB226 ,Group Modifier Bit 226" "0,1" textline " " bitfld.long 0x00 1. " GMB225 ,Group Modifier Bit 225" "0,1" bitfld.long 0x00 0. " GMB224 ,Group Modifier Bit 224" "0,1" else hgroup.long 0x0D1C++0x03 hide.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D20))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)) group.long 0x0D20++0x03 line.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8" bitfld.long 0x00 31. " GMB287 ,Group Modifier Bit 287" "0,1" bitfld.long 0x00 30. " GMB286 ,Group Modifier Bit 286" "0,1" bitfld.long 0x00 29. " GMB285 ,Group Modifier Bit 285" "0,1" textline " " bitfld.long 0x00 28. " GMB284 ,Group Modifier Bit 284" "0,1" bitfld.long 0x00 27. " GMB283 ,Group Modifier Bit 283" "0,1" bitfld.long 0x00 26. " GMB282 ,Group Modifier Bit 282" "0,1" textline " " bitfld.long 0x00 25. " GMB281 ,Group Modifier Bit 281" "0,1" bitfld.long 0x00 24. " GMB280 ,Group Modifier Bit 280" "0,1" bitfld.long 0x00 23. " GMB279 ,Group Modifier Bit 279" "0,1" textline " " bitfld.long 0x00 22. " GMB278 ,Group Modifier Bit 278" "0,1" bitfld.long 0x00 21. " GMB277 ,Group Modifier Bit 277" "0,1" bitfld.long 0x00 20. " GMB276 ,Group Modifier Bit 276" "0,1" textline " " bitfld.long 0x00 19. " GMB275 ,Group Modifier Bit 275" "0,1" bitfld.long 0x00 18. " GMB274 ,Group Modifier Bit 274" "0,1" bitfld.long 0x00 17. " GMB273 ,Group Modifier Bit 273" "0,1" textline " " bitfld.long 0x00 16. " GMB272 ,Group Modifier Bit 272" "0,1" bitfld.long 0x00 15. " GMB271 ,Group Modifier Bit 271" "0,1" bitfld.long 0x00 14. " GMB270 ,Group Modifier Bit 270" "0,1" textline " " bitfld.long 0x00 13. " GMB269 ,Group Modifier Bit 269" "0,1" bitfld.long 0x00 12. " GMB268 ,Group Modifier Bit 268" "0,1" bitfld.long 0x00 11. " GMB267 ,Group Modifier Bit 267" "0,1" textline " " bitfld.long 0x00 10. " GMB266 ,Group Modifier Bit 266" "0,1" bitfld.long 0x00 9. " GMB265 ,Group Modifier Bit 265" "0,1" bitfld.long 0x00 8. " GMB264 ,Group Modifier Bit 264" "0,1" textline " " bitfld.long 0x00 7. " GMB263 ,Group Modifier Bit 263" "0,1" bitfld.long 0x00 6. " GMB262 ,Group Modifier Bit 262" "0,1" bitfld.long 0x00 5. " GMB261 ,Group Modifier Bit 261" "0,1" textline " " bitfld.long 0x00 4. " GMB260 ,Group Modifier Bit 260" "0,1" bitfld.long 0x00 3. " GMB259 ,Group Modifier Bit 259" "0,1" bitfld.long 0x00 2. " GMB258 ,Group Modifier Bit 258" "0,1" textline " " bitfld.long 0x00 1. " GMB257 ,Group Modifier Bit 257" "0,1" bitfld.long 0x00 0. " GMB256 ,Group Modifier Bit 256" "0,1" else hgroup.long 0x0D20++0x03 hide.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D24))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)) group.long 0x0D24++0x03 line.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9" bitfld.long 0x00 31. " GMB319 ,Group Modifier Bit 319" "0,1" bitfld.long 0x00 30. " GMB318 ,Group Modifier Bit 318" "0,1" bitfld.long 0x00 29. " GMB317 ,Group Modifier Bit 317" "0,1" textline " " bitfld.long 0x00 28. " GMB316 ,Group Modifier Bit 316" "0,1" bitfld.long 0x00 27. " GMB315 ,Group Modifier Bit 315" "0,1" bitfld.long 0x00 26. " GMB314 ,Group Modifier Bit 314" "0,1" textline " " bitfld.long 0x00 25. " GMB313 ,Group Modifier Bit 313" "0,1" bitfld.long 0x00 24. " GMB312 ,Group Modifier Bit 312" "0,1" bitfld.long 0x00 23. " GMB311 ,Group Modifier Bit 311" "0,1" textline " " bitfld.long 0x00 22. " GMB310 ,Group Modifier Bit 310" "0,1" bitfld.long 0x00 21. " GMB309 ,Group Modifier Bit 309" "0,1" bitfld.long 0x00 20. " GMB308 ,Group Modifier Bit 308" "0,1" textline " " bitfld.long 0x00 19. " GMB307 ,Group Modifier Bit 307" "0,1" bitfld.long 0x00 18. " GMB306 ,Group Modifier Bit 306" "0,1" bitfld.long 0x00 17. " GMB305 ,Group Modifier Bit 305" "0,1" textline " " bitfld.long 0x00 16. " GMB304 ,Group Modifier Bit 304" "0,1" bitfld.long 0x00 15. " GMB303 ,Group Modifier Bit 303" "0,1" bitfld.long 0x00 14. " GMB302 ,Group Modifier Bit 302" "0,1" textline " " bitfld.long 0x00 13. " GMB301 ,Group Modifier Bit 301" "0,1" bitfld.long 0x00 12. " GMB300 ,Group Modifier Bit 300" "0,1" bitfld.long 0x00 11. " GMB299 ,Group Modifier Bit 299" "0,1" textline " " bitfld.long 0x00 10. " GMB298 ,Group Modifier Bit 298" "0,1" bitfld.long 0x00 9. " GMB297 ,Group Modifier Bit 297" "0,1" bitfld.long 0x00 8. " GMB296 ,Group Modifier Bit 296" "0,1" textline " " bitfld.long 0x00 7. " GMB295 ,Group Modifier Bit 295" "0,1" bitfld.long 0x00 6. " GMB294 ,Group Modifier Bit 294" "0,1" bitfld.long 0x00 5. " GMB293 ,Group Modifier Bit 293" "0,1" textline " " bitfld.long 0x00 4. " GMB292 ,Group Modifier Bit 292" "0,1" bitfld.long 0x00 3. " GMB291 ,Group Modifier Bit 291" "0,1" bitfld.long 0x00 2. " GMB290 ,Group Modifier Bit 290" "0,1" textline " " bitfld.long 0x00 1. " GMB289 ,Group Modifier Bit 289" "0,1" bitfld.long 0x00 0. " GMB288 ,Group Modifier Bit 288" "0,1" else hgroup.long 0x0D24++0x03 hide.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D28))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)) group.long 0x0D28++0x03 line.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10" bitfld.long 0x00 31. " GMB351 ,Group Modifier Bit 351" "0,1" bitfld.long 0x00 30. " GMB350 ,Group Modifier Bit 350" "0,1" bitfld.long 0x00 29. " GMB349 ,Group Modifier Bit 349" "0,1" textline " " bitfld.long 0x00 28. " GMB348 ,Group Modifier Bit 348" "0,1" bitfld.long 0x00 27. " GMB347 ,Group Modifier Bit 347" "0,1" bitfld.long 0x00 26. " GMB346 ,Group Modifier Bit 346" "0,1" textline " " bitfld.long 0x00 25. " GMB345 ,Group Modifier Bit 345" "0,1" bitfld.long 0x00 24. " GMB344 ,Group Modifier Bit 344" "0,1" bitfld.long 0x00 23. " GMB343 ,Group Modifier Bit 343" "0,1" textline " " bitfld.long 0x00 22. " GMB342 ,Group Modifier Bit 342" "0,1" bitfld.long 0x00 21. " GMB341 ,Group Modifier Bit 341" "0,1" bitfld.long 0x00 20. " GMB340 ,Group Modifier Bit 340" "0,1" textline " " bitfld.long 0x00 19. " GMB339 ,Group Modifier Bit 339" "0,1" bitfld.long 0x00 18. " GMB338 ,Group Modifier Bit 338" "0,1" bitfld.long 0x00 17. " GMB337 ,Group Modifier Bit 337" "0,1" textline " " bitfld.long 0x00 16. " GMB336 ,Group Modifier Bit 336" "0,1" bitfld.long 0x00 15. " GMB335 ,Group Modifier Bit 335" "0,1" bitfld.long 0x00 14. " GMB334 ,Group Modifier Bit 334" "0,1" textline " " bitfld.long 0x00 13. " GMB333 ,Group Modifier Bit 333" "0,1" bitfld.long 0x00 12. " GMB332 ,Group Modifier Bit 332" "0,1" bitfld.long 0x00 11. " GMB331 ,Group Modifier Bit 331" "0,1" textline " " bitfld.long 0x00 10. " GMB330 ,Group Modifier Bit 330" "0,1" bitfld.long 0x00 9. " GMB329 ,Group Modifier Bit 329" "0,1" bitfld.long 0x00 8. " GMB328 ,Group Modifier Bit 328" "0,1" textline " " bitfld.long 0x00 7. " GMB327 ,Group Modifier Bit 327" "0,1" bitfld.long 0x00 6. " GMB326 ,Group Modifier Bit 326" "0,1" bitfld.long 0x00 5. " GMB325 ,Group Modifier Bit 325" "0,1" textline " " bitfld.long 0x00 4. " GMB324 ,Group Modifier Bit 324" "0,1" bitfld.long 0x00 3. " GMB323 ,Group Modifier Bit 323" "0,1" bitfld.long 0x00 2. " GMB322 ,Group Modifier Bit 322" "0,1" textline " " bitfld.long 0x00 1. " GMB321 ,Group Modifier Bit 321" "0,1" bitfld.long 0x00 0. " GMB320 ,Group Modifier Bit 320" "0,1" else hgroup.long 0x0D28++0x03 hide.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D2C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)) group.long 0x0D2C++0x03 line.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11" bitfld.long 0x00 31. " GMB383 ,Group Modifier Bit 383" "0,1" bitfld.long 0x00 30. " GMB382 ,Group Modifier Bit 382" "0,1" bitfld.long 0x00 29. " GMB381 ,Group Modifier Bit 381" "0,1" textline " " bitfld.long 0x00 28. " GMB380 ,Group Modifier Bit 380" "0,1" bitfld.long 0x00 27. " GMB379 ,Group Modifier Bit 379" "0,1" bitfld.long 0x00 26. " GMB378 ,Group Modifier Bit 378" "0,1" textline " " bitfld.long 0x00 25. " GMB377 ,Group Modifier Bit 377" "0,1" bitfld.long 0x00 24. " GMB376 ,Group Modifier Bit 376" "0,1" bitfld.long 0x00 23. " GMB375 ,Group Modifier Bit 375" "0,1" textline " " bitfld.long 0x00 22. " GMB374 ,Group Modifier Bit 374" "0,1" bitfld.long 0x00 21. " GMB373 ,Group Modifier Bit 373" "0,1" bitfld.long 0x00 20. " GMB372 ,Group Modifier Bit 372" "0,1" textline " " bitfld.long 0x00 19. " GMB371 ,Group Modifier Bit 371" "0,1" bitfld.long 0x00 18. " GMB370 ,Group Modifier Bit 370" "0,1" bitfld.long 0x00 17. " GMB369 ,Group Modifier Bit 369" "0,1" textline " " bitfld.long 0x00 16. " GMB368 ,Group Modifier Bit 368" "0,1" bitfld.long 0x00 15. " GMB367 ,Group Modifier Bit 367" "0,1" bitfld.long 0x00 14. " GMB366 ,Group Modifier Bit 366" "0,1" textline " " bitfld.long 0x00 13. " GMB365 ,Group Modifier Bit 365" "0,1" bitfld.long 0x00 12. " GMB364 ,Group Modifier Bit 364" "0,1" bitfld.long 0x00 11. " GMB363 ,Group Modifier Bit 363" "0,1" textline " " bitfld.long 0x00 10. " GMB362 ,Group Modifier Bit 362" "0,1" bitfld.long 0x00 9. " GMB361 ,Group Modifier Bit 361" "0,1" bitfld.long 0x00 8. " GMB360 ,Group Modifier Bit 360" "0,1" textline " " bitfld.long 0x00 7. " GMB359 ,Group Modifier Bit 359" "0,1" bitfld.long 0x00 6. " GMB358 ,Group Modifier Bit 358" "0,1" bitfld.long 0x00 5. " GMB357 ,Group Modifier Bit 357" "0,1" textline " " bitfld.long 0x00 4. " GMB356 ,Group Modifier Bit 356" "0,1" bitfld.long 0x00 3. " GMB355 ,Group Modifier Bit 355" "0,1" bitfld.long 0x00 2. " GMB354 ,Group Modifier Bit 354" "0,1" textline " " bitfld.long 0x00 1. " GMB353 ,Group Modifier Bit 353" "0,1" bitfld.long 0x00 0. " GMB352 ,Group Modifier Bit 352" "0,1" else hgroup.long 0x0D2C++0x03 hide.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D30))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)) group.long 0x0D30++0x03 line.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12" bitfld.long 0x00 31. " GMB415 ,Group Modifier Bit 415" "0,1" bitfld.long 0x00 30. " GMB414 ,Group Modifier Bit 414" "0,1" bitfld.long 0x00 29. " GMB413 ,Group Modifier Bit 413" "0,1" textline " " bitfld.long 0x00 28. " GMB412 ,Group Modifier Bit 412" "0,1" bitfld.long 0x00 27. " GMB411 ,Group Modifier Bit 411" "0,1" bitfld.long 0x00 26. " GMB410 ,Group Modifier Bit 410" "0,1" textline " " bitfld.long 0x00 25. " GMB409 ,Group Modifier Bit 409" "0,1" bitfld.long 0x00 24. " GMB408 ,Group Modifier Bit 408" "0,1" bitfld.long 0x00 23. " GMB407 ,Group Modifier Bit 407" "0,1" textline " " bitfld.long 0x00 22. " GMB406 ,Group Modifier Bit 406" "0,1" bitfld.long 0x00 21. " GMB405 ,Group Modifier Bit 405" "0,1" bitfld.long 0x00 20. " GMB404 ,Group Modifier Bit 404" "0,1" textline " " bitfld.long 0x00 19. " GMB403 ,Group Modifier Bit 403" "0,1" bitfld.long 0x00 18. " GMB402 ,Group Modifier Bit 402" "0,1" bitfld.long 0x00 17. " GMB401 ,Group Modifier Bit 401" "0,1" textline " " bitfld.long 0x00 16. " GMB400 ,Group Modifier Bit 400" "0,1" bitfld.long 0x00 15. " GMB399 ,Group Modifier Bit 399" "0,1" bitfld.long 0x00 14. " GMB398 ,Group Modifier Bit 398" "0,1" textline " " bitfld.long 0x00 13. " GMB397 ,Group Modifier Bit 397" "0,1" bitfld.long 0x00 12. " GMB396 ,Group Modifier Bit 396" "0,1" bitfld.long 0x00 11. " GMB395 ,Group Modifier Bit 395" "0,1" textline " " bitfld.long 0x00 10. " GMB394 ,Group Modifier Bit 394" "0,1" bitfld.long 0x00 9. " GMB393 ,Group Modifier Bit 393" "0,1" bitfld.long 0x00 8. " GMB392 ,Group Modifier Bit 392" "0,1" textline " " bitfld.long 0x00 7. " GMB391 ,Group Modifier Bit 391" "0,1" bitfld.long 0x00 6. " GMB390 ,Group Modifier Bit 390" "0,1" bitfld.long 0x00 5. " GMB389 ,Group Modifier Bit 389" "0,1" textline " " bitfld.long 0x00 4. " GMB388 ,Group Modifier Bit 388" "0,1" bitfld.long 0x00 3. " GMB387 ,Group Modifier Bit 387" "0,1" bitfld.long 0x00 2. " GMB386 ,Group Modifier Bit 386" "0,1" textline " " bitfld.long 0x00 1. " GMB385 ,Group Modifier Bit 385" "0,1" bitfld.long 0x00 0. " GMB384 ,Group Modifier Bit 384" "0,1" else hgroup.long 0x0D30++0x03 hide.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D34))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)) group.long 0x0D34++0x03 line.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13" bitfld.long 0x00 31. " GMB447 ,Group Modifier Bit 447" "0,1" bitfld.long 0x00 30. " GMB446 ,Group Modifier Bit 446" "0,1" bitfld.long 0x00 29. " GMB445 ,Group Modifier Bit 445" "0,1" textline " " bitfld.long 0x00 28. " GMB444 ,Group Modifier Bit 444" "0,1" bitfld.long 0x00 27. " GMB443 ,Group Modifier Bit 443" "0,1" bitfld.long 0x00 26. " GMB442 ,Group Modifier Bit 442" "0,1" textline " " bitfld.long 0x00 25. " GMB441 ,Group Modifier Bit 441" "0,1" bitfld.long 0x00 24. " GMB440 ,Group Modifier Bit 440" "0,1" bitfld.long 0x00 23. " GMB439 ,Group Modifier Bit 439" "0,1" textline " " bitfld.long 0x00 22. " GMB438 ,Group Modifier Bit 438" "0,1" bitfld.long 0x00 21. " GMB437 ,Group Modifier Bit 437" "0,1" bitfld.long 0x00 20. " GMB436 ,Group Modifier Bit 436" "0,1" textline " " bitfld.long 0x00 19. " GMB435 ,Group Modifier Bit 435" "0,1" bitfld.long 0x00 18. " GMB434 ,Group Modifier Bit 434" "0,1" bitfld.long 0x00 17. " GMB433 ,Group Modifier Bit 433" "0,1" textline " " bitfld.long 0x00 16. " GMB432 ,Group Modifier Bit 432" "0,1" bitfld.long 0x00 15. " GMB431 ,Group Modifier Bit 431" "0,1" bitfld.long 0x00 14. " GMB430 ,Group Modifier Bit 430" "0,1" textline " " bitfld.long 0x00 13. " GMB429 ,Group Modifier Bit 429" "0,1" bitfld.long 0x00 12. " GMB428 ,Group Modifier Bit 428" "0,1" bitfld.long 0x00 11. " GMB427 ,Group Modifier Bit 427" "0,1" textline " " bitfld.long 0x00 10. " GMB426 ,Group Modifier Bit 426" "0,1" bitfld.long 0x00 9. " GMB425 ,Group Modifier Bit 425" "0,1" bitfld.long 0x00 8. " GMB424 ,Group Modifier Bit 424" "0,1" textline " " bitfld.long 0x00 7. " GMB423 ,Group Modifier Bit 423" "0,1" bitfld.long 0x00 6. " GMB422 ,Group Modifier Bit 422" "0,1" bitfld.long 0x00 5. " GMB421 ,Group Modifier Bit 421" "0,1" textline " " bitfld.long 0x00 4. " GMB420 ,Group Modifier Bit 420" "0,1" bitfld.long 0x00 3. " GMB419 ,Group Modifier Bit 419" "0,1" bitfld.long 0x00 2. " GMB418 ,Group Modifier Bit 418" "0,1" textline " " bitfld.long 0x00 1. " GMB417 ,Group Modifier Bit 417" "0,1" bitfld.long 0x00 0. " GMB416 ,Group Modifier Bit 416" "0,1" else hgroup.long 0x0D34++0x03 hide.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D38))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)) group.long 0x0D38++0x03 line.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14" bitfld.long 0x00 31. " GMB479 ,Group Modifier Bit 479" "0,1" bitfld.long 0x00 30. " GMB478 ,Group Modifier Bit 478" "0,1" bitfld.long 0x00 29. " GMB477 ,Group Modifier Bit 477" "0,1" textline " " bitfld.long 0x00 28. " GMB476 ,Group Modifier Bit 476" "0,1" bitfld.long 0x00 27. " GMB475 ,Group Modifier Bit 475" "0,1" bitfld.long 0x00 26. " GMB474 ,Group Modifier Bit 474" "0,1" textline " " bitfld.long 0x00 25. " GMB473 ,Group Modifier Bit 473" "0,1" bitfld.long 0x00 24. " GMB472 ,Group Modifier Bit 472" "0,1" bitfld.long 0x00 23. " GMB471 ,Group Modifier Bit 471" "0,1" textline " " bitfld.long 0x00 22. " GMB470 ,Group Modifier Bit 470" "0,1" bitfld.long 0x00 21. " GMB469 ,Group Modifier Bit 469" "0,1" bitfld.long 0x00 20. " GMB468 ,Group Modifier Bit 468" "0,1" textline " " bitfld.long 0x00 19. " GMB467 ,Group Modifier Bit 467" "0,1" bitfld.long 0x00 18. " GMB466 ,Group Modifier Bit 466" "0,1" bitfld.long 0x00 17. " GMB465 ,Group Modifier Bit 465" "0,1" textline " " bitfld.long 0x00 16. " GMB464 ,Group Modifier Bit 464" "0,1" bitfld.long 0x00 15. " GMB463 ,Group Modifier Bit 463" "0,1" bitfld.long 0x00 14. " GMB462 ,Group Modifier Bit 462" "0,1" textline " " bitfld.long 0x00 13. " GMB461 ,Group Modifier Bit 461" "0,1" bitfld.long 0x00 12. " GMB460 ,Group Modifier Bit 460" "0,1" bitfld.long 0x00 11. " GMB459 ,Group Modifier Bit 459" "0,1" textline " " bitfld.long 0x00 10. " GMB458 ,Group Modifier Bit 458" "0,1" bitfld.long 0x00 9. " GMB457 ,Group Modifier Bit 457" "0,1" bitfld.long 0x00 8. " GMB456 ,Group Modifier Bit 456" "0,1" textline " " bitfld.long 0x00 7. " GMB455 ,Group Modifier Bit 455" "0,1" bitfld.long 0x00 6. " GMB454 ,Group Modifier Bit 454" "0,1" bitfld.long 0x00 5. " GMB453 ,Group Modifier Bit 453" "0,1" textline " " bitfld.long 0x00 4. " GMB452 ,Group Modifier Bit 452" "0,1" bitfld.long 0x00 3. " GMB451 ,Group Modifier Bit 451" "0,1" bitfld.long 0x00 2. " GMB450 ,Group Modifier Bit 450" "0,1" textline " " bitfld.long 0x00 1. " GMB449 ,Group Modifier Bit 449" "0,1" bitfld.long 0x00 0. " GMB448 ,Group Modifier Bit 448" "0,1" else hgroup.long 0x0D38++0x03 hide.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D3C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)) group.long 0x0D3C++0x03 line.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15" bitfld.long 0x00 31. " GMB511 ,Group Modifier Bit 511" "0,1" bitfld.long 0x00 30. " GMB510 ,Group Modifier Bit 510" "0,1" bitfld.long 0x00 29. " GMB509 ,Group Modifier Bit 509" "0,1" textline " " bitfld.long 0x00 28. " GMB508 ,Group Modifier Bit 508" "0,1" bitfld.long 0x00 27. " GMB507 ,Group Modifier Bit 507" "0,1" bitfld.long 0x00 26. " GMB506 ,Group Modifier Bit 506" "0,1" textline " " bitfld.long 0x00 25. " GMB505 ,Group Modifier Bit 505" "0,1" bitfld.long 0x00 24. " GMB504 ,Group Modifier Bit 504" "0,1" bitfld.long 0x00 23. " GMB503 ,Group Modifier Bit 503" "0,1" textline " " bitfld.long 0x00 22. " GMB502 ,Group Modifier Bit 502" "0,1" bitfld.long 0x00 21. " GMB501 ,Group Modifier Bit 501" "0,1" bitfld.long 0x00 20. " GMB500 ,Group Modifier Bit 500" "0,1" textline " " bitfld.long 0x00 19. " GMB499 ,Group Modifier Bit 499" "0,1" bitfld.long 0x00 18. " GMB498 ,Group Modifier Bit 498" "0,1" bitfld.long 0x00 17. " GMB497 ,Group Modifier Bit 497" "0,1" textline " " bitfld.long 0x00 16. " GMB496 ,Group Modifier Bit 496" "0,1" bitfld.long 0x00 15. " GMB495 ,Group Modifier Bit 495" "0,1" bitfld.long 0x00 14. " GMB494 ,Group Modifier Bit 494" "0,1" textline " " bitfld.long 0x00 13. " GMB493 ,Group Modifier Bit 493" "0,1" bitfld.long 0x00 12. " GMB492 ,Group Modifier Bit 492" "0,1" bitfld.long 0x00 11. " GMB491 ,Group Modifier Bit 491" "0,1" textline " " bitfld.long 0x00 10. " GMB490 ,Group Modifier Bit 490" "0,1" bitfld.long 0x00 9. " GMB489 ,Group Modifier Bit 489" "0,1" bitfld.long 0x00 8. " GMB488 ,Group Modifier Bit 488" "0,1" textline " " bitfld.long 0x00 7. " GMB487 ,Group Modifier Bit 487" "0,1" bitfld.long 0x00 6. " GMB486 ,Group Modifier Bit 486" "0,1" bitfld.long 0x00 5. " GMB485 ,Group Modifier Bit 485" "0,1" textline " " bitfld.long 0x00 4. " GMB484 ,Group Modifier Bit 484" "0,1" bitfld.long 0x00 3. " GMB483 ,Group Modifier Bit 483" "0,1" bitfld.long 0x00 2. " GMB482 ,Group Modifier Bit 482" "0,1" textline " " bitfld.long 0x00 1. " GMB481 ,Group Modifier Bit 481" "0,1" bitfld.long 0x00 0. " GMB480 ,Group Modifier Bit 480" "0,1" else hgroup.long 0x0D3C++0x03 hide.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D40))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x0D40++0x03 line.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16" bitfld.long 0x00 31. " GMB543 ,Group Modifier Bit 543" "0,1" bitfld.long 0x00 30. " GMB542 ,Group Modifier Bit 542" "0,1" bitfld.long 0x00 29. " GMB541 ,Group Modifier Bit 541" "0,1" textline " " bitfld.long 0x00 28. " GMB540 ,Group Modifier Bit 540" "0,1" bitfld.long 0x00 27. " GMB539 ,Group Modifier Bit 539" "0,1" bitfld.long 0x00 26. " GMB538 ,Group Modifier Bit 538" "0,1" textline " " bitfld.long 0x00 25. " GMB537 ,Group Modifier Bit 537" "0,1" bitfld.long 0x00 24. " GMB536 ,Group Modifier Bit 536" "0,1" bitfld.long 0x00 23. " GMB535 ,Group Modifier Bit 535" "0,1" textline " " bitfld.long 0x00 22. " GMB534 ,Group Modifier Bit 534" "0,1" bitfld.long 0x00 21. " GMB533 ,Group Modifier Bit 533" "0,1" bitfld.long 0x00 20. " GMB532 ,Group Modifier Bit 532" "0,1" textline " " bitfld.long 0x00 19. " GMB531 ,Group Modifier Bit 531" "0,1" bitfld.long 0x00 18. " GMB530 ,Group Modifier Bit 530" "0,1" bitfld.long 0x00 17. " GMB529 ,Group Modifier Bit 529" "0,1" textline " " bitfld.long 0x00 16. " GMB528 ,Group Modifier Bit 528" "0,1" bitfld.long 0x00 15. " GMB527 ,Group Modifier Bit 527" "0,1" bitfld.long 0x00 14. " GMB526 ,Group Modifier Bit 526" "0,1" textline " " bitfld.long 0x00 13. " GMB525 ,Group Modifier Bit 525" "0,1" bitfld.long 0x00 12. " GMB524 ,Group Modifier Bit 524" "0,1" bitfld.long 0x00 11. " GMB523 ,Group Modifier Bit 523" "0,1" textline " " bitfld.long 0x00 10. " GMB522 ,Group Modifier Bit 522" "0,1" bitfld.long 0x00 9. " GMB521 ,Group Modifier Bit 521" "0,1" bitfld.long 0x00 8. " GMB520 ,Group Modifier Bit 520" "0,1" textline " " bitfld.long 0x00 7. " GMB519 ,Group Modifier Bit 519" "0,1" bitfld.long 0x00 6. " GMB518 ,Group Modifier Bit 518" "0,1" bitfld.long 0x00 5. " GMB517 ,Group Modifier Bit 517" "0,1" textline " " bitfld.long 0x00 4. " GMB516 ,Group Modifier Bit 516" "0,1" bitfld.long 0x00 3. " GMB515 ,Group Modifier Bit 515" "0,1" bitfld.long 0x00 2. " GMB514 ,Group Modifier Bit 514" "0,1" textline " " bitfld.long 0x00 1. " GMB513 ,Group Modifier Bit 513" "0,1" bitfld.long 0x00 0. " GMB512 ,Group Modifier Bit 512" "0,1" else hgroup.long 0x0D40++0x03 hide.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D44))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x0D44++0x03 line.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17" bitfld.long 0x00 31. " GMB575 ,Group Modifier Bit 575" "0,1" bitfld.long 0x00 30. " GMB574 ,Group Modifier Bit 574" "0,1" bitfld.long 0x00 29. " GMB573 ,Group Modifier Bit 573" "0,1" textline " " bitfld.long 0x00 28. " GMB572 ,Group Modifier Bit 572" "0,1" bitfld.long 0x00 27. " GMB571 ,Group Modifier Bit 571" "0,1" bitfld.long 0x00 26. " GMB570 ,Group Modifier Bit 570" "0,1" textline " " bitfld.long 0x00 25. " GMB569 ,Group Modifier Bit 569" "0,1" bitfld.long 0x00 24. " GMB568 ,Group Modifier Bit 568" "0,1" bitfld.long 0x00 23. " GMB567 ,Group Modifier Bit 567" "0,1" textline " " bitfld.long 0x00 22. " GMB566 ,Group Modifier Bit 566" "0,1" bitfld.long 0x00 21. " GMB565 ,Group Modifier Bit 565" "0,1" bitfld.long 0x00 20. " GMB564 ,Group Modifier Bit 564" "0,1" textline " " bitfld.long 0x00 19. " GMB563 ,Group Modifier Bit 563" "0,1" bitfld.long 0x00 18. " GMB562 ,Group Modifier Bit 562" "0,1" bitfld.long 0x00 17. " GMB561 ,Group Modifier Bit 561" "0,1" textline " " bitfld.long 0x00 16. " GMB560 ,Group Modifier Bit 560" "0,1" bitfld.long 0x00 15. " GMB559 ,Group Modifier Bit 559" "0,1" bitfld.long 0x00 14. " GMB558 ,Group Modifier Bit 558" "0,1" textline " " bitfld.long 0x00 13. " GMB557 ,Group Modifier Bit 557" "0,1" bitfld.long 0x00 12. " GMB556 ,Group Modifier Bit 556" "0,1" bitfld.long 0x00 11. " GMB555 ,Group Modifier Bit 555" "0,1" textline " " bitfld.long 0x00 10. " GMB554 ,Group Modifier Bit 554" "0,1" bitfld.long 0x00 9. " GMB553 ,Group Modifier Bit 553" "0,1" bitfld.long 0x00 8. " GMB552 ,Group Modifier Bit 552" "0,1" textline " " bitfld.long 0x00 7. " GMB551 ,Group Modifier Bit 551" "0,1" bitfld.long 0x00 6. " GMB550 ,Group Modifier Bit 550" "0,1" bitfld.long 0x00 5. " GMB549 ,Group Modifier Bit 549" "0,1" textline " " bitfld.long 0x00 4. " GMB548 ,Group Modifier Bit 548" "0,1" bitfld.long 0x00 3. " GMB547 ,Group Modifier Bit 547" "0,1" bitfld.long 0x00 2. " GMB546 ,Group Modifier Bit 546" "0,1" textline " " bitfld.long 0x00 1. " GMB545 ,Group Modifier Bit 545" "0,1" bitfld.long 0x00 0. " GMB544 ,Group Modifier Bit 544" "0,1" else hgroup.long 0x0D44++0x03 hide.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D48))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x0D48++0x03 line.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18" bitfld.long 0x00 31. " GMB607 ,Group Modifier Bit 607" "0,1" bitfld.long 0x00 30. " GMB606 ,Group Modifier Bit 606" "0,1" bitfld.long 0x00 29. " GMB605 ,Group Modifier Bit 605" "0,1" textline " " bitfld.long 0x00 28. " GMB604 ,Group Modifier Bit 604" "0,1" bitfld.long 0x00 27. " GMB603 ,Group Modifier Bit 603" "0,1" bitfld.long 0x00 26. " GMB602 ,Group Modifier Bit 602" "0,1" textline " " bitfld.long 0x00 25. " GMB601 ,Group Modifier Bit 601" "0,1" bitfld.long 0x00 24. " GMB600 ,Group Modifier Bit 600" "0,1" bitfld.long 0x00 23. " GMB599 ,Group Modifier Bit 599" "0,1" textline " " bitfld.long 0x00 22. " GMB598 ,Group Modifier Bit 598" "0,1" bitfld.long 0x00 21. " GMB597 ,Group Modifier Bit 597" "0,1" bitfld.long 0x00 20. " GMB596 ,Group Modifier Bit 596" "0,1" textline " " bitfld.long 0x00 19. " GMB595 ,Group Modifier Bit 595" "0,1" bitfld.long 0x00 18. " GMB594 ,Group Modifier Bit 594" "0,1" bitfld.long 0x00 17. " GMB593 ,Group Modifier Bit 593" "0,1" textline " " bitfld.long 0x00 16. " GMB592 ,Group Modifier Bit 592" "0,1" bitfld.long 0x00 15. " GMB591 ,Group Modifier Bit 591" "0,1" bitfld.long 0x00 14. " GMB590 ,Group Modifier Bit 590" "0,1" textline " " bitfld.long 0x00 13. " GMB589 ,Group Modifier Bit 589" "0,1" bitfld.long 0x00 12. " GMB588 ,Group Modifier Bit 588" "0,1" bitfld.long 0x00 11. " GMB587 ,Group Modifier Bit 587" "0,1" textline " " bitfld.long 0x00 10. " GMB586 ,Group Modifier Bit 586" "0,1" bitfld.long 0x00 9. " GMB585 ,Group Modifier Bit 585" "0,1" bitfld.long 0x00 8. " GMB584 ,Group Modifier Bit 584" "0,1" textline " " bitfld.long 0x00 7. " GMB583 ,Group Modifier Bit 583" "0,1" bitfld.long 0x00 6. " GMB582 ,Group Modifier Bit 582" "0,1" bitfld.long 0x00 5. " GMB581 ,Group Modifier Bit 581" "0,1" textline " " bitfld.long 0x00 4. " GMB580 ,Group Modifier Bit 580" "0,1" bitfld.long 0x00 3. " GMB579 ,Group Modifier Bit 579" "0,1" bitfld.long 0x00 2. " GMB578 ,Group Modifier Bit 578" "0,1" textline " " bitfld.long 0x00 1. " GMB577 ,Group Modifier Bit 577" "0,1" bitfld.long 0x00 0. " GMB576 ,Group Modifier Bit 576" "0,1" else hgroup.long 0x0D48++0x03 hide.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D4C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x0D4C++0x03 line.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19" bitfld.long 0x00 31. " GMB639 ,Group Modifier Bit 639" "0,1" bitfld.long 0x00 30. " GMB638 ,Group Modifier Bit 638" "0,1" bitfld.long 0x00 29. " GMB637 ,Group Modifier Bit 637" "0,1" textline " " bitfld.long 0x00 28. " GMB636 ,Group Modifier Bit 636" "0,1" bitfld.long 0x00 27. " GMB635 ,Group Modifier Bit 635" "0,1" bitfld.long 0x00 26. " GMB634 ,Group Modifier Bit 634" "0,1" textline " " bitfld.long 0x00 25. " GMB633 ,Group Modifier Bit 633" "0,1" bitfld.long 0x00 24. " GMB632 ,Group Modifier Bit 632" "0,1" bitfld.long 0x00 23. " GMB631 ,Group Modifier Bit 631" "0,1" textline " " bitfld.long 0x00 22. " GMB630 ,Group Modifier Bit 630" "0,1" bitfld.long 0x00 21. " GMB629 ,Group Modifier Bit 629" "0,1" bitfld.long 0x00 20. " GMB628 ,Group Modifier Bit 628" "0,1" textline " " bitfld.long 0x00 19. " GMB627 ,Group Modifier Bit 627" "0,1" bitfld.long 0x00 18. " GMB626 ,Group Modifier Bit 626" "0,1" bitfld.long 0x00 17. " GMB625 ,Group Modifier Bit 625" "0,1" textline " " bitfld.long 0x00 16. " GMB624 ,Group Modifier Bit 624" "0,1" bitfld.long 0x00 15. " GMB623 ,Group Modifier Bit 623" "0,1" bitfld.long 0x00 14. " GMB622 ,Group Modifier Bit 622" "0,1" textline " " bitfld.long 0x00 13. " GMB621 ,Group Modifier Bit 621" "0,1" bitfld.long 0x00 12. " GMB620 ,Group Modifier Bit 620" "0,1" bitfld.long 0x00 11. " GMB619 ,Group Modifier Bit 619" "0,1" textline " " bitfld.long 0x00 10. " GMB618 ,Group Modifier Bit 618" "0,1" bitfld.long 0x00 9. " GMB617 ,Group Modifier Bit 617" "0,1" bitfld.long 0x00 8. " GMB616 ,Group Modifier Bit 616" "0,1" textline " " bitfld.long 0x00 7. " GMB615 ,Group Modifier Bit 615" "0,1" bitfld.long 0x00 6. " GMB614 ,Group Modifier Bit 614" "0,1" bitfld.long 0x00 5. " GMB613 ,Group Modifier Bit 613" "0,1" textline " " bitfld.long 0x00 4. " GMB612 ,Group Modifier Bit 612" "0,1" bitfld.long 0x00 3. " GMB611 ,Group Modifier Bit 611" "0,1" bitfld.long 0x00 2. " GMB610 ,Group Modifier Bit 610" "0,1" textline " " bitfld.long 0x00 1. " GMB609 ,Group Modifier Bit 609" "0,1" bitfld.long 0x00 0. " GMB608 ,Group Modifier Bit 608" "0,1" else hgroup.long 0x0D4C++0x03 hide.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D50))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x0D50++0x03 line.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20" bitfld.long 0x00 31. " GMB671 ,Group Modifier Bit 671" "0,1" bitfld.long 0x00 30. " GMB670 ,Group Modifier Bit 670" "0,1" bitfld.long 0x00 29. " GMB669 ,Group Modifier Bit 669" "0,1" textline " " bitfld.long 0x00 28. " GMB668 ,Group Modifier Bit 668" "0,1" bitfld.long 0x00 27. " GMB667 ,Group Modifier Bit 667" "0,1" bitfld.long 0x00 26. " GMB666 ,Group Modifier Bit 666" "0,1" textline " " bitfld.long 0x00 25. " GMB665 ,Group Modifier Bit 665" "0,1" bitfld.long 0x00 24. " GMB664 ,Group Modifier Bit 664" "0,1" bitfld.long 0x00 23. " GMB663 ,Group Modifier Bit 663" "0,1" textline " " bitfld.long 0x00 22. " GMB662 ,Group Modifier Bit 662" "0,1" bitfld.long 0x00 21. " GMB661 ,Group Modifier Bit 661" "0,1" bitfld.long 0x00 20. " GMB660 ,Group Modifier Bit 660" "0,1" textline " " bitfld.long 0x00 19. " GMB659 ,Group Modifier Bit 659" "0,1" bitfld.long 0x00 18. " GMB658 ,Group Modifier Bit 658" "0,1" bitfld.long 0x00 17. " GMB657 ,Group Modifier Bit 657" "0,1" textline " " bitfld.long 0x00 16. " GMB656 ,Group Modifier Bit 656" "0,1" bitfld.long 0x00 15. " GMB655 ,Group Modifier Bit 655" "0,1" bitfld.long 0x00 14. " GMB654 ,Group Modifier Bit 654" "0,1" textline " " bitfld.long 0x00 13. " GMB653 ,Group Modifier Bit 653" "0,1" bitfld.long 0x00 12. " GMB652 ,Group Modifier Bit 652" "0,1" bitfld.long 0x00 11. " GMB651 ,Group Modifier Bit 651" "0,1" textline " " bitfld.long 0x00 10. " GMB650 ,Group Modifier Bit 650" "0,1" bitfld.long 0x00 9. " GMB649 ,Group Modifier Bit 649" "0,1" bitfld.long 0x00 8. " GMB648 ,Group Modifier Bit 648" "0,1" textline " " bitfld.long 0x00 7. " GMB647 ,Group Modifier Bit 647" "0,1" bitfld.long 0x00 6. " GMB646 ,Group Modifier Bit 646" "0,1" bitfld.long 0x00 5. " GMB645 ,Group Modifier Bit 645" "0,1" textline " " bitfld.long 0x00 4. " GMB644 ,Group Modifier Bit 644" "0,1" bitfld.long 0x00 3. " GMB643 ,Group Modifier Bit 643" "0,1" bitfld.long 0x00 2. " GMB642 ,Group Modifier Bit 642" "0,1" textline " " bitfld.long 0x00 1. " GMB641 ,Group Modifier Bit 641" "0,1" bitfld.long 0x00 0. " GMB640 ,Group Modifier Bit 640" "0,1" else hgroup.long 0x0D50++0x03 hide.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D54))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x0D54++0x03 line.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21" bitfld.long 0x00 31. " GMB703 ,Group Modifier Bit 703" "0,1" bitfld.long 0x00 30. " GMB702 ,Group Modifier Bit 702" "0,1" bitfld.long 0x00 29. " GMB701 ,Group Modifier Bit 701" "0,1" textline " " bitfld.long 0x00 28. " GMB700 ,Group Modifier Bit 700" "0,1" bitfld.long 0x00 27. " GMB699 ,Group Modifier Bit 699" "0,1" bitfld.long 0x00 26. " GMB698 ,Group Modifier Bit 698" "0,1" textline " " bitfld.long 0x00 25. " GMB697 ,Group Modifier Bit 697" "0,1" bitfld.long 0x00 24. " GMB696 ,Group Modifier Bit 696" "0,1" bitfld.long 0x00 23. " GMB695 ,Group Modifier Bit 695" "0,1" textline " " bitfld.long 0x00 22. " GMB694 ,Group Modifier Bit 694" "0,1" bitfld.long 0x00 21. " GMB693 ,Group Modifier Bit 693" "0,1" bitfld.long 0x00 20. " GMB692 ,Group Modifier Bit 692" "0,1" textline " " bitfld.long 0x00 19. " GMB691 ,Group Modifier Bit 691" "0,1" bitfld.long 0x00 18. " GMB690 ,Group Modifier Bit 690" "0,1" bitfld.long 0x00 17. " GMB689 ,Group Modifier Bit 689" "0,1" textline " " bitfld.long 0x00 16. " GMB688 ,Group Modifier Bit 688" "0,1" bitfld.long 0x00 15. " GMB687 ,Group Modifier Bit 687" "0,1" bitfld.long 0x00 14. " GMB686 ,Group Modifier Bit 686" "0,1" textline " " bitfld.long 0x00 13. " GMB685 ,Group Modifier Bit 685" "0,1" bitfld.long 0x00 12. " GMB684 ,Group Modifier Bit 684" "0,1" bitfld.long 0x00 11. " GMB683 ,Group Modifier Bit 683" "0,1" textline " " bitfld.long 0x00 10. " GMB682 ,Group Modifier Bit 682" "0,1" bitfld.long 0x00 9. " GMB681 ,Group Modifier Bit 681" "0,1" bitfld.long 0x00 8. " GMB680 ,Group Modifier Bit 680" "0,1" textline " " bitfld.long 0x00 7. " GMB679 ,Group Modifier Bit 679" "0,1" bitfld.long 0x00 6. " GMB678 ,Group Modifier Bit 678" "0,1" bitfld.long 0x00 5. " GMB677 ,Group Modifier Bit 677" "0,1" textline " " bitfld.long 0x00 4. " GMB676 ,Group Modifier Bit 676" "0,1" bitfld.long 0x00 3. " GMB675 ,Group Modifier Bit 675" "0,1" bitfld.long 0x00 2. " GMB674 ,Group Modifier Bit 674" "0,1" textline " " bitfld.long 0x00 1. " GMB673 ,Group Modifier Bit 673" "0,1" bitfld.long 0x00 0. " GMB672 ,Group Modifier Bit 672" "0,1" else hgroup.long 0x0D54++0x03 hide.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D58))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x0D58++0x03 line.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22" bitfld.long 0x00 31. " GMB735 ,Group Modifier Bit 735" "0,1" bitfld.long 0x00 30. " GMB734 ,Group Modifier Bit 734" "0,1" bitfld.long 0x00 29. " GMB733 ,Group Modifier Bit 733" "0,1" textline " " bitfld.long 0x00 28. " GMB732 ,Group Modifier Bit 732" "0,1" bitfld.long 0x00 27. " GMB731 ,Group Modifier Bit 731" "0,1" bitfld.long 0x00 26. " GMB730 ,Group Modifier Bit 730" "0,1" textline " " bitfld.long 0x00 25. " GMB729 ,Group Modifier Bit 729" "0,1" bitfld.long 0x00 24. " GMB728 ,Group Modifier Bit 728" "0,1" bitfld.long 0x00 23. " GMB727 ,Group Modifier Bit 727" "0,1" textline " " bitfld.long 0x00 22. " GMB726 ,Group Modifier Bit 726" "0,1" bitfld.long 0x00 21. " GMB725 ,Group Modifier Bit 725" "0,1" bitfld.long 0x00 20. " GMB724 ,Group Modifier Bit 724" "0,1" textline " " bitfld.long 0x00 19. " GMB723 ,Group Modifier Bit 723" "0,1" bitfld.long 0x00 18. " GMB722 ,Group Modifier Bit 722" "0,1" bitfld.long 0x00 17. " GMB721 ,Group Modifier Bit 721" "0,1" textline " " bitfld.long 0x00 16. " GMB720 ,Group Modifier Bit 720" "0,1" bitfld.long 0x00 15. " GMB719 ,Group Modifier Bit 719" "0,1" bitfld.long 0x00 14. " GMB718 ,Group Modifier Bit 718" "0,1" textline " " bitfld.long 0x00 13. " GMB717 ,Group Modifier Bit 717" "0,1" bitfld.long 0x00 12. " GMB716 ,Group Modifier Bit 716" "0,1" bitfld.long 0x00 11. " GMB715 ,Group Modifier Bit 715" "0,1" textline " " bitfld.long 0x00 10. " GMB714 ,Group Modifier Bit 714" "0,1" bitfld.long 0x00 9. " GMB713 ,Group Modifier Bit 713" "0,1" bitfld.long 0x00 8. " GMB712 ,Group Modifier Bit 712" "0,1" textline " " bitfld.long 0x00 7. " GMB711 ,Group Modifier Bit 711" "0,1" bitfld.long 0x00 6. " GMB710 ,Group Modifier Bit 710" "0,1" bitfld.long 0x00 5. " GMB709 ,Group Modifier Bit 709" "0,1" textline " " bitfld.long 0x00 4. " GMB708 ,Group Modifier Bit 708" "0,1" bitfld.long 0x00 3. " GMB707 ,Group Modifier Bit 707" "0,1" bitfld.long 0x00 2. " GMB706 ,Group Modifier Bit 706" "0,1" textline " " bitfld.long 0x00 1. " GMB705 ,Group Modifier Bit 705" "0,1" bitfld.long 0x00 0. " GMB704 ,Group Modifier Bit 704" "0,1" else hgroup.long 0x0D58++0x03 hide.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D5C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x0D5C++0x03 line.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23" bitfld.long 0x00 31. " GMB767 ,Group Modifier Bit 767" "0,1" bitfld.long 0x00 30. " GMB766 ,Group Modifier Bit 766" "0,1" bitfld.long 0x00 29. " GMB765 ,Group Modifier Bit 765" "0,1" textline " " bitfld.long 0x00 28. " GMB764 ,Group Modifier Bit 764" "0,1" bitfld.long 0x00 27. " GMB763 ,Group Modifier Bit 763" "0,1" bitfld.long 0x00 26. " GMB762 ,Group Modifier Bit 762" "0,1" textline " " bitfld.long 0x00 25. " GMB761 ,Group Modifier Bit 761" "0,1" bitfld.long 0x00 24. " GMB760 ,Group Modifier Bit 760" "0,1" bitfld.long 0x00 23. " GMB759 ,Group Modifier Bit 759" "0,1" textline " " bitfld.long 0x00 22. " GMB758 ,Group Modifier Bit 758" "0,1" bitfld.long 0x00 21. " GMB757 ,Group Modifier Bit 757" "0,1" bitfld.long 0x00 20. " GMB756 ,Group Modifier Bit 756" "0,1" textline " " bitfld.long 0x00 19. " GMB755 ,Group Modifier Bit 755" "0,1" bitfld.long 0x00 18. " GMB754 ,Group Modifier Bit 754" "0,1" bitfld.long 0x00 17. " GMB753 ,Group Modifier Bit 753" "0,1" textline " " bitfld.long 0x00 16. " GMB752 ,Group Modifier Bit 752" "0,1" bitfld.long 0x00 15. " GMB751 ,Group Modifier Bit 751" "0,1" bitfld.long 0x00 14. " GMB750 ,Group Modifier Bit 750" "0,1" textline " " bitfld.long 0x00 13. " GMB749 ,Group Modifier Bit 749" "0,1" bitfld.long 0x00 12. " GMB748 ,Group Modifier Bit 748" "0,1" bitfld.long 0x00 11. " GMB747 ,Group Modifier Bit 747" "0,1" textline " " bitfld.long 0x00 10. " GMB746 ,Group Modifier Bit 746" "0,1" bitfld.long 0x00 9. " GMB745 ,Group Modifier Bit 745" "0,1" bitfld.long 0x00 8. " GMB744 ,Group Modifier Bit 744" "0,1" textline " " bitfld.long 0x00 7. " GMB743 ,Group Modifier Bit 743" "0,1" bitfld.long 0x00 6. " GMB742 ,Group Modifier Bit 742" "0,1" bitfld.long 0x00 5. " GMB741 ,Group Modifier Bit 741" "0,1" textline " " bitfld.long 0x00 4. " GMB740 ,Group Modifier Bit 740" "0,1" bitfld.long 0x00 3. " GMB739 ,Group Modifier Bit 739" "0,1" bitfld.long 0x00 2. " GMB738 ,Group Modifier Bit 738" "0,1" textline " " bitfld.long 0x00 1. " GMB737 ,Group Modifier Bit 737" "0,1" bitfld.long 0x00 0. " GMB736 ,Group Modifier Bit 736" "0,1" else hgroup.long 0x0D5C++0x03 hide.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D60))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x0D60++0x03 line.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24" bitfld.long 0x00 31. " GMB799 ,Group Modifier Bit 799" "0,1" bitfld.long 0x00 30. " GMB798 ,Group Modifier Bit 798" "0,1" bitfld.long 0x00 29. " GMB797 ,Group Modifier Bit 797" "0,1" textline " " bitfld.long 0x00 28. " GMB796 ,Group Modifier Bit 796" "0,1" bitfld.long 0x00 27. " GMB795 ,Group Modifier Bit 795" "0,1" bitfld.long 0x00 26. " GMB794 ,Group Modifier Bit 794" "0,1" textline " " bitfld.long 0x00 25. " GMB793 ,Group Modifier Bit 793" "0,1" bitfld.long 0x00 24. " GMB792 ,Group Modifier Bit 792" "0,1" bitfld.long 0x00 23. " GMB791 ,Group Modifier Bit 791" "0,1" textline " " bitfld.long 0x00 22. " GMB790 ,Group Modifier Bit 790" "0,1" bitfld.long 0x00 21. " GMB789 ,Group Modifier Bit 789" "0,1" bitfld.long 0x00 20. " GMB788 ,Group Modifier Bit 788" "0,1" textline " " bitfld.long 0x00 19. " GMB787 ,Group Modifier Bit 787" "0,1" bitfld.long 0x00 18. " GMB786 ,Group Modifier Bit 786" "0,1" bitfld.long 0x00 17. " GMB785 ,Group Modifier Bit 785" "0,1" textline " " bitfld.long 0x00 16. " GMB784 ,Group Modifier Bit 784" "0,1" bitfld.long 0x00 15. " GMB783 ,Group Modifier Bit 783" "0,1" bitfld.long 0x00 14. " GMB782 ,Group Modifier Bit 782" "0,1" textline " " bitfld.long 0x00 13. " GMB781 ,Group Modifier Bit 781" "0,1" bitfld.long 0x00 12. " GMB780 ,Group Modifier Bit 780" "0,1" bitfld.long 0x00 11. " GMB779 ,Group Modifier Bit 779" "0,1" textline " " bitfld.long 0x00 10. " GMB778 ,Group Modifier Bit 778" "0,1" bitfld.long 0x00 9. " GMB777 ,Group Modifier Bit 777" "0,1" bitfld.long 0x00 8. " GMB776 ,Group Modifier Bit 776" "0,1" textline " " bitfld.long 0x00 7. " GMB775 ,Group Modifier Bit 775" "0,1" bitfld.long 0x00 6. " GMB774 ,Group Modifier Bit 774" "0,1" bitfld.long 0x00 5. " GMB773 ,Group Modifier Bit 773" "0,1" textline " " bitfld.long 0x00 4. " GMB772 ,Group Modifier Bit 772" "0,1" bitfld.long 0x00 3. " GMB771 ,Group Modifier Bit 771" "0,1" bitfld.long 0x00 2. " GMB770 ,Group Modifier Bit 770" "0,1" textline " " bitfld.long 0x00 1. " GMB769 ,Group Modifier Bit 769" "0,1" bitfld.long 0x00 0. " GMB768 ,Group Modifier Bit 768" "0,1" else hgroup.long 0x0D60++0x03 hide.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D64))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x0D64++0x03 line.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25" bitfld.long 0x00 31. " GMB831 ,Group Modifier Bit 831" "0,1" bitfld.long 0x00 30. " GMB830 ,Group Modifier Bit 830" "0,1" bitfld.long 0x00 29. " GMB829 ,Group Modifier Bit 829" "0,1" textline " " bitfld.long 0x00 28. " GMB828 ,Group Modifier Bit 828" "0,1" bitfld.long 0x00 27. " GMB827 ,Group Modifier Bit 827" "0,1" bitfld.long 0x00 26. " GMB826 ,Group Modifier Bit 826" "0,1" textline " " bitfld.long 0x00 25. " GMB825 ,Group Modifier Bit 825" "0,1" bitfld.long 0x00 24. " GMB824 ,Group Modifier Bit 824" "0,1" bitfld.long 0x00 23. " GMB823 ,Group Modifier Bit 823" "0,1" textline " " bitfld.long 0x00 22. " GMB822 ,Group Modifier Bit 822" "0,1" bitfld.long 0x00 21. " GMB821 ,Group Modifier Bit 821" "0,1" bitfld.long 0x00 20. " GMB820 ,Group Modifier Bit 820" "0,1" textline " " bitfld.long 0x00 19. " GMB819 ,Group Modifier Bit 819" "0,1" bitfld.long 0x00 18. " GMB818 ,Group Modifier Bit 818" "0,1" bitfld.long 0x00 17. " GMB817 ,Group Modifier Bit 817" "0,1" textline " " bitfld.long 0x00 16. " GMB816 ,Group Modifier Bit 816" "0,1" bitfld.long 0x00 15. " GMB815 ,Group Modifier Bit 815" "0,1" bitfld.long 0x00 14. " GMB814 ,Group Modifier Bit 814" "0,1" textline " " bitfld.long 0x00 13. " GMB813 ,Group Modifier Bit 813" "0,1" bitfld.long 0x00 12. " GMB812 ,Group Modifier Bit 812" "0,1" bitfld.long 0x00 11. " GMB811 ,Group Modifier Bit 811" "0,1" textline " " bitfld.long 0x00 10. " GMB810 ,Group Modifier Bit 810" "0,1" bitfld.long 0x00 9. " GMB809 ,Group Modifier Bit 809" "0,1" bitfld.long 0x00 8. " GMB808 ,Group Modifier Bit 808" "0,1" textline " " bitfld.long 0x00 7. " GMB807 ,Group Modifier Bit 807" "0,1" bitfld.long 0x00 6. " GMB806 ,Group Modifier Bit 806" "0,1" bitfld.long 0x00 5. " GMB805 ,Group Modifier Bit 805" "0,1" textline " " bitfld.long 0x00 4. " GMB804 ,Group Modifier Bit 804" "0,1" bitfld.long 0x00 3. " GMB803 ,Group Modifier Bit 803" "0,1" bitfld.long 0x00 2. " GMB802 ,Group Modifier Bit 802" "0,1" textline " " bitfld.long 0x00 1. " GMB801 ,Group Modifier Bit 801" "0,1" bitfld.long 0x00 0. " GMB800 ,Group Modifier Bit 800" "0,1" else hgroup.long 0x0D64++0x03 hide.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D68))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01A)) group.long 0x0D68++0x03 line.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26" bitfld.long 0x00 31. " GMB863 ,Group Modifier Bit 863" "0,1" bitfld.long 0x00 30. " GMB862 ,Group Modifier Bit 862" "0,1" bitfld.long 0x00 29. " GMB861 ,Group Modifier Bit 861" "0,1" textline " " bitfld.long 0x00 28. " GMB860 ,Group Modifier Bit 860" "0,1" bitfld.long 0x00 27. " GMB859 ,Group Modifier Bit 859" "0,1" bitfld.long 0x00 26. " GMB858 ,Group Modifier Bit 858" "0,1" textline " " bitfld.long 0x00 25. " GMB857 ,Group Modifier Bit 857" "0,1" bitfld.long 0x00 24. " GMB856 ,Group Modifier Bit 856" "0,1" bitfld.long 0x00 23. " GMB855 ,Group Modifier Bit 855" "0,1" textline " " bitfld.long 0x00 22. " GMB854 ,Group Modifier Bit 854" "0,1" bitfld.long 0x00 21. " GMB853 ,Group Modifier Bit 853" "0,1" bitfld.long 0x00 20. " GMB852 ,Group Modifier Bit 852" "0,1" textline " " bitfld.long 0x00 19. " GMB851 ,Group Modifier Bit 851" "0,1" bitfld.long 0x00 18. " GMB850 ,Group Modifier Bit 850" "0,1" bitfld.long 0x00 17. " GMB849 ,Group Modifier Bit 849" "0,1" textline " " bitfld.long 0x00 16. " GMB848 ,Group Modifier Bit 848" "0,1" bitfld.long 0x00 15. " GMB847 ,Group Modifier Bit 847" "0,1" bitfld.long 0x00 14. " GMB846 ,Group Modifier Bit 846" "0,1" textline " " bitfld.long 0x00 13. " GMB845 ,Group Modifier Bit 845" "0,1" bitfld.long 0x00 12. " GMB844 ,Group Modifier Bit 844" "0,1" bitfld.long 0x00 11. " GMB843 ,Group Modifier Bit 843" "0,1" textline " " bitfld.long 0x00 10. " GMB842 ,Group Modifier Bit 842" "0,1" bitfld.long 0x00 9. " GMB841 ,Group Modifier Bit 841" "0,1" bitfld.long 0x00 8. " GMB840 ,Group Modifier Bit 840" "0,1" textline " " bitfld.long 0x00 7. " GMB839 ,Group Modifier Bit 839" "0,1" bitfld.long 0x00 6. " GMB838 ,Group Modifier Bit 838" "0,1" bitfld.long 0x00 5. " GMB837 ,Group Modifier Bit 837" "0,1" textline " " bitfld.long 0x00 4. " GMB836 ,Group Modifier Bit 836" "0,1" bitfld.long 0x00 3. " GMB835 ,Group Modifier Bit 835" "0,1" bitfld.long 0x00 2. " GMB834 ,Group Modifier Bit 834" "0,1" textline " " bitfld.long 0x00 1. " GMB833 ,Group Modifier Bit 833" "0,1" bitfld.long 0x00 0. " GMB832 ,Group Modifier Bit 832" "0,1" else hgroup.long 0x0D68++0x03 hide.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D6C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x0D6C++0x03 line.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27" bitfld.long 0x00 31. " GMB895 ,Group Modifier Bit 895" "0,1" bitfld.long 0x00 30. " GMB894 ,Group Modifier Bit 894" "0,1" bitfld.long 0x00 29. " GMB893 ,Group Modifier Bit 893" "0,1" textline " " bitfld.long 0x00 28. " GMB892 ,Group Modifier Bit 892" "0,1" bitfld.long 0x00 27. " GMB891 ,Group Modifier Bit 891" "0,1" bitfld.long 0x00 26. " GMB890 ,Group Modifier Bit 890" "0,1" textline " " bitfld.long 0x00 25. " GMB889 ,Group Modifier Bit 889" "0,1" bitfld.long 0x00 24. " GMB888 ,Group Modifier Bit 888" "0,1" bitfld.long 0x00 23. " GMB887 ,Group Modifier Bit 887" "0,1" textline " " bitfld.long 0x00 22. " GMB886 ,Group Modifier Bit 886" "0,1" bitfld.long 0x00 21. " GMB885 ,Group Modifier Bit 885" "0,1" bitfld.long 0x00 20. " GMB884 ,Group Modifier Bit 884" "0,1" textline " " bitfld.long 0x00 19. " GMB883 ,Group Modifier Bit 883" "0,1" bitfld.long 0x00 18. " GMB882 ,Group Modifier Bit 882" "0,1" bitfld.long 0x00 17. " GMB881 ,Group Modifier Bit 881" "0,1" textline " " bitfld.long 0x00 16. " GMB880 ,Group Modifier Bit 880" "0,1" bitfld.long 0x00 15. " GMB879 ,Group Modifier Bit 879" "0,1" bitfld.long 0x00 14. " GMB878 ,Group Modifier Bit 878" "0,1" textline " " bitfld.long 0x00 13. " GMB877 ,Group Modifier Bit 877" "0,1" bitfld.long 0x00 12. " GMB876 ,Group Modifier Bit 876" "0,1" bitfld.long 0x00 11. " GMB875 ,Group Modifier Bit 875" "0,1" textline " " bitfld.long 0x00 10. " GMB874 ,Group Modifier Bit 874" "0,1" bitfld.long 0x00 9. " GMB873 ,Group Modifier Bit 873" "0,1" bitfld.long 0x00 8. " GMB872 ,Group Modifier Bit 872" "0,1" textline " " bitfld.long 0x00 7. " GMB871 ,Group Modifier Bit 871" "0,1" bitfld.long 0x00 6. " GMB870 ,Group Modifier Bit 870" "0,1" bitfld.long 0x00 5. " GMB869 ,Group Modifier Bit 869" "0,1" textline " " bitfld.long 0x00 4. " GMB868 ,Group Modifier Bit 868" "0,1" bitfld.long 0x00 3. " GMB867 ,Group Modifier Bit 867" "0,1" bitfld.long 0x00 2. " GMB866 ,Group Modifier Bit 866" "0,1" textline " " bitfld.long 0x00 1. " GMB865 ,Group Modifier Bit 865" "0,1" bitfld.long 0x00 0. " GMB864 ,Group Modifier Bit 864" "0,1" else hgroup.long 0x0D6C++0x03 hide.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D70))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x0D70++0x03 line.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28" bitfld.long 0x00 31. " GMB927 ,Group Modifier Bit 927" "0,1" bitfld.long 0x00 30. " GMB926 ,Group Modifier Bit 926" "0,1" bitfld.long 0x00 29. " GMB925 ,Group Modifier Bit 925" "0,1" textline " " bitfld.long 0x00 28. " GMB924 ,Group Modifier Bit 924" "0,1" bitfld.long 0x00 27. " GMB923 ,Group Modifier Bit 923" "0,1" bitfld.long 0x00 26. " GMB922 ,Group Modifier Bit 922" "0,1" textline " " bitfld.long 0x00 25. " GMB921 ,Group Modifier Bit 921" "0,1" bitfld.long 0x00 24. " GMB920 ,Group Modifier Bit 920" "0,1" bitfld.long 0x00 23. " GMB919 ,Group Modifier Bit 919" "0,1" textline " " bitfld.long 0x00 22. " GMB918 ,Group Modifier Bit 918" "0,1" bitfld.long 0x00 21. " GMB917 ,Group Modifier Bit 917" "0,1" bitfld.long 0x00 20. " GMB916 ,Group Modifier Bit 916" "0,1" textline " " bitfld.long 0x00 19. " GMB915 ,Group Modifier Bit 915" "0,1" bitfld.long 0x00 18. " GMB914 ,Group Modifier Bit 914" "0,1" bitfld.long 0x00 17. " GMB913 ,Group Modifier Bit 913" "0,1" textline " " bitfld.long 0x00 16. " GMB912 ,Group Modifier Bit 912" "0,1" bitfld.long 0x00 15. " GMB911 ,Group Modifier Bit 911" "0,1" bitfld.long 0x00 14. " GMB910 ,Group Modifier Bit 910" "0,1" textline " " bitfld.long 0x00 13. " GMB909 ,Group Modifier Bit 909" "0,1" bitfld.long 0x00 12. " GMB908 ,Group Modifier Bit 908" "0,1" bitfld.long 0x00 11. " GMB907 ,Group Modifier Bit 907" "0,1" textline " " bitfld.long 0x00 10. " GMB906 ,Group Modifier Bit 906" "0,1" bitfld.long 0x00 9. " GMB905 ,Group Modifier Bit 905" "0,1" bitfld.long 0x00 8. " GMB904 ,Group Modifier Bit 904" "0,1" textline " " bitfld.long 0x00 7. " GMB903 ,Group Modifier Bit 903" "0,1" bitfld.long 0x00 6. " GMB902 ,Group Modifier Bit 902" "0,1" bitfld.long 0x00 5. " GMB901 ,Group Modifier Bit 901" "0,1" textline " " bitfld.long 0x00 4. " GMB900 ,Group Modifier Bit 900" "0,1" bitfld.long 0x00 3. " GMB899 ,Group Modifier Bit 899" "0,1" bitfld.long 0x00 2. " GMB898 ,Group Modifier Bit 898" "0,1" textline " " bitfld.long 0x00 1. " GMB897 ,Group Modifier Bit 897" "0,1" bitfld.long 0x00 0. " GMB896 ,Group Modifier Bit 896" "0,1" else hgroup.long 0x0D70++0x03 hide.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D74))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x0D74++0x03 line.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29" bitfld.long 0x00 31. " GMB959 ,Group Modifier Bit 959" "0,1" bitfld.long 0x00 30. " GMB958 ,Group Modifier Bit 958" "0,1" bitfld.long 0x00 29. " GMB957 ,Group Modifier Bit 957" "0,1" textline " " bitfld.long 0x00 28. " GMB956 ,Group Modifier Bit 956" "0,1" bitfld.long 0x00 27. " GMB955 ,Group Modifier Bit 955" "0,1" bitfld.long 0x00 26. " GMB954 ,Group Modifier Bit 954" "0,1" textline " " bitfld.long 0x00 25. " GMB953 ,Group Modifier Bit 953" "0,1" bitfld.long 0x00 24. " GMB952 ,Group Modifier Bit 952" "0,1" bitfld.long 0x00 23. " GMB951 ,Group Modifier Bit 951" "0,1" textline " " bitfld.long 0x00 22. " GMB950 ,Group Modifier Bit 950" "0,1" bitfld.long 0x00 21. " GMB949 ,Group Modifier Bit 949" "0,1" bitfld.long 0x00 20. " GMB948 ,Group Modifier Bit 948" "0,1" textline " " bitfld.long 0x00 19. " GMB947 ,Group Modifier Bit 947" "0,1" bitfld.long 0x00 18. " GMB946 ,Group Modifier Bit 946" "0,1" bitfld.long 0x00 17. " GMB945 ,Group Modifier Bit 945" "0,1" textline " " bitfld.long 0x00 16. " GMB944 ,Group Modifier Bit 944" "0,1" bitfld.long 0x00 15. " GMB943 ,Group Modifier Bit 943" "0,1" bitfld.long 0x00 14. " GMB942 ,Group Modifier Bit 942" "0,1" textline " " bitfld.long 0x00 13. " GMB941 ,Group Modifier Bit 941" "0,1" bitfld.long 0x00 12. " GMB940 ,Group Modifier Bit 940" "0,1" bitfld.long 0x00 11. " GMB939 ,Group Modifier Bit 939" "0,1" textline " " bitfld.long 0x00 10. " GMB938 ,Group Modifier Bit 938" "0,1" bitfld.long 0x00 9. " GMB937 ,Group Modifier Bit 937" "0,1" bitfld.long 0x00 8. " GMB936 ,Group Modifier Bit 936" "0,1" textline " " bitfld.long 0x00 7. " GMB935 ,Group Modifier Bit 935" "0,1" bitfld.long 0x00 6. " GMB934 ,Group Modifier Bit 934" "0,1" bitfld.long 0x00 5. " GMB933 ,Group Modifier Bit 933" "0,1" textline " " bitfld.long 0x00 4. " GMB932 ,Group Modifier Bit 932" "0,1" bitfld.long 0x00 3. " GMB931 ,Group Modifier Bit 931" "0,1" bitfld.long 0x00 2. " GMB930 ,Group Modifier Bit 930" "0,1" textline " " bitfld.long 0x00 1. " GMB929 ,Group Modifier Bit 929" "0,1" bitfld.long 0x00 0. " GMB928 ,Group Modifier Bit 928" "0,1" else hgroup.long 0x0D74++0x03 hide.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D78))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x0D78++0x03 line.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30" bitfld.long 0x00 31. " GMB991 ,Group Modifier Bit 991" "0,1" bitfld.long 0x00 30. " GMB990 ,Group Modifier Bit 990" "0,1" bitfld.long 0x00 29. " GMB989 ,Group Modifier Bit 989" "0,1" textline " " bitfld.long 0x00 28. " GMB988 ,Group Modifier Bit 988" "0,1" bitfld.long 0x00 27. " GMB987 ,Group Modifier Bit 987" "0,1" bitfld.long 0x00 26. " GMB986 ,Group Modifier Bit 986" "0,1" textline " " bitfld.long 0x00 25. " GMB985 ,Group Modifier Bit 985" "0,1" bitfld.long 0x00 24. " GMB984 ,Group Modifier Bit 984" "0,1" bitfld.long 0x00 23. " GMB983 ,Group Modifier Bit 983" "0,1" textline " " bitfld.long 0x00 22. " GMB982 ,Group Modifier Bit 982" "0,1" bitfld.long 0x00 21. " GMB981 ,Group Modifier Bit 981" "0,1" bitfld.long 0x00 20. " GMB980 ,Group Modifier Bit 980" "0,1" textline " " bitfld.long 0x00 19. " GMB979 ,Group Modifier Bit 979" "0,1" bitfld.long 0x00 18. " GMB978 ,Group Modifier Bit 978" "0,1" bitfld.long 0x00 17. " GMB977 ,Group Modifier Bit 977" "0,1" textline " " bitfld.long 0x00 16. " GMB976 ,Group Modifier Bit 976" "0,1" bitfld.long 0x00 15. " GMB975 ,Group Modifier Bit 975" "0,1" bitfld.long 0x00 14. " GMB974 ,Group Modifier Bit 974" "0,1" textline " " bitfld.long 0x00 13. " GMB973 ,Group Modifier Bit 973" "0,1" bitfld.long 0x00 12. " GMB972 ,Group Modifier Bit 972" "0,1" bitfld.long 0x00 11. " GMB971 ,Group Modifier Bit 971" "0,1" textline " " bitfld.long 0x00 10. " GMB970 ,Group Modifier Bit 970" "0,1" bitfld.long 0x00 9. " GMB969 ,Group Modifier Bit 969" "0,1" bitfld.long 0x00 8. " GMB968 ,Group Modifier Bit 968" "0,1" textline " " bitfld.long 0x00 7. " GMB967 ,Group Modifier Bit 967" "0,1" bitfld.long 0x00 6. " GMB966 ,Group Modifier Bit 966" "0,1" bitfld.long 0x00 5. " GMB965 ,Group Modifier Bit 965" "0,1" textline " " bitfld.long 0x00 4. " GMB964 ,Group Modifier Bit 964" "0,1" bitfld.long 0x00 3. " GMB963 ,Group Modifier Bit 963" "0,1" bitfld.long 0x00 2. " GMB962 ,Group Modifier Bit 962" "0,1" textline " " bitfld.long 0x00 1. " GMB961 ,Group Modifier Bit 961" "0,1" bitfld.long 0x00 0. " GMB960 ,Group Modifier Bit 960" "0,1" else hgroup.long 0x0D78++0x03 hide.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30" endif tree.end width 14. tree "Non-secure Access Control Registers" hgroup.long 0x0E00++0x03 hide.long 0x00 "GICD_NSACR0,Non-secure Access Control Register 0" hgroup.long 0xE04++0x03 hide.long 0x00 "GICD_NSACR1,Non-secure Access Control Register 1" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE08))) group.long 0xE08++0x03 line.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2" bitfld.long 0x00 30.--31. " NS_ACCESS47 ,Controls Non-secure access of the interrupt with ID47 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS46 ,Controls Non-secure access of the interrupt with ID46 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS45 ,Controls Non-secure access of the interrupt with ID45 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS44 ,Controls Non-secure access of the interrupt with ID44 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS43 ,Controls Non-secure access of the interrupt with ID43 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS42 ,Controls Non-secure access of the interrupt with ID42 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS41 ,Controls Non-secure access of the interrupt with ID41 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS40 ,Controls Non-secure access of the interrupt with ID40 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS39 ,Controls Non-secure access of the interrupt with ID39 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS38 ,Controls Non-secure access of the interrupt with ID38 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS37 ,Controls Non-secure access of the interrupt with ID37 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS36 ,Controls Non-secure access of the interrupt with ID36 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS35 ,Controls Non-secure access of the interrupt with ID35 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS34 ,Controls Non-secure access of the interrupt with ID34 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS33 ,Controls Non-secure access of the interrupt with ID33 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS32 ,Controls Non-secure access of the interrupt with ID32 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE08++0x03 hide.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0C))) group.long 0xE0C++0x03 line.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3" bitfld.long 0x00 30.--31. " NS_ACCESS63 ,Controls Non-secure access of the interrupt with ID63 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS62 ,Controls Non-secure access of the interrupt with ID62 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS61 ,Controls Non-secure access of the interrupt with ID61 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS60 ,Controls Non-secure access of the interrupt with ID60 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS59 ,Controls Non-secure access of the interrupt with ID59 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS58 ,Controls Non-secure access of the interrupt with ID58 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS57 ,Controls Non-secure access of the interrupt with ID57 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS56 ,Controls Non-secure access of the interrupt with ID56 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS55 ,Controls Non-secure access of the interrupt with ID55 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS54 ,Controls Non-secure access of the interrupt with ID54 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS53 ,Controls Non-secure access of the interrupt with ID53 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS52 ,Controls Non-secure access of the interrupt with ID52 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS51 ,Controls Non-secure access of the interrupt with ID51 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS50 ,Controls Non-secure access of the interrupt with ID50 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS49 ,Controls Non-secure access of the interrupt with ID49 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS48 ,Controls Non-secure access of the interrupt with ID48 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE0C++0x03 hide.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE10))) group.long 0xE10++0x03 line.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4" bitfld.long 0x00 30.--31. " NS_ACCESS79 ,Controls Non-secure access of the interrupt with ID79 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS78 ,Controls Non-secure access of the interrupt with ID78 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS77 ,Controls Non-secure access of the interrupt with ID77 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS76 ,Controls Non-secure access of the interrupt with ID76 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS75 ,Controls Non-secure access of the interrupt with ID75 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS74 ,Controls Non-secure access of the interrupt with ID74 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS73 ,Controls Non-secure access of the interrupt with ID73 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS72 ,Controls Non-secure access of the interrupt with ID72 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS71 ,Controls Non-secure access of the interrupt with ID71 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS70 ,Controls Non-secure access of the interrupt with ID70 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS69 ,Controls Non-secure access of the interrupt with ID69 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS68 ,Controls Non-secure access of the interrupt with ID68 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS67 ,Controls Non-secure access of the interrupt with ID67 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS66 ,Controls Non-secure access of the interrupt with ID66 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS65 ,Controls Non-secure access of the interrupt with ID65 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS64 ,Controls Non-secure access of the interrupt with ID64 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE10++0x03 hide.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE14))) group.long 0xE14++0x03 line.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5" bitfld.long 0x00 30.--31. " NS_ACCESS95 ,Controls Non-secure access of the interrupt with ID95 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS94 ,Controls Non-secure access of the interrupt with ID94 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS93 ,Controls Non-secure access of the interrupt with ID93 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS92 ,Controls Non-secure access of the interrupt with ID92 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS91 ,Controls Non-secure access of the interrupt with ID91 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS90 ,Controls Non-secure access of the interrupt with ID90 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS89 ,Controls Non-secure access of the interrupt with ID89 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS88 ,Controls Non-secure access of the interrupt with ID88 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS87 ,Controls Non-secure access of the interrupt with ID87 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS86 ,Controls Non-secure access of the interrupt with ID86 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS85 ,Controls Non-secure access of the interrupt with ID85 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS84 ,Controls Non-secure access of the interrupt with ID84 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS83 ,Controls Non-secure access of the interrupt with ID83 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS82 ,Controls Non-secure access of the interrupt with ID82 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS81 ,Controls Non-secure access of the interrupt with ID81 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS80 ,Controls Non-secure access of the interrupt with ID80 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE14++0x03 hide.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE18))) group.long 0xE18++0x03 line.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6" bitfld.long 0x00 30.--31. " NS_ACCESS111 ,Controls Non-secure access of the interrupt with ID111" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS110 ,Controls Non-secure access of the interrupt with ID110" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS109 ,Controls Non-secure access of the interrupt with ID109" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS108 ,Controls Non-secure access of the interrupt with ID108" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS107 ,Controls Non-secure access of the interrupt with ID107" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS106 ,Controls Non-secure access of the interrupt with ID106" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS105 ,Controls Non-secure access of the interrupt with ID105" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS104 ,Controls Non-secure access of the interrupt with ID104" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS103 ,Controls Non-secure access of the interrupt with ID103" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS102 ,Controls Non-secure access of the interrupt with ID102" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS101 ,Controls Non-secure access of the interrupt with ID101" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS100 ,Controls Non-secure access of the interrupt with ID100" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS99 ,Controls Non-secure access of the interrupt with ID99 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS98 ,Controls Non-secure access of the interrupt with ID98 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS97 ,Controls Non-secure access of the interrupt with ID97 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS96 ,Controls Non-secure access of the interrupt with ID96 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE18++0x03 hide.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE1C))) group.long 0xE1C++0x03 line.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7" bitfld.long 0x00 30.--31. " NS_ACCESS127 ,Controls Non-secure access of the interrupt with ID127" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS126 ,Controls Non-secure access of the interrupt with ID126" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS125 ,Controls Non-secure access of the interrupt with ID125" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS124 ,Controls Non-secure access of the interrupt with ID124" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS123 ,Controls Non-secure access of the interrupt with ID123" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS122 ,Controls Non-secure access of the interrupt with ID122" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS121 ,Controls Non-secure access of the interrupt with ID121" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS120 ,Controls Non-secure access of the interrupt with ID120" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS119 ,Controls Non-secure access of the interrupt with ID119" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS118 ,Controls Non-secure access of the interrupt with ID118" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS117 ,Controls Non-secure access of the interrupt with ID117" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS116 ,Controls Non-secure access of the interrupt with ID116" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS115 ,Controls Non-secure access of the interrupt with ID115" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS114 ,Controls Non-secure access of the interrupt with ID114" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS113 ,Controls Non-secure access of the interrupt with ID113" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS112 ,Controls Non-secure access of the interrupt with ID112" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE1C++0x03 hide.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE20))) group.long 0xE20++0x03 line.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8" bitfld.long 0x00 30.--31. " NS_ACCESS143 ,Controls Non-secure access of the interrupt with ID143" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS142 ,Controls Non-secure access of the interrupt with ID142" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS141 ,Controls Non-secure access of the interrupt with ID141" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS140 ,Controls Non-secure access of the interrupt with ID140" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS139 ,Controls Non-secure access of the interrupt with ID139" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS138 ,Controls Non-secure access of the interrupt with ID138" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS137 ,Controls Non-secure access of the interrupt with ID137" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS136 ,Controls Non-secure access of the interrupt with ID136" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS135 ,Controls Non-secure access of the interrupt with ID135" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS134 ,Controls Non-secure access of the interrupt with ID134" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS133 ,Controls Non-secure access of the interrupt with ID133" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS132 ,Controls Non-secure access of the interrupt with ID132" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS131 ,Controls Non-secure access of the interrupt with ID131" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS130 ,Controls Non-secure access of the interrupt with ID130" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS129 ,Controls Non-secure access of the interrupt with ID129" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS128 ,Controls Non-secure access of the interrupt with ID128" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE20++0x03 hide.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE24))) group.long 0xE24++0x03 line.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9" bitfld.long 0x00 30.--31. " NS_ACCESS159 ,Controls Non-secure access of the interrupt with ID159" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS158 ,Controls Non-secure access of the interrupt with ID158" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS157 ,Controls Non-secure access of the interrupt with ID157" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS156 ,Controls Non-secure access of the interrupt with ID156" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS155 ,Controls Non-secure access of the interrupt with ID155" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS154 ,Controls Non-secure access of the interrupt with ID154" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS153 ,Controls Non-secure access of the interrupt with ID153" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS152 ,Controls Non-secure access of the interrupt with ID152" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS151 ,Controls Non-secure access of the interrupt with ID151" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS150 ,Controls Non-secure access of the interrupt with ID150" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS149 ,Controls Non-secure access of the interrupt with ID149" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS148 ,Controls Non-secure access of the interrupt with ID148" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS147 ,Controls Non-secure access of the interrupt with ID147" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS146 ,Controls Non-secure access of the interrupt with ID146" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS145 ,Controls Non-secure access of the interrupt with ID145" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS144 ,Controls Non-secure access of the interrupt with ID144" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE24++0x03 hide.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE28))) group.long 0xE28++0x03 line.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10" bitfld.long 0x00 30.--31. " NS_ACCESS175 ,Controls Non-secure access of the interrupt with ID175" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS174 ,Controls Non-secure access of the interrupt with ID174" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS173 ,Controls Non-secure access of the interrupt with ID173" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS172 ,Controls Non-secure access of the interrupt with ID172" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS171 ,Controls Non-secure access of the interrupt with ID171" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS170 ,Controls Non-secure access of the interrupt with ID170" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS169 ,Controls Non-secure access of the interrupt with ID169" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS168 ,Controls Non-secure access of the interrupt with ID168" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS167 ,Controls Non-secure access of the interrupt with ID167" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS166 ,Controls Non-secure access of the interrupt with ID166" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS165 ,Controls Non-secure access of the interrupt with ID165" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS164 ,Controls Non-secure access of the interrupt with ID164" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS163 ,Controls Non-secure access of the interrupt with ID163" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS162 ,Controls Non-secure access of the interrupt with ID162" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS161 ,Controls Non-secure access of the interrupt with ID161" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS160 ,Controls Non-secure access of the interrupt with ID160" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE28++0x03 hide.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE2C))) group.long 0xE2C++0x03 line.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11" bitfld.long 0x00 30.--31. " NS_ACCESS191 ,Controls Non-secure access of the interrupt with ID191" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS190 ,Controls Non-secure access of the interrupt with ID190" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS189 ,Controls Non-secure access of the interrupt with ID189" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS188 ,Controls Non-secure access of the interrupt with ID188" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS187 ,Controls Non-secure access of the interrupt with ID187" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS186 ,Controls Non-secure access of the interrupt with ID186" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS185 ,Controls Non-secure access of the interrupt with ID185" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS184 ,Controls Non-secure access of the interrupt with ID184" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS183 ,Controls Non-secure access of the interrupt with ID183" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS182 ,Controls Non-secure access of the interrupt with ID182" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS181 ,Controls Non-secure access of the interrupt with ID181" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS180 ,Controls Non-secure access of the interrupt with ID180" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS179 ,Controls Non-secure access of the interrupt with ID179" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS178 ,Controls Non-secure access of the interrupt with ID178" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS177 ,Controls Non-secure access of the interrupt with ID177" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS176 ,Controls Non-secure access of the interrupt with ID176" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE2C++0x03 hide.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE30))) group.long 0xE30++0x03 line.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12" bitfld.long 0x00 30.--31. " NS_ACCESS207 ,Controls Non-secure access of the interrupt with ID207" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS206 ,Controls Non-secure access of the interrupt with ID206" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS205 ,Controls Non-secure access of the interrupt with ID205" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS204 ,Controls Non-secure access of the interrupt with ID204" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS203 ,Controls Non-secure access of the interrupt with ID203" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS202 ,Controls Non-secure access of the interrupt with ID202" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS201 ,Controls Non-secure access of the interrupt with ID201" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS200 ,Controls Non-secure access of the interrupt with ID200" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS199 ,Controls Non-secure access of the interrupt with ID199" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS198 ,Controls Non-secure access of the interrupt with ID198" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS197 ,Controls Non-secure access of the interrupt with ID197" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS196 ,Controls Non-secure access of the interrupt with ID196" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS195 ,Controls Non-secure access of the interrupt with ID195" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS194 ,Controls Non-secure access of the interrupt with ID194" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS193 ,Controls Non-secure access of the interrupt with ID193" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS192 ,Controls Non-secure access of the interrupt with ID192" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE30++0x03 hide.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE34))) group.long 0xE34++0x03 line.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13" bitfld.long 0x00 30.--31. " NS_ACCESS223 ,Controls Non-secure access of the interrupt with ID223" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS222 ,Controls Non-secure access of the interrupt with ID222" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS221 ,Controls Non-secure access of the interrupt with ID221" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS220 ,Controls Non-secure access of the interrupt with ID220" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS219 ,Controls Non-secure access of the interrupt with ID219" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS218 ,Controls Non-secure access of the interrupt with ID218" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS217 ,Controls Non-secure access of the interrupt with ID217" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS216 ,Controls Non-secure access of the interrupt with ID216" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS215 ,Controls Non-secure access of the interrupt with ID215" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS214 ,Controls Non-secure access of the interrupt with ID214" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS213 ,Controls Non-secure access of the interrupt with ID213" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS212 ,Controls Non-secure access of the interrupt with ID212" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS211 ,Controls Non-secure access of the interrupt with ID211" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS210 ,Controls Non-secure access of the interrupt with ID210" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS209 ,Controls Non-secure access of the interrupt with ID209" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS208 ,Controls Non-secure access of the interrupt with ID208" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE34++0x03 hide.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE38))) group.long 0xE38++0x03 line.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14" bitfld.long 0x00 30.--31. " NS_ACCESS239 ,Controls Non-secure access of the interrupt with ID239" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS238 ,Controls Non-secure access of the interrupt with ID238" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS237 ,Controls Non-secure access of the interrupt with ID237" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS236 ,Controls Non-secure access of the interrupt with ID236" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS235 ,Controls Non-secure access of the interrupt with ID235" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS234 ,Controls Non-secure access of the interrupt with ID234" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS233 ,Controls Non-secure access of the interrupt with ID233" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS232 ,Controls Non-secure access of the interrupt with ID232" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS231 ,Controls Non-secure access of the interrupt with ID231" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS230 ,Controls Non-secure access of the interrupt with ID230" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS229 ,Controls Non-secure access of the interrupt with ID229" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS228 ,Controls Non-secure access of the interrupt with ID228" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS227 ,Controls Non-secure access of the interrupt with ID227" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS226 ,Controls Non-secure access of the interrupt with ID226" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS225 ,Controls Non-secure access of the interrupt with ID225" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS224 ,Controls Non-secure access of the interrupt with ID224" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE38++0x03 hide.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE3C))) group.long 0xE3C++0x03 line.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15" bitfld.long 0x00 30.--31. " NS_ACCESS255 ,Controls Non-secure access of the interrupt with ID255" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS254 ,Controls Non-secure access of the interrupt with ID254" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS253 ,Controls Non-secure access of the interrupt with ID253" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS252 ,Controls Non-secure access of the interrupt with ID252" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS251 ,Controls Non-secure access of the interrupt with ID251" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS250 ,Controls Non-secure access of the interrupt with ID250" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS249 ,Controls Non-secure access of the interrupt with ID249" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS248 ,Controls Non-secure access of the interrupt with ID248" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS247 ,Controls Non-secure access of the interrupt with ID247" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS246 ,Controls Non-secure access of the interrupt with ID246" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS245 ,Controls Non-secure access of the interrupt with ID245" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS244 ,Controls Non-secure access of the interrupt with ID244" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS243 ,Controls Non-secure access of the interrupt with ID243" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS242 ,Controls Non-secure access of the interrupt with ID242" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS241 ,Controls Non-secure access of the interrupt with ID241" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS240 ,Controls Non-secure access of the interrupt with ID240" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE3C++0x03 hide.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE40))) group.long 0xE40++0x03 line.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16" bitfld.long 0x00 30.--31. " NS_ACCESS271 ,Controls Non-secure access of the interrupt with ID271" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS270 ,Controls Non-secure access of the interrupt with ID270" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS269 ,Controls Non-secure access of the interrupt with ID269" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS268 ,Controls Non-secure access of the interrupt with ID268" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS267 ,Controls Non-secure access of the interrupt with ID267" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS266 ,Controls Non-secure access of the interrupt with ID266" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS265 ,Controls Non-secure access of the interrupt with ID265" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS264 ,Controls Non-secure access of the interrupt with ID264" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS263 ,Controls Non-secure access of the interrupt with ID263" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS262 ,Controls Non-secure access of the interrupt with ID262" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS261 ,Controls Non-secure access of the interrupt with ID261" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS260 ,Controls Non-secure access of the interrupt with ID260" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS259 ,Controls Non-secure access of the interrupt with ID259" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS258 ,Controls Non-secure access of the interrupt with ID258" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS257 ,Controls Non-secure access of the interrupt with ID257" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS256 ,Controls Non-secure access of the interrupt with ID256" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE40++0x03 hide.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE44))) group.long 0xE44++0x03 line.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17" bitfld.long 0x00 30.--31. " NS_ACCESS287 ,Controls Non-secure access of the interrupt with ID287" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS286 ,Controls Non-secure access of the interrupt with ID286" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS285 ,Controls Non-secure access of the interrupt with ID285" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS284 ,Controls Non-secure access of the interrupt with ID284" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS283 ,Controls Non-secure access of the interrupt with ID283" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS282 ,Controls Non-secure access of the interrupt with ID282" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS281 ,Controls Non-secure access of the interrupt with ID281" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS280 ,Controls Non-secure access of the interrupt with ID280" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS279 ,Controls Non-secure access of the interrupt with ID279" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS278 ,Controls Non-secure access of the interrupt with ID278" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS277 ,Controls Non-secure access of the interrupt with ID277" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS276 ,Controls Non-secure access of the interrupt with ID276" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS275 ,Controls Non-secure access of the interrupt with ID275" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS274 ,Controls Non-secure access of the interrupt with ID274" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS273 ,Controls Non-secure access of the interrupt with ID273" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS272 ,Controls Non-secure access of the interrupt with ID272" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE44++0x03 hide.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE48))) group.long 0xE48++0x03 line.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18" bitfld.long 0x00 30.--31. " NS_ACCESS303 ,Controls Non-secure access of the interrupt with ID303" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS302 ,Controls Non-secure access of the interrupt with ID302" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS301 ,Controls Non-secure access of the interrupt with ID301" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS300 ,Controls Non-secure access of the interrupt with ID300" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS299 ,Controls Non-secure access of the interrupt with ID299" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS298 ,Controls Non-secure access of the interrupt with ID298" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS297 ,Controls Non-secure access of the interrupt with ID297" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS296 ,Controls Non-secure access of the interrupt with ID296" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS295 ,Controls Non-secure access of the interrupt with ID295" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS294 ,Controls Non-secure access of the interrupt with ID294" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS293 ,Controls Non-secure access of the interrupt with ID293" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS292 ,Controls Non-secure access of the interrupt with ID292" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS291 ,Controls Non-secure access of the interrupt with ID291" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS290 ,Controls Non-secure access of the interrupt with ID290" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS289 ,Controls Non-secure access of the interrupt with ID289" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS288 ,Controls Non-secure access of the interrupt with ID288" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE48++0x03 hide.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4C))) group.long 0xE4C++0x03 line.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19" bitfld.long 0x00 30.--31. " NS_ACCESS319 ,Controls Non-secure access of the interrupt with ID319" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS318 ,Controls Non-secure access of the interrupt with ID318" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS317 ,Controls Non-secure access of the interrupt with ID317" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS316 ,Controls Non-secure access of the interrupt with ID316" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS315 ,Controls Non-secure access of the interrupt with ID315" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS314 ,Controls Non-secure access of the interrupt with ID314" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS313 ,Controls Non-secure access of the interrupt with ID313" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS312 ,Controls Non-secure access of the interrupt with ID312" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS311 ,Controls Non-secure access of the interrupt with ID311" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS310 ,Controls Non-secure access of the interrupt with ID310" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS309 ,Controls Non-secure access of the interrupt with ID309" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS308 ,Controls Non-secure access of the interrupt with ID308" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS307 ,Controls Non-secure access of the interrupt with ID307" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS306 ,Controls Non-secure access of the interrupt with ID306" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS305 ,Controls Non-secure access of the interrupt with ID305" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS304 ,Controls Non-secure access of the interrupt with ID304" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE4C++0x03 hide.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE50))) group.long 0xE50++0x03 line.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20" bitfld.long 0x00 30.--31. " NS_ACCESS335 ,Controls Non-secure access of the interrupt with ID335" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS334 ,Controls Non-secure access of the interrupt with ID334" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS333 ,Controls Non-secure access of the interrupt with ID333" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS332 ,Controls Non-secure access of the interrupt with ID332" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS331 ,Controls Non-secure access of the interrupt with ID331" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS330 ,Controls Non-secure access of the interrupt with ID330" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS329 ,Controls Non-secure access of the interrupt with ID329" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS328 ,Controls Non-secure access of the interrupt with ID328" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS327 ,Controls Non-secure access of the interrupt with ID327" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS326 ,Controls Non-secure access of the interrupt with ID326" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS325 ,Controls Non-secure access of the interrupt with ID325" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS324 ,Controls Non-secure access of the interrupt with ID324" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS323 ,Controls Non-secure access of the interrupt with ID323" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS322 ,Controls Non-secure access of the interrupt with ID322" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS321 ,Controls Non-secure access of the interrupt with ID321" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS320 ,Controls Non-secure access of the interrupt with ID320" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE50++0x03 hide.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE54))) group.long 0xE54++0x03 line.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21" bitfld.long 0x00 30.--31. " NS_ACCESS351 ,Controls Non-secure access of the interrupt with ID351" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS350 ,Controls Non-secure access of the interrupt with ID350" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS349 ,Controls Non-secure access of the interrupt with ID349" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS348 ,Controls Non-secure access of the interrupt with ID348" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS347 ,Controls Non-secure access of the interrupt with ID347" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS346 ,Controls Non-secure access of the interrupt with ID346" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS345 ,Controls Non-secure access of the interrupt with ID345" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS344 ,Controls Non-secure access of the interrupt with ID344" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS343 ,Controls Non-secure access of the interrupt with ID343" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS342 ,Controls Non-secure access of the interrupt with ID342" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS341 ,Controls Non-secure access of the interrupt with ID341" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS340 ,Controls Non-secure access of the interrupt with ID340" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS339 ,Controls Non-secure access of the interrupt with ID339" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS338 ,Controls Non-secure access of the interrupt with ID338" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS337 ,Controls Non-secure access of the interrupt with ID337" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS336 ,Controls Non-secure access of the interrupt with ID336" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE54++0x03 hide.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE58))) group.long 0xE58++0x03 line.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22" bitfld.long 0x00 30.--31. " NS_ACCESS367 ,Controls Non-secure access of the interrupt with ID367" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS366 ,Controls Non-secure access of the interrupt with ID366" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS365 ,Controls Non-secure access of the interrupt with ID365" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS364 ,Controls Non-secure access of the interrupt with ID364" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS363 ,Controls Non-secure access of the interrupt with ID363" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS362 ,Controls Non-secure access of the interrupt with ID362" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS361 ,Controls Non-secure access of the interrupt with ID361" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS360 ,Controls Non-secure access of the interrupt with ID360" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS359 ,Controls Non-secure access of the interrupt with ID359" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS358 ,Controls Non-secure access of the interrupt with ID358" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS357 ,Controls Non-secure access of the interrupt with ID357" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS356 ,Controls Non-secure access of the interrupt with ID356" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS355 ,Controls Non-secure access of the interrupt with ID355" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS354 ,Controls Non-secure access of the interrupt with ID354" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS353 ,Controls Non-secure access of the interrupt with ID353" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS352 ,Controls Non-secure access of the interrupt with ID352" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE58++0x03 hide.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE5C))) group.long 0xE5C++0x03 line.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23" bitfld.long 0x00 30.--31. " NS_ACCESS383 ,Controls Non-secure access of the interrupt with ID383" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS382 ,Controls Non-secure access of the interrupt with ID382" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS381 ,Controls Non-secure access of the interrupt with ID381" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS380 ,Controls Non-secure access of the interrupt with ID380" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS379 ,Controls Non-secure access of the interrupt with ID379" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS378 ,Controls Non-secure access of the interrupt with ID378" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS377 ,Controls Non-secure access of the interrupt with ID377" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS376 ,Controls Non-secure access of the interrupt with ID376" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS375 ,Controls Non-secure access of the interrupt with ID375" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS374 ,Controls Non-secure access of the interrupt with ID374" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS373 ,Controls Non-secure access of the interrupt with ID373" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS372 ,Controls Non-secure access of the interrupt with ID372" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS371 ,Controls Non-secure access of the interrupt with ID371" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS370 ,Controls Non-secure access of the interrupt with ID370" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS369 ,Controls Non-secure access of the interrupt with ID369" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS368 ,Controls Non-secure access of the interrupt with ID368" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE5C++0x03 hide.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE60))) group.long 0xE60++0x03 line.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24" bitfld.long 0x00 30.--31. " NS_ACCESS399 ,Controls Non-secure access of the interrupt with ID399" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS398 ,Controls Non-secure access of the interrupt with ID398" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS397 ,Controls Non-secure access of the interrupt with ID397" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS396 ,Controls Non-secure access of the interrupt with ID396" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS395 ,Controls Non-secure access of the interrupt with ID395" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS394 ,Controls Non-secure access of the interrupt with ID394" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS393 ,Controls Non-secure access of the interrupt with ID393" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS392 ,Controls Non-secure access of the interrupt with ID392" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS391 ,Controls Non-secure access of the interrupt with ID391" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS390 ,Controls Non-secure access of the interrupt with ID390" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS389 ,Controls Non-secure access of the interrupt with ID389" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS388 ,Controls Non-secure access of the interrupt with ID388" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS387 ,Controls Non-secure access of the interrupt with ID387" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS386 ,Controls Non-secure access of the interrupt with ID386" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS385 ,Controls Non-secure access of the interrupt with ID385" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS384 ,Controls Non-secure access of the interrupt with ID384" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE60++0x03 hide.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE64))) group.long 0xE64++0x03 line.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25" bitfld.long 0x00 30.--31. " NS_ACCESS415 ,Controls Non-secure access of the interrupt with ID415" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS414 ,Controls Non-secure access of the interrupt with ID414" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS413 ,Controls Non-secure access of the interrupt with ID413" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS412 ,Controls Non-secure access of the interrupt with ID412" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS411 ,Controls Non-secure access of the interrupt with ID411" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS410 ,Controls Non-secure access of the interrupt with ID410" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS409 ,Controls Non-secure access of the interrupt with ID409" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS408 ,Controls Non-secure access of the interrupt with ID408" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS407 ,Controls Non-secure access of the interrupt with ID407" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS406 ,Controls Non-secure access of the interrupt with ID406" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS405 ,Controls Non-secure access of the interrupt with ID405" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS404 ,Controls Non-secure access of the interrupt with ID404" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS403 ,Controls Non-secure access of the interrupt with ID403" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS402 ,Controls Non-secure access of the interrupt with ID402" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS401 ,Controls Non-secure access of the interrupt with ID401" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS400 ,Controls Non-secure access of the interrupt with ID400" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE64++0x03 hide.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE68))) group.long 0xE68++0x03 line.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26" bitfld.long 0x00 30.--31. " NS_ACCESS431 ,Controls Non-secure access of the interrupt with ID431" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS430 ,Controls Non-secure access of the interrupt with ID430" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS429 ,Controls Non-secure access of the interrupt with ID429" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS428 ,Controls Non-secure access of the interrupt with ID428" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS427 ,Controls Non-secure access of the interrupt with ID427" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS426 ,Controls Non-secure access of the interrupt with ID426" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS425 ,Controls Non-secure access of the interrupt with ID425" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS424 ,Controls Non-secure access of the interrupt with ID424" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS423 ,Controls Non-secure access of the interrupt with ID423" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS422 ,Controls Non-secure access of the interrupt with ID422" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS421 ,Controls Non-secure access of the interrupt with ID421" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS420 ,Controls Non-secure access of the interrupt with ID420" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS419 ,Controls Non-secure access of the interrupt with ID419" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS418 ,Controls Non-secure access of the interrupt with ID418" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS417 ,Controls Non-secure access of the interrupt with ID417" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS416 ,Controls Non-secure access of the interrupt with ID416" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE68++0x03 hide.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE6C))) group.long 0xE6C++0x03 line.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27" bitfld.long 0x00 30.--31. " NS_ACCESS447 ,Controls Non-secure access of the interrupt with ID447" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS446 ,Controls Non-secure access of the interrupt with ID446" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS445 ,Controls Non-secure access of the interrupt with ID445" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS444 ,Controls Non-secure access of the interrupt with ID444" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS443 ,Controls Non-secure access of the interrupt with ID443" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS442 ,Controls Non-secure access of the interrupt with ID442" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS441 ,Controls Non-secure access of the interrupt with ID441" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS440 ,Controls Non-secure access of the interrupt with ID440" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS439 ,Controls Non-secure access of the interrupt with ID439" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS438 ,Controls Non-secure access of the interrupt with ID438" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS437 ,Controls Non-secure access of the interrupt with ID437" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS436 ,Controls Non-secure access of the interrupt with ID436" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS435 ,Controls Non-secure access of the interrupt with ID435" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS434 ,Controls Non-secure access of the interrupt with ID434" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS433 ,Controls Non-secure access of the interrupt with ID433" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS432 ,Controls Non-secure access of the interrupt with ID432" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE6C++0x03 hide.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE70))) group.long 0xE70++0x03 line.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28" bitfld.long 0x00 30.--31. " NS_ACCESS463 ,Controls Non-secure access of the interrupt with ID463" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS462 ,Controls Non-secure access of the interrupt with ID462" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS461 ,Controls Non-secure access of the interrupt with ID461" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS460 ,Controls Non-secure access of the interrupt with ID460" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS459 ,Controls Non-secure access of the interrupt with ID459" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS458 ,Controls Non-secure access of the interrupt with ID458" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS457 ,Controls Non-secure access of the interrupt with ID457" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS456 ,Controls Non-secure access of the interrupt with ID456" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS455 ,Controls Non-secure access of the interrupt with ID455" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS454 ,Controls Non-secure access of the interrupt with ID454" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS453 ,Controls Non-secure access of the interrupt with ID453" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS452 ,Controls Non-secure access of the interrupt with ID452" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS451 ,Controls Non-secure access of the interrupt with ID451" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS450 ,Controls Non-secure access of the interrupt with ID450" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS449 ,Controls Non-secure access of the interrupt with ID449" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS448 ,Controls Non-secure access of the interrupt with ID448" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE70++0x03 hide.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE74))) group.long 0xE74++0x03 line.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29" bitfld.long 0x00 30.--31. " NS_ACCESS479 ,Controls Non-secure access of the interrupt with ID479" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS478 ,Controls Non-secure access of the interrupt with ID478" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS477 ,Controls Non-secure access of the interrupt with ID477" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS476 ,Controls Non-secure access of the interrupt with ID476" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS475 ,Controls Non-secure access of the interrupt with ID475" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS474 ,Controls Non-secure access of the interrupt with ID474" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS473 ,Controls Non-secure access of the interrupt with ID473" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS472 ,Controls Non-secure access of the interrupt with ID472" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS471 ,Controls Non-secure access of the interrupt with ID471" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS470 ,Controls Non-secure access of the interrupt with ID470" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS469 ,Controls Non-secure access of the interrupt with ID469" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS468 ,Controls Non-secure access of the interrupt with ID468" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS467 ,Controls Non-secure access of the interrupt with ID467" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS466 ,Controls Non-secure access of the interrupt with ID466" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS465 ,Controls Non-secure access of the interrupt with ID465" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS464 ,Controls Non-secure access of the interrupt with ID464" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE74++0x03 hide.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE78))) group.long 0xE78++0x03 line.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30" bitfld.long 0x00 30.--31. " NS_ACCESS495 ,Controls Non-secure access of the interrupt with ID495" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS494 ,Controls Non-secure access of the interrupt with ID494" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS493 ,Controls Non-secure access of the interrupt with ID493" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS492 ,Controls Non-secure access of the interrupt with ID492" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS491 ,Controls Non-secure access of the interrupt with ID491" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS490 ,Controls Non-secure access of the interrupt with ID490" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS489 ,Controls Non-secure access of the interrupt with ID489" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS488 ,Controls Non-secure access of the interrupt with ID488" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS487 ,Controls Non-secure access of the interrupt with ID487" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS486 ,Controls Non-secure access of the interrupt with ID486" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS485 ,Controls Non-secure access of the interrupt with ID485" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS484 ,Controls Non-secure access of the interrupt with ID484" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS483 ,Controls Non-secure access of the interrupt with ID483" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS482 ,Controls Non-secure access of the interrupt with ID482" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS481 ,Controls Non-secure access of the interrupt with ID481" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS480 ,Controls Non-secure access of the interrupt with ID480" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE78++0x03 hide.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE7C))) group.long 0xE7C++0x03 line.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31" bitfld.long 0x00 30.--31. " NS_ACCESS511 ,Controls Non-secure access of the interrupt with ID511" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS510 ,Controls Non-secure access of the interrupt with ID510" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS509 ,Controls Non-secure access of the interrupt with ID509" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS508 ,Controls Non-secure access of the interrupt with ID508" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS507 ,Controls Non-secure access of the interrupt with ID507" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS506 ,Controls Non-secure access of the interrupt with ID506" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS505 ,Controls Non-secure access of the interrupt with ID505" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS504 ,Controls Non-secure access of the interrupt with ID504" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS503 ,Controls Non-secure access of the interrupt with ID503" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS502 ,Controls Non-secure access of the interrupt with ID502" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS501 ,Controls Non-secure access of the interrupt with ID501" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS500 ,Controls Non-secure access of the interrupt with ID500" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS499 ,Controls Non-secure access of the interrupt with ID499" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS498 ,Controls Non-secure access of the interrupt with ID498" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS497 ,Controls Non-secure access of the interrupt with ID497" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS496 ,Controls Non-secure access of the interrupt with ID496" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE7C++0x03 hide.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE80))) group.long 0xE80++0x03 line.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32" bitfld.long 0x00 30.--31. " NS_ACCESS527 ,Controls Non-secure access of the interrupt with ID527" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS526 ,Controls Non-secure access of the interrupt with ID526" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS525 ,Controls Non-secure access of the interrupt with ID525" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS524 ,Controls Non-secure access of the interrupt with ID524" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS523 ,Controls Non-secure access of the interrupt with ID523" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS522 ,Controls Non-secure access of the interrupt with ID522" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS521 ,Controls Non-secure access of the interrupt with ID521" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS520 ,Controls Non-secure access of the interrupt with ID520" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS519 ,Controls Non-secure access of the interrupt with ID519" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS518 ,Controls Non-secure access of the interrupt with ID518" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS517 ,Controls Non-secure access of the interrupt with ID517" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS516 ,Controls Non-secure access of the interrupt with ID516" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS515 ,Controls Non-secure access of the interrupt with ID515" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS514 ,Controls Non-secure access of the interrupt with ID514" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS513 ,Controls Non-secure access of the interrupt with ID513" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS512 ,Controls Non-secure access of the interrupt with ID512" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE80++0x03 hide.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE84))) group.long 0xE84++0x03 line.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33" bitfld.long 0x00 30.--31. " NS_ACCESS543 ,Controls Non-secure access of the interrupt with ID543" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS542 ,Controls Non-secure access of the interrupt with ID542" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS541 ,Controls Non-secure access of the interrupt with ID541" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS540 ,Controls Non-secure access of the interrupt with ID540" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS539 ,Controls Non-secure access of the interrupt with ID539" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS538 ,Controls Non-secure access of the interrupt with ID538" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS537 ,Controls Non-secure access of the interrupt with ID537" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS536 ,Controls Non-secure access of the interrupt with ID536" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS535 ,Controls Non-secure access of the interrupt with ID535" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS534 ,Controls Non-secure access of the interrupt with ID534" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS533 ,Controls Non-secure access of the interrupt with ID533" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS532 ,Controls Non-secure access of the interrupt with ID532" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS531 ,Controls Non-secure access of the interrupt with ID531" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS530 ,Controls Non-secure access of the interrupt with ID530" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS529 ,Controls Non-secure access of the interrupt with ID529" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS528 ,Controls Non-secure access of the interrupt with ID528" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE84++0x03 hide.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE88))) group.long 0xE88++0x03 line.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34" bitfld.long 0x00 30.--31. " NS_ACCESS559 ,Controls Non-secure access of the interrupt with ID559" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS558 ,Controls Non-secure access of the interrupt with ID558" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS557 ,Controls Non-secure access of the interrupt with ID557" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS556 ,Controls Non-secure access of the interrupt with ID556" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS555 ,Controls Non-secure access of the interrupt with ID555" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS554 ,Controls Non-secure access of the interrupt with ID554" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS553 ,Controls Non-secure access of the interrupt with ID553" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS552 ,Controls Non-secure access of the interrupt with ID552" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS551 ,Controls Non-secure access of the interrupt with ID551" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS550 ,Controls Non-secure access of the interrupt with ID550" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS549 ,Controls Non-secure access of the interrupt with ID549" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS548 ,Controls Non-secure access of the interrupt with ID548" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS547 ,Controls Non-secure access of the interrupt with ID547" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS546 ,Controls Non-secure access of the interrupt with ID546" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS545 ,Controls Non-secure access of the interrupt with ID545" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS544 ,Controls Non-secure access of the interrupt with ID544" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE88++0x03 hide.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8C))) group.long 0xE8C++0x03 line.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35" bitfld.long 0x00 30.--31. " NS_ACCESS575 ,Controls Non-secure access of the interrupt with ID575" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS574 ,Controls Non-secure access of the interrupt with ID574" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS573 ,Controls Non-secure access of the interrupt with ID573" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS572 ,Controls Non-secure access of the interrupt with ID572" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS571 ,Controls Non-secure access of the interrupt with ID571" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS570 ,Controls Non-secure access of the interrupt with ID570" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS569 ,Controls Non-secure access of the interrupt with ID569" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS568 ,Controls Non-secure access of the interrupt with ID568" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS567 ,Controls Non-secure access of the interrupt with ID567" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS566 ,Controls Non-secure access of the interrupt with ID566" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS565 ,Controls Non-secure access of the interrupt with ID565" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS564 ,Controls Non-secure access of the interrupt with ID564" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS563 ,Controls Non-secure access of the interrupt with ID563" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS562 ,Controls Non-secure access of the interrupt with ID562" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS561 ,Controls Non-secure access of the interrupt with ID561" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS560 ,Controls Non-secure access of the interrupt with ID560" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE8C++0x03 hide.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE90))) group.long 0xE90++0x03 line.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36" bitfld.long 0x00 30.--31. " NS_ACCESS591 ,Controls Non-secure access of the interrupt with ID591" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS590 ,Controls Non-secure access of the interrupt with ID590" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS589 ,Controls Non-secure access of the interrupt with ID589" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS588 ,Controls Non-secure access of the interrupt with ID588" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS587 ,Controls Non-secure access of the interrupt with ID587" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS586 ,Controls Non-secure access of the interrupt with ID586" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS585 ,Controls Non-secure access of the interrupt with ID585" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS584 ,Controls Non-secure access of the interrupt with ID584" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS583 ,Controls Non-secure access of the interrupt with ID583" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS582 ,Controls Non-secure access of the interrupt with ID582" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS581 ,Controls Non-secure access of the interrupt with ID581" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS580 ,Controls Non-secure access of the interrupt with ID580" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS579 ,Controls Non-secure access of the interrupt with ID579" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS578 ,Controls Non-secure access of the interrupt with ID578" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS577 ,Controls Non-secure access of the interrupt with ID577" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS576 ,Controls Non-secure access of the interrupt with ID576" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE90++0x03 hide.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE94))) group.long 0xE94++0x03 line.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37" bitfld.long 0x00 30.--31. " NS_ACCESS607 ,Controls Non-secure access of the interrupt with ID607" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS606 ,Controls Non-secure access of the interrupt with ID606" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS605 ,Controls Non-secure access of the interrupt with ID605" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS604 ,Controls Non-secure access of the interrupt with ID604" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS603 ,Controls Non-secure access of the interrupt with ID603" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS602 ,Controls Non-secure access of the interrupt with ID602" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS601 ,Controls Non-secure access of the interrupt with ID601" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS600 ,Controls Non-secure access of the interrupt with ID600" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS599 ,Controls Non-secure access of the interrupt with ID599" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS598 ,Controls Non-secure access of the interrupt with ID598" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS597 ,Controls Non-secure access of the interrupt with ID597" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS596 ,Controls Non-secure access of the interrupt with ID596" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS595 ,Controls Non-secure access of the interrupt with ID595" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS594 ,Controls Non-secure access of the interrupt with ID594" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS593 ,Controls Non-secure access of the interrupt with ID593" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS592 ,Controls Non-secure access of the interrupt with ID592" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE94++0x03 hide.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE98))) group.long 0xE98++0x03 line.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38" bitfld.long 0x00 30.--31. " NS_ACCESS623 ,Controls Non-secure access of the interrupt with ID623" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS622 ,Controls Non-secure access of the interrupt with ID622" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS621 ,Controls Non-secure access of the interrupt with ID621" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS620 ,Controls Non-secure access of the interrupt with ID620" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS619 ,Controls Non-secure access of the interrupt with ID619" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS618 ,Controls Non-secure access of the interrupt with ID618" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS617 ,Controls Non-secure access of the interrupt with ID617" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS616 ,Controls Non-secure access of the interrupt with ID616" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS615 ,Controls Non-secure access of the interrupt with ID615" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS614 ,Controls Non-secure access of the interrupt with ID614" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS613 ,Controls Non-secure access of the interrupt with ID613" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS612 ,Controls Non-secure access of the interrupt with ID612" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS611 ,Controls Non-secure access of the interrupt with ID611" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS610 ,Controls Non-secure access of the interrupt with ID610" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS609 ,Controls Non-secure access of the interrupt with ID609" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS608 ,Controls Non-secure access of the interrupt with ID608" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE98++0x03 hide.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE9C))) group.long 0xE9C++0x03 line.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39" bitfld.long 0x00 30.--31. " NS_ACCESS639 ,Controls Non-secure access of the interrupt with ID639" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS638 ,Controls Non-secure access of the interrupt with ID638" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS637 ,Controls Non-secure access of the interrupt with ID637" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS636 ,Controls Non-secure access of the interrupt with ID636" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS635 ,Controls Non-secure access of the interrupt with ID635" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS634 ,Controls Non-secure access of the interrupt with ID634" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS633 ,Controls Non-secure access of the interrupt with ID633" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS632 ,Controls Non-secure access of the interrupt with ID632" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS631 ,Controls Non-secure access of the interrupt with ID631" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS630 ,Controls Non-secure access of the interrupt with ID630" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS629 ,Controls Non-secure access of the interrupt with ID629" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS628 ,Controls Non-secure access of the interrupt with ID628" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS627 ,Controls Non-secure access of the interrupt with ID627" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS626 ,Controls Non-secure access of the interrupt with ID626" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS625 ,Controls Non-secure access of the interrupt with ID625" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS624 ,Controls Non-secure access of the interrupt with ID624" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE9C++0x03 hide.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA0))) group.long 0xEA0++0x03 line.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40" bitfld.long 0x00 30.--31. " NS_ACCESS655 ,Controls Non-secure access of the interrupt with ID655" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS654 ,Controls Non-secure access of the interrupt with ID654" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS653 ,Controls Non-secure access of the interrupt with ID653" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS652 ,Controls Non-secure access of the interrupt with ID652" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS651 ,Controls Non-secure access of the interrupt with ID651" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS650 ,Controls Non-secure access of the interrupt with ID650" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS649 ,Controls Non-secure access of the interrupt with ID649" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS648 ,Controls Non-secure access of the interrupt with ID648" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS647 ,Controls Non-secure access of the interrupt with ID647" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS646 ,Controls Non-secure access of the interrupt with ID646" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS645 ,Controls Non-secure access of the interrupt with ID645" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS644 ,Controls Non-secure access of the interrupt with ID644" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS643 ,Controls Non-secure access of the interrupt with ID643" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS642 ,Controls Non-secure access of the interrupt with ID642" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS641 ,Controls Non-secure access of the interrupt with ID641" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS640 ,Controls Non-secure access of the interrupt with ID640" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA0++0x03 hide.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA4))) group.long 0xEA4++0x03 line.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41" bitfld.long 0x00 30.--31. " NS_ACCESS671 ,Controls Non-secure access of the interrupt with ID671" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS670 ,Controls Non-secure access of the interrupt with ID670" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS669 ,Controls Non-secure access of the interrupt with ID669" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS668 ,Controls Non-secure access of the interrupt with ID668" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS667 ,Controls Non-secure access of the interrupt with ID667" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS666 ,Controls Non-secure access of the interrupt with ID666" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS665 ,Controls Non-secure access of the interrupt with ID665" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS664 ,Controls Non-secure access of the interrupt with ID664" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS663 ,Controls Non-secure access of the interrupt with ID663" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS662 ,Controls Non-secure access of the interrupt with ID662" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS661 ,Controls Non-secure access of the interrupt with ID661" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS660 ,Controls Non-secure access of the interrupt with ID660" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS659 ,Controls Non-secure access of the interrupt with ID659" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS658 ,Controls Non-secure access of the interrupt with ID658" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS657 ,Controls Non-secure access of the interrupt with ID657" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS656 ,Controls Non-secure access of the interrupt with ID656" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA4++0x03 hide.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA8))) group.long 0xEA8++0x03 line.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42" bitfld.long 0x00 30.--31. " NS_ACCESS687 ,Controls Non-secure access of the interrupt with ID687" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS686 ,Controls Non-secure access of the interrupt with ID686" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS685 ,Controls Non-secure access of the interrupt with ID685" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS684 ,Controls Non-secure access of the interrupt with ID684" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS683 ,Controls Non-secure access of the interrupt with ID683" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS682 ,Controls Non-secure access of the interrupt with ID682" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS681 ,Controls Non-secure access of the interrupt with ID681" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS680 ,Controls Non-secure access of the interrupt with ID680" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS679 ,Controls Non-secure access of the interrupt with ID679" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS678 ,Controls Non-secure access of the interrupt with ID678" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS677 ,Controls Non-secure access of the interrupt with ID677" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS676 ,Controls Non-secure access of the interrupt with ID676" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS675 ,Controls Non-secure access of the interrupt with ID675" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS674 ,Controls Non-secure access of the interrupt with ID674" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS673 ,Controls Non-secure access of the interrupt with ID673" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS672 ,Controls Non-secure access of the interrupt with ID672" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA8++0x03 hide.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEAC))) group.long 0xEAC++0x03 line.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43" bitfld.long 0x00 30.--31. " NS_ACCESS703 ,Controls Non-secure access of the interrupt with ID703" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS702 ,Controls Non-secure access of the interrupt with ID702" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS701 ,Controls Non-secure access of the interrupt with ID701" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS700 ,Controls Non-secure access of the interrupt with ID700" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS699 ,Controls Non-secure access of the interrupt with ID699" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS698 ,Controls Non-secure access of the interrupt with ID698" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS697 ,Controls Non-secure access of the interrupt with ID697" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS696 ,Controls Non-secure access of the interrupt with ID696" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS695 ,Controls Non-secure access of the interrupt with ID695" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS694 ,Controls Non-secure access of the interrupt with ID694" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS693 ,Controls Non-secure access of the interrupt with ID693" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS692 ,Controls Non-secure access of the interrupt with ID692" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS691 ,Controls Non-secure access of the interrupt with ID691" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS690 ,Controls Non-secure access of the interrupt with ID690" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS689 ,Controls Non-secure access of the interrupt with ID689" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS688 ,Controls Non-secure access of the interrupt with ID688" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEAC++0x03 hide.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB0))) group.long 0xEB0++0x03 line.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44" bitfld.long 0x00 30.--31. " NS_ACCESS719 ,Controls Non-secure access of the interrupt with ID719" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS718 ,Controls Non-secure access of the interrupt with ID718" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS717 ,Controls Non-secure access of the interrupt with ID717" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS716 ,Controls Non-secure access of the interrupt with ID716" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS715 ,Controls Non-secure access of the interrupt with ID715" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS714 ,Controls Non-secure access of the interrupt with ID714" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS713 ,Controls Non-secure access of the interrupt with ID713" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS712 ,Controls Non-secure access of the interrupt with ID712" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS711 ,Controls Non-secure access of the interrupt with ID711" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS710 ,Controls Non-secure access of the interrupt with ID710" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS709 ,Controls Non-secure access of the interrupt with ID709" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS708 ,Controls Non-secure access of the interrupt with ID708" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS707 ,Controls Non-secure access of the interrupt with ID707" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS706 ,Controls Non-secure access of the interrupt with ID706" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS705 ,Controls Non-secure access of the interrupt with ID705" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS704 ,Controls Non-secure access of the interrupt with ID704" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB0++0x03 hide.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB4))) group.long 0xEB4++0x03 line.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45" bitfld.long 0x00 30.--31. " NS_ACCESS735 ,Controls Non-secure access of the interrupt with ID735" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS734 ,Controls Non-secure access of the interrupt with ID734" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS733 ,Controls Non-secure access of the interrupt with ID733" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS732 ,Controls Non-secure access of the interrupt with ID732" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS731 ,Controls Non-secure access of the interrupt with ID731" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS730 ,Controls Non-secure access of the interrupt with ID730" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS729 ,Controls Non-secure access of the interrupt with ID729" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS728 ,Controls Non-secure access of the interrupt with ID728" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS727 ,Controls Non-secure access of the interrupt with ID727" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS726 ,Controls Non-secure access of the interrupt with ID726" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS725 ,Controls Non-secure access of the interrupt with ID725" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS724 ,Controls Non-secure access of the interrupt with ID724" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS723 ,Controls Non-secure access of the interrupt with ID723" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS722 ,Controls Non-secure access of the interrupt with ID722" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS721 ,Controls Non-secure access of the interrupt with ID721" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS720 ,Controls Non-secure access of the interrupt with ID720" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB4++0x03 hide.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB8))) group.long 0xEB8++0x03 line.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46" bitfld.long 0x00 30.--31. " NS_ACCESS751 ,Controls Non-secure access of the interrupt with ID751" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS750 ,Controls Non-secure access of the interrupt with ID750" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS749 ,Controls Non-secure access of the interrupt with ID749" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS748 ,Controls Non-secure access of the interrupt with ID748" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS747 ,Controls Non-secure access of the interrupt with ID747" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS746 ,Controls Non-secure access of the interrupt with ID746" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS745 ,Controls Non-secure access of the interrupt with ID745" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS744 ,Controls Non-secure access of the interrupt with ID744" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS743 ,Controls Non-secure access of the interrupt with ID743" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS742 ,Controls Non-secure access of the interrupt with ID742" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS741 ,Controls Non-secure access of the interrupt with ID741" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS740 ,Controls Non-secure access of the interrupt with ID740" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS739 ,Controls Non-secure access of the interrupt with ID739" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS738 ,Controls Non-secure access of the interrupt with ID738" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS737 ,Controls Non-secure access of the interrupt with ID737" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS736 ,Controls Non-secure access of the interrupt with ID736" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB8++0x03 hide.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEBC))) group.long 0xEBC++0x03 line.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47" bitfld.long 0x00 30.--31. " NS_ACCESS767 ,Controls Non-secure access of the interrupt with ID767" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS766 ,Controls Non-secure access of the interrupt with ID766" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS765 ,Controls Non-secure access of the interrupt with ID765" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS764 ,Controls Non-secure access of the interrupt with ID764" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS763 ,Controls Non-secure access of the interrupt with ID763" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS762 ,Controls Non-secure access of the interrupt with ID762" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS761 ,Controls Non-secure access of the interrupt with ID761" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS760 ,Controls Non-secure access of the interrupt with ID760" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS759 ,Controls Non-secure access of the interrupt with ID759" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS758 ,Controls Non-secure access of the interrupt with ID758" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS757 ,Controls Non-secure access of the interrupt with ID757" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS756 ,Controls Non-secure access of the interrupt with ID756" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS755 ,Controls Non-secure access of the interrupt with ID755" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS754 ,Controls Non-secure access of the interrupt with ID754" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS753 ,Controls Non-secure access of the interrupt with ID753" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS752 ,Controls Non-secure access of the interrupt with ID752" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEBC++0x03 hide.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC0))) group.long 0xEC0++0x03 line.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48" bitfld.long 0x00 30.--31. " NS_ACCESS783 ,Controls Non-secure access of the interrupt with ID783" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS782 ,Controls Non-secure access of the interrupt with ID782" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS781 ,Controls Non-secure access of the interrupt with ID781" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS780 ,Controls Non-secure access of the interrupt with ID780" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS779 ,Controls Non-secure access of the interrupt with ID779" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS778 ,Controls Non-secure access of the interrupt with ID778" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS777 ,Controls Non-secure access of the interrupt with ID777" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS776 ,Controls Non-secure access of the interrupt with ID776" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS775 ,Controls Non-secure access of the interrupt with ID775" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS774 ,Controls Non-secure access of the interrupt with ID774" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS773 ,Controls Non-secure access of the interrupt with ID773" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS772 ,Controls Non-secure access of the interrupt with ID772" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS771 ,Controls Non-secure access of the interrupt with ID771" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS770 ,Controls Non-secure access of the interrupt with ID770" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS769 ,Controls Non-secure access of the interrupt with ID769" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS768 ,Controls Non-secure access of the interrupt with ID768" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC0++0x03 hide.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC4))) group.long 0xEC4++0x03 line.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49" bitfld.long 0x00 30.--31. " NS_ACCESS799 ,Controls Non-secure access of the interrupt with ID799" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS798 ,Controls Non-secure access of the interrupt with ID798" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS797 ,Controls Non-secure access of the interrupt with ID797" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS796 ,Controls Non-secure access of the interrupt with ID796" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS795 ,Controls Non-secure access of the interrupt with ID795" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS794 ,Controls Non-secure access of the interrupt with ID794" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS793 ,Controls Non-secure access of the interrupt with ID793" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS792 ,Controls Non-secure access of the interrupt with ID792" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS791 ,Controls Non-secure access of the interrupt with ID791" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS790 ,Controls Non-secure access of the interrupt with ID790" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS789 ,Controls Non-secure access of the interrupt with ID789" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS788 ,Controls Non-secure access of the interrupt with ID788" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS787 ,Controls Non-secure access of the interrupt with ID787" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS786 ,Controls Non-secure access of the interrupt with ID786" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS785 ,Controls Non-secure access of the interrupt with ID785" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS784 ,Controls Non-secure access of the interrupt with ID784" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC4++0x03 hide.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC8))) group.long 0xEC8++0x03 line.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50" bitfld.long 0x00 30.--31. " NS_ACCESS815 ,Controls Non-secure access of the interrupt with ID815" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS814 ,Controls Non-secure access of the interrupt with ID814" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS813 ,Controls Non-secure access of the interrupt with ID813" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS812 ,Controls Non-secure access of the interrupt with ID812" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS811 ,Controls Non-secure access of the interrupt with ID811" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS810 ,Controls Non-secure access of the interrupt with ID810" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS809 ,Controls Non-secure access of the interrupt with ID809" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS808 ,Controls Non-secure access of the interrupt with ID808" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS807 ,Controls Non-secure access of the interrupt with ID807" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS806 ,Controls Non-secure access of the interrupt with ID806" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS805 ,Controls Non-secure access of the interrupt with ID805" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS804 ,Controls Non-secure access of the interrupt with ID804" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS803 ,Controls Non-secure access of the interrupt with ID803" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS802 ,Controls Non-secure access of the interrupt with ID802" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS801 ,Controls Non-secure access of the interrupt with ID801" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS800 ,Controls Non-secure access of the interrupt with ID800" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC8++0x03 hide.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xECC))) group.long 0xECC++0x03 line.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51" bitfld.long 0x00 30.--31. " NS_ACCESS831 ,Controls Non-secure access of the interrupt with ID831" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS830 ,Controls Non-secure access of the interrupt with ID830" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS829 ,Controls Non-secure access of the interrupt with ID829" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS828 ,Controls Non-secure access of the interrupt with ID828" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS827 ,Controls Non-secure access of the interrupt with ID827" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS826 ,Controls Non-secure access of the interrupt with ID826" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS825 ,Controls Non-secure access of the interrupt with ID825" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS824 ,Controls Non-secure access of the interrupt with ID824" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS823 ,Controls Non-secure access of the interrupt with ID823" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS822 ,Controls Non-secure access of the interrupt with ID822" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS821 ,Controls Non-secure access of the interrupt with ID821" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS820 ,Controls Non-secure access of the interrupt with ID820" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS819 ,Controls Non-secure access of the interrupt with ID819" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS818 ,Controls Non-secure access of the interrupt with ID818" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS817 ,Controls Non-secure access of the interrupt with ID817" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS816 ,Controls Non-secure access of the interrupt with ID816" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xECC++0x03 hide.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED0))) group.long 0xED0++0x03 line.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52" bitfld.long 0x00 30.--31. " NS_ACCESS847 ,Controls Non-secure access of the interrupt with ID847" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS846 ,Controls Non-secure access of the interrupt with ID846" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS845 ,Controls Non-secure access of the interrupt with ID845" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS844 ,Controls Non-secure access of the interrupt with ID844" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS843 ,Controls Non-secure access of the interrupt with ID843" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS842 ,Controls Non-secure access of the interrupt with ID842" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS841 ,Controls Non-secure access of the interrupt with ID841" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS840 ,Controls Non-secure access of the interrupt with ID840" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS839 ,Controls Non-secure access of the interrupt with ID839" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS838 ,Controls Non-secure access of the interrupt with ID838" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS837 ,Controls Non-secure access of the interrupt with ID837" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS836 ,Controls Non-secure access of the interrupt with ID836" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS835 ,Controls Non-secure access of the interrupt with ID835" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS834 ,Controls Non-secure access of the interrupt with ID834" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS833 ,Controls Non-secure access of the interrupt with ID833" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS832 ,Controls Non-secure access of the interrupt with ID832" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED0++0x03 hide.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED4))) group.long 0xED4++0x03 line.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53" bitfld.long 0x00 30.--31. " NS_ACCESS863 ,Controls Non-secure access of the interrupt with ID863" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS862 ,Controls Non-secure access of the interrupt with ID862" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS861 ,Controls Non-secure access of the interrupt with ID861" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS860 ,Controls Non-secure access of the interrupt with ID860" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS859 ,Controls Non-secure access of the interrupt with ID859" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS858 ,Controls Non-secure access of the interrupt with ID858" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS857 ,Controls Non-secure access of the interrupt with ID857" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS856 ,Controls Non-secure access of the interrupt with ID856" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS855 ,Controls Non-secure access of the interrupt with ID855" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS854 ,Controls Non-secure access of the interrupt with ID854" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS853 ,Controls Non-secure access of the interrupt with ID853" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS852 ,Controls Non-secure access of the interrupt with ID852" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS851 ,Controls Non-secure access of the interrupt with ID851" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS850 ,Controls Non-secure access of the interrupt with ID850" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS849 ,Controls Non-secure access of the interrupt with ID849" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS848 ,Controls Non-secure access of the interrupt with ID848" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED4++0x03 hide.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED8))) group.long 0xED8++0x03 line.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54" bitfld.long 0x00 30.--31. " NS_ACCESS879 ,Controls Non-secure access of the interrupt with ID879" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS878 ,Controls Non-secure access of the interrupt with ID878" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS877 ,Controls Non-secure access of the interrupt with ID877" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS876 ,Controls Non-secure access of the interrupt with ID876" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS875 ,Controls Non-secure access of the interrupt with ID875" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS874 ,Controls Non-secure access of the interrupt with ID874" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS873 ,Controls Non-secure access of the interrupt with ID873" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS872 ,Controls Non-secure access of the interrupt with ID872" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS871 ,Controls Non-secure access of the interrupt with ID871" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS870 ,Controls Non-secure access of the interrupt with ID870" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS869 ,Controls Non-secure access of the interrupt with ID869" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS868 ,Controls Non-secure access of the interrupt with ID868" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS867 ,Controls Non-secure access of the interrupt with ID867" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS866 ,Controls Non-secure access of the interrupt with ID866" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS865 ,Controls Non-secure access of the interrupt with ID865" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS864 ,Controls Non-secure access of the interrupt with ID864" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED8++0x03 hide.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEDC))) group.long 0xEDC++0x03 line.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55" bitfld.long 0x00 30.--31. " NS_ACCESS895 ,Controls Non-secure access of the interrupt with ID895" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS894 ,Controls Non-secure access of the interrupt with ID894" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS893 ,Controls Non-secure access of the interrupt with ID893" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS892 ,Controls Non-secure access of the interrupt with ID892" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS891 ,Controls Non-secure access of the interrupt with ID891" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS890 ,Controls Non-secure access of the interrupt with ID890" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS889 ,Controls Non-secure access of the interrupt with ID889" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS888 ,Controls Non-secure access of the interrupt with ID888" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS887 ,Controls Non-secure access of the interrupt with ID887" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS886 ,Controls Non-secure access of the interrupt with ID886" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS885 ,Controls Non-secure access of the interrupt with ID885" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS884 ,Controls Non-secure access of the interrupt with ID884" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS883 ,Controls Non-secure access of the interrupt with ID883" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS882 ,Controls Non-secure access of the interrupt with ID882" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS881 ,Controls Non-secure access of the interrupt with ID881" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS880 ,Controls Non-secure access of the interrupt with ID880" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEDC++0x03 hide.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE0))) group.long 0xEE0++0x03 line.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56" bitfld.long 0x00 30.--31. " NS_ACCESS911 ,Controls Non-secure access of the interrupt with ID911" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS910 ,Controls Non-secure access of the interrupt with ID910" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS909 ,Controls Non-secure access of the interrupt with ID909" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS908 ,Controls Non-secure access of the interrupt with ID908" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS907 ,Controls Non-secure access of the interrupt with ID907" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS906 ,Controls Non-secure access of the interrupt with ID906" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS905 ,Controls Non-secure access of the interrupt with ID905" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS904 ,Controls Non-secure access of the interrupt with ID904" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS903 ,Controls Non-secure access of the interrupt with ID903" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS902 ,Controls Non-secure access of the interrupt with ID902" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS901 ,Controls Non-secure access of the interrupt with ID901" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS900 ,Controls Non-secure access of the interrupt with ID900" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS899 ,Controls Non-secure access of the interrupt with ID899" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS898 ,Controls Non-secure access of the interrupt with ID898" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS897 ,Controls Non-secure access of the interrupt with ID897" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS896 ,Controls Non-secure access of the interrupt with ID896" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE0++0x03 hide.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE4))) group.long 0xEE4++0x03 line.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57" bitfld.long 0x00 30.--31. " NS_ACCESS927 ,Controls Non-secure access of the interrupt with ID927" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS926 ,Controls Non-secure access of the interrupt with ID926" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS925 ,Controls Non-secure access of the interrupt with ID925" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS924 ,Controls Non-secure access of the interrupt with ID924" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS923 ,Controls Non-secure access of the interrupt with ID923" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS922 ,Controls Non-secure access of the interrupt with ID922" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS921 ,Controls Non-secure access of the interrupt with ID921" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS920 ,Controls Non-secure access of the interrupt with ID920" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS919 ,Controls Non-secure access of the interrupt with ID919" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS918 ,Controls Non-secure access of the interrupt with ID918" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS917 ,Controls Non-secure access of the interrupt with ID917" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS916 ,Controls Non-secure access of the interrupt with ID916" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS915 ,Controls Non-secure access of the interrupt with ID915" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS914 ,Controls Non-secure access of the interrupt with ID914" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS913 ,Controls Non-secure access of the interrupt with ID913" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS912 ,Controls Non-secure access of the interrupt with ID912" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE4++0x03 hide.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE8))) group.long 0xEE8++0x03 line.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58" bitfld.long 0x00 30.--31. " NS_ACCESS943 ,Controls Non-secure access of the interrupt with ID943" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS942 ,Controls Non-secure access of the interrupt with ID942" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS941 ,Controls Non-secure access of the interrupt with ID941" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS940 ,Controls Non-secure access of the interrupt with ID940" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS939 ,Controls Non-secure access of the interrupt with ID939" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS938 ,Controls Non-secure access of the interrupt with ID938" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS937 ,Controls Non-secure access of the interrupt with ID937" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS936 ,Controls Non-secure access of the interrupt with ID936" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS935 ,Controls Non-secure access of the interrupt with ID935" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS934 ,Controls Non-secure access of the interrupt with ID934" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS933 ,Controls Non-secure access of the interrupt with ID933" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS932 ,Controls Non-secure access of the interrupt with ID932" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS931 ,Controls Non-secure access of the interrupt with ID931" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS930 ,Controls Non-secure access of the interrupt with ID930" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS929 ,Controls Non-secure access of the interrupt with ID929" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS928 ,Controls Non-secure access of the interrupt with ID928" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE8++0x03 hide.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEEC))) group.long 0xEEC++0x03 line.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59" bitfld.long 0x00 30.--31. " NS_ACCESS959 ,Controls Non-secure access of the interrupt with ID959" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS958 ,Controls Non-secure access of the interrupt with ID958" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS957 ,Controls Non-secure access of the interrupt with ID957" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS956 ,Controls Non-secure access of the interrupt with ID956" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS955 ,Controls Non-secure access of the interrupt with ID955" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS954 ,Controls Non-secure access of the interrupt with ID954" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS953 ,Controls Non-secure access of the interrupt with ID953" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS952 ,Controls Non-secure access of the interrupt with ID952" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS951 ,Controls Non-secure access of the interrupt with ID951" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS950 ,Controls Non-secure access of the interrupt with ID950" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS949 ,Controls Non-secure access of the interrupt with ID949" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS948 ,Controls Non-secure access of the interrupt with ID948" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS947 ,Controls Non-secure access of the interrupt with ID947" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS946 ,Controls Non-secure access of the interrupt with ID946" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS945 ,Controls Non-secure access of the interrupt with ID945" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS944 ,Controls Non-secure access of the interrupt with ID944" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEEC++0x03 hide.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF0))) group.long 0xEF0++0x03 line.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60" bitfld.long 0x00 30.--31. " NS_ACCESS975 ,Controls Non-secure access of the interrupt with ID975" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS974 ,Controls Non-secure access of the interrupt with ID974" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS973 ,Controls Non-secure access of the interrupt with ID973" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS972 ,Controls Non-secure access of the interrupt with ID972" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS971 ,Controls Non-secure access of the interrupt with ID971" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS970 ,Controls Non-secure access of the interrupt with ID970" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS969 ,Controls Non-secure access of the interrupt with ID969" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS968 ,Controls Non-secure access of the interrupt with ID968" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS967 ,Controls Non-secure access of the interrupt with ID967" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS966 ,Controls Non-secure access of the interrupt with ID966" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS965 ,Controls Non-secure access of the interrupt with ID965" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS964 ,Controls Non-secure access of the interrupt with ID964" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS963 ,Controls Non-secure access of the interrupt with ID963" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS962 ,Controls Non-secure access of the interrupt with ID962" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS961 ,Controls Non-secure access of the interrupt with ID961" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS960 ,Controls Non-secure access of the interrupt with ID960" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEF0++0x03 hide.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF4))) group.long 0xEF4++0x03 line.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61" bitfld.long 0x00 30.--31. " NS_ACCESS991 ,Controls Non-secure access of the interrupt with ID991" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS990 ,Controls Non-secure access of the interrupt with ID990" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS989 ,Controls Non-secure access of the interrupt with ID989" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS988 ,Controls Non-secure access of the interrupt with ID988" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS987 ,Controls Non-secure access of the interrupt with ID987" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS986 ,Controls Non-secure access of the interrupt with ID986" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS985 ,Controls Non-secure access of the interrupt with ID985" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS984 ,Controls Non-secure access of the interrupt with ID984" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS983 ,Controls Non-secure access of the interrupt with ID983" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS982 ,Controls Non-secure access of the interrupt with ID982" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS981 ,Controls Non-secure access of the interrupt with ID981" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS980 ,Controls Non-secure access of the interrupt with ID980" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS979 ,Controls Non-secure access of the interrupt with ID979" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS978 ,Controls Non-secure access of the interrupt with ID978" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS977 ,Controls Non-secure access of the interrupt with ID977" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS976 ,Controls Non-secure access of the interrupt with ID976" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEF4++0x03 hide.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61" endif tree.end width 25. tree "Software Generated Interrupt" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0F00++0x03 hide.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" hgroup.long 0xF10++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0" hgroup.long 0xF14++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1" hgroup.long 0xF18++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2" hgroup.long 0xF1C++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3" hgroup.long 0xF20++0x03 hide.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0" hgroup.long 0xF24++0x03 hide.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1" hgroup.long 0xF28++0x03 hide.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2" hgroup.long 0xF2C++0x03 hide.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" group.long 0xF10++0x03 line.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0" group.long 0xF14++0x03 line.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1" group.long 0xF18++0x03 line.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2" group.long 0xF1C++0x03 line.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3" group.long 0xF20++0x03 line.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0" group.long 0xF24++0x03 line.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1" group.long 0xF28++0x03 line.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2" group.long 0xF2C++0x03 line.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3" endif tree.end width 24. tree "Interrupt Routing Registers" group.quad 0x6100++0x07 line.quad 0x00 "GICD_IROUTER32 ,Interrupt Routing Register 32 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6108++0x07 line.quad 0x00 "GICD_IROUTER33 ,Interrupt Routing Register 33 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6110++0x07 line.quad 0x00 "GICD_IROUTER34 ,Interrupt Routing Register 34 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6118++0x07 line.quad 0x00 "GICD_IROUTER35 ,Interrupt Routing Register 35 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6120++0x07 line.quad 0x00 "GICD_IROUTER36 ,Interrupt Routing Register 36 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6128++0x07 line.quad 0x00 "GICD_IROUTER37 ,Interrupt Routing Register 37 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6130++0x07 line.quad 0x00 "GICD_IROUTER38 ,Interrupt Routing Register 38 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6138++0x07 line.quad 0x00 "GICD_IROUTER39 ,Interrupt Routing Register 39 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6140++0x07 line.quad 0x00 "GICD_IROUTER40 ,Interrupt Routing Register 40 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6148++0x07 line.quad 0x00 "GICD_IROUTER41 ,Interrupt Routing Register 41 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6150++0x07 line.quad 0x00 "GICD_IROUTER42 ,Interrupt Routing Register 42 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6158++0x07 line.quad 0x00 "GICD_IROUTER43 ,Interrupt Routing Register 43 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6160++0x07 line.quad 0x00 "GICD_IROUTER44 ,Interrupt Routing Register 44 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6168++0x07 line.quad 0x00 "GICD_IROUTER45 ,Interrupt Routing Register 45 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6170++0x07 line.quad 0x00 "GICD_IROUTER46 ,Interrupt Routing Register 46 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6178++0x07 line.quad 0x00 "GICD_IROUTER47 ,Interrupt Routing Register 47 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6180++0x07 line.quad 0x00 "GICD_IROUTER48 ,Interrupt Routing Register 48 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6188++0x07 line.quad 0x00 "GICD_IROUTER49 ,Interrupt Routing Register 49 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6190++0x07 line.quad 0x00 "GICD_IROUTER50 ,Interrupt Routing Register 50 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6198++0x07 line.quad 0x00 "GICD_IROUTER51 ,Interrupt Routing Register 51 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A0++0x07 line.quad 0x00 "GICD_IROUTER52 ,Interrupt Routing Register 52 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A8++0x07 line.quad 0x00 "GICD_IROUTER53 ,Interrupt Routing Register 53 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B0++0x07 line.quad 0x00 "GICD_IROUTER54 ,Interrupt Routing Register 54 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B8++0x07 line.quad 0x00 "GICD_IROUTER55 ,Interrupt Routing Register 55 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C0++0x07 line.quad 0x00 "GICD_IROUTER56 ,Interrupt Routing Register 56 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C8++0x07 line.quad 0x00 "GICD_IROUTER57 ,Interrupt Routing Register 57 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D0++0x07 line.quad 0x00 "GICD_IROUTER58 ,Interrupt Routing Register 58 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D8++0x07 line.quad 0x00 "GICD_IROUTER59 ,Interrupt Routing Register 59 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E0++0x07 line.quad 0x00 "GICD_IROUTER60 ,Interrupt Routing Register 60 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E8++0x07 line.quad 0x00 "GICD_IROUTER61 ,Interrupt Routing Register 61 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F0++0x07 line.quad 0x00 "GICD_IROUTER62 ,Interrupt Routing Register 62 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F8++0x07 line.quad 0x00 "GICD_IROUTER63 ,Interrupt Routing Register 63 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6200++0x07 line.quad 0x00 "GICD_IROUTER64 ,Interrupt Routing Register 64 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6208++0x07 line.quad 0x00 "GICD_IROUTER65 ,Interrupt Routing Register 65 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6210++0x07 line.quad 0x00 "GICD_IROUTER66 ,Interrupt Routing Register 66 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6218++0x07 line.quad 0x00 "GICD_IROUTER67 ,Interrupt Routing Register 67 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6220++0x07 line.quad 0x00 "GICD_IROUTER68 ,Interrupt Routing Register 68 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6228++0x07 line.quad 0x00 "GICD_IROUTER69 ,Interrupt Routing Register 69 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6230++0x07 line.quad 0x00 "GICD_IROUTER70 ,Interrupt Routing Register 70 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6238++0x07 line.quad 0x00 "GICD_IROUTER71 ,Interrupt Routing Register 71 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6240++0x07 line.quad 0x00 "GICD_IROUTER72 ,Interrupt Routing Register 72 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6248++0x07 line.quad 0x00 "GICD_IROUTER73 ,Interrupt Routing Register 73 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6250++0x07 line.quad 0x00 "GICD_IROUTER74 ,Interrupt Routing Register 74 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6258++0x07 line.quad 0x00 "GICD_IROUTER75 ,Interrupt Routing Register 75 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6260++0x07 line.quad 0x00 "GICD_IROUTER76 ,Interrupt Routing Register 76 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6268++0x07 line.quad 0x00 "GICD_IROUTER77 ,Interrupt Routing Register 77 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6270++0x07 line.quad 0x00 "GICD_IROUTER78 ,Interrupt Routing Register 78 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6278++0x07 line.quad 0x00 "GICD_IROUTER79 ,Interrupt Routing Register 79 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6280++0x07 line.quad 0x00 "GICD_IROUTER80 ,Interrupt Routing Register 80 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6288++0x07 line.quad 0x00 "GICD_IROUTER81 ,Interrupt Routing Register 81 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6290++0x07 line.quad 0x00 "GICD_IROUTER82 ,Interrupt Routing Register 82 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6298++0x07 line.quad 0x00 "GICD_IROUTER83 ,Interrupt Routing Register 83 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A0++0x07 line.quad 0x00 "GICD_IROUTER84 ,Interrupt Routing Register 84 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A8++0x07 line.quad 0x00 "GICD_IROUTER85 ,Interrupt Routing Register 85 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B0++0x07 line.quad 0x00 "GICD_IROUTER86 ,Interrupt Routing Register 86 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B8++0x07 line.quad 0x00 "GICD_IROUTER87 ,Interrupt Routing Register 87 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C0++0x07 line.quad 0x00 "GICD_IROUTER88 ,Interrupt Routing Register 88 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C8++0x07 line.quad 0x00 "GICD_IROUTER89 ,Interrupt Routing Register 89 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D0++0x07 line.quad 0x00 "GICD_IROUTER90 ,Interrupt Routing Register 90 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D8++0x07 line.quad 0x00 "GICD_IROUTER91 ,Interrupt Routing Register 91 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E0++0x07 line.quad 0x00 "GICD_IROUTER92 ,Interrupt Routing Register 92 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E8++0x07 line.quad 0x00 "GICD_IROUTER93 ,Interrupt Routing Register 93 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F0++0x07 line.quad 0x00 "GICD_IROUTER94 ,Interrupt Routing Register 94 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F8++0x07 line.quad 0x00 "GICD_IROUTER95 ,Interrupt Routing Register 95 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6300++0x07 line.quad 0x00 "GICD_IROUTER96 ,Interrupt Routing Register 96 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6308++0x07 line.quad 0x00 "GICD_IROUTER97 ,Interrupt Routing Register 97 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6310++0x07 line.quad 0x00 "GICD_IROUTER98 ,Interrupt Routing Register 98 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6318++0x07 line.quad 0x00 "GICD_IROUTER99 ,Interrupt Routing Register 99 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6320++0x07 line.quad 0x00 "GICD_IROUTER100,Interrupt Routing Register 100" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6328++0x07 line.quad 0x00 "GICD_IROUTER101,Interrupt Routing Register 101" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6330++0x07 line.quad 0x00 "GICD_IROUTER102,Interrupt Routing Register 102" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6338++0x07 line.quad 0x00 "GICD_IROUTER103,Interrupt Routing Register 103" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6340++0x07 line.quad 0x00 "GICD_IROUTER104,Interrupt Routing Register 104" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6348++0x07 line.quad 0x00 "GICD_IROUTER105,Interrupt Routing Register 105" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6350++0x07 line.quad 0x00 "GICD_IROUTER106,Interrupt Routing Register 106" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6358++0x07 line.quad 0x00 "GICD_IROUTER107,Interrupt Routing Register 107" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6360++0x07 line.quad 0x00 "GICD_IROUTER108,Interrupt Routing Register 108" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6368++0x07 line.quad 0x00 "GICD_IROUTER109,Interrupt Routing Register 109" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6370++0x07 line.quad 0x00 "GICD_IROUTER110,Interrupt Routing Register 110" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6378++0x07 line.quad 0x00 "GICD_IROUTER111,Interrupt Routing Register 111" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6380++0x07 line.quad 0x00 "GICD_IROUTER112,Interrupt Routing Register 112" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6388++0x07 line.quad 0x00 "GICD_IROUTER113,Interrupt Routing Register 113" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6390++0x07 line.quad 0x00 "GICD_IROUTER114,Interrupt Routing Register 114" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6398++0x07 line.quad 0x00 "GICD_IROUTER115,Interrupt Routing Register 115" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A0++0x07 line.quad 0x00 "GICD_IROUTER116,Interrupt Routing Register 116" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A8++0x07 line.quad 0x00 "GICD_IROUTER117,Interrupt Routing Register 117" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B0++0x07 line.quad 0x00 "GICD_IROUTER118,Interrupt Routing Register 118" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B8++0x07 line.quad 0x00 "GICD_IROUTER119,Interrupt Routing Register 119" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C0++0x07 line.quad 0x00 "GICD_IROUTER120,Interrupt Routing Register 120" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C8++0x07 line.quad 0x00 "GICD_IROUTER121,Interrupt Routing Register 121" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D0++0x07 line.quad 0x00 "GICD_IROUTER122,Interrupt Routing Register 122" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D8++0x07 line.quad 0x00 "GICD_IROUTER123,Interrupt Routing Register 123" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E0++0x07 line.quad 0x00 "GICD_IROUTER124,Interrupt Routing Register 124" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E8++0x07 line.quad 0x00 "GICD_IROUTER125,Interrupt Routing Register 125" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F0++0x07 line.quad 0x00 "GICD_IROUTER126,Interrupt Routing Register 126" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F8++0x07 line.quad 0x00 "GICD_IROUTER127,Interrupt Routing Register 127" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6400++0x07 line.quad 0x00 "GICD_IROUTER128,Interrupt Routing Register 128" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6408++0x07 line.quad 0x00 "GICD_IROUTER129,Interrupt Routing Register 129" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6410++0x07 line.quad 0x00 "GICD_IROUTER130,Interrupt Routing Register 130" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6418++0x07 line.quad 0x00 "GICD_IROUTER131,Interrupt Routing Register 131" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6420++0x07 line.quad 0x00 "GICD_IROUTER132,Interrupt Routing Register 132" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6428++0x07 line.quad 0x00 "GICD_IROUTER133,Interrupt Routing Register 133" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6430++0x07 line.quad 0x00 "GICD_IROUTER134,Interrupt Routing Register 134" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6438++0x07 line.quad 0x00 "GICD_IROUTER135,Interrupt Routing Register 135" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6440++0x07 line.quad 0x00 "GICD_IROUTER136,Interrupt Routing Register 136" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6448++0x07 line.quad 0x00 "GICD_IROUTER137,Interrupt Routing Register 137" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6450++0x07 line.quad 0x00 "GICD_IROUTER138,Interrupt Routing Register 138" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6458++0x07 line.quad 0x00 "GICD_IROUTER139,Interrupt Routing Register 139" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6460++0x07 line.quad 0x00 "GICD_IROUTER140,Interrupt Routing Register 140" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6468++0x07 line.quad 0x00 "GICD_IROUTER141,Interrupt Routing Register 141" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6470++0x07 line.quad 0x00 "GICD_IROUTER142,Interrupt Routing Register 142" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6478++0x07 line.quad 0x00 "GICD_IROUTER143,Interrupt Routing Register 143" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6480++0x07 line.quad 0x00 "GICD_IROUTER144,Interrupt Routing Register 144" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6488++0x07 line.quad 0x00 "GICD_IROUTER145,Interrupt Routing Register 145" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6490++0x07 line.quad 0x00 "GICD_IROUTER146,Interrupt Routing Register 146" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6498++0x07 line.quad 0x00 "GICD_IROUTER147,Interrupt Routing Register 147" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A0++0x07 line.quad 0x00 "GICD_IROUTER148,Interrupt Routing Register 148" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A8++0x07 line.quad 0x00 "GICD_IROUTER149,Interrupt Routing Register 149" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B0++0x07 line.quad 0x00 "GICD_IROUTER150,Interrupt Routing Register 150" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B8++0x07 line.quad 0x00 "GICD_IROUTER151,Interrupt Routing Register 151" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C0++0x07 line.quad 0x00 "GICD_IROUTER152,Interrupt Routing Register 152" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C8++0x07 line.quad 0x00 "GICD_IROUTER153,Interrupt Routing Register 153" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D0++0x07 line.quad 0x00 "GICD_IROUTER154,Interrupt Routing Register 154" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D8++0x07 line.quad 0x00 "GICD_IROUTER155,Interrupt Routing Register 155" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E0++0x07 line.quad 0x00 "GICD_IROUTER156,Interrupt Routing Register 156" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E8++0x07 line.quad 0x00 "GICD_IROUTER157,Interrupt Routing Register 157" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F0++0x07 line.quad 0x00 "GICD_IROUTER158,Interrupt Routing Register 158" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F8++0x07 line.quad 0x00 "GICD_IROUTER159,Interrupt Routing Register 159" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6500++0x07 line.quad 0x00 "GICD_IROUTER160,Interrupt Routing Register 160" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6508++0x07 line.quad 0x00 "GICD_IROUTER161,Interrupt Routing Register 161" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6510++0x07 line.quad 0x00 "GICD_IROUTER162,Interrupt Routing Register 162" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6518++0x07 line.quad 0x00 "GICD_IROUTER163,Interrupt Routing Register 163" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6520++0x07 line.quad 0x00 "GICD_IROUTER164,Interrupt Routing Register 164" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6528++0x07 line.quad 0x00 "GICD_IROUTER165,Interrupt Routing Register 165" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6530++0x07 line.quad 0x00 "GICD_IROUTER166,Interrupt Routing Register 166" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6538++0x07 line.quad 0x00 "GICD_IROUTER167,Interrupt Routing Register 167" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6540++0x07 line.quad 0x00 "GICD_IROUTER168,Interrupt Routing Register 168" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6548++0x07 line.quad 0x00 "GICD_IROUTER169,Interrupt Routing Register 169" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6550++0x07 line.quad 0x00 "GICD_IROUTER170,Interrupt Routing Register 170" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6558++0x07 line.quad 0x00 "GICD_IROUTER171,Interrupt Routing Register 171" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6560++0x07 line.quad 0x00 "GICD_IROUTER172,Interrupt Routing Register 172" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6568++0x07 line.quad 0x00 "GICD_IROUTER173,Interrupt Routing Register 173" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6570++0x07 line.quad 0x00 "GICD_IROUTER174,Interrupt Routing Register 174" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6578++0x07 line.quad 0x00 "GICD_IROUTER175,Interrupt Routing Register 175" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6580++0x07 line.quad 0x00 "GICD_IROUTER176,Interrupt Routing Register 176" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6588++0x07 line.quad 0x00 "GICD_IROUTER177,Interrupt Routing Register 177" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6590++0x07 line.quad 0x00 "GICD_IROUTER178,Interrupt Routing Register 178" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6598++0x07 line.quad 0x00 "GICD_IROUTER179,Interrupt Routing Register 179" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A0++0x07 line.quad 0x00 "GICD_IROUTER180,Interrupt Routing Register 180" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A8++0x07 line.quad 0x00 "GICD_IROUTER181,Interrupt Routing Register 181" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B0++0x07 line.quad 0x00 "GICD_IROUTER182,Interrupt Routing Register 182" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B8++0x07 line.quad 0x00 "GICD_IROUTER183,Interrupt Routing Register 183" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C0++0x07 line.quad 0x00 "GICD_IROUTER184,Interrupt Routing Register 184" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C8++0x07 line.quad 0x00 "GICD_IROUTER185,Interrupt Routing Register 185" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D0++0x07 line.quad 0x00 "GICD_IROUTER186,Interrupt Routing Register 186" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D8++0x07 line.quad 0x00 "GICD_IROUTER187,Interrupt Routing Register 187" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E0++0x07 line.quad 0x00 "GICD_IROUTER188,Interrupt Routing Register 188" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E8++0x07 line.quad 0x00 "GICD_IROUTER189,Interrupt Routing Register 189" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F0++0x07 line.quad 0x00 "GICD_IROUTER190,Interrupt Routing Register 190" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F8++0x07 line.quad 0x00 "GICD_IROUTER191,Interrupt Routing Register 191" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6600++0x07 line.quad 0x00 "GICD_IROUTER192,Interrupt Routing Register 192" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6608++0x07 line.quad 0x00 "GICD_IROUTER193,Interrupt Routing Register 193" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6610++0x07 line.quad 0x00 "GICD_IROUTER194,Interrupt Routing Register 194" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6618++0x07 line.quad 0x00 "GICD_IROUTER195,Interrupt Routing Register 195" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6620++0x07 line.quad 0x00 "GICD_IROUTER196,Interrupt Routing Register 196" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6628++0x07 line.quad 0x00 "GICD_IROUTER197,Interrupt Routing Register 197" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6630++0x07 line.quad 0x00 "GICD_IROUTER198,Interrupt Routing Register 198" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6638++0x07 line.quad 0x00 "GICD_IROUTER199,Interrupt Routing Register 199" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6640++0x07 line.quad 0x00 "GICD_IROUTER200,Interrupt Routing Register 200" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6648++0x07 line.quad 0x00 "GICD_IROUTER201,Interrupt Routing Register 201" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6650++0x07 line.quad 0x00 "GICD_IROUTER202,Interrupt Routing Register 202" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6658++0x07 line.quad 0x00 "GICD_IROUTER203,Interrupt Routing Register 203" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6660++0x07 line.quad 0x00 "GICD_IROUTER204,Interrupt Routing Register 204" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6668++0x07 line.quad 0x00 "GICD_IROUTER205,Interrupt Routing Register 205" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6670++0x07 line.quad 0x00 "GICD_IROUTER206,Interrupt Routing Register 206" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6678++0x07 line.quad 0x00 "GICD_IROUTER207,Interrupt Routing Register 207" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6680++0x07 line.quad 0x00 "GICD_IROUTER208,Interrupt Routing Register 208" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6688++0x07 line.quad 0x00 "GICD_IROUTER209,Interrupt Routing Register 209" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6690++0x07 line.quad 0x00 "GICD_IROUTER210,Interrupt Routing Register 210" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6698++0x07 line.quad 0x00 "GICD_IROUTER211,Interrupt Routing Register 211" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A0++0x07 line.quad 0x00 "GICD_IROUTER212,Interrupt Routing Register 212" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A8++0x07 line.quad 0x00 "GICD_IROUTER213,Interrupt Routing Register 213" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B0++0x07 line.quad 0x00 "GICD_IROUTER214,Interrupt Routing Register 214" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B8++0x07 line.quad 0x00 "GICD_IROUTER215,Interrupt Routing Register 215" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C0++0x07 line.quad 0x00 "GICD_IROUTER216,Interrupt Routing Register 216" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C8++0x07 line.quad 0x00 "GICD_IROUTER217,Interrupt Routing Register 217" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D0++0x07 line.quad 0x00 "GICD_IROUTER218,Interrupt Routing Register 218" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D8++0x07 line.quad 0x00 "GICD_IROUTER219,Interrupt Routing Register 219" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E0++0x07 line.quad 0x00 "GICD_IROUTER220,Interrupt Routing Register 220" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E8++0x07 line.quad 0x00 "GICD_IROUTER221,Interrupt Routing Register 221" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F0++0x07 line.quad 0x00 "GICD_IROUTER222,Interrupt Routing Register 222" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F8++0x07 line.quad 0x00 "GICD_IROUTER223,Interrupt Routing Register 223" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6700++0x07 line.quad 0x00 "GICD_IROUTER224,Interrupt Routing Register 224" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6708++0x07 line.quad 0x00 "GICD_IROUTER225,Interrupt Routing Register 225" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6710++0x07 line.quad 0x00 "GICD_IROUTER226,Interrupt Routing Register 226" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6718++0x07 line.quad 0x00 "GICD_IROUTER227,Interrupt Routing Register 227" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6720++0x07 line.quad 0x00 "GICD_IROUTER228,Interrupt Routing Register 228" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6728++0x07 line.quad 0x00 "GICD_IROUTER229,Interrupt Routing Register 229" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6730++0x07 line.quad 0x00 "GICD_IROUTER230,Interrupt Routing Register 230" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6738++0x07 line.quad 0x00 "GICD_IROUTER231,Interrupt Routing Register 231" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6740++0x07 line.quad 0x00 "GICD_IROUTER232,Interrupt Routing Register 232" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6748++0x07 line.quad 0x00 "GICD_IROUTER233,Interrupt Routing Register 233" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6750++0x07 line.quad 0x00 "GICD_IROUTER234,Interrupt Routing Register 234" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6758++0x07 line.quad 0x00 "GICD_IROUTER235,Interrupt Routing Register 235" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6760++0x07 line.quad 0x00 "GICD_IROUTER236,Interrupt Routing Register 236" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6768++0x07 line.quad 0x00 "GICD_IROUTER237,Interrupt Routing Register 237" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6770++0x07 line.quad 0x00 "GICD_IROUTER238,Interrupt Routing Register 238" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6778++0x07 line.quad 0x00 "GICD_IROUTER239,Interrupt Routing Register 239" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6780++0x07 line.quad 0x00 "GICD_IROUTER240,Interrupt Routing Register 240" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6788++0x07 line.quad 0x00 "GICD_IROUTER241,Interrupt Routing Register 241" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6790++0x07 line.quad 0x00 "GICD_IROUTER242,Interrupt Routing Register 242" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6798++0x07 line.quad 0x00 "GICD_IROUTER243,Interrupt Routing Register 243" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A0++0x07 line.quad 0x00 "GICD_IROUTER244,Interrupt Routing Register 244" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A8++0x07 line.quad 0x00 "GICD_IROUTER245,Interrupt Routing Register 245" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B0++0x07 line.quad 0x00 "GICD_IROUTER246,Interrupt Routing Register 246" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B8++0x07 line.quad 0x00 "GICD_IROUTER247,Interrupt Routing Register 247" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C0++0x07 line.quad 0x00 "GICD_IROUTER248,Interrupt Routing Register 248" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C8++0x07 line.quad 0x00 "GICD_IROUTER249,Interrupt Routing Register 249" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D0++0x07 line.quad 0x00 "GICD_IROUTER250,Interrupt Routing Register 250" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D8++0x07 line.quad 0x00 "GICD_IROUTER251,Interrupt Routing Register 251" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E0++0x07 line.quad 0x00 "GICD_IROUTER252,Interrupt Routing Register 252" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E8++0x07 line.quad 0x00 "GICD_IROUTER253,Interrupt Routing Register 253" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F0++0x07 line.quad 0x00 "GICD_IROUTER254,Interrupt Routing Register 254" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F8++0x07 line.quad 0x00 "GICD_IROUTER255,Interrupt Routing Register 255" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6800++0x07 line.quad 0x00 "GICD_IROUTER256,Interrupt Routing Register 256" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6808++0x07 line.quad 0x00 "GICD_IROUTER257,Interrupt Routing Register 257" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6810++0x07 line.quad 0x00 "GICD_IROUTER258,Interrupt Routing Register 258" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6818++0x07 line.quad 0x00 "GICD_IROUTER259,Interrupt Routing Register 259" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6820++0x07 line.quad 0x00 "GICD_IROUTER260,Interrupt Routing Register 260" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6828++0x07 line.quad 0x00 "GICD_IROUTER261,Interrupt Routing Register 261" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6830++0x07 line.quad 0x00 "GICD_IROUTER262,Interrupt Routing Register 262" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6838++0x07 line.quad 0x00 "GICD_IROUTER263,Interrupt Routing Register 263" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6840++0x07 line.quad 0x00 "GICD_IROUTER264,Interrupt Routing Register 264" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6848++0x07 line.quad 0x00 "GICD_IROUTER265,Interrupt Routing Register 265" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6850++0x07 line.quad 0x00 "GICD_IROUTER266,Interrupt Routing Register 266" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6858++0x07 line.quad 0x00 "GICD_IROUTER267,Interrupt Routing Register 267" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6860++0x07 line.quad 0x00 "GICD_IROUTER268,Interrupt Routing Register 268" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6868++0x07 line.quad 0x00 "GICD_IROUTER269,Interrupt Routing Register 269" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6870++0x07 line.quad 0x00 "GICD_IROUTER270,Interrupt Routing Register 270" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6878++0x07 line.quad 0x00 "GICD_IROUTER271,Interrupt Routing Register 271" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6880++0x07 line.quad 0x00 "GICD_IROUTER272,Interrupt Routing Register 272" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6888++0x07 line.quad 0x00 "GICD_IROUTER273,Interrupt Routing Register 273" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6890++0x07 line.quad 0x00 "GICD_IROUTER274,Interrupt Routing Register 274" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6898++0x07 line.quad 0x00 "GICD_IROUTER275,Interrupt Routing Register 275" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A0++0x07 line.quad 0x00 "GICD_IROUTER276,Interrupt Routing Register 276" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A8++0x07 line.quad 0x00 "GICD_IROUTER277,Interrupt Routing Register 277" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B0++0x07 line.quad 0x00 "GICD_IROUTER278,Interrupt Routing Register 278" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B8++0x07 line.quad 0x00 "GICD_IROUTER279,Interrupt Routing Register 279" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C0++0x07 line.quad 0x00 "GICD_IROUTER280,Interrupt Routing Register 280" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C8++0x07 line.quad 0x00 "GICD_IROUTER281,Interrupt Routing Register 281" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D0++0x07 line.quad 0x00 "GICD_IROUTER282,Interrupt Routing Register 282" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D8++0x07 line.quad 0x00 "GICD_IROUTER283,Interrupt Routing Register 283" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E0++0x07 line.quad 0x00 "GICD_IROUTER284,Interrupt Routing Register 284" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E8++0x07 line.quad 0x00 "GICD_IROUTER285,Interrupt Routing Register 285" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F0++0x07 line.quad 0x00 "GICD_IROUTER286,Interrupt Routing Register 286" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F8++0x07 line.quad 0x00 "GICD_IROUTER287,Interrupt Routing Register 287" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6900++0x07 line.quad 0x00 "GICD_IROUTER288,Interrupt Routing Register 288" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6908++0x07 line.quad 0x00 "GICD_IROUTER289,Interrupt Routing Register 289" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6910++0x07 line.quad 0x00 "GICD_IROUTER290,Interrupt Routing Register 290" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6918++0x07 line.quad 0x00 "GICD_IROUTER291,Interrupt Routing Register 291" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6920++0x07 line.quad 0x00 "GICD_IROUTER292,Interrupt Routing Register 292" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6928++0x07 line.quad 0x00 "GICD_IROUTER293,Interrupt Routing Register 293" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6930++0x07 line.quad 0x00 "GICD_IROUTER294,Interrupt Routing Register 294" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6938++0x07 line.quad 0x00 "GICD_IROUTER295,Interrupt Routing Register 295" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6940++0x07 line.quad 0x00 "GICD_IROUTER296,Interrupt Routing Register 296" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6948++0x07 line.quad 0x00 "GICD_IROUTER297,Interrupt Routing Register 297" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6950++0x07 line.quad 0x00 "GICD_IROUTER298,Interrupt Routing Register 298" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6958++0x07 line.quad 0x00 "GICD_IROUTER299,Interrupt Routing Register 299" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6960++0x07 line.quad 0x00 "GICD_IROUTER300,Interrupt Routing Register 300" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6968++0x07 line.quad 0x00 "GICD_IROUTER301,Interrupt Routing Register 301" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6970++0x07 line.quad 0x00 "GICD_IROUTER302,Interrupt Routing Register 302" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6978++0x07 line.quad 0x00 "GICD_IROUTER303,Interrupt Routing Register 303" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6980++0x07 line.quad 0x00 "GICD_IROUTER304,Interrupt Routing Register 304" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6988++0x07 line.quad 0x00 "GICD_IROUTER305,Interrupt Routing Register 305" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6990++0x07 line.quad 0x00 "GICD_IROUTER306,Interrupt Routing Register 306" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6998++0x07 line.quad 0x00 "GICD_IROUTER307,Interrupt Routing Register 307" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A0++0x07 line.quad 0x00 "GICD_IROUTER308,Interrupt Routing Register 308" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A8++0x07 line.quad 0x00 "GICD_IROUTER309,Interrupt Routing Register 309" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B0++0x07 line.quad 0x00 "GICD_IROUTER310,Interrupt Routing Register 310" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B8++0x07 line.quad 0x00 "GICD_IROUTER311,Interrupt Routing Register 311" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C0++0x07 line.quad 0x00 "GICD_IROUTER312,Interrupt Routing Register 312" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C8++0x07 line.quad 0x00 "GICD_IROUTER313,Interrupt Routing Register 313" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D0++0x07 line.quad 0x00 "GICD_IROUTER314,Interrupt Routing Register 314" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D8++0x07 line.quad 0x00 "GICD_IROUTER315,Interrupt Routing Register 315" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E0++0x07 line.quad 0x00 "GICD_IROUTER316,Interrupt Routing Register 316" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E8++0x07 line.quad 0x00 "GICD_IROUTER317,Interrupt Routing Register 317" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F0++0x07 line.quad 0x00 "GICD_IROUTER318,Interrupt Routing Register 318" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F8++0x07 line.quad 0x00 "GICD_IROUTER319,Interrupt Routing Register 319" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A00++0x07 line.quad 0x00 "GICD_IROUTER320,Interrupt Routing Register 320" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A08++0x07 line.quad 0x00 "GICD_IROUTER321,Interrupt Routing Register 321" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A10++0x07 line.quad 0x00 "GICD_IROUTER322,Interrupt Routing Register 322" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A18++0x07 line.quad 0x00 "GICD_IROUTER323,Interrupt Routing Register 323" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A20++0x07 line.quad 0x00 "GICD_IROUTER324,Interrupt Routing Register 324" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A28++0x07 line.quad 0x00 "GICD_IROUTER325,Interrupt Routing Register 325" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A30++0x07 line.quad 0x00 "GICD_IROUTER326,Interrupt Routing Register 326" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A38++0x07 line.quad 0x00 "GICD_IROUTER327,Interrupt Routing Register 327" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A40++0x07 line.quad 0x00 "GICD_IROUTER328,Interrupt Routing Register 328" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A48++0x07 line.quad 0x00 "GICD_IROUTER329,Interrupt Routing Register 329" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A50++0x07 line.quad 0x00 "GICD_IROUTER330,Interrupt Routing Register 330" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A58++0x07 line.quad 0x00 "GICD_IROUTER331,Interrupt Routing Register 331" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A60++0x07 line.quad 0x00 "GICD_IROUTER332,Interrupt Routing Register 332" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A68++0x07 line.quad 0x00 "GICD_IROUTER333,Interrupt Routing Register 333" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A70++0x07 line.quad 0x00 "GICD_IROUTER334,Interrupt Routing Register 334" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A78++0x07 line.quad 0x00 "GICD_IROUTER335,Interrupt Routing Register 335" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A80++0x07 line.quad 0x00 "GICD_IROUTER336,Interrupt Routing Register 336" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A88++0x07 line.quad 0x00 "GICD_IROUTER337,Interrupt Routing Register 337" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A90++0x07 line.quad 0x00 "GICD_IROUTER338,Interrupt Routing Register 338" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A98++0x07 line.quad 0x00 "GICD_IROUTER339,Interrupt Routing Register 339" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA0++0x07 line.quad 0x00 "GICD_IROUTER340,Interrupt Routing Register 340" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA8++0x07 line.quad 0x00 "GICD_IROUTER341,Interrupt Routing Register 341" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB0++0x07 line.quad 0x00 "GICD_IROUTER342,Interrupt Routing Register 342" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB8++0x07 line.quad 0x00 "GICD_IROUTER343,Interrupt Routing Register 343" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC0++0x07 line.quad 0x00 "GICD_IROUTER344,Interrupt Routing Register 344" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC8++0x07 line.quad 0x00 "GICD_IROUTER345,Interrupt Routing Register 345" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD0++0x07 line.quad 0x00 "GICD_IROUTER346,Interrupt Routing Register 346" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD8++0x07 line.quad 0x00 "GICD_IROUTER347,Interrupt Routing Register 347" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE0++0x07 line.quad 0x00 "GICD_IROUTER348,Interrupt Routing Register 348" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE8++0x07 line.quad 0x00 "GICD_IROUTER349,Interrupt Routing Register 349" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF0++0x07 line.quad 0x00 "GICD_IROUTER350,Interrupt Routing Register 350" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF8++0x07 line.quad 0x00 "GICD_IROUTER351,Interrupt Routing Register 351" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B00++0x07 line.quad 0x00 "GICD_IROUTER352,Interrupt Routing Register 352" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B08++0x07 line.quad 0x00 "GICD_IROUTER353,Interrupt Routing Register 353" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B10++0x07 line.quad 0x00 "GICD_IROUTER354,Interrupt Routing Register 354" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B18++0x07 line.quad 0x00 "GICD_IROUTER355,Interrupt Routing Register 355" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B20++0x07 line.quad 0x00 "GICD_IROUTER356,Interrupt Routing Register 356" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B28++0x07 line.quad 0x00 "GICD_IROUTER357,Interrupt Routing Register 357" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B30++0x07 line.quad 0x00 "GICD_IROUTER358,Interrupt Routing Register 358" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B38++0x07 line.quad 0x00 "GICD_IROUTER359,Interrupt Routing Register 359" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B40++0x07 line.quad 0x00 "GICD_IROUTER360,Interrupt Routing Register 360" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B48++0x07 line.quad 0x00 "GICD_IROUTER361,Interrupt Routing Register 361" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B50++0x07 line.quad 0x00 "GICD_IROUTER362,Interrupt Routing Register 362" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B58++0x07 line.quad 0x00 "GICD_IROUTER363,Interrupt Routing Register 363" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B60++0x07 line.quad 0x00 "GICD_IROUTER364,Interrupt Routing Register 364" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B68++0x07 line.quad 0x00 "GICD_IROUTER365,Interrupt Routing Register 365" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B70++0x07 line.quad 0x00 "GICD_IROUTER366,Interrupt Routing Register 366" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B78++0x07 line.quad 0x00 "GICD_IROUTER367,Interrupt Routing Register 367" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B80++0x07 line.quad 0x00 "GICD_IROUTER368,Interrupt Routing Register 368" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B88++0x07 line.quad 0x00 "GICD_IROUTER369,Interrupt Routing Register 369" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B90++0x07 line.quad 0x00 "GICD_IROUTER370,Interrupt Routing Register 370" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B98++0x07 line.quad 0x00 "GICD_IROUTER371,Interrupt Routing Register 371" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA0++0x07 line.quad 0x00 "GICD_IROUTER372,Interrupt Routing Register 372" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA8++0x07 line.quad 0x00 "GICD_IROUTER373,Interrupt Routing Register 373" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB0++0x07 line.quad 0x00 "GICD_IROUTER374,Interrupt Routing Register 374" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB8++0x07 line.quad 0x00 "GICD_IROUTER375,Interrupt Routing Register 375" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC0++0x07 line.quad 0x00 "GICD_IROUTER376,Interrupt Routing Register 376" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC8++0x07 line.quad 0x00 "GICD_IROUTER377,Interrupt Routing Register 377" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD0++0x07 line.quad 0x00 "GICD_IROUTER378,Interrupt Routing Register 378" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD8++0x07 line.quad 0x00 "GICD_IROUTER379,Interrupt Routing Register 379" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE0++0x07 line.quad 0x00 "GICD_IROUTER380,Interrupt Routing Register 380" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE8++0x07 line.quad 0x00 "GICD_IROUTER381,Interrupt Routing Register 381" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF0++0x07 line.quad 0x00 "GICD_IROUTER382,Interrupt Routing Register 382" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF8++0x07 line.quad 0x00 "GICD_IROUTER383,Interrupt Routing Register 383" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C00++0x07 line.quad 0x00 "GICD_IROUTER384,Interrupt Routing Register 384" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C08++0x07 line.quad 0x00 "GICD_IROUTER385,Interrupt Routing Register 385" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C10++0x07 line.quad 0x00 "GICD_IROUTER386,Interrupt Routing Register 386" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C18++0x07 line.quad 0x00 "GICD_IROUTER387,Interrupt Routing Register 387" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C20++0x07 line.quad 0x00 "GICD_IROUTER388,Interrupt Routing Register 388" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C28++0x07 line.quad 0x00 "GICD_IROUTER389,Interrupt Routing Register 389" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C30++0x07 line.quad 0x00 "GICD_IROUTER390,Interrupt Routing Register 390" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C38++0x07 line.quad 0x00 "GICD_IROUTER391,Interrupt Routing Register 391" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C40++0x07 line.quad 0x00 "GICD_IROUTER392,Interrupt Routing Register 392" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C48++0x07 line.quad 0x00 "GICD_IROUTER393,Interrupt Routing Register 393" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C50++0x07 line.quad 0x00 "GICD_IROUTER394,Interrupt Routing Register 394" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C58++0x07 line.quad 0x00 "GICD_IROUTER395,Interrupt Routing Register 395" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C60++0x07 line.quad 0x00 "GICD_IROUTER396,Interrupt Routing Register 396" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C68++0x07 line.quad 0x00 "GICD_IROUTER397,Interrupt Routing Register 397" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C70++0x07 line.quad 0x00 "GICD_IROUTER398,Interrupt Routing Register 398" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C78++0x07 line.quad 0x00 "GICD_IROUTER399,Interrupt Routing Register 399" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C80++0x07 line.quad 0x00 "GICD_IROUTER400,Interrupt Routing Register 400" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C88++0x07 line.quad 0x00 "GICD_IROUTER401,Interrupt Routing Register 401" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C90++0x07 line.quad 0x00 "GICD_IROUTER402,Interrupt Routing Register 402" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C98++0x07 line.quad 0x00 "GICD_IROUTER403,Interrupt Routing Register 403" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA0++0x07 line.quad 0x00 "GICD_IROUTER404,Interrupt Routing Register 404" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA8++0x07 line.quad 0x00 "GICD_IROUTER405,Interrupt Routing Register 405" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB0++0x07 line.quad 0x00 "GICD_IROUTER406,Interrupt Routing Register 406" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB8++0x07 line.quad 0x00 "GICD_IROUTER407,Interrupt Routing Register 407" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC0++0x07 line.quad 0x00 "GICD_IROUTER408,Interrupt Routing Register 408" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC8++0x07 line.quad 0x00 "GICD_IROUTER409,Interrupt Routing Register 409" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD0++0x07 line.quad 0x00 "GICD_IROUTER410,Interrupt Routing Register 410" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD8++0x07 line.quad 0x00 "GICD_IROUTER411,Interrupt Routing Register 411" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE0++0x07 line.quad 0x00 "GICD_IROUTER412,Interrupt Routing Register 412" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE8++0x07 line.quad 0x00 "GICD_IROUTER413,Interrupt Routing Register 413" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF0++0x07 line.quad 0x00 "GICD_IROUTER414,Interrupt Routing Register 414" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF8++0x07 line.quad 0x00 "GICD_IROUTER415,Interrupt Routing Register 415" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D00++0x07 line.quad 0x00 "GICD_IROUTER416,Interrupt Routing Register 416" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D08++0x07 line.quad 0x00 "GICD_IROUTER417,Interrupt Routing Register 417" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D10++0x07 line.quad 0x00 "GICD_IROUTER418,Interrupt Routing Register 418" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D18++0x07 line.quad 0x00 "GICD_IROUTER419,Interrupt Routing Register 419" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D20++0x07 line.quad 0x00 "GICD_IROUTER420,Interrupt Routing Register 420" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D28++0x07 line.quad 0x00 "GICD_IROUTER421,Interrupt Routing Register 421" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D30++0x07 line.quad 0x00 "GICD_IROUTER422,Interrupt Routing Register 422" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D38++0x07 line.quad 0x00 "GICD_IROUTER423,Interrupt Routing Register 423" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D40++0x07 line.quad 0x00 "GICD_IROUTER424,Interrupt Routing Register 424" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D48++0x07 line.quad 0x00 "GICD_IROUTER425,Interrupt Routing Register 425" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D50++0x07 line.quad 0x00 "GICD_IROUTER426,Interrupt Routing Register 426" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D58++0x07 line.quad 0x00 "GICD_IROUTER427,Interrupt Routing Register 427" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D60++0x07 line.quad 0x00 "GICD_IROUTER428,Interrupt Routing Register 428" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D68++0x07 line.quad 0x00 "GICD_IROUTER429,Interrupt Routing Register 429" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D70++0x07 line.quad 0x00 "GICD_IROUTER430,Interrupt Routing Register 430" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D78++0x07 line.quad 0x00 "GICD_IROUTER431,Interrupt Routing Register 431" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D80++0x07 line.quad 0x00 "GICD_IROUTER432,Interrupt Routing Register 432" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D88++0x07 line.quad 0x00 "GICD_IROUTER433,Interrupt Routing Register 433" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D90++0x07 line.quad 0x00 "GICD_IROUTER434,Interrupt Routing Register 434" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D98++0x07 line.quad 0x00 "GICD_IROUTER435,Interrupt Routing Register 435" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA0++0x07 line.quad 0x00 "GICD_IROUTER436,Interrupt Routing Register 436" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA8++0x07 line.quad 0x00 "GICD_IROUTER437,Interrupt Routing Register 437" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB0++0x07 line.quad 0x00 "GICD_IROUTER438,Interrupt Routing Register 438" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB8++0x07 line.quad 0x00 "GICD_IROUTER439,Interrupt Routing Register 439" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC0++0x07 line.quad 0x00 "GICD_IROUTER440,Interrupt Routing Register 440" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC8++0x07 line.quad 0x00 "GICD_IROUTER441,Interrupt Routing Register 441" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD0++0x07 line.quad 0x00 "GICD_IROUTER442,Interrupt Routing Register 442" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD8++0x07 line.quad 0x00 "GICD_IROUTER443,Interrupt Routing Register 443" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE0++0x07 line.quad 0x00 "GICD_IROUTER444,Interrupt Routing Register 444" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE8++0x07 line.quad 0x00 "GICD_IROUTER445,Interrupt Routing Register 445" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF0++0x07 line.quad 0x00 "GICD_IROUTER446,Interrupt Routing Register 446" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF8++0x07 line.quad 0x00 "GICD_IROUTER447,Interrupt Routing Register 447" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E00++0x07 line.quad 0x00 "GICD_IROUTER448,Interrupt Routing Register 448" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E08++0x07 line.quad 0x00 "GICD_IROUTER449,Interrupt Routing Register 449" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E10++0x07 line.quad 0x00 "GICD_IROUTER450,Interrupt Routing Register 450" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E18++0x07 line.quad 0x00 "GICD_IROUTER451,Interrupt Routing Register 451" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E20++0x07 line.quad 0x00 "GICD_IROUTER452,Interrupt Routing Register 452" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E28++0x07 line.quad 0x00 "GICD_IROUTER453,Interrupt Routing Register 453" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E30++0x07 line.quad 0x00 "GICD_IROUTER454,Interrupt Routing Register 454" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E38++0x07 line.quad 0x00 "GICD_IROUTER455,Interrupt Routing Register 455" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E40++0x07 line.quad 0x00 "GICD_IROUTER456,Interrupt Routing Register 456" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E48++0x07 line.quad 0x00 "GICD_IROUTER457,Interrupt Routing Register 457" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E50++0x07 line.quad 0x00 "GICD_IROUTER458,Interrupt Routing Register 458" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E58++0x07 line.quad 0x00 "GICD_IROUTER459,Interrupt Routing Register 459" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E60++0x07 line.quad 0x00 "GICD_IROUTER460,Interrupt Routing Register 460" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E68++0x07 line.quad 0x00 "GICD_IROUTER461,Interrupt Routing Register 461" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E70++0x07 line.quad 0x00 "GICD_IROUTER462,Interrupt Routing Register 462" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E78++0x07 line.quad 0x00 "GICD_IROUTER463,Interrupt Routing Register 463" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E80++0x07 line.quad 0x00 "GICD_IROUTER464,Interrupt Routing Register 464" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E88++0x07 line.quad 0x00 "GICD_IROUTER465,Interrupt Routing Register 465" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E90++0x07 line.quad 0x00 "GICD_IROUTER466,Interrupt Routing Register 466" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E98++0x07 line.quad 0x00 "GICD_IROUTER467,Interrupt Routing Register 467" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA0++0x07 line.quad 0x00 "GICD_IROUTER468,Interrupt Routing Register 468" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA8++0x07 line.quad 0x00 "GICD_IROUTER469,Interrupt Routing Register 469" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB0++0x07 line.quad 0x00 "GICD_IROUTER470,Interrupt Routing Register 470" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB8++0x07 line.quad 0x00 "GICD_IROUTER471,Interrupt Routing Register 471" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC0++0x07 line.quad 0x00 "GICD_IROUTER472,Interrupt Routing Register 472" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC8++0x07 line.quad 0x00 "GICD_IROUTER473,Interrupt Routing Register 473" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED0++0x07 line.quad 0x00 "GICD_IROUTER474,Interrupt Routing Register 474" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED8++0x07 line.quad 0x00 "GICD_IROUTER475,Interrupt Routing Register 475" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE0++0x07 line.quad 0x00 "GICD_IROUTER476,Interrupt Routing Register 476" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE8++0x07 line.quad 0x00 "GICD_IROUTER477,Interrupt Routing Register 477" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF0++0x07 line.quad 0x00 "GICD_IROUTER478,Interrupt Routing Register 478" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF8++0x07 line.quad 0x00 "GICD_IROUTER479,Interrupt Routing Register 479" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F00++0x07 line.quad 0x00 "GICD_IROUTER480,Interrupt Routing Register 480" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F08++0x07 line.quad 0x00 "GICD_IROUTER481,Interrupt Routing Register 481" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F10++0x07 line.quad 0x00 "GICD_IROUTER482,Interrupt Routing Register 482" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F18++0x07 line.quad 0x00 "GICD_IROUTER483,Interrupt Routing Register 483" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F20++0x07 line.quad 0x00 "GICD_IROUTER484,Interrupt Routing Register 484" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F28++0x07 line.quad 0x00 "GICD_IROUTER485,Interrupt Routing Register 485" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F30++0x07 line.quad 0x00 "GICD_IROUTER486,Interrupt Routing Register 486" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F38++0x07 line.quad 0x00 "GICD_IROUTER487,Interrupt Routing Register 487" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F40++0x07 line.quad 0x00 "GICD_IROUTER488,Interrupt Routing Register 488" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F48++0x07 line.quad 0x00 "GICD_IROUTER489,Interrupt Routing Register 489" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F50++0x07 line.quad 0x00 "GICD_IROUTER490,Interrupt Routing Register 490" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F58++0x07 line.quad 0x00 "GICD_IROUTER491,Interrupt Routing Register 491" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F60++0x07 line.quad 0x00 "GICD_IROUTER492,Interrupt Routing Register 492" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F68++0x07 line.quad 0x00 "GICD_IROUTER493,Interrupt Routing Register 493" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F70++0x07 line.quad 0x00 "GICD_IROUTER494,Interrupt Routing Register 494" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F78++0x07 line.quad 0x00 "GICD_IROUTER495,Interrupt Routing Register 495" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F80++0x07 line.quad 0x00 "GICD_IROUTER496,Interrupt Routing Register 496" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F88++0x07 line.quad 0x00 "GICD_IROUTER497,Interrupt Routing Register 497" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F90++0x07 line.quad 0x00 "GICD_IROUTER498,Interrupt Routing Register 498" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F98++0x07 line.quad 0x00 "GICD_IROUTER499,Interrupt Routing Register 499" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA0++0x07 line.quad 0x00 "GICD_IROUTER500,Interrupt Routing Register 500" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA8++0x07 line.quad 0x00 "GICD_IROUTER501,Interrupt Routing Register 501" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB0++0x07 line.quad 0x00 "GICD_IROUTER502,Interrupt Routing Register 502" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB8++0x07 line.quad 0x00 "GICD_IROUTER503,Interrupt Routing Register 503" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC0++0x07 line.quad 0x00 "GICD_IROUTER504,Interrupt Routing Register 504" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC8++0x07 line.quad 0x00 "GICD_IROUTER505,Interrupt Routing Register 505" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD0++0x07 line.quad 0x00 "GICD_IROUTER506,Interrupt Routing Register 506" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD8++0x07 line.quad 0x00 "GICD_IROUTER507,Interrupt Routing Register 507" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE0++0x07 line.quad 0x00 "GICD_IROUTER508,Interrupt Routing Register 508" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE8++0x07 line.quad 0x00 "GICD_IROUTER509,Interrupt Routing Register 509" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF0++0x07 line.quad 0x00 "GICD_IROUTER510,Interrupt Routing Register 510" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF8++0x07 line.quad 0x00 "GICD_IROUTER511,Interrupt Routing Register 511" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7000++0x07 line.quad 0x00 "GICD_IROUTER512,Interrupt Routing Register 512" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7008++0x07 line.quad 0x00 "GICD_IROUTER513,Interrupt Routing Register 513" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7010++0x07 line.quad 0x00 "GICD_IROUTER514,Interrupt Routing Register 514" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7018++0x07 line.quad 0x00 "GICD_IROUTER515,Interrupt Routing Register 515" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7020++0x07 line.quad 0x00 "GICD_IROUTER516,Interrupt Routing Register 516" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7028++0x07 line.quad 0x00 "GICD_IROUTER517,Interrupt Routing Register 517" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7030++0x07 line.quad 0x00 "GICD_IROUTER518,Interrupt Routing Register 518" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7038++0x07 line.quad 0x00 "GICD_IROUTER519,Interrupt Routing Register 519" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7040++0x07 line.quad 0x00 "GICD_IROUTER520,Interrupt Routing Register 520" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7048++0x07 line.quad 0x00 "GICD_IROUTER521,Interrupt Routing Register 521" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7050++0x07 line.quad 0x00 "GICD_IROUTER522,Interrupt Routing Register 522" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7058++0x07 line.quad 0x00 "GICD_IROUTER523,Interrupt Routing Register 523" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7060++0x07 line.quad 0x00 "GICD_IROUTER524,Interrupt Routing Register 524" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7068++0x07 line.quad 0x00 "GICD_IROUTER525,Interrupt Routing Register 525" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7070++0x07 line.quad 0x00 "GICD_IROUTER526,Interrupt Routing Register 526" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7078++0x07 line.quad 0x00 "GICD_IROUTER527,Interrupt Routing Register 527" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7080++0x07 line.quad 0x00 "GICD_IROUTER528,Interrupt Routing Register 528" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7088++0x07 line.quad 0x00 "GICD_IROUTER529,Interrupt Routing Register 529" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7090++0x07 line.quad 0x00 "GICD_IROUTER530,Interrupt Routing Register 530" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7098++0x07 line.quad 0x00 "GICD_IROUTER531,Interrupt Routing Register 531" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A0++0x07 line.quad 0x00 "GICD_IROUTER532,Interrupt Routing Register 532" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A8++0x07 line.quad 0x00 "GICD_IROUTER533,Interrupt Routing Register 533" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B0++0x07 line.quad 0x00 "GICD_IROUTER534,Interrupt Routing Register 534" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B8++0x07 line.quad 0x00 "GICD_IROUTER535,Interrupt Routing Register 535" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C0++0x07 line.quad 0x00 "GICD_IROUTER536,Interrupt Routing Register 536" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C8++0x07 line.quad 0x00 "GICD_IROUTER537,Interrupt Routing Register 537" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D0++0x07 line.quad 0x00 "GICD_IROUTER538,Interrupt Routing Register 538" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D8++0x07 line.quad 0x00 "GICD_IROUTER539,Interrupt Routing Register 539" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E0++0x07 line.quad 0x00 "GICD_IROUTER540,Interrupt Routing Register 540" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E8++0x07 line.quad 0x00 "GICD_IROUTER541,Interrupt Routing Register 541" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F0++0x07 line.quad 0x00 "GICD_IROUTER542,Interrupt Routing Register 542" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F8++0x07 line.quad 0x00 "GICD_IROUTER543,Interrupt Routing Register 543" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7100++0x07 line.quad 0x00 "GICD_IROUTER544,Interrupt Routing Register 544" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7108++0x07 line.quad 0x00 "GICD_IROUTER545,Interrupt Routing Register 545" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7110++0x07 line.quad 0x00 "GICD_IROUTER546,Interrupt Routing Register 546" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7118++0x07 line.quad 0x00 "GICD_IROUTER547,Interrupt Routing Register 547" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7120++0x07 line.quad 0x00 "GICD_IROUTER548,Interrupt Routing Register 548" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7128++0x07 line.quad 0x00 "GICD_IROUTER549,Interrupt Routing Register 549" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7130++0x07 line.quad 0x00 "GICD_IROUTER550,Interrupt Routing Register 550" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7138++0x07 line.quad 0x00 "GICD_IROUTER551,Interrupt Routing Register 551" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7140++0x07 line.quad 0x00 "GICD_IROUTER552,Interrupt Routing Register 552" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7148++0x07 line.quad 0x00 "GICD_IROUTER553,Interrupt Routing Register 553" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7150++0x07 line.quad 0x00 "GICD_IROUTER554,Interrupt Routing Register 554" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7158++0x07 line.quad 0x00 "GICD_IROUTER555,Interrupt Routing Register 555" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7160++0x07 line.quad 0x00 "GICD_IROUTER556,Interrupt Routing Register 556" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7168++0x07 line.quad 0x00 "GICD_IROUTER557,Interrupt Routing Register 557" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7170++0x07 line.quad 0x00 "GICD_IROUTER558,Interrupt Routing Register 558" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7178++0x07 line.quad 0x00 "GICD_IROUTER559,Interrupt Routing Register 559" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7180++0x07 line.quad 0x00 "GICD_IROUTER560,Interrupt Routing Register 560" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7188++0x07 line.quad 0x00 "GICD_IROUTER561,Interrupt Routing Register 561" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7190++0x07 line.quad 0x00 "GICD_IROUTER562,Interrupt Routing Register 562" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7198++0x07 line.quad 0x00 "GICD_IROUTER563,Interrupt Routing Register 563" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A0++0x07 line.quad 0x00 "GICD_IROUTER564,Interrupt Routing Register 564" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A8++0x07 line.quad 0x00 "GICD_IROUTER565,Interrupt Routing Register 565" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B0++0x07 line.quad 0x00 "GICD_IROUTER566,Interrupt Routing Register 566" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B8++0x07 line.quad 0x00 "GICD_IROUTER567,Interrupt Routing Register 567" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C0++0x07 line.quad 0x00 "GICD_IROUTER568,Interrupt Routing Register 568" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C8++0x07 line.quad 0x00 "GICD_IROUTER569,Interrupt Routing Register 569" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D0++0x07 line.quad 0x00 "GICD_IROUTER570,Interrupt Routing Register 570" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D8++0x07 line.quad 0x00 "GICD_IROUTER571,Interrupt Routing Register 571" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E0++0x07 line.quad 0x00 "GICD_IROUTER572,Interrupt Routing Register 572" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E8++0x07 line.quad 0x00 "GICD_IROUTER573,Interrupt Routing Register 573" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F0++0x07 line.quad 0x00 "GICD_IROUTER574,Interrupt Routing Register 574" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F8++0x07 line.quad 0x00 "GICD_IROUTER575,Interrupt Routing Register 575" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7200++0x07 line.quad 0x00 "GICD_IROUTER576,Interrupt Routing Register 576" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7208++0x07 line.quad 0x00 "GICD_IROUTER577,Interrupt Routing Register 577" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7210++0x07 line.quad 0x00 "GICD_IROUTER578,Interrupt Routing Register 578" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7218++0x07 line.quad 0x00 "GICD_IROUTER579,Interrupt Routing Register 579" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7220++0x07 line.quad 0x00 "GICD_IROUTER580,Interrupt Routing Register 580" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7228++0x07 line.quad 0x00 "GICD_IROUTER581,Interrupt Routing Register 581" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7230++0x07 line.quad 0x00 "GICD_IROUTER582,Interrupt Routing Register 582" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7238++0x07 line.quad 0x00 "GICD_IROUTER583,Interrupt Routing Register 583" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7240++0x07 line.quad 0x00 "GICD_IROUTER584,Interrupt Routing Register 584" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7248++0x07 line.quad 0x00 "GICD_IROUTER585,Interrupt Routing Register 585" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7250++0x07 line.quad 0x00 "GICD_IROUTER586,Interrupt Routing Register 586" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7258++0x07 line.quad 0x00 "GICD_IROUTER587,Interrupt Routing Register 587" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7260++0x07 line.quad 0x00 "GICD_IROUTER588,Interrupt Routing Register 588" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7268++0x07 line.quad 0x00 "GICD_IROUTER589,Interrupt Routing Register 589" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7270++0x07 line.quad 0x00 "GICD_IROUTER590,Interrupt Routing Register 590" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7278++0x07 line.quad 0x00 "GICD_IROUTER591,Interrupt Routing Register 591" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7280++0x07 line.quad 0x00 "GICD_IROUTER592,Interrupt Routing Register 592" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7288++0x07 line.quad 0x00 "GICD_IROUTER593,Interrupt Routing Register 593" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7290++0x07 line.quad 0x00 "GICD_IROUTER594,Interrupt Routing Register 594" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7298++0x07 line.quad 0x00 "GICD_IROUTER595,Interrupt Routing Register 595" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A0++0x07 line.quad 0x00 "GICD_IROUTER596,Interrupt Routing Register 596" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A8++0x07 line.quad 0x00 "GICD_IROUTER597,Interrupt Routing Register 597" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B0++0x07 line.quad 0x00 "GICD_IROUTER598,Interrupt Routing Register 598" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B8++0x07 line.quad 0x00 "GICD_IROUTER599,Interrupt Routing Register 599" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C0++0x07 line.quad 0x00 "GICD_IROUTER600,Interrupt Routing Register 600" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C8++0x07 line.quad 0x00 "GICD_IROUTER601,Interrupt Routing Register 601" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D0++0x07 line.quad 0x00 "GICD_IROUTER602,Interrupt Routing Register 602" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D8++0x07 line.quad 0x00 "GICD_IROUTER603,Interrupt Routing Register 603" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E0++0x07 line.quad 0x00 "GICD_IROUTER604,Interrupt Routing Register 604" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E8++0x07 line.quad 0x00 "GICD_IROUTER605,Interrupt Routing Register 605" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F0++0x07 line.quad 0x00 "GICD_IROUTER606,Interrupt Routing Register 606" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F8++0x07 line.quad 0x00 "GICD_IROUTER607,Interrupt Routing Register 607" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7300++0x07 line.quad 0x00 "GICD_IROUTER608,Interrupt Routing Register 608" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7308++0x07 line.quad 0x00 "GICD_IROUTER609,Interrupt Routing Register 609" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7310++0x07 line.quad 0x00 "GICD_IROUTER610,Interrupt Routing Register 610" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7318++0x07 line.quad 0x00 "GICD_IROUTER611,Interrupt Routing Register 611" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7320++0x07 line.quad 0x00 "GICD_IROUTER612,Interrupt Routing Register 612" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7328++0x07 line.quad 0x00 "GICD_IROUTER613,Interrupt Routing Register 613" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7330++0x07 line.quad 0x00 "GICD_IROUTER614,Interrupt Routing Register 614" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7338++0x07 line.quad 0x00 "GICD_IROUTER615,Interrupt Routing Register 615" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7340++0x07 line.quad 0x00 "GICD_IROUTER616,Interrupt Routing Register 616" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7348++0x07 line.quad 0x00 "GICD_IROUTER617,Interrupt Routing Register 617" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7350++0x07 line.quad 0x00 "GICD_IROUTER618,Interrupt Routing Register 618" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7358++0x07 line.quad 0x00 "GICD_IROUTER619,Interrupt Routing Register 619" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7360++0x07 line.quad 0x00 "GICD_IROUTER620,Interrupt Routing Register 620" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7368++0x07 line.quad 0x00 "GICD_IROUTER621,Interrupt Routing Register 621" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7370++0x07 line.quad 0x00 "GICD_IROUTER622,Interrupt Routing Register 622" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7378++0x07 line.quad 0x00 "GICD_IROUTER623,Interrupt Routing Register 623" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7380++0x07 line.quad 0x00 "GICD_IROUTER624,Interrupt Routing Register 624" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7388++0x07 line.quad 0x00 "GICD_IROUTER625,Interrupt Routing Register 625" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7390++0x07 line.quad 0x00 "GICD_IROUTER626,Interrupt Routing Register 626" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7398++0x07 line.quad 0x00 "GICD_IROUTER627,Interrupt Routing Register 627" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A0++0x07 line.quad 0x00 "GICD_IROUTER628,Interrupt Routing Register 628" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A8++0x07 line.quad 0x00 "GICD_IROUTER629,Interrupt Routing Register 629" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B0++0x07 line.quad 0x00 "GICD_IROUTER630,Interrupt Routing Register 630" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B8++0x07 line.quad 0x00 "GICD_IROUTER631,Interrupt Routing Register 631" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C0++0x07 line.quad 0x00 "GICD_IROUTER632,Interrupt Routing Register 632" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C8++0x07 line.quad 0x00 "GICD_IROUTER633,Interrupt Routing Register 633" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D0++0x07 line.quad 0x00 "GICD_IROUTER634,Interrupt Routing Register 634" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D8++0x07 line.quad 0x00 "GICD_IROUTER635,Interrupt Routing Register 635" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E0++0x07 line.quad 0x00 "GICD_IROUTER636,Interrupt Routing Register 636" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E8++0x07 line.quad 0x00 "GICD_IROUTER637,Interrupt Routing Register 637" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F0++0x07 line.quad 0x00 "GICD_IROUTER638,Interrupt Routing Register 638" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F8++0x07 line.quad 0x00 "GICD_IROUTER639,Interrupt Routing Register 639" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7400++0x07 line.quad 0x00 "GICD_IROUTER640,Interrupt Routing Register 640" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7408++0x07 line.quad 0x00 "GICD_IROUTER641,Interrupt Routing Register 641" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7410++0x07 line.quad 0x00 "GICD_IROUTER642,Interrupt Routing Register 642" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7418++0x07 line.quad 0x00 "GICD_IROUTER643,Interrupt Routing Register 643" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7420++0x07 line.quad 0x00 "GICD_IROUTER644,Interrupt Routing Register 644" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7428++0x07 line.quad 0x00 "GICD_IROUTER645,Interrupt Routing Register 645" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7430++0x07 line.quad 0x00 "GICD_IROUTER646,Interrupt Routing Register 646" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7438++0x07 line.quad 0x00 "GICD_IROUTER647,Interrupt Routing Register 647" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7440++0x07 line.quad 0x00 "GICD_IROUTER648,Interrupt Routing Register 648" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7448++0x07 line.quad 0x00 "GICD_IROUTER649,Interrupt Routing Register 649" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7450++0x07 line.quad 0x00 "GICD_IROUTER650,Interrupt Routing Register 650" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7458++0x07 line.quad 0x00 "GICD_IROUTER651,Interrupt Routing Register 651" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7460++0x07 line.quad 0x00 "GICD_IROUTER652,Interrupt Routing Register 652" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7468++0x07 line.quad 0x00 "GICD_IROUTER653,Interrupt Routing Register 653" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7470++0x07 line.quad 0x00 "GICD_IROUTER654,Interrupt Routing Register 654" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7478++0x07 line.quad 0x00 "GICD_IROUTER655,Interrupt Routing Register 655" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7480++0x07 line.quad 0x00 "GICD_IROUTER656,Interrupt Routing Register 656" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7488++0x07 line.quad 0x00 "GICD_IROUTER657,Interrupt Routing Register 657" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7490++0x07 line.quad 0x00 "GICD_IROUTER658,Interrupt Routing Register 658" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7498++0x07 line.quad 0x00 "GICD_IROUTER659,Interrupt Routing Register 659" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A0++0x07 line.quad 0x00 "GICD_IROUTER660,Interrupt Routing Register 660" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A8++0x07 line.quad 0x00 "GICD_IROUTER661,Interrupt Routing Register 661" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B0++0x07 line.quad 0x00 "GICD_IROUTER662,Interrupt Routing Register 662" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B8++0x07 line.quad 0x00 "GICD_IROUTER663,Interrupt Routing Register 663" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C0++0x07 line.quad 0x00 "GICD_IROUTER664,Interrupt Routing Register 664" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C8++0x07 line.quad 0x00 "GICD_IROUTER665,Interrupt Routing Register 665" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D0++0x07 line.quad 0x00 "GICD_IROUTER666,Interrupt Routing Register 666" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D8++0x07 line.quad 0x00 "GICD_IROUTER667,Interrupt Routing Register 667" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E0++0x07 line.quad 0x00 "GICD_IROUTER668,Interrupt Routing Register 668" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E8++0x07 line.quad 0x00 "GICD_IROUTER669,Interrupt Routing Register 669" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F0++0x07 line.quad 0x00 "GICD_IROUTER670,Interrupt Routing Register 670" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F8++0x07 line.quad 0x00 "GICD_IROUTER671,Interrupt Routing Register 671" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7500++0x07 line.quad 0x00 "GICD_IROUTER672,Interrupt Routing Register 672" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7508++0x07 line.quad 0x00 "GICD_IROUTER673,Interrupt Routing Register 673" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7510++0x07 line.quad 0x00 "GICD_IROUTER674,Interrupt Routing Register 674" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7518++0x07 line.quad 0x00 "GICD_IROUTER675,Interrupt Routing Register 675" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7520++0x07 line.quad 0x00 "GICD_IROUTER676,Interrupt Routing Register 676" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7528++0x07 line.quad 0x00 "GICD_IROUTER677,Interrupt Routing Register 677" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7530++0x07 line.quad 0x00 "GICD_IROUTER678,Interrupt Routing Register 678" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7538++0x07 line.quad 0x00 "GICD_IROUTER679,Interrupt Routing Register 679" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7540++0x07 line.quad 0x00 "GICD_IROUTER680,Interrupt Routing Register 680" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7548++0x07 line.quad 0x00 "GICD_IROUTER681,Interrupt Routing Register 681" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7550++0x07 line.quad 0x00 "GICD_IROUTER682,Interrupt Routing Register 682" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7558++0x07 line.quad 0x00 "GICD_IROUTER683,Interrupt Routing Register 683" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7560++0x07 line.quad 0x00 "GICD_IROUTER684,Interrupt Routing Register 684" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7568++0x07 line.quad 0x00 "GICD_IROUTER685,Interrupt Routing Register 685" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7570++0x07 line.quad 0x00 "GICD_IROUTER686,Interrupt Routing Register 686" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7578++0x07 line.quad 0x00 "GICD_IROUTER687,Interrupt Routing Register 687" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7580++0x07 line.quad 0x00 "GICD_IROUTER688,Interrupt Routing Register 688" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7588++0x07 line.quad 0x00 "GICD_IROUTER689,Interrupt Routing Register 689" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7590++0x07 line.quad 0x00 "GICD_IROUTER690,Interrupt Routing Register 690" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7598++0x07 line.quad 0x00 "GICD_IROUTER691,Interrupt Routing Register 691" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A0++0x07 line.quad 0x00 "GICD_IROUTER692,Interrupt Routing Register 692" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A8++0x07 line.quad 0x00 "GICD_IROUTER693,Interrupt Routing Register 693" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B0++0x07 line.quad 0x00 "GICD_IROUTER694,Interrupt Routing Register 694" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B8++0x07 line.quad 0x00 "GICD_IROUTER695,Interrupt Routing Register 695" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C0++0x07 line.quad 0x00 "GICD_IROUTER696,Interrupt Routing Register 696" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C8++0x07 line.quad 0x00 "GICD_IROUTER697,Interrupt Routing Register 697" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D0++0x07 line.quad 0x00 "GICD_IROUTER698,Interrupt Routing Register 698" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D8++0x07 line.quad 0x00 "GICD_IROUTER699,Interrupt Routing Register 699" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E0++0x07 line.quad 0x00 "GICD_IROUTER700,Interrupt Routing Register 700" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E8++0x07 line.quad 0x00 "GICD_IROUTER701,Interrupt Routing Register 701" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F0++0x07 line.quad 0x00 "GICD_IROUTER702,Interrupt Routing Register 702" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F8++0x07 line.quad 0x00 "GICD_IROUTER703,Interrupt Routing Register 703" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7600++0x07 line.quad 0x00 "GICD_IROUTER704,Interrupt Routing Register 704" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7608++0x07 line.quad 0x00 "GICD_IROUTER705,Interrupt Routing Register 705" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7610++0x07 line.quad 0x00 "GICD_IROUTER706,Interrupt Routing Register 706" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7618++0x07 line.quad 0x00 "GICD_IROUTER707,Interrupt Routing Register 707" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7620++0x07 line.quad 0x00 "GICD_IROUTER708,Interrupt Routing Register 708" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7628++0x07 line.quad 0x00 "GICD_IROUTER709,Interrupt Routing Register 709" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7630++0x07 line.quad 0x00 "GICD_IROUTER710,Interrupt Routing Register 710" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7638++0x07 line.quad 0x00 "GICD_IROUTER711,Interrupt Routing Register 711" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7640++0x07 line.quad 0x00 "GICD_IROUTER712,Interrupt Routing Register 712" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7648++0x07 line.quad 0x00 "GICD_IROUTER713,Interrupt Routing Register 713" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7650++0x07 line.quad 0x00 "GICD_IROUTER714,Interrupt Routing Register 714" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7658++0x07 line.quad 0x00 "GICD_IROUTER715,Interrupt Routing Register 715" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7660++0x07 line.quad 0x00 "GICD_IROUTER716,Interrupt Routing Register 716" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7668++0x07 line.quad 0x00 "GICD_IROUTER717,Interrupt Routing Register 717" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7670++0x07 line.quad 0x00 "GICD_IROUTER718,Interrupt Routing Register 718" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7678++0x07 line.quad 0x00 "GICD_IROUTER719,Interrupt Routing Register 719" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7680++0x07 line.quad 0x00 "GICD_IROUTER720,Interrupt Routing Register 720" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7688++0x07 line.quad 0x00 "GICD_IROUTER721,Interrupt Routing Register 721" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7690++0x07 line.quad 0x00 "GICD_IROUTER722,Interrupt Routing Register 722" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7698++0x07 line.quad 0x00 "GICD_IROUTER723,Interrupt Routing Register 723" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A0++0x07 line.quad 0x00 "GICD_IROUTER724,Interrupt Routing Register 724" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A8++0x07 line.quad 0x00 "GICD_IROUTER725,Interrupt Routing Register 725" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B0++0x07 line.quad 0x00 "GICD_IROUTER726,Interrupt Routing Register 726" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B8++0x07 line.quad 0x00 "GICD_IROUTER727,Interrupt Routing Register 727" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C0++0x07 line.quad 0x00 "GICD_IROUTER728,Interrupt Routing Register 728" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C8++0x07 line.quad 0x00 "GICD_IROUTER729,Interrupt Routing Register 729" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D0++0x07 line.quad 0x00 "GICD_IROUTER730,Interrupt Routing Register 730" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D8++0x07 line.quad 0x00 "GICD_IROUTER731,Interrupt Routing Register 731" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E0++0x07 line.quad 0x00 "GICD_IROUTER732,Interrupt Routing Register 732" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E8++0x07 line.quad 0x00 "GICD_IROUTER733,Interrupt Routing Register 733" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F0++0x07 line.quad 0x00 "GICD_IROUTER734,Interrupt Routing Register 734" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F8++0x07 line.quad 0x00 "GICD_IROUTER735,Interrupt Routing Register 735" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7700++0x07 line.quad 0x00 "GICD_IROUTER736,Interrupt Routing Register 736" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7708++0x07 line.quad 0x00 "GICD_IROUTER737,Interrupt Routing Register 737" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7710++0x07 line.quad 0x00 "GICD_IROUTER738,Interrupt Routing Register 738" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7718++0x07 line.quad 0x00 "GICD_IROUTER739,Interrupt Routing Register 739" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7720++0x07 line.quad 0x00 "GICD_IROUTER740,Interrupt Routing Register 740" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7728++0x07 line.quad 0x00 "GICD_IROUTER741,Interrupt Routing Register 741" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7730++0x07 line.quad 0x00 "GICD_IROUTER742,Interrupt Routing Register 742" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7738++0x07 line.quad 0x00 "GICD_IROUTER743,Interrupt Routing Register 743" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7740++0x07 line.quad 0x00 "GICD_IROUTER744,Interrupt Routing Register 744" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7748++0x07 line.quad 0x00 "GICD_IROUTER745,Interrupt Routing Register 745" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7750++0x07 line.quad 0x00 "GICD_IROUTER746,Interrupt Routing Register 746" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7758++0x07 line.quad 0x00 "GICD_IROUTER747,Interrupt Routing Register 747" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7760++0x07 line.quad 0x00 "GICD_IROUTER748,Interrupt Routing Register 748" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7768++0x07 line.quad 0x00 "GICD_IROUTER749,Interrupt Routing Register 749" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7770++0x07 line.quad 0x00 "GICD_IROUTER750,Interrupt Routing Register 750" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7778++0x07 line.quad 0x00 "GICD_IROUTER751,Interrupt Routing Register 751" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7780++0x07 line.quad 0x00 "GICD_IROUTER752,Interrupt Routing Register 752" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7788++0x07 line.quad 0x00 "GICD_IROUTER753,Interrupt Routing Register 753" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7790++0x07 line.quad 0x00 "GICD_IROUTER754,Interrupt Routing Register 754" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7798++0x07 line.quad 0x00 "GICD_IROUTER755,Interrupt Routing Register 755" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A0++0x07 line.quad 0x00 "GICD_IROUTER756,Interrupt Routing Register 756" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A8++0x07 line.quad 0x00 "GICD_IROUTER757,Interrupt Routing Register 757" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B0++0x07 line.quad 0x00 "GICD_IROUTER758,Interrupt Routing Register 758" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B8++0x07 line.quad 0x00 "GICD_IROUTER759,Interrupt Routing Register 759" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C0++0x07 line.quad 0x00 "GICD_IROUTER760,Interrupt Routing Register 760" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C8++0x07 line.quad 0x00 "GICD_IROUTER761,Interrupt Routing Register 761" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D0++0x07 line.quad 0x00 "GICD_IROUTER762,Interrupt Routing Register 762" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D8++0x07 line.quad 0x00 "GICD_IROUTER763,Interrupt Routing Register 763" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E0++0x07 line.quad 0x00 "GICD_IROUTER764,Interrupt Routing Register 764" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E8++0x07 line.quad 0x00 "GICD_IROUTER765,Interrupt Routing Register 765" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F0++0x07 line.quad 0x00 "GICD_IROUTER766,Interrupt Routing Register 766" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F8++0x07 line.quad 0x00 "GICD_IROUTER767,Interrupt Routing Register 767" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7800++0x07 line.quad 0x00 "GICD_IROUTER768,Interrupt Routing Register 768" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7808++0x07 line.quad 0x00 "GICD_IROUTER769,Interrupt Routing Register 769" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7810++0x07 line.quad 0x00 "GICD_IROUTER770,Interrupt Routing Register 770" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7818++0x07 line.quad 0x00 "GICD_IROUTER771,Interrupt Routing Register 771" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7820++0x07 line.quad 0x00 "GICD_IROUTER772,Interrupt Routing Register 772" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7828++0x07 line.quad 0x00 "GICD_IROUTER773,Interrupt Routing Register 773" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7830++0x07 line.quad 0x00 "GICD_IROUTER774,Interrupt Routing Register 774" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7838++0x07 line.quad 0x00 "GICD_IROUTER775,Interrupt Routing Register 775" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7840++0x07 line.quad 0x00 "GICD_IROUTER776,Interrupt Routing Register 776" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7848++0x07 line.quad 0x00 "GICD_IROUTER777,Interrupt Routing Register 777" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7850++0x07 line.quad 0x00 "GICD_IROUTER778,Interrupt Routing Register 778" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7858++0x07 line.quad 0x00 "GICD_IROUTER779,Interrupt Routing Register 779" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7860++0x07 line.quad 0x00 "GICD_IROUTER780,Interrupt Routing Register 780" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7868++0x07 line.quad 0x00 "GICD_IROUTER781,Interrupt Routing Register 781" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7870++0x07 line.quad 0x00 "GICD_IROUTER782,Interrupt Routing Register 782" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7878++0x07 line.quad 0x00 "GICD_IROUTER783,Interrupt Routing Register 783" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7880++0x07 line.quad 0x00 "GICD_IROUTER784,Interrupt Routing Register 784" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7888++0x07 line.quad 0x00 "GICD_IROUTER785,Interrupt Routing Register 785" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7890++0x07 line.quad 0x00 "GICD_IROUTER786,Interrupt Routing Register 786" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7898++0x07 line.quad 0x00 "GICD_IROUTER787,Interrupt Routing Register 787" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A0++0x07 line.quad 0x00 "GICD_IROUTER788,Interrupt Routing Register 788" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A8++0x07 line.quad 0x00 "GICD_IROUTER789,Interrupt Routing Register 789" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B0++0x07 line.quad 0x00 "GICD_IROUTER790,Interrupt Routing Register 790" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B8++0x07 line.quad 0x00 "GICD_IROUTER791,Interrupt Routing Register 791" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C0++0x07 line.quad 0x00 "GICD_IROUTER792,Interrupt Routing Register 792" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C8++0x07 line.quad 0x00 "GICD_IROUTER793,Interrupt Routing Register 793" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D0++0x07 line.quad 0x00 "GICD_IROUTER794,Interrupt Routing Register 794" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D8++0x07 line.quad 0x00 "GICD_IROUTER795,Interrupt Routing Register 795" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E0++0x07 line.quad 0x00 "GICD_IROUTER796,Interrupt Routing Register 796" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E8++0x07 line.quad 0x00 "GICD_IROUTER797,Interrupt Routing Register 797" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F0++0x07 line.quad 0x00 "GICD_IROUTER798,Interrupt Routing Register 798" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F8++0x07 line.quad 0x00 "GICD_IROUTER799,Interrupt Routing Register 799" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7900++0x07 line.quad 0x00 "GICD_IROUTER800,Interrupt Routing Register 800" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7908++0x07 line.quad 0x00 "GICD_IROUTER801,Interrupt Routing Register 801" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7910++0x07 line.quad 0x00 "GICD_IROUTER802,Interrupt Routing Register 802" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7918++0x07 line.quad 0x00 "GICD_IROUTER803,Interrupt Routing Register 803" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7920++0x07 line.quad 0x00 "GICD_IROUTER804,Interrupt Routing Register 804" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7928++0x07 line.quad 0x00 "GICD_IROUTER805,Interrupt Routing Register 805" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7930++0x07 line.quad 0x00 "GICD_IROUTER806,Interrupt Routing Register 806" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7938++0x07 line.quad 0x00 "GICD_IROUTER807,Interrupt Routing Register 807" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7940++0x07 line.quad 0x00 "GICD_IROUTER808,Interrupt Routing Register 808" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7948++0x07 line.quad 0x00 "GICD_IROUTER809,Interrupt Routing Register 809" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7950++0x07 line.quad 0x00 "GICD_IROUTER810,Interrupt Routing Register 810" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7958++0x07 line.quad 0x00 "GICD_IROUTER811,Interrupt Routing Register 811" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7960++0x07 line.quad 0x00 "GICD_IROUTER812,Interrupt Routing Register 812" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7968++0x07 line.quad 0x00 "GICD_IROUTER813,Interrupt Routing Register 813" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7970++0x07 line.quad 0x00 "GICD_IROUTER814,Interrupt Routing Register 814" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7978++0x07 line.quad 0x00 "GICD_IROUTER815,Interrupt Routing Register 815" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7980++0x07 line.quad 0x00 "GICD_IROUTER816,Interrupt Routing Register 816" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7988++0x07 line.quad 0x00 "GICD_IROUTER817,Interrupt Routing Register 817" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7990++0x07 line.quad 0x00 "GICD_IROUTER818,Interrupt Routing Register 818" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7998++0x07 line.quad 0x00 "GICD_IROUTER819,Interrupt Routing Register 819" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A0++0x07 line.quad 0x00 "GICD_IROUTER820,Interrupt Routing Register 820" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A8++0x07 line.quad 0x00 "GICD_IROUTER821,Interrupt Routing Register 821" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B0++0x07 line.quad 0x00 "GICD_IROUTER822,Interrupt Routing Register 822" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B8++0x07 line.quad 0x00 "GICD_IROUTER823,Interrupt Routing Register 823" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C0++0x07 line.quad 0x00 "GICD_IROUTER824,Interrupt Routing Register 824" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C8++0x07 line.quad 0x00 "GICD_IROUTER825,Interrupt Routing Register 825" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D0++0x07 line.quad 0x00 "GICD_IROUTER826,Interrupt Routing Register 826" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D8++0x07 line.quad 0x00 "GICD_IROUTER827,Interrupt Routing Register 827" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E0++0x07 line.quad 0x00 "GICD_IROUTER828,Interrupt Routing Register 828" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E8++0x07 line.quad 0x00 "GICD_IROUTER829,Interrupt Routing Register 829" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F0++0x07 line.quad 0x00 "GICD_IROUTER830,Interrupt Routing Register 830" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F8++0x07 line.quad 0x00 "GICD_IROUTER831,Interrupt Routing Register 831" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A00++0x07 line.quad 0x00 "GICD_IROUTER832,Interrupt Routing Register 832" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A08++0x07 line.quad 0x00 "GICD_IROUTER833,Interrupt Routing Register 833" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A10++0x07 line.quad 0x00 "GICD_IROUTER834,Interrupt Routing Register 834" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A18++0x07 line.quad 0x00 "GICD_IROUTER835,Interrupt Routing Register 835" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A20++0x07 line.quad 0x00 "GICD_IROUTER836,Interrupt Routing Register 836" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A28++0x07 line.quad 0x00 "GICD_IROUTER837,Interrupt Routing Register 837" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A30++0x07 line.quad 0x00 "GICD_IROUTER838,Interrupt Routing Register 838" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A38++0x07 line.quad 0x00 "GICD_IROUTER839,Interrupt Routing Register 839" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A40++0x07 line.quad 0x00 "GICD_IROUTER840,Interrupt Routing Register 840" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A48++0x07 line.quad 0x00 "GICD_IROUTER841,Interrupt Routing Register 841" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A50++0x07 line.quad 0x00 "GICD_IROUTER842,Interrupt Routing Register 842" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A58++0x07 line.quad 0x00 "GICD_IROUTER843,Interrupt Routing Register 843" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A60++0x07 line.quad 0x00 "GICD_IROUTER844,Interrupt Routing Register 844" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A68++0x07 line.quad 0x00 "GICD_IROUTER845,Interrupt Routing Register 845" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A70++0x07 line.quad 0x00 "GICD_IROUTER846,Interrupt Routing Register 846" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A78++0x07 line.quad 0x00 "GICD_IROUTER847,Interrupt Routing Register 847" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A80++0x07 line.quad 0x00 "GICD_IROUTER848,Interrupt Routing Register 848" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A88++0x07 line.quad 0x00 "GICD_IROUTER849,Interrupt Routing Register 849" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A90++0x07 line.quad 0x00 "GICD_IROUTER850,Interrupt Routing Register 850" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A98++0x07 line.quad 0x00 "GICD_IROUTER851,Interrupt Routing Register 851" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA0++0x07 line.quad 0x00 "GICD_IROUTER852,Interrupt Routing Register 852" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA8++0x07 line.quad 0x00 "GICD_IROUTER853,Interrupt Routing Register 853" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB0++0x07 line.quad 0x00 "GICD_IROUTER854,Interrupt Routing Register 854" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB8++0x07 line.quad 0x00 "GICD_IROUTER855,Interrupt Routing Register 855" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC0++0x07 line.quad 0x00 "GICD_IROUTER856,Interrupt Routing Register 856" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC8++0x07 line.quad 0x00 "GICD_IROUTER857,Interrupt Routing Register 857" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD0++0x07 line.quad 0x00 "GICD_IROUTER858,Interrupt Routing Register 858" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD8++0x07 line.quad 0x00 "GICD_IROUTER859,Interrupt Routing Register 859" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE0++0x07 line.quad 0x00 "GICD_IROUTER860,Interrupt Routing Register 860" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE8++0x07 line.quad 0x00 "GICD_IROUTER861,Interrupt Routing Register 861" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF0++0x07 line.quad 0x00 "GICD_IROUTER862,Interrupt Routing Register 862" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF8++0x07 line.quad 0x00 "GICD_IROUTER863,Interrupt Routing Register 863" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B00++0x07 line.quad 0x00 "GICD_IROUTER864,Interrupt Routing Register 864" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B08++0x07 line.quad 0x00 "GICD_IROUTER865,Interrupt Routing Register 865" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B10++0x07 line.quad 0x00 "GICD_IROUTER866,Interrupt Routing Register 866" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B18++0x07 line.quad 0x00 "GICD_IROUTER867,Interrupt Routing Register 867" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B20++0x07 line.quad 0x00 "GICD_IROUTER868,Interrupt Routing Register 868" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B28++0x07 line.quad 0x00 "GICD_IROUTER869,Interrupt Routing Register 869" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B30++0x07 line.quad 0x00 "GICD_IROUTER870,Interrupt Routing Register 870" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B38++0x07 line.quad 0x00 "GICD_IROUTER871,Interrupt Routing Register 871" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B40++0x07 line.quad 0x00 "GICD_IROUTER872,Interrupt Routing Register 872" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B48++0x07 line.quad 0x00 "GICD_IROUTER873,Interrupt Routing Register 873" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B50++0x07 line.quad 0x00 "GICD_IROUTER874,Interrupt Routing Register 874" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B58++0x07 line.quad 0x00 "GICD_IROUTER875,Interrupt Routing Register 875" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B60++0x07 line.quad 0x00 "GICD_IROUTER876,Interrupt Routing Register 876" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B68++0x07 line.quad 0x00 "GICD_IROUTER877,Interrupt Routing Register 877" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B70++0x07 line.quad 0x00 "GICD_IROUTER878,Interrupt Routing Register 878" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B78++0x07 line.quad 0x00 "GICD_IROUTER879,Interrupt Routing Register 879" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B80++0x07 line.quad 0x00 "GICD_IROUTER880,Interrupt Routing Register 880" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B88++0x07 line.quad 0x00 "GICD_IROUTER881,Interrupt Routing Register 881" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B90++0x07 line.quad 0x00 "GICD_IROUTER882,Interrupt Routing Register 882" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B98++0x07 line.quad 0x00 "GICD_IROUTER883,Interrupt Routing Register 883" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA0++0x07 line.quad 0x00 "GICD_IROUTER884,Interrupt Routing Register 884" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA8++0x07 line.quad 0x00 "GICD_IROUTER885,Interrupt Routing Register 885" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB0++0x07 line.quad 0x00 "GICD_IROUTER886,Interrupt Routing Register 886" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB8++0x07 line.quad 0x00 "GICD_IROUTER887,Interrupt Routing Register 887" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC0++0x07 line.quad 0x00 "GICD_IROUTER888,Interrupt Routing Register 888" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC8++0x07 line.quad 0x00 "GICD_IROUTER889,Interrupt Routing Register 889" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD0++0x07 line.quad 0x00 "GICD_IROUTER890,Interrupt Routing Register 890" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD8++0x07 line.quad 0x00 "GICD_IROUTER891,Interrupt Routing Register 891" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE0++0x07 line.quad 0x00 "GICD_IROUTER892,Interrupt Routing Register 892" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE8++0x07 line.quad 0x00 "GICD_IROUTER893,Interrupt Routing Register 893" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF0++0x07 line.quad 0x00 "GICD_IROUTER894,Interrupt Routing Register 894" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF8++0x07 line.quad 0x00 "GICD_IROUTER895,Interrupt Routing Register 895" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C00++0x07 line.quad 0x00 "GICD_IROUTER896,Interrupt Routing Register 896" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C08++0x07 line.quad 0x00 "GICD_IROUTER897,Interrupt Routing Register 897" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C10++0x07 line.quad 0x00 "GICD_IROUTER898,Interrupt Routing Register 898" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C18++0x07 line.quad 0x00 "GICD_IROUTER899,Interrupt Routing Register 899" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C20++0x07 line.quad 0x00 "GICD_IROUTER900,Interrupt Routing Register 900" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C28++0x07 line.quad 0x00 "GICD_IROUTER901,Interrupt Routing Register 901" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C30++0x07 line.quad 0x00 "GICD_IROUTER902,Interrupt Routing Register 902" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C38++0x07 line.quad 0x00 "GICD_IROUTER903,Interrupt Routing Register 903" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C40++0x07 line.quad 0x00 "GICD_IROUTER904,Interrupt Routing Register 904" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C48++0x07 line.quad 0x00 "GICD_IROUTER905,Interrupt Routing Register 905" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C50++0x07 line.quad 0x00 "GICD_IROUTER906,Interrupt Routing Register 906" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C58++0x07 line.quad 0x00 "GICD_IROUTER907,Interrupt Routing Register 907" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C60++0x07 line.quad 0x00 "GICD_IROUTER908,Interrupt Routing Register 908" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C68++0x07 line.quad 0x00 "GICD_IROUTER909,Interrupt Routing Register 909" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C70++0x07 line.quad 0x00 "GICD_IROUTER910,Interrupt Routing Register 910" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C78++0x07 line.quad 0x00 "GICD_IROUTER911,Interrupt Routing Register 911" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C80++0x07 line.quad 0x00 "GICD_IROUTER912,Interrupt Routing Register 912" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C88++0x07 line.quad 0x00 "GICD_IROUTER913,Interrupt Routing Register 913" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C90++0x07 line.quad 0x00 "GICD_IROUTER914,Interrupt Routing Register 914" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C98++0x07 line.quad 0x00 "GICD_IROUTER915,Interrupt Routing Register 915" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA0++0x07 line.quad 0x00 "GICD_IROUTER916,Interrupt Routing Register 916" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA8++0x07 line.quad 0x00 "GICD_IROUTER917,Interrupt Routing Register 917" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB0++0x07 line.quad 0x00 "GICD_IROUTER918,Interrupt Routing Register 918" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB8++0x07 line.quad 0x00 "GICD_IROUTER919,Interrupt Routing Register 919" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC0++0x07 line.quad 0x00 "GICD_IROUTER920,Interrupt Routing Register 920" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC8++0x07 line.quad 0x00 "GICD_IROUTER921,Interrupt Routing Register 921" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD0++0x07 line.quad 0x00 "GICD_IROUTER922,Interrupt Routing Register 922" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD8++0x07 line.quad 0x00 "GICD_IROUTER923,Interrupt Routing Register 923" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE0++0x07 line.quad 0x00 "GICD_IROUTER924,Interrupt Routing Register 924" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE8++0x07 line.quad 0x00 "GICD_IROUTER925,Interrupt Routing Register 925" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF0++0x07 line.quad 0x00 "GICD_IROUTER926,Interrupt Routing Register 926" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF8++0x07 line.quad 0x00 "GICD_IROUTER927,Interrupt Routing Register 927" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D00++0x07 line.quad 0x00 "GICD_IROUTER928,Interrupt Routing Register 928" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D08++0x07 line.quad 0x00 "GICD_IROUTER929,Interrupt Routing Register 929" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D10++0x07 line.quad 0x00 "GICD_IROUTER930,Interrupt Routing Register 930" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D18++0x07 line.quad 0x00 "GICD_IROUTER931,Interrupt Routing Register 931" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D20++0x07 line.quad 0x00 "GICD_IROUTER932,Interrupt Routing Register 932" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D28++0x07 line.quad 0x00 "GICD_IROUTER933,Interrupt Routing Register 933" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D30++0x07 line.quad 0x00 "GICD_IROUTER934,Interrupt Routing Register 934" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D38++0x07 line.quad 0x00 "GICD_IROUTER935,Interrupt Routing Register 935" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D40++0x07 line.quad 0x00 "GICD_IROUTER936,Interrupt Routing Register 936" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D48++0x07 line.quad 0x00 "GICD_IROUTER937,Interrupt Routing Register 937" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D50++0x07 line.quad 0x00 "GICD_IROUTER938,Interrupt Routing Register 938" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D58++0x07 line.quad 0x00 "GICD_IROUTER939,Interrupt Routing Register 939" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D60++0x07 line.quad 0x00 "GICD_IROUTER940,Interrupt Routing Register 940" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D68++0x07 line.quad 0x00 "GICD_IROUTER941,Interrupt Routing Register 941" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D70++0x07 line.quad 0x00 "GICD_IROUTER942,Interrupt Routing Register 942" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D78++0x07 line.quad 0x00 "GICD_IROUTER943,Interrupt Routing Register 943" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D80++0x07 line.quad 0x00 "GICD_IROUTER944,Interrupt Routing Register 944" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D88++0x07 line.quad 0x00 "GICD_IROUTER945,Interrupt Routing Register 945" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D90++0x07 line.quad 0x00 "GICD_IROUTER946,Interrupt Routing Register 946" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D98++0x07 line.quad 0x00 "GICD_IROUTER947,Interrupt Routing Register 947" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA0++0x07 line.quad 0x00 "GICD_IROUTER948,Interrupt Routing Register 948" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA8++0x07 line.quad 0x00 "GICD_IROUTER949,Interrupt Routing Register 949" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB0++0x07 line.quad 0x00 "GICD_IROUTER950,Interrupt Routing Register 950" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB8++0x07 line.quad 0x00 "GICD_IROUTER951,Interrupt Routing Register 951" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC0++0x07 line.quad 0x00 "GICD_IROUTER952,Interrupt Routing Register 952" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC8++0x07 line.quad 0x00 "GICD_IROUTER953,Interrupt Routing Register 953" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD0++0x07 line.quad 0x00 "GICD_IROUTER954,Interrupt Routing Register 954" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD8++0x07 line.quad 0x00 "GICD_IROUTER955,Interrupt Routing Register 955" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE0++0x07 line.quad 0x00 "GICD_IROUTER956,Interrupt Routing Register 956" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE8++0x07 line.quad 0x00 "GICD_IROUTER957,Interrupt Routing Register 957" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF0++0x07 line.quad 0x00 "GICD_IROUTER958,Interrupt Routing Register 958" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF8++0x07 line.quad 0x00 "GICD_IROUTER959,Interrupt Routing Register 959" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E00++0x07 line.quad 0x00 "GICD_IROUTER960,Interrupt Routing Register 960" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E08++0x07 line.quad 0x00 "GICD_IROUTER961,Interrupt Routing Register 961" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E10++0x07 line.quad 0x00 "GICD_IROUTER962,Interrupt Routing Register 962" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E18++0x07 line.quad 0x00 "GICD_IROUTER963,Interrupt Routing Register 963" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E20++0x07 line.quad 0x00 "GICD_IROUTER964,Interrupt Routing Register 964" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E28++0x07 line.quad 0x00 "GICD_IROUTER965,Interrupt Routing Register 965" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E30++0x07 line.quad 0x00 "GICD_IROUTER966,Interrupt Routing Register 966" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E38++0x07 line.quad 0x00 "GICD_IROUTER967,Interrupt Routing Register 967" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E40++0x07 line.quad 0x00 "GICD_IROUTER968,Interrupt Routing Register 968" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E48++0x07 line.quad 0x00 "GICD_IROUTER969,Interrupt Routing Register 969" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E50++0x07 line.quad 0x00 "GICD_IROUTER970,Interrupt Routing Register 970" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E58++0x07 line.quad 0x00 "GICD_IROUTER971,Interrupt Routing Register 971" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E60++0x07 line.quad 0x00 "GICD_IROUTER972,Interrupt Routing Register 972" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E68++0x07 line.quad 0x00 "GICD_IROUTER973,Interrupt Routing Register 973" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E70++0x07 line.quad 0x00 "GICD_IROUTER974,Interrupt Routing Register 974" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E78++0x07 line.quad 0x00 "GICD_IROUTER975,Interrupt Routing Register 975" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E80++0x07 line.quad 0x00 "GICD_IROUTER976,Interrupt Routing Register 976" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E88++0x07 line.quad 0x00 "GICD_IROUTER977,Interrupt Routing Register 977" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E90++0x07 line.quad 0x00 "GICD_IROUTER978,Interrupt Routing Register 978" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E98++0x07 line.quad 0x00 "GICD_IROUTER979,Interrupt Routing Register 979" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA0++0x07 line.quad 0x00 "GICD_IROUTER980,Interrupt Routing Register 980" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA8++0x07 line.quad 0x00 "GICD_IROUTER981,Interrupt Routing Register 981" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB0++0x07 line.quad 0x00 "GICD_IROUTER982,Interrupt Routing Register 982" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB8++0x07 line.quad 0x00 "GICD_IROUTER983,Interrupt Routing Register 983" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC0++0x07 line.quad 0x00 "GICD_IROUTER984,Interrupt Routing Register 984" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC8++0x07 line.quad 0x00 "GICD_IROUTER985,Interrupt Routing Register 985" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED0++0x07 line.quad 0x00 "GICD_IROUTER986,Interrupt Routing Register 986" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED8++0x07 line.quad 0x00 "GICD_IROUTER987,Interrupt Routing Register 987" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE0++0x07 line.quad 0x00 "GICD_IROUTER988,Interrupt Routing Register 988" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE8++0x07 line.quad 0x00 "GICD_IROUTER989,Interrupt Routing Register 989" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF0++0x07 line.quad 0x00 "GICD_IROUTER990,Interrupt Routing Register 990" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF8++0x07 line.quad 0x00 "GICD_IROUTER991,Interrupt Routing Register 991" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" tree.end width 22. tree "Implementation Defined Test Registers" rgroup.long 0xC000++0x03 line.long 0x00 "GICD_ESTATUSR,GICD_ESTATUSR" bitfld.long 0x00 31. " SRWP ,Super Register Write Pending" "Not pending,Pending" wgroup.long 0xC004++0x03 line.long 0x00 "GICD_ERRTESTR,Error Test Register" bitfld.long 0x00 1. " AXIM_ERR ,Drives the axim_err pin to 0b1 for 1 cycle" "Low,High" bitfld.long 0x00 0. " ECC_FATAL ,Drives the ecc_fatal pin to 0b1 for 1 cycle" "Low,High" textline " " if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) rgroup.long 0xC084++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" bitfld.long 0x00 31. " SPIS63 ,SPI Status Bit 63" "Low,High" bitfld.long 0x00 30. " SPIS62 ,SPI Status Bit 62" "Low,High" bitfld.long 0x00 29. " SPIS61 ,SPI Status Bit 61" "Low,High" textline " " bitfld.long 0x00 28. " SPIS60 ,SPI Status Bit 60" "Low,High" bitfld.long 0x00 27. " SPIS59 ,SPI Status Bit 59" "Low,High" bitfld.long 0x00 26. " SPIS58 ,SPI Status Bit 58" "Low,High" textline " " bitfld.long 0x00 25. " SPIS57 ,SPI Status Bit 57" "Low,High" bitfld.long 0x00 24. " SPIS56 ,SPI Status Bit 56" "Low,High" bitfld.long 0x00 23. " SPIS55 ,SPI Status Bit 55" "Low,High" textline " " bitfld.long 0x00 22. " SPIS54 ,SPI Status Bit 54" "Low,High" bitfld.long 0x00 21. " SPIS53 ,SPI Status Bit 53" "Low,High" bitfld.long 0x00 20. " SPIS52 ,SPI Status Bit 52" "Low,High" textline " " bitfld.long 0x00 19. " SPIS51 ,SPI Status Bit 51" "Low,High" bitfld.long 0x00 18. " SPIS50 ,SPI Status Bit 50" "Low,High" bitfld.long 0x00 17. " SPIS49 ,SPI Status Bit 49" "Low,High" textline " " bitfld.long 0x00 16. " SPIS48 ,SPI Status Bit 48" "Low,High" bitfld.long 0x00 15. " SPIS47 ,SPI Status Bit 47" "Low,High" bitfld.long 0x00 14. " SPIS46 ,SPI Status Bit 46" "Low,High" textline " " bitfld.long 0x00 13. " SPIS45 ,SPI Status Bit 45" "Low,High" bitfld.long 0x00 12. " SPIS44 ,SPI Status Bit 44" "Low,High" bitfld.long 0x00 11. " SPIS43 ,SPI Status Bit 43" "Low,High" textline " " bitfld.long 0x00 10. " SPIS42 ,SPI Status Bit 42" "Low,High" bitfld.long 0x00 9. " SPIS41 ,SPI Status Bit 41" "Low,High" bitfld.long 0x00 8. " SPIS40 ,SPI Status Bit 40" "Low,High" textline " " bitfld.long 0x00 7. " SPIS39 ,SPI Status Bit 39" "Low,High" bitfld.long 0x00 6. " SPIS38 ,SPI Status Bit 38" "Low,High" bitfld.long 0x00 5. " SPIS37 ,SPI Status Bit 37" "Low,High" textline " " bitfld.long 0x00 4. " SPIS36 ,SPI Status Bit 36" "Low,High" bitfld.long 0x00 3. " SPIS35 ,SPI Status Bit 35" "Low,High" bitfld.long 0x00 2. " SPIS34 ,SPI Status Bit 34" "Low,High" textline " " bitfld.long 0x00 1. " SPIS33 ,SPI Status Bit 33" "Low,High" bitfld.long 0x00 0. " SPIS32 ,SPI Status Bit 32" "Low,High" else hgroup.long 0xC084++0x03 hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) rgroup.long 0xC088++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" bitfld.long 0x00 31. " SPIS95 ,SPI Status Bit 95" "Low,High" bitfld.long 0x00 30. " SPIS94 ,SPI Status Bit 94" "Low,High" bitfld.long 0x00 29. " SPIS93 ,SPI Status Bit 93" "Low,High" textline " " bitfld.long 0x00 28. " SPIS92 ,SPI Status Bit 92" "Low,High" bitfld.long 0x00 27. " SPIS91 ,SPI Status Bit 91" "Low,High" bitfld.long 0x00 26. " SPIS90 ,SPI Status Bit 90" "Low,High" textline " " bitfld.long 0x00 25. " SPIS89 ,SPI Status Bit 89" "Low,High" bitfld.long 0x00 24. " SPIS88 ,SPI Status Bit 88" "Low,High" bitfld.long 0x00 23. " SPIS87 ,SPI Status Bit 87" "Low,High" textline " " bitfld.long 0x00 22. " SPIS86 ,SPI Status Bit 86" "Low,High" bitfld.long 0x00 21. " SPIS85 ,SPI Status Bit 85" "Low,High" bitfld.long 0x00 20. " SPIS84 ,SPI Status Bit 84" "Low,High" textline " " bitfld.long 0x00 19. " SPIS83 ,SPI Status Bit 83" "Low,High" bitfld.long 0x00 18. " SPIS82 ,SPI Status Bit 82" "Low,High" bitfld.long 0x00 17. " SPIS81 ,SPI Status Bit 81" "Low,High" textline " " bitfld.long 0x00 16. " SPIS80 ,SPI Status Bit 80" "Low,High" bitfld.long 0x00 15. " SPIS79 ,SPI Status Bit 79" "Low,High" bitfld.long 0x00 14. " SPIS78 ,SPI Status Bit 78" "Low,High" textline " " bitfld.long 0x00 13. " SPIS77 ,SPI Status Bit 77" "Low,High" bitfld.long 0x00 12. " SPIS76 ,SPI Status Bit 76" "Low,High" bitfld.long 0x00 11. " SPIS75 ,SPI Status Bit 75" "Low,High" textline " " bitfld.long 0x00 10. " SPIS74 ,SPI Status Bit 74" "Low,High" bitfld.long 0x00 9. " SPIS73 ,SPI Status Bit 73" "Low,High" bitfld.long 0x00 8. " SPIS72 ,SPI Status Bit 72" "Low,High" textline " " bitfld.long 0x00 7. " SPIS71 ,SPI Status Bit 71" "Low,High" bitfld.long 0x00 6. " SPIS70 ,SPI Status Bit 70" "Low,High" bitfld.long 0x00 5. " SPIS69 ,SPI Status Bit 69" "Low,High" textline " " bitfld.long 0x00 4. " SPIS68 ,SPI Status Bit 68" "Low,High" bitfld.long 0x00 3. " SPIS67 ,SPI Status Bit 67" "Low,High" bitfld.long 0x00 2. " SPIS66 ,SPI Status Bit 66" "Low,High" textline " " bitfld.long 0x00 1. " SPIS65 ,SPI Status Bit 65" "Low,High" bitfld.long 0x00 0. " SPIS64 ,SPI Status Bit 64" "Low,High" else hgroup.long 0xC088++0x03 hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) rgroup.long 0xC08C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" bitfld.long 0x00 31. " SPIS127 ,SPI Status Bit 127" "Low,High" bitfld.long 0x00 30. " SPIS126 ,SPI Status Bit 126" "Low,High" bitfld.long 0x00 29. " SPIS125 ,SPI Status Bit 125" "Low,High" textline " " bitfld.long 0x00 28. " SPIS124 ,SPI Status Bit 124" "Low,High" bitfld.long 0x00 27. " SPIS123 ,SPI Status Bit 123" "Low,High" bitfld.long 0x00 26. " SPIS122 ,SPI Status Bit 122" "Low,High" textline " " bitfld.long 0x00 25. " SPIS121 ,SPI Status Bit 121" "Low,High" bitfld.long 0x00 24. " SPIS120 ,SPI Status Bit 120" "Low,High" bitfld.long 0x00 23. " SPIS119 ,SPI Status Bit 119" "Low,High" textline " " bitfld.long 0x00 22. " SPIS118 ,SPI Status Bit 118" "Low,High" bitfld.long 0x00 21. " SPIS117 ,SPI Status Bit 117" "Low,High" bitfld.long 0x00 20. " SPIS116 ,SPI Status Bit 116" "Low,High" textline " " bitfld.long 0x00 19. " SPIS115 ,SPI Status Bit 115" "Low,High" bitfld.long 0x00 18. " SPIS114 ,SPI Status Bit 114" "Low,High" bitfld.long 0x00 17. " SPIS113 ,SPI Status Bit 113" "Low,High" textline " " bitfld.long 0x00 16. " SPIS112 ,SPI Status Bit 112" "Low,High" bitfld.long 0x00 15. " SPIS111 ,SPI Status Bit 111" "Low,High" bitfld.long 0x00 14. " SPIS110 ,SPI Status Bit 110" "Low,High" textline " " bitfld.long 0x00 13. " SPIS109 ,SPI Status Bit 109" "Low,High" bitfld.long 0x00 12. " SPIS108 ,SPI Status Bit 108" "Low,High" bitfld.long 0x00 11. " SPIS107 ,SPI Status Bit 107" "Low,High" textline " " bitfld.long 0x00 10. " SPIS106 ,SPI Status Bit 106" "Low,High" bitfld.long 0x00 9. " SPIS105 ,SPI Status Bit 105" "Low,High" bitfld.long 0x00 8. " SPIS104 ,SPI Status Bit 104" "Low,High" textline " " bitfld.long 0x00 7. " SPIS103 ,SPI Status Bit 103" "Low,High" bitfld.long 0x00 6. " SPIS102 ,SPI Status Bit 102" "Low,High" bitfld.long 0x00 5. " SPIS101 ,SPI Status Bit 101" "Low,High" textline " " bitfld.long 0x00 4. " SPIS100 ,SPI Status Bit 100" "Low,High" bitfld.long 0x00 3. " SPIS99 ,SPI Status Bit 99" "Low,High" bitfld.long 0x00 2. " SPIS98 ,SPI Status Bit 98" "Low,High" textline " " bitfld.long 0x00 1. " SPIS97 ,SPI Status Bit 97" "Low,High" bitfld.long 0x00 0. " SPIS96 ,SPI Status Bit 96" "Low,High" else hgroup.long 0xC08C++0x03 hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) rgroup.long 0xC090++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" bitfld.long 0x00 31. " SPIS159 ,SPI Status Bit 159" "Low,High" bitfld.long 0x00 30. " SPIS158 ,SPI Status Bit 158" "Low,High" bitfld.long 0x00 29. " SPIS157 ,SPI Status Bit 157" "Low,High" textline " " bitfld.long 0x00 28. " SPIS156 ,SPI Status Bit 156" "Low,High" bitfld.long 0x00 27. " SPIS155 ,SPI Status Bit 155" "Low,High" bitfld.long 0x00 26. " SPIS154 ,SPI Status Bit 154" "Low,High" textline " " bitfld.long 0x00 25. " SPIS153 ,SPI Status Bit 153" "Low,High" bitfld.long 0x00 24. " SPIS152 ,SPI Status Bit 152" "Low,High" bitfld.long 0x00 23. " SPIS151 ,SPI Status Bit 151" "Low,High" textline " " bitfld.long 0x00 22. " SPIS150 ,SPI Status Bit 150" "Low,High" bitfld.long 0x00 21. " SPIS149 ,SPI Status Bit 149" "Low,High" bitfld.long 0x00 20. " SPIS148 ,SPI Status Bit 148" "Low,High" textline " " bitfld.long 0x00 19. " SPIS147 ,SPI Status Bit 147" "Low,High" bitfld.long 0x00 18. " SPIS146 ,SPI Status Bit 146" "Low,High" bitfld.long 0x00 17. " SPIS145 ,SPI Status Bit 145" "Low,High" textline " " bitfld.long 0x00 16. " SPIS144 ,SPI Status Bit 144" "Low,High" bitfld.long 0x00 15. " SPIS143 ,SPI Status Bit 143" "Low,High" bitfld.long 0x00 14. " SPIS142 ,SPI Status Bit 142" "Low,High" textline " " bitfld.long 0x00 13. " SPIS141 ,SPI Status Bit 141" "Low,High" bitfld.long 0x00 12. " SPIS140 ,SPI Status Bit 140" "Low,High" bitfld.long 0x00 11. " SPIS139 ,SPI Status Bit 139" "Low,High" textline " " bitfld.long 0x00 10. " SPIS138 ,SPI Status Bit 138" "Low,High" bitfld.long 0x00 9. " SPIS137 ,SPI Status Bit 137" "Low,High" bitfld.long 0x00 8. " SPIS136 ,SPI Status Bit 136" "Low,High" textline " " bitfld.long 0x00 7. " SPIS135 ,SPI Status Bit 135" "Low,High" bitfld.long 0x00 6. " SPIS134 ,SPI Status Bit 134" "Low,High" bitfld.long 0x00 5. " SPIS133 ,SPI Status Bit 133" "Low,High" textline " " bitfld.long 0x00 4. " SPIS132 ,SPI Status Bit 132" "Low,High" bitfld.long 0x00 3. " SPIS131 ,SPI Status Bit 131" "Low,High" bitfld.long 0x00 2. " SPIS130 ,SPI Status Bit 130" "Low,High" textline " " bitfld.long 0x00 1. " SPIS129 ,SPI Status Bit 129" "Low,High" bitfld.long 0x00 0. " SPIS128 ,SPI Status Bit 128" "Low,High" else hgroup.long 0xC090++0x03 hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) rgroup.long 0xC094++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" bitfld.long 0x00 31. " SPIS191 ,SPI Status Bit 191" "Low,High" bitfld.long 0x00 30. " SPIS190 ,SPI Status Bit 190" "Low,High" bitfld.long 0x00 29. " SPIS189 ,SPI Status Bit 189" "Low,High" textline " " bitfld.long 0x00 28. " SPIS188 ,SPI Status Bit 188" "Low,High" bitfld.long 0x00 27. " SPIS187 ,SPI Status Bit 187" "Low,High" bitfld.long 0x00 26. " SPIS186 ,SPI Status Bit 186" "Low,High" textline " " bitfld.long 0x00 25. " SPIS185 ,SPI Status Bit 185" "Low,High" bitfld.long 0x00 24. " SPIS184 ,SPI Status Bit 184" "Low,High" bitfld.long 0x00 23. " SPIS183 ,SPI Status Bit 183" "Low,High" textline " " bitfld.long 0x00 22. " SPIS182 ,SPI Status Bit 182" "Low,High" bitfld.long 0x00 21. " SPIS181 ,SPI Status Bit 181" "Low,High" bitfld.long 0x00 20. " SPIS180 ,SPI Status Bit 180" "Low,High" textline " " bitfld.long 0x00 19. " SPIS179 ,SPI Status Bit 179" "Low,High" bitfld.long 0x00 18. " SPIS178 ,SPI Status Bit 178" "Low,High" bitfld.long 0x00 17. " SPIS177 ,SPI Status Bit 177" "Low,High" textline " " bitfld.long 0x00 16. " SPIS176 ,SPI Status Bit 176" "Low,High" bitfld.long 0x00 15. " SPIS175 ,SPI Status Bit 175" "Low,High" bitfld.long 0x00 14. " SPIS174 ,SPI Status Bit 174" "Low,High" textline " " bitfld.long 0x00 13. " SPIS173 ,SPI Status Bit 173" "Low,High" bitfld.long 0x00 12. " SPIS172 ,SPI Status Bit 172" "Low,High" bitfld.long 0x00 11. " SPIS171 ,SPI Status Bit 171" "Low,High" textline " " bitfld.long 0x00 10. " SPIS170 ,SPI Status Bit 170" "Low,High" bitfld.long 0x00 9. " SPIS169 ,SPI Status Bit 169" "Low,High" bitfld.long 0x00 8. " SPIS168 ,SPI Status Bit 168" "Low,High" textline " " bitfld.long 0x00 7. " SPIS167 ,SPI Status Bit 167" "Low,High" bitfld.long 0x00 6. " SPIS166 ,SPI Status Bit 166" "Low,High" bitfld.long 0x00 5. " SPIS165 ,SPI Status Bit 165" "Low,High" textline " " bitfld.long 0x00 4. " SPIS164 ,SPI Status Bit 164" "Low,High" bitfld.long 0x00 3. " SPIS163 ,SPI Status Bit 163" "Low,High" bitfld.long 0x00 2. " SPIS162 ,SPI Status Bit 162" "Low,High" textline " " bitfld.long 0x00 1. " SPIS161 ,SPI Status Bit 161" "Low,High" bitfld.long 0x00 0. " SPIS160 ,SPI Status Bit 160" "Low,High" else hgroup.long 0xC094++0x03 hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) rgroup.long 0xC098++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" bitfld.long 0x00 31. " SPIS223 ,SPI Status Bit 223" "Low,High" bitfld.long 0x00 30. " SPIS222 ,SPI Status Bit 222" "Low,High" bitfld.long 0x00 29. " SPIS221 ,SPI Status Bit 221" "Low,High" textline " " bitfld.long 0x00 28. " SPIS220 ,SPI Status Bit 220" "Low,High" bitfld.long 0x00 27. " SPIS219 ,SPI Status Bit 219" "Low,High" bitfld.long 0x00 26. " SPIS218 ,SPI Status Bit 218" "Low,High" textline " " bitfld.long 0x00 25. " SPIS217 ,SPI Status Bit 217" "Low,High" bitfld.long 0x00 24. " SPIS216 ,SPI Status Bit 216" "Low,High" bitfld.long 0x00 23. " SPIS215 ,SPI Status Bit 215" "Low,High" textline " " bitfld.long 0x00 22. " SPIS214 ,SPI Status Bit 214" "Low,High" bitfld.long 0x00 21. " SPIS213 ,SPI Status Bit 213" "Low,High" bitfld.long 0x00 20. " SPIS212 ,SPI Status Bit 212" "Low,High" textline " " bitfld.long 0x00 19. " SPIS211 ,SPI Status Bit 211" "Low,High" bitfld.long 0x00 18. " SPIS210 ,SPI Status Bit 210" "Low,High" bitfld.long 0x00 17. " SPIS209 ,SPI Status Bit 209" "Low,High" textline " " bitfld.long 0x00 16. " SPIS208 ,SPI Status Bit 208" "Low,High" bitfld.long 0x00 15. " SPIS207 ,SPI Status Bit 207" "Low,High" bitfld.long 0x00 14. " SPIS206 ,SPI Status Bit 206" "Low,High" textline " " bitfld.long 0x00 13. " SPIS205 ,SPI Status Bit 205" "Low,High" bitfld.long 0x00 12. " SPIS204 ,SPI Status Bit 204" "Low,High" bitfld.long 0x00 11. " SPIS203 ,SPI Status Bit 203" "Low,High" textline " " bitfld.long 0x00 10. " SPIS202 ,SPI Status Bit 202" "Low,High" bitfld.long 0x00 9. " SPIS201 ,SPI Status Bit 201" "Low,High" bitfld.long 0x00 8. " SPIS200 ,SPI Status Bit 200" "Low,High" textline " " bitfld.long 0x00 7. " SPIS199 ,SPI Status Bit 199" "Low,High" bitfld.long 0x00 6. " SPIS198 ,SPI Status Bit 198" "Low,High" bitfld.long 0x00 5. " SPIS197 ,SPI Status Bit 197" "Low,High" textline " " bitfld.long 0x00 4. " SPIS196 ,SPI Status Bit 196" "Low,High" bitfld.long 0x00 3. " SPIS195 ,SPI Status Bit 195" "Low,High" bitfld.long 0x00 2. " SPIS194 ,SPI Status Bit 194" "Low,High" textline " " bitfld.long 0x00 1. " SPIS193 ,SPI Status Bit 193" "Low,High" bitfld.long 0x00 0. " SPIS192 ,SPI Status Bit 192" "Low,High" else hgroup.long 0xC098++0x03 hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) rgroup.long 0xC09C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" bitfld.long 0x00 31. " SPIS255 ,SPI Status Bit 255" "Low,High" bitfld.long 0x00 30. " SPIS254 ,SPI Status Bit 254" "Low,High" bitfld.long 0x00 29. " SPIS253 ,SPI Status Bit 253" "Low,High" textline " " bitfld.long 0x00 28. " SPIS252 ,SPI Status Bit 252" "Low,High" bitfld.long 0x00 27. " SPIS251 ,SPI Status Bit 251" "Low,High" bitfld.long 0x00 26. " SPIS250 ,SPI Status Bit 250" "Low,High" textline " " bitfld.long 0x00 25. " SPIS249 ,SPI Status Bit 249" "Low,High" bitfld.long 0x00 24. " SPIS248 ,SPI Status Bit 248" "Low,High" bitfld.long 0x00 23. " SPIS247 ,SPI Status Bit 247" "Low,High" textline " " bitfld.long 0x00 22. " SPIS246 ,SPI Status Bit 246" "Low,High" bitfld.long 0x00 21. " SPIS245 ,SPI Status Bit 245" "Low,High" bitfld.long 0x00 20. " SPIS244 ,SPI Status Bit 244" "Low,High" textline " " bitfld.long 0x00 19. " SPIS243 ,SPI Status Bit 243" "Low,High" bitfld.long 0x00 18. " SPIS242 ,SPI Status Bit 242" "Low,High" bitfld.long 0x00 17. " SPIS241 ,SPI Status Bit 241" "Low,High" textline " " bitfld.long 0x00 16. " SPIS240 ,SPI Status Bit 240" "Low,High" bitfld.long 0x00 15. " SPIS239 ,SPI Status Bit 239" "Low,High" bitfld.long 0x00 14. " SPIS238 ,SPI Status Bit 238" "Low,High" textline " " bitfld.long 0x00 13. " SPIS237 ,SPI Status Bit 237" "Low,High" bitfld.long 0x00 12. " SPIS236 ,SPI Status Bit 236" "Low,High" bitfld.long 0x00 11. " SPIS235 ,SPI Status Bit 235" "Low,High" textline " " bitfld.long 0x00 10. " SPIS234 ,SPI Status Bit 234" "Low,High" bitfld.long 0x00 9. " SPIS233 ,SPI Status Bit 233" "Low,High" bitfld.long 0x00 8. " SPIS232 ,SPI Status Bit 232" "Low,High" textline " " bitfld.long 0x00 7. " SPIS231 ,SPI Status Bit 231" "Low,High" bitfld.long 0x00 6. " SPIS230 ,SPI Status Bit 230" "Low,High" bitfld.long 0x00 5. " SPIS229 ,SPI Status Bit 229" "Low,High" textline " " bitfld.long 0x00 4. " SPIS228 ,SPI Status Bit 228" "Low,High" bitfld.long 0x00 3. " SPIS227 ,SPI Status Bit 227" "Low,High" bitfld.long 0x00 2. " SPIS226 ,SPI Status Bit 226" "Low,High" textline " " bitfld.long 0x00 1. " SPIS225 ,SPI Status Bit 225" "Low,High" bitfld.long 0x00 0. " SPIS224 ,SPI Status Bit 224" "Low,High" else hgroup.long 0xC09C++0x03 hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) rgroup.long 0xC0A0++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" bitfld.long 0x00 31. " SPIS287 ,SPI Status Bit 287" "Low,High" bitfld.long 0x00 30. " SPIS286 ,SPI Status Bit 286" "Low,High" bitfld.long 0x00 29. " SPIS285 ,SPI Status Bit 285" "Low,High" textline " " bitfld.long 0x00 28. " SPIS284 ,SPI Status Bit 284" "Low,High" bitfld.long 0x00 27. " SPIS283 ,SPI Status Bit 283" "Low,High" bitfld.long 0x00 26. " SPIS282 ,SPI Status Bit 282" "Low,High" textline " " bitfld.long 0x00 25. " SPIS281 ,SPI Status Bit 281" "Low,High" bitfld.long 0x00 24. " SPIS280 ,SPI Status Bit 280" "Low,High" bitfld.long 0x00 23. " SPIS279 ,SPI Status Bit 279" "Low,High" textline " " bitfld.long 0x00 22. " SPIS278 ,SPI Status Bit 278" "Low,High" bitfld.long 0x00 21. " SPIS277 ,SPI Status Bit 277" "Low,High" bitfld.long 0x00 20. " SPIS276 ,SPI Status Bit 276" "Low,High" textline " " bitfld.long 0x00 19. " SPIS275 ,SPI Status Bit 275" "Low,High" bitfld.long 0x00 18. " SPIS274 ,SPI Status Bit 274" "Low,High" bitfld.long 0x00 17. " SPIS273 ,SPI Status Bit 273" "Low,High" textline " " bitfld.long 0x00 16. " SPIS272 ,SPI Status Bit 272" "Low,High" bitfld.long 0x00 15. " SPIS271 ,SPI Status Bit 271" "Low,High" bitfld.long 0x00 14. " SPIS270 ,SPI Status Bit 270" "Low,High" textline " " bitfld.long 0x00 13. " SPIS269 ,SPI Status Bit 269" "Low,High" bitfld.long 0x00 12. " SPIS268 ,SPI Status Bit 268" "Low,High" bitfld.long 0x00 11. " SPIS267 ,SPI Status Bit 267" "Low,High" textline " " bitfld.long 0x00 10. " SPIS266 ,SPI Status Bit 266" "Low,High" bitfld.long 0x00 9. " SPIS265 ,SPI Status Bit 265" "Low,High" bitfld.long 0x00 8. " SPIS264 ,SPI Status Bit 264" "Low,High" textline " " bitfld.long 0x00 7. " SPIS263 ,SPI Status Bit 263" "Low,High" bitfld.long 0x00 6. " SPIS262 ,SPI Status Bit 262" "Low,High" bitfld.long 0x00 5. " SPIS261 ,SPI Status Bit 261" "Low,High" textline " " bitfld.long 0x00 4. " SPIS260 ,SPI Status Bit 260" "Low,High" bitfld.long 0x00 3. " SPIS259 ,SPI Status Bit 259" "Low,High" bitfld.long 0x00 2. " SPIS258 ,SPI Status Bit 258" "Low,High" textline " " bitfld.long 0x00 1. " SPIS257 ,SPI Status Bit 257" "Low,High" bitfld.long 0x00 0. " SPIS256 ,SPI Status Bit 256" "Low,High" else hgroup.long 0xC0A0++0x03 hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) rgroup.long 0xC0A4++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" bitfld.long 0x00 31. " SPIS319 ,SPI Status Bit 319" "Low,High" bitfld.long 0x00 30. " SPIS318 ,SPI Status Bit 318" "Low,High" bitfld.long 0x00 29. " SPIS317 ,SPI Status Bit 317" "Low,High" textline " " bitfld.long 0x00 28. " SPIS316 ,SPI Status Bit 316" "Low,High" bitfld.long 0x00 27. " SPIS315 ,SPI Status Bit 315" "Low,High" bitfld.long 0x00 26. " SPIS314 ,SPI Status Bit 314" "Low,High" textline " " bitfld.long 0x00 25. " SPIS313 ,SPI Status Bit 313" "Low,High" bitfld.long 0x00 24. " SPIS312 ,SPI Status Bit 312" "Low,High" bitfld.long 0x00 23. " SPIS311 ,SPI Status Bit 311" "Low,High" textline " " bitfld.long 0x00 22. " SPIS310 ,SPI Status Bit 310" "Low,High" bitfld.long 0x00 21. " SPIS309 ,SPI Status Bit 309" "Low,High" bitfld.long 0x00 20. " SPIS308 ,SPI Status Bit 308" "Low,High" textline " " bitfld.long 0x00 19. " SPIS307 ,SPI Status Bit 307" "Low,High" bitfld.long 0x00 18. " SPIS306 ,SPI Status Bit 306" "Low,High" bitfld.long 0x00 17. " SPIS305 ,SPI Status Bit 305" "Low,High" textline " " bitfld.long 0x00 16. " SPIS304 ,SPI Status Bit 304" "Low,High" bitfld.long 0x00 15. " SPIS303 ,SPI Status Bit 303" "Low,High" bitfld.long 0x00 14. " SPIS302 ,SPI Status Bit 302" "Low,High" textline " " bitfld.long 0x00 13. " SPIS301 ,SPI Status Bit 301" "Low,High" bitfld.long 0x00 12. " SPIS300 ,SPI Status Bit 300" "Low,High" bitfld.long 0x00 11. " SPIS299 ,SPI Status Bit 299" "Low,High" textline " " bitfld.long 0x00 10. " SPIS298 ,SPI Status Bit 298" "Low,High" bitfld.long 0x00 9. " SPIS297 ,SPI Status Bit 297" "Low,High" bitfld.long 0x00 8. " SPIS296 ,SPI Status Bit 296" "Low,High" textline " " bitfld.long 0x00 7. " SPIS295 ,SPI Status Bit 295" "Low,High" bitfld.long 0x00 6. " SPIS294 ,SPI Status Bit 294" "Low,High" bitfld.long 0x00 5. " SPIS293 ,SPI Status Bit 293" "Low,High" textline " " bitfld.long 0x00 4. " SPIS292 ,SPI Status Bit 292" "Low,High" bitfld.long 0x00 3. " SPIS291 ,SPI Status Bit 291" "Low,High" bitfld.long 0x00 2. " SPIS290 ,SPI Status Bit 290" "Low,High" textline " " bitfld.long 0x00 1. " SPIS289 ,SPI Status Bit 289" "Low,High" bitfld.long 0x00 0. " SPIS288 ,SPI Status Bit 288" "Low,High" else hgroup.long 0xC0A4++0x03 hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) rgroup.long 0xC0A8++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" bitfld.long 0x00 31. " SPIS351 ,SPI Status Bit 351" "Low,High" bitfld.long 0x00 30. " SPIS350 ,SPI Status Bit 350" "Low,High" bitfld.long 0x00 29. " SPIS349 ,SPI Status Bit 349" "Low,High" textline " " bitfld.long 0x00 28. " SPIS348 ,SPI Status Bit 348" "Low,High" bitfld.long 0x00 27. " SPIS347 ,SPI Status Bit 347" "Low,High" bitfld.long 0x00 26. " SPIS346 ,SPI Status Bit 346" "Low,High" textline " " bitfld.long 0x00 25. " SPIS345 ,SPI Status Bit 345" "Low,High" bitfld.long 0x00 24. " SPIS344 ,SPI Status Bit 344" "Low,High" bitfld.long 0x00 23. " SPIS343 ,SPI Status Bit 343" "Low,High" textline " " bitfld.long 0x00 22. " SPIS342 ,SPI Status Bit 342" "Low,High" bitfld.long 0x00 21. " SPIS341 ,SPI Status Bit 341" "Low,High" bitfld.long 0x00 20. " SPIS340 ,SPI Status Bit 340" "Low,High" textline " " bitfld.long 0x00 19. " SPIS339 ,SPI Status Bit 339" "Low,High" bitfld.long 0x00 18. " SPIS338 ,SPI Status Bit 338" "Low,High" bitfld.long 0x00 17. " SPIS337 ,SPI Status Bit 337" "Low,High" textline " " bitfld.long 0x00 16. " SPIS336 ,SPI Status Bit 336" "Low,High" bitfld.long 0x00 15. " SPIS335 ,SPI Status Bit 335" "Low,High" bitfld.long 0x00 14. " SPIS334 ,SPI Status Bit 334" "Low,High" textline " " bitfld.long 0x00 13. " SPIS333 ,SPI Status Bit 333" "Low,High" bitfld.long 0x00 12. " SPIS332 ,SPI Status Bit 332" "Low,High" bitfld.long 0x00 11. " SPIS331 ,SPI Status Bit 331" "Low,High" textline " " bitfld.long 0x00 10. " SPIS330 ,SPI Status Bit 330" "Low,High" bitfld.long 0x00 9. " SPIS329 ,SPI Status Bit 329" "Low,High" bitfld.long 0x00 8. " SPIS328 ,SPI Status Bit 328" "Low,High" textline " " bitfld.long 0x00 7. " SPIS327 ,SPI Status Bit 327" "Low,High" bitfld.long 0x00 6. " SPIS326 ,SPI Status Bit 326" "Low,High" bitfld.long 0x00 5. " SPIS325 ,SPI Status Bit 325" "Low,High" textline " " bitfld.long 0x00 4. " SPIS324 ,SPI Status Bit 324" "Low,High" bitfld.long 0x00 3. " SPIS323 ,SPI Status Bit 323" "Low,High" bitfld.long 0x00 2. " SPIS322 ,SPI Status Bit 322" "Low,High" textline " " bitfld.long 0x00 1. " SPIS321 ,SPI Status Bit 321" "Low,High" bitfld.long 0x00 0. " SPIS320 ,SPI Status Bit 320" "Low,High" else hgroup.long 0xC0A8++0x03 hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) rgroup.long 0xC0AC++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" bitfld.long 0x00 31. " SPIS383 ,SPI Status Bit 383" "Low,High" bitfld.long 0x00 30. " SPIS382 ,SPI Status Bit 382" "Low,High" bitfld.long 0x00 29. " SPIS381 ,SPI Status Bit 381" "Low,High" textline " " bitfld.long 0x00 28. " SPIS380 ,SPI Status Bit 380" "Low,High" bitfld.long 0x00 27. " SPIS379 ,SPI Status Bit 379" "Low,High" bitfld.long 0x00 26. " SPIS378 ,SPI Status Bit 378" "Low,High" textline " " bitfld.long 0x00 25. " SPIS377 ,SPI Status Bit 377" "Low,High" bitfld.long 0x00 24. " SPIS376 ,SPI Status Bit 376" "Low,High" bitfld.long 0x00 23. " SPIS375 ,SPI Status Bit 375" "Low,High" textline " " bitfld.long 0x00 22. " SPIS374 ,SPI Status Bit 374" "Low,High" bitfld.long 0x00 21. " SPIS373 ,SPI Status Bit 373" "Low,High" bitfld.long 0x00 20. " SPIS372 ,SPI Status Bit 372" "Low,High" textline " " bitfld.long 0x00 19. " SPIS371 ,SPI Status Bit 371" "Low,High" bitfld.long 0x00 18. " SPIS370 ,SPI Status Bit 370" "Low,High" bitfld.long 0x00 17. " SPIS369 ,SPI Status Bit 369" "Low,High" textline " " bitfld.long 0x00 16. " SPIS368 ,SPI Status Bit 368" "Low,High" bitfld.long 0x00 15. " SPIS367 ,SPI Status Bit 367" "Low,High" bitfld.long 0x00 14. " SPIS366 ,SPI Status Bit 366" "Low,High" textline " " bitfld.long 0x00 13. " SPIS365 ,SPI Status Bit 365" "Low,High" bitfld.long 0x00 12. " SPIS364 ,SPI Status Bit 364" "Low,High" bitfld.long 0x00 11. " SPIS363 ,SPI Status Bit 363" "Low,High" textline " " bitfld.long 0x00 10. " SPIS362 ,SPI Status Bit 362" "Low,High" bitfld.long 0x00 9. " SPIS361 ,SPI Status Bit 361" "Low,High" bitfld.long 0x00 8. " SPIS360 ,SPI Status Bit 360" "Low,High" textline " " bitfld.long 0x00 7. " SPIS359 ,SPI Status Bit 359" "Low,High" bitfld.long 0x00 6. " SPIS358 ,SPI Status Bit 358" "Low,High" bitfld.long 0x00 5. " SPIS357 ,SPI Status Bit 357" "Low,High" textline " " bitfld.long 0x00 4. " SPIS356 ,SPI Status Bit 356" "Low,High" bitfld.long 0x00 3. " SPIS355 ,SPI Status Bit 355" "Low,High" bitfld.long 0x00 2. " SPIS354 ,SPI Status Bit 354" "Low,High" textline " " bitfld.long 0x00 1. " SPIS353 ,SPI Status Bit 353" "Low,High" bitfld.long 0x00 0. " SPIS352 ,SPI Status Bit 352" "Low,High" else hgroup.long 0xC0AC++0x03 hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) rgroup.long 0xC0B0++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" bitfld.long 0x00 31. " SPIS415 ,SPI Status Bit 415" "Low,High" bitfld.long 0x00 30. " SPIS414 ,SPI Status Bit 414" "Low,High" bitfld.long 0x00 29. " SPIS413 ,SPI Status Bit 413" "Low,High" textline " " bitfld.long 0x00 28. " SPIS412 ,SPI Status Bit 412" "Low,High" bitfld.long 0x00 27. " SPIS411 ,SPI Status Bit 411" "Low,High" bitfld.long 0x00 26. " SPIS410 ,SPI Status Bit 410" "Low,High" textline " " bitfld.long 0x00 25. " SPIS409 ,SPI Status Bit 409" "Low,High" bitfld.long 0x00 24. " SPIS408 ,SPI Status Bit 408" "Low,High" bitfld.long 0x00 23. " SPIS407 ,SPI Status Bit 407" "Low,High" textline " " bitfld.long 0x00 22. " SPIS406 ,SPI Status Bit 406" "Low,High" bitfld.long 0x00 21. " SPIS405 ,SPI Status Bit 405" "Low,High" bitfld.long 0x00 20. " SPIS404 ,SPI Status Bit 404" "Low,High" textline " " bitfld.long 0x00 19. " SPIS403 ,SPI Status Bit 403" "Low,High" bitfld.long 0x00 18. " SPIS402 ,SPI Status Bit 402" "Low,High" bitfld.long 0x00 17. " SPIS401 ,SPI Status Bit 401" "Low,High" textline " " bitfld.long 0x00 16. " SPIS400 ,SPI Status Bit 400" "Low,High" bitfld.long 0x00 15. " SPIS399 ,SPI Status Bit 399" "Low,High" bitfld.long 0x00 14. " SPIS398 ,SPI Status Bit 398" "Low,High" textline " " bitfld.long 0x00 13. " SPIS397 ,SPI Status Bit 397" "Low,High" bitfld.long 0x00 12. " SPIS396 ,SPI Status Bit 396" "Low,High" bitfld.long 0x00 11. " SPIS395 ,SPI Status Bit 395" "Low,High" textline " " bitfld.long 0x00 10. " SPIS394 ,SPI Status Bit 394" "Low,High" bitfld.long 0x00 9. " SPIS393 ,SPI Status Bit 393" "Low,High" bitfld.long 0x00 8. " SPIS392 ,SPI Status Bit 392" "Low,High" textline " " bitfld.long 0x00 7. " SPIS391 ,SPI Status Bit 391" "Low,High" bitfld.long 0x00 6. " SPIS390 ,SPI Status Bit 390" "Low,High" bitfld.long 0x00 5. " SPIS389 ,SPI Status Bit 389" "Low,High" textline " " bitfld.long 0x00 4. " SPIS388 ,SPI Status Bit 388" "Low,High" bitfld.long 0x00 3. " SPIS387 ,SPI Status Bit 387" "Low,High" bitfld.long 0x00 2. " SPIS386 ,SPI Status Bit 386" "Low,High" textline " " bitfld.long 0x00 1. " SPIS385 ,SPI Status Bit 385" "Low,High" bitfld.long 0x00 0. " SPIS384 ,SPI Status Bit 384" "Low,High" else hgroup.long 0xC0B0++0x03 hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) rgroup.long 0xC0B4++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" bitfld.long 0x00 31. " SPIS447 ,SPI Status Bit 447" "Low,High" bitfld.long 0x00 30. " SPIS446 ,SPI Status Bit 446" "Low,High" bitfld.long 0x00 29. " SPIS445 ,SPI Status Bit 445" "Low,High" textline " " bitfld.long 0x00 28. " SPIS444 ,SPI Status Bit 444" "Low,High" bitfld.long 0x00 27. " SPIS443 ,SPI Status Bit 443" "Low,High" bitfld.long 0x00 26. " SPIS442 ,SPI Status Bit 442" "Low,High" textline " " bitfld.long 0x00 25. " SPIS441 ,SPI Status Bit 441" "Low,High" bitfld.long 0x00 24. " SPIS440 ,SPI Status Bit 440" "Low,High" bitfld.long 0x00 23. " SPIS439 ,SPI Status Bit 439" "Low,High" textline " " bitfld.long 0x00 22. " SPIS438 ,SPI Status Bit 438" "Low,High" bitfld.long 0x00 21. " SPIS437 ,SPI Status Bit 437" "Low,High" bitfld.long 0x00 20. " SPIS436 ,SPI Status Bit 436" "Low,High" textline " " bitfld.long 0x00 19. " SPIS435 ,SPI Status Bit 435" "Low,High" bitfld.long 0x00 18. " SPIS434 ,SPI Status Bit 434" "Low,High" bitfld.long 0x00 17. " SPIS433 ,SPI Status Bit 433" "Low,High" textline " " bitfld.long 0x00 16. " SPIS432 ,SPI Status Bit 432" "Low,High" bitfld.long 0x00 15. " SPIS431 ,SPI Status Bit 431" "Low,High" bitfld.long 0x00 14. " SPIS430 ,SPI Status Bit 430" "Low,High" textline " " bitfld.long 0x00 13. " SPIS429 ,SPI Status Bit 429" "Low,High" bitfld.long 0x00 12. " SPIS428 ,SPI Status Bit 428" "Low,High" bitfld.long 0x00 11. " SPIS427 ,SPI Status Bit 427" "Low,High" textline " " bitfld.long 0x00 10. " SPIS426 ,SPI Status Bit 426" "Low,High" bitfld.long 0x00 9. " SPIS425 ,SPI Status Bit 425" "Low,High" bitfld.long 0x00 8. " SPIS424 ,SPI Status Bit 424" "Low,High" textline " " bitfld.long 0x00 7. " SPIS423 ,SPI Status Bit 423" "Low,High" bitfld.long 0x00 6. " SPIS422 ,SPI Status Bit 422" "Low,High" bitfld.long 0x00 5. " SPIS421 ,SPI Status Bit 421" "Low,High" textline " " bitfld.long 0x00 4. " SPIS420 ,SPI Status Bit 420" "Low,High" bitfld.long 0x00 3. " SPIS419 ,SPI Status Bit 419" "Low,High" bitfld.long 0x00 2. " SPIS418 ,SPI Status Bit 418" "Low,High" textline " " bitfld.long 0x00 1. " SPIS417 ,SPI Status Bit 417" "Low,High" bitfld.long 0x00 0. " SPIS416 ,SPI Status Bit 416" "Low,High" else hgroup.long 0xC0B4++0x03 hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) rgroup.long 0xC0B8++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" bitfld.long 0x00 31. " SPIS479 ,SPI Status Bit 479" "Low,High" bitfld.long 0x00 30. " SPIS478 ,SPI Status Bit 478" "Low,High" bitfld.long 0x00 29. " SPIS477 ,SPI Status Bit 477" "Low,High" textline " " bitfld.long 0x00 28. " SPIS476 ,SPI Status Bit 476" "Low,High" bitfld.long 0x00 27. " SPIS475 ,SPI Status Bit 475" "Low,High" bitfld.long 0x00 26. " SPIS474 ,SPI Status Bit 474" "Low,High" textline " " bitfld.long 0x00 25. " SPIS473 ,SPI Status Bit 473" "Low,High" bitfld.long 0x00 24. " SPIS472 ,SPI Status Bit 472" "Low,High" bitfld.long 0x00 23. " SPIS471 ,SPI Status Bit 471" "Low,High" textline " " bitfld.long 0x00 22. " SPIS470 ,SPI Status Bit 470" "Low,High" bitfld.long 0x00 21. " SPIS469 ,SPI Status Bit 469" "Low,High" bitfld.long 0x00 20. " SPIS468 ,SPI Status Bit 468" "Low,High" textline " " bitfld.long 0x00 19. " SPIS467 ,SPI Status Bit 467" "Low,High" bitfld.long 0x00 18. " SPIS466 ,SPI Status Bit 466" "Low,High" bitfld.long 0x00 17. " SPIS465 ,SPI Status Bit 465" "Low,High" textline " " bitfld.long 0x00 16. " SPIS464 ,SPI Status Bit 464" "Low,High" bitfld.long 0x00 15. " SPIS463 ,SPI Status Bit 463" "Low,High" bitfld.long 0x00 14. " SPIS462 ,SPI Status Bit 462" "Low,High" textline " " bitfld.long 0x00 13. " SPIS461 ,SPI Status Bit 461" "Low,High" bitfld.long 0x00 12. " SPIS460 ,SPI Status Bit 460" "Low,High" bitfld.long 0x00 11. " SPIS459 ,SPI Status Bit 459" "Low,High" textline " " bitfld.long 0x00 10. " SPIS458 ,SPI Status Bit 458" "Low,High" bitfld.long 0x00 9. " SPIS457 ,SPI Status Bit 457" "Low,High" bitfld.long 0x00 8. " SPIS456 ,SPI Status Bit 456" "Low,High" textline " " bitfld.long 0x00 7. " SPIS455 ,SPI Status Bit 455" "Low,High" bitfld.long 0x00 6. " SPIS454 ,SPI Status Bit 454" "Low,High" bitfld.long 0x00 5. " SPIS453 ,SPI Status Bit 453" "Low,High" textline " " bitfld.long 0x00 4. " SPIS452 ,SPI Status Bit 452" "Low,High" bitfld.long 0x00 3. " SPIS451 ,SPI Status Bit 451" "Low,High" bitfld.long 0x00 2. " SPIS450 ,SPI Status Bit 450" "Low,High" textline " " bitfld.long 0x00 1. " SPIS449 ,SPI Status Bit 449" "Low,High" bitfld.long 0x00 0. " SPIS448 ,SPI Status Bit 448" "Low,High" else hgroup.long 0xC0B8++0x03 hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) rgroup.long 0xC0BC++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" bitfld.long 0x00 31. " SPIS511 ,SPI Status Bit 511" "Low,High" bitfld.long 0x00 30. " SPIS510 ,SPI Status Bit 510" "Low,High" bitfld.long 0x00 29. " SPIS509 ,SPI Status Bit 509" "Low,High" textline " " bitfld.long 0x00 28. " SPIS508 ,SPI Status Bit 508" "Low,High" bitfld.long 0x00 27. " SPIS507 ,SPI Status Bit 507" "Low,High" bitfld.long 0x00 26. " SPIS506 ,SPI Status Bit 506" "Low,High" textline " " bitfld.long 0x00 25. " SPIS505 ,SPI Status Bit 505" "Low,High" bitfld.long 0x00 24. " SPIS504 ,SPI Status Bit 504" "Low,High" bitfld.long 0x00 23. " SPIS503 ,SPI Status Bit 503" "Low,High" textline " " bitfld.long 0x00 22. " SPIS502 ,SPI Status Bit 502" "Low,High" bitfld.long 0x00 21. " SPIS501 ,SPI Status Bit 501" "Low,High" bitfld.long 0x00 20. " SPIS500 ,SPI Status Bit 500" "Low,High" textline " " bitfld.long 0x00 19. " SPIS499 ,SPI Status Bit 499" "Low,High" bitfld.long 0x00 18. " SPIS498 ,SPI Status Bit 498" "Low,High" bitfld.long 0x00 17. " SPIS497 ,SPI Status Bit 497" "Low,High" textline " " bitfld.long 0x00 16. " SPIS496 ,SPI Status Bit 496" "Low,High" bitfld.long 0x00 15. " SPIS495 ,SPI Status Bit 495" "Low,High" bitfld.long 0x00 14. " SPIS494 ,SPI Status Bit 494" "Low,High" textline " " bitfld.long 0x00 13. " SPIS493 ,SPI Status Bit 493" "Low,High" bitfld.long 0x00 12. " SPIS492 ,SPI Status Bit 492" "Low,High" bitfld.long 0x00 11. " SPIS491 ,SPI Status Bit 491" "Low,High" textline " " bitfld.long 0x00 10. " SPIS490 ,SPI Status Bit 490" "Low,High" bitfld.long 0x00 9. " SPIS489 ,SPI Status Bit 489" "Low,High" bitfld.long 0x00 8. " SPIS488 ,SPI Status Bit 488" "Low,High" textline " " bitfld.long 0x00 7. " SPIS487 ,SPI Status Bit 487" "Low,High" bitfld.long 0x00 6. " SPIS486 ,SPI Status Bit 486" "Low,High" bitfld.long 0x00 5. " SPIS485 ,SPI Status Bit 485" "Low,High" textline " " bitfld.long 0x00 4. " SPIS484 ,SPI Status Bit 484" "Low,High" bitfld.long 0x00 3. " SPIS483 ,SPI Status Bit 483" "Low,High" bitfld.long 0x00 2. " SPIS482 ,SPI Status Bit 482" "Low,High" textline " " bitfld.long 0x00 1. " SPIS481 ,SPI Status Bit 481" "Low,High" bitfld.long 0x00 0. " SPIS480 ,SPI Status Bit 480" "Low,High" else hgroup.long 0xC0BC++0x03 hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) rgroup.long 0xC0C0++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" bitfld.long 0x00 31. " SPIS543 ,SPI Status Bit 543" "Low,High" bitfld.long 0x00 30. " SPIS542 ,SPI Status Bit 542" "Low,High" bitfld.long 0x00 29. " SPIS541 ,SPI Status Bit 541" "Low,High" textline " " bitfld.long 0x00 28. " SPIS540 ,SPI Status Bit 540" "Low,High" bitfld.long 0x00 27. " SPIS539 ,SPI Status Bit 539" "Low,High" bitfld.long 0x00 26. " SPIS538 ,SPI Status Bit 538" "Low,High" textline " " bitfld.long 0x00 25. " SPIS537 ,SPI Status Bit 537" "Low,High" bitfld.long 0x00 24. " SPIS536 ,SPI Status Bit 536" "Low,High" bitfld.long 0x00 23. " SPIS535 ,SPI Status Bit 535" "Low,High" textline " " bitfld.long 0x00 22. " SPIS534 ,SPI Status Bit 534" "Low,High" bitfld.long 0x00 21. " SPIS533 ,SPI Status Bit 533" "Low,High" bitfld.long 0x00 20. " SPIS532 ,SPI Status Bit 532" "Low,High" textline " " bitfld.long 0x00 19. " SPIS531 ,SPI Status Bit 531" "Low,High" bitfld.long 0x00 18. " SPIS530 ,SPI Status Bit 530" "Low,High" bitfld.long 0x00 17. " SPIS529 ,SPI Status Bit 529" "Low,High" textline " " bitfld.long 0x00 16. " SPIS528 ,SPI Status Bit 528" "Low,High" bitfld.long 0x00 15. " SPIS527 ,SPI Status Bit 527" "Low,High" bitfld.long 0x00 14. " SPIS526 ,SPI Status Bit 526" "Low,High" textline " " bitfld.long 0x00 13. " SPIS525 ,SPI Status Bit 525" "Low,High" bitfld.long 0x00 12. " SPIS524 ,SPI Status Bit 524" "Low,High" bitfld.long 0x00 11. " SPIS523 ,SPI Status Bit 523" "Low,High" textline " " bitfld.long 0x00 10. " SPIS522 ,SPI Status Bit 522" "Low,High" bitfld.long 0x00 9. " SPIS521 ,SPI Status Bit 521" "Low,High" bitfld.long 0x00 8. " SPIS520 ,SPI Status Bit 520" "Low,High" textline " " bitfld.long 0x00 7. " SPIS519 ,SPI Status Bit 519" "Low,High" bitfld.long 0x00 6. " SPIS518 ,SPI Status Bit 518" "Low,High" bitfld.long 0x00 5. " SPIS517 ,SPI Status Bit 517" "Low,High" textline " " bitfld.long 0x00 4. " SPIS516 ,SPI Status Bit 516" "Low,High" bitfld.long 0x00 3. " SPIS515 ,SPI Status Bit 515" "Low,High" bitfld.long 0x00 2. " SPIS514 ,SPI Status Bit 514" "Low,High" textline " " bitfld.long 0x00 1. " SPIS513 ,SPI Status Bit 513" "Low,High" bitfld.long 0x00 0. " SPIS512 ,SPI Status Bit 512" "Low,High" else hgroup.long 0xC0C0++0x03 hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) rgroup.long 0xC0C4++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" bitfld.long 0x00 31. " SPIS575 ,SPI Status Bit 575" "Low,High" bitfld.long 0x00 30. " SPIS574 ,SPI Status Bit 574" "Low,High" bitfld.long 0x00 29. " SPIS573 ,SPI Status Bit 573" "Low,High" textline " " bitfld.long 0x00 28. " SPIS572 ,SPI Status Bit 572" "Low,High" bitfld.long 0x00 27. " SPIS571 ,SPI Status Bit 571" "Low,High" bitfld.long 0x00 26. " SPIS570 ,SPI Status Bit 570" "Low,High" textline " " bitfld.long 0x00 25. " SPIS569 ,SPI Status Bit 569" "Low,High" bitfld.long 0x00 24. " SPIS568 ,SPI Status Bit 568" "Low,High" bitfld.long 0x00 23. " SPIS567 ,SPI Status Bit 567" "Low,High" textline " " bitfld.long 0x00 22. " SPIS566 ,SPI Status Bit 566" "Low,High" bitfld.long 0x00 21. " SPIS565 ,SPI Status Bit 565" "Low,High" bitfld.long 0x00 20. " SPIS564 ,SPI Status Bit 564" "Low,High" textline " " bitfld.long 0x00 19. " SPIS563 ,SPI Status Bit 563" "Low,High" bitfld.long 0x00 18. " SPIS562 ,SPI Status Bit 562" "Low,High" bitfld.long 0x00 17. " SPIS561 ,SPI Status Bit 561" "Low,High" textline " " bitfld.long 0x00 16. " SPIS560 ,SPI Status Bit 560" "Low,High" bitfld.long 0x00 15. " SPIS559 ,SPI Status Bit 559" "Low,High" bitfld.long 0x00 14. " SPIS558 ,SPI Status Bit 558" "Low,High" textline " " bitfld.long 0x00 13. " SPIS557 ,SPI Status Bit 557" "Low,High" bitfld.long 0x00 12. " SPIS556 ,SPI Status Bit 556" "Low,High" bitfld.long 0x00 11. " SPIS555 ,SPI Status Bit 555" "Low,High" textline " " bitfld.long 0x00 10. " SPIS554 ,SPI Status Bit 554" "Low,High" bitfld.long 0x00 9. " SPIS553 ,SPI Status Bit 553" "Low,High" bitfld.long 0x00 8. " SPIS552 ,SPI Status Bit 552" "Low,High" textline " " bitfld.long 0x00 7. " SPIS551 ,SPI Status Bit 551" "Low,High" bitfld.long 0x00 6. " SPIS550 ,SPI Status Bit 550" "Low,High" bitfld.long 0x00 5. " SPIS549 ,SPI Status Bit 549" "Low,High" textline " " bitfld.long 0x00 4. " SPIS548 ,SPI Status Bit 548" "Low,High" bitfld.long 0x00 3. " SPIS547 ,SPI Status Bit 547" "Low,High" bitfld.long 0x00 2. " SPIS546 ,SPI Status Bit 546" "Low,High" textline " " bitfld.long 0x00 1. " SPIS545 ,SPI Status Bit 545" "Low,High" bitfld.long 0x00 0. " SPIS544 ,SPI Status Bit 544" "Low,High" else hgroup.long 0xC0C4++0x03 hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) rgroup.long 0xC0C8++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" bitfld.long 0x00 31. " SPIS607 ,SPI Status Bit 607" "Low,High" bitfld.long 0x00 30. " SPIS606 ,SPI Status Bit 606" "Low,High" bitfld.long 0x00 29. " SPIS605 ,SPI Status Bit 605" "Low,High" textline " " bitfld.long 0x00 28. " SPIS604 ,SPI Status Bit 604" "Low,High" bitfld.long 0x00 27. " SPIS603 ,SPI Status Bit 603" "Low,High" bitfld.long 0x00 26. " SPIS602 ,SPI Status Bit 602" "Low,High" textline " " bitfld.long 0x00 25. " SPIS601 ,SPI Status Bit 601" "Low,High" bitfld.long 0x00 24. " SPIS600 ,SPI Status Bit 600" "Low,High" bitfld.long 0x00 23. " SPIS599 ,SPI Status Bit 599" "Low,High" textline " " bitfld.long 0x00 22. " SPIS598 ,SPI Status Bit 598" "Low,High" bitfld.long 0x00 21. " SPIS597 ,SPI Status Bit 597" "Low,High" bitfld.long 0x00 20. " SPIS596 ,SPI Status Bit 596" "Low,High" textline " " bitfld.long 0x00 19. " SPIS595 ,SPI Status Bit 595" "Low,High" bitfld.long 0x00 18. " SPIS594 ,SPI Status Bit 594" "Low,High" bitfld.long 0x00 17. " SPIS593 ,SPI Status Bit 593" "Low,High" textline " " bitfld.long 0x00 16. " SPIS592 ,SPI Status Bit 592" "Low,High" bitfld.long 0x00 15. " SPIS591 ,SPI Status Bit 591" "Low,High" bitfld.long 0x00 14. " SPIS590 ,SPI Status Bit 590" "Low,High" textline " " bitfld.long 0x00 13. " SPIS589 ,SPI Status Bit 589" "Low,High" bitfld.long 0x00 12. " SPIS588 ,SPI Status Bit 588" "Low,High" bitfld.long 0x00 11. " SPIS587 ,SPI Status Bit 587" "Low,High" textline " " bitfld.long 0x00 10. " SPIS586 ,SPI Status Bit 586" "Low,High" bitfld.long 0x00 9. " SPIS585 ,SPI Status Bit 585" "Low,High" bitfld.long 0x00 8. " SPIS584 ,SPI Status Bit 584" "Low,High" textline " " bitfld.long 0x00 7. " SPIS583 ,SPI Status Bit 583" "Low,High" bitfld.long 0x00 6. " SPIS582 ,SPI Status Bit 582" "Low,High" bitfld.long 0x00 5. " SPIS581 ,SPI Status Bit 581" "Low,High" textline " " bitfld.long 0x00 4. " SPIS580 ,SPI Status Bit 580" "Low,High" bitfld.long 0x00 3. " SPIS579 ,SPI Status Bit 579" "Low,High" bitfld.long 0x00 2. " SPIS578 ,SPI Status Bit 578" "Low,High" textline " " bitfld.long 0x00 1. " SPIS577 ,SPI Status Bit 577" "Low,High" bitfld.long 0x00 0. " SPIS576 ,SPI Status Bit 576" "Low,High" else hgroup.long 0xC0C8++0x03 hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) rgroup.long 0xC0CC++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" bitfld.long 0x00 31. " SPIS639 ,SPI Status Bit 639" "Low,High" bitfld.long 0x00 30. " SPIS638 ,SPI Status Bit 638" "Low,High" bitfld.long 0x00 29. " SPIS637 ,SPI Status Bit 637" "Low,High" textline " " bitfld.long 0x00 28. " SPIS636 ,SPI Status Bit 636" "Low,High" bitfld.long 0x00 27. " SPIS635 ,SPI Status Bit 635" "Low,High" bitfld.long 0x00 26. " SPIS634 ,SPI Status Bit 634" "Low,High" textline " " bitfld.long 0x00 25. " SPIS633 ,SPI Status Bit 633" "Low,High" bitfld.long 0x00 24. " SPIS632 ,SPI Status Bit 632" "Low,High" bitfld.long 0x00 23. " SPIS631 ,SPI Status Bit 631" "Low,High" textline " " bitfld.long 0x00 22. " SPIS630 ,SPI Status Bit 630" "Low,High" bitfld.long 0x00 21. " SPIS629 ,SPI Status Bit 629" "Low,High" bitfld.long 0x00 20. " SPIS628 ,SPI Status Bit 628" "Low,High" textline " " bitfld.long 0x00 19. " SPIS627 ,SPI Status Bit 627" "Low,High" bitfld.long 0x00 18. " SPIS626 ,SPI Status Bit 626" "Low,High" bitfld.long 0x00 17. " SPIS625 ,SPI Status Bit 625" "Low,High" textline " " bitfld.long 0x00 16. " SPIS624 ,SPI Status Bit 624" "Low,High" bitfld.long 0x00 15. " SPIS623 ,SPI Status Bit 623" "Low,High" bitfld.long 0x00 14. " SPIS622 ,SPI Status Bit 622" "Low,High" textline " " bitfld.long 0x00 13. " SPIS621 ,SPI Status Bit 621" "Low,High" bitfld.long 0x00 12. " SPIS620 ,SPI Status Bit 620" "Low,High" bitfld.long 0x00 11. " SPIS619 ,SPI Status Bit 619" "Low,High" textline " " bitfld.long 0x00 10. " SPIS618 ,SPI Status Bit 618" "Low,High" bitfld.long 0x00 9. " SPIS617 ,SPI Status Bit 617" "Low,High" bitfld.long 0x00 8. " SPIS616 ,SPI Status Bit 616" "Low,High" textline " " bitfld.long 0x00 7. " SPIS615 ,SPI Status Bit 615" "Low,High" bitfld.long 0x00 6. " SPIS614 ,SPI Status Bit 614" "Low,High" bitfld.long 0x00 5. " SPIS613 ,SPI Status Bit 613" "Low,High" textline " " bitfld.long 0x00 4. " SPIS612 ,SPI Status Bit 612" "Low,High" bitfld.long 0x00 3. " SPIS611 ,SPI Status Bit 611" "Low,High" bitfld.long 0x00 2. " SPIS610 ,SPI Status Bit 610" "Low,High" textline " " bitfld.long 0x00 1. " SPIS609 ,SPI Status Bit 609" "Low,High" bitfld.long 0x00 0. " SPIS608 ,SPI Status Bit 608" "Low,High" else hgroup.long 0xC0CC++0x03 hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) rgroup.long 0xC0D0++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" bitfld.long 0x00 31. " SPIS671 ,SPI Status Bit 671" "Low,High" bitfld.long 0x00 30. " SPIS670 ,SPI Status Bit 670" "Low,High" bitfld.long 0x00 29. " SPIS669 ,SPI Status Bit 669" "Low,High" textline " " bitfld.long 0x00 28. " SPIS668 ,SPI Status Bit 668" "Low,High" bitfld.long 0x00 27. " SPIS667 ,SPI Status Bit 667" "Low,High" bitfld.long 0x00 26. " SPIS666 ,SPI Status Bit 666" "Low,High" textline " " bitfld.long 0x00 25. " SPIS665 ,SPI Status Bit 665" "Low,High" bitfld.long 0x00 24. " SPIS664 ,SPI Status Bit 664" "Low,High" bitfld.long 0x00 23. " SPIS663 ,SPI Status Bit 663" "Low,High" textline " " bitfld.long 0x00 22. " SPIS662 ,SPI Status Bit 662" "Low,High" bitfld.long 0x00 21. " SPIS661 ,SPI Status Bit 661" "Low,High" bitfld.long 0x00 20. " SPIS660 ,SPI Status Bit 660" "Low,High" textline " " bitfld.long 0x00 19. " SPIS659 ,SPI Status Bit 659" "Low,High" bitfld.long 0x00 18. " SPIS658 ,SPI Status Bit 658" "Low,High" bitfld.long 0x00 17. " SPIS657 ,SPI Status Bit 657" "Low,High" textline " " bitfld.long 0x00 16. " SPIS656 ,SPI Status Bit 656" "Low,High" bitfld.long 0x00 15. " SPIS655 ,SPI Status Bit 655" "Low,High" bitfld.long 0x00 14. " SPIS654 ,SPI Status Bit 654" "Low,High" textline " " bitfld.long 0x00 13. " SPIS653 ,SPI Status Bit 653" "Low,High" bitfld.long 0x00 12. " SPIS652 ,SPI Status Bit 652" "Low,High" bitfld.long 0x00 11. " SPIS651 ,SPI Status Bit 651" "Low,High" textline " " bitfld.long 0x00 10. " SPIS650 ,SPI Status Bit 650" "Low,High" bitfld.long 0x00 9. " SPIS649 ,SPI Status Bit 649" "Low,High" bitfld.long 0x00 8. " SPIS648 ,SPI Status Bit 648" "Low,High" textline " " bitfld.long 0x00 7. " SPIS647 ,SPI Status Bit 647" "Low,High" bitfld.long 0x00 6. " SPIS646 ,SPI Status Bit 646" "Low,High" bitfld.long 0x00 5. " SPIS645 ,SPI Status Bit 645" "Low,High" textline " " bitfld.long 0x00 4. " SPIS644 ,SPI Status Bit 644" "Low,High" bitfld.long 0x00 3. " SPIS643 ,SPI Status Bit 643" "Low,High" bitfld.long 0x00 2. " SPIS642 ,SPI Status Bit 642" "Low,High" textline " " bitfld.long 0x00 1. " SPIS641 ,SPI Status Bit 641" "Low,High" bitfld.long 0x00 0. " SPIS640 ,SPI Status Bit 640" "Low,High" else hgroup.long 0xC0D0++0x03 hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) rgroup.long 0xC0D4++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" bitfld.long 0x00 31. " SPIS703 ,SPI Status Bit 703" "Low,High" bitfld.long 0x00 30. " SPIS702 ,SPI Status Bit 702" "Low,High" bitfld.long 0x00 29. " SPIS701 ,SPI Status Bit 701" "Low,High" textline " " bitfld.long 0x00 28. " SPIS700 ,SPI Status Bit 700" "Low,High" bitfld.long 0x00 27. " SPIS699 ,SPI Status Bit 699" "Low,High" bitfld.long 0x00 26. " SPIS698 ,SPI Status Bit 698" "Low,High" textline " " bitfld.long 0x00 25. " SPIS697 ,SPI Status Bit 697" "Low,High" bitfld.long 0x00 24. " SPIS696 ,SPI Status Bit 696" "Low,High" bitfld.long 0x00 23. " SPIS695 ,SPI Status Bit 695" "Low,High" textline " " bitfld.long 0x00 22. " SPIS694 ,SPI Status Bit 694" "Low,High" bitfld.long 0x00 21. " SPIS693 ,SPI Status Bit 693" "Low,High" bitfld.long 0x00 20. " SPIS692 ,SPI Status Bit 692" "Low,High" textline " " bitfld.long 0x00 19. " SPIS691 ,SPI Status Bit 691" "Low,High" bitfld.long 0x00 18. " SPIS690 ,SPI Status Bit 690" "Low,High" bitfld.long 0x00 17. " SPIS689 ,SPI Status Bit 689" "Low,High" textline " " bitfld.long 0x00 16. " SPIS688 ,SPI Status Bit 688" "Low,High" bitfld.long 0x00 15. " SPIS687 ,SPI Status Bit 687" "Low,High" bitfld.long 0x00 14. " SPIS686 ,SPI Status Bit 686" "Low,High" textline " " bitfld.long 0x00 13. " SPIS685 ,SPI Status Bit 685" "Low,High" bitfld.long 0x00 12. " SPIS684 ,SPI Status Bit 684" "Low,High" bitfld.long 0x00 11. " SPIS683 ,SPI Status Bit 683" "Low,High" textline " " bitfld.long 0x00 10. " SPIS682 ,SPI Status Bit 682" "Low,High" bitfld.long 0x00 9. " SPIS681 ,SPI Status Bit 681" "Low,High" bitfld.long 0x00 8. " SPIS680 ,SPI Status Bit 680" "Low,High" textline " " bitfld.long 0x00 7. " SPIS679 ,SPI Status Bit 679" "Low,High" bitfld.long 0x00 6. " SPIS678 ,SPI Status Bit 678" "Low,High" bitfld.long 0x00 5. " SPIS677 ,SPI Status Bit 677" "Low,High" textline " " bitfld.long 0x00 4. " SPIS676 ,SPI Status Bit 676" "Low,High" bitfld.long 0x00 3. " SPIS675 ,SPI Status Bit 675" "Low,High" bitfld.long 0x00 2. " SPIS674 ,SPI Status Bit 674" "Low,High" textline " " bitfld.long 0x00 1. " SPIS673 ,SPI Status Bit 673" "Low,High" bitfld.long 0x00 0. " SPIS672 ,SPI Status Bit 672" "Low,High" else hgroup.long 0xC0D4++0x03 hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) rgroup.long 0xC0D8++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" bitfld.long 0x00 31. " SPIS735 ,SPI Status Bit 735" "Low,High" bitfld.long 0x00 30. " SPIS734 ,SPI Status Bit 734" "Low,High" bitfld.long 0x00 29. " SPIS733 ,SPI Status Bit 733" "Low,High" textline " " bitfld.long 0x00 28. " SPIS732 ,SPI Status Bit 732" "Low,High" bitfld.long 0x00 27. " SPIS731 ,SPI Status Bit 731" "Low,High" bitfld.long 0x00 26. " SPIS730 ,SPI Status Bit 730" "Low,High" textline " " bitfld.long 0x00 25. " SPIS729 ,SPI Status Bit 729" "Low,High" bitfld.long 0x00 24. " SPIS728 ,SPI Status Bit 728" "Low,High" bitfld.long 0x00 23. " SPIS727 ,SPI Status Bit 727" "Low,High" textline " " bitfld.long 0x00 22. " SPIS726 ,SPI Status Bit 726" "Low,High" bitfld.long 0x00 21. " SPIS725 ,SPI Status Bit 725" "Low,High" bitfld.long 0x00 20. " SPIS724 ,SPI Status Bit 724" "Low,High" textline " " bitfld.long 0x00 19. " SPIS723 ,SPI Status Bit 723" "Low,High" bitfld.long 0x00 18. " SPIS722 ,SPI Status Bit 722" "Low,High" bitfld.long 0x00 17. " SPIS721 ,SPI Status Bit 721" "Low,High" textline " " bitfld.long 0x00 16. " SPIS720 ,SPI Status Bit 720" "Low,High" bitfld.long 0x00 15. " SPIS719 ,SPI Status Bit 719" "Low,High" bitfld.long 0x00 14. " SPIS718 ,SPI Status Bit 718" "Low,High" textline " " bitfld.long 0x00 13. " SPIS717 ,SPI Status Bit 717" "Low,High" bitfld.long 0x00 12. " SPIS716 ,SPI Status Bit 716" "Low,High" bitfld.long 0x00 11. " SPIS715 ,SPI Status Bit 715" "Low,High" textline " " bitfld.long 0x00 10. " SPIS714 ,SPI Status Bit 714" "Low,High" bitfld.long 0x00 9. " SPIS713 ,SPI Status Bit 713" "Low,High" bitfld.long 0x00 8. " SPIS712 ,SPI Status Bit 712" "Low,High" textline " " bitfld.long 0x00 7. " SPIS711 ,SPI Status Bit 711" "Low,High" bitfld.long 0x00 6. " SPIS710 ,SPI Status Bit 710" "Low,High" bitfld.long 0x00 5. " SPIS709 ,SPI Status Bit 709" "Low,High" textline " " bitfld.long 0x00 4. " SPIS708 ,SPI Status Bit 708" "Low,High" bitfld.long 0x00 3. " SPIS707 ,SPI Status Bit 707" "Low,High" bitfld.long 0x00 2. " SPIS706 ,SPI Status Bit 706" "Low,High" textline " " bitfld.long 0x00 1. " SPIS705 ,SPI Status Bit 705" "Low,High" bitfld.long 0x00 0. " SPIS704 ,SPI Status Bit 704" "Low,High" else hgroup.long 0xC0D8++0x03 hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) rgroup.long 0xC0DC++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" bitfld.long 0x00 31. " SPIS767 ,SPI Status Bit 767" "Low,High" bitfld.long 0x00 30. " SPIS766 ,SPI Status Bit 766" "Low,High" bitfld.long 0x00 29. " SPIS765 ,SPI Status Bit 765" "Low,High" textline " " bitfld.long 0x00 28. " SPIS764 ,SPI Status Bit 764" "Low,High" bitfld.long 0x00 27. " SPIS763 ,SPI Status Bit 763" "Low,High" bitfld.long 0x00 26. " SPIS762 ,SPI Status Bit 762" "Low,High" textline " " bitfld.long 0x00 25. " SPIS761 ,SPI Status Bit 761" "Low,High" bitfld.long 0x00 24. " SPIS760 ,SPI Status Bit 760" "Low,High" bitfld.long 0x00 23. " SPIS759 ,SPI Status Bit 759" "Low,High" textline " " bitfld.long 0x00 22. " SPIS758 ,SPI Status Bit 758" "Low,High" bitfld.long 0x00 21. " SPIS757 ,SPI Status Bit 757" "Low,High" bitfld.long 0x00 20. " SPIS756 ,SPI Status Bit 756" "Low,High" textline " " bitfld.long 0x00 19. " SPIS755 ,SPI Status Bit 755" "Low,High" bitfld.long 0x00 18. " SPIS754 ,SPI Status Bit 754" "Low,High" bitfld.long 0x00 17. " SPIS753 ,SPI Status Bit 753" "Low,High" textline " " bitfld.long 0x00 16. " SPIS752 ,SPI Status Bit 752" "Low,High" bitfld.long 0x00 15. " SPIS751 ,SPI Status Bit 751" "Low,High" bitfld.long 0x00 14. " SPIS750 ,SPI Status Bit 750" "Low,High" textline " " bitfld.long 0x00 13. " SPIS749 ,SPI Status Bit 749" "Low,High" bitfld.long 0x00 12. " SPIS748 ,SPI Status Bit 748" "Low,High" bitfld.long 0x00 11. " SPIS747 ,SPI Status Bit 747" "Low,High" textline " " bitfld.long 0x00 10. " SPIS746 ,SPI Status Bit 746" "Low,High" bitfld.long 0x00 9. " SPIS745 ,SPI Status Bit 745" "Low,High" bitfld.long 0x00 8. " SPIS744 ,SPI Status Bit 744" "Low,High" textline " " bitfld.long 0x00 7. " SPIS743 ,SPI Status Bit 743" "Low,High" bitfld.long 0x00 6. " SPIS742 ,SPI Status Bit 742" "Low,High" bitfld.long 0x00 5. " SPIS741 ,SPI Status Bit 741" "Low,High" textline " " bitfld.long 0x00 4. " SPIS740 ,SPI Status Bit 740" "Low,High" bitfld.long 0x00 3. " SPIS739 ,SPI Status Bit 739" "Low,High" bitfld.long 0x00 2. " SPIS738 ,SPI Status Bit 738" "Low,High" textline " " bitfld.long 0x00 1. " SPIS737 ,SPI Status Bit 737" "Low,High" bitfld.long 0x00 0. " SPIS736 ,SPI Status Bit 736" "Low,High" else hgroup.long 0xC0DC++0x03 hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) rgroup.long 0xC0E0++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" bitfld.long 0x00 31. " SPIS799 ,SPI Status Bit 799" "Low,High" bitfld.long 0x00 30. " SPIS798 ,SPI Status Bit 798" "Low,High" bitfld.long 0x00 29. " SPIS797 ,SPI Status Bit 797" "Low,High" textline " " bitfld.long 0x00 28. " SPIS796 ,SPI Status Bit 796" "Low,High" bitfld.long 0x00 27. " SPIS795 ,SPI Status Bit 795" "Low,High" bitfld.long 0x00 26. " SPIS794 ,SPI Status Bit 794" "Low,High" textline " " bitfld.long 0x00 25. " SPIS793 ,SPI Status Bit 793" "Low,High" bitfld.long 0x00 24. " SPIS792 ,SPI Status Bit 792" "Low,High" bitfld.long 0x00 23. " SPIS791 ,SPI Status Bit 791" "Low,High" textline " " bitfld.long 0x00 22. " SPIS790 ,SPI Status Bit 790" "Low,High" bitfld.long 0x00 21. " SPIS789 ,SPI Status Bit 789" "Low,High" bitfld.long 0x00 20. " SPIS788 ,SPI Status Bit 788" "Low,High" textline " " bitfld.long 0x00 19. " SPIS787 ,SPI Status Bit 787" "Low,High" bitfld.long 0x00 18. " SPIS786 ,SPI Status Bit 786" "Low,High" bitfld.long 0x00 17. " SPIS785 ,SPI Status Bit 785" "Low,High" textline " " bitfld.long 0x00 16. " SPIS784 ,SPI Status Bit 784" "Low,High" bitfld.long 0x00 15. " SPIS783 ,SPI Status Bit 783" "Low,High" bitfld.long 0x00 14. " SPIS782 ,SPI Status Bit 782" "Low,High" textline " " bitfld.long 0x00 13. " SPIS781 ,SPI Status Bit 781" "Low,High" bitfld.long 0x00 12. " SPIS780 ,SPI Status Bit 780" "Low,High" bitfld.long 0x00 11. " SPIS779 ,SPI Status Bit 779" "Low,High" textline " " bitfld.long 0x00 10. " SPIS778 ,SPI Status Bit 778" "Low,High" bitfld.long 0x00 9. " SPIS777 ,SPI Status Bit 777" "Low,High" bitfld.long 0x00 8. " SPIS776 ,SPI Status Bit 776" "Low,High" textline " " bitfld.long 0x00 7. " SPIS775 ,SPI Status Bit 775" "Low,High" bitfld.long 0x00 6. " SPIS774 ,SPI Status Bit 774" "Low,High" bitfld.long 0x00 5. " SPIS773 ,SPI Status Bit 773" "Low,High" textline " " bitfld.long 0x00 4. " SPIS772 ,SPI Status Bit 772" "Low,High" bitfld.long 0x00 3. " SPIS771 ,SPI Status Bit 771" "Low,High" bitfld.long 0x00 2. " SPIS770 ,SPI Status Bit 770" "Low,High" textline " " bitfld.long 0x00 1. " SPIS769 ,SPI Status Bit 769" "Low,High" bitfld.long 0x00 0. " SPIS768 ,SPI Status Bit 768" "Low,High" else hgroup.long 0xC0E0++0x03 hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) rgroup.long 0xC0E4++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" bitfld.long 0x00 31. " SPIS831 ,SPI Status Bit 831" "Low,High" bitfld.long 0x00 30. " SPIS830 ,SPI Status Bit 830" "Low,High" bitfld.long 0x00 29. " SPIS829 ,SPI Status Bit 829" "Low,High" textline " " bitfld.long 0x00 28. " SPIS828 ,SPI Status Bit 828" "Low,High" bitfld.long 0x00 27. " SPIS827 ,SPI Status Bit 827" "Low,High" bitfld.long 0x00 26. " SPIS826 ,SPI Status Bit 826" "Low,High" textline " " bitfld.long 0x00 25. " SPIS825 ,SPI Status Bit 825" "Low,High" bitfld.long 0x00 24. " SPIS824 ,SPI Status Bit 824" "Low,High" bitfld.long 0x00 23. " SPIS823 ,SPI Status Bit 823" "Low,High" textline " " bitfld.long 0x00 22. " SPIS822 ,SPI Status Bit 822" "Low,High" bitfld.long 0x00 21. " SPIS821 ,SPI Status Bit 821" "Low,High" bitfld.long 0x00 20. " SPIS820 ,SPI Status Bit 820" "Low,High" textline " " bitfld.long 0x00 19. " SPIS819 ,SPI Status Bit 819" "Low,High" bitfld.long 0x00 18. " SPIS818 ,SPI Status Bit 818" "Low,High" bitfld.long 0x00 17. " SPIS817 ,SPI Status Bit 817" "Low,High" textline " " bitfld.long 0x00 16. " SPIS816 ,SPI Status Bit 816" "Low,High" bitfld.long 0x00 15. " SPIS815 ,SPI Status Bit 815" "Low,High" bitfld.long 0x00 14. " SPIS814 ,SPI Status Bit 814" "Low,High" textline " " bitfld.long 0x00 13. " SPIS813 ,SPI Status Bit 813" "Low,High" bitfld.long 0x00 12. " SPIS812 ,SPI Status Bit 812" "Low,High" bitfld.long 0x00 11. " SPIS811 ,SPI Status Bit 811" "Low,High" textline " " bitfld.long 0x00 10. " SPIS810 ,SPI Status Bit 810" "Low,High" bitfld.long 0x00 9. " SPIS809 ,SPI Status Bit 809" "Low,High" bitfld.long 0x00 8. " SPIS808 ,SPI Status Bit 808" "Low,High" textline " " bitfld.long 0x00 7. " SPIS807 ,SPI Status Bit 807" "Low,High" bitfld.long 0x00 6. " SPIS806 ,SPI Status Bit 806" "Low,High" bitfld.long 0x00 5. " SPIS805 ,SPI Status Bit 805" "Low,High" textline " " bitfld.long 0x00 4. " SPIS804 ,SPI Status Bit 804" "Low,High" bitfld.long 0x00 3. " SPIS803 ,SPI Status Bit 803" "Low,High" bitfld.long 0x00 2. " SPIS802 ,SPI Status Bit 802" "Low,High" textline " " bitfld.long 0x00 1. " SPIS801 ,SPI Status Bit 801" "Low,High" bitfld.long 0x00 0. " SPIS800 ,SPI Status Bit 800" "Low,High" else hgroup.long 0xC0E4++0x03 hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) rgroup.long 0xC0E8++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" bitfld.long 0x00 31. " SPIS863 ,SPI Status Bit 863" "Low,High" bitfld.long 0x00 30. " SPIS862 ,SPI Status Bit 862" "Low,High" bitfld.long 0x00 29. " SPIS861 ,SPI Status Bit 861" "Low,High" textline " " bitfld.long 0x00 28. " SPIS860 ,SPI Status Bit 860" "Low,High" bitfld.long 0x00 27. " SPIS859 ,SPI Status Bit 859" "Low,High" bitfld.long 0x00 26. " SPIS858 ,SPI Status Bit 858" "Low,High" textline " " bitfld.long 0x00 25. " SPIS857 ,SPI Status Bit 857" "Low,High" bitfld.long 0x00 24. " SPIS856 ,SPI Status Bit 856" "Low,High" bitfld.long 0x00 23. " SPIS855 ,SPI Status Bit 855" "Low,High" textline " " bitfld.long 0x00 22. " SPIS854 ,SPI Status Bit 854" "Low,High" bitfld.long 0x00 21. " SPIS853 ,SPI Status Bit 853" "Low,High" bitfld.long 0x00 20. " SPIS852 ,SPI Status Bit 852" "Low,High" textline " " bitfld.long 0x00 19. " SPIS851 ,SPI Status Bit 851" "Low,High" bitfld.long 0x00 18. " SPIS850 ,SPI Status Bit 850" "Low,High" bitfld.long 0x00 17. " SPIS849 ,SPI Status Bit 849" "Low,High" textline " " bitfld.long 0x00 16. " SPIS848 ,SPI Status Bit 848" "Low,High" bitfld.long 0x00 15. " SPIS847 ,SPI Status Bit 847" "Low,High" bitfld.long 0x00 14. " SPIS846 ,SPI Status Bit 846" "Low,High" textline " " bitfld.long 0x00 13. " SPIS845 ,SPI Status Bit 845" "Low,High" bitfld.long 0x00 12. " SPIS844 ,SPI Status Bit 844" "Low,High" bitfld.long 0x00 11. " SPIS843 ,SPI Status Bit 843" "Low,High" textline " " bitfld.long 0x00 10. " SPIS842 ,SPI Status Bit 842" "Low,High" bitfld.long 0x00 9. " SPIS841 ,SPI Status Bit 841" "Low,High" bitfld.long 0x00 8. " SPIS840 ,SPI Status Bit 840" "Low,High" textline " " bitfld.long 0x00 7. " SPIS839 ,SPI Status Bit 839" "Low,High" bitfld.long 0x00 6. " SPIS838 ,SPI Status Bit 838" "Low,High" bitfld.long 0x00 5. " SPIS837 ,SPI Status Bit 837" "Low,High" textline " " bitfld.long 0x00 4. " SPIS836 ,SPI Status Bit 836" "Low,High" bitfld.long 0x00 3. " SPIS835 ,SPI Status Bit 835" "Low,High" bitfld.long 0x00 2. " SPIS834 ,SPI Status Bit 834" "Low,High" textline " " bitfld.long 0x00 1. " SPIS833 ,SPI Status Bit 833" "Low,High" bitfld.long 0x00 0. " SPIS832 ,SPI Status Bit 832" "Low,High" else hgroup.long 0xC0E8++0x03 hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) rgroup.long 0xC0EC++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" bitfld.long 0x00 31. " SPIS895 ,SPI Status Bit 895" "Low,High" bitfld.long 0x00 30. " SPIS894 ,SPI Status Bit 894" "Low,High" bitfld.long 0x00 29. " SPIS893 ,SPI Status Bit 893" "Low,High" textline " " bitfld.long 0x00 28. " SPIS892 ,SPI Status Bit 892" "Low,High" bitfld.long 0x00 27. " SPIS891 ,SPI Status Bit 891" "Low,High" bitfld.long 0x00 26. " SPIS890 ,SPI Status Bit 890" "Low,High" textline " " bitfld.long 0x00 25. " SPIS889 ,SPI Status Bit 889" "Low,High" bitfld.long 0x00 24. " SPIS888 ,SPI Status Bit 888" "Low,High" bitfld.long 0x00 23. " SPIS887 ,SPI Status Bit 887" "Low,High" textline " " bitfld.long 0x00 22. " SPIS886 ,SPI Status Bit 886" "Low,High" bitfld.long 0x00 21. " SPIS885 ,SPI Status Bit 885" "Low,High" bitfld.long 0x00 20. " SPIS884 ,SPI Status Bit 884" "Low,High" textline " " bitfld.long 0x00 19. " SPIS883 ,SPI Status Bit 883" "Low,High" bitfld.long 0x00 18. " SPIS882 ,SPI Status Bit 882" "Low,High" bitfld.long 0x00 17. " SPIS881 ,SPI Status Bit 881" "Low,High" textline " " bitfld.long 0x00 16. " SPIS880 ,SPI Status Bit 880" "Low,High" bitfld.long 0x00 15. " SPIS879 ,SPI Status Bit 879" "Low,High" bitfld.long 0x00 14. " SPIS878 ,SPI Status Bit 878" "Low,High" textline " " bitfld.long 0x00 13. " SPIS877 ,SPI Status Bit 877" "Low,High" bitfld.long 0x00 12. " SPIS876 ,SPI Status Bit 876" "Low,High" bitfld.long 0x00 11. " SPIS875 ,SPI Status Bit 875" "Low,High" textline " " bitfld.long 0x00 10. " SPIS874 ,SPI Status Bit 874" "Low,High" bitfld.long 0x00 9. " SPIS873 ,SPI Status Bit 873" "Low,High" bitfld.long 0x00 8. " SPIS872 ,SPI Status Bit 872" "Low,High" textline " " bitfld.long 0x00 7. " SPIS871 ,SPI Status Bit 871" "Low,High" bitfld.long 0x00 6. " SPIS870 ,SPI Status Bit 870" "Low,High" bitfld.long 0x00 5. " SPIS869 ,SPI Status Bit 869" "Low,High" textline " " bitfld.long 0x00 4. " SPIS868 ,SPI Status Bit 868" "Low,High" bitfld.long 0x00 3. " SPIS867 ,SPI Status Bit 867" "Low,High" bitfld.long 0x00 2. " SPIS866 ,SPI Status Bit 866" "Low,High" textline " " bitfld.long 0x00 1. " SPIS865 ,SPI Status Bit 865" "Low,High" bitfld.long 0x00 0. " SPIS864 ,SPI Status Bit 864" "Low,High" else hgroup.long 0xC0EC++0x03 hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) rgroup.long 0xC0F0++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" bitfld.long 0x00 31. " SPIS927 ,SPI Status Bit 927" "Low,High" bitfld.long 0x00 30. " SPIS926 ,SPI Status Bit 926" "Low,High" bitfld.long 0x00 29. " SPIS925 ,SPI Status Bit 925" "Low,High" textline " " bitfld.long 0x00 28. " SPIS924 ,SPI Status Bit 924" "Low,High" bitfld.long 0x00 27. " SPIS923 ,SPI Status Bit 923" "Low,High" bitfld.long 0x00 26. " SPIS922 ,SPI Status Bit 922" "Low,High" textline " " bitfld.long 0x00 25. " SPIS921 ,SPI Status Bit 921" "Low,High" bitfld.long 0x00 24. " SPIS920 ,SPI Status Bit 920" "Low,High" bitfld.long 0x00 23. " SPIS919 ,SPI Status Bit 919" "Low,High" textline " " bitfld.long 0x00 22. " SPIS918 ,SPI Status Bit 918" "Low,High" bitfld.long 0x00 21. " SPIS917 ,SPI Status Bit 917" "Low,High" bitfld.long 0x00 20. " SPIS916 ,SPI Status Bit 916" "Low,High" textline " " bitfld.long 0x00 19. " SPIS915 ,SPI Status Bit 915" "Low,High" bitfld.long 0x00 18. " SPIS914 ,SPI Status Bit 914" "Low,High" bitfld.long 0x00 17. " SPIS913 ,SPI Status Bit 913" "Low,High" textline " " bitfld.long 0x00 16. " SPIS912 ,SPI Status Bit 912" "Low,High" bitfld.long 0x00 15. " SPIS911 ,SPI Status Bit 911" "Low,High" bitfld.long 0x00 14. " SPIS910 ,SPI Status Bit 910" "Low,High" textline " " bitfld.long 0x00 13. " SPIS909 ,SPI Status Bit 909" "Low,High" bitfld.long 0x00 12. " SPIS908 ,SPI Status Bit 908" "Low,High" bitfld.long 0x00 11. " SPIS907 ,SPI Status Bit 907" "Low,High" textline " " bitfld.long 0x00 10. " SPIS906 ,SPI Status Bit 906" "Low,High" bitfld.long 0x00 9. " SPIS905 ,SPI Status Bit 905" "Low,High" bitfld.long 0x00 8. " SPIS904 ,SPI Status Bit 904" "Low,High" textline " " bitfld.long 0x00 7. " SPIS903 ,SPI Status Bit 903" "Low,High" bitfld.long 0x00 6. " SPIS902 ,SPI Status Bit 902" "Low,High" bitfld.long 0x00 5. " SPIS901 ,SPI Status Bit 901" "Low,High" textline " " bitfld.long 0x00 4. " SPIS900 ,SPI Status Bit 900" "Low,High" bitfld.long 0x00 3. " SPIS899 ,SPI Status Bit 899" "Low,High" bitfld.long 0x00 2. " SPIS898 ,SPI Status Bit 898" "Low,High" textline " " bitfld.long 0x00 1. " SPIS897 ,SPI Status Bit 897" "Low,High" bitfld.long 0x00 0. " SPIS896 ,SPI Status Bit 896" "Low,High" else hgroup.long 0xC0F0++0x03 hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) rgroup.long 0xC0F4++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" bitfld.long 0x00 31. " SPIS959 ,SPI Status Bit 959" "Low,High" bitfld.long 0x00 30. " SPIS958 ,SPI Status Bit 958" "Low,High" bitfld.long 0x00 29. " SPIS957 ,SPI Status Bit 957" "Low,High" textline " " bitfld.long 0x00 28. " SPIS956 ,SPI Status Bit 956" "Low,High" bitfld.long 0x00 27. " SPIS955 ,SPI Status Bit 955" "Low,High" bitfld.long 0x00 26. " SPIS954 ,SPI Status Bit 954" "Low,High" textline " " bitfld.long 0x00 25. " SPIS953 ,SPI Status Bit 953" "Low,High" bitfld.long 0x00 24. " SPIS952 ,SPI Status Bit 952" "Low,High" bitfld.long 0x00 23. " SPIS951 ,SPI Status Bit 951" "Low,High" textline " " bitfld.long 0x00 22. " SPIS950 ,SPI Status Bit 950" "Low,High" bitfld.long 0x00 21. " SPIS949 ,SPI Status Bit 949" "Low,High" bitfld.long 0x00 20. " SPIS948 ,SPI Status Bit 948" "Low,High" textline " " bitfld.long 0x00 19. " SPIS947 ,SPI Status Bit 947" "Low,High" bitfld.long 0x00 18. " SPIS946 ,SPI Status Bit 946" "Low,High" bitfld.long 0x00 17. " SPIS945 ,SPI Status Bit 945" "Low,High" textline " " bitfld.long 0x00 16. " SPIS944 ,SPI Status Bit 944" "Low,High" bitfld.long 0x00 15. " SPIS943 ,SPI Status Bit 943" "Low,High" bitfld.long 0x00 14. " SPIS942 ,SPI Status Bit 942" "Low,High" textline " " bitfld.long 0x00 13. " SPIS941 ,SPI Status Bit 941" "Low,High" bitfld.long 0x00 12. " SPIS940 ,SPI Status Bit 940" "Low,High" bitfld.long 0x00 11. " SPIS939 ,SPI Status Bit 939" "Low,High" textline " " bitfld.long 0x00 10. " SPIS938 ,SPI Status Bit 938" "Low,High" bitfld.long 0x00 9. " SPIS937 ,SPI Status Bit 937" "Low,High" bitfld.long 0x00 8. " SPIS936 ,SPI Status Bit 936" "Low,High" textline " " bitfld.long 0x00 7. " SPIS935 ,SPI Status Bit 935" "Low,High" bitfld.long 0x00 6. " SPIS934 ,SPI Status Bit 934" "Low,High" bitfld.long 0x00 5. " SPIS933 ,SPI Status Bit 933" "Low,High" textline " " bitfld.long 0x00 4. " SPIS932 ,SPI Status Bit 932" "Low,High" bitfld.long 0x00 3. " SPIS931 ,SPI Status Bit 931" "Low,High" bitfld.long 0x00 2. " SPIS930 ,SPI Status Bit 930" "Low,High" textline " " bitfld.long 0x00 1. " SPIS929 ,SPI Status Bit 929" "Low,High" bitfld.long 0x00 0. " SPIS928 ,SPI Status Bit 928" "Low,High" else hgroup.long 0xC0F4++0x03 hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) rgroup.long 0xC0F8++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" bitfld.long 0x00 31. " SPIS991 ,SPI Status Bit 991" "Low,High" bitfld.long 0x00 30. " SPIS990 ,SPI Status Bit 990" "Low,High" bitfld.long 0x00 29. " SPIS989 ,SPI Status Bit 989" "Low,High" textline " " bitfld.long 0x00 28. " SPIS988 ,SPI Status Bit 988" "Low,High" bitfld.long 0x00 27. " SPIS987 ,SPI Status Bit 987" "Low,High" bitfld.long 0x00 26. " SPIS986 ,SPI Status Bit 986" "Low,High" textline " " bitfld.long 0x00 25. " SPIS985 ,SPI Status Bit 985" "Low,High" bitfld.long 0x00 24. " SPIS984 ,SPI Status Bit 984" "Low,High" bitfld.long 0x00 23. " SPIS983 ,SPI Status Bit 983" "Low,High" textline " " bitfld.long 0x00 22. " SPIS982 ,SPI Status Bit 982" "Low,High" bitfld.long 0x00 21. " SPIS981 ,SPI Status Bit 981" "Low,High" bitfld.long 0x00 20. " SPIS980 ,SPI Status Bit 980" "Low,High" textline " " bitfld.long 0x00 19. " SPIS979 ,SPI Status Bit 979" "Low,High" bitfld.long 0x00 18. " SPIS978 ,SPI Status Bit 978" "Low,High" bitfld.long 0x00 17. " SPIS977 ,SPI Status Bit 977" "Low,High" textline " " bitfld.long 0x00 16. " SPIS976 ,SPI Status Bit 976" "Low,High" bitfld.long 0x00 15. " SPIS975 ,SPI Status Bit 975" "Low,High" bitfld.long 0x00 14. " SPIS974 ,SPI Status Bit 974" "Low,High" textline " " bitfld.long 0x00 13. " SPIS973 ,SPI Status Bit 973" "Low,High" bitfld.long 0x00 12. " SPIS972 ,SPI Status Bit 972" "Low,High" bitfld.long 0x00 11. " SPIS971 ,SPI Status Bit 971" "Low,High" textline " " bitfld.long 0x00 10. " SPIS970 ,SPI Status Bit 970" "Low,High" bitfld.long 0x00 9. " SPIS969 ,SPI Status Bit 969" "Low,High" bitfld.long 0x00 8. " SPIS968 ,SPI Status Bit 968" "Low,High" textline " " bitfld.long 0x00 7. " SPIS967 ,SPI Status Bit 967" "Low,High" bitfld.long 0x00 6. " SPIS966 ,SPI Status Bit 966" "Low,High" bitfld.long 0x00 5. " SPIS965 ,SPI Status Bit 965" "Low,High" textline " " bitfld.long 0x00 4. " SPIS964 ,SPI Status Bit 964" "Low,High" bitfld.long 0x00 3. " SPIS963 ,SPI Status Bit 963" "Low,High" bitfld.long 0x00 2. " SPIS962 ,SPI Status Bit 962" "Low,High" textline " " bitfld.long 0x00 1. " SPIS961 ,SPI Status Bit 961" "Low,High" bitfld.long 0x00 0. " SPIS960 ,SPI Status Bit 960" "Low,High" else hgroup.long 0xC0F8++0x03 hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" endif tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Not Used,Used" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end width 0x0B base (COMP.BASE("GICD",-1.)+0x20000) width 24. tree "Interrupt Translation Service" group.long 0x00++0x03 line.long 0x00 "GITS_CTLR,ITS Control Register" rbitfld.long 0x00 31. " QUIESCENT ,Indicates completion of all ITS operations" "Not quiescent,Quiescent" bitfld.long 0x00 0. " ENABLED ,Controls whether the ITS is enabled" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "GITS_IIDR,ITS Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)&&(((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" textline " " bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" textline " " bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1" elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" textline " " bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" textline " " bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" textline " " bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1" else rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" textline " " bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.quad 0x80++0x07 line.quad 0x00 "GITS_CBASER,The command queue control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the command queue" "Not allocated,Allocated" bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the command queue" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the command queue" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the base physical address of the command queue" textline " " bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the command queue" "Non-shareable,Inner Shareable,Outer Shareable,?..." hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of 4KB pages of physical memory allocated to the command queue minus one" group.quad 0x88++0x7 line.quad 0x00 "GITS_CWRITER,The command queue write pointer" hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER" bitfld.quad 0x00 0. " RETRY ,Restarts the processing of commands by the ITS if it stalled because of a command error" "No effect,Restarted" group.quad 0x90++0x07 line.quad 0x00 "GITS_CREADR,The command queue read pointer" hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER" bitfld.quad 0x00 0. " STALLED ,Reports whether the processing of commands is stalled because of a command error" "Not stalled,Stalled" if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0100))&0x700000000000000)==0x00) group.quad 0x100++0x07 line.quad 0x00 "GITS_BASER0,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" textline " " bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.quad 0x00 12.--47. 1. " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." else group.quad 0x100++0x07 line.quad 0x00 "GITS_BASER0,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" textline " " bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.quad 0x00 12.--47. 0x10 " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of pages of physical memory allocated to the table minus one" endif textline " " wgroup.long 0xC000++0x03 line.long 0x00 "GITS_TRKCTLR,Tracking Control Register" bitfld.long 0x00 1. " LPI_TRACK ,Write 0b1 to capture information about the next interrupt that the ITS generated or failed to generate because of misprogramming" "No effect,Capture" bitfld.long 0x00 0. " CACHE_COUNT_RESET ,Write 0b1 to reset the cache hit and miss counters in GITS_TRKICR and GITS_TRKLCR" "No effect,Reset" if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x1F)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 6. " PID_OUT_OF_RANGE ,Indicates that the LPI PID is larger than that allowed by the IDbits field in the GICR_PROPBASER" "0,1" bitfld.long 0x00 5. " TARGET_OUT_OF_RANGE ,Indicates that target collection has not been successfully mapped using MAPC or that the target core does not have LPIs enabled in GICR_CTLR" "0,1" textline " " bitfld.long 0x00 4. " NO_TRANSLATION ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" textline " " bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0xF)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 4. " NO_TRANSLATION ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" textline " " bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" textline " " bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x3)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" else rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01) rgroup.long 0xC008++0x03 line.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register" hexmask.long.tbyte 0x00 0.--19. 1. " LPI_DID ,The Device ID for the interrupt that was tracked" else hgroup.long 0xC008++0x03 hide.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01) rgroup.long 0xC00C++0x03 line.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register" hexmask.long.word 0x00 0.--15. 1. " LPI_PID ,The ID after translation for an interrupt that was tracked and generated an LPI successfully" else hgroup.long 0xC00C++0x03 hide.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01) rgroup.long 0xC010++0x03 line.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register" hexmask.long.word 0x00 0.--15. 1. " LPI_ID ,The ID before translation of the interrupt that was tracked" else hgroup.long 0xC010++0x03 hide.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01) rgroup.long 0xC014++0x03 line.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register" hexmask.long.byte 0x00 0.--6. 1. " LPI_TARGET_CORE ,The target core for an interrupt that was tracked and generated an LPI successfully" else hgroup.long 0xC014++0x03 hide.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register" endif rgroup.long 0xC018++0x03 line.long 0x00 "GITS_TRKICR,Debug ITE Cache Statistics" hexmask.long.word 0x00 16.--31. 1. " ITE_CACHE_HITS ,Number of hits in the ITE cache" hexmask.long.word 0x00 0.--15. 1. " ITE_CACHE_MISSES ,Number of misses in the ITE cache" rgroup.long 0xC01C++0x03 line.long 0x00 "GITS_TRKLCR,Debug LPI Cache Statistics" hexmask.long.word 0x00 16.--31. 1. " LPI_CACHE_HITS ,Number of hits in the LPI cache" hexmask.long.word 0x00 0.--15. 1. " LPI_CACHE_MISSES ,Number of misses in the LPI cache" rgroup.long 0xFFE0++0x03 line.long 0x00 "GITS_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GITS_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GITS_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High" textline " " bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GITS_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GITS_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GITS_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GITS_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GITS_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GITS_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GITS_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GITS_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GITS_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" textline " " base (COMP.BASE("GICD",-1.)+0x20000)+0x10000 if (((per.l((COMP.BASE("GICD",-1.)+0x20000)))&0x01)==0x01) wgroup.long 0x40++0x03 line.long 0x00 "GITS_TRANSLATER,ITS Translation Register" else hgroup.long 0x40++0x03 hide.long 0x00 "GITS_TRANSLATER,ITS Translation Register" endif tree.end width 0x0B base COMP.BASE("GICR",-1.) width 17. tree "Redistributor Interface" tree "Control Registers" if (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x21) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes" bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes" textline " " bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled" elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x20) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes" bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes" textline " " bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x01) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" endif rgroup.long 0x0004++0x03 line.long 0x00 "GICR_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" rgroup.quad 0x0008++0x07 line.quad 0x00 "GICR_TYPER,Interrupt Controller Type Register" hexmask.quad.byte 0x00 56.--63. 1. " AFF3 ,Affinity level 3 value for the Redistributor" hexmask.quad.byte 0x00 48.--55. 1. " AFF2 ,Affinity level 2 value for the Redistributor" hexmask.quad.byte 0x00 40.--47. 1. " AFF1 ,Affinity level 1 value for the Redistributor" textline " " hexmask.quad.byte 0x00 32.--39. 1. " AFF0 ,Affinity level 0 value for the Redistributor" bitfld.quad 0x00 24.--25. " COMMONLPIAFF ,The affinity level at which Redistributors share a LPI Configuration table" "All levels,AFF3,AFF3/AFF2,AFF3/AFF2/AFF1" hexmask.quad.word 0x00 8.--23. 1. " PROCESSOR_NUMBER ,A unique identifier for the PE" textline " " bitfld.quad 0x00 5. " DPGS ,Sets support for GICR_CTLR.DPG* bits" "Not supported,Supported" bitfld.quad 0x00 4. " LAST ,Indicates whether this Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages" "Not highest,Highest" bitfld.quad 0x00 3. " DIRECTLPI ,Indicates whether this Redistributor supports direct injection of LPIs" "Not supported,Supported" textline " " bitfld.quad 0x00 0. " PLPIS ,Indicates whether the GIC implementation supports physical LPIs" "Not supported,Supported" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)||((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x0014)))) group.long 0x0014++0x03 line.long 0x00 "GICR_WAKER,Power Management Control Register" bitfld.long 0x00 31. " QUIESCENT ,This bit shows that the GIC-500 is idle and can be powered down if required" "Not quiescent,Quiescent" bitfld.long 0x00 2. " CHILDRENASLEEP ,Indicates the bus between the CPU interface and this Redistributor is quiescent" "Not quiescent,Quiescent" bitfld.long 0x00 1. " PROCESSORASLEEP ,Indicates if this Redistributor must assert a WakeRequest if there is a pending interrupt targeted at the connected core" "No,Yes" textline " " bitfld.long 0x00 0. " SLEEP ,Indicates if GIC-500 ensures that all the caches are consistent with external memory and that it is safe to power off" "No,Yes" textline " " else hgroup.long 0x0014++0x03 hide.long 0x00 "GICR_WAKER,Power Management Control Register" endif group.quad 0x070++0x07 line.quad 0x00 "GICR_PROPBASER,Common LPI configuration table base register" bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the physical address containing the LPI Configuration table" textline " " bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Configuration table" "Non-shareable,Inner Shareable,Outer Shareable,?..." bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " bitfld.quad 0x00 0.--4. " IDBITS ,The number of bits of LPI INTID supported minus one by the LPI Configuration table starting at Physical_Address" group.quad 0x78++0x07 line.quad 0x00 "GICR_PENDBASER,LPI pending table base register" bitfld.quad 0x00 62. " PTZ ,Pending Table Zero" "Not zero,Zero" bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Pending table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" textline " " hexmask.quad 0x00 16.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:16] of the physical address containing the LPI Pending table" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Pending table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Pending table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " tree.end tree "SGI and PPI Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10080)) group.long 0x10080++0x03 line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x000) group.long 0x10080++0x03 line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" else hgroup.long 0x10080++0x03 hide.long 0x00 "GICR_IGROUPR0,Interrupt Group Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif textline " " width 24. group.long 0x10100++0x03 line.long 0x0 "GICR_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" group.long 0x10200++0x03 line.long 0x0 "GICR_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" group.long 0x10300++0x03 line.long 0x0 "GICR_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" textline " " width 18. group.long 0x10400++0x03 line.long 0x00 "GICR_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x10404++0x03 line.long 0x00 "GICR_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x10408++0x03 line.long 0x00 "GICR_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x1040C++0x03 line.long 0x00 "GICR_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x10410++0x03 line.long 0x00 "GICR_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x10414++0x03 line.long 0x00 "GICR_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x10418++0x03 line.long 0x00 "GICR_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x1041C++0x03 line.long 0x00 "GICR_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " textline " " rgroup.long 0x10C00++0x03 line.long 0x00 "GICR_ICFGR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge" group.long 0x10C04++0x03 line.long 0x00 "GICR_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge" textline " " width 18. if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10D00)) group.long 0x10D00++0x03 line.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0" bitfld.long 0x00 31. " GMB31 ,Group Modifier Bit 31" "0,1" bitfld.long 0x00 30. " GMB30 ,Group Modifier Bit 30" "0,1" bitfld.long 0x00 29. " GMB29 ,Group Modifier Bit 29" "0,1" textline " " bitfld.long 0x00 28. " GMB28 ,Group Modifier Bit 28" "0,1" bitfld.long 0x00 27. " GMB27 ,Group Modifier Bit 27" "0,1" bitfld.long 0x00 26. " GMB26 ,Group Modifier Bit 26" "0,1" textline " " bitfld.long 0x00 25. " GMB25 ,Group Modifier Bit 25" "0,1" bitfld.long 0x00 24. " GMB24 ,Group Modifier Bit 24" "0,1" bitfld.long 0x00 23. " GMB23 ,Group Modifier Bit 23" "0,1" textline " " bitfld.long 0x00 22. " GMB22 ,Group Modifier Bit 22" "0,1" bitfld.long 0x00 21. " GMB21 ,Group Modifier Bit 21" "0,1" bitfld.long 0x00 20. " GMB20 ,Group Modifier Bit 20" "0,1" textline " " bitfld.long 0x00 19. " GMB19 ,Group Modifier Bit 19" "0,1" bitfld.long 0x00 18. " GMB18 ,Group Modifier Bit 18" "0,1" bitfld.long 0x00 17. " GMB17 ,Group Modifier Bit 17" "0,1" textline " " bitfld.long 0x00 16. " GMB16 ,Group Modifier Bit 16" "0,1" bitfld.long 0x00 15. " GMB15 ,Group Modifier Bit 15" "0,1" bitfld.long 0x00 14. " GMB14 ,Group Modifier Bit 14" "0,1" textline " " bitfld.long 0x00 13. " GMB13 ,Group Modifier Bit 13" "0,1" bitfld.long 0x00 12. " GMB12 ,Group Modifier Bit 12" "0,1" bitfld.long 0x00 11. " GMB11 ,Group Modifier Bit 11" "0,1" textline " " bitfld.long 0x00 10. " GMB10 ,Group Modifier Bit 10" "0,1" bitfld.long 0x00 9. " GMB9 ,Group Modifier Bit 9" "0,1" bitfld.long 0x00 8. " GMB8 ,Group Modifier Bit 8" "0,1" textline " " bitfld.long 0x00 7. " GMB7 ,Group Modifier Bit 7" "0,1" bitfld.long 0x00 6. " GMB6 ,Group Modifier Bit 6" "0,1" bitfld.long 0x00 5. " GMB5 ,Group Modifier Bit 5" "0,1" textline " " bitfld.long 0x00 4. " GMB4 ,Group Modifier Bit 4" "0,1" bitfld.long 0x00 3. " GMB3 ,Group Modifier Bit 3" "0,1" bitfld.long 0x00 2. " GMB2 ,Group Modifier Bit 2" "0,1" textline " " bitfld.long 0x00 1. " GMB1 ,Group Modifier Bit 1" "0,1" bitfld.long 0x00 0. " GMB0 ,Group Modifier Bit 0" "0,1" textline " " else hgroup.long 0x10D00++0x03 hide.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10E00)) group.long 0x10E00++0x03 line.long 0x00 "GICR_NSACR,Non-secure Access Control Register" bitfld.long 0x00 30.--31. " NS_ACCESS15 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID15" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 28.--29. " NS_ACCESS14 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID14" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 26.--27. " NS_ACCESS13 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID13" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 24.--25. " NS_ACCESS12 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID12" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 22.--23. " NS_ACCESS11 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID11" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 20.--21. " NS_ACCESS10 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID10" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 18.--19. " NS_ACCESS9 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID9" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 16.--17. " NS_ACCESS8 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID8" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 14.--15. " NS_ACCESS7 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID7" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 12.--13. " NS_ACCESS6 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID6" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 10.--11. " NS_ACCESS5 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID5" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 8.--9. " NS_ACCESS4 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID4" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 6.--7. " NS_ACCESS3 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID3" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 4.--5. " NS_ACCESS2 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID2" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 2.--3. " NS_ACCESS1 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID1" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 0.--1. " NS_ACCESS0 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID0" "No access,G0S,G0S/G1S,?..." textline " " else hgroup.long 0x10E00++0x03 hide.long 0x00 "GICR_NSACR,Non-secure Access Control Register" textline " " textline " " textline " " textline " " textline " " endif rgroup.long 0x1C000++0x03 line.long 0x00 "GICR_MISCSTATUSR,Miscellaneous Status Register" bitfld.long 0x00 31. " CPU_AS ,CPU active state. This bit returns the actual status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read" "Low,High" bitfld.long 0x00 2. " ENABLEGRP1_S ,EnableGrp1 Secure" "0,1" bitfld.long 0x00 1. " ENABLEGRP1_NS ,EnableGrp1 Non-secure" "0,1" textline " " bitfld.long 0x00 0. " ENABLEGRP0 ,EnableGrp0" "0,1" rgroup.long 0x1C080++0x03 line.long 0x00 "GICR_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 31. " PPI31S ,Actual status of the PPI31 input signal" "Low,High" bitfld.long 0x00 30. " PPI30S ,Actual status of the PPI30 input signal" "Low,High" bitfld.long 0x00 29. " PPI29S ,Actual status of the PPI29 input signal" "Low,High" textline " " bitfld.long 0x00 28. " PPI28S ,Actual status of the PPI28 input signal" "Low,High" bitfld.long 0x00 27. " PPI27S ,Actual status of the PPI27 input signal" "Low,High" bitfld.long 0x00 26. " PPI26S ,Actual status of the PPI26 input signal" "Low,High" textline " " bitfld.long 0x00 25. " PPI25S ,Actual status of the PPI25 input signal" "Low,High" bitfld.long 0x00 24. " PPI24S ,Actual status of the PPI24 input signal" "Low,High" bitfld.long 0x00 23. " PPI23S ,Actual status of the PPI23 input signal" "Low,High" textline " " bitfld.long 0x00 22. " PPI22S ,Actual status of the PPI22 input signal" "Low,High" bitfld.long 0x00 21. " PPI21S ,Actual status of the PPI21 input signal" "Low,High" bitfld.long 0x00 20. " PPI20S ,Actual status of the PPI20 input signal" "Low,High" textline " " bitfld.long 0x00 19. " PPI19S ,Actual status of the PPI19 input signal" "Low,High" bitfld.long 0x00 18. " PPI18S ,Actual status of the PPI18 input signal" "Low,High" bitfld.long 0x00 17. " PPI17S ,Actual status of the PPI17 input signal" "Low,High" textline " " bitfld.long 0x00 16. " PPI16S ,Actual status of the PPI16 input signal" "Low,High" tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICR_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICR_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICR_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICR_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICR_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GICR_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GICR_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GICR_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICR_CIDR0,Component ID0 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICR_CIDR1,Component ID1 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICR_CIDR2,Component ID2 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICR_CIDR3,Component ID3 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end width 0x0B sif COMP.AVAILABLE("GICC") base COMP.BASE("GICC",-1.) width 14. tree "CPU Interface" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICC",-1.))) group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 10. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 9. " EOIMODES ,Controls the behavior of Secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" textline " " bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both" bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400) group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behavior of accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both" textline " " bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled" endif textline " " group.long 0x04++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" group.long 0x08++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x0C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x10++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x14++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x18++0x03 line.long 0x00 "GICC_HPPIR,Highest Priority Pending Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" group.long 0x1C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x20++0x03 hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register" in wgroup.long 0x24++0x03 line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x28++0x03 line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x2C++0x03 line.long 0x00 "GICC_STATUSR,CPU Interface Status Register" bitfld.long 0x00 4. " ASV ,Attempted security violation" "Not detected,Detected" bitfld.long 0x00 3. " WROD ,Write to an RO location" "Not detected,Detected" bitfld.long 0x00 2. " RWOD ,Read of a WO location" "Not detected,Detected" textline " " bitfld.long 0x00 1. " WRD ,Write to a reserved location" "Not detected,Detected" bitfld.long 0x00 0. " RRD ,Read of a reserved location" "Not detected,Detected" group.long 0xD0++0x03 line.long 0x00 "GICC_APR0,Active Priorities Register 0" group.long 0xD4++0x03 line.long 0x00 "GICC_APR1,Active Priorities Register 1" group.long 0xD8++0x03 line.long 0x00 "GICC_APR2,Active Priorities Register 2" group.long 0xDC++0x03 line.long 0x00 "GICC_APR3,Active Priorities Register 3" group.long 0xE0++0x03 line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register 0" group.long 0xE4++0x03 line.long 0x00 "GICC_NSAPR1,Non-Secure Active Priorities Register 1" group.long 0xE8++0x03 line.long 0x00 "GICC_NSAPR2,Non-Secure Active Priorities Register 2" group.long 0xEC++0x03 line.long 0x00 "GICC_NSAPR3,Non-Secure Active Priorities Register 3" rgroup.long 0xFC++0x03 line.long 0x00 "GICC_IIDR,CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" ",,,GICv3,?..." bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICC_DIR,Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" tree.end width 0x0b endif sif COMP.AVAILABLE("GICH") base COMP.BASE("GICH",-1.) width 13. tree "Virtual CPU Control Interface" group.long 0x00++0x03 line.long 0x00 "GICH_HCR,Hypervisor Control Register" bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " VGRP1DIE ,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " VGRP1EIE ,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " VGRP0DIE ,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " VGRP0EIE ,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " NPIE ,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " LRENPIE ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UIE ,Underflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,Virtual CPU interface Enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "GICH_VTR,Virtual Type Register" bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "1,2,3,4,5,6,7,8" bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "1,2,3,4,5,6,7,8" bitfld.long 0x00 23.--25. " IDBITS ,The number of virtual interrupt identifier bits supported" "16 bits,24 bits,?..." textline " " bitfld.long 0x00 22. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. " A3V ,Affinity 3 valid" "Invalid,Valid" bitfld.long 0x00 0.--4. " LISTREGS ,List regs number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0x08++0x03 line.long 0x00 "GICH_VMCR,Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. " VPMR ,Virtual priority mask" bitfld.long 0x00 21.--23. " VBPR0 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 0)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VBPR1 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 1)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9. " VEOIM ,Virtual EOImode. DP - Drop the priority / ID - interrupt deactivate" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" textline " " bitfld.long 0x00 4. " VCBPR ,Virtual Common Binary Point Register" "ABPR,BPR" bitfld.long 0x00 3. " VFIQEN ,Virtual FIQ enable" "Disabled,Enabled" bitfld.long 0x00 2. " VACKCTL ,Virtual AckCtl" "INTID=1022,INTID=corresponding" bitfld.long 0x00 1. " VENG1 ,Virtual interrupt enable for group 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " VENG0 ,Virtual interrupt enable for group 0" "Disabled,Enabled" rgroup.long 0x10++0x03 line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register" bitfld.long 0x00 7. " VGRP1D ,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 6. " VGRP1E ,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 5. " VGRP0D ,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 4. " VGRP0E ,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted" textline " " bitfld.long 0x00 3. " NP ,No Pending maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 2. " LRENP ,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 1. " U ,Underflow maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 0. " EOI ,End Of Interrupt maintenance interrupt assertion" "Not asserted,Asserted" rgroup.long 0x20++0x03 line.long 0x00 "GICH_EISR0,End of Interrupt Status Register" bitfld.long 0x00 15. " STATUS15 ,EOI maintenance interrupt status for List register 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " STATUS14 ,EOI maintenance interrupt status for List register 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " STATUS13 ,EOI maintenance interrupt status for List register 13" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " STATUS12 ,EOI maintenance interrupt status for List register 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " STATUS11 ,EOI maintenance interrupt status for List register 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " STATUS10 ,EOI maintenance interrupt status for List register 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " STATUS9 ,EOI maintenance interrupt status for List register 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " STATUS8 ,EOI maintenance interrupt status for List register 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " STATUS7 ,EOI maintenance interrupt status for List register 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " STATUS6 ,EOI maintenance interrupt status for List register 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " STATUS5 ,EOI maintenance interrupt status for List register 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " STATUS4 ,EOI maintenance interrupt status for List register 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " STATUS3 ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt" rgroup.long 0x30++0x03 line.long 0x00 "GICH_ELRSR0,Empty List register Status Register" bitfld.long 0x00 15. " STATUS15 ,Status bit for List register 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " STATUS14 ,Status bit for List register 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " STATUS13 ,Status bit for List register 13" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " STATUS12 ,Status bit for List register 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " STATUS11 ,Status bit for List register 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " STATUS10 ,Status bit for List register 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " STATUS9 ,Status bit for List register 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " STATUS8 ,Status bit for List register 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " STATUS7 ,Status bit for List register 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " STATUS6 ,Status bit for List register 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " STATUS5 ,Status bit for List register 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " STATUS4 ,Status bit for List register 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " STATUS3 ,Status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,Status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,Status bit for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,Status bit for List register 0" "No interrupt,Interrupt" textline " " group.long 0xF0++0x03 line.long 0x00 "GICH_APR0,Active Priorities Register 0" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xF4++0x03 line.long 0x00 "GICH_APR1,Active Priorities Register 1" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xF8++0x03 line.long 0x00 "GICH_APR2,Active Priorities Register 2" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "GICH_APR3,Active Priorities Register 3" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" textline " " group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x110++0x03 line.long 0x00 "GICH_LR4,List Register 4" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x114++0x03 line.long 0x00 "GICH_LR5,List Register 5" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x118++0x03 line.long 0x00 "GICH_LR6,List Register 6" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x11C++0x03 line.long 0x00 "GICH_LR7,List Register 7" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x120++0x03 line.long 0x00 "GICH_LR8,List Register 8" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x124++0x03 line.long 0x00 "GICH_LR9,List Register 9" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x128++0x03 line.long 0x00 "GICH_LR10,List Register 10" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x12C++0x03 line.long 0x00 "GICH_LR11,List Register 11" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x130++0x03 line.long 0x00 "GICH_LR12,List Register 12" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x134++0x03 line.long 0x00 "GICH_LR13,List Register 13" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x138++0x03 line.long 0x00 "GICH_LR14,List Register 14" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" tree.end width 0x0b endif sif COMP.AVAILABLE("GICV") base COMP.BASE("GICV",-1.) width 14. tree "Virtual CPU Interface" group.long 0x00++0x03 line.long 0x00 "GICV_CTLR,VM Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behaviour of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 4. " CBPR ,Controls whether GICV_BPR affects both Group 0 and Group 1 interrupts" "Group 0,Both" bitfld.long 0x00 3. " FIQEN ,FIQ Enable" "Disabled,Enabled" bitfld.long 0x00 2. " ACKCTL ,Acknowledge control. Return ID of the corresponding interrupt" "1022,Corresponding" textline " " bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signalling of Group 1 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signalling of Group 0 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled" group.long 0x04++0x03 line.long 0x00 "GICV_PMR,VM Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for the virtual CPU interface" group.long 0x08++0x03 line.long 0x00 "GICV_BPR,VM Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" rgroup.long 0x0C++0x03 line.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" wgroup.long 0x10++0x03 line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" rgroup.long 0x14++0x03 line.long 0x00 "GICV_RPR,VM Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x18++0x03 line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" group.long 0x1C++0x03 line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" rgroup.long 0x20++0x03 line.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" wgroup.long 0x24++0x03 line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" rgroup.long 0x28++0x03 line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" textline "" group.long 0xD0++0x03 line.long 0x00 "GICV_APR0,VM Active Priority Register 0" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xD4++0x03 line.long 0x00 "GICV_APR1,VM Active Priority Register 1" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xD8++0x03 line.long 0x00 "GICV_APR2,VM Active Priority Register 2" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "GICV_APR3,VM Active Priority Register 3" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" textline " " rgroup.long 0xFC++0x03 line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" ",,,GICv3,?..." hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" tree.end width 0x0b endif width 0x0B AUTOINDENT.POP tree.end tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "A53" base ad:0x0 tree "A53_RS_BW_LIMITER0_REGS" base ad:0x30403000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,PID function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" group.long 0x4++0x3 line.long 0x0 "REGS_CTRL,This register controls the overall behavior of the rate limiter module" bitfld.long 0x0 4. "REGION_FILTER_EN,Enable the region filter which will only apply the bandwith and transaction limits to the configured address regions" "0,1" bitfld.long 0x0 3. "WR_TXN_ENABLE,Enable limiting maximum outstanding write transactions" "0,1" bitfld.long 0x0 2. "RD_TXN_ENABLE,Enable limiting maximum outstanding read transactions" "0,1" bitfld.long 0x0 1. "WR_BW_ENABLE,Enable write bandwidth limiting" "0,1" bitfld.long 0x0 0. "RD_BW_ENABLE,Enable read bandwidth limiting" "0,1" group.long 0x100++0xB line.long 0x0 "REGS_RD_BW_CIR,Read Bandwidth Committed Information Rate" hexmask.long 0x0 0.--31. 1. "CIR,Committed Information Rate" line.long 0x4 "REGS_RD_BW_PIR,Read Bandwidth Peak Information Rate" hexmask.long 0x4 0.--31. 1. "PIR,Peak Information Rate" line.long 0x8 "REGS_RD_BW_BURST_OFFSET,Read Bandwidth Burst Offset" hexmask.long.word 0x8 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity. Peak Information Rate will still apply" rgroup.long 0x10C++0x3 line.long 0x0 "REGS_RD_BW_INFO,Read Bandwidth State machine information. Primarly for verification purposes" bitfld.long 0x0 0.--1. "COLOR,Read Bandwidth three-color marker output from rategen submodule" "0,1,2,3" group.long 0x120++0x7 line.long 0x0 "REGS_RD_BW_STATS,Read Bandwidth Statistics Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable read bandwidth statistics" "0,1" line.long 0x4 "REGS_RD_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR" hexmask.long 0x4 0.--31. 1. "THRESHOLD,Read bandwidth stats threshold in bytes. Note that this is total bytes unlike CIR and PIR. CIR and PIR are based on a rolling window and the statistics threshold is based on a fixed window. This will still take into account DDR bytes used so.." rgroup.long 0x128++0x13 line.long 0x0 "REGS_RD_BW_WINDOWS_CNT,Read Bandwidth Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Read bandwidth window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_RD_BW_CIR_CNT,Read Bandwidth Statistics - CIR Count" hexmask.long 0x4 0.--31. 1. "VAL,The total number of statistics windows in which Read Commit Information Rate occurred. Note that if PIR is set to a lower value than CIR or if the burst offset feature is used this will also count times that PIR is reached." line.long 0x8 "REGS_RD_BW_PIR_CNT,Read Bandwidth Statistics - PIR Count" hexmask.long 0x8 0.--31. 1. "VAL,The total number of statistics windows in which Read Peak Information Rate occurred" line.long 0xC "REGS_RD_BW_THRSHLD_CNT,Read Bandwidth Statistics - Threshold Count" hexmask.long 0xC 0.--31. 1. "VAL,The total number of statistics windows in which Read bytes transferred exceeded the statistics threshold" line.long 0x10 "REGS_RD_BYTES_MAX,The maximum number of bytes seen in a single statitsics window. This can be compared with the window size to calculate the maximum bandwidth seen" hexmask.long 0x10 0.--31. 1. "VAL,Max number of bytes in a single window. This number accounts for DDR bandwidth consumed not simply the accumulation of the packet bytecnt values across a window. The max bandwidth calculation is the total bytes value in this MMR divided by the.." group.long 0x300++0x3 line.long 0x0 "REGS_RD_TXN,The maximum number of outstanding read transactions the rate limiter will allow" hexmask.long.word 0x0 0.--15. 1. "LIMIT,The maximum number of outstanding read transactions allowed. NOTE: This cannot be programmed to a zero. If a zero is written it will default to the reset value of 16'd64 as a limit of zero outstanding transactions would hang the interface." rgroup.long 0x30C++0x3 line.long 0x0 "REGS_RD_TXN_INFO,Read Transaction State machine information. Primarly for verification purposes" hexmask.long.byte 0x0 0.--6. 1. "OCC,Read transaction scoreboard occupancy" group.long 0x320++0x7 line.long 0x0 "REGS_RD_TXN_STATS,Read Transaction Stats Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable read transaction statistics" "0,1" line.long 0x4 "REGS_RD_TXN_STATS_THRSHLD,A statistics threshold separate from the read transaction limit" hexmask.long.word 0x4 0.--15. 1. "THRESHOLD,Read transaction statistics threshold. The threshold can be set to any value though it will saturate at the outstanding transaction limit if it is set to a value greater than the programmed outstanding read transaction limit" rgroup.long 0x328++0x17 line.long 0x0 "REGS_RD_TXN_WINDOWS_CNT,Read Transaction Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Read transaction window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_RD_TXN_LMT_CNT,Read Transaction Statistics - number of windows in which the outstanding transaction limit was reached" hexmask.long 0x4 0.--31. 1. "VAL,The number of statistics windows in which the outstanding read transaction limit was reached" line.long 0x8 "REGS_RD_TXN_THRSHLD_CNT,Read Transaction Statistics - number of windows in which the statistics threshold was reached" hexmask.long 0x8 0.--31. 1. "VAL,The number of statistics windows in which the number of outstanding read transactions was greater than or equal to the threshold in RD_TXN_STATS_THRSHLD" line.long 0xC "REGS_RD_TXN_LIMIT_TOTAL,Read Transaction Statistics - Cycles at Outstanding Read Transactions Limit" hexmask.long 0xC 0.--31. 1. "VAL,The total number of cycles with the read transactions outstanding at the programmed limit since statistics collection began" line.long 0x10 "REGS_RD_TXN_THRSHLD_TOTAL,Read Transaction Statistics - Cycles at the Statistics Threshold" hexmask.long 0x10 0.--31. 1. "VAL,The total number of cycles with read transactions outstanding greater than or equal to the statistics threshold in RD_TXN_STATS_THRSHLD since statistics collection began" line.long 0x14 "REGS_RD_TXN_MAX,Read Transaction Statistics - Max Observed Outstanding Read Transactions" hexmask.long.word 0x14 0.--15. 1. "VAL,The maximum outstanding read transactions at any point in time regardless of the programmed limit" tree.end tree "A53_WS_BW_LIMITER1_REGS" base ad:0x30402000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,PID function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" group.long 0x4++0x3 line.long 0x0 "REGS_CTRL,This register controls the overall behavior of the rate limiter module" bitfld.long 0x0 4. "REGION_FILTER_EN,Enable the region filter which will only apply the bandwith and transaction limits to the configured address regions" "0,1" bitfld.long 0x0 3. "WR_TXN_ENABLE,Enable limiting maximum outstanding write transactions" "0,1" bitfld.long 0x0 2. "RD_TXN_ENABLE,Enable limiting maximum outstanding read transactions" "0,1" bitfld.long 0x0 1. "WR_BW_ENABLE,Enable write bandwidth limiting" "0,1" bitfld.long 0x0 0. "RD_BW_ENABLE,Enable read bandwidth limiting" "0,1" group.long 0x200++0xB line.long 0x0 "REGS_WR_BW_CIR,Write Bandwidth Committed Information Rate" hexmask.long 0x0 0.--31. 1. "CIR,Committed Information Rate" line.long 0x4 "REGS_WR_BW_PIR,Write Bandwidth Peak Information Rate" hexmask.long 0x4 0.--31. 1. "PIR,Peak Information Rate" line.long 0x8 "REGS_WR_BW_BURST_OFFSET,Write Bandwidth Burst Offset" hexmask.long.word 0x8 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity. Peak Information Rate will still apply" rgroup.long 0x20C++0x3 line.long 0x0 "REGS_WR_BW_INFO,Write Bandwidth State machine information. Primarly for verification purposes" bitfld.long 0x0 0.--1. "COLOR,Write Bandwidth three-color marker output from rategen submodule" "0,1,2,3" group.long 0x220++0x7 line.long 0x0 "REGS_WR_BW_STATS,Write Bandwidth Statistics Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable write bandwidth statistics" "0,1" line.long 0x4 "REGS_WR_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR" hexmask.long 0x4 0.--31. 1. "THRESHOLD,Write bandwidth stats threshold in bytes. Note that this is total bytes unlike CIR and PIR. CIR and PIR are based on a rolling window and the statistics threshold is based on a fixed window. This will still take into account DDR bytes used .." rgroup.long 0x228++0x13 line.long 0x0 "REGS_WR_BW_WINDOWS_CNT,Write Bandwidth Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Write bandwidth window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_WR_BW_CIR_CNT,Write Bandwidth Statistics - CIR Count" hexmask.long 0x4 0.--31. 1. "VAL,The total number of statistics windows in which Write Commit Information Rate occurred. Note that if PIR is set to a lower value than CIR or if the burst offset feature is used this will also count times that PIR is reached." line.long 0x8 "REGS_WR_BW_PIR_CNT,Write Bandwidth Statistics - PIR Count" hexmask.long 0x8 0.--31. 1. "VAL,The total number of statistics windows in which Write Peak Information Rate occurred" line.long 0xC "REGS_WR_BW_THRSHLD_CNT,Write Bandwidth Statistics - Threshold Count" hexmask.long 0xC 0.--31. 1. "VAL,The total number of statistics windows in which Write bytes transferred exceeded the statistics threshold" line.long 0x10 "REGS_WR_BYTES_MAX,The maximum number of bytes seen in a single statitsics window. This can be compared with the window size to calculate the maximum bandwidth seen" hexmask.long 0x10 0.--31. 1. "VAL,Max number of bytes in a single window. This number accounts for DDR bandwidth consumed not simply the accumulation of the packet bytecnt values across a window. The max bandwidth calculation is the total bytes value in this MMR divided by the.." group.long 0x400++0x3 line.long 0x0 "REGS_WR_TXN,The maximum number of outstanding write transactions the rate limiter will allow" hexmask.long.word 0x0 0.--15. 1. "LIMIT,The maximum number of outstanding write transactions allowed. NOTE: This cannot be programmed to a zero. If a zero is written it will default to the reset value of 16'd64 as a limit of zero outstanding transactions would hang the interface." rgroup.long 0x40C++0x3 line.long 0x0 "REGS_WR_TXN_INFO,Write Transaction State machine information. Primarly for verification purposes" hexmask.long.byte 0x0 0.--6. 1. "OCC,Write transaction scoreboard occupancy" group.long 0x420++0x7 line.long 0x0 "REGS_WR_TXN_STATS,Write Transaction Stats Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable write transaction statistics" "0,1" line.long 0x4 "REGS_WR_TXN_STATS_THRSHLD,A statistics threshold separate from the write transaction limit" hexmask.long.word 0x4 0.--15. 1. "THRESHOLD,Write transaction statistics threshold. The threshold can be set to any value though it will saturate at the outstanding transaction limit if it is set to a value greater than the programmed outstanding write transaction limit" rgroup.long 0x428++0x17 line.long 0x0 "REGS_WR_TXN_WINDOWS_CNT,Write Transaction Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Write transaction window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_WR_TXN_LMT_CNT,Write Transaction Statistics - number of windows in which the outstanding transaction limit was reached" hexmask.long 0x4 0.--31. 1. "VAL,The number of statistics windows in which the outstanding write transaction limit was reached" line.long 0x8 "REGS_WR_TXN_THRSHLD_CNT,Write Transaction Statistics - number of windows in which the statistics threshold was reached" hexmask.long 0x8 0.--31. 1. "VAL,The number of statistics windows in which the number of outstanding write transactions was greater than or equal to the threshold in WR_TXN_STATS_THRSHLD" line.long 0xC "REGS_WR_TXN_LIMIT_TOTAL,Write Transaction Statistics - Cycles at Outstanding Write Transactions Limit" hexmask.long 0xC 0.--31. 1. "VAL,The total number of cycles with the write transactions outstanding at the programmed limit since statistics collection began" line.long 0x10 "REGS_WR_TXN_THRSHLD_TOTAL,Write Transaction Statistics - Cycles at the Statistics Threshold" hexmask.long 0x10 0.--31. 1. "VAL,The total number of cycles with write transactions outstanding greater than or equal to the statistics threshold in WR_TXN_STATS_THRSHLD since statistics collection began" line.long 0x14 "REGS_WR_TXN_MAX,Write Transaction Statistics - Max Observed Outstanding Write Transactions" hexmask.long.word 0x14 0.--15. 1. "VAL,The maximum outstanding write transactions at any point in time regardless of the programmed limit" tree.end tree.end tree "A53SS0" base ad:0x0 tree "A53SS0_CORE0" tree "A53SS0_CORE0_CTI" base ad:0x730020000 group.long 0x0++0x3 line.long 0x0 "APBADDR_CTI_CPU0_CTICONTROL,CTI Control Register" hexmask.long 0x0 1.--31. 1. "RES0_CTICONTROL_31_1,Reserved RES0." bitfld.long 0x0 0. "GLBEN,Enables or disables the CTI mapping functions. Possible values of this field are: 0 CTI mapping functions disabled. 1 CTI mapping functions enabled. When the mapping.." "0,1" group.long 0x10++0x2F line.long 0x0 "APBADDR_CTI_CPU0_CTIINTACK,CTI Output Trigger Acknowledge Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--7. 1. "ACK_N,Can be used to create soft acknowledges for output triggers" line.long 0x4 "APBADDR_CTI_CPU0_CTIAPPSET,CTI Application Trigger Set Register" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "CTIAPPSETX,Application trigger enable" line.long 0x8 "APBADDR_CTI_CPU0_CTIAPPCLEAR,CTI Application Trigger Clear Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x8 0.--3. 1. "CTIAPPCLEARX,Application trigger disable" line.long 0xC "APBADDR_CTI_CPU0_CTIAPPPULSE,CTI Application Pulse Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0xC 0.--3. 1. "CTIAPPPULSEX,Generate event pulse on ECT channel ." line.long 0x10 "APBADDR_CTI_CPU0_CTIINEN0,CTI Input Trigger to Output Channel Enable Register 0" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x10 0.--3. 1. "INENX,Input trigger 0 to output channel enable" line.long 0x14 "APBADDR_CTI_CPU0_CTIINEN1,CTI Input Trigger to Output Channel Enable Register 1" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x14 0.--3. 1. "INENX,Input trigger 1 to output channel enable" line.long 0x18 "APBADDR_CTI_CPU0_CTIINEN2,CTI Input Trigger to Output Channel Enable Register 2" hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x18 0.--3. 1. "INENX,Input trigger 2 to output channel enable" line.long 0x1C "APBADDR_CTI_CPU0_CTIINEN3,CTI Input Trigger to Output Channel Enable Register 3" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x1C 0.--3. 1. "INENX,Input trigger 3 to output channel enable" line.long 0x20 "APBADDR_CTI_CPU0_CTIINEN4,CTI Input Trigger to Output Channel Enable Register 4" hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x20 0.--3. 1. "INENX,Input trigger 4 to output channel enable" line.long 0x24 "APBADDR_CTI_CPU0_CTIINEN5,CTI Input Trigger to Output Channel Enable Register 5" hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x24 0.--3. 1. "INENX,Input trigger 5 to output channel enable" line.long 0x28 "APBADDR_CTI_CPU0_CTIINEN6,CTI Input Trigger to Output Channel Enable Register 6" hexmask.long 0x28 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x28 0.--3. 1. "INENX,Input trigger 6 to output channel enable" line.long 0x2C "APBADDR_CTI_CPU0_CTIINEN7,CTI Input Trigger to Output Channel Enable Register 7" hexmask.long 0x2C 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x2C 0.--3. 1. "INENX,Input trigger 7 to output channel enable" group.long 0xA0++0x1F line.long 0x0 "APBADDR_CTI_CPU0_CTIOUTEN0,CTI Input Channel to Output Trigger Enable Register 0" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--3. 1. "OUTENX,Input channel to output trigger 0 enable" line.long 0x4 "APBADDR_CTI_CPU0_CTIOUTEN1,CTI Input Channel to Output Trigger Enable Register 1" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "OUTENX,Input channel to output trigger 1 enable" line.long 0x8 "APBADDR_CTI_CPU0_CTIOUTEN2,CTI Input Channel to Output Trigger Enable Register 2" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x8 0.--3. 1. "OUTENX,Input channel to output trigger 2 enable" line.long 0xC "APBADDR_CTI_CPU0_CTIOUTEN3,CTI Input Channel to Output Trigger Enable Register 3" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0xC 0.--3. 1. "OUTENX,Input channel to output trigger 3 enable" line.long 0x10 "APBADDR_CTI_CPU0_CTIOUTEN4,CTI Input Channel to Output Trigger Enable Register 4" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x10 0.--3. 1. "OUTENX,Input channel to output trigger 4 enable" line.long 0x14 "APBADDR_CTI_CPU0_CTIOUTEN5,CTI Input Channel to Output Trigger Enable Register 5" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x14 0.--3. 1. "OUTENX,Input channel to output trigger 5 enable" line.long 0x18 "APBADDR_CTI_CPU0_CTIOUTEN6,CTI Input Channel to Output Trigger Enable Register 6" hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x18 0.--3. 1. "OUTENX,Input channel to output trigger 6 enable" line.long 0x1C "APBADDR_CTI_CPU0_CTIOUTEN7,CTI Input Channel to Output Trigger Enable Register 7" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x1C 0.--3. 1. "OUTENX,Input channel to output trigger 7 enable" group.long 0x130++0x17 line.long 0x0 "APBADDR_CTI_CPU0_CTITRIGINSTATUS,CTI Trigger In Status Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--7. 1. "TRINN,Provides the status of the trigger inputs" line.long 0x4 "APBADDR_CTI_CPU0_CTITRIGOUTSTATUS,CTI Trigger Out Status Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--7. 1. "TROUTN,Provides the status of the trigger outputs" line.long 0x8 "APBADDR_CTI_CPU0_CTICHINSTATUS,CTI Channel In Status Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x8 0.--3. 1. "CHINN,Provides the raw status of the ECT channel inputs to the CTI" line.long 0xC "APBADDR_CTI_CPU0_CTICHOUTSTATUS,CTI Channel Out Status Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0xC 0.--3. 1. "CHOUTN,Provides the status of the ECT channel outputs from the CTI" line.long 0x10 "APBADDR_CTI_CPU0_CTIGATE,CTI Channel Gate Enable Register" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x10 0.--3. 1. "GATEX,Determines whether events on channels propagate through the CTM to other ECT components or from the CTM into the CTI" line.long 0x14 "APBADDR_CTI_CPU0_ASICCTL,CTI External Multiplexor Control register" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_ASICCTL_31_8,Reserved RES0." hexmask.long.byte 0x14 0.--7. 1. "ASICCTL,IMPLEMENTATION DEFINED ASIC control. Provides a control for external multiplexing of additional triggers into the CTI.If external multiplexing of trigger signals is implemented then the number of multiplexed signals on each trigger must be.." group.long 0xF00++0x3 line.long 0x0 "APBADDR_CTI_CPU0_CTIITCTRL,CTI Integration mode Control Register" hexmask.long 0x0 1.--31. 1. "RES0_CTIITCTRL_31_1,Reserved RES0." bitfld.long 0x0 0. "IME,Integration mode enable. When IME == 1 the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED. 0 Normal operation." "0,1" group.long 0xFA0++0x5F line.long 0x0 "APBADDR_CTI_CPU0_CTICLAIMSET,CTI Claim Set" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--3. 1. "CLAIMX,CLAIM tag set bit" line.long 0x4 "APBADDR_CTI_CPU0_CTICLAIMCLR,CTI Claim Clear" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "CLAIMX,Clear CLAIM tag" line.long 0x8 "APBADDR_CTI_CPU0_CTIDEVAFF0,CTI Device Affinity Register 0" hexmask.long 0x8 0.--31. 1. "CTIDEVAFF0,MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0xC "APBADDR_CTI_CPU0_CTIDEVAFF1,CTI Device Affinity Register 1" hexmask.long 0xC 0.--31. 1. "CTIDEVAFF1,MPIDR_EL1 high half. Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x10 "APBADDR_CTI_CPU0_CTILAR,CTI Lock Access Register" hexmask.long 0x10 0.--31. 1. "KEY,Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register locks the lock disabling write.." line.long 0x14 "APBADDR_CTI_CPU0_CTILSR,CTI Lock Status Register" hexmask.long 0x14 3.--31. 1. "RES0_CTILSR_31_3,Reserved RES0." bitfld.long 0x14 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" bitfld.long 0x14 1. "SLK,Software lock status for this component. For an access to LSR that is not a memory-mapped access or when the software lock is not implemented this field is RES0.For memory-mapped accesses when the software lock is implemented possible values of.." "0,1" newline bitfld.long 0x14 0. "SLI,Software lock implemented. For an access to LSR that is not a memory-mapped access this field is RAZ. For memory-mapped accesses the value of this field is IMPLEMENTATION DEFINED. Permitted values are: 0 Software lock not.." "0,1" line.long 0x18 "APBADDR_CTI_CPU0_CTIAUTHSTATUS,CTI Authentication Status Register" hexmask.long 0x18 4.--31. 1. "RES0_CTIAUTHSTATUS_31_4,Reserved RES0." bitfld.long 0x18 2.--3. "NSNID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SNID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSNID." "0,1,2,3" bitfld.long 0x18 0.--1. "NSID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSID." "0,1,2,3" line.long 0x1C "APBADDR_CTI_CPU0_CTIDEVARCH,CTI Device Architecture Register" hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For CTI this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A." "0,1" hexmask.long.byte 0x1C 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For CTI the revision defined by v8-A is 0x0.All other values are reserved." newline hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For CTI:Bits [15:12] are the architecture version 0x1.Bits [11:0] are the architecture part number 0xA14.This corresponds to CTI.." line.long 0x20 "APBADDR_CTI_CPU0_CTIDEVID2,CTI Device ID Register 2" hexmask.long 0x20 0.--31. 1. "RES0_CTIDEVID2_31_0,Reserved RES0." line.long 0x24 "APBADDR_CTI_CPU0_CTIDEVID1,CTI Device ID Register 1" hexmask.long 0x24 0.--31. 1. "RES0_CTIDEVID1_31_0,Reserved RES0." line.long 0x28 "APBADDR_CTI_CPU0_CTIDEVID,CTI Device ID Register 0" hexmask.long.byte 0x28 26.--31. 1. "RES0_CTIDEVID_31_26,Reserved RES0." bitfld.long 0x28 24.--25. "INOUT,Input/output options. Indicates presence of the input gate. If the CTM is not implemented this field is RAZ. 00 CTIGATE does not mask propagation of input events from external channels. 01.." "0,1,2,3" bitfld.long 0x28 22.--23. "RES0_CTIDEVID_23_22,Reserved RES0." "0,1,2,3" newline hexmask.long.byte 0x28 16.--21. 1. "NUMCHAN,Number of ECT channels implemented. IMPLEMENTATION DEFINED. For v8-A valid values are: 000011 3 channels [0..2] implemented. 000100 4 channels [0..3] implemented." bitfld.long 0x28 14.--15. "RES0_CTIDEVID_15_14,Reserved RES0." "0,1,2,3" hexmask.long.byte 0x28 8.--13. 1. "NUMTRIG,Number of triggers implemented. IMPLEMENTATION DEFINED. This is one more than the index of the largest trigger rather than the actual number of triggers.For v8-A valid values are: 000011 Up to 3 triggers [0..2] implemented." newline bitfld.long 0x28 5.--7. "RES0_CTIDEVID_7_5,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 0.--4. 1. "EXTMUXNUM,Maximum number of external triggers available for multiplexing into the CTI. This relates only to additional external triggers outside those defined for v8-A." line.long 0x2C "APBADDR_CTI_CPU0_CTIDEVTYPE,CTI Device Type Register" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_CTIDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x2C 4.--7. 1. "SUB,Subtype. Must read as 0x1 to indicate this is a processor component." hexmask.long.byte 0x2C 0.--3. 1. "MAJOR,Major type. Must read as 0x4 to indicate this is a cross-trigger component." line.long 0x30 "APBADDR_CTI_CPU0_CTIPIDR4,CTI Peripheral Identification Register 4" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_CTIPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x30 4.--7. 1. "SIZE,Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers." hexmask.long.byte 0x30 0.--3. 1. "DES_2,Designer JEP106 continuation code least significant nibble. For ARM Limited this field is 0b0100." line.long 0x34 "APBADDR_CTI_CPU0_CTIPIDR5,CTI Peripheral Identification Register 5" hexmask.long 0x34 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x38 "APBADDR_CTI_CPU0_CTIPIDR6,CTI Peripheral Identification Register 6" hexmask.long 0x38 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x3C "APBADDR_CTI_CPU0_CTIPIDR7,CTI Peripheral Identification Register 7" hexmask.long 0x3C 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x40 "APBADDR_CTI_CPU0_CTIPIDR0,CTI Peripheral Identification Register 0" hexmask.long.tbyte 0x40 8.--31. 1. "RES0_CTIPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x40 0.--7. 1. "PART_0,Part number least significant byte." line.long 0x44 "APBADDR_CTI_CPU0_CTIPIDR1,CTI Peripheral Identification Register 1" hexmask.long.tbyte 0x44 8.--31. 1. "RES0_CTIPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x44 4.--7. 1. "DES_0,Designer least significant nibble of JEP106 ID code. For ARM Limited this field is 0b1011." hexmask.long.byte 0x44 0.--3. 1. "PART_1,Part number most significant nibble." line.long 0x48 "APBADDR_CTI_CPU0_CTIPIDR2,CTI Peripheral Identification Register 2" hexmask.long.tbyte 0x48 8.--31. 1. "RES0_CTIPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x48 4.--7. 1. "REVISION,Part major revision. Parts can also use this field to extend Part number to 16-bits." bitfld.long 0x48 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" newline bitfld.long 0x48 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0x4C "APBADDR_CTI_CPU0_CTIPIDR3,CTI Peripheral Identification Register 3" hexmask.long.tbyte 0x4C 8.--31. 1. "RES0_CTIPIDR3_31_8,Reserved RES0." hexmask.long.byte 0x4C 4.--7. 1. "REVAND,Part minor revision. Parts using CTIPIDR2.REVISION as an extension to the Part number must use this field as a major revision number." hexmask.long.byte 0x4C 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x50 "APBADDR_CTI_CPU0_CTICIDR0,CTI Component Identification Register 0" hexmask.long.tbyte 0x50 8.--31. 1. "RES0_CTICIDR0_31_8,Reserved RES0." hexmask.long.byte 0x50 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x54 "APBADDR_CTI_CPU0_CTICIDR1,CTI Component Identification Register 1" hexmask.long.tbyte 0x54 8.--31. 1. "RES0_CTICIDR1_31_8,Reserved RES0." hexmask.long.byte 0x54 4.--7. 1. "CLASS,Component class. Reads as 0x9 debug component." hexmask.long.byte 0x54 0.--3. 1. "PRMBL_1,Preamble. RAZ." line.long 0x58 "APBADDR_CTI_CPU0_CTICIDR2,CTI Component Identification Register 2" hexmask.long.tbyte 0x58 8.--31. 1. "RES0_CTICIDR2_31_8,Reserved RES0." hexmask.long.byte 0x58 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x5C "APBADDR_CTI_CPU0_CTICIDR3,CTI Component Identification Register 3" hexmask.long.tbyte 0x5C 8.--31. 1. "RES0_CTICIDR3_31_8,Reserved RES0." hexmask.long.byte 0x5C 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree "A53SS0_CORE0_DBG" base ad:0x730010000 group.long 0x20++0x7 line.long 0x0 "APBADDR_DBG_CPU0_EDESR,External Debug Event Status Register" hexmask.long 0x0 3.--31. 1. "RES0_EDESR_31_3,Reserved RES0." bitfld.long 0x0 2. "SS,Halting step debug event pending. Possible values of this field are: 0 Reading this means that a Halting step debug event is not pending. Writing this means no action. 1 Reading this means that.." "0,1" newline bitfld.long 0x0 1. "RC,Reset catch debug event pending. Possible values of this field are: 0 Reading this means that a Reset catch debug event is not pending. Writing this means no action. 1 Reading this means that a.." "0,1" bitfld.long 0x0 0. "OSUC,OS unlock debug event pending. Possible values of this field are: 0 Reading this means that an OS unlock catch debug event is not pending. Writing this means no action. 1 Reading this means.." "0,1" line.long 0x4 "APBADDR_DBG_CPU0_EDECR,External Debug Execution Control Register" hexmask.long 0x4 3.--31. 1. "RES0_EDECR_31_3,Reserved RES0." bitfld.long 0x4 2. "SS,Halting step enable. Possible values of this field are: 0 Halting step debug event disabled. 1 Halting step debug event enabled. If the value of EDECR.SS is changed when the.." "0,1" newline bitfld.long 0x4 1. "RCE,Reset catch enable. Possible values of this field are: 0 Reset catch debug event disabled. 1 Reset catch debug event enabled." "0,1" bitfld.long 0x4 0. "OSUCE,OS unlock catch enabled. Possible values of this field are: 0 OS unlock catch debug event disabled. 1 OS unlock catch debug event enabled." "0,1" group.long 0x30++0x7 line.long 0x0 "APBADDR_DBG_CPU0_EDWAR_31_0,External Debug Watchpoint Address Register (low word)" hexmask.long 0x0 0.--31. 1. "EDWAR_31_0,Watchpoint address. The virtual data address being accessed when a watchpoint debug event was triggered and caused entry to Debug state.UNKNOWN if the processor is not in Debug state or if Debug state was entered other than for a watchpoint.." line.long 0x4 "APBADDR_DBG_CPU0_EDWAR_63_32,External Debug Watchpoint Address Register (high word)" hexmask.long 0x4 0.--31. 1. "EDWAR_63_32,Watchpoint address. The virtual data address being accessed when a watchpoint debug event was triggered and caused entry to Debug state.UNKNOWN if the processor is not in Debug state or if Debug state was entered other than for a watchpoint.." group.long 0x80++0x1B line.long 0x0 "APBADDR_DBG_CPU0_DBGDTRRX_EL0,Debug Data Transfer Register Receive" hexmask.long 0x0 0.--31. 1. "DBGDTRRX_EL0,Update DTRRX. Writes to this register update the value in DTRRX and set RXfull to 1.Reads of this register return the last value written to DTRRX and do not change RXfull." line.long 0x4 "APBADDR_DBG_CPU0_EDITR,External Debug Instruction Transfer Register" hexmask.long 0x4 0.--31. 1. "EDITR,Used in Debug state for passing instructions to the processor for execution" line.long 0x8 "APBADDR_DBG_CPU0_EDSCR,External Debug Status and Control Register" bitfld.long 0x8 31. "RES0_EDSCR_31_31,Reserved RES0." "0,1" bitfld.long 0x8 30. "RXFULL,DTRRX full. This bit is RO." "0,1" newline bitfld.long 0x8 29. "TXFULL,DTRTX full. This bit is RO." "0,1" bitfld.long 0x8 28. "ITO,EDITR overrun. This bit is RO.If the processor is not in Debug state this bit is UNKNOWN. ITO is set to 0 on entry to Debug state." "0,1" newline bitfld.long 0x8 27. "RXO,DTRRX overrun. This bit is RO." "0,1" bitfld.long 0x8 26. "TXU,DTRTX underrun. This bit is RO." "0,1" newline bitfld.long 0x8 25. "PIPEADV,Pipeline advance. Read-only. Set to 1 every time the processor pipeline retires one or more instructions. Cleared to 0 by a write to EDRCR.CSPA.The architecture does not define precisely when this bit is set to 1. It requires only that this.." "0,1" bitfld.long 0x8 24. "ITE,ITR empty. This bit is RO.If the processor is not in Debug state this bit is UNKNOWN. It is always valid in Debug state." "0,1" newline bitfld.long 0x8 22.--23. "INTDIS,Interrupt disable. Disables taking interrupts [including virtual interrupts and System Error interrupts] in Non-Debug state.If external invasive debug is disabled the value of this field is ignored.If external invasive debug is enabled the.." "0,1,2,3" bitfld.long 0x8 21. "TDA,Trap debug registers accesses." "0,1" newline bitfld.long 0x8 20. "MA,Memory access mode. Controls use of memory-access mode for accessing EDITR and the DCC. This bit is ignored if in Non-debug state and set to zero on entry to Debug state.Possible values of this field are: 0 Normal access mode.." "0,1" bitfld.long 0x8 19. "RES0_EDSCR_19_19,Reserved RES0." "0,1" newline bitfld.long 0x8 18. "NS,Non-secure status. Read-only. When in Debug state gives the current security state: 0 Secure state IsSecure[] == TRUE 1 Non-secure state IsSecure[] == FALSE. In Non-debug.." "0,1" bitfld.long 0x8 17. "RES0_EDSCR_17_17,Reserved RES0." "0,1" newline bitfld.long 0x8 16. "SDD,Secure debug disabled. This bit is RO.On entry to Debug state:If entering in Secure state SDD is set to 0.If entering in Non-secure state SDD is set to the inverse of ExternalSecureInvasiveDebugEnabled[].In Debug state the value of the SDD bit.." "0,1" bitfld.long 0x8 15. "RES0_EDSCR_15_15,Reserved RES0." "0,1" newline bitfld.long 0x8 14. "HDE,Halting debug mode enable. Possible values of this bit are: 0 Halting debug mode disabled. 1 Halting debug mode enabled." "0,1" hexmask.long.byte 0x8 10.--13. 1. "RW,Exception level register-width status. Read-only. In Debug state each bit gives the current register width status of each EL: 1111 All exception levels are AArch64 state. 1110 EL0 is AArch32.." newline bitfld.long 0x8 8.--9. "EL,Exception level. Read-only. In Debug state this gives the current EL of the processor.In Non-debug state this field is RAZ." "0,1,2,3" bitfld.long 0x8 7. "A,System Error interrupt pending. Read-only. In Debug state indicates whether a SError interrupt is pending:If HCR_EL2.{AMO TGE} = {1 0} and in Non-secure EL0 or EL1 a virtual SError interrupt.Otherwise a physical SError interrupt. 0.." "0,1" newline bitfld.long 0x8 6. "ERR,Cumulative error flag. This field is RO. It is set to 1 following exceptions in Debug state and on any signaled overrun or underrun on the DTR or EDITR." "0,1" hexmask.long.byte 0x8 0.--5. 1. "STATUS,Debug status flags. This field is RO.The possible values of this field are: 000010 Processor is in Non-debug state. 000001 Processor is restarting [exiting Debug state]." line.long 0xC "APBADDR_DBG_CPU0_DBGDTRTX_EL0,Debug Data Transfer Register Transmit" hexmask.long 0xC 0.--31. 1. "DBGDTRTX_EL0,Return DTRTX. Reads of this register return the value in DTRTX and clear TXfull to 0.Writes of this register update the value in DTRTX and do not change TXfull." line.long 0x10 "APBADDR_DBG_CPU0_EDRCR,External Debug Reserve Control Register" hexmask.long 0x10 5.--31. 1. "RES0_EDRCR_31_5,Reserved RES0." bitfld.long 0x10 4. "CBRRQ,Allow imprecise entry to Debug state. The actions on writing to this bit are: 0 No action. 1 Allow imprecise entry to Debug state for example by canceling pending bus accesses." "0,1" newline bitfld.long 0x10 3. "CSPA,Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The actions on writing to this bit are: 0 No action. 1 Clear the EDSCR.PipeAdv bit to 0." "0,1" bitfld.long 0x10 2. "CSE,Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The actions on writing to this bit are: 0 No action. 1 Clear the EDSCR.{TXU RXO ERR} bits and if the processor is in.." "0,1" newline bitfld.long 0x10 0.--1. "RES0_EDRCR_1_0,Reserved RES0." "0,1,2,3" line.long 0x14 "APBADDR_DBG_CPU0_EDACR,External Debug Auxiliary Control Register" hexmask.long 0x14 0.--31. 1. "RES0_EDACR_31_0,Reserved RES0" line.long 0x18 "APBADDR_DBG_CPU0_EDECCR,External Debug Exception Catch Control Register" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDECCR_31_8,Reserved RES0." hexmask.long.byte 0x18 4.--7. 1. "NSE,Coarse-grained Non-secure exception catch. Possible values of this field are: 0000 Exception catch debug event disabled for Non-secure exception levels. 0010 Exception catch debug event enabled.." newline hexmask.long.byte 0x18 0.--3. 1. "SE,Coarse-grained Secure exception catch. Possible values of this field are: 0000 Exception catch debug event disabled for Secure exception levels. 0010 Exception catch debug event enabled for.." group.long 0xA0++0xF line.long 0x0 "APBADDR_DBG_CPU0_EDPCSR_31_0,External Debug Program Counter Sample Register (low word)" hexmask.long 0x0 0.--31. 1. "EDPCSR_31_0,PC Sample low word EDPCSRlo. Bits [31:0] of the sampled instruction address value. Reading EDPCSRlo has the side-effect of updating EDCIDSR EDVIDSR and EDPCSRhi. However:If the processor is in Debug state or Sample-based profiling is.." line.long 0x4 "APBADDR_DBG_CPU0_EDCIDSR,External Debug Context ID Sample Register" hexmask.long 0x4 0.--31. 1. "CONTEXTIDR,The sampled value of CONTEXTIDR_EL1 captured on reading the low half of EDPCSR.If EL3 is implemented and using AArch32 then CONTEXTIDR is a Banked register and EDCIDSR samples the current Banked copy of CONTEXTIDR." line.long 0x8 "APBADDR_DBG_CPU0_EDVIDSR,External Debug Virtual Context Sample Register" bitfld.long 0x8 31. "NS,Non-secure state sample. Indicates the security state associated with the most recent EDPCSR sample." "0,1" bitfld.long 0x8 30. "E2,Exception level 2 status sample. Indicates whether the most recent EDPCSR sample was associated with EL2. If EDVIDSR.NS == 0 this bit is 0." "0,1" newline bitfld.long 0x8 29. "E3,Exception level 3 status sample. Indicates whether the most recent EDPCSR sample was associated with AArch64 EL3. If EDVIDSR.NS == 1 or the processor was in AArch32 state when EDPCSR was read this bit is 0." "0,1" bitfld.long 0x8 28. "HV,EDPCSR high half valid. Indicates whether bits [63:32] of the most recent EDPCSR sample are valid. If EDVIDSR.HV == 0 the value of EDPCSR[63:32] is RAZ." "0,1" newline hexmask.long.tbyte 0x8 8.--27. 1. "RES0_EDVIDSR_27_8,Reserved RES0." hexmask.long.byte 0x8 0.--7. 1. "VMID,VMID sample. The value of VTTBR_EL2.VMID associated with the most recent EDPCSR sample. If EDVIDSR.NS == 0 or EDVIDSR.E2 == 1 this field is RAZ." line.long 0xC "APBADDR_DBG_CPU0_EDPCSR_63_32,External Debug Program Counter Sample Register (high word)" hexmask.long 0xC 0.--31. 1. "EDPCSR_63_32,PC Sample high word EDPCSRhi. If EDVIDSR.HV == 0 then this field is RAZ otherwise bits [63:32] of the sampled PC." group.long 0x300++0x3 line.long 0x0 "APBADDR_DBG_CPU0_OSLAR_EL1,OS Lock Access Register" hexmask.long 0x0 1.--31. 1. "RES0_OSLAR_EL1_31_1,Reserved RES0." bitfld.long 0x0 0. "OSLK,On writes to OSLAR_EL1 bit[0] is copied to the OS lock.Use EDPRSR.OSLK to check the current status of the lock." "0,1" group.long 0x310++0x7 line.long 0x0 "APBADDR_DBG_CPU0_EDPRCR,External Debug Power/Reset Control Register" hexmask.long 0x0 4.--31. 1. "RES0_EDPRCR_31_4,Reserved RES0." bitfld.long 0x0 3. "COREPURQ,Core powerup request. Allows a debugger to request that the power controller power up the core enabling access to the debug register in the Core power domain. The actions on writing to this bit are: 0 No effect." "0,1" newline bitfld.long 0x0 2. "RES0_EDPRCR_2_2,Reserved RES0." "0,1" bitfld.long 0x0 1. "CWRR,Warm reset request. Write only bit that reads as zero. The actions on writing to this bit are: 0 No action. 1 Request Warm reset. The processor ignores writes to this bit if.." "0,1" newline bitfld.long 0x0 0. "CORENPDRQ,Core no powerdown request. Requests emulation of powerdown. Possible values of this bit are: 0 On a powerdown request the system powers down the Core power domain. 1 On a powerdown.." "0,1" line.long 0x4 "APBADDR_DBG_CPU0_EDPRSR,External Debug Processor Status Register" hexmask.long.tbyte 0x4 12.--31. 1. "RES0_EDPRSR_31_12,Reserved RES0." bitfld.long 0x4 11. "SDR,Sticky debug restart. Set to 1 when the processor exits Debug state and cleared to 0 following reads of EDPRSR. 0 The processor has not restarted since EDPRSR was last read. 1 The processor has.." "0,1" newline bitfld.long 0x4 10. "SPMAD,Sticky EPMAD error. Set to 1 if an access returns an error because AllowExternalPMUAccess[] == FALSE. 0 No accesses to the external performance monitors registers have failed since EDPRSR was last read. 1.." "0,1" bitfld.long 0x4 9. "EPMAD,External performance monitors access disable status. 0 External performance monitors access enabled. 1 External performance monitors access disabled. If external performance.." "0,1" newline bitfld.long 0x4 8. "SDAD,Sticky EDAD error. Set to 1 if an access returns an error because AllowExternalDebugAccess[] == FALSE. 0 No accesses to the external debug registers have failed since EDPRSR was last read. 1.." "0,1" bitfld.long 0x4 7. "EDAD,External debug access disable status. 0 External debug access enabled. 1 External debug access disabled. This bit is UNKNOWN on reads if either of EDPRSR.{DLK R} is 1 or.." "0,1" newline bitfld.long 0x4 6. "DLK,OS Double Lock status bit. 0 OSDLR_EL1.DLK == 0 or EDPRCR.CORENPDRQ == 1 or the processor is in Debug state. 1 OSDLR_EL1.DLK == 1 and EDPRCR.CORENPDRQ == 0 and the processor is in Non-debug.." "0,1" bitfld.long 0x4 5. "OSLK,OS lock status bit. A read of this bit returns the value of OSLSR_EL1.OSLK.This bit is UNKNOWN on reads if either of EDPRSR.{DLK R} is 1 or EDPRSR.PU is 0." "0,1" newline bitfld.long 0x4 4. "HALTED,Halted status bit. Possible values are: 0 EDSCR.STATUS is 0b000010 [processor in Non-debug state]. 1 EDSCR.STATUS is not 0b000010. This bit is UNKNOWN on reads if EDPRSR.PU.." "0,1" bitfld.long 0x4 3. "SR,Sticky core reset status bit. Possible values are: 0 The non-debug logic of the processor is not in reset state and has not been reset since the last time EDPRSR was read. 1 The non-debug logic.." "0,1" newline bitfld.long 0x4 2. "R,Core reset status bit. Possible values are: 0 The non-debug logic of the processor is not in reset state. 1 The non-debug logic of the processor is in reset state. This bit is.." "0,1" bitfld.long 0x4 1. "SPD,Sticky core power-down status bit.This bit is set to 1 on Cold reset to indicate the state of the debug registers has been lost. Since a Cold reset is required on powering up the processor this usually indicates the Core power domain has been.." "0,1" newline bitfld.long 0x4 0. "PU,Core power-up status bit. Indicates whether the Core power domain debug registers can be accessed: 0 Core is in a low-power or power-down state where the debug registers cannot be accessed. 1.." "0,1" group.long 0x400++0xB line.long 0x0 "APBADDR_DBG_CPU0_DBGBVR0_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR0_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR0_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU0_DBGBVR0_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR0_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR0_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU0_DBGBCR0_EL1,Debug Breakpoint Control Register 0" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR0_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR0_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR0_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x410++0xB line.long 0x0 "APBADDR_DBG_CPU0_DBGBVR1_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR1_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR1_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU0_DBGBVR1_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR1_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR1_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU0_DBGBCR1_EL1,Debug Breakpoint Control Register 1" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR1_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR1_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR1_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x420++0xB line.long 0x0 "APBADDR_DBG_CPU0_DBGBVR2_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR2_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR2_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU0_DBGBVR2_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR2_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR2_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU0_DBGBCR2_EL1,Debug Breakpoint Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR2_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR2_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR2_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x430++0xB line.long 0x0 "APBADDR_DBG_CPU0_DBGBVR3_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR3_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR3_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU0_DBGBVR3_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR3_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR3_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU0_DBGBCR3_EL1,Debug Breakpoint Control Register 3" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR3_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR3_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR3_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x440++0xB line.long 0x0 "APBADDR_DBG_CPU0_DBGBVR4_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR4_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR4_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU0_DBGBVR4_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR4_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR4_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU0_DBGBCR4_EL1,Debug Breakpoint Control Register 4" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR4_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR4_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR4_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x450++0xB line.long 0x0 "APBADDR_DBG_CPU0_DBGBVR5_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR5_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR5_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU0_DBGBVR5_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR5_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR5_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU0_DBGBCR5_EL1,Debug Breakpoint Control Register 5" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR5_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR5_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR5_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x800++0xB line.long 0x0 "APBADDR_DBG_CPU0_DBGWVR0_EL1_31_0,Debug Watchpoint Value Register 0" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR0_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU0_DBGWVR0_EL1_63_32,Debug Watchpoint Extended Value Register 0" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU0_DBGWCR0_EL1,Debug Watchpoint Control Register 0" bitfld.long 0x8 29.--31. "RES0_DBGWCR0_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR0_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0x810++0xB line.long 0x0 "APBADDR_DBG_CPU0_DBGWVR1_EL1_31_0,Debug Watchpoint Value Register 1" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR1_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU0_DBGWVR1_EL1_63_32,Debug Watchpoint Extended Value Register 1" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU0_DBGWCR1_EL1,Debug Watchpoint Control Register 1" bitfld.long 0x8 29.--31. "RES0_DBGWCR1_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR1_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0x820++0xB line.long 0x0 "APBADDR_DBG_CPU0_DBGWVR2_EL1_31_0,Debug Watchpoint Value Register 2" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR2_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU0_DBGWVR2_EL1_63_32,Debug Watchpoint Extended Value Register 2" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU0_DBGWCR2_EL1,Debug Watchpoint Control Register 2" bitfld.long 0x8 29.--31. "RES0_DBGWCR2_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR2_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0x830++0xB line.long 0x0 "APBADDR_DBG_CPU0_DBGWVR3_EL1_31_0,Debug Watchpoint Value Register 3" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR3_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU0_DBGWVR3_EL1_63_32,Debug Watchpoint Extended Value Register 3" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU0_DBGWCR3_EL1,Debug Watchpoint Control Register 3" bitfld.long 0x8 29.--31. "RES0_DBGWCR3_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR3_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0xD00++0x3 line.long 0x0 "APBADDR_DBG_CPU0_MIDR_EL1,Main ID Register" hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,The Implementer code. This field must hold an implementer code that has been assigned by ARM." hexmask.long.byte 0x0 20.--23. 1. "VARIANT,An IMPLEMENTATION DEFINED variant number. Typically this field is used to distinguish between different product variants or major revisions of a product." newline hexmask.long.byte 0x0 16.--19. 1. "ARCHITECTURE" hexmask.long.word 0x0 4.--15. 1. "PARTNUM,An IMPLEMENTATION DEFINED primary part number for the device. On processors implemented by ARM if the top four bits of the primary part number are 0x0 or 0x7 the variant and architecture are encoded differently" newline hexmask.long.byte 0x0 0.--3. 1. "REVISION,An IMPLEMENTATION DEFINED revision number for the device" group.long 0xD20++0x3F line.long 0x0 "APBADDR_DBG_CPU0_ID_AA64PFR0_EL1_31_0,Processor Feature Register 0 (low word)" hexmask.long.byte 0x0 28.--31. 1. "RES0_ID_AA64PFR0_EL1_31_0_31_28,Reserved RES0." hexmask.long.byte 0x0 24.--27. 1. "GIC,GIC system register interface. Permitted values are: 0000 No GIC system registers are supported. 0001 GICv3 system registers are supported. All other values are reserved." newline hexmask.long.byte 0x0 20.--23. 1. "ADVSIMD,Advanced SIMD. Permitted values are: 0000 Advanced SIMD is implemented. 1111 Advanced SIMD is not implemented. All other values are reserved." hexmask.long.byte 0x0 16.--19. 1. "FP,Floating-point. Permitted values are: 0000 Floating-point is implemented. 1111 Floating-point is not implemented. All other values are reserved." newline hexmask.long.byte 0x0 12.--15. 1. "EL3,EL3 exception level handling. Permitted values are: 0000 EL3 is not implemented. 0001 EL3 can be executed in AArch64 state only. 0010 EL3 can be executed.." hexmask.long.byte 0x0 8.--11. 1. "EL2,EL2 exception level handling. Permitted values are: 0000 EL2 is not implemented. 0001 EL2 can be executed in AArch64 state only. 0010 EL2 can be executed.." newline hexmask.long.byte 0x0 4.--7. 1. "EL1,EL1 exception level handling. Permitted values are: 0000 EL1 is not implemented. 0001 EL1 can be executed in AArch64 state only. 0010 EL1 can be executed.." hexmask.long.byte 0x0 0.--3. 1. "EL0,EL0 exception level handling. Permitted values are: 0000 EL0 is not implemented. 0001 EL0 can be executed in AArch64 state only. 0010 EL0 can be executed.." line.long 0x4 "APBADDR_DBG_CPU0_ID_AA64PFR0_EL1_63_32,Processor Feature Register 0 (high word)" hexmask.long 0x4 0.--31. 1. "RES0_ID_AA64PFR0_EL1_63_32_31_0,Reserved RES0." line.long 0x8 "APBADDR_DBG_CPU0_ID_AA64DFR0_EL1_31_0,Debug Feature Register 0 (low word)" hexmask.long.byte 0x8 28.--31. 1. "CTX_CMPS,Number of breakpoints that are context-aware minus 1. These are the highest numbered breakpoints." hexmask.long.byte 0x8 24.--27. 1. "RES0_ID_AA64DFR0_EL1_31_0_27_24,Reserved RES0." newline hexmask.long.byte 0x8 20.--23. 1. "WRPS,Number of watchpoints minus 1. The value of 0b0000 is reserved." hexmask.long.byte 0x8 16.--19. 1. "RES0_ID_AA64DFR0_EL1_31_0_19_16,Reserved RES0." newline hexmask.long.byte 0x8 12.--15. 1. "BRPS,Number of breakpoints minus 1. The value of 0b0000 is reserved." hexmask.long.byte 0x8 8.--11. 1. "PMUVER,Performance Monitors extension version. Indicates whether system register interface to Performance Monitors extension is implemented. Permitted values are: 0000 Performance Monitors extension system registers not implemented." newline hexmask.long.byte 0x8 4.--7. 1. "TRACEVER,Trace extension. Indicates whether system register interface to Trace extension is implemented. Permitted values are: 0000 Trace extension system registers not implemented. 0001 Trace.." hexmask.long.byte 0x8 0.--3. 1. "DEBUGVER,Debug architecture version. Indicates presence of v8-A debug architecture. 0110 v8-A debug architecture. All other values are reserved." line.long 0xC "APBADDR_DBG_CPU0_ID_AA64DFR0_EL1_63_32,Debug Feature Register 0 (high word)" hexmask.long 0xC 0.--31. 1. "RES0_ID_AA64DFR0_EL1_63_32_31_0,Reserved RES0." line.long 0x10 "APBADDR_DBG_CPU0_ID_AA64ISAR0_EL1_31_0,Instruction Set Attribute Register 0 (low word)" hexmask.long.word 0x10 20.--31. 1. "RES0_ID_AA64ISAR0_EL1_31_0_31_20,Reserved RES0." hexmask.long.byte 0x10 16.--19. 1. "CRC32,CRC32 instructions in AArch64. Possible values of this field are: 0000 No CRC32 instructions implemented. 0001 CRC32B CRC32H CRC32W CRC32X CRC32CB CRC32CH CRC32CW and CRC32CX.." newline hexmask.long.byte 0x10 12.--15. 1. "SHA2,SHA2 instructions in AArch64. Possible values of this field are: 0000 No SHA2 instructions implemented. 0001 SHA256H SHA256H2 SHA256SU0 and SHA256SU1 instructions implemented." hexmask.long.byte 0x10 8.--11. 1. "SHA1,SHA1 instructions in AArch64. Possible values of this field are: 0000 No SHA1 instructions implemented. 0001 SHA1C SHA1P SHA1M SHA1H SHA1SU0 and SHA1SU1 instructions implemented." newline hexmask.long.byte 0x10 4.--7. 1. "AES,AES instructions in AArch64. Possible values of this field are: 0000 No AES instructions implemented. 0001 AESE AESD AESMC and AESIMC instructions implemented. 0010.." hexmask.long.byte 0x10 0.--3. 1. "RES0_ID_AA64ISAR0_EL1_31_0_3_0,Reserved RES0." line.long 0x14 "APBADDR_DBG_CPU0_ID_AA64ISAR0_EL1_63_32,Instruction Set Attribute Register 0 (high word)" hexmask.long 0x14 0.--31. 1. "RES0_ID_AA64ISAR0_EL1_63_32_31_0,Reserved RES0." line.long 0x18 "APBADDR_DBG_CPU0_ID_AA64MMFR0_EL1_31_0,Memory Model Feature Register 0 (low word)" hexmask.long.byte 0x18 28.--31. 1. "TGRAN4,Support for 4 Kbyte memory translation granule size. Permitted values are: 0000 4 KB granule supported. 1111 4 KB granule not supported. All other values are reserved." hexmask.long.byte 0x18 24.--27. 1. "TGRAN64,Support for 64 Kbyte memory translation granule size. Permitted values are: 0000 64 KB granule supported. 1111 64 KB granule not supported. All other values are reserved." newline hexmask.long.byte 0x18 20.--23. 1. "TGRAN16,Support for 16 Kbyte memory translation granule size. Permitted values are: 0000 16 KB granule not supported. 0001 16 KB granule supported. All other values are reserved." hexmask.long.byte 0x18 16.--19. 1. "BIGENDEL0,Mixed-endian support at EL0 only. Permitted values are: 0000 No mixed-endian support at EL0. The SCTLR_EL1.E0E bit has a fixed value. 0001 Mixed-endian support at EL0. The SCTLR_EL1.E0E.." newline hexmask.long.byte 0x18 12.--15. 1. "SNSMEM,Secure versus Non-secure Memory distinction. Permitted values are: 0000 Does not support a distinction between Secure and Non-secure Memory. 0001 Does support a distinction between Secure.." hexmask.long.byte 0x18 8.--11. 1. "BIGEND,Mixed-endian configuration support. Permitted values are: 0000 No mixed-endian support. The SCTLR_ELx.EE bits have a fixed value. See the BigEndEL0 field bits[19:16] for whether EL0 supports mixed-endian." newline hexmask.long.byte 0x18 4.--7. 1. "ASIDBITS,Number of ASID bits. Permitted values are: 0000 8 bits. 0010 16 bits. All other values are reserved." hexmask.long.byte 0x18 0.--3. 1. "PARANGE,Physical Address range supported. Permitted values are: 0000 32 bits 4 GB. 0001 36 bits 64 GB. 0010 40 bits 1 TB. 0011.." line.long 0x1C "APBADDR_DBG_CPU0_ID_AA64MMFR0_EL1_63_32,Memory Model Feature Register 0 (high word)" hexmask.long 0x1C 0.--31. 1. "RES0_ID_AA64MMFR0_EL1_63_32_31_0,Reserved RES0." line.long 0x20 "APBADDR_DBG_CPU0_ID_AA64PFR1_EL1_31_0,Processor Feature Register 1 (low word)" hexmask.long 0x20 0.--31. 1. "RES0_ID_AA64PFR1_EL1_31_0_31_0,Reserved RES0." line.long 0x24 "APBADDR_DBG_CPU0_ID_AA64PFR1_EL1_63_32,Processor Feature Register 1 (high word)" hexmask.long 0x24 0.--31. 1. "RES0_ID_AA64PFR1_EL1_63_32_31_0,Reserved RES0." line.long 0x28 "APBADDR_DBG_CPU0_ID_AA64DFR1_EL1_31_0,Auxiliary Feature Register 1 (low word)" hexmask.long 0x28 0.--31. 1. "RES0_ID_AA64DFR1_EL1_31_0_31_0,Reserved RES0." line.long 0x2C "APBADDR_DBG_CPU0_ID_AA64DFR1_EL1_63_32,Auxiliary Feature Register 1 (high word)" hexmask.long 0x2C 0.--31. 1. "RES0_ID_AA64DFR1_EL1_63_32_31_0,Reserved RES0." line.long 0x30 "APBADDR_DBG_CPU0_ID_AA64ISAR1_EL1_31_0,Instruction Set Attribute Register 1 (low word)" hexmask.long 0x30 0.--31. 1. "RES0_ID_AA64ISAR1_EL1_31_0_31_0,Reserved RES0." line.long 0x34 "APBADDR_DBG_CPU0_ID_AA64ISAR1_EL1_63_32,Instruction Set Attribute Register 1 (high word)" hexmask.long 0x34 0.--31. 1. "RES0_ID_AA64ISAR1_EL1_63_32_31_0,Reserved RES0." line.long 0x38 "APBADDR_DBG_CPU0_ID_AA64MMFR1_EL1_31_0,Memory Model Feature Register 1 (low word)" hexmask.long 0x38 0.--31. 1. "RES0_ID_AA64MMFR1_EL1_31_0_31_0,Reserved RES0." line.long 0x3C "APBADDR_DBG_CPU0_ID_AA64MMFR1_EL1_63_32,Memory Model Feature Register 1 (high word)" hexmask.long 0x3C 0.--31. 1. "RES0_ID_AA64MMFR1_EL1_63_32_31_0,Reserved RES0." group.long 0xF00++0x3 line.long 0x0 "APBADDR_DBG_CPU0_EDITCTRL,External Debug Integration mode Control Register" hexmask.long 0x0 1.--31. 1. "RES0_EDITCTRL_31_1,Reserved RES0." bitfld.long 0x0 0. "IME,Integration mode enable. When IME == 1 the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED. 0 Normal operation." "0,1" group.long 0xFA0++0x33 line.long 0x0 "APBADDR_DBG_CPU0_DBGCLAIMSET_EL1,Debug Claim Tag Set Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_DBGCLAIMSET_EL1_31_8,Reserved RAZ/SBZ. Software can rely on these bits reading as zero and must use a should-be-zero policy on writes. Implementations must ignore writes." hexmask.long.byte 0x0 0.--7. 1. "CLAIM,Claim set bits. RAO.Writing a 1 to one of these bits sets the corresponding CLAIM bit to 1. This is an indirect write to the CLAIM bits.A single write operation can set multiple bits to 1. Writing 0 to one of these bits has no effect." line.long 0x4 "APBADDR_DBG_CPU0_DBGCLAIMCLR_EL1,Debug Claim Tag Clear Register" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_DBGCLAIMCLR_EL1_31_8,Reserved RAZ/SBZ. Software can rely on these bits reading as zero and must use a should-be-zero policy on writes. Implementations must ignore writes." hexmask.long.byte 0x4 0.--7. 1. "CLAIM,Claim clear bits. Reading this field returns the current value of the CLAIM bits.Writing a 1 to one of these bits clears the corresponding CLAIM bit to 0. This is an indirect write to the CLAIM bits.A single write operation can clear multiple bits.." line.long 0x8 "APBADDR_DBG_CPU0_EDDEVAFF0,External Debug Device Affinity Register 0" hexmask.long 0x8 0.--31. 1. "EDDEVAFF0,MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0xC "APBADDR_DBG_CPU0_EDDEVAFF1,External Debug Device Affinity Register 1" hexmask.long 0xC 0.--31. 1. "EDDEVAFF1,MPIDR_EL1 high half. Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x10 "APBADDR_DBG_CPU0_EDLAR,External Debug Lock Access Register" hexmask.long 0x10 0.--31. 1. "KEY,Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register locks the lock disabling write.." line.long 0x14 "APBADDR_DBG_CPU0_EDLSR,External Debug Lock Status Register" hexmask.long 0x14 3.--31. 1. "RES0_EDLSR_31_3,Reserved RES0." bitfld.long 0x14 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" newline bitfld.long 0x14 1. "SLK,Software lock status for this component. For an access to LSR that is not a memory-mapped access or when the software lock is not implemented this field is RES0.For memory-mapped accesses when the software lock is implemented possible values of.." "0,1" bitfld.long 0x14 0. "SLI,Software lock implemented. For an access to LSR that is not a memory-mapped access this field is RAZ. For memory-mapped accesses the value of this field is IMPLEMENTATION DEFINED. Permitted values are: 0 Software lock not.." "0,1" line.long 0x18 "APBADDR_DBG_CPU0_DBGAUTHSTATUS_EL1,Debug Authentication Status register" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_DBGAUTHSTATUS_EL1_31_8,Reserved RES0." bitfld.long 0x18 6.--7. "SNID,Secure non-invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Non-secure. 10 Implemented and disabled." "0,1,2,3" newline bitfld.long 0x18 4.--5. "SID,Secure invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Non-secure. 10 Implemented and disabled." "0,1,2,3" bitfld.long 0x18 2.--3. "NSNID,Non-secure non-invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Secure. 10 Implemented and disabled." "0,1,2,3" newline bitfld.long 0x18 0.--1. "NSID,Non-secure invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Secure. 10 Implemented and disabled." "0,1,2,3" line.long 0x1C "APBADDR_DBG_CPU0_EDDEVARCH,External Debug Device Architecture Register" hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For debug this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A." "0,1" newline hexmask.long.byte 0x1C 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For debug the revision defined by v8-A is 0x0.All other values are reserved." hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For debug:Bits [15:12] are the architecture version 0x6.Bits [11:0] are the architecture part number 0xA15.This corresponds to debug.." line.long 0x20 "APBADDR_DBG_CPU0_EDDEVID2,External Debug Device ID Register 2" hexmask.long 0x20 0.--31. 1. "RES0_EDDEVID2_31_0,Reserved RES0." line.long 0x24 "APBADDR_DBG_CPU0_EDDEVID1,External Debug Device ID Register 1" hexmask.long 0x24 4.--31. 1. "RES0_EDDEVID1_31_4,Reserved RES0." hexmask.long.byte 0x24 0.--3. 1. "PCSROFFSET,This field indicates the offset applied to PC samples returned by reads of EDPCSR. Permitted values of this field in v8-A are: 0000 EDPCSR not implemented. 0010 EDPCSR implemented and.." line.long 0x28 "APBADDR_DBG_CPU0_EDDEVID,External Debug Device ID Register 0" hexmask.long.byte 0x28 28.--31. 1. "RES0_EDDEVID_31_28,Reserved RES0." hexmask.long.byte 0x28 24.--27. 1. "AUXREGS,Indicates support for Auxiliary registers. Permitted values for this field are: 0000 None supported. 0001 Support for External Debug Auxiliary Control Register EDACR. All.." newline hexmask.long.tbyte 0x28 4.--23. 1. "RES0_EDDEVID_23_4,Reserved RES0." hexmask.long.byte 0x28 0.--3. 1. "PCSAMPLE,Indicates the level of Sample-based profiling support using external debug registers 40 through 43. Permitted values of this field in v8-A are: 0000 Architecture-defined form of Sample-based profiling not implemented." line.long 0x2C "APBADDR_DBG_CPU0_EDDEVTYPE,External Debug Device Type Register" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_EDDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x2C 4.--7. 1. "SUB,Subtype. Must read as 0x1 to indicate this is a processor component." newline hexmask.long.byte 0x2C 0.--3. 1. "MAJOR,Major type. Must read as 0x5 to indicate this is a debug logic component." line.long 0x30 "APBADDR_DBG_CPU0_EDPIDR4,External Debug Peripheral Identification Register 4" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_EDPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x30 4.--7. 1. "SIZE,Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers." newline hexmask.long.byte 0x30 0.--3. 1. "DES_2,Designer JEP106 continuation code least significant nibble. For ARM Limited this field is 0b0100." group.long 0xFE0++0x1F line.long 0x0 "APBADDR_DBG_CPU0_EDPIDR0,External Debug Peripheral Identification Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_EDPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x0 0.--7. 1. "PART_0,Part number least significant byte." line.long 0x4 "APBADDR_DBG_CPU0_EDPIDR1,External Debug Peripheral Identification Register 1" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_EDPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x4 4.--7. 1. "DES_0,Designer least significant nibble of JEP106 ID code. For ARM Limited this field is 0b1011." newline hexmask.long.byte 0x4 0.--3. 1. "PART_1,Part number most significant nibble." line.long 0x8 "APBADDR_DBG_CPU0_EDPIDR2,External Debug Peripheral Identification Register 2" hexmask.long.tbyte 0x8 8.--31. 1. "RES0_EDPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x8 4.--7. 1. "REVISION,Part major revision. Parts can also use this field to extend Part number to 16-bits." newline bitfld.long 0x8 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" bitfld.long 0x8 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0xC "APBADDR_DBG_CPU0_EDPIDR3,External Debug Peripheral Identification Register 3" hexmask.long.tbyte 0xC 8.--31. 1. "RES0_EDPIDR3_31_8,Reserved RES0." hexmask.long.byte 0xC 4.--7. 1. "REVAND,Part minor revision. Parts using EDPIDR2.REVISION as an extension to the Part number must use this field as a major revision number." newline hexmask.long.byte 0xC 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x10 "APBADDR_DBG_CPU0_EDCIDR0,External Debug Component Identification Register 0" hexmask.long.tbyte 0x10 8.--31. 1. "RES0_EDCIDR0_31_8,Reserved RES0." hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x14 "APBADDR_DBG_CPU0_EDCIDR1,External Debug Component Identification Register 1" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_EDCIDR1_31_8,Reserved RES0." hexmask.long.byte 0x14 4.--7. 1. "CLASS,Component class. Reads as 0x9 debug component." newline hexmask.long.byte 0x14 0.--3. 1. "PRMBL_1,Preamble. RAZ." line.long 0x18 "APBADDR_DBG_CPU0_EDCIDR2,External Debug Component Identification Register 2" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDCIDR2_31_8,Reserved RES0." hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x1C "APBADDR_DBG_CPU0_EDCIDR3,External Debug Component Identification Register 3" hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_EDCIDR3_31_8,Reserved RES0." hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree "A53SS0_CORE0_ECC_AGGR" base ad:0x718400 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_CORE0_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_CORE0_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_CORE0_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR_CORE0_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_CORE0_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_CORE0_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 26. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 25. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 24. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 23. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_CORE0_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 26. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_CORE0_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 26. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_CORE0_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_CORE0_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 26. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 25. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 24. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 23. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_CORE0_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 26. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_CORE0_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 26. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_CORE0_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_CORE0_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_CORE0_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_CORE0_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "A53SS0_CORE0_ETM" base ad:0x730040000 group.long 0x4++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCPRGCTLR,Programming Control Register" hexmask.long 0x0 1.--31. 1. "RES0_TRCPRGCTLR_31_1,Reserved RES0." bitfld.long 0x0 0. "EN,Trace unit enable bit. Possible values are: 0 The trace unit is disabled. All trace resources are inactive and no trace is generated. 1 The trace unit is enabled." "0,1" group.long 0xC++0x7 line.long 0x0 "APBADDR_ETM_CPU0_TRCSTATR,Status Register" hexmask.long 0x0 2.--31. 1. "RES0_TRCSTATR_31_2,Reserved RES0." bitfld.long 0x0 1. "PMSTABLE,Programmer's model stable bit: 0 The programmer's model is not stable. 1 The programmer's model is stable. When polled the trace unit trace registers return stable data." "0,1" bitfld.long 0x0 0. "IDLE,Idle status bit: 0 The trace unit is not idle. 1 The trace unit is idle. The trace unit is idle when all of the following are true:TRCPRGCTLR.EN==0 or the OS Lock is.." "0,1" line.long 0x4 "APBADDR_ETM_CPU0_TRCCONFIGR,Trace Configuration Register" hexmask.long.word 0x4 18.--31. 1. "RES0_TRCCONFIGR_31_18,Reserved RES0." bitfld.long 0x4 17. "DV,Data value tracing bit: 0 Data value tracing is disabled. 1 Data value tracing is enabled when INSTP0 is not 0b00. TRCIDR0.TRCDATA indicates whether this bit is supported. If.." "0,1" bitfld.long 0x4 16. "DA,Data address tracing bit: 0 Data address tracing is disabled. 1 Data address tracing is enabled when INSTP0 is not 0b00. TRCIDR0.TRCDATA indicates whether this bit is.." "0,1" newline bitfld.long 0x4 15. "RES0_TRCCONFIGR_15_15,Reserved RES0." "0,1" bitfld.long 0x4 13.--14. "QE,Q element enable field: 00 Q elements are disabled. 01 Q elements with instruction counts are enabled. Q elements without instruction counts are disabled. 11.." "0,1,2,3" bitfld.long 0x4 12. "RS,Return stack enable bit. 0 Return stack is disabled. 1 Return stack is enabled. TRCIDR0.RETSTACK indicates whether this bit is supported. If it is not supported then this bit.." "0,1" newline bitfld.long 0x4 11. "TS,Global timestamp tracing bit: 0 Global timestamp tracing is disabled. 1 Global timestamp tracing is enabled. TRCTSCTLR controls the insertion of timestamps in the trace." "0,1" bitfld.long 0x4 8.--10. "COND,Conditional instruction tracing bit. The permitted values are: 000 Conditional instruction tracing is disabled. 001 Conditional load instructions are traced. 010.." "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "VMID,VMID tracing bit: 0 VMID tracing is disabled. 1 VMID tracing is enabled. TRCIDR2.VMIDSIZE indicates whether this bit is supported. If it is not supported then this bit is RES0." "0,1" newline bitfld.long 0x4 6. "CID,Context ID tracing bit: 0 Context ID tracing is disabled. 1 Context ID tracing is enabled. TRCIDR2.CIDSIZE indicates whether this bit is supported. If it is not supported then.." "0,1" bitfld.long 0x4 5. "RES0_TRCCONFIGR_5_5,Reserved RES0." "0,1" bitfld.long 0x4 4. "CCI,Cycle counting instruction trace bit: 0 Cycle counting in the instruction trace is disabled. 1 Cycle counting in the instruction trace is enabled. TRCCCCTLR controls the threshold value for.." "0,1" newline bitfld.long 0x4 3. "BB,Branch broadcast mode bit: 0 Branch broadcast mode is disabled. 1 Branch broadcast mode is enabled. TRCBBCTLR controls which regions of memory are enabled to use branch broadcasting." "0,1" bitfld.long 0x4 1.--2. "INSTP0,Instruction P0 bit. This field controls whether load and store instructions are traced as P0 instructions: 00 Do not trace load and store instructions as P0 instructions. 01 Trace load.." "0,1,2,3" bitfld.long 0x4 0. "RES1_TRCCONFIGR_0_0,Reserved RES1." "0,1" group.long 0x18++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCAUXCTLR,Auxiliary Control Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_TRCAUXCTLR_31_8,Reserved RES0" bitfld.long 0x0 7. "COREIFEN,Keep core interface enabled regardless of trace enable register state" "0,1" bitfld.long 0x0 6. "RES0_TRCAUXCTLR_6_6,Reserved RES0" "0,1" newline bitfld.long 0x0 5. "AUTHNOFLUSH,Do not flush trace on de-assertion of authentication inputs. When this bit is set to 1 the trace unit behavior deviates from architecturally-specified behavior." "0,1" bitfld.long 0x0 4. "TSNODELAY,Do not delay timestamp insertion based on FIFO depth." "0,1" bitfld.long 0x0 3. "SYNCDELAY,Delay periodic synchronization if FIFO is more than half-full." "0,1" newline bitfld.long 0x0 2. "OVFLW,Force an overflow if synchronization is not completed when second synchronization becomes due. When this bit is set to 1 the trace unit behavior deviates from architecturally-specified behavior." "0,1" bitfld.long 0x0 1. "IDLEACK,Force idle-drain acknowledge high CPU does not wait for trace to drain before entering WFX state. When this bit is set to 1 trace unit behavior deviates from architecturally-specified behavior." "0,1" bitfld.long 0x0 0. "AFREADY,Always respond to AFREADY immediately. Does not have any interaction with FIFO draining even in WFI state." "0,1" group.long 0x20++0x7 line.long 0x0 "APBADDR_ETM_CPU0_TRCEVENTCTL0R,Event Control 0 Register" bitfld.long 0x0 31. "TYPE3,Selects the resource type for trace event 3" "0,1" bitfld.long 0x0 28.--30. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--27. 1. "SEL3,Selects the resource number based on the value of TYPE3" newline bitfld.long 0x0 23. "TYPE2,Selects the resource type for trace event 2" "0,1" bitfld.long 0x0 20.--22. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--19. 1. "SEL2,Selects the resource number based on the value of TYPE2" newline bitfld.long 0x0 15. "TYPE1,Selects the resource type for trace event 1" "0,1" bitfld.long 0x0 12.--14. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "SEL1,Selects the resource number based on the value of TYPE1" newline bitfld.long 0x0 7. "TYPE0,Selects the resource type for trace event 0" "0,1" bitfld.long 0x0 4.--6. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "SEL0,Selects the resource number based on the value of TYPE0" line.long 0x4 "APBADDR_ETM_CPU0_TRCEVENTCTL1R,Event Control 1 Register" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved RES0" bitfld.long 0x4 12. "LPOVERRIDE,Low power state behavior override" "0,1" bitfld.long 0x4 11. "ATB,ATB trigger enable" "0,1" newline hexmask.long.byte 0x4 4.--10. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "EN,One bit per event to enable generation of an event element in the instruction trace stream when the selected event occurs" group.long 0x2C++0x17 line.long 0x0 "APBADDR_ETM_CPU0_TRCSTALLCTLR,Stall Control Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved RES0" bitfld.long 0x0 8. "ISTALL,Controls if the trace unit can stall the processor when the instruction trace buffer space is less than LEVEL" "0,1" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved RES0" newline bitfld.long 0x0 2.--3. "LEVEL,The field can support 4 monotonic levels from 0b00 to 0b11" "0,1,2,3" bitfld.long 0x0 0.--1. "RESERVED,Reserved RES0" "0,1,2,3" line.long 0x4 "APBADDR_ETM_CPU0_TRCTSCTLR,Global Timestamp Control Register" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_TRCTSCTLR_31_8,Reserved RES0." hexmask.long.byte 0x4 0.--7. 1. "EVENT,An event selector. When the selected event is triggered the trace unit inserts a global timestamp into the trace streams." line.long 0x8 "APBADDR_ETM_CPU0_TRCSYNCPR,Synchronization Period Register" hexmask.long 0x8 5.--31. 1. "RES0_TRCSYNCPR_31_5,Reserved RES0." hexmask.long.byte 0x8 0.--4. 1. "PERIOD,Controls how many bytes of trace the sum of instruction and data that a trace unit can generate before a periodic trace synchronization request occurs. The number of bytes is always a power of two and the permitted values are: 00000.." line.long 0xC "APBADDR_ETM_CPU0_TRCCCCTLR,Cycle Count Control Register" hexmask.long.tbyte 0xC 12.--31. 1. "RES0_TRCCCCTLR_31_12,Reserved RES0." hexmask.long.word 0xC 0.--11. 1. "THRESHOLD,Sets the threshold value for instruction trace cycle counting.The minimum threshold value that can be programmed into THRESHOLD is given in TRCIDR3.CCITMIN.Writing a value of zero might cause UNPREDICTABLE behaviour." line.long 0x10 "APBADDR_ETM_CPU0_TRCBBCTLR,Branch Broadcast Control Register" hexmask.long.tbyte 0x10 9.--31. 1. "RES0_TRCBBCTLR_31_9,Reserved RES0." bitfld.long 0x10 8. "MODE,Mode bit: 0 Exclude mode. Branch broadcasting is not enabled in the address range that RANGE defines. If RANGE==0 then branch broadcasting is enabled for the entire memory map. 1 Include mode." "0,1" hexmask.long.byte 0x10 0.--7. 1. "RANGE,Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each bit represents an address range comparator pair so bit[n] controls the selection of address range comparator pair n. If bit[n] is: 0.." line.long 0x14 "APBADDR_ETM_CPU0_TRCTRACEIDR,Trace ID Register" hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x14 0.--6. 1. "TRACEID,Trace ID value. When only instruction tracing is enabled this provides the trace ID." group.long 0x80++0xB line.long 0x0 "APBADDR_ETM_CPU0_TRCVICTLR,ViewInst Main Control Register" hexmask.long.byte 0x0 24.--31. 1. "RES0_TRCVICTLR_31_24,Reserved RES0." hexmask.long.byte 0x0 20.--23. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Non-secure state for exception level n." hexmask.long.byte 0x0 16.--19. 1. "EXLEVEL_S,In Secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Secure state for exception level n. 1.." newline hexmask.long.byte 0x0 12.--15. 1. "RES0_TRCVICTLR_15_12,Reserved RES0." bitfld.long 0x0 11. "TRCERR,If TRCIDR3.TRCERR==1 this bit controls whether a trace unit must trace a system error exception: 0 The trace unit does not trace a system error exception unless it traces the exception or instruction immediately prior to the.." "0,1" bitfld.long 0x0 10. "TRCRESET,Controls whether a trace unit must trace a Reset exception: 0 The trace unit does not trace a Reset exception unless it traces the exception or instruction immediately prior to the Reset exception. 1.." "0,1" newline bitfld.long 0x0 9. "SSSTATUS,IF TRCIDR4.NUMACPAIRS>0 or TRCIDR.NUMPC>0 this bit returns the status of the start-stop logic: 0 The start-stop logic is in the stopped state. 1 The start-stop logic is in the started.." "0,1" bitfld.long 0x0 8. "RES0_TRCVICTLR_8_8,Reserved RES0." "0,1" hexmask.long.byte 0x0 0.--7. 1. "EVENT,An event selector. [TODO: Add the bit assignments for EVENT fields into the descriptions directly?]" line.long 0x4 "APBADDR_ETM_CPU0_TRCVIIECTLR,ViewInst Include-Exclude Control Register" hexmask.long.byte 0x4 24.--31. 1. "RES0_TRCVIIECTLR_31_24,Reserved RES0." hexmask.long.byte 0x4 16.--23. 1. "EXCLUDE,0 1 The implemented width of the field n is IMPLEMENTATION DEFINED and is set by the value of TRCIDR4.NUMACPAIRS. Unimplemented bits are RAZ/WI." hexmask.long.byte 0x4 8.--15. 1. "RES0_TRCVIIECTLR_15_8,Reserved RES0." newline hexmask.long.byte 0x4 0.--7. 1. "INCLUDE,Include range field. Selects which address range comparator pairs are in use with ViewInst include control. Each bit represents an address range comparator pair so bit[m] controls the selection of address range comparator pair m. If bit[m] is:.." line.long 0x8 "APBADDR_ETM_CPU0_TRCVISSCTLR,ViewInst Start-Stop Control Register" hexmask.long.word 0x8 16.--31. 1. "STOP,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of stopping trace. Each bit represents a single address comparator so bit[m] controls the selection of single address comparator m-16. If bit[m].." hexmask.long.word 0x8 0.--15. 1. "START,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of starting trace. Each bit represents a single address comparator so bit[n] controls the selection of single address comparator n. If bit[n] is:.." group.long 0x100++0xB line.long 0x0 "APBADDR_ETM_CPU0_TRCSEQEVR0,Sequencer State Transition Control Registers 0" hexmask.long.word 0x0 16.--31. 1. "RES0_TRCSEQEVR0_31_16,Reserved RES0." hexmask.long.byte 0x0 8.--15. 1. "B_N,Backward field. Contains an event number. When the event occurs then the sequencer state moves from state n+1 to state n.For example for TRCSEQEVR2 if B2==0x14 then when event 0x14 occurs the sequencer moves from state 3 to state 2." hexmask.long.byte 0x0 0.--7. 1. "F_N,Forward field. Contains an event number. When the event occurs then the sequencer state moves from state n to state n+1.For example for TRCSEQEVR1 if F1==0x12 then when event 0x12 occurs the sequencer moves from state 1 to state 2." line.long 0x4 "APBADDR_ETM_CPU0_TRCSEQEVR1,Sequencer State Transition Control Registers 1" hexmask.long.word 0x4 16.--31. 1. "RES0_TRCSEQEVR1_31_16,Reserved RES0." hexmask.long.byte 0x4 8.--15. 1. "B_N,Backward field. Contains an event number. When the event occurs then the sequencer state moves from state n+1 to state n.For example for TRCSEQEVR2 if B2==0x14 then when event 0x14 occurs the sequencer moves from state 3 to state 2." hexmask.long.byte 0x4 0.--7. 1. "F_N,Forward field. Contains an event number. When the event occurs then the sequencer state moves from state n to state n+1.For example for TRCSEQEVR1 if F1==0x12 then when event 0x12 occurs the sequencer moves from state 1 to state 2." line.long 0x8 "APBADDR_ETM_CPU0_TRCSEQEVR2,Sequencer State Transition Control Registers 2" hexmask.long.word 0x8 16.--31. 1. "RES0_TRCSEQEVR2_31_16,Reserved RES0." hexmask.long.byte 0x8 8.--15. 1. "B_N,Backward field. Contains an event number. When the event occurs then the sequencer state moves from state n+1 to state n.For example for TRCSEQEVR2 if B2==0x14 then when event 0x14 occurs the sequencer moves from state 3 to state 2." hexmask.long.byte 0x8 0.--7. 1. "F_N,Forward field. Contains an event number. When the event occurs then the sequencer state moves from state n to state n+1.For example for TRCSEQEVR1 if F1==0x12 then when event 0x12 occurs the sequencer moves from state 1 to state 2." group.long 0x118++0xB line.long 0x0 "APBADDR_ETM_CPU0_TRCSEQRSTEVR,Sequencer Reset Control Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_TRCSEQRSTEVR_31_8,Reserved RES0." hexmask.long.byte 0x0 0.--7. 1. "RST,Contains an event number. When the event occurs then the sequencer state moves to state 0." line.long 0x4 "APBADDR_ETM_CPU0_TRCSEQSTR,Sequencer State Register" hexmask.long 0x4 2.--31. 1. "RES0_TRCSEQSTR_31_2,Reserved RES0." bitfld.long 0x4 0.--1. "STATE,Sets or returns the state of the sequencer: 00 State 0. 01 State 1. 10 State 2. 11 State 3." "0,1,2,3" line.long 0x8 "APBADDR_ETM_CPU0_TRCEXTINSELR,External Input Select Register" bitfld.long 0x8 29.--31. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "SEL3,Selects an event from the external input bus for External Input Resource 3." bitfld.long 0x8 21.--23. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 16.--20. 1. "SEL2,Selects an event from the external input bus for External Input Resource 2" bitfld.long 0x8 13.--15. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--12. 1. "SEL1,Selects an event from the external input bus for External Input Resource 1" newline bitfld.long 0x8 5.--7. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--4. 1. "SEL0,Selects an event from the external input bus for External Input Resource 0" group.long 0x140++0x7 line.long 0x0 "APBADDR_ETM_CPU0_TRCCNTRLDVR0,Counter Reload Value Registers 0" hexmask.long.word 0x0 16.--31. 1. "RES0_TRCCNTRLDVR0_31_16,Reserved RES0." hexmask.long.word 0x0 0.--15. 1. "VALUE_N,Contains the reload value for counter . When a reload event occurs for counter then the trace unit copies the VALUE field into counter ." line.long 0x4 "APBADDR_ETM_CPU0_TRCCNTRLDVR1,Counter Reload Value Registers 1" hexmask.long.word 0x4 16.--31. 1. "RES0_TRCCNTRLDVR1_31_16,Reserved RES0." hexmask.long.word 0x4 0.--15. 1. "VALUE_N,Contains the reload value for counter . When a reload event occurs for counter then the trace unit copies the VALUE field into counter ." group.long 0x150++0x7 line.long 0x0 "APBADDR_ETM_CPU0_TRCCNTCTLR0,Counter Control Register 0" hexmask.long.word 0x0 18.--31. 1. "RES0_TRCCNTCTLR0_31_18,Reserved RES0." bitfld.long 0x0 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter decrements when a reload event occurs for counter : 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit.." "0,1" bitfld.long 0x0 16. "RLDSELF_N,Controls whether a reload event occurs for counter when counter reaches zero: 0 The trace unit does not generate a reload event. 1 The trace unit generates a reload event for.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter ." hexmask.long.byte 0x0 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter to decrement." line.long 0x4 "APBADDR_ETM_CPU0_TRCCNTCTLR1,Counter Control Register 1" hexmask.long.word 0x4 18.--31. 1. "RES0_TRCCNTCTLR1_31_18,Reserved RES0." bitfld.long 0x4 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter decrements when a reload event occurs for counter : 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit.." "0,1" bitfld.long 0x4 16. "RLDSELF_N,Controls whether a reload event occurs for counter when counter reaches zero: 0 The trace unit does not generate a reload event. 1 The trace unit generates a reload event for.." "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter ." hexmask.long.byte 0x4 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter to decrement." group.long 0x160++0x7 line.long 0x0 "APBADDR_ETM_CPU0_TRCCNTVR0,Counter Value Registers 0" hexmask.long.word 0x0 16.--31. 1. "RES0_TRCCNTVR0_31_16,Reserved RES0." hexmask.long.word 0x0 0.--15. 1. "VALUE_N,Contains the count value of counter ." line.long 0x4 "APBADDR_ETM_CPU0_TRCCNTVR1,Counter Value Registers 1" hexmask.long.word 0x4 16.--31. 1. "RES0_TRCCNTVR1_31_16,Reserved RES0." hexmask.long.word 0x4 0.--15. 1. "VALUE_N,Contains the count value of counter ." group.long 0x180++0x17 line.long 0x0 "APBADDR_ETM_CPU0_TRCIDR8,ID Register 8" hexmask.long 0x0 0.--31. 1. "MAXSPEC,Indicates the maximum speculation depth of the instruction trace stream. This is the maximum number of P0 elements in the trace stream that can be speculative at any time." line.long 0x4 "APBADDR_ETM_CPU0_TRCIDR9,ID Register 9" hexmask.long 0x4 0.--31. 1. "NUMP0KEY,Indicates the number of P0 right-hand keys that the trace unit can use. A value of 0 or 1 indicates one P0 key." line.long 0x8 "APBADDR_ETM_CPU0_TRCIDR10,ID Register 10" hexmask.long 0x8 0.--31. 1. "NUMP1KEY,Indicates the number of P1 right-hand keys that the trace unit can use. The number includes normal and special keys." line.long 0xC "APBADDR_ETM_CPU0_TRCIDR11,ID Register 11" hexmask.long 0xC 0.--31. 1. "NUMP1SPC,Indicates the number of special P1 right-hand keys that the trace unit can use." line.long 0x10 "APBADDR_ETM_CPU0_TRCIDR12,ID Register 12" hexmask.long 0x10 0.--31. 1. "NUMCONDKEY,Indicates the number of conditional instruction right-hand keys that the trace unit can use. The number includes normal and special keys." line.long 0x14 "APBADDR_ETM_CPU0_TRCIDR13,ID Register 13" hexmask.long 0x14 0.--31. 1. "NUMCONDSPC,Indicates the number of special conditional instruction right-hand keys that the trace unit can use." group.long 0x1C0++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCIMSPEC0,Implementation Specific Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_TRCIMSPEC0_31_8,Reserved RES0." hexmask.long.byte 0x0 4.--7. 1. "EN,If SUPPORT is not 0b0000 controls whether the IMPLEMENTATION DEFINED features are enabled. The permitted values are: 0000 The IMPLEMENTATION DEFINED features are not enabled. The trace unit must behave as if the IMPLEMENTATION.." hexmask.long.byte 0x0 0.--3. 1. "SUPPORT,Indicates whether the implementation supports IMPLEMENTATION DEFINED features. The permitted values are: 0000 No IMPLEMENTATION DEFINED features are supported. The EN field is RES0. and any other value which.." group.long 0x1E0++0x17 line.long 0x0 "APBADDR_ETM_CPU0_TRCIDR0,ID Register 0" bitfld.long 0x0 30.--31. "RES0_TRCIDR0_31_30,Reserved RES0." "0,1,2,3" bitfld.long 0x0 29. "COMMOPT,Conditional instruction tracing support bit. Indicates if the trace unit supports conditional instruction tracing: 0 Conditional instruction tracing is not supported. 1 Conditional.." "0,1" hexmask.long.byte 0x0 24.--28. 1. "TSSIZE,Global timestamp size field. The permitted values are: 00000 Global timestamping is not implemented. 00110 Implementation supports a maximum global timestamp of 48bits." newline hexmask.long.byte 0x0 17.--23. 1. "RES0_TRCIDR0_23_17,Reserved RES0." bitfld.long 0x0 15.--16. "QSUPP,Q element support field. The permitted values are: 00 Q element support is not implemented. TRCCONFIGR.QE is RES0. 01 Q element support is implemented and only supports Q elements with.." "0,1,2,3" bitfld.long 0x0 14. "QFILT,Q element filtering support field. The permitted values are: 0 Q element filtering is not implemented. 1 Q element filtering is implemented. TRCQCTLR is implemented. When.." "0,1" newline bitfld.long 0x0 12.--13. "CONDTYPE,Conditional tracing field. The permitted values are: 00 The trace unit indicates only if a conditional instruction is a pass or fail. 01 The trace unit provides the Current Program Status.." "0,1,2,3" bitfld.long 0x0 10.--11. "NUMEVENT,Number of events field. Indicates how many events the trace unit supports: 00 The trace unit supports 1 event. 01 The trace unit supports 2 events. 10.." "0,1,2,3" bitfld.long 0x0 9. "RETSTACK,Return stack bit. Indicates if the implementation supports a return stack: 0 Return stack is not implemented. 1 Return stack is implemented so TRCCONFIGR.RS is supported." "0,1" newline bitfld.long 0x0 8. "RES0_TRCIDR0_8_8,Reserved RES0." "0,1" bitfld.long 0x0 7. "TRCCCI,Cycle counting instruction bit. Indicates if the trace unit supports cycle counting for instructions: 0 Cycle counting in the instruction trace is not implemented. 1 Cycle counting in the.." "0,1" bitfld.long 0x0 6. "TRCCOND,Conditional instruction tracing support bit. Indicates if the trace unit supports conditional instruction tracing: 0 Conditional instruction tracing is not supported. 1 Conditional.." "0,1" newline bitfld.long 0x0 5. "TRCBB,Branch broadcast tracing support bit. Indicates if the trace unit supports branch broadcast tracing: 0 Branch broadcast tracing is not supported. 1 Branch broadcast tracing is supported so.." "0,1" bitfld.long 0x0 3.--4. "TRCDATA,Conditional tracing field. The permitted values are: 00 Data tracing is not supported. 11 Tracing of data addresses and data values is supported so TRCCONFIGR.DA TRCCONFIGR.DV .." "0,1,2,3" bitfld.long 0x0 1.--2. "INSTP0,P0 tracing support field. The permitted values are: 00 Tracing of load and store instructions as P0 elements is not supported. 11 Tracing of load and store instructions as P0 elements is.." "0,1,2,3" newline bitfld.long 0x0 0. "RES0_TRCIDR0_0_0,Reserved RES0." "0,1" line.long 0x4 "APBADDR_ETM_CPU0_TRCIDR1,ID Register 1" hexmask.long.byte 0x4 24.--31. 1. "DESIGNER,Indicates which company designed the trace unit. The permitted values are: 01000001 ARM Limited. 01000100 Digital Equipment Corporation. 01001101.." hexmask.long.byte 0x4 16.--23. 1. "RES0_TRCIDR1_23_16,Reserved RES0." hexmask.long.byte 0x4 12.--15. 1. "RES1_TRCIDR1_15_12,Reserved RES1." newline hexmask.long.byte 0x4 8.--11. 1. "TRCARCHMAJ,Indicates the major version of the ETM architecture. The permitted value is: 100 ETMv4. All other values are reserved." hexmask.long.byte 0x4 4.--7. 1. "TRCARCHMIN,Indicates the minor version of the ETM architecture. The permitted value is: 0 ETMv4 minor version 0. All other values are reserved." hexmask.long.byte 0x4 0.--3. 1. "REVISION,Returns an IMPLEMENTATION DEFINED value that identifies the revision of the trace registers and the OS Save and Restore registers.ARM recommends:That the initial implementation sets REVISION==0x0 and the field then increments for any subsequent.." line.long 0x8 "APBADDR_ETM_CPU0_TRCIDR2,ID Register 2" bitfld.long 0x8 29.--31. "RES0_TRCIDR2_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 25.--28. 1. "CCSIZE,Indicates the size of the cycle counter in bits minus 12. 0000 The cycle counter is 12 bits in length. 0001 The cycle counter is 13 bits in length. and so on up to 0b1000 .." hexmask.long.byte 0x8 20.--24. 1. "DVSIZE,Indicates the data value size in bytes. The permitted values are: 00000 Data value tracing is not supported. Therefore an implementation must also set TRCIDR0.TRCDATA==0b00. 00100 Maximum.." newline hexmask.long.byte 0x8 15.--19. 1. "DASIZE,Indicates the data address size in bytes. The permitted values are: 00000 Data address tracing is not supported. Therefore an implementation must also set TRCIDR0.TRCDATA==0b00. 00100.." hexmask.long.byte 0x8 10.--14. 1. "VMIDSIZE,Indicates the VMID size. The permitted values are: 00000 VMID tracing is not supported. 00001 Maximum of 8-bit VMID size so TRCCONFIGR.VMID is supported. All other.." hexmask.long.byte 0x8 5.--9. 1. "CIDSIZE,Indicates the Context ID size. The permitted values are: 00000 Context ID tracing is not supported. 00100 Maximum of 32-bit Context ID size so TRCCONFIGR.CID is supported." newline hexmask.long.byte 0x8 0.--4. 1. "IASIZE,Indicates the instruction address size. The permitted values are: 00100 Maximum of 32-bit address size. 01000 Maximum of 64-bit address size. All other values are reserved." line.long 0xC "APBADDR_ETM_CPU0_TRCIDR3,ID Register 3" bitfld.long 0xC 31. "NOOVERFLOW,Indicates if TRCSTALLCTLR.NOOVERFLOW is supported: 0 TRCSTALLCTLR.NOOVERFLOW is not supported or STALLCTL==0. 1 TRCSTALLCTLR.NOOVERFLOW is supported." "0,1" bitfld.long 0xC 28.--30. "NUMPROC,Indicates the number of processors available for tracing. The possible values are: 000 The trace unit can trace one processor. 001 The trace unit can trace two processors." "0,1,2,3,4,5,6,7" bitfld.long 0xC 27. "SYSSTALL,Indicates if the implementation can support stall control: 0 The system does not support stall control of the processor. 1 The system can support stall control of the processor." "0,1" newline bitfld.long 0xC 26. "STALLCTL,Indicates if TRCSTALLCTLR is supported: 0 TRCSTALLCTLR is not supported. 1 TRCSTALLCTLR is supported." "0,1" bitfld.long 0xC 25. "SYNCPR,Indicates if an implementation has a fixed synchronization period: 0 TRCSYNCPR is read-write so software can change the synchronization period. 1 TRCSYNCPR is read-only so the.." "0,1" bitfld.long 0xC 24. "TRCERR,Indicates if TRCVICTLR.TRCERR is supported: 0 TRCVICTLR.TRCERR is not supported 1 TRCVICTLR.TRCERR is supported." "0,1" newline hexmask.long.byte 0xC 20.--23. 1. "EXLEVEL_NS,In Non-secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Non-secure state exception level n is not supported so the corresponding bits in.." hexmask.long.byte 0xC 16.--19. 1. "EXLEVEL_S,In Secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Secure state exception level n is not supported so the corresponding bits in TRCACATRn.EXLEVEL_S and.." hexmask.long.byte 0xC 12.--15. 1. "RES0_TRCIDR3_15_12,Reserved RES0." newline hexmask.long.word 0xC 0.--11. 1. "CCITMIN,Indicates the minimum value that can be programmed in TRCCCCTLR.THRESHOLD.When cycle counting in the instruction trace is supported that is TRCIDR0.TRCCCI==1 then the minimum value of this field is 0x001 otherwise it is 0x000." line.long 0x10 "APBADDR_ETM_CPU0_TRCIDR4,ID Register 4" hexmask.long.byte 0x10 28.--31. 1. "NUMVMIDC,Indicates the number of VMID comparators that are available for tracing. The permitted values are: 0000 No VMID comparators are available. 0001 The implementation has one VMID comparator." hexmask.long.byte 0x10 24.--27. 1. "NUMCIDC,Indicates the number of Context ID comparators that are available for tracing. The permitted values are: 0000 No Context ID comparators are available. 0001 The implementation has one.." hexmask.long.byte 0x10 20.--23. 1. "NUMSSCC,Indicates the number of single-shot comparator controls that are available for tracing. The permitted values are: 0000 No single-shot comparator controls are available. 0001 The.." newline hexmask.long.byte 0x10 16.--19. 1. "NUMRSPAIR,Indicates the number of resource selection pairs that are available for tracing. The permitted values are: 0000 The implementation has one resource selection pair. 0001 The implementation.." hexmask.long.byte 0x10 12.--15. 1. "NUMPC,Indicates the number of processor comparator inputs that are available for tracing. The permitted values are: 0000 No processor comparator inputs are available. 0001 The implementation has.." bitfld.long 0x10 9.--11. "RES0_TRCIDR4_11_9,Reserved RES0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "SUPPDAC,Indicates if the implementation can support data address comparisons: 0 The implementation does not support data address comparisons. 1 The implementation can support data address comparisons" "0,1" hexmask.long.byte 0x10 4.--7. 1. "NUMDVC,Indicates the number of data value comparators that are available for tracing. The permitted values are: 0000 No data value comparators are available. 0001 The implementation has one data.." hexmask.long.byte 0x10 0.--3. 1. "NUMACPAIRS,Indicates the number of address comparator pairs that are available for tracing. The permitted values are: 0000 No address comparator pairs are available. 0001 The implementation has one.." line.long 0x14 "APBADDR_ETM_CPU0_TRCIDR5,ID Register 5" bitfld.long 0x14 31. "REDFUNCNTR,Indicates if the reduced function counter is implemented: 0 The reduced function counter is not supported. 1 Counter 0 is implemented as a reduced function counter." "0,1" bitfld.long 0x14 28.--30. "NUMCNTR,Indicates the number of counters that are available for tracing. The permitted values are: 000 No counters are available. 001 The implementation has one counter." "0,1,2,3,4,5,6,7" bitfld.long 0x14 25.--27. "NUMSEQSTATE,Indicates the number of sequencer states that are implemented. The permitted values are: 000 No sequencer states are implemented. 100 The implementation has four sequencer states." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 24. "RES0_TRCIDR5_24_24,Reserved RES0." "0,1" bitfld.long 0x14 23. "LPOVERRIDE,Indicates if the implementation can support low-power state override: 0 The implementation does not support low-power state override. 1 The implementation supports low-power state.." "0,1" bitfld.long 0x14 22. "ATBTRIG,Indicates if the implementation can support ATB triggers: 0 The implementation does not support ATB triggers. 1 The implementation supports ATB triggers and the TRCEVENTCTL1R.ATBTRIG field.." "0,1" newline hexmask.long.byte 0x14 16.--21. 1. "TRACEIDSIZE,Indicates the trace ID width. The permitted value is: 111 The implementation supports a 7-bit trace ID. This sets the width of the TRCTRACEIDR.TRACEID field. All other values are reserved.The CoreSight ATB.." hexmask.long.byte 0x14 12.--15. 1. "RES0_TRCIDR5_15_12,Reserved RES0." bitfld.long 0x14 9.--11. "NUMEXTINSEL,Indicates how many external input select resources are implemented. The permitted values are: 000 No external input select resources are available. If NUMEXTINSEL is zero NUMEXTIN must also be zero." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 0.--8. 1. "NUMEXTIN,Indicates how many external inputs are implemented. The permitted values are: 000000000 No external inputs are available. If NUMEXTIN is zero NUMEXTINSEL must also be zero. 000000001 The.." group.long 0x208++0x37 line.long 0x0 "APBADDR_ETM_CPU0_TRCRSCTLR2,Resource Selection Control Registers 2" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCRSCTLR2_31_22,Reserved RES0." bitfld.long 0x0 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x0 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x0 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x4 "APBADDR_ETM_CPU0_TRCRSCTLR3,Resource Selection Control Registers 3" hexmask.long.word 0x4 22.--31. 1. "RES0_TRCRSCTLR3_31_22,Reserved RES0." bitfld.long 0x4 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x4 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x4 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x4 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x8 "APBADDR_ETM_CPU0_TRCRSCTLR4,Resource Selection Control Registers 4" hexmask.long.word 0x8 22.--31. 1. "RES0_TRCRSCTLR4_31_22,Reserved RES0." bitfld.long 0x8 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x8 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x8 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0xC "APBADDR_ETM_CPU0_TRCRSCTLR5,Resource Selection Control Registers 5" hexmask.long.word 0xC 22.--31. 1. "RES0_TRCRSCTLR5_31_22,Reserved RES0." bitfld.long 0xC 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0xC 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0xC 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0xC 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x10 "APBADDR_ETM_CPU0_TRCRSCTLR6,Resource Selection Control Registers 6" hexmask.long.word 0x10 22.--31. 1. "RES0_TRCRSCTLR6_31_22,Reserved RES0." bitfld.long 0x10 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x10 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x10 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x14 "APBADDR_ETM_CPU0_TRCRSCTLR7,Resource Selection Control Registers 7" hexmask.long.word 0x14 22.--31. 1. "RES0_TRCRSCTLR7_31_22,Reserved RES0." bitfld.long 0x14 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x14 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x14 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x14 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x18 "APBADDR_ETM_CPU0_TRCRSCTLR8,Resource Selection Control Registers 8" hexmask.long.word 0x18 22.--31. 1. "RES0_TRCRSCTLR8_31_22,Reserved RES0." bitfld.long 0x18 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x18 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x18 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x18 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x1C "APBADDR_ETM_CPU0_TRCRSCTLR9,Resource Selection Control Registers 9" hexmask.long.word 0x1C 22.--31. 1. "RES0_TRCRSCTLR9_31_22,Reserved RES0." bitfld.long 0x1C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x1C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x1C 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x1C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x20 "APBADDR_ETM_CPU0_TRCRSCTLR10,Resource Selection Control Registers 10" hexmask.long.word 0x20 22.--31. 1. "RES0_TRCRSCTLR10_31_22,Reserved RES0." bitfld.long 0x20 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x20 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x20 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x20 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x24 "APBADDR_ETM_CPU0_TRCRSCTLR11,Resource Selection Control Registers 11" hexmask.long.word 0x24 22.--31. 1. "RES0_TRCRSCTLR11_31_22,Reserved RES0." bitfld.long 0x24 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x24 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x24 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x24 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x28 "APBADDR_ETM_CPU0_TRCRSCTLR12,Resource Selection Control Registers 12" hexmask.long.word 0x28 22.--31. 1. "RES0_TRCRSCTLR12_31_22,Reserved RES0." bitfld.long 0x28 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x28 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x28 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x28 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x2C "APBADDR_ETM_CPU0_TRCRSCTLR13,Resource Selection Control Registers 13" hexmask.long.word 0x2C 22.--31. 1. "RES0_TRCRSCTLR13_31_22,Reserved RES0." bitfld.long 0x2C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x2C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x2C 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x2C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x30 "APBADDR_ETM_CPU0_TRCRSCTLR14,Resource Selection Control Registers 14" hexmask.long.word 0x30 22.--31. 1. "RES0_TRCRSCTLR14_31_22,Reserved RES0." bitfld.long 0x30 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x30 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x30 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x30 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x34 "APBADDR_ETM_CPU0_TRCRSCTLR15,Resource Selection Control Registers 15" hexmask.long.word 0x34 22.--31. 1. "RES0_TRCRSCTLR15_31_22,Reserved RES0." bitfld.long 0x34 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x34 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x34 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x34 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." group.long 0x280++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCSSCCR0,Single-Shot Comparator Control Register 0" hexmask.long.byte 0x0 25.--31. 1. "RES0_TRCSSCCR0_31_25,Reserved RES0." bitfld.long 0x0 24. "RST,Controls whether the single-shot comparator resource is reset when it fires. 0 When the single-shot comparator resource fires it is not reset. 1 When the single-shot comparator resource fires .." "0,1" hexmask.long.byte 0x0 16.--23. 1. "ARC,Selects one or more address range comparators for single-shot control.Each bit represents an address range comparator pair so bit[n-16] controls the selection of address range comparator pair n-16. If bit[n-16] is: 0 The address.." newline hexmask.long.word 0x0 0.--15. 1. "SAC,Selects one or more single address comparators for single-shot control.Each bit represents a single address comparator so bit[n] controls the selection of single address comparator n. If bit[n] is: 0 The single address comparator.." group.long 0x2A0++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCSSCSR0,Single-Shot Comparator Status Register 0" bitfld.long 0x0 31. "STATUS,Single-shot status bit. Indicates if any of the comparators that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects have matched: 0 No match has occurred. 1 One or more matches has occurred. If.." "0,1" hexmask.long 0x0 3.--30. 1. "RES0_TRCSSCSR0_30_3,Reserved RES0." bitfld.long 0x0 2. "DV,Data value comparator support bit. Indicates if the trace unit supports data address with data value comparisons: 0 Single-shot data address with data value comparisons are not supported. 1.." "0,1" newline bitfld.long 0x0 1. "DA,Data address comparator support bit. Indicates if the trace unit supports data address comparisons: 0 Single-shot data address comparisons are not supported. 1 Single-shot data address.." "0,1" bitfld.long 0x0 0. "INST,Instruction address comparator support bit. Indicates if the trace unit supports instruction address comparisons: 0 Single-shot instruction address comparisons are not supported. 1 Single-shot.." "0,1" group.long 0x300++0x7 line.long 0x0 "APBADDR_ETM_CPU0_TRCOSLAR,OS Lock Access Register" hexmask.long 0x0 1.--31. 1. "RES0_TRCOSLAR_31_1,Reserved RES0." bitfld.long 0x0 0. "LOCK,OS Lock control bit: 0 Unlocks the OS Lock. 1 Locks the OS Lock. This setting disables the trace unit." "0,1" line.long 0x4 "APBADDR_ETM_CPU0_TRCOSLSR,OS Lock Status Register" hexmask.long 0x4 4.--31. 1. "RES0_TRCOSLSR_31_4,Reserved RES0." bitfld.long 0x4 3. "PRESENT,Indicates whether the OS Lock is implemented.This bit is RES1 which indicates that the OS Lock is always implemented." "0,1" bitfld.long 0x4 2. "BIT32,This bit is RES0 which indicates that software must perform a 32-bit write to update the TRCOSLAR." "0,1" newline bitfld.long 0x4 1. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked. 1 The OS Lock is locked. When the trace unit core power domain is powered down the value is UNKNOWN. The TRCPDSR indicates if.." "0,1" bitfld.long 0x4 0. "RES0_TRCOSLSR_0_0,Reserved RES0." "0,1" group.long 0x310++0x7 line.long 0x0 "APBADDR_ETM_CPU0_TRCPDCR,Power Down Control Register" hexmask.long 0x0 4.--31. 1. "RES0_TRCPDCR_31_4,Reserved RES0." bitfld.long 0x0 3. "PU,Powerup request bit: 0 The system can remove power from the trace unit. The TRCPDSR indicates if the trace unit is powered down. 1 The system must provide power to the trace unit." "0,1" bitfld.long 0x0 0.--2. "RES0_TRCPDCR_2_0,Reserved RES0." "0,1,2,3,4,5,6,7" line.long 0x4 "APBADDR_ETM_CPU0_TRCPDSR,Power Down Status Register" hexmask.long 0x4 6.--31. 1. "RES0_TRCPDSR_31_6,Reserved RES0." bitfld.long 0x4 5. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked. 1 The OS Lock is locked. The value is UNKNOWN when the trace unit core power domain is powered down that is when POWER==0." "0,1" bitfld.long 0x4 2.--4. "RES0_TRCPDSR_4_2,Reserved RES0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 1. "STICKYPD,Sticky powerdown status bit. Indicates whether the trace register state is valid: 0 If POWER==1 then the state of TRCOSLSR and the trace registers are valid. If POWER==0 then it is UNKNOWN whether the state of TRCOSLSR and the.." "0,1" bitfld.long 0x4 0. "POWER,Power status bit: 0 The trace unit core power domain is not powered. The trace registers are not accessible and they all return an error response. 1 The trace unit core power domain is.." "0,1" group.long 0x400++0x3F line.long 0x0 "APBADDR_ETM_CPU0_TRCACVR0_31_0,Address Comparator Value Registers 0 (low word)" hexmask.long 0x0 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x4 "APBADDR_ETM_CPU0_TRCACVR0_63_32,Address Comparator Value Registers 0 (high word)" hexmask.long 0x4 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x8 "APBADDR_ETM_CPU0_TRCACVR1_31_0,Address Comparator Value Registers 1 (low word)" hexmask.long 0x8 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0xC "APBADDR_ETM_CPU0_TRCACVR1_63_32,Address Comparator Value Registers 1 (high word)" hexmask.long 0xC 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x10 "APBADDR_ETM_CPU0_TRCACVR2_31_0,Address Comparator Value Registers 2 (low word)" hexmask.long 0x10 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x14 "APBADDR_ETM_CPU0_TRCACVR2_63_32,Address Comparator Value Registers 2 (high word)" hexmask.long 0x14 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x18 "APBADDR_ETM_CPU0_TRCACVR3_31_0,Address Comparator Value Registers 3 (low word)" hexmask.long 0x18 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x1C "APBADDR_ETM_CPU0_TRCACVR3_63_32,Address Comparator Value Registers 3 (high word)" hexmask.long 0x1C 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x20 "APBADDR_ETM_CPU0_TRCACVR4_31_0,Address Comparator Value Registers 4 (low word)" hexmask.long 0x20 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x24 "APBADDR_ETM_CPU0_TRCACVR4_63_32,Address Comparator Value Registers 4 (high word)" hexmask.long 0x24 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x28 "APBADDR_ETM_CPU0_TRCACVR5_31_0,Address Comparator Value Registers 5 (low word)" hexmask.long 0x28 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x2C "APBADDR_ETM_CPU0_TRCACVR5_63_32,Address Comparator Value Registers 5 (high word)" hexmask.long 0x2C 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x30 "APBADDR_ETM_CPU0_TRCACVR6_31_0,Address Comparator Value Registers 6 (low word)" hexmask.long 0x30 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x34 "APBADDR_ETM_CPU0_TRCACVR6_63_32,Address Comparator Value Registers 6 (high word)" hexmask.long 0x34 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x38 "APBADDR_ETM_CPU0_TRCACVR7_31_0,Address Comparator Value Registers 7 (low word)" hexmask.long 0x38 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x3C "APBADDR_ETM_CPU0_TRCACVR7_63_32,Address Comparator Value Registers 7 (high word)" hexmask.long 0x3C 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." group.long 0x480++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCACATR0,Address Comparator Access Type Registers 0" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR0_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR0_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x488++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCACATR1,Address Comparator Access Type Registers 1" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR1_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR1_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x490++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCACATR2,Address Comparator Access Type Registers 2" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR2_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR2_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x498++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCACATR3,Address Comparator Access Type Registers 3" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR3_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR3_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4A0++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCACATR4,Address Comparator Access Type Registers 4" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR4_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR4_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4A8++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCACATR5,Address Comparator Access Type Registers 5" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR5_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR5_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4B0++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCACATR6,Address Comparator Access Type Registers 6" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR6_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR6_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4B8++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCACATR7,Address Comparator Access Type Registers 7" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR7_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR7_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x600++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCCIDCVR0,Context ID Comparator Value Register 0" hexmask.long 0x0 0.--31. 1. "VALUE,Context ID value. The implemented width of this field is IMPLEMENTATION DEFINED and is set by TRCIDR2.CIDSIZE. Unimplemented bits are RAZ/WI.After a processor reset the ETM architecture assumes that the Context ID is zero until the processor.." group.long 0x640++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCVMIDCVR0,VMID Comparator Value Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--7. 1. "VALUE,Contains a VMID value." group.long 0x680++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCCIDCCTLR0,Context ID Comparator Control Register 0" hexmask.long 0x0 0.--31. 1. "COMP_N,Controls the mask value that the trace unit applies to TRCCIDCVRn. Each bit in this field corresponds to a byte in TRCCIDCVRn. When a bit is: 0 The trace unit includes the relevant byte in TRCCIDCVRn when it performs the Context.." group.long 0xEE4++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCITATBIDR,Integration ATB Identification Register" hexmask.long 0x0 7.--31. 1. "RES0_TRCITATBIDR_31_7,Reserved RES0" hexmask.long.byte 0x0 0.--6. 1. "ID,Drives the ATIDMn[6:0] output pins" group.long 0xEEC++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCITIDATAR,Integration Instruction ATB Data Register" hexmask.long 0x0 5.--31. 1. "RES0_TRCITIDATAR_31_5,Reserved RES0" bitfld.long 0x0 4. "ATDATAM_31,Drives the ATDATAM[31] output" "0,1" bitfld.long 0x0 3. "ATDATAM_23,Drives the ATDATAM[23] output" "0,1" newline bitfld.long 0x0 2. "ATDATAM_15,Drives the ATDATAM[15] output" "0,1" bitfld.long 0x0 1. "ATDATAM_7,Drives the ATDATAM[7] output" "0,1" bitfld.long 0x0 0. "ATDATAM_0,Drives the ATDATAM[0] output" "0,1" group.long 0xEF4++0x3 line.long 0x0 "APBADDR_ETM_CPU0_TRCITIATBINR,Integration Instruction ATB In Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved. Read undefined." bitfld.long 0x0 1. "AFVALIDM,Returns the value of the AFVALIDMn input pin" "0,1" bitfld.long 0x0 0. "ATREADYM,Returns the value of the ATREADYMn input pin" "0,1" group.long 0xEFC++0x7 line.long 0x0 "APBADDR_ETM_CPU0_TRCITIATBOUTR,Integration Instruction ATB Out Register" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved. Read undefined." bitfld.long 0x0 8.--9. "BYTES,Drives the ATBYTESMn[1:0] output pins" "0,1,2,3" hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved. Read undefined." newline bitfld.long 0x0 1. "AFREADY,Drives the AFREADYMn output pin" "0,1" bitfld.long 0x0 0. "ATVALID,Drives the ATVALIDMn output pin" "0,1" line.long 0x4 "APBADDR_ETM_CPU0_TRCITCTRL,Integration Mode Control Register" hexmask.long 0x4 1.--31. 1. "RES0_TRCITCTRL_31_1,Reserved RES0." bitfld.long 0x4 0. "ITEN,Integration mode enable bit: 0 The trace unit is not in integration mode. 1 The trace unit is in integration mode. This mode enables a debug agent to perform topology detection and.." "0,1" group.long 0xFA0++0x1F line.long 0x0 "APBADDR_ETM_CPU0_TRCCLAIMSET,Claim Tag Set Register" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--3. 1. "SET,Sets bits in the claim tag and determines the number of claim tag bits implemented." line.long 0x4 "APBADDR_ETM_CPU0_TRCCLAIMCLR,Claim Tag Clear Register" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "CLR,Clears bits in the claim tag and determines the current value of the claim tag." line.long 0x8 "APBADDR_ETM_CPU0_TRCDEVAFF0,Device Affinity Register 0" hexmask.long 0x8 0.--31. 1. "MPIDR_EL1_31_0,Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0xC "APBADDR_ETM_CPU0_TRCDEVAFF1,Device Affinity Register 1" hexmask.long 0xC 0.--31. 1. "MPIDR_EL1_63_32,Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x10 "APBADDR_ETM_CPU0_TRCLAR,Software Lock Access Register" hexmask.long 0x10 0.--31. 1. "KEY,Writing the key value 0xC5ACCE55 to this field clears the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register sets the lock disabling write accesses to this.." line.long 0x14 "APBADDR_ETM_CPU0_TRCLSR,Software Lock Status Register" hexmask.long 0x14 3.--31. 1. "RES0_TRCLSR_31_3,Reserved RES0." bitfld.long 0x14 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" bitfld.long 0x14 1. "SLK,Software lock status for this component. Possible values of this field are: 0 Lock clear. Writes are permitted to this component's registers. 1 Lock set. Writes to this component's registers.." "0,1" newline bitfld.long 0x14 0. "SLI,Software lock implemented. RAO." "0,1" line.long 0x18 "APBADDR_ETM_CPU0_TRCAUTHSTATUS,Authentication Status Register" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCAUTHSTATUS_31_8,Reserved RES0." bitfld.long 0x18 6.--7. "SNID,Indicates whether the system enables the trace unit to support Secure non-invasive debug: 00 The trace unit does not implement support for Secure non-invasive debug. 01 Reserved." "0,1,2,3" bitfld.long 0x18 4.--5. "SID,Indicates whether the trace unit supports Secure invasive debug: 00 The trace unit does not support Secure invasive debug. All other values are reserved." "0,1,2,3" newline bitfld.long 0x18 2.--3. "NSNID,Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: 00 The trace unit does not implement support for Non-secure non-invasive debug. 01 Reserved." "0,1,2,3" bitfld.long 0x18 0.--1. "NSID,Indicates whether the trace unit supports Non-secure invasive debug: 00 The trace unit does not support Non-secure invasive debug. All other values are reserved." "0,1,2,3" line.long 0x1C "APBADDR_ETM_CPU0_TRCDEVARCH,Device Architecture Register" hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For trace this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is RAO." "0,1" hexmask.long.byte 0x1C 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For trace the revision defined by ETMv4 is 0x0.All other values are reserved." newline hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For trace bits [15:12] are the architecture version 0x4; bits [11:0] are the architecture part number 0xA13.This corresponds to trace.." group.long 0xFC8++0x37 line.long 0x0 "APBADDR_ETM_CPU0_TRCDEVID,Device ID Register" hexmask.long 0x0 0.--31. 1. "DEVID,Indicates the capabilities of the trace unit. The implemented width of this field and its bit assignments are IMPLEMENTATION DEFINED. Unimplemented bits are RAZ/WI.If a component is configurable then ARM recommends that this field can also indicate.." line.long 0x4 "APBADDR_ETM_CPU0_TRCDEVTYPE,Device Type Register" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_TRCDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x4 4.--7. 1. "SUB,Returns 0x1 to indicate that the ETM generates processor trace.All other values are reserved." hexmask.long.byte 0x4 0.--3. 1. "MAIN,Returns 0x3 to indicate that the ETM is a trace source.All other values are reserved." line.long 0x8 "APBADDR_ETM_CPU0_TRCPIDR4,Peripheral Identification Register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RES0_TRCPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x8 4.--7. 1. "SIZE,Size of the component. RES0. This indicates that the ETM memory map occupies 4KB." hexmask.long.byte 0x8 0.--3. 1. "DES_2,Designer JEP106 continuation code. For ARM Limited this field is 0b0100." line.long 0xC "APBADDR_ETM_CPU0_TRCPIDR5,Peripheral Identification Register 5" hexmask.long.tbyte 0xC 8.--31. 1. "RES0_TRCPIDR5_31_8,Reserved RES0." hexmask.long.byte 0xC 0.--7. 1. "RESERVED,RES0 reserved for future use." line.long 0x10 "APBADDR_ETM_CPU0_TRCPIDR6,Peripheral Identification Register 6" hexmask.long.tbyte 0x10 8.--31. 1. "RES0_TRCPIDR6_31_8,Reserved RES0." hexmask.long.byte 0x10 0.--7. 1. "RESERVED,RES0 reserved for future use." line.long 0x14 "APBADDR_ETM_CPU0_TRCPIDR7,Peripheral Identification Register 7" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_TRCPIDR7_31_8,Reserved RES0." hexmask.long.byte 0x14 0.--7. 1. "RESERVED,RES0 reserved for future use." line.long 0x18 "APBADDR_ETM_CPU0_TRCPIDR0,Peripheral Identification Register 0" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x18 0.--7. 1. "PART_0,Part number bits[7:0]." line.long 0x1C "APBADDR_ETM_CPU0_TRCPIDR1,Peripheral Identification Register 1" hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_TRCPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x1C 4.--7. 1. "DES_0,Designer bits[3:0] of JEP106 ID code. For ARM Limited this field is 0b1011." hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part number bits[11:8]." line.long 0x20 "APBADDR_ETM_CPU0_TRCPIDR2,Peripheral Identification Register 2" hexmask.long.tbyte 0x20 8.--31. 1. "RES0_TRCPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x20 4.--7. 1. "REVISION,The IMPLEMENTATION DEFINED revision number for the ETM implementation. See also TRCIDR1.REVISION." bitfld.long 0x20 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" newline bitfld.long 0x20 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0x24 "APBADDR_ETM_CPU0_TRCPIDR3,Peripheral Identification Register 3" hexmask.long.tbyte 0x24 8.--31. 1. "RES0_TRCPIDR3_31_8,Reserved RES0." hexmask.long.byte 0x24 4.--7. 1. "REVAND,The IMPLEMENTATION DEFINED manufacturing revision number for the implementation. After silicon is available if metal fixes are necessary the manufacturer can alter the top metal layer so that this field can indicate any post-fab silicon changes." hexmask.long.byte 0x24 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x28 "APBADDR_ETM_CPU0_TRCCIDR0,Component Identification Register 0" hexmask.long.tbyte 0x28 8.--31. 1. "RES0_TRCCIDR0_31_8,Reserved RES0." hexmask.long.byte 0x28 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x2C "APBADDR_ETM_CPU0_TRCCIDR1,Component Identification Register 1" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_TRCCIDR1_31_8,Reserved RES0." hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Component class. Reads as 0x9 to indicate that the ETM is a debug component with CoreSight architecture compliant management registers." hexmask.long.byte 0x2C 0.--3. 1. "PRMBL_1,Preamble. Must read as 0x0." line.long 0x30 "APBADDR_ETM_CPU0_TRCCIDR2,Component Identification Register 2" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_TRCCIDR2_31_8,Reserved RES0." hexmask.long.byte 0x30 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x34 "APBADDR_ETM_CPU0_TRCCIDR3,Component Identification Register 3" hexmask.long.tbyte 0x34 8.--31. 1. "RES0_TRCCIDR3_31_8,Reserved RES0." hexmask.long.byte 0x34 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree "A53SS0_CORE0_PMU" base ad:0x730030000 group.long 0x0++0x3 line.long 0x0 "APBADDR_PMU_CPU0_PMEVCNTR0_EL0,Performance Monitors Event Count Register 0" hexmask.long 0x0 0.--31. 1. "PMEVCNTR0_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x8++0x3 line.long 0x0 "APBADDR_PMU_CPU0_PMEVCNTR1_EL0,Performance Monitors Event Count Register 1" hexmask.long 0x0 0.--31. 1. "PMEVCNTR1_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x10++0x3 line.long 0x0 "APBADDR_PMU_CPU0_PMEVCNTR2_EL0,Performance Monitors Event Count Register 2" hexmask.long 0x0 0.--31. 1. "PMEVCNTR2_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x18++0x3 line.long 0x0 "APBADDR_PMU_CPU0_PMEVCNTR3_EL0,Performance Monitors Event Count Register 3" hexmask.long 0x0 0.--31. 1. "PMEVCNTR3_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x20++0x3 line.long 0x0 "APBADDR_PMU_CPU0_PMEVCNTR4_EL0,Performance Monitors Event Count Register 4" hexmask.long 0x0 0.--31. 1. "PMEVCNTR4_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x28++0x3 line.long 0x0 "APBADDR_PMU_CPU0_PMEVCNTR5_EL0,Performance Monitors Event Count Register 5" hexmask.long 0x0 0.--31. 1. "PMEVCNTR5_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0xF8++0x7 line.long 0x0 "APBADDR_PMU_CPU0_PMCCNTR_EL0_31_0,Performance Monitors Cycle Counter (low word)" hexmask.long 0x0 0.--31. 1. "CCNT,Cycle count. Depending on the values of PMCR_EL0.{LC D} the cycle count increments in one of the following ways:Every processor clock cycle.Every 64th processor clock cycle.The cycle count can be reset to zero by writing 1 to PMCR_EL0.C." line.long 0x4 "APBADDR_PMU_CPU0_PMCCNTR_EL0_63_32,Performance Monitors Cycle Counter (high word)" hexmask.long 0x4 0.--31. 1. "CCNT,Cycle count. Depending on the values of PMCR_EL0.{LC D} the cycle count increments in one of the following ways:Every processor clock cycle.Every 64th processor clock cycle.The cycle count can be reset to zero by writing 1 to PMCR_EL0.C." group.long 0x400++0x17 line.long 0x0 "APBADDR_PMU_CPU0_PMEVTYPER0_EL0,Performance Monitors Event Type Register 0" bitfld.long 0x0 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x0 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x0 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x0 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x0 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x0 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x0 10.--25. 1. "RES0_PMEVTYPER0_EL0_25_10,Reserved RES0." hexmask.long.word 0x0 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x4 "APBADDR_PMU_CPU0_PMEVTYPER1_EL0,Performance Monitors Event Type Register 1" bitfld.long 0x4 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x4 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x4 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x4 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x4 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x4 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x4 10.--25. 1. "RES0_PMEVTYPER1_EL0_25_10,Reserved RES0." hexmask.long.word 0x4 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x8 "APBADDR_PMU_CPU0_PMEVTYPER2_EL0,Performance Monitors Event Type Register 2" bitfld.long 0x8 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x8 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x8 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x8 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x8 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x8 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x8 10.--25. 1. "RES0_PMEVTYPER2_EL0_25_10,Reserved RES0." hexmask.long.word 0x8 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0xC "APBADDR_PMU_CPU0_PMEVTYPER3_EL0,Performance Monitors Event Type Register 3" bitfld.long 0xC 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0xC 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0xC 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0xC 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0xC 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0xC 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0xC 10.--25. 1. "RES0_PMEVTYPER3_EL0_25_10,Reserved RES0." hexmask.long.word 0xC 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x10 "APBADDR_PMU_CPU0_PMEVTYPER4_EL0,Performance Monitors Event Type Register 4" bitfld.long 0x10 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x10 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x10 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x10 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x10 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x10 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x10 10.--25. 1. "RES0_PMEVTYPER4_EL0_25_10,Reserved RES0." hexmask.long.word 0x10 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x14 "APBADDR_PMU_CPU0_PMEVTYPER5_EL0,Performance Monitors Event Type Register 5" bitfld.long 0x14 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x14 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x14 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x14 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x14 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x14 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x14 10.--25. 1. "RES0_PMEVTYPER5_EL0_25_10,Reserved RES0." hexmask.long.word 0x14 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." group.long 0x47C++0x3 line.long 0x0 "APBADDR_PMU_CPU0_PMCCFILTR_EL0,Performance Monitors Cycle Counter Filter Register" bitfld.long 0x0 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count cycles in EL1. 1.." "0,1" bitfld.long 0x0 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count cycles in EL0. 1.." "0,1" newline bitfld.long 0x0 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P cycles in Non-secure EL1 are counted.Otherwise cycles in Non-secure EL1 are.." "0,1" bitfld.long 0x0 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U cycles in Non-secure EL0 are counted.Otherwise cycles in Non-secure EL0 are.." "0,1" newline bitfld.long 0x0 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count cycles in EL2. 1 Count cycles in EL2." "0,1" bitfld.long 0x0 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P cycles in Secure EL3 are counted.Otherwise cycles in Secure EL3.." "0,1" newline hexmask.long 0x0 0.--25. 1. "RES0_PMCCFILTR_EL0_25_0,Reserved RES0." group.long 0xC00++0x3 line.long 0x0 "APBADDR_PMU_CPU0_PMCNTENSET_EL0,Performance Monitors Count Enable Set Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 enable bit. Enables the cycle counter register. Possible values are: 0 When read means the cycle counter is disabled. When written has no effect. 1 When read means the cycle.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter enable bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: 0 When read means that PMEVCNTR is disabled. When written has no effect. 1.." group.long 0xC20++0x3 line.long 0x0 "APBADDR_PMU_CPU0_PMCNTENCLR_EL0,Performance Monitors Count Enable Clear Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 disable bit. Disables the cycle counter register. Possible values are: 0 When read means the cycle counter is disabled. When written has no effect. 1 When read means the cycle.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter disable bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: 0 When read means that PMEVCNTR is disabled. When written has no effect." group.long 0xC40++0x3 line.long 0x0 "APBADDR_PMU_CPU0_PMINTENSET_EL1,Performance Monitors Interrupt Enable Set Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow interrupt request enable bit. Possible values are: 0 When read means the cycle counter overflow interrupt request is disabled. When written has no effect. 1 When read .." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow interrupt request enable bit for PMEVCNTR_EL0.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: 0 When read means that the PMEVCNTR_EL0 event counter interrupt request is.." group.long 0xC60++0x3 line.long 0x0 "APBADDR_PMU_CPU0_PMINTENCLR_EL1,Performance Monitors Interrupt Enable Clear Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow interrupt request disable bit. Possible values are: 0 When read means the cycle counter overflow interrupt request is disabled. When written has no effect. 1 When read .." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow interrupt request disable bit for PMEVCNTR_EL0.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: 0 When read means that the PMEVCNTR_EL0 event counter interrupt request is.." group.long 0xC80++0x3 line.long 0x0 "APBADDR_PMU_CPU0_PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow bit. Possible values are: 0 When read means the cycle counter has not overflowed. When written has no effect. 1 When read means the cycle counter has overflowed. When.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow clear bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: 0 When read means that PMEVCNTR has not overflowed. When written has no effect." group.long 0xCA0++0x3 line.long 0x0 "APBADDR_PMU_CPU0_PMSWINC_EL0,Performance Monitors Software Increment Register" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--5. 1. "P_X,Event counter software increment bit for PMEVCNTR" group.long 0xCC0++0x3 line.long 0x0 "APBADDR_PMU_CPU0_PMOVSSET_EL0,Performance Monitors Overflow Flag Status Set Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow bit. Possible values are: 0 When read means the cycle counter has not overflowed. When written has no effect. 1 When read means the cycle counter has overflowed. When.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow set bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: 0 When read means that PMEVCNTR has not overflowed. When written has no effect." group.long 0xE00++0x7 line.long 0x0 "APBADDR_PMU_CPU0_PMCFGR,Performance Monitors Configuration Register" hexmask.long.word 0x0 20.--31. 1. "RES0_PMCFGR_31_20,Reserved RES0." bitfld.long 0x0 19. "UEN,User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface so this bit is RES0." "0,1" newline bitfld.long 0x0 18. "WT,This feature is not supported so this bit is RES0." "0,1" bitfld.long 0x0 17. "NA,This feature is not supported so this bit is RES0." "0,1" newline bitfld.long 0x0 16. "EX,Export supported. Value is IMPLEMENTATION DEFINED. 0 PMCR_EL0.X is RES0. 1 PMCR_EL0.X is read/write." "0,1" bitfld.long 0x0 15. "CCD,Cycle counter has prescale. This is RES1 if AArch32 is supported at any EL and RES0 otherwise. 0 PMCR_EL0.D is RES0. 1 PMCR_EL0.D is read/write." "0,1" newline bitfld.long 0x0 14. "CC,Dedicated cycle counter [counter 31] supported. This bit is RES1." "0,1" hexmask.long.byte 0x0 8.--13. 1. "SIZE,Size of counters. This field determines the spacing of counters in the memory-map.In v8-A the counters are at doubleword-aligned addresses and the largest counter is 64-bits so this field is 0b111111." newline hexmask.long.byte 0x0 0.--7. 1. "N,Number of counters implemented in addition to the cycle counter PMCCNTR_EL0. The maximum number of event counters is 31 so bits[7:5] are always RES0. 00000000 Only PMCCNTR_EL0 implemented. 00000001.." line.long 0x4 "APBADDR_PMU_CPU0_PMCR_EL0,Performance Monitors Control Register" hexmask.long.tbyte 0x4 11.--31. 1. "RES0_PMCR_EL0_31_11,Reserved RAZ/WI." hexmask.long.byte 0x4 7.--10. 1. "RES0_PMCR_EL0_10_7,Reserved RES0." newline bitfld.long 0x4 6. "LC,Long cycle counter enable. Determines which PMCCNTR_EL0 bit generates an overflow recorded by PMOVSR[31]. 0 Cycle counter overflow on increment that changes PMCCNTR_EL0[31] from 1 to 0. 1 Cycle.." "0,1" bitfld.long 0x4 5. "DP,Disable cycle counter when event counting is prohibited. The possible values of this bit are: 0 PMCCNTR_EL0 if enabled counts when event counting is prohibited. 1 PMCCNTR_EL0 does not count.." "0,1" newline bitfld.long 0x4 4. "X,Enable export of events in an IMPLEMENTATION DEFINED event stream. The possible values of this bit are: 0 Do not export events. 1 Export events where not prohibited. This bit is.." "0,1" bitfld.long 0x4 3. "D,Clock divider. The possible values of this bit are: 0 When enabled PMCCNTR_EL0 counts every clock cycle. 1 When enabled PMCCNTR_EL0 counts once every 64 clock cycles. This bit.." "0,1" newline bitfld.long 0x4 2. "C,Cycle counter reset. This bit is WO. The effects of writing to this bit are: 0 No action. 1 Reset PMCCNTR_EL0 to zero. This bit is always RAZ.Resetting PMCCNTR_EL0 does not.." "0,1" bitfld.long 0x4 1. "P,Event counter reset. This bit is WO. The effects of writing to this bit are: 0 No action. 1 Reset all event counters not including PMCCNTR_EL0 to zero. This bit is always.." "0,1" newline bitfld.long 0x4 0. "E,Enable. The possible values of this bit are: 0 All counters including PMCCNTR_EL0 are disabled. 1 All counters are enabled by PMCNTENSET_EL0. This bit is RW." "0,1" group.long 0xE20++0x7 line.long 0x0 "APBADDR_PMU_CPU0_PMCEID0_EL0,Performance Monitors Common Event Identification Register 0" hexmask.long 0x0 0.--31. 1. "CE_31_0,Common architectural and microarchitectural feature events that can be counted by the PMU event counters.For each bit described in the following table the event is implemented if the bit is set to 1 or not implemented if the bit is set to.." line.long 0x4 "APBADDR_PMU_CPU0_PMCEID1_EL0,Performance Monitors Common Event Identification Register 1" hexmask.long 0x4 1.--31. 1. "RES0_PMCEID1_EL0_31_1,Reserved RES0." bitfld.long 0x4 0. "CE_32,Common architectural and microarchitectural feature events that can be counted by the PMU event counters.For the bit described in the following table the event is implemented if the bit is set to 1 or not implemented if the bit is set to.." "0,1" group.long 0xF00++0x3 line.long 0x0 "APBADDR_PMU_CPU0_PMITCTRL,Performance Monitors Integration mode Control Register" hexmask.long 0x0 1.--31. 1. "RES0_PMITCTRL_31_1,Reserved RES0." bitfld.long 0x0 0. "IME,Integration mode enable. When IME == 1 the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED. 0 Normal operation." "0,1" group.long 0xFA8++0x17 line.long 0x0 "APBADDR_PMU_CPU0_PMDEVAFF0,Performance Monitors Device Affinity Register 0" hexmask.long 0x0 0.--31. 1. "PMDEVAFF0,MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x4 "APBADDR_PMU_CPU0_PMDEVAFF1,Performance Monitors Device Affinity Register 1" hexmask.long 0x4 0.--31. 1. "PMDEVAFF1,MPIDR_EL1 high half. Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x8 "APBADDR_PMU_CPU0_PMLAR,Performance Monitors Lock Access Register" hexmask.long 0x8 0.--31. 1. "KEY,Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register locks the lock disabling write.." line.long 0xC "APBADDR_PMU_CPU0_PMLSR,Performance Monitors Lock Status Register" hexmask.long 0xC 3.--31. 1. "RES0_PMLSR_31_3,Reserved RES0." bitfld.long 0xC 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" newline bitfld.long 0xC 1. "SLK,Software lock status for this component. For an access to LSR that is not a memory-mapped access or when the software lock is not implemented this field is RES0.For memory-mapped accesses when the software lock is implemented possible values of.." "0,1" bitfld.long 0xC 0. "SLI,Software lock implemented. For an access to LSR that is not a memory-mapped access this field is RAZ. For memory-mapped accesses the value of this field is IMPLEMENTATION DEFINED. Permitted values are: 0 Software lock not.." "0,1" line.long 0x10 "APBADDR_PMU_CPU0_PMAUTHSTATUS,Performance Monitors Authentication Status Register" hexmask.long.tbyte 0x10 8.--31. 1. "RES0_PMAUTHSTATUS_31_8,Reserved RES0." bitfld.long 0x10 6.--7. "SNID,Holds the same value as DBGAUTHSTATUS_EL1.SNID." "0,1,2,3" newline bitfld.long 0x10 4.--5. "RES0_PMAUTHSTATUS_5_4,Reserved RES0." "0,1,2,3" bitfld.long 0x10 2.--3. "NSNID,Holds the same value as DBGAUTHSTATUS_EL1.NSNID." "0,1,2,3" newline bitfld.long 0x10 0.--1. "RES0_PMAUTHSTATUS_1_0,Reserved RES0." "0,1,2,3" line.long 0x14 "APBADDR_PMU_CPU0_PMDEVARCH,Performance Monitors Device Architecture Register" hexmask.long.word 0x14 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For Performance Monitors this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x14 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A." "0,1" newline hexmask.long.byte 0x14 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For Performance Monitors the revision defined by v8-A is 0x0.All other values are reserved." hexmask.long.word 0x14 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For Performance Monitors:Bits [15:12] are the architecture version 0x2.Bits [11:0] are the architecture part number 0xA16.This.." group.long 0xFCC++0x33 line.long 0x0 "APBADDR_PMU_CPU0_PMDEVTYPE,Performance Monitors Device Type Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_PMDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x0 4.--7. 1. "SUB,Subtype. Must read as 0x1 to indicate this is a processor component." newline hexmask.long.byte 0x0 0.--3. 1. "MAJOR,Major type. Must read as 0x6 to indicate this is a performance monitor component." line.long 0x4 "APBADDR_PMU_CPU0_PMPIDR4,Performance Monitors Peripheral Identification Register 4" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_PMPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x4 4.--7. 1. "SIZE,Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers." newline hexmask.long.byte 0x4 0.--3. 1. "DES_2,Designer JEP106 continuation code least significant nibble. For ARM Limited this field is 0b0100." line.long 0x8 "APBADDR_PMU_CPU0_PMPIDR5,Performance Monitors Peripheral Identification Register 5" hexmask.long 0x8 0.--31. 1. "RESERVED,Reserved RES0" line.long 0xC "APBADDR_PMU_CPU0_PMPIDR6,Performance Monitors Peripheral Identification Register 6" hexmask.long 0xC 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x10 "APBADDR_PMU_CPU0_PMPIDR7,Performance Monitors Peripheral Identification Register 7" hexmask.long 0x10 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x14 "APBADDR_PMU_CPU0_PMPIDR0,Performance Monitors Peripheral Identification Register 0" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_PMPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x14 0.--7. 1. "PART_0,Part number least significant byte." line.long 0x18 "APBADDR_PMU_CPU0_PMPIDR1,Performance Monitors Peripheral Identification Register 1" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_PMPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x18 4.--7. 1. "DES_0,Designer least significant nibble of JEP106 ID code. For ARM Limited this field is 0b1011." newline hexmask.long.byte 0x18 0.--3. 1. "PART_1,Part number most significant nibble." line.long 0x1C "APBADDR_PMU_CPU0_PMPIDR2,Performance Monitors Peripheral Identification Register 2" hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_PMPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x1C 4.--7. 1. "REVISION,Part major revision. Parts can also use this field to extend Part number to 16-bits." newline bitfld.long 0x1C 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" bitfld.long 0x1C 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0x20 "APBADDR_PMU_CPU0_PMPIDR3,Performance Monitors Peripheral Identification Register 3" hexmask.long.tbyte 0x20 8.--31. 1. "RES0_PMPIDR3_31_8,Reserved RES0." hexmask.long.byte 0x20 4.--7. 1. "REVAND,Part minor revision. Parts using PMPIDR2.REVISION as an extension to the Part number must use this field as a major revision number." newline hexmask.long.byte 0x20 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x24 "APBADDR_PMU_CPU0_PMCIDR0,Performance Monitors Component Identification Register 0" hexmask.long.tbyte 0x24 8.--31. 1. "RES0_PMCIDR0_31_8,Reserved RES0." hexmask.long.byte 0x24 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x28 "APBADDR_PMU_CPU0_PMCIDR1,Performance Monitors Component Identification Register 1" hexmask.long.tbyte 0x28 8.--31. 1. "RES0_PMCIDR1_31_8,Reserved RES0." hexmask.long.byte 0x28 4.--7. 1. "CLASS,Component class. Reads as 0x9 debug component." newline hexmask.long.byte 0x28 0.--3. 1. "PRMBL_1,Preamble. RAZ." line.long 0x2C "APBADDR_PMU_CPU0_PMCIDR2,Performance Monitors Component Identification Register 2" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_PMCIDR2_31_8,Reserved RES0." hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x30 "APBADDR_PMU_CPU0_PMCIDR3,Performance Monitors Component Identification Register 3" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_PMCIDR3_31_8,Reserved RES0." hexmask.long.byte 0x30 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree.end tree "A53SS0_CORE1" tree "A53SS0_CORE1_CTI" base ad:0x730140000 group.long 0x0++0x3 line.long 0x0 "APBADDR_CTI_CPU1_CTICONTROL,CTI Control Register" hexmask.long 0x0 1.--31. 1. "RES0_CTICONTROL_31_1,Reserved RES0." bitfld.long 0x0 0. "GLBEN,Enables or disables the CTI mapping functions. Possible values of this field are: 0 CTI mapping functions disabled. 1 CTI mapping functions enabled. When the mapping.." "0,1" group.long 0x10++0x2F line.long 0x0 "APBADDR_CTI_CPU1_CTIINTACK,CTI Output Trigger Acknowledge Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--7. 1. "ACK_N,Can be used to create soft acknowledges for output triggers" line.long 0x4 "APBADDR_CTI_CPU1_CTIAPPSET,CTI Application Trigger Set Register" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "CTIAPPSETX,Application trigger enable" line.long 0x8 "APBADDR_CTI_CPU1_CTIAPPCLEAR,CTI Application Trigger Clear Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x8 0.--3. 1. "CTIAPPCLEARX,Application trigger disable" line.long 0xC "APBADDR_CTI_CPU1_CTIAPPPULSE,CTI Application Pulse Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0xC 0.--3. 1. "CTIAPPPULSEX,Generate event pulse on ECT channel ." line.long 0x10 "APBADDR_CTI_CPU1_CTIINEN0,CTI Input Trigger to Output Channel Enable Register 0" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x10 0.--3. 1. "INENX,Input trigger 0 to output channel enable" line.long 0x14 "APBADDR_CTI_CPU1_CTIINEN1,CTI Input Trigger to Output Channel Enable Register 1" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x14 0.--3. 1. "INENX,Input trigger 1 to output channel enable" line.long 0x18 "APBADDR_CTI_CPU1_CTIINEN2,CTI Input Trigger to Output Channel Enable Register 2" hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x18 0.--3. 1. "INENX,Input trigger 2 to output channel enable" line.long 0x1C "APBADDR_CTI_CPU1_CTIINEN3,CTI Input Trigger to Output Channel Enable Register 3" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x1C 0.--3. 1. "INENX,Input trigger 3 to output channel enable" line.long 0x20 "APBADDR_CTI_CPU1_CTIINEN4,CTI Input Trigger to Output Channel Enable Register 4" hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x20 0.--3. 1. "INENX,Input trigger 4 to output channel enable" line.long 0x24 "APBADDR_CTI_CPU1_CTIINEN5,CTI Input Trigger to Output Channel Enable Register 5" hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x24 0.--3. 1. "INENX,Input trigger 5 to output channel enable" line.long 0x28 "APBADDR_CTI_CPU1_CTIINEN6,CTI Input Trigger to Output Channel Enable Register 6" hexmask.long 0x28 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x28 0.--3. 1. "INENX,Input trigger 6 to output channel enable" line.long 0x2C "APBADDR_CTI_CPU1_CTIINEN7,CTI Input Trigger to Output Channel Enable Register 7" hexmask.long 0x2C 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x2C 0.--3. 1. "INENX,Input trigger 7 to output channel enable" group.long 0xA0++0x1F line.long 0x0 "APBADDR_CTI_CPU1_CTIOUTEN0,CTI Input Channel to Output Trigger Enable Register 0" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--3. 1. "OUTENX,Input channel to output trigger 0 enable" line.long 0x4 "APBADDR_CTI_CPU1_CTIOUTEN1,CTI Input Channel to Output Trigger Enable Register 1" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "OUTENX,Input channel to output trigger 1 enable" line.long 0x8 "APBADDR_CTI_CPU1_CTIOUTEN2,CTI Input Channel to Output Trigger Enable Register 2" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x8 0.--3. 1. "OUTENX,Input channel to output trigger 2 enable" line.long 0xC "APBADDR_CTI_CPU1_CTIOUTEN3,CTI Input Channel to Output Trigger Enable Register 3" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0xC 0.--3. 1. "OUTENX,Input channel to output trigger 3 enable" line.long 0x10 "APBADDR_CTI_CPU1_CTIOUTEN4,CTI Input Channel to Output Trigger Enable Register 4" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x10 0.--3. 1. "OUTENX,Input channel to output trigger 4 enable" line.long 0x14 "APBADDR_CTI_CPU1_CTIOUTEN5,CTI Input Channel to Output Trigger Enable Register 5" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x14 0.--3. 1. "OUTENX,Input channel to output trigger 5 enable" line.long 0x18 "APBADDR_CTI_CPU1_CTIOUTEN6,CTI Input Channel to Output Trigger Enable Register 6" hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x18 0.--3. 1. "OUTENX,Input channel to output trigger 6 enable" line.long 0x1C "APBADDR_CTI_CPU1_CTIOUTEN7,CTI Input Channel to Output Trigger Enable Register 7" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x1C 0.--3. 1. "OUTENX,Input channel to output trigger 7 enable" group.long 0x130++0x17 line.long 0x0 "APBADDR_CTI_CPU1_CTITRIGINSTATUS,CTI Trigger In Status Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--7. 1. "TRINN,Provides the status of the trigger inputs" line.long 0x4 "APBADDR_CTI_CPU1_CTITRIGOUTSTATUS,CTI Trigger Out Status Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--7. 1. "TROUTN,Provides the status of the trigger outputs" line.long 0x8 "APBADDR_CTI_CPU1_CTICHINSTATUS,CTI Channel In Status Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x8 0.--3. 1. "CHINN,Provides the raw status of the ECT channel inputs to the CTI" line.long 0xC "APBADDR_CTI_CPU1_CTICHOUTSTATUS,CTI Channel Out Status Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0xC 0.--3. 1. "CHOUTN,Provides the status of the ECT channel outputs from the CTI" line.long 0x10 "APBADDR_CTI_CPU1_CTIGATE,CTI Channel Gate Enable Register" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x10 0.--3. 1. "GATEX,Determines whether events on channels propagate through the CTM to other ECT components or from the CTM into the CTI" line.long 0x14 "APBADDR_CTI_CPU1_ASICCTL,CTI External Multiplexor Control register" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_ASICCTL_31_8,Reserved RES0." hexmask.long.byte 0x14 0.--7. 1. "ASICCTL,IMPLEMENTATION DEFINED ASIC control. Provides a control for external multiplexing of additional triggers into the CTI.If external multiplexing of trigger signals is implemented then the number of multiplexed signals on each trigger must be.." group.long 0xF00++0x3 line.long 0x0 "APBADDR_CTI_CPU1_CTIITCTRL,CTI Integration mode Control Register" hexmask.long 0x0 1.--31. 1. "RES0_CTIITCTRL_31_1,Reserved RES0." bitfld.long 0x0 0. "IME,Integration mode enable. When IME == 1 the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED. 0 Normal operation." "0,1" group.long 0xFA0++0x5F line.long 0x0 "APBADDR_CTI_CPU1_CTICLAIMSET,CTI Claim Set" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--3. 1. "CLAIMX,CLAIM tag set bit" line.long 0x4 "APBADDR_CTI_CPU1_CTICLAIMCLR,CTI Claim Clear" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "CLAIMX,Clear CLAIM tag" line.long 0x8 "APBADDR_CTI_CPU1_CTIDEVAFF0,CTI Device Affinity Register 0" hexmask.long 0x8 0.--31. 1. "CTIDEVAFF0,MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0xC "APBADDR_CTI_CPU1_CTIDEVAFF1,CTI Device Affinity Register 1" hexmask.long 0xC 0.--31. 1. "CTIDEVAFF1,MPIDR_EL1 high half. Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x10 "APBADDR_CTI_CPU1_CTILAR,CTI Lock Access Register" hexmask.long 0x10 0.--31. 1. "KEY,Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register locks the lock disabling write.." line.long 0x14 "APBADDR_CTI_CPU1_CTILSR,CTI Lock Status Register" hexmask.long 0x14 3.--31. 1. "RES0_CTILSR_31_3,Reserved RES0." bitfld.long 0x14 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" bitfld.long 0x14 1. "SLK,Software lock status for this component. For an access to LSR that is not a memory-mapped access or when the software lock is not implemented this field is RES0.For memory-mapped accesses when the software lock is implemented possible values of.." "0,1" newline bitfld.long 0x14 0. "SLI,Software lock implemented. For an access to LSR that is not a memory-mapped access this field is RAZ. For memory-mapped accesses the value of this field is IMPLEMENTATION DEFINED. Permitted values are: 0 Software lock not.." "0,1" line.long 0x18 "APBADDR_CTI_CPU1_CTIAUTHSTATUS,CTI Authentication Status Register" hexmask.long 0x18 4.--31. 1. "RES0_CTIAUTHSTATUS_31_4,Reserved RES0." bitfld.long 0x18 2.--3. "NSNID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SNID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSNID." "0,1,2,3" bitfld.long 0x18 0.--1. "NSID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSID." "0,1,2,3" line.long 0x1C "APBADDR_CTI_CPU1_CTIDEVARCH,CTI Device Architecture Register" hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For CTI this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A." "0,1" hexmask.long.byte 0x1C 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For CTI the revision defined by v8-A is 0x0.All other values are reserved." newline hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For CTI:Bits [15:12] are the architecture version 0x1.Bits [11:0] are the architecture part number 0xA14.This corresponds to CTI.." line.long 0x20 "APBADDR_CTI_CPU1_CTIDEVID2,CTI Device ID Register 2" hexmask.long 0x20 0.--31. 1. "RES0_CTIDEVID2_31_0,Reserved RES0." line.long 0x24 "APBADDR_CTI_CPU1_CTIDEVID1,CTI Device ID Register 1" hexmask.long 0x24 0.--31. 1. "RES0_CTIDEVID1_31_0,Reserved RES0." line.long 0x28 "APBADDR_CTI_CPU1_CTIDEVID,CTI Device ID Register 0" hexmask.long.byte 0x28 26.--31. 1. "RES0_CTIDEVID_31_26,Reserved RES0." bitfld.long 0x28 24.--25. "INOUT,Input/output options. Indicates presence of the input gate. If the CTM is not implemented this field is RAZ. 00 CTIGATE does not mask propagation of input events from external channels. 01.." "0,1,2,3" bitfld.long 0x28 22.--23. "RES0_CTIDEVID_23_22,Reserved RES0." "0,1,2,3" newline hexmask.long.byte 0x28 16.--21. 1. "NUMCHAN,Number of ECT channels implemented. IMPLEMENTATION DEFINED. For v8-A valid values are: 000011 3 channels [0..2] implemented. 000100 4 channels [0..3] implemented." bitfld.long 0x28 14.--15. "RES0_CTIDEVID_15_14,Reserved RES0." "0,1,2,3" hexmask.long.byte 0x28 8.--13. 1. "NUMTRIG,Number of triggers implemented. IMPLEMENTATION DEFINED. This is one more than the index of the largest trigger rather than the actual number of triggers.For v8-A valid values are: 000011 Up to 3 triggers [0..2] implemented." newline bitfld.long 0x28 5.--7. "RES0_CTIDEVID_7_5,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 0.--4. 1. "EXTMUXNUM,Maximum number of external triggers available for multiplexing into the CTI. This relates only to additional external triggers outside those defined for v8-A." line.long 0x2C "APBADDR_CTI_CPU1_CTIDEVTYPE,CTI Device Type Register" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_CTIDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x2C 4.--7. 1. "SUB,Subtype. Must read as 0x1 to indicate this is a processor component." hexmask.long.byte 0x2C 0.--3. 1. "MAJOR,Major type. Must read as 0x4 to indicate this is a cross-trigger component." line.long 0x30 "APBADDR_CTI_CPU1_CTIPIDR4,CTI Peripheral Identification Register 4" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_CTIPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x30 4.--7. 1. "SIZE,Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers." hexmask.long.byte 0x30 0.--3. 1. "DES_2,Designer JEP106 continuation code least significant nibble. For ARM Limited this field is 0b0100." line.long 0x34 "APBADDR_CTI_CPU1_CTIPIDR5,CTI Peripheral Identification Register 5" hexmask.long 0x34 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x38 "APBADDR_CTI_CPU1_CTIPIDR6,CTI Peripheral Identification Register 6" hexmask.long 0x38 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x3C "APBADDR_CTI_CPU1_CTIPIDR7,CTI Peripheral Identification Register 7" hexmask.long 0x3C 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x40 "APBADDR_CTI_CPU1_CTIPIDR0,CTI Peripheral Identification Register 0" hexmask.long.tbyte 0x40 8.--31. 1. "RES0_CTIPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x40 0.--7. 1. "PART_0,Part number least significant byte." line.long 0x44 "APBADDR_CTI_CPU1_CTIPIDR1,CTI Peripheral Identification Register 1" hexmask.long.tbyte 0x44 8.--31. 1. "RES0_CTIPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x44 4.--7. 1. "DES_0,Designer least significant nibble of JEP106 ID code. For ARM Limited this field is 0b1011." hexmask.long.byte 0x44 0.--3. 1. "PART_1,Part number most significant nibble." line.long 0x48 "APBADDR_CTI_CPU1_CTIPIDR2,CTI Peripheral Identification Register 2" hexmask.long.tbyte 0x48 8.--31. 1. "RES0_CTIPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x48 4.--7. 1. "REVISION,Part major revision. Parts can also use this field to extend Part number to 16-bits." bitfld.long 0x48 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" newline bitfld.long 0x48 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0x4C "APBADDR_CTI_CPU1_CTIPIDR3,CTI Peripheral Identification Register 3" hexmask.long.tbyte 0x4C 8.--31. 1. "RES0_CTIPIDR3_31_8,Reserved RES0." hexmask.long.byte 0x4C 4.--7. 1. "REVAND,Part minor revision. Parts using CTIPIDR2.REVISION as an extension to the Part number must use this field as a major revision number." hexmask.long.byte 0x4C 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x50 "APBADDR_CTI_CPU1_CTICIDR0,CTI Component Identification Register 0" hexmask.long.tbyte 0x50 8.--31. 1. "RES0_CTICIDR0_31_8,Reserved RES0." hexmask.long.byte 0x50 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x54 "APBADDR_CTI_CPU1_CTICIDR1,CTI Component Identification Register 1" hexmask.long.tbyte 0x54 8.--31. 1. "RES0_CTICIDR1_31_8,Reserved RES0." hexmask.long.byte 0x54 4.--7. 1. "CLASS,Component class. Reads as 0x9 debug component." hexmask.long.byte 0x54 0.--3. 1. "PRMBL_1,Preamble. RAZ." line.long 0x58 "APBADDR_CTI_CPU1_CTICIDR2,CTI Component Identification Register 2" hexmask.long.tbyte 0x58 8.--31. 1. "RES0_CTICIDR2_31_8,Reserved RES0." hexmask.long.byte 0x58 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x5C "APBADDR_CTI_CPU1_CTICIDR3,CTI Component Identification Register 3" hexmask.long.tbyte 0x5C 8.--31. 1. "RES0_CTICIDR3_31_8,Reserved RES0." hexmask.long.byte 0x5C 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree "A53SS0_CORE1_DBG" base ad:0x730110000 group.long 0x20++0x7 line.long 0x0 "APBADDR_DBG_CPU1_EDESR,External Debug Event Status Register" hexmask.long 0x0 3.--31. 1. "RES0_EDESR_31_3,Reserved RES0." bitfld.long 0x0 2. "SS,Halting step debug event pending. Possible values of this field are: 0 Reading this means that a Halting step debug event is not pending. Writing this means no action. 1 Reading this means that.." "0,1" newline bitfld.long 0x0 1. "RC,Reset catch debug event pending. Possible values of this field are: 0 Reading this means that a Reset catch debug event is not pending. Writing this means no action. 1 Reading this means that a.." "0,1" bitfld.long 0x0 0. "OSUC,OS unlock debug event pending. Possible values of this field are: 0 Reading this means that an OS unlock catch debug event is not pending. Writing this means no action. 1 Reading this means.." "0,1" line.long 0x4 "APBADDR_DBG_CPU1_EDECR,External Debug Execution Control Register" hexmask.long 0x4 3.--31. 1. "RES0_EDECR_31_3,Reserved RES0." bitfld.long 0x4 2. "SS,Halting step enable. Possible values of this field are: 0 Halting step debug event disabled. 1 Halting step debug event enabled. If the value of EDECR.SS is changed when the.." "0,1" newline bitfld.long 0x4 1. "RCE,Reset catch enable. Possible values of this field are: 0 Reset catch debug event disabled. 1 Reset catch debug event enabled." "0,1" bitfld.long 0x4 0. "OSUCE,OS unlock catch enabled. Possible values of this field are: 0 OS unlock catch debug event disabled. 1 OS unlock catch debug event enabled." "0,1" group.long 0x30++0x7 line.long 0x0 "APBADDR_DBG_CPU1_EDWAR_31_0,External Debug Watchpoint Address Register (low word)" hexmask.long 0x0 0.--31. 1. "EDWAR_31_0,Watchpoint address. The virtual data address being accessed when a watchpoint debug event was triggered and caused entry to Debug state.UNKNOWN if the processor is not in Debug state or if Debug state was entered other than for a watchpoint.." line.long 0x4 "APBADDR_DBG_CPU1_EDWAR_63_32,External Debug Watchpoint Address Register (high word)" hexmask.long 0x4 0.--31. 1. "EDWAR_63_32,Watchpoint address. The virtual data address being accessed when a watchpoint debug event was triggered and caused entry to Debug state.UNKNOWN if the processor is not in Debug state or if Debug state was entered other than for a watchpoint.." group.long 0x80++0x1B line.long 0x0 "APBADDR_DBG_CPU1_DBGDTRRX_EL0,Debug Data Transfer Register Receive" hexmask.long 0x0 0.--31. 1. "DBGDTRRX_EL0,Update DTRRX. Writes to this register update the value in DTRRX and set RXfull to 1.Reads of this register return the last value written to DTRRX and do not change RXfull." line.long 0x4 "APBADDR_DBG_CPU1_EDITR,External Debug Instruction Transfer Register" hexmask.long 0x4 0.--31. 1. "EDITR,Used in Debug state for passing instructions to the processor for execution" line.long 0x8 "APBADDR_DBG_CPU1_EDSCR,External Debug Status and Control Register" bitfld.long 0x8 31. "RES0_EDSCR_31_31,Reserved RES0." "0,1" bitfld.long 0x8 30. "RXFULL,DTRRX full. This bit is RO." "0,1" newline bitfld.long 0x8 29. "TXFULL,DTRTX full. This bit is RO." "0,1" bitfld.long 0x8 28. "ITO,EDITR overrun. This bit is RO.If the processor is not in Debug state this bit is UNKNOWN. ITO is set to 0 on entry to Debug state." "0,1" newline bitfld.long 0x8 27. "RXO,DTRRX overrun. This bit is RO." "0,1" bitfld.long 0x8 26. "TXU,DTRTX underrun. This bit is RO." "0,1" newline bitfld.long 0x8 25. "PIPEADV,Pipeline advance. Read-only. Set to 1 every time the processor pipeline retires one or more instructions. Cleared to 0 by a write to EDRCR.CSPA.The architecture does not define precisely when this bit is set to 1. It requires only that this.." "0,1" bitfld.long 0x8 24. "ITE,ITR empty. This bit is RO.If the processor is not in Debug state this bit is UNKNOWN. It is always valid in Debug state." "0,1" newline bitfld.long 0x8 22.--23. "INTDIS,Interrupt disable. Disables taking interrupts [including virtual interrupts and System Error interrupts] in Non-Debug state.If external invasive debug is disabled the value of this field is ignored.If external invasive debug is enabled the.." "0,1,2,3" bitfld.long 0x8 21. "TDA,Trap debug registers accesses." "0,1" newline bitfld.long 0x8 20. "MA,Memory access mode. Controls use of memory-access mode for accessing EDITR and the DCC. This bit is ignored if in Non-debug state and set to zero on entry to Debug state.Possible values of this field are: 0 Normal access mode.." "0,1" bitfld.long 0x8 19. "RES0_EDSCR_19_19,Reserved RES0." "0,1" newline bitfld.long 0x8 18. "NS,Non-secure status. Read-only. When in Debug state gives the current security state: 0 Secure state IsSecure[] == TRUE 1 Non-secure state IsSecure[] == FALSE. In Non-debug.." "0,1" bitfld.long 0x8 17. "RES0_EDSCR_17_17,Reserved RES0." "0,1" newline bitfld.long 0x8 16. "SDD,Secure debug disabled. This bit is RO.On entry to Debug state:If entering in Secure state SDD is set to 0.If entering in Non-secure state SDD is set to the inverse of ExternalSecureInvasiveDebugEnabled[].In Debug state the value of the SDD bit.." "0,1" bitfld.long 0x8 15. "RES0_EDSCR_15_15,Reserved RES0." "0,1" newline bitfld.long 0x8 14. "HDE,Halting debug mode enable. Possible values of this bit are: 0 Halting debug mode disabled. 1 Halting debug mode enabled." "0,1" hexmask.long.byte 0x8 10.--13. 1. "RW,Exception level register-width status. Read-only. In Debug state each bit gives the current register width status of each EL: 1111 All exception levels are AArch64 state. 1110 EL0 is AArch32.." newline bitfld.long 0x8 8.--9. "EL,Exception level. Read-only. In Debug state this gives the current EL of the processor.In Non-debug state this field is RAZ." "0,1,2,3" bitfld.long 0x8 7. "A,System Error interrupt pending. Read-only. In Debug state indicates whether a SError interrupt is pending:If HCR_EL2.{AMO TGE} = {1 0} and in Non-secure EL0 or EL1 a virtual SError interrupt.Otherwise a physical SError interrupt. 0.." "0,1" newline bitfld.long 0x8 6. "ERR,Cumulative error flag. This field is RO. It is set to 1 following exceptions in Debug state and on any signaled overrun or underrun on the DTR or EDITR." "0,1" hexmask.long.byte 0x8 0.--5. 1. "STATUS,Debug status flags. This field is RO.The possible values of this field are: 000010 Processor is in Non-debug state. 000001 Processor is restarting [exiting Debug state]." line.long 0xC "APBADDR_DBG_CPU1_DBGDTRTX_EL0,Debug Data Transfer Register Transmit" hexmask.long 0xC 0.--31. 1. "DBGDTRTX_EL0,Return DTRTX. Reads of this register return the value in DTRTX and clear TXfull to 0.Writes of this register update the value in DTRTX and do not change TXfull." line.long 0x10 "APBADDR_DBG_CPU1_EDRCR,External Debug Reserve Control Register" hexmask.long 0x10 5.--31. 1. "RES0_EDRCR_31_5,Reserved RES0." bitfld.long 0x10 4. "CBRRQ,Allow imprecise entry to Debug state. The actions on writing to this bit are: 0 No action. 1 Allow imprecise entry to Debug state for example by canceling pending bus accesses." "0,1" newline bitfld.long 0x10 3. "CSPA,Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The actions on writing to this bit are: 0 No action. 1 Clear the EDSCR.PipeAdv bit to 0." "0,1" bitfld.long 0x10 2. "CSE,Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The actions on writing to this bit are: 0 No action. 1 Clear the EDSCR.{TXU RXO ERR} bits and if the processor is in.." "0,1" newline bitfld.long 0x10 0.--1. "RES0_EDRCR_1_0,Reserved RES0." "0,1,2,3" line.long 0x14 "APBADDR_DBG_CPU1_EDACR,External Debug Auxiliary Control Register" hexmask.long 0x14 0.--31. 1. "RES0_EDACR_31_0,Reserved RES0" line.long 0x18 "APBADDR_DBG_CPU1_EDECCR,External Debug Exception Catch Control Register" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDECCR_31_8,Reserved RES0." hexmask.long.byte 0x18 4.--7. 1. "NSE,Coarse-grained Non-secure exception catch. Possible values of this field are: 0000 Exception catch debug event disabled for Non-secure exception levels. 0010 Exception catch debug event enabled.." newline hexmask.long.byte 0x18 0.--3. 1. "SE,Coarse-grained Secure exception catch. Possible values of this field are: 0000 Exception catch debug event disabled for Secure exception levels. 0010 Exception catch debug event enabled for.." group.long 0xA0++0xF line.long 0x0 "APBADDR_DBG_CPU1_EDPCSR_31_0,External Debug Program Counter Sample Register (low word)" hexmask.long 0x0 0.--31. 1. "EDPCSR_31_0,PC Sample low word EDPCSRlo. Bits [31:0] of the sampled instruction address value. Reading EDPCSRlo has the side-effect of updating EDCIDSR EDVIDSR and EDPCSRhi. However:If the processor is in Debug state or Sample-based profiling is.." line.long 0x4 "APBADDR_DBG_CPU1_EDCIDSR,External Debug Context ID Sample Register" hexmask.long 0x4 0.--31. 1. "CONTEXTIDR,The sampled value of CONTEXTIDR_EL1 captured on reading the low half of EDPCSR.If EL3 is implemented and using AArch32 then CONTEXTIDR is a Banked register and EDCIDSR samples the current Banked copy of CONTEXTIDR." line.long 0x8 "APBADDR_DBG_CPU1_EDVIDSR,External Debug Virtual Context Sample Register" bitfld.long 0x8 31. "NS,Non-secure state sample. Indicates the security state associated with the most recent EDPCSR sample." "0,1" bitfld.long 0x8 30. "E2,Exception level 2 status sample. Indicates whether the most recent EDPCSR sample was associated with EL2. If EDVIDSR.NS == 0 this bit is 0." "0,1" newline bitfld.long 0x8 29. "E3,Exception level 3 status sample. Indicates whether the most recent EDPCSR sample was associated with AArch64 EL3. If EDVIDSR.NS == 1 or the processor was in AArch32 state when EDPCSR was read this bit is 0." "0,1" bitfld.long 0x8 28. "HV,EDPCSR high half valid. Indicates whether bits [63:32] of the most recent EDPCSR sample are valid. If EDVIDSR.HV == 0 the value of EDPCSR[63:32] is RAZ." "0,1" newline hexmask.long.tbyte 0x8 8.--27. 1. "RES0_EDVIDSR_27_8,Reserved RES0." hexmask.long.byte 0x8 0.--7. 1. "VMID,VMID sample. The value of VTTBR_EL2.VMID associated with the most recent EDPCSR sample. If EDVIDSR.NS == 0 or EDVIDSR.E2 == 1 this field is RAZ." line.long 0xC "APBADDR_DBG_CPU1_EDPCSR_63_32,External Debug Program Counter Sample Register (high word)" hexmask.long 0xC 0.--31. 1. "EDPCSR_63_32,PC Sample high word EDPCSRhi. If EDVIDSR.HV == 0 then this field is RAZ otherwise bits [63:32] of the sampled PC." group.long 0x300++0x3 line.long 0x0 "APBADDR_DBG_CPU1_OSLAR_EL1,OS Lock Access Register" hexmask.long 0x0 1.--31. 1. "RES0_OSLAR_EL1_31_1,Reserved RES0." bitfld.long 0x0 0. "OSLK,On writes to OSLAR_EL1 bit[0] is copied to the OS lock.Use EDPRSR.OSLK to check the current status of the lock." "0,1" group.long 0x310++0x7 line.long 0x0 "APBADDR_DBG_CPU1_EDPRCR,External Debug Power/Reset Control Register" hexmask.long 0x0 4.--31. 1. "RES0_EDPRCR_31_4,Reserved RES0." bitfld.long 0x0 3. "COREPURQ,Core powerup request. Allows a debugger to request that the power controller power up the core enabling access to the debug register in the Core power domain. The actions on writing to this bit are: 0 No effect." "0,1" newline bitfld.long 0x0 2. "RES0_EDPRCR_2_2,Reserved RES0." "0,1" bitfld.long 0x0 1. "CWRR,Warm reset request. Write only bit that reads as zero. The actions on writing to this bit are: 0 No action. 1 Request Warm reset. The processor ignores writes to this bit if.." "0,1" newline bitfld.long 0x0 0. "CORENPDRQ,Core no powerdown request. Requests emulation of powerdown. Possible values of this bit are: 0 On a powerdown request the system powers down the Core power domain. 1 On a powerdown.." "0,1" line.long 0x4 "APBADDR_DBG_CPU1_EDPRSR,External Debug Processor Status Register" hexmask.long.tbyte 0x4 12.--31. 1. "RES0_EDPRSR_31_12,Reserved RES0." bitfld.long 0x4 11. "SDR,Sticky debug restart. Set to 1 when the processor exits Debug state and cleared to 0 following reads of EDPRSR. 0 The processor has not restarted since EDPRSR was last read. 1 The processor has.." "0,1" newline bitfld.long 0x4 10. "SPMAD,Sticky EPMAD error. Set to 1 if an access returns an error because AllowExternalPMUAccess[] == FALSE. 0 No accesses to the external performance monitors registers have failed since EDPRSR was last read. 1.." "0,1" bitfld.long 0x4 9. "EPMAD,External performance monitors access disable status. 0 External performance monitors access enabled. 1 External performance monitors access disabled. If external performance.." "0,1" newline bitfld.long 0x4 8. "SDAD,Sticky EDAD error. Set to 1 if an access returns an error because AllowExternalDebugAccess[] == FALSE. 0 No accesses to the external debug registers have failed since EDPRSR was last read. 1.." "0,1" bitfld.long 0x4 7. "EDAD,External debug access disable status. 0 External debug access enabled. 1 External debug access disabled. This bit is UNKNOWN on reads if either of EDPRSR.{DLK R} is 1 or.." "0,1" newline bitfld.long 0x4 6. "DLK,OS Double Lock status bit. 0 OSDLR_EL1.DLK == 0 or EDPRCR.CORENPDRQ == 1 or the processor is in Debug state. 1 OSDLR_EL1.DLK == 1 and EDPRCR.CORENPDRQ == 0 and the processor is in Non-debug.." "0,1" bitfld.long 0x4 5. "OSLK,OS lock status bit. A read of this bit returns the value of OSLSR_EL1.OSLK.This bit is UNKNOWN on reads if either of EDPRSR.{DLK R} is 1 or EDPRSR.PU is 0." "0,1" newline bitfld.long 0x4 4. "HALTED,Halted status bit. Possible values are: 0 EDSCR.STATUS is 0b000010 [processor in Non-debug state]. 1 EDSCR.STATUS is not 0b000010. This bit is UNKNOWN on reads if EDPRSR.PU.." "0,1" bitfld.long 0x4 3. "SR,Sticky core reset status bit. Possible values are: 0 The non-debug logic of the processor is not in reset state and has not been reset since the last time EDPRSR was read. 1 The non-debug logic.." "0,1" newline bitfld.long 0x4 2. "R,Core reset status bit. Possible values are: 0 The non-debug logic of the processor is not in reset state. 1 The non-debug logic of the processor is in reset state. This bit is.." "0,1" bitfld.long 0x4 1. "SPD,Sticky core power-down status bit.This bit is set to 1 on Cold reset to indicate the state of the debug registers has been lost. Since a Cold reset is required on powering up the processor this usually indicates the Core power domain has been.." "0,1" newline bitfld.long 0x4 0. "PU,Core power-up status bit. Indicates whether the Core power domain debug registers can be accessed: 0 Core is in a low-power or power-down state where the debug registers cannot be accessed. 1.." "0,1" group.long 0x400++0xB line.long 0x0 "APBADDR_DBG_CPU1_DBGBVR0_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR0_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR0_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU1_DBGBVR0_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR0_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR0_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU1_DBGBCR0_EL1,Debug Breakpoint Control Register 0" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR0_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR0_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR0_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x410++0xB line.long 0x0 "APBADDR_DBG_CPU1_DBGBVR1_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR1_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR1_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU1_DBGBVR1_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR1_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR1_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU1_DBGBCR1_EL1,Debug Breakpoint Control Register 1" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR1_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR1_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR1_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x420++0xB line.long 0x0 "APBADDR_DBG_CPU1_DBGBVR2_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR2_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR2_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU1_DBGBVR2_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR2_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR2_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU1_DBGBCR2_EL1,Debug Breakpoint Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR2_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR2_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR2_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x430++0xB line.long 0x0 "APBADDR_DBG_CPU1_DBGBVR3_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR3_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR3_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU1_DBGBVR3_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR3_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR3_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU1_DBGBCR3_EL1,Debug Breakpoint Control Register 3" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR3_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR3_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR3_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x440++0xB line.long 0x0 "APBADDR_DBG_CPU1_DBGBVR4_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR4_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR4_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU1_DBGBVR4_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR4_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR4_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU1_DBGBCR4_EL1,Debug Breakpoint Control Register 4" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR4_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR4_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR4_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x450++0xB line.long 0x0 "APBADDR_DBG_CPU1_DBGBVR5_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR5_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR5_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU1_DBGBVR5_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR5_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR5_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU1_DBGBCR5_EL1,Debug Breakpoint Control Register 5" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR5_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR5_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR5_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x800++0xB line.long 0x0 "APBADDR_DBG_CPU1_DBGWVR0_EL1_31_0,Debug Watchpoint Value Register 0" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR0_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU1_DBGWVR0_EL1_63_32,Debug Watchpoint Extended Value Register 0" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU1_DBGWCR0_EL1,Debug Watchpoint Control Register 0" bitfld.long 0x8 29.--31. "RES0_DBGWCR0_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR0_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0x810++0xB line.long 0x0 "APBADDR_DBG_CPU1_DBGWVR1_EL1_31_0,Debug Watchpoint Value Register 1" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR1_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU1_DBGWVR1_EL1_63_32,Debug Watchpoint Extended Value Register 1" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU1_DBGWCR1_EL1,Debug Watchpoint Control Register 1" bitfld.long 0x8 29.--31. "RES0_DBGWCR1_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR1_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0x820++0xB line.long 0x0 "APBADDR_DBG_CPU1_DBGWVR2_EL1_31_0,Debug Watchpoint Value Register 2" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR2_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU1_DBGWVR2_EL1_63_32,Debug Watchpoint Extended Value Register 2" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU1_DBGWCR2_EL1,Debug Watchpoint Control Register 2" bitfld.long 0x8 29.--31. "RES0_DBGWCR2_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR2_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0x830++0xB line.long 0x0 "APBADDR_DBG_CPU1_DBGWVR3_EL1_31_0,Debug Watchpoint Value Register 3" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR3_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU1_DBGWVR3_EL1_63_32,Debug Watchpoint Extended Value Register 3" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU1_DBGWCR3_EL1,Debug Watchpoint Control Register 3" bitfld.long 0x8 29.--31. "RES0_DBGWCR3_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR3_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0xD00++0x3 line.long 0x0 "APBADDR_DBG_CPU1_MIDR_EL1,Main ID Register" hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,The Implementer code. This field must hold an implementer code that has been assigned by ARM." hexmask.long.byte 0x0 20.--23. 1. "VARIANT,An IMPLEMENTATION DEFINED variant number. Typically this field is used to distinguish between different product variants or major revisions of a product." newline hexmask.long.byte 0x0 16.--19. 1. "ARCHITECTURE" hexmask.long.word 0x0 4.--15. 1. "PARTNUM,An IMPLEMENTATION DEFINED primary part number for the device. On processors implemented by ARM if the top four bits of the primary part number are 0x0 or 0x7 the variant and architecture are encoded differently" newline hexmask.long.byte 0x0 0.--3. 1. "REVISION,An IMPLEMENTATION DEFINED revision number for the device" group.long 0xD20++0x3F line.long 0x0 "APBADDR_DBG_CPU1_ID_AA64PFR0_EL1_31_0,Processor Feature Register 0 (low word)" hexmask.long.byte 0x0 28.--31. 1. "RES0_ID_AA64PFR0_EL1_31_0_31_28,Reserved RES0." hexmask.long.byte 0x0 24.--27. 1. "GIC,GIC system register interface. Permitted values are: 0000 No GIC system registers are supported. 0001 GICv3 system registers are supported. All other values are reserved." newline hexmask.long.byte 0x0 20.--23. 1. "ADVSIMD,Advanced SIMD. Permitted values are: 0000 Advanced SIMD is implemented. 1111 Advanced SIMD is not implemented. All other values are reserved." hexmask.long.byte 0x0 16.--19. 1. "FP,Floating-point. Permitted values are: 0000 Floating-point is implemented. 1111 Floating-point is not implemented. All other values are reserved." newline hexmask.long.byte 0x0 12.--15. 1. "EL3,EL3 exception level handling. Permitted values are: 0000 EL3 is not implemented. 0001 EL3 can be executed in AArch64 state only. 0010 EL3 can be executed.." hexmask.long.byte 0x0 8.--11. 1. "EL2,EL2 exception level handling. Permitted values are: 0000 EL2 is not implemented. 0001 EL2 can be executed in AArch64 state only. 0010 EL2 can be executed.." newline hexmask.long.byte 0x0 4.--7. 1. "EL1,EL1 exception level handling. Permitted values are: 0000 EL1 is not implemented. 0001 EL1 can be executed in AArch64 state only. 0010 EL1 can be executed.." hexmask.long.byte 0x0 0.--3. 1. "EL0,EL0 exception level handling. Permitted values are: 0000 EL0 is not implemented. 0001 EL0 can be executed in AArch64 state only. 0010 EL0 can be executed.." line.long 0x4 "APBADDR_DBG_CPU1_ID_AA64PFR0_EL1_63_32,Processor Feature Register 0 (high word)" hexmask.long 0x4 0.--31. 1. "RES0_ID_AA64PFR0_EL1_63_32_31_0,Reserved RES0." line.long 0x8 "APBADDR_DBG_CPU1_ID_AA64DFR0_EL1_31_0,Debug Feature Register 0 (low word)" hexmask.long.byte 0x8 28.--31. 1. "CTX_CMPS,Number of breakpoints that are context-aware minus 1. These are the highest numbered breakpoints." hexmask.long.byte 0x8 24.--27. 1. "RES0_ID_AA64DFR0_EL1_31_0_27_24,Reserved RES0." newline hexmask.long.byte 0x8 20.--23. 1. "WRPS,Number of watchpoints minus 1. The value of 0b0000 is reserved." hexmask.long.byte 0x8 16.--19. 1. "RES0_ID_AA64DFR0_EL1_31_0_19_16,Reserved RES0." newline hexmask.long.byte 0x8 12.--15. 1. "BRPS,Number of breakpoints minus 1. The value of 0b0000 is reserved." hexmask.long.byte 0x8 8.--11. 1. "PMUVER,Performance Monitors extension version. Indicates whether system register interface to Performance Monitors extension is implemented. Permitted values are: 0000 Performance Monitors extension system registers not implemented." newline hexmask.long.byte 0x8 4.--7. 1. "TRACEVER,Trace extension. Indicates whether system register interface to Trace extension is implemented. Permitted values are: 0000 Trace extension system registers not implemented. 0001 Trace.." hexmask.long.byte 0x8 0.--3. 1. "DEBUGVER,Debug architecture version. Indicates presence of v8-A debug architecture. 0110 v8-A debug architecture. All other values are reserved." line.long 0xC "APBADDR_DBG_CPU1_ID_AA64DFR0_EL1_63_32,Debug Feature Register 0 (high word)" hexmask.long 0xC 0.--31. 1. "RES0_ID_AA64DFR0_EL1_63_32_31_0,Reserved RES0." line.long 0x10 "APBADDR_DBG_CPU1_ID_AA64ISAR0_EL1_31_0,Instruction Set Attribute Register 0 (low word)" hexmask.long.word 0x10 20.--31. 1. "RES0_ID_AA64ISAR0_EL1_31_0_31_20,Reserved RES0." hexmask.long.byte 0x10 16.--19. 1. "CRC32,CRC32 instructions in AArch64. Possible values of this field are: 0000 No CRC32 instructions implemented. 0001 CRC32B CRC32H CRC32W CRC32X CRC32CB CRC32CH CRC32CW and CRC32CX.." newline hexmask.long.byte 0x10 12.--15. 1. "SHA2,SHA2 instructions in AArch64. Possible values of this field are: 0000 No SHA2 instructions implemented. 0001 SHA256H SHA256H2 SHA256SU0 and SHA256SU1 instructions implemented." hexmask.long.byte 0x10 8.--11. 1. "SHA1,SHA1 instructions in AArch64. Possible values of this field are: 0000 No SHA1 instructions implemented. 0001 SHA1C SHA1P SHA1M SHA1H SHA1SU0 and SHA1SU1 instructions implemented." newline hexmask.long.byte 0x10 4.--7. 1. "AES,AES instructions in AArch64. Possible values of this field are: 0000 No AES instructions implemented. 0001 AESE AESD AESMC and AESIMC instructions implemented. 0010.." hexmask.long.byte 0x10 0.--3. 1. "RES0_ID_AA64ISAR0_EL1_31_0_3_0,Reserved RES0." line.long 0x14 "APBADDR_DBG_CPU1_ID_AA64ISAR0_EL1_63_32,Instruction Set Attribute Register 0 (high word)" hexmask.long 0x14 0.--31. 1. "RES0_ID_AA64ISAR0_EL1_63_32_31_0,Reserved RES0." line.long 0x18 "APBADDR_DBG_CPU1_ID_AA64MMFR0_EL1_31_0,Memory Model Feature Register 0 (low word)" hexmask.long.byte 0x18 28.--31. 1. "TGRAN4,Support for 4 Kbyte memory translation granule size. Permitted values are: 0000 4 KB granule supported. 1111 4 KB granule not supported. All other values are reserved." hexmask.long.byte 0x18 24.--27. 1. "TGRAN64,Support for 64 Kbyte memory translation granule size. Permitted values are: 0000 64 KB granule supported. 1111 64 KB granule not supported. All other values are reserved." newline hexmask.long.byte 0x18 20.--23. 1. "TGRAN16,Support for 16 Kbyte memory translation granule size. Permitted values are: 0000 16 KB granule not supported. 0001 16 KB granule supported. All other values are reserved." hexmask.long.byte 0x18 16.--19. 1. "BIGENDEL0,Mixed-endian support at EL0 only. Permitted values are: 0000 No mixed-endian support at EL0. The SCTLR_EL1.E0E bit has a fixed value. 0001 Mixed-endian support at EL0. The SCTLR_EL1.E0E.." newline hexmask.long.byte 0x18 12.--15. 1. "SNSMEM,Secure versus Non-secure Memory distinction. Permitted values are: 0000 Does not support a distinction between Secure and Non-secure Memory. 0001 Does support a distinction between Secure.." hexmask.long.byte 0x18 8.--11. 1. "BIGEND,Mixed-endian configuration support. Permitted values are: 0000 No mixed-endian support. The SCTLR_ELx.EE bits have a fixed value. See the BigEndEL0 field bits[19:16] for whether EL0 supports mixed-endian." newline hexmask.long.byte 0x18 4.--7. 1. "ASIDBITS,Number of ASID bits. Permitted values are: 0000 8 bits. 0010 16 bits. All other values are reserved." hexmask.long.byte 0x18 0.--3. 1. "PARANGE,Physical Address range supported. Permitted values are: 0000 32 bits 4 GB. 0001 36 bits 64 GB. 0010 40 bits 1 TB. 0011.." line.long 0x1C "APBADDR_DBG_CPU1_ID_AA64MMFR0_EL1_63_32,Memory Model Feature Register 0 (high word)" hexmask.long 0x1C 0.--31. 1. "RES0_ID_AA64MMFR0_EL1_63_32_31_0,Reserved RES0." line.long 0x20 "APBADDR_DBG_CPU1_ID_AA64PFR1_EL1_31_0,Processor Feature Register 1 (low word)" hexmask.long 0x20 0.--31. 1. "RES0_ID_AA64PFR1_EL1_31_0_31_0,Reserved RES0." line.long 0x24 "APBADDR_DBG_CPU1_ID_AA64PFR1_EL1_63_32,Processor Feature Register 1 (high word)" hexmask.long 0x24 0.--31. 1. "RES0_ID_AA64PFR1_EL1_63_32_31_0,Reserved RES0." line.long 0x28 "APBADDR_DBG_CPU1_ID_AA64DFR1_EL1_31_0,Auxiliary Feature Register 1 (low word)" hexmask.long 0x28 0.--31. 1. "RES0_ID_AA64DFR1_EL1_31_0_31_0,Reserved RES0." line.long 0x2C "APBADDR_DBG_CPU1_ID_AA64DFR1_EL1_63_32,Auxiliary Feature Register 1 (high word)" hexmask.long 0x2C 0.--31. 1. "RES0_ID_AA64DFR1_EL1_63_32_31_0,Reserved RES0." line.long 0x30 "APBADDR_DBG_CPU1_ID_AA64ISAR1_EL1_31_0,Instruction Set Attribute Register 1 (low word)" hexmask.long 0x30 0.--31. 1. "RES0_ID_AA64ISAR1_EL1_31_0_31_0,Reserved RES0." line.long 0x34 "APBADDR_DBG_CPU1_ID_AA64ISAR1_EL1_63_32,Instruction Set Attribute Register 1 (high word)" hexmask.long 0x34 0.--31. 1. "RES0_ID_AA64ISAR1_EL1_63_32_31_0,Reserved RES0." line.long 0x38 "APBADDR_DBG_CPU1_ID_AA64MMFR1_EL1_31_0,Memory Model Feature Register 1 (low word)" hexmask.long 0x38 0.--31. 1. "RES0_ID_AA64MMFR1_EL1_31_0_31_0,Reserved RES0." line.long 0x3C "APBADDR_DBG_CPU1_ID_AA64MMFR1_EL1_63_32,Memory Model Feature Register 1 (high word)" hexmask.long 0x3C 0.--31. 1. "RES0_ID_AA64MMFR1_EL1_63_32_31_0,Reserved RES0." group.long 0xF00++0x3 line.long 0x0 "APBADDR_DBG_CPU1_EDITCTRL,External Debug Integration mode Control Register" hexmask.long 0x0 1.--31. 1. "RES0_EDITCTRL_31_1,Reserved RES0." bitfld.long 0x0 0. "IME,Integration mode enable. When IME == 1 the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED. 0 Normal operation." "0,1" group.long 0xFA0++0x33 line.long 0x0 "APBADDR_DBG_CPU1_DBGCLAIMSET_EL1,Debug Claim Tag Set Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_DBGCLAIMSET_EL1_31_8,Reserved RAZ/SBZ. Software can rely on these bits reading as zero and must use a should-be-zero policy on writes. Implementations must ignore writes." hexmask.long.byte 0x0 0.--7. 1. "CLAIM,Claim set bits. RAO.Writing a 1 to one of these bits sets the corresponding CLAIM bit to 1. This is an indirect write to the CLAIM bits.A single write operation can set multiple bits to 1. Writing 0 to one of these bits has no effect." line.long 0x4 "APBADDR_DBG_CPU1_DBGCLAIMCLR_EL1,Debug Claim Tag Clear Register" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_DBGCLAIMCLR_EL1_31_8,Reserved RAZ/SBZ. Software can rely on these bits reading as zero and must use a should-be-zero policy on writes. Implementations must ignore writes." hexmask.long.byte 0x4 0.--7. 1. "CLAIM,Claim clear bits. Reading this field returns the current value of the CLAIM bits.Writing a 1 to one of these bits clears the corresponding CLAIM bit to 0. This is an indirect write to the CLAIM bits.A single write operation can clear multiple bits.." line.long 0x8 "APBADDR_DBG_CPU1_EDDEVAFF0,External Debug Device Affinity Register 0" hexmask.long 0x8 0.--31. 1. "EDDEVAFF0,MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0xC "APBADDR_DBG_CPU1_EDDEVAFF1,External Debug Device Affinity Register 1" hexmask.long 0xC 0.--31. 1. "EDDEVAFF1,MPIDR_EL1 high half. Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x10 "APBADDR_DBG_CPU1_EDLAR,External Debug Lock Access Register" hexmask.long 0x10 0.--31. 1. "KEY,Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register locks the lock disabling write.." line.long 0x14 "APBADDR_DBG_CPU1_EDLSR,External Debug Lock Status Register" hexmask.long 0x14 3.--31. 1. "RES0_EDLSR_31_3,Reserved RES0." bitfld.long 0x14 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" newline bitfld.long 0x14 1. "SLK,Software lock status for this component. For an access to LSR that is not a memory-mapped access or when the software lock is not implemented this field is RES0.For memory-mapped accesses when the software lock is implemented possible values of.." "0,1" bitfld.long 0x14 0. "SLI,Software lock implemented. For an access to LSR that is not a memory-mapped access this field is RAZ. For memory-mapped accesses the value of this field is IMPLEMENTATION DEFINED. Permitted values are: 0 Software lock not.." "0,1" line.long 0x18 "APBADDR_DBG_CPU1_DBGAUTHSTATUS_EL1,Debug Authentication Status register" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_DBGAUTHSTATUS_EL1_31_8,Reserved RES0." bitfld.long 0x18 6.--7. "SNID,Secure non-invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Non-secure. 10 Implemented and disabled." "0,1,2,3" newline bitfld.long 0x18 4.--5. "SID,Secure invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Non-secure. 10 Implemented and disabled." "0,1,2,3" bitfld.long 0x18 2.--3. "NSNID,Non-secure non-invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Secure. 10 Implemented and disabled." "0,1,2,3" newline bitfld.long 0x18 0.--1. "NSID,Non-secure invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Secure. 10 Implemented and disabled." "0,1,2,3" line.long 0x1C "APBADDR_DBG_CPU1_EDDEVARCH,External Debug Device Architecture Register" hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For debug this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A." "0,1" newline hexmask.long.byte 0x1C 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For debug the revision defined by v8-A is 0x0.All other values are reserved." hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For debug:Bits [15:12] are the architecture version 0x6.Bits [11:0] are the architecture part number 0xA15.This corresponds to debug.." line.long 0x20 "APBADDR_DBG_CPU1_EDDEVID2,External Debug Device ID Register 2" hexmask.long 0x20 0.--31. 1. "RES0_EDDEVID2_31_0,Reserved RES0." line.long 0x24 "APBADDR_DBG_CPU1_EDDEVID1,External Debug Device ID Register 1" hexmask.long 0x24 4.--31. 1. "RES0_EDDEVID1_31_4,Reserved RES0." hexmask.long.byte 0x24 0.--3. 1. "PCSROFFSET,This field indicates the offset applied to PC samples returned by reads of EDPCSR. Permitted values of this field in v8-A are: 0000 EDPCSR not implemented. 0010 EDPCSR implemented and.." line.long 0x28 "APBADDR_DBG_CPU1_EDDEVID,External Debug Device ID Register 0" hexmask.long.byte 0x28 28.--31. 1. "RES0_EDDEVID_31_28,Reserved RES0." hexmask.long.byte 0x28 24.--27. 1. "AUXREGS,Indicates support for Auxiliary registers. Permitted values for this field are: 0000 None supported. 0001 Support for External Debug Auxiliary Control Register EDACR. All.." newline hexmask.long.tbyte 0x28 4.--23. 1. "RES0_EDDEVID_23_4,Reserved RES0." hexmask.long.byte 0x28 0.--3. 1. "PCSAMPLE,Indicates the level of Sample-based profiling support using external debug registers 40 through 43. Permitted values of this field in v8-A are: 0000 Architecture-defined form of Sample-based profiling not implemented." line.long 0x2C "APBADDR_DBG_CPU1_EDDEVTYPE,External Debug Device Type Register" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_EDDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x2C 4.--7. 1. "SUB,Subtype. Must read as 0x1 to indicate this is a processor component." newline hexmask.long.byte 0x2C 0.--3. 1. "MAJOR,Major type. Must read as 0x5 to indicate this is a debug logic component." line.long 0x30 "APBADDR_DBG_CPU1_EDPIDR4,External Debug Peripheral Identification Register 4" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_EDPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x30 4.--7. 1. "SIZE,Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers." newline hexmask.long.byte 0x30 0.--3. 1. "DES_2,Designer JEP106 continuation code least significant nibble. For ARM Limited this field is 0b0100." group.long 0xFE0++0x1F line.long 0x0 "APBADDR_DBG_CPU1_EDPIDR0,External Debug Peripheral Identification Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_EDPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x0 0.--7. 1. "PART_0,Part number least significant byte." line.long 0x4 "APBADDR_DBG_CPU1_EDPIDR1,External Debug Peripheral Identification Register 1" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_EDPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x4 4.--7. 1. "DES_0,Designer least significant nibble of JEP106 ID code. For ARM Limited this field is 0b1011." newline hexmask.long.byte 0x4 0.--3. 1. "PART_1,Part number most significant nibble." line.long 0x8 "APBADDR_DBG_CPU1_EDPIDR2,External Debug Peripheral Identification Register 2" hexmask.long.tbyte 0x8 8.--31. 1. "RES0_EDPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x8 4.--7. 1. "REVISION,Part major revision. Parts can also use this field to extend Part number to 16-bits." newline bitfld.long 0x8 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" bitfld.long 0x8 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0xC "APBADDR_DBG_CPU1_EDPIDR3,External Debug Peripheral Identification Register 3" hexmask.long.tbyte 0xC 8.--31. 1. "RES0_EDPIDR3_31_8,Reserved RES0." hexmask.long.byte 0xC 4.--7. 1. "REVAND,Part minor revision. Parts using EDPIDR2.REVISION as an extension to the Part number must use this field as a major revision number." newline hexmask.long.byte 0xC 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x10 "APBADDR_DBG_CPU1_EDCIDR0,External Debug Component Identification Register 0" hexmask.long.tbyte 0x10 8.--31. 1. "RES0_EDCIDR0_31_8,Reserved RES0." hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x14 "APBADDR_DBG_CPU1_EDCIDR1,External Debug Component Identification Register 1" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_EDCIDR1_31_8,Reserved RES0." hexmask.long.byte 0x14 4.--7. 1. "CLASS,Component class. Reads as 0x9 debug component." newline hexmask.long.byte 0x14 0.--3. 1. "PRMBL_1,Preamble. RAZ." line.long 0x18 "APBADDR_DBG_CPU1_EDCIDR2,External Debug Component Identification Register 2" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDCIDR2_31_8,Reserved RES0." hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x1C "APBADDR_DBG_CPU1_EDCIDR3,External Debug Component Identification Register 3" hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_EDCIDR3_31_8,Reserved RES0." hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree "A53SS0_CORE1_ECC_AGGR" base ad:0x718800 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_CORE1_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_CORE1_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_CORE1_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR_CORE1_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_CORE1_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_CORE1_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 26. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 25. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 24. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 23. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_CORE1_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 26. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_CORE1_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 26. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_CORE1_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_CORE1_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 26. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 25. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 24. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 23. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_CORE1_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 26. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_CORE1_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 26. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_CORE1_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_CORE1_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_CORE1_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_CORE1_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "A53SS0_CORE1_ETM" base ad:0x730130000 group.long 0x4++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCPRGCTLR,Programming Control Register" hexmask.long 0x0 1.--31. 1. "RES0_TRCPRGCTLR_31_1,Reserved RES0." bitfld.long 0x0 0. "EN,Trace unit enable bit. Possible values are: 0 The trace unit is disabled. All trace resources are inactive and no trace is generated. 1 The trace unit is enabled." "0,1" group.long 0xC++0x7 line.long 0x0 "APBADDR_ETM_CPU1_TRCSTATR,Status Register" hexmask.long 0x0 2.--31. 1. "RES0_TRCSTATR_31_2,Reserved RES0." bitfld.long 0x0 1. "PMSTABLE,Programmer's model stable bit: 0 The programmer's model is not stable. 1 The programmer's model is stable. When polled the trace unit trace registers return stable data." "0,1" bitfld.long 0x0 0. "IDLE,Idle status bit: 0 The trace unit is not idle. 1 The trace unit is idle. The trace unit is idle when all of the following are true:TRCPRGCTLR.EN==0 or the OS Lock is.." "0,1" line.long 0x4 "APBADDR_ETM_CPU1_TRCCONFIGR,Trace Configuration Register" hexmask.long.word 0x4 18.--31. 1. "RES0_TRCCONFIGR_31_18,Reserved RES0." bitfld.long 0x4 17. "DV,Data value tracing bit: 0 Data value tracing is disabled. 1 Data value tracing is enabled when INSTP0 is not 0b00. TRCIDR0.TRCDATA indicates whether this bit is supported. If.." "0,1" bitfld.long 0x4 16. "DA,Data address tracing bit: 0 Data address tracing is disabled. 1 Data address tracing is enabled when INSTP0 is not 0b00. TRCIDR0.TRCDATA indicates whether this bit is.." "0,1" newline bitfld.long 0x4 15. "RES0_TRCCONFIGR_15_15,Reserved RES0." "0,1" bitfld.long 0x4 13.--14. "QE,Q element enable field: 00 Q elements are disabled. 01 Q elements with instruction counts are enabled. Q elements without instruction counts are disabled. 11.." "0,1,2,3" bitfld.long 0x4 12. "RS,Return stack enable bit. 0 Return stack is disabled. 1 Return stack is enabled. TRCIDR0.RETSTACK indicates whether this bit is supported. If it is not supported then this bit.." "0,1" newline bitfld.long 0x4 11. "TS,Global timestamp tracing bit: 0 Global timestamp tracing is disabled. 1 Global timestamp tracing is enabled. TRCTSCTLR controls the insertion of timestamps in the trace." "0,1" bitfld.long 0x4 8.--10. "COND,Conditional instruction tracing bit. The permitted values are: 000 Conditional instruction tracing is disabled. 001 Conditional load instructions are traced. 010.." "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "VMID,VMID tracing bit: 0 VMID tracing is disabled. 1 VMID tracing is enabled. TRCIDR2.VMIDSIZE indicates whether this bit is supported. If it is not supported then this bit is RES0." "0,1" newline bitfld.long 0x4 6. "CID,Context ID tracing bit: 0 Context ID tracing is disabled. 1 Context ID tracing is enabled. TRCIDR2.CIDSIZE indicates whether this bit is supported. If it is not supported then.." "0,1" bitfld.long 0x4 5. "RES0_TRCCONFIGR_5_5,Reserved RES0." "0,1" bitfld.long 0x4 4. "CCI,Cycle counting instruction trace bit: 0 Cycle counting in the instruction trace is disabled. 1 Cycle counting in the instruction trace is enabled. TRCCCCTLR controls the threshold value for.." "0,1" newline bitfld.long 0x4 3. "BB,Branch broadcast mode bit: 0 Branch broadcast mode is disabled. 1 Branch broadcast mode is enabled. TRCBBCTLR controls which regions of memory are enabled to use branch broadcasting." "0,1" bitfld.long 0x4 1.--2. "INSTP0,Instruction P0 bit. This field controls whether load and store instructions are traced as P0 instructions: 00 Do not trace load and store instructions as P0 instructions. 01 Trace load.." "0,1,2,3" bitfld.long 0x4 0. "RES1_TRCCONFIGR_0_0,Reserved RES1." "0,1" group.long 0x18++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCAUXCTLR,Auxiliary Control Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_TRCAUXCTLR_31_8,Reserved RES0" bitfld.long 0x0 7. "COREIFEN,Keep core interface enabled regardless of trace enable register state" "0,1" bitfld.long 0x0 6. "RES0_TRCAUXCTLR_6_6,Reserved RES0" "0,1" newline bitfld.long 0x0 5. "AUTHNOFLUSH,Do not flush trace on de-assertion of authentication inputs. When this bit is set to 1 the trace unit behavior deviates from architecturally-specified behavior." "0,1" bitfld.long 0x0 4. "TSNODELAY,Do not delay timestamp insertion based on FIFO depth." "0,1" bitfld.long 0x0 3. "SYNCDELAY,Delay periodic synchronization if FIFO is more than half-full." "0,1" newline bitfld.long 0x0 2. "OVFLW,Force an overflow if synchronization is not completed when second synchronization becomes due. When this bit is set to 1 the trace unit behavior deviates from architecturally-specified behavior." "0,1" bitfld.long 0x0 1. "IDLEACK,Force idle-drain acknowledge high CPU does not wait for trace to drain before entering WFX state. When this bit is set to 1 trace unit behavior deviates from architecturally-specified behavior." "0,1" bitfld.long 0x0 0. "AFREADY,Always respond to AFREADY immediately. Does not have any interaction with FIFO draining even in WFI state." "0,1" group.long 0x20++0x7 line.long 0x0 "APBADDR_ETM_CPU1_TRCEVENTCTL0R,Event Control 0 Register" bitfld.long 0x0 31. "TYPE3,Selects the resource type for trace event 3" "0,1" bitfld.long 0x0 28.--30. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--27. 1. "SEL3,Selects the resource number based on the value of TYPE3" newline bitfld.long 0x0 23. "TYPE2,Selects the resource type for trace event 2" "0,1" bitfld.long 0x0 20.--22. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--19. 1. "SEL2,Selects the resource number based on the value of TYPE2" newline bitfld.long 0x0 15. "TYPE1,Selects the resource type for trace event 1" "0,1" bitfld.long 0x0 12.--14. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "SEL1,Selects the resource number based on the value of TYPE1" newline bitfld.long 0x0 7. "TYPE0,Selects the resource type for trace event 0" "0,1" bitfld.long 0x0 4.--6. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "SEL0,Selects the resource number based on the value of TYPE0" line.long 0x4 "APBADDR_ETM_CPU1_TRCEVENTCTL1R,Event Control 1 Register" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved RES0" bitfld.long 0x4 12. "LPOVERRIDE,Low power state behavior override" "0,1" bitfld.long 0x4 11. "ATB,ATB trigger enable" "0,1" newline hexmask.long.byte 0x4 4.--10. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "EN,One bit per event to enable generation of an event element in the instruction trace stream when the selected event occurs" group.long 0x2C++0x17 line.long 0x0 "APBADDR_ETM_CPU1_TRCSTALLCTLR,Stall Control Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved RES0" bitfld.long 0x0 8. "ISTALL,Controls if the trace unit can stall the processor when the instruction trace buffer space is less than LEVEL" "0,1" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved RES0" newline bitfld.long 0x0 2.--3. "LEVEL,The field can support 4 monotonic levels from 0b00 to 0b11" "0,1,2,3" bitfld.long 0x0 0.--1. "RESERVED,Reserved RES0" "0,1,2,3" line.long 0x4 "APBADDR_ETM_CPU1_TRCTSCTLR,Global Timestamp Control Register" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_TRCTSCTLR_31_8,Reserved RES0." hexmask.long.byte 0x4 0.--7. 1. "EVENT,An event selector. When the selected event is triggered the trace unit inserts a global timestamp into the trace streams." line.long 0x8 "APBADDR_ETM_CPU1_TRCSYNCPR,Synchronization Period Register" hexmask.long 0x8 5.--31. 1. "RES0_TRCSYNCPR_31_5,Reserved RES0." hexmask.long.byte 0x8 0.--4. 1. "PERIOD,Controls how many bytes of trace the sum of instruction and data that a trace unit can generate before a periodic trace synchronization request occurs. The number of bytes is always a power of two and the permitted values are: 00000.." line.long 0xC "APBADDR_ETM_CPU1_TRCCCCTLR,Cycle Count Control Register" hexmask.long.tbyte 0xC 12.--31. 1. "RES0_TRCCCCTLR_31_12,Reserved RES0." hexmask.long.word 0xC 0.--11. 1. "THRESHOLD,Sets the threshold value for instruction trace cycle counting.The minimum threshold value that can be programmed into THRESHOLD is given in TRCIDR3.CCITMIN.Writing a value of zero might cause UNPREDICTABLE behaviour." line.long 0x10 "APBADDR_ETM_CPU1_TRCBBCTLR,Branch Broadcast Control Register" hexmask.long.tbyte 0x10 9.--31. 1. "RES0_TRCBBCTLR_31_9,Reserved RES0." bitfld.long 0x10 8. "MODE,Mode bit: 0 Exclude mode. Branch broadcasting is not enabled in the address range that RANGE defines. If RANGE==0 then branch broadcasting is enabled for the entire memory map. 1 Include mode." "0,1" hexmask.long.byte 0x10 0.--7. 1. "RANGE,Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each bit represents an address range comparator pair so bit[n] controls the selection of address range comparator pair n. If bit[n] is: 0.." line.long 0x14 "APBADDR_ETM_CPU1_TRCTRACEIDR,Trace ID Register" hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x14 0.--6. 1. "TRACEID,Trace ID value. When only instruction tracing is enabled this provides the trace ID." group.long 0x80++0xB line.long 0x0 "APBADDR_ETM_CPU1_TRCVICTLR,ViewInst Main Control Register" hexmask.long.byte 0x0 24.--31. 1. "RES0_TRCVICTLR_31_24,Reserved RES0." hexmask.long.byte 0x0 20.--23. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Non-secure state for exception level n." hexmask.long.byte 0x0 16.--19. 1. "EXLEVEL_S,In Secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Secure state for exception level n. 1.." newline hexmask.long.byte 0x0 12.--15. 1. "RES0_TRCVICTLR_15_12,Reserved RES0." bitfld.long 0x0 11. "TRCERR,If TRCIDR3.TRCERR==1 this bit controls whether a trace unit must trace a system error exception: 0 The trace unit does not trace a system error exception unless it traces the exception or instruction immediately prior to the.." "0,1" bitfld.long 0x0 10. "TRCRESET,Controls whether a trace unit must trace a Reset exception: 0 The trace unit does not trace a Reset exception unless it traces the exception or instruction immediately prior to the Reset exception. 1.." "0,1" newline bitfld.long 0x0 9. "SSSTATUS,IF TRCIDR4.NUMACPAIRS>0 or TRCIDR.NUMPC>0 this bit returns the status of the start-stop logic: 0 The start-stop logic is in the stopped state. 1 The start-stop logic is in the started.." "0,1" bitfld.long 0x0 8. "RES0_TRCVICTLR_8_8,Reserved RES0." "0,1" hexmask.long.byte 0x0 0.--7. 1. "EVENT,An event selector. [TODO: Add the bit assignments for EVENT fields into the descriptions directly?]" line.long 0x4 "APBADDR_ETM_CPU1_TRCVIIECTLR,ViewInst Include-Exclude Control Register" hexmask.long.byte 0x4 24.--31. 1. "RES0_TRCVIIECTLR_31_24,Reserved RES0." hexmask.long.byte 0x4 16.--23. 1. "EXCLUDE,0 1 The implemented width of the field n is IMPLEMENTATION DEFINED and is set by the value of TRCIDR4.NUMACPAIRS. Unimplemented bits are RAZ/WI." hexmask.long.byte 0x4 8.--15. 1. "RES0_TRCVIIECTLR_15_8,Reserved RES0." newline hexmask.long.byte 0x4 0.--7. 1. "INCLUDE,Include range field. Selects which address range comparator pairs are in use with ViewInst include control. Each bit represents an address range comparator pair so bit[m] controls the selection of address range comparator pair m. If bit[m] is:.." line.long 0x8 "APBADDR_ETM_CPU1_TRCVISSCTLR,ViewInst Start-Stop Control Register" hexmask.long.word 0x8 16.--31. 1. "STOP,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of stopping trace. Each bit represents a single address comparator so bit[m] controls the selection of single address comparator m-16. If bit[m].." hexmask.long.word 0x8 0.--15. 1. "START,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of starting trace. Each bit represents a single address comparator so bit[n] controls the selection of single address comparator n. If bit[n] is:.." group.long 0x100++0xB line.long 0x0 "APBADDR_ETM_CPU1_TRCSEQEVR0,Sequencer State Transition Control Registers 0" hexmask.long.word 0x0 16.--31. 1. "RES0_TRCSEQEVR0_31_16,Reserved RES0." hexmask.long.byte 0x0 8.--15. 1. "B_N,Backward field. Contains an event number. When the event occurs then the sequencer state moves from state n+1 to state n.For example for TRCSEQEVR2 if B2==0x14 then when event 0x14 occurs the sequencer moves from state 3 to state 2." hexmask.long.byte 0x0 0.--7. 1. "F_N,Forward field. Contains an event number. When the event occurs then the sequencer state moves from state n to state n+1.For example for TRCSEQEVR1 if F1==0x12 then when event 0x12 occurs the sequencer moves from state 1 to state 2." line.long 0x4 "APBADDR_ETM_CPU1_TRCSEQEVR1,Sequencer State Transition Control Registers 1" hexmask.long.word 0x4 16.--31. 1. "RES0_TRCSEQEVR1_31_16,Reserved RES0." hexmask.long.byte 0x4 8.--15. 1. "B_N,Backward field. Contains an event number. When the event occurs then the sequencer state moves from state n+1 to state n.For example for TRCSEQEVR2 if B2==0x14 then when event 0x14 occurs the sequencer moves from state 3 to state 2." hexmask.long.byte 0x4 0.--7. 1. "F_N,Forward field. Contains an event number. When the event occurs then the sequencer state moves from state n to state n+1.For example for TRCSEQEVR1 if F1==0x12 then when event 0x12 occurs the sequencer moves from state 1 to state 2." line.long 0x8 "APBADDR_ETM_CPU1_TRCSEQEVR2,Sequencer State Transition Control Registers 2" hexmask.long.word 0x8 16.--31. 1. "RES0_TRCSEQEVR2_31_16,Reserved RES0." hexmask.long.byte 0x8 8.--15. 1. "B_N,Backward field. Contains an event number. When the event occurs then the sequencer state moves from state n+1 to state n.For example for TRCSEQEVR2 if B2==0x14 then when event 0x14 occurs the sequencer moves from state 3 to state 2." hexmask.long.byte 0x8 0.--7. 1. "F_N,Forward field. Contains an event number. When the event occurs then the sequencer state moves from state n to state n+1.For example for TRCSEQEVR1 if F1==0x12 then when event 0x12 occurs the sequencer moves from state 1 to state 2." group.long 0x118++0xB line.long 0x0 "APBADDR_ETM_CPU1_TRCSEQRSTEVR,Sequencer Reset Control Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_TRCSEQRSTEVR_31_8,Reserved RES0." hexmask.long.byte 0x0 0.--7. 1. "RST,Contains an event number. When the event occurs then the sequencer state moves to state 0." line.long 0x4 "APBADDR_ETM_CPU1_TRCSEQSTR,Sequencer State Register" hexmask.long 0x4 2.--31. 1. "RES0_TRCSEQSTR_31_2,Reserved RES0." bitfld.long 0x4 0.--1. "STATE,Sets or returns the state of the sequencer: 00 State 0. 01 State 1. 10 State 2. 11 State 3." "0,1,2,3" line.long 0x8 "APBADDR_ETM_CPU1_TRCEXTINSELR,External Input Select Register" bitfld.long 0x8 29.--31. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "SEL3,Selects an event from the external input bus for External Input Resource 3." bitfld.long 0x8 21.--23. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 16.--20. 1. "SEL2,Selects an event from the external input bus for External Input Resource 2" bitfld.long 0x8 13.--15. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--12. 1. "SEL1,Selects an event from the external input bus for External Input Resource 1" newline bitfld.long 0x8 5.--7. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--4. 1. "SEL0,Selects an event from the external input bus for External Input Resource 0" group.long 0x140++0x7 line.long 0x0 "APBADDR_ETM_CPU1_TRCCNTRLDVR0,Counter Reload Value Registers 0" hexmask.long.word 0x0 16.--31. 1. "RES0_TRCCNTRLDVR0_31_16,Reserved RES0." hexmask.long.word 0x0 0.--15. 1. "VALUE_N,Contains the reload value for counter . When a reload event occurs for counter then the trace unit copies the VALUE field into counter ." line.long 0x4 "APBADDR_ETM_CPU1_TRCCNTRLDVR1,Counter Reload Value Registers 1" hexmask.long.word 0x4 16.--31. 1. "RES0_TRCCNTRLDVR1_31_16,Reserved RES0." hexmask.long.word 0x4 0.--15. 1. "VALUE_N,Contains the reload value for counter . When a reload event occurs for counter then the trace unit copies the VALUE field into counter ." group.long 0x150++0x7 line.long 0x0 "APBADDR_ETM_CPU1_TRCCNTCTLR0,Counter Control Register 0" hexmask.long.word 0x0 18.--31. 1. "RES0_TRCCNTCTLR0_31_18,Reserved RES0." bitfld.long 0x0 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter decrements when a reload event occurs for counter : 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit.." "0,1" bitfld.long 0x0 16. "RLDSELF_N,Controls whether a reload event occurs for counter when counter reaches zero: 0 The trace unit does not generate a reload event. 1 The trace unit generates a reload event for.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter ." hexmask.long.byte 0x0 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter to decrement." line.long 0x4 "APBADDR_ETM_CPU1_TRCCNTCTLR1,Counter Control Register 1" hexmask.long.word 0x4 18.--31. 1. "RES0_TRCCNTCTLR1_31_18,Reserved RES0." bitfld.long 0x4 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter decrements when a reload event occurs for counter : 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit.." "0,1" bitfld.long 0x4 16. "RLDSELF_N,Controls whether a reload event occurs for counter when counter reaches zero: 0 The trace unit does not generate a reload event. 1 The trace unit generates a reload event for.." "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter ." hexmask.long.byte 0x4 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter to decrement." group.long 0x160++0x7 line.long 0x0 "APBADDR_ETM_CPU1_TRCCNTVR0,Counter Value Registers 0" hexmask.long.word 0x0 16.--31. 1. "RES0_TRCCNTVR0_31_16,Reserved RES0." hexmask.long.word 0x0 0.--15. 1. "VALUE_N,Contains the count value of counter ." line.long 0x4 "APBADDR_ETM_CPU1_TRCCNTVR1,Counter Value Registers 1" hexmask.long.word 0x4 16.--31. 1. "RES0_TRCCNTVR1_31_16,Reserved RES0." hexmask.long.word 0x4 0.--15. 1. "VALUE_N,Contains the count value of counter ." group.long 0x180++0x17 line.long 0x0 "APBADDR_ETM_CPU1_TRCIDR8,ID Register 8" hexmask.long 0x0 0.--31. 1. "MAXSPEC,Indicates the maximum speculation depth of the instruction trace stream. This is the maximum number of P0 elements in the trace stream that can be speculative at any time." line.long 0x4 "APBADDR_ETM_CPU1_TRCIDR9,ID Register 9" hexmask.long 0x4 0.--31. 1. "NUMP0KEY,Indicates the number of P0 right-hand keys that the trace unit can use. A value of 0 or 1 indicates one P0 key." line.long 0x8 "APBADDR_ETM_CPU1_TRCIDR10,ID Register 10" hexmask.long 0x8 0.--31. 1. "NUMP1KEY,Indicates the number of P1 right-hand keys that the trace unit can use. The number includes normal and special keys." line.long 0xC "APBADDR_ETM_CPU1_TRCIDR11,ID Register 11" hexmask.long 0xC 0.--31. 1. "NUMP1SPC,Indicates the number of special P1 right-hand keys that the trace unit can use." line.long 0x10 "APBADDR_ETM_CPU1_TRCIDR12,ID Register 12" hexmask.long 0x10 0.--31. 1. "NUMCONDKEY,Indicates the number of conditional instruction right-hand keys that the trace unit can use. The number includes normal and special keys." line.long 0x14 "APBADDR_ETM_CPU1_TRCIDR13,ID Register 13" hexmask.long 0x14 0.--31. 1. "NUMCONDSPC,Indicates the number of special conditional instruction right-hand keys that the trace unit can use." group.long 0x1C0++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCIMSPEC0,Implementation Specific Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_TRCIMSPEC0_31_8,Reserved RES0." hexmask.long.byte 0x0 4.--7. 1. "EN,If SUPPORT is not 0b0000 controls whether the IMPLEMENTATION DEFINED features are enabled. The permitted values are: 0000 The IMPLEMENTATION DEFINED features are not enabled. The trace unit must behave as if the IMPLEMENTATION.." hexmask.long.byte 0x0 0.--3. 1. "SUPPORT,Indicates whether the implementation supports IMPLEMENTATION DEFINED features. The permitted values are: 0000 No IMPLEMENTATION DEFINED features are supported. The EN field is RES0. and any other value which.." group.long 0x1E0++0x17 line.long 0x0 "APBADDR_ETM_CPU1_TRCIDR0,ID Register 0" bitfld.long 0x0 30.--31. "RES0_TRCIDR0_31_30,Reserved RES0." "0,1,2,3" bitfld.long 0x0 29. "COMMOPT,Conditional instruction tracing support bit. Indicates if the trace unit supports conditional instruction tracing: 0 Conditional instruction tracing is not supported. 1 Conditional.." "0,1" hexmask.long.byte 0x0 24.--28. 1. "TSSIZE,Global timestamp size field. The permitted values are: 00000 Global timestamping is not implemented. 00110 Implementation supports a maximum global timestamp of 48bits." newline hexmask.long.byte 0x0 17.--23. 1. "RES0_TRCIDR0_23_17,Reserved RES0." bitfld.long 0x0 15.--16. "QSUPP,Q element support field. The permitted values are: 00 Q element support is not implemented. TRCCONFIGR.QE is RES0. 01 Q element support is implemented and only supports Q elements with.." "0,1,2,3" bitfld.long 0x0 14. "QFILT,Q element filtering support field. The permitted values are: 0 Q element filtering is not implemented. 1 Q element filtering is implemented. TRCQCTLR is implemented. When.." "0,1" newline bitfld.long 0x0 12.--13. "CONDTYPE,Conditional tracing field. The permitted values are: 00 The trace unit indicates only if a conditional instruction is a pass or fail. 01 The trace unit provides the Current Program Status.." "0,1,2,3" bitfld.long 0x0 10.--11. "NUMEVENT,Number of events field. Indicates how many events the trace unit supports: 00 The trace unit supports 1 event. 01 The trace unit supports 2 events. 10.." "0,1,2,3" bitfld.long 0x0 9. "RETSTACK,Return stack bit. Indicates if the implementation supports a return stack: 0 Return stack is not implemented. 1 Return stack is implemented so TRCCONFIGR.RS is supported." "0,1" newline bitfld.long 0x0 8. "RES0_TRCIDR0_8_8,Reserved RES0." "0,1" bitfld.long 0x0 7. "TRCCCI,Cycle counting instruction bit. Indicates if the trace unit supports cycle counting for instructions: 0 Cycle counting in the instruction trace is not implemented. 1 Cycle counting in the.." "0,1" bitfld.long 0x0 6. "TRCCOND,Conditional instruction tracing support bit. Indicates if the trace unit supports conditional instruction tracing: 0 Conditional instruction tracing is not supported. 1 Conditional.." "0,1" newline bitfld.long 0x0 5. "TRCBB,Branch broadcast tracing support bit. Indicates if the trace unit supports branch broadcast tracing: 0 Branch broadcast tracing is not supported. 1 Branch broadcast tracing is supported so.." "0,1" bitfld.long 0x0 3.--4. "TRCDATA,Conditional tracing field. The permitted values are: 00 Data tracing is not supported. 11 Tracing of data addresses and data values is supported so TRCCONFIGR.DA TRCCONFIGR.DV .." "0,1,2,3" bitfld.long 0x0 1.--2. "INSTP0,P0 tracing support field. The permitted values are: 00 Tracing of load and store instructions as P0 elements is not supported. 11 Tracing of load and store instructions as P0 elements is.." "0,1,2,3" newline bitfld.long 0x0 0. "RES0_TRCIDR0_0_0,Reserved RES0." "0,1" line.long 0x4 "APBADDR_ETM_CPU1_TRCIDR1,ID Register 1" hexmask.long.byte 0x4 24.--31. 1. "DESIGNER,Indicates which company designed the trace unit. The permitted values are: 01000001 ARM Limited. 01000100 Digital Equipment Corporation. 01001101.." hexmask.long.byte 0x4 16.--23. 1. "RES0_TRCIDR1_23_16,Reserved RES0." hexmask.long.byte 0x4 12.--15. 1. "RES1_TRCIDR1_15_12,Reserved RES1." newline hexmask.long.byte 0x4 8.--11. 1. "TRCARCHMAJ,Indicates the major version of the ETM architecture. The permitted value is: 100 ETMv4. All other values are reserved." hexmask.long.byte 0x4 4.--7. 1. "TRCARCHMIN,Indicates the minor version of the ETM architecture. The permitted value is: 0 ETMv4 minor version 0. All other values are reserved." hexmask.long.byte 0x4 0.--3. 1. "REVISION,Returns an IMPLEMENTATION DEFINED value that identifies the revision of the trace registers and the OS Save and Restore registers.ARM recommends:That the initial implementation sets REVISION==0x0 and the field then increments for any subsequent.." line.long 0x8 "APBADDR_ETM_CPU1_TRCIDR2,ID Register 2" bitfld.long 0x8 29.--31. "RES0_TRCIDR2_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 25.--28. 1. "CCSIZE,Indicates the size of the cycle counter in bits minus 12. 0000 The cycle counter is 12 bits in length. 0001 The cycle counter is 13 bits in length. and so on up to 0b1000 .." hexmask.long.byte 0x8 20.--24. 1. "DVSIZE,Indicates the data value size in bytes. The permitted values are: 00000 Data value tracing is not supported. Therefore an implementation must also set TRCIDR0.TRCDATA==0b00. 00100 Maximum.." newline hexmask.long.byte 0x8 15.--19. 1. "DASIZE,Indicates the data address size in bytes. The permitted values are: 00000 Data address tracing is not supported. Therefore an implementation must also set TRCIDR0.TRCDATA==0b00. 00100.." hexmask.long.byte 0x8 10.--14. 1. "VMIDSIZE,Indicates the VMID size. The permitted values are: 00000 VMID tracing is not supported. 00001 Maximum of 8-bit VMID size so TRCCONFIGR.VMID is supported. All other.." hexmask.long.byte 0x8 5.--9. 1. "CIDSIZE,Indicates the Context ID size. The permitted values are: 00000 Context ID tracing is not supported. 00100 Maximum of 32-bit Context ID size so TRCCONFIGR.CID is supported." newline hexmask.long.byte 0x8 0.--4. 1. "IASIZE,Indicates the instruction address size. The permitted values are: 00100 Maximum of 32-bit address size. 01000 Maximum of 64-bit address size. All other values are reserved." line.long 0xC "APBADDR_ETM_CPU1_TRCIDR3,ID Register 3" bitfld.long 0xC 31. "NOOVERFLOW,Indicates if TRCSTALLCTLR.NOOVERFLOW is supported: 0 TRCSTALLCTLR.NOOVERFLOW is not supported or STALLCTL==0. 1 TRCSTALLCTLR.NOOVERFLOW is supported." "0,1" bitfld.long 0xC 28.--30. "NUMPROC,Indicates the number of processors available for tracing. The possible values are: 000 The trace unit can trace one processor. 001 The trace unit can trace two processors." "0,1,2,3,4,5,6,7" bitfld.long 0xC 27. "SYSSTALL,Indicates if the implementation can support stall control: 0 The system does not support stall control of the processor. 1 The system can support stall control of the processor." "0,1" newline bitfld.long 0xC 26. "STALLCTL,Indicates if TRCSTALLCTLR is supported: 0 TRCSTALLCTLR is not supported. 1 TRCSTALLCTLR is supported." "0,1" bitfld.long 0xC 25. "SYNCPR,Indicates if an implementation has a fixed synchronization period: 0 TRCSYNCPR is read-write so software can change the synchronization period. 1 TRCSYNCPR is read-only so the.." "0,1" bitfld.long 0xC 24. "TRCERR,Indicates if TRCVICTLR.TRCERR is supported: 0 TRCVICTLR.TRCERR is not supported 1 TRCVICTLR.TRCERR is supported." "0,1" newline hexmask.long.byte 0xC 20.--23. 1. "EXLEVEL_NS,In Non-secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Non-secure state exception level n is not supported so the corresponding bits in.." hexmask.long.byte 0xC 16.--19. 1. "EXLEVEL_S,In Secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Secure state exception level n is not supported so the corresponding bits in TRCACATRn.EXLEVEL_S and.." hexmask.long.byte 0xC 12.--15. 1. "RES0_TRCIDR3_15_12,Reserved RES0." newline hexmask.long.word 0xC 0.--11. 1. "CCITMIN,Indicates the minimum value that can be programmed in TRCCCCTLR.THRESHOLD.When cycle counting in the instruction trace is supported that is TRCIDR0.TRCCCI==1 then the minimum value of this field is 0x001 otherwise it is 0x000." line.long 0x10 "APBADDR_ETM_CPU1_TRCIDR4,ID Register 4" hexmask.long.byte 0x10 28.--31. 1. "NUMVMIDC,Indicates the number of VMID comparators that are available for tracing. The permitted values are: 0000 No VMID comparators are available. 0001 The implementation has one VMID comparator." hexmask.long.byte 0x10 24.--27. 1. "NUMCIDC,Indicates the number of Context ID comparators that are available for tracing. The permitted values are: 0000 No Context ID comparators are available. 0001 The implementation has one.." hexmask.long.byte 0x10 20.--23. 1. "NUMSSCC,Indicates the number of single-shot comparator controls that are available for tracing. The permitted values are: 0000 No single-shot comparator controls are available. 0001 The.." newline hexmask.long.byte 0x10 16.--19. 1. "NUMRSPAIR,Indicates the number of resource selection pairs that are available for tracing. The permitted values are: 0000 The implementation has one resource selection pair. 0001 The implementation.." hexmask.long.byte 0x10 12.--15. 1. "NUMPC,Indicates the number of processor comparator inputs that are available for tracing. The permitted values are: 0000 No processor comparator inputs are available. 0001 The implementation has.." bitfld.long 0x10 9.--11. "RES0_TRCIDR4_11_9,Reserved RES0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "SUPPDAC,Indicates if the implementation can support data address comparisons: 0 The implementation does not support data address comparisons. 1 The implementation can support data address comparisons" "0,1" hexmask.long.byte 0x10 4.--7. 1. "NUMDVC,Indicates the number of data value comparators that are available for tracing. The permitted values are: 0000 No data value comparators are available. 0001 The implementation has one data.." hexmask.long.byte 0x10 0.--3. 1. "NUMACPAIRS,Indicates the number of address comparator pairs that are available for tracing. The permitted values are: 0000 No address comparator pairs are available. 0001 The implementation has one.." line.long 0x14 "APBADDR_ETM_CPU1_TRCIDR5,ID Register 5" bitfld.long 0x14 31. "REDFUNCNTR,Indicates if the reduced function counter is implemented: 0 The reduced function counter is not supported. 1 Counter 0 is implemented as a reduced function counter." "0,1" bitfld.long 0x14 28.--30. "NUMCNTR,Indicates the number of counters that are available for tracing. The permitted values are: 000 No counters are available. 001 The implementation has one counter." "0,1,2,3,4,5,6,7" bitfld.long 0x14 25.--27. "NUMSEQSTATE,Indicates the number of sequencer states that are implemented. The permitted values are: 000 No sequencer states are implemented. 100 The implementation has four sequencer states." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 24. "RES0_TRCIDR5_24_24,Reserved RES0." "0,1" bitfld.long 0x14 23. "LPOVERRIDE,Indicates if the implementation can support low-power state override: 0 The implementation does not support low-power state override. 1 The implementation supports low-power state.." "0,1" bitfld.long 0x14 22. "ATBTRIG,Indicates if the implementation can support ATB triggers: 0 The implementation does not support ATB triggers. 1 The implementation supports ATB triggers and the TRCEVENTCTL1R.ATBTRIG field.." "0,1" newline hexmask.long.byte 0x14 16.--21. 1. "TRACEIDSIZE,Indicates the trace ID width. The permitted value is: 111 The implementation supports a 7-bit trace ID. This sets the width of the TRCTRACEIDR.TRACEID field. All other values are reserved.The CoreSight ATB.." hexmask.long.byte 0x14 12.--15. 1. "RES0_TRCIDR5_15_12,Reserved RES0." bitfld.long 0x14 9.--11. "NUMEXTINSEL,Indicates how many external input select resources are implemented. The permitted values are: 000 No external input select resources are available. If NUMEXTINSEL is zero NUMEXTIN must also be zero." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 0.--8. 1. "NUMEXTIN,Indicates how many external inputs are implemented. The permitted values are: 000000000 No external inputs are available. If NUMEXTIN is zero NUMEXTINSEL must also be zero. 000000001 The.." group.long 0x208++0x37 line.long 0x0 "APBADDR_ETM_CPU1_TRCRSCTLR2,Resource Selection Control Registers 2" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCRSCTLR2_31_22,Reserved RES0." bitfld.long 0x0 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x0 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x0 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x4 "APBADDR_ETM_CPU1_TRCRSCTLR3,Resource Selection Control Registers 3" hexmask.long.word 0x4 22.--31. 1. "RES0_TRCRSCTLR3_31_22,Reserved RES0." bitfld.long 0x4 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x4 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x4 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x4 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x8 "APBADDR_ETM_CPU1_TRCRSCTLR4,Resource Selection Control Registers 4" hexmask.long.word 0x8 22.--31. 1. "RES0_TRCRSCTLR4_31_22,Reserved RES0." bitfld.long 0x8 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x8 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x8 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0xC "APBADDR_ETM_CPU1_TRCRSCTLR5,Resource Selection Control Registers 5" hexmask.long.word 0xC 22.--31. 1. "RES0_TRCRSCTLR5_31_22,Reserved RES0." bitfld.long 0xC 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0xC 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0xC 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0xC 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x10 "APBADDR_ETM_CPU1_TRCRSCTLR6,Resource Selection Control Registers 6" hexmask.long.word 0x10 22.--31. 1. "RES0_TRCRSCTLR6_31_22,Reserved RES0." bitfld.long 0x10 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x10 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x10 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x14 "APBADDR_ETM_CPU1_TRCRSCTLR7,Resource Selection Control Registers 7" hexmask.long.word 0x14 22.--31. 1. "RES0_TRCRSCTLR7_31_22,Reserved RES0." bitfld.long 0x14 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x14 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x14 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x14 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x18 "APBADDR_ETM_CPU1_TRCRSCTLR8,Resource Selection Control Registers 8" hexmask.long.word 0x18 22.--31. 1. "RES0_TRCRSCTLR8_31_22,Reserved RES0." bitfld.long 0x18 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x18 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x18 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x18 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x1C "APBADDR_ETM_CPU1_TRCRSCTLR9,Resource Selection Control Registers 9" hexmask.long.word 0x1C 22.--31. 1. "RES0_TRCRSCTLR9_31_22,Reserved RES0." bitfld.long 0x1C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x1C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x1C 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x1C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x20 "APBADDR_ETM_CPU1_TRCRSCTLR10,Resource Selection Control Registers 10" hexmask.long.word 0x20 22.--31. 1. "RES0_TRCRSCTLR10_31_22,Reserved RES0." bitfld.long 0x20 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x20 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x20 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x20 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x24 "APBADDR_ETM_CPU1_TRCRSCTLR11,Resource Selection Control Registers 11" hexmask.long.word 0x24 22.--31. 1. "RES0_TRCRSCTLR11_31_22,Reserved RES0." bitfld.long 0x24 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x24 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x24 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x24 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x28 "APBADDR_ETM_CPU1_TRCRSCTLR12,Resource Selection Control Registers 12" hexmask.long.word 0x28 22.--31. 1. "RES0_TRCRSCTLR12_31_22,Reserved RES0." bitfld.long 0x28 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x28 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x28 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x28 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x2C "APBADDR_ETM_CPU1_TRCRSCTLR13,Resource Selection Control Registers 13" hexmask.long.word 0x2C 22.--31. 1. "RES0_TRCRSCTLR13_31_22,Reserved RES0." bitfld.long 0x2C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x2C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x2C 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x2C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x30 "APBADDR_ETM_CPU1_TRCRSCTLR14,Resource Selection Control Registers 14" hexmask.long.word 0x30 22.--31. 1. "RES0_TRCRSCTLR14_31_22,Reserved RES0." bitfld.long 0x30 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x30 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x30 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x30 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x34 "APBADDR_ETM_CPU1_TRCRSCTLR15,Resource Selection Control Registers 15" hexmask.long.word 0x34 22.--31. 1. "RES0_TRCRSCTLR15_31_22,Reserved RES0." bitfld.long 0x34 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x34 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x34 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x34 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." group.long 0x280++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCSSCCR0,Single-Shot Comparator Control Register 0" hexmask.long.byte 0x0 25.--31. 1. "RES0_TRCSSCCR0_31_25,Reserved RES0." bitfld.long 0x0 24. "RST,Controls whether the single-shot comparator resource is reset when it fires. 0 When the single-shot comparator resource fires it is not reset. 1 When the single-shot comparator resource fires .." "0,1" hexmask.long.byte 0x0 16.--23. 1. "ARC,Selects one or more address range comparators for single-shot control.Each bit represents an address range comparator pair so bit[n-16] controls the selection of address range comparator pair n-16. If bit[n-16] is: 0 The address.." newline hexmask.long.word 0x0 0.--15. 1. "SAC,Selects one or more single address comparators for single-shot control.Each bit represents a single address comparator so bit[n] controls the selection of single address comparator n. If bit[n] is: 0 The single address comparator.." group.long 0x2A0++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCSSCSR0,Single-Shot Comparator Status Register 0" bitfld.long 0x0 31. "STATUS,Single-shot status bit. Indicates if any of the comparators that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects have matched: 0 No match has occurred. 1 One or more matches has occurred. If.." "0,1" hexmask.long 0x0 3.--30. 1. "RES0_TRCSSCSR0_30_3,Reserved RES0." bitfld.long 0x0 2. "DV,Data value comparator support bit. Indicates if the trace unit supports data address with data value comparisons: 0 Single-shot data address with data value comparisons are not supported. 1.." "0,1" newline bitfld.long 0x0 1. "DA,Data address comparator support bit. Indicates if the trace unit supports data address comparisons: 0 Single-shot data address comparisons are not supported. 1 Single-shot data address.." "0,1" bitfld.long 0x0 0. "INST,Instruction address comparator support bit. Indicates if the trace unit supports instruction address comparisons: 0 Single-shot instruction address comparisons are not supported. 1 Single-shot.." "0,1" group.long 0x300++0x7 line.long 0x0 "APBADDR_ETM_CPU1_TRCOSLAR,OS Lock Access Register" hexmask.long 0x0 1.--31. 1. "RES0_TRCOSLAR_31_1,Reserved RES0." bitfld.long 0x0 0. "LOCK,OS Lock control bit: 0 Unlocks the OS Lock. 1 Locks the OS Lock. This setting disables the trace unit." "0,1" line.long 0x4 "APBADDR_ETM_CPU1_TRCOSLSR,OS Lock Status Register" hexmask.long 0x4 4.--31. 1. "RES0_TRCOSLSR_31_4,Reserved RES0." bitfld.long 0x4 3. "PRESENT,Indicates whether the OS Lock is implemented.This bit is RES1 which indicates that the OS Lock is always implemented." "0,1" bitfld.long 0x4 2. "BIT32,This bit is RES0 which indicates that software must perform a 32-bit write to update the TRCOSLAR." "0,1" newline bitfld.long 0x4 1. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked. 1 The OS Lock is locked. When the trace unit core power domain is powered down the value is UNKNOWN. The TRCPDSR indicates if.." "0,1" bitfld.long 0x4 0. "RES0_TRCOSLSR_0_0,Reserved RES0." "0,1" group.long 0x310++0x7 line.long 0x0 "APBADDR_ETM_CPU1_TRCPDCR,Power Down Control Register" hexmask.long 0x0 4.--31. 1. "RES0_TRCPDCR_31_4,Reserved RES0." bitfld.long 0x0 3. "PU,Powerup request bit: 0 The system can remove power from the trace unit. The TRCPDSR indicates if the trace unit is powered down. 1 The system must provide power to the trace unit." "0,1" bitfld.long 0x0 0.--2. "RES0_TRCPDCR_2_0,Reserved RES0." "0,1,2,3,4,5,6,7" line.long 0x4 "APBADDR_ETM_CPU1_TRCPDSR,Power Down Status Register" hexmask.long 0x4 6.--31. 1. "RES0_TRCPDSR_31_6,Reserved RES0." bitfld.long 0x4 5. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked. 1 The OS Lock is locked. The value is UNKNOWN when the trace unit core power domain is powered down that is when POWER==0." "0,1" bitfld.long 0x4 2.--4. "RES0_TRCPDSR_4_2,Reserved RES0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 1. "STICKYPD,Sticky powerdown status bit. Indicates whether the trace register state is valid: 0 If POWER==1 then the state of TRCOSLSR and the trace registers are valid. If POWER==0 then it is UNKNOWN whether the state of TRCOSLSR and the.." "0,1" bitfld.long 0x4 0. "POWER,Power status bit: 0 The trace unit core power domain is not powered. The trace registers are not accessible and they all return an error response. 1 The trace unit core power domain is.." "0,1" group.long 0x400++0x3F line.long 0x0 "APBADDR_ETM_CPU1_TRCACVR0_31_0,Address Comparator Value Registers 0 (low word)" hexmask.long 0x0 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x4 "APBADDR_ETM_CPU1_TRCACVR0_63_32,Address Comparator Value Registers 0 (high word)" hexmask.long 0x4 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x8 "APBADDR_ETM_CPU1_TRCACVR1_31_0,Address Comparator Value Registers 1 (low word)" hexmask.long 0x8 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0xC "APBADDR_ETM_CPU1_TRCACVR1_63_32,Address Comparator Value Registers 1 (high word)" hexmask.long 0xC 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x10 "APBADDR_ETM_CPU1_TRCACVR2_31_0,Address Comparator Value Registers 2 (low word)" hexmask.long 0x10 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x14 "APBADDR_ETM_CPU1_TRCACVR2_63_32,Address Comparator Value Registers 2 (high word)" hexmask.long 0x14 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x18 "APBADDR_ETM_CPU1_TRCACVR3_31_0,Address Comparator Value Registers 3 (low word)" hexmask.long 0x18 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x1C "APBADDR_ETM_CPU1_TRCACVR3_63_32,Address Comparator Value Registers 3 (high word)" hexmask.long 0x1C 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x20 "APBADDR_ETM_CPU1_TRCACVR4_31_0,Address Comparator Value Registers 4 (low word)" hexmask.long 0x20 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x24 "APBADDR_ETM_CPU1_TRCACVR4_63_32,Address Comparator Value Registers 4 (high word)" hexmask.long 0x24 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x28 "APBADDR_ETM_CPU1_TRCACVR5_31_0,Address Comparator Value Registers 5 (low word)" hexmask.long 0x28 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x2C "APBADDR_ETM_CPU1_TRCACVR5_63_32,Address Comparator Value Registers 5 (high word)" hexmask.long 0x2C 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x30 "APBADDR_ETM_CPU1_TRCACVR6_31_0,Address Comparator Value Registers 6 (low word)" hexmask.long 0x30 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x34 "APBADDR_ETM_CPU1_TRCACVR6_63_32,Address Comparator Value Registers 6 (high word)" hexmask.long 0x34 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x38 "APBADDR_ETM_CPU1_TRCACVR7_31_0,Address Comparator Value Registers 7 (low word)" hexmask.long 0x38 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x3C "APBADDR_ETM_CPU1_TRCACVR7_63_32,Address Comparator Value Registers 7 (high word)" hexmask.long 0x3C 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." group.long 0x480++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCACATR0,Address Comparator Access Type Registers 0" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR0_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR0_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x488++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCACATR1,Address Comparator Access Type Registers 1" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR1_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR1_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x490++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCACATR2,Address Comparator Access Type Registers 2" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR2_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR2_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x498++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCACATR3,Address Comparator Access Type Registers 3" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR3_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR3_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4A0++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCACATR4,Address Comparator Access Type Registers 4" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR4_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR4_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4A8++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCACATR5,Address Comparator Access Type Registers 5" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR5_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR5_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4B0++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCACATR6,Address Comparator Access Type Registers 6" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR6_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR6_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4B8++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCACATR7,Address Comparator Access Type Registers 7" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR7_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR7_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x600++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCCIDCVR0,Context ID Comparator Value Register 0" hexmask.long 0x0 0.--31. 1. "VALUE,Context ID value. The implemented width of this field is IMPLEMENTATION DEFINED and is set by TRCIDR2.CIDSIZE. Unimplemented bits are RAZ/WI.After a processor reset the ETM architecture assumes that the Context ID is zero until the processor.." group.long 0x640++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCVMIDCVR0,VMID Comparator Value Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--7. 1. "VALUE,Contains a VMID value." group.long 0x680++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCCIDCCTLR0,Context ID Comparator Control Register 0" hexmask.long 0x0 0.--31. 1. "COMP_N,Controls the mask value that the trace unit applies to TRCCIDCVRn. Each bit in this field corresponds to a byte in TRCCIDCVRn. When a bit is: 0 The trace unit includes the relevant byte in TRCCIDCVRn when it performs the Context.." group.long 0xEE4++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCITATBIDR,Integration ATB Identification Register" hexmask.long 0x0 7.--31. 1. "RES0_TRCITATBIDR_31_7,Reserved RES0" hexmask.long.byte 0x0 0.--6. 1. "ID,Drives the ATIDMn[6:0] output pins" group.long 0xEEC++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCITIDATAR,Integration Instruction ATB Data Register" hexmask.long 0x0 5.--31. 1. "RES0_TRCITIDATAR_31_5,Reserved RES0" bitfld.long 0x0 4. "ATDATAM_31,Drives the ATDATAM[31] output" "0,1" bitfld.long 0x0 3. "ATDATAM_23,Drives the ATDATAM[23] output" "0,1" newline bitfld.long 0x0 2. "ATDATAM_15,Drives the ATDATAM[15] output" "0,1" bitfld.long 0x0 1. "ATDATAM_7,Drives the ATDATAM[7] output" "0,1" bitfld.long 0x0 0. "ATDATAM_0,Drives the ATDATAM[0] output" "0,1" group.long 0xEF4++0x3 line.long 0x0 "APBADDR_ETM_CPU1_TRCITIATBINR,Integration Instruction ATB In Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved. Read undefined." bitfld.long 0x0 1. "AFVALIDM,Returns the value of the AFVALIDMn input pin" "0,1" bitfld.long 0x0 0. "ATREADYM,Returns the value of the ATREADYMn input pin" "0,1" group.long 0xEFC++0x7 line.long 0x0 "APBADDR_ETM_CPU1_TRCITIATBOUTR,Integration Instruction ATB Out Register" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved. Read undefined." bitfld.long 0x0 8.--9. "BYTES,Drives the ATBYTESMn[1:0] output pins" "0,1,2,3" hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved. Read undefined." newline bitfld.long 0x0 1. "AFREADY,Drives the AFREADYMn output pin" "0,1" bitfld.long 0x0 0. "ATVALID,Drives the ATVALIDMn output pin" "0,1" line.long 0x4 "APBADDR_ETM_CPU1_TRCITCTRL,Integration Mode Control Register" hexmask.long 0x4 1.--31. 1. "RES0_TRCITCTRL_31_1,Reserved RES0." bitfld.long 0x4 0. "ITEN,Integration mode enable bit: 0 The trace unit is not in integration mode. 1 The trace unit is in integration mode. This mode enables a debug agent to perform topology detection and.." "0,1" group.long 0xFA0++0x1F line.long 0x0 "APBADDR_ETM_CPU1_TRCCLAIMSET,Claim Tag Set Register" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--3. 1. "SET,Sets bits in the claim tag and determines the number of claim tag bits implemented." line.long 0x4 "APBADDR_ETM_CPU1_TRCCLAIMCLR,Claim Tag Clear Register" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "CLR,Clears bits in the claim tag and determines the current value of the claim tag." line.long 0x8 "APBADDR_ETM_CPU1_TRCDEVAFF0,Device Affinity Register 0" hexmask.long 0x8 0.--31. 1. "MPIDR_EL1_31_0,Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0xC "APBADDR_ETM_CPU1_TRCDEVAFF1,Device Affinity Register 1" hexmask.long 0xC 0.--31. 1. "MPIDR_EL1_63_32,Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x10 "APBADDR_ETM_CPU1_TRCLAR,Software Lock Access Register" hexmask.long 0x10 0.--31. 1. "KEY,Writing the key value 0xC5ACCE55 to this field clears the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register sets the lock disabling write accesses to this.." line.long 0x14 "APBADDR_ETM_CPU1_TRCLSR,Software Lock Status Register" hexmask.long 0x14 3.--31. 1. "RES0_TRCLSR_31_3,Reserved RES0." bitfld.long 0x14 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" bitfld.long 0x14 1. "SLK,Software lock status for this component. Possible values of this field are: 0 Lock clear. Writes are permitted to this component's registers. 1 Lock set. Writes to this component's registers.." "0,1" newline bitfld.long 0x14 0. "SLI,Software lock implemented. RAO." "0,1" line.long 0x18 "APBADDR_ETM_CPU1_TRCAUTHSTATUS,Authentication Status Register" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCAUTHSTATUS_31_8,Reserved RES0." bitfld.long 0x18 6.--7. "SNID,Indicates whether the system enables the trace unit to support Secure non-invasive debug: 00 The trace unit does not implement support for Secure non-invasive debug. 01 Reserved." "0,1,2,3" bitfld.long 0x18 4.--5. "SID,Indicates whether the trace unit supports Secure invasive debug: 00 The trace unit does not support Secure invasive debug. All other values are reserved." "0,1,2,3" newline bitfld.long 0x18 2.--3. "NSNID,Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: 00 The trace unit does not implement support for Non-secure non-invasive debug. 01 Reserved." "0,1,2,3" bitfld.long 0x18 0.--1. "NSID,Indicates whether the trace unit supports Non-secure invasive debug: 00 The trace unit does not support Non-secure invasive debug. All other values are reserved." "0,1,2,3" line.long 0x1C "APBADDR_ETM_CPU1_TRCDEVARCH,Device Architecture Register" hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For trace this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is RAO." "0,1" hexmask.long.byte 0x1C 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For trace the revision defined by ETMv4 is 0x0.All other values are reserved." newline hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For trace bits [15:12] are the architecture version 0x4; bits [11:0] are the architecture part number 0xA13.This corresponds to trace.." group.long 0xFC8++0x37 line.long 0x0 "APBADDR_ETM_CPU1_TRCDEVID,Device ID Register" hexmask.long 0x0 0.--31. 1. "DEVID,Indicates the capabilities of the trace unit. The implemented width of this field and its bit assignments are IMPLEMENTATION DEFINED. Unimplemented bits are RAZ/WI.If a component is configurable then ARM recommends that this field can also indicate.." line.long 0x4 "APBADDR_ETM_CPU1_TRCDEVTYPE,Device Type Register" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_TRCDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x4 4.--7. 1. "SUB,Returns 0x1 to indicate that the ETM generates processor trace.All other values are reserved." hexmask.long.byte 0x4 0.--3. 1. "MAIN,Returns 0x3 to indicate that the ETM is a trace source.All other values are reserved." line.long 0x8 "APBADDR_ETM_CPU1_TRCPIDR4,Peripheral Identification Register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RES0_TRCPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x8 4.--7. 1. "SIZE,Size of the component. RES0. This indicates that the ETM memory map occupies 4KB." hexmask.long.byte 0x8 0.--3. 1. "DES_2,Designer JEP106 continuation code. For ARM Limited this field is 0b0100." line.long 0xC "APBADDR_ETM_CPU1_TRCPIDR5,Peripheral Identification Register 5" hexmask.long.tbyte 0xC 8.--31. 1. "RES0_TRCPIDR5_31_8,Reserved RES0." hexmask.long.byte 0xC 0.--7. 1. "RESERVED,RES0 reserved for future use." line.long 0x10 "APBADDR_ETM_CPU1_TRCPIDR6,Peripheral Identification Register 6" hexmask.long.tbyte 0x10 8.--31. 1. "RES0_TRCPIDR6_31_8,Reserved RES0." hexmask.long.byte 0x10 0.--7. 1. "RESERVED,RES0 reserved for future use." line.long 0x14 "APBADDR_ETM_CPU1_TRCPIDR7,Peripheral Identification Register 7" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_TRCPIDR7_31_8,Reserved RES0." hexmask.long.byte 0x14 0.--7. 1. "RESERVED,RES0 reserved for future use." line.long 0x18 "APBADDR_ETM_CPU1_TRCPIDR0,Peripheral Identification Register 0" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x18 0.--7. 1. "PART_0,Part number bits[7:0]." line.long 0x1C "APBADDR_ETM_CPU1_TRCPIDR1,Peripheral Identification Register 1" hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_TRCPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x1C 4.--7. 1. "DES_0,Designer bits[3:0] of JEP106 ID code. For ARM Limited this field is 0b1011." hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part number bits[11:8]." line.long 0x20 "APBADDR_ETM_CPU1_TRCPIDR2,Peripheral Identification Register 2" hexmask.long.tbyte 0x20 8.--31. 1. "RES0_TRCPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x20 4.--7. 1. "REVISION,The IMPLEMENTATION DEFINED revision number for the ETM implementation. See also TRCIDR1.REVISION." bitfld.long 0x20 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" newline bitfld.long 0x20 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0x24 "APBADDR_ETM_CPU1_TRCPIDR3,Peripheral Identification Register 3" hexmask.long.tbyte 0x24 8.--31. 1. "RES0_TRCPIDR3_31_8,Reserved RES0." hexmask.long.byte 0x24 4.--7. 1. "REVAND,The IMPLEMENTATION DEFINED manufacturing revision number for the implementation. After silicon is available if metal fixes are necessary the manufacturer can alter the top metal layer so that this field can indicate any post-fab silicon changes." hexmask.long.byte 0x24 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x28 "APBADDR_ETM_CPU1_TRCCIDR0,Component Identification Register 0" hexmask.long.tbyte 0x28 8.--31. 1. "RES0_TRCCIDR0_31_8,Reserved RES0." hexmask.long.byte 0x28 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x2C "APBADDR_ETM_CPU1_TRCCIDR1,Component Identification Register 1" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_TRCCIDR1_31_8,Reserved RES0." hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Component class. Reads as 0x9 to indicate that the ETM is a debug component with CoreSight architecture compliant management registers." hexmask.long.byte 0x2C 0.--3. 1. "PRMBL_1,Preamble. Must read as 0x0." line.long 0x30 "APBADDR_ETM_CPU1_TRCCIDR2,Component Identification Register 2" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_TRCCIDR2_31_8,Reserved RES0." hexmask.long.byte 0x30 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x34 "APBADDR_ETM_CPU1_TRCCIDR3,Component Identification Register 3" hexmask.long.tbyte 0x34 8.--31. 1. "RES0_TRCCIDR3_31_8,Reserved RES0." hexmask.long.byte 0x34 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree "A53SS0_CORE1_PMU" base ad:0x730120000 group.long 0x0++0x3 line.long 0x0 "APBADDR_PMU_CPU1_PMEVCNTR0_EL0,Performance Monitors Event Count Register 0" hexmask.long 0x0 0.--31. 1. "PMEVCNTR0_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x8++0x3 line.long 0x0 "APBADDR_PMU_CPU1_PMEVCNTR1_EL0,Performance Monitors Event Count Register 1" hexmask.long 0x0 0.--31. 1. "PMEVCNTR1_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x10++0x3 line.long 0x0 "APBADDR_PMU_CPU1_PMEVCNTR2_EL0,Performance Monitors Event Count Register 2" hexmask.long 0x0 0.--31. 1. "PMEVCNTR2_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x18++0x3 line.long 0x0 "APBADDR_PMU_CPU1_PMEVCNTR3_EL0,Performance Monitors Event Count Register 3" hexmask.long 0x0 0.--31. 1. "PMEVCNTR3_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x20++0x3 line.long 0x0 "APBADDR_PMU_CPU1_PMEVCNTR4_EL0,Performance Monitors Event Count Register 4" hexmask.long 0x0 0.--31. 1. "PMEVCNTR4_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x28++0x3 line.long 0x0 "APBADDR_PMU_CPU1_PMEVCNTR5_EL0,Performance Monitors Event Count Register 5" hexmask.long 0x0 0.--31. 1. "PMEVCNTR5_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0xF8++0x7 line.long 0x0 "APBADDR_PMU_CPU1_PMCCNTR_EL0_31_0,Performance Monitors Cycle Counter (low word)" hexmask.long 0x0 0.--31. 1. "CCNT,Cycle count. Depending on the values of PMCR_EL0.{LC D} the cycle count increments in one of the following ways:Every processor clock cycle.Every 64th processor clock cycle.The cycle count can be reset to zero by writing 1 to PMCR_EL0.C." line.long 0x4 "APBADDR_PMU_CPU1_PMCCNTR_EL0_63_32,Performance Monitors Cycle Counter (high word)" hexmask.long 0x4 0.--31. 1. "CCNT,Cycle count. Depending on the values of PMCR_EL0.{LC D} the cycle count increments in one of the following ways:Every processor clock cycle.Every 64th processor clock cycle.The cycle count can be reset to zero by writing 1 to PMCR_EL0.C." group.long 0x400++0x17 line.long 0x0 "APBADDR_PMU_CPU1_PMEVTYPER0_EL0,Performance Monitors Event Type Register 0" bitfld.long 0x0 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x0 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x0 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x0 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x0 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x0 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x0 10.--25. 1. "RES0_PMEVTYPER0_EL0_25_10,Reserved RES0." hexmask.long.word 0x0 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x4 "APBADDR_PMU_CPU1_PMEVTYPER1_EL0,Performance Monitors Event Type Register 1" bitfld.long 0x4 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x4 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x4 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x4 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x4 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x4 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x4 10.--25. 1. "RES0_PMEVTYPER1_EL0_25_10,Reserved RES0." hexmask.long.word 0x4 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x8 "APBADDR_PMU_CPU1_PMEVTYPER2_EL0,Performance Monitors Event Type Register 2" bitfld.long 0x8 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x8 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x8 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x8 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x8 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x8 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x8 10.--25. 1. "RES0_PMEVTYPER2_EL0_25_10,Reserved RES0." hexmask.long.word 0x8 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0xC "APBADDR_PMU_CPU1_PMEVTYPER3_EL0,Performance Monitors Event Type Register 3" bitfld.long 0xC 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0xC 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0xC 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0xC 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0xC 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0xC 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0xC 10.--25. 1. "RES0_PMEVTYPER3_EL0_25_10,Reserved RES0." hexmask.long.word 0xC 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x10 "APBADDR_PMU_CPU1_PMEVTYPER4_EL0,Performance Monitors Event Type Register 4" bitfld.long 0x10 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x10 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x10 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x10 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x10 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x10 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x10 10.--25. 1. "RES0_PMEVTYPER4_EL0_25_10,Reserved RES0." hexmask.long.word 0x10 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x14 "APBADDR_PMU_CPU1_PMEVTYPER5_EL0,Performance Monitors Event Type Register 5" bitfld.long 0x14 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x14 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x14 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x14 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x14 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x14 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x14 10.--25. 1. "RES0_PMEVTYPER5_EL0_25_10,Reserved RES0." hexmask.long.word 0x14 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." group.long 0x47C++0x3 line.long 0x0 "APBADDR_PMU_CPU1_PMCCFILTR_EL0,Performance Monitors Cycle Counter Filter Register" bitfld.long 0x0 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count cycles in EL1. 1.." "0,1" bitfld.long 0x0 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count cycles in EL0. 1.." "0,1" newline bitfld.long 0x0 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P cycles in Non-secure EL1 are counted.Otherwise cycles in Non-secure EL1 are.." "0,1" bitfld.long 0x0 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U cycles in Non-secure EL0 are counted.Otherwise cycles in Non-secure EL0 are.." "0,1" newline bitfld.long 0x0 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count cycles in EL2. 1 Count cycles in EL2." "0,1" bitfld.long 0x0 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P cycles in Secure EL3 are counted.Otherwise cycles in Secure EL3.." "0,1" newline hexmask.long 0x0 0.--25. 1. "RES0_PMCCFILTR_EL0_25_0,Reserved RES0." group.long 0xC00++0x3 line.long 0x0 "APBADDR_PMU_CPU1_PMCNTENSET_EL0,Performance Monitors Count Enable Set Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 enable bit. Enables the cycle counter register. Possible values are: 0 When read means the cycle counter is disabled. When written has no effect. 1 When read means the cycle.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter enable bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: 0 When read means that PMEVCNTR is disabled. When written has no effect. 1.." group.long 0xC20++0x3 line.long 0x0 "APBADDR_PMU_CPU1_PMCNTENCLR_EL0,Performance Monitors Count Enable Clear Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 disable bit. Disables the cycle counter register. Possible values are: 0 When read means the cycle counter is disabled. When written has no effect. 1 When read means the cycle.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter disable bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: 0 When read means that PMEVCNTR is disabled. When written has no effect." group.long 0xC40++0x3 line.long 0x0 "APBADDR_PMU_CPU1_PMINTENSET_EL1,Performance Monitors Interrupt Enable Set Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow interrupt request enable bit. Possible values are: 0 When read means the cycle counter overflow interrupt request is disabled. When written has no effect. 1 When read .." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow interrupt request enable bit for PMEVCNTR_EL0.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: 0 When read means that the PMEVCNTR_EL0 event counter interrupt request is.." group.long 0xC60++0x3 line.long 0x0 "APBADDR_PMU_CPU1_PMINTENCLR_EL1,Performance Monitors Interrupt Enable Clear Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow interrupt request disable bit. Possible values are: 0 When read means the cycle counter overflow interrupt request is disabled. When written has no effect. 1 When read .." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow interrupt request disable bit for PMEVCNTR_EL0.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: 0 When read means that the PMEVCNTR_EL0 event counter interrupt request is.." group.long 0xC80++0x3 line.long 0x0 "APBADDR_PMU_CPU1_PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow bit. Possible values are: 0 When read means the cycle counter has not overflowed. When written has no effect. 1 When read means the cycle counter has overflowed. When.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow clear bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: 0 When read means that PMEVCNTR has not overflowed. When written has no effect." group.long 0xCA0++0x3 line.long 0x0 "APBADDR_PMU_CPU1_PMSWINC_EL0,Performance Monitors Software Increment Register" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--5. 1. "P_X,Event counter software increment bit for PMEVCNTR" group.long 0xCC0++0x3 line.long 0x0 "APBADDR_PMU_CPU1_PMOVSSET_EL0,Performance Monitors Overflow Flag Status Set Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow bit. Possible values are: 0 When read means the cycle counter has not overflowed. When written has no effect. 1 When read means the cycle counter has overflowed. When.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow set bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: 0 When read means that PMEVCNTR has not overflowed. When written has no effect." group.long 0xE00++0x7 line.long 0x0 "APBADDR_PMU_CPU1_PMCFGR,Performance Monitors Configuration Register" hexmask.long.word 0x0 20.--31. 1. "RES0_PMCFGR_31_20,Reserved RES0." bitfld.long 0x0 19. "UEN,User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface so this bit is RES0." "0,1" newline bitfld.long 0x0 18. "WT,This feature is not supported so this bit is RES0." "0,1" bitfld.long 0x0 17. "NA,This feature is not supported so this bit is RES0." "0,1" newline bitfld.long 0x0 16. "EX,Export supported. Value is IMPLEMENTATION DEFINED. 0 PMCR_EL0.X is RES0. 1 PMCR_EL0.X is read/write." "0,1" bitfld.long 0x0 15. "CCD,Cycle counter has prescale. This is RES1 if AArch32 is supported at any EL and RES0 otherwise. 0 PMCR_EL0.D is RES0. 1 PMCR_EL0.D is read/write." "0,1" newline bitfld.long 0x0 14. "CC,Dedicated cycle counter [counter 31] supported. This bit is RES1." "0,1" hexmask.long.byte 0x0 8.--13. 1. "SIZE,Size of counters. This field determines the spacing of counters in the memory-map.In v8-A the counters are at doubleword-aligned addresses and the largest counter is 64-bits so this field is 0b111111." newline hexmask.long.byte 0x0 0.--7. 1. "N,Number of counters implemented in addition to the cycle counter PMCCNTR_EL0. The maximum number of event counters is 31 so bits[7:5] are always RES0. 00000000 Only PMCCNTR_EL0 implemented. 00000001.." line.long 0x4 "APBADDR_PMU_CPU1_PMCR_EL0,Performance Monitors Control Register" hexmask.long.tbyte 0x4 11.--31. 1. "RES0_PMCR_EL0_31_11,Reserved RAZ/WI." hexmask.long.byte 0x4 7.--10. 1. "RES0_PMCR_EL0_10_7,Reserved RES0." newline bitfld.long 0x4 6. "LC,Long cycle counter enable. Determines which PMCCNTR_EL0 bit generates an overflow recorded by PMOVSR[31]. 0 Cycle counter overflow on increment that changes PMCCNTR_EL0[31] from 1 to 0. 1 Cycle.." "0,1" bitfld.long 0x4 5. "DP,Disable cycle counter when event counting is prohibited. The possible values of this bit are: 0 PMCCNTR_EL0 if enabled counts when event counting is prohibited. 1 PMCCNTR_EL0 does not count.." "0,1" newline bitfld.long 0x4 4. "X,Enable export of events in an IMPLEMENTATION DEFINED event stream. The possible values of this bit are: 0 Do not export events. 1 Export events where not prohibited. This bit is.." "0,1" bitfld.long 0x4 3. "D,Clock divider. The possible values of this bit are: 0 When enabled PMCCNTR_EL0 counts every clock cycle. 1 When enabled PMCCNTR_EL0 counts once every 64 clock cycles. This bit.." "0,1" newline bitfld.long 0x4 2. "C,Cycle counter reset. This bit is WO. The effects of writing to this bit are: 0 No action. 1 Reset PMCCNTR_EL0 to zero. This bit is always RAZ.Resetting PMCCNTR_EL0 does not.." "0,1" bitfld.long 0x4 1. "P,Event counter reset. This bit is WO. The effects of writing to this bit are: 0 No action. 1 Reset all event counters not including PMCCNTR_EL0 to zero. This bit is always.." "0,1" newline bitfld.long 0x4 0. "E,Enable. The possible values of this bit are: 0 All counters including PMCCNTR_EL0 are disabled. 1 All counters are enabled by PMCNTENSET_EL0. This bit is RW." "0,1" group.long 0xE20++0x7 line.long 0x0 "APBADDR_PMU_CPU1_PMCEID0_EL0,Performance Monitors Common Event Identification Register 0" hexmask.long 0x0 0.--31. 1. "CE_31_0,Common architectural and microarchitectural feature events that can be counted by the PMU event counters.For each bit described in the following table the event is implemented if the bit is set to 1 or not implemented if the bit is set to.." line.long 0x4 "APBADDR_PMU_CPU1_PMCEID1_EL0,Performance Monitors Common Event Identification Register 1" hexmask.long 0x4 1.--31. 1. "RES0_PMCEID1_EL0_31_1,Reserved RES0." bitfld.long 0x4 0. "CE_32,Common architectural and microarchitectural feature events that can be counted by the PMU event counters.For the bit described in the following table the event is implemented if the bit is set to 1 or not implemented if the bit is set to.." "0,1" group.long 0xF00++0x3 line.long 0x0 "APBADDR_PMU_CPU1_PMITCTRL,Performance Monitors Integration mode Control Register" hexmask.long 0x0 1.--31. 1. "RES0_PMITCTRL_31_1,Reserved RES0." bitfld.long 0x0 0. "IME,Integration mode enable. When IME == 1 the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED. 0 Normal operation." "0,1" group.long 0xFA8++0x17 line.long 0x0 "APBADDR_PMU_CPU1_PMDEVAFF0,Performance Monitors Device Affinity Register 0" hexmask.long 0x0 0.--31. 1. "PMDEVAFF0,MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x4 "APBADDR_PMU_CPU1_PMDEVAFF1,Performance Monitors Device Affinity Register 1" hexmask.long 0x4 0.--31. 1. "PMDEVAFF1,MPIDR_EL1 high half. Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x8 "APBADDR_PMU_CPU1_PMLAR,Performance Monitors Lock Access Register" hexmask.long 0x8 0.--31. 1. "KEY,Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register locks the lock disabling write.." line.long 0xC "APBADDR_PMU_CPU1_PMLSR,Performance Monitors Lock Status Register" hexmask.long 0xC 3.--31. 1. "RES0_PMLSR_31_3,Reserved RES0." bitfld.long 0xC 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" newline bitfld.long 0xC 1. "SLK,Software lock status for this component. For an access to LSR that is not a memory-mapped access or when the software lock is not implemented this field is RES0.For memory-mapped accesses when the software lock is implemented possible values of.." "0,1" bitfld.long 0xC 0. "SLI,Software lock implemented. For an access to LSR that is not a memory-mapped access this field is RAZ. For memory-mapped accesses the value of this field is IMPLEMENTATION DEFINED. Permitted values are: 0 Software lock not.." "0,1" line.long 0x10 "APBADDR_PMU_CPU1_PMAUTHSTATUS,Performance Monitors Authentication Status Register" hexmask.long.tbyte 0x10 8.--31. 1. "RES0_PMAUTHSTATUS_31_8,Reserved RES0." bitfld.long 0x10 6.--7. "SNID,Holds the same value as DBGAUTHSTATUS_EL1.SNID." "0,1,2,3" newline bitfld.long 0x10 4.--5. "RES0_PMAUTHSTATUS_5_4,Reserved RES0." "0,1,2,3" bitfld.long 0x10 2.--3. "NSNID,Holds the same value as DBGAUTHSTATUS_EL1.NSNID." "0,1,2,3" newline bitfld.long 0x10 0.--1. "RES0_PMAUTHSTATUS_1_0,Reserved RES0." "0,1,2,3" line.long 0x14 "APBADDR_PMU_CPU1_PMDEVARCH,Performance Monitors Device Architecture Register" hexmask.long.word 0x14 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For Performance Monitors this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x14 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A." "0,1" newline hexmask.long.byte 0x14 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For Performance Monitors the revision defined by v8-A is 0x0.All other values are reserved." hexmask.long.word 0x14 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For Performance Monitors:Bits [15:12] are the architecture version 0x2.Bits [11:0] are the architecture part number 0xA16.This.." group.long 0xFCC++0x33 line.long 0x0 "APBADDR_PMU_CPU1_PMDEVTYPE,Performance Monitors Device Type Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_PMDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x0 4.--7. 1. "SUB,Subtype. Must read as 0x1 to indicate this is a processor component." newline hexmask.long.byte 0x0 0.--3. 1. "MAJOR,Major type. Must read as 0x6 to indicate this is a performance monitor component." line.long 0x4 "APBADDR_PMU_CPU1_PMPIDR4,Performance Monitors Peripheral Identification Register 4" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_PMPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x4 4.--7. 1. "SIZE,Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers." newline hexmask.long.byte 0x4 0.--3. 1. "DES_2,Designer JEP106 continuation code least significant nibble. For ARM Limited this field is 0b0100." line.long 0x8 "APBADDR_PMU_CPU1_PMPIDR5,Performance Monitors Peripheral Identification Register 5" hexmask.long 0x8 0.--31. 1. "RESERVED,Reserved RES0" line.long 0xC "APBADDR_PMU_CPU1_PMPIDR6,Performance Monitors Peripheral Identification Register 6" hexmask.long 0xC 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x10 "APBADDR_PMU_CPU1_PMPIDR7,Performance Monitors Peripheral Identification Register 7" hexmask.long 0x10 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x14 "APBADDR_PMU_CPU1_PMPIDR0,Performance Monitors Peripheral Identification Register 0" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_PMPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x14 0.--7. 1. "PART_0,Part number least significant byte." line.long 0x18 "APBADDR_PMU_CPU1_PMPIDR1,Performance Monitors Peripheral Identification Register 1" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_PMPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x18 4.--7. 1. "DES_0,Designer least significant nibble of JEP106 ID code. For ARM Limited this field is 0b1011." newline hexmask.long.byte 0x18 0.--3. 1. "PART_1,Part number most significant nibble." line.long 0x1C "APBADDR_PMU_CPU1_PMPIDR2,Performance Monitors Peripheral Identification Register 2" hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_PMPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x1C 4.--7. 1. "REVISION,Part major revision. Parts can also use this field to extend Part number to 16-bits." newline bitfld.long 0x1C 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" bitfld.long 0x1C 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0x20 "APBADDR_PMU_CPU1_PMPIDR3,Performance Monitors Peripheral Identification Register 3" hexmask.long.tbyte 0x20 8.--31. 1. "RES0_PMPIDR3_31_8,Reserved RES0." hexmask.long.byte 0x20 4.--7. 1. "REVAND,Part minor revision. Parts using PMPIDR2.REVISION as an extension to the Part number must use this field as a major revision number." newline hexmask.long.byte 0x20 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x24 "APBADDR_PMU_CPU1_PMCIDR0,Performance Monitors Component Identification Register 0" hexmask.long.tbyte 0x24 8.--31. 1. "RES0_PMCIDR0_31_8,Reserved RES0." hexmask.long.byte 0x24 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x28 "APBADDR_PMU_CPU1_PMCIDR1,Performance Monitors Component Identification Register 1" hexmask.long.tbyte 0x28 8.--31. 1. "RES0_PMCIDR1_31_8,Reserved RES0." hexmask.long.byte 0x28 4.--7. 1. "CLASS,Component class. Reads as 0x9 debug component." newline hexmask.long.byte 0x28 0.--3. 1. "PRMBL_1,Preamble. RAZ." line.long 0x2C "APBADDR_PMU_CPU1_PMCIDR2,Performance Monitors Component Identification Register 2" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_PMCIDR2_31_8,Reserved RES0." hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x30 "APBADDR_PMU_CPU1_PMCIDR3,Performance Monitors Component Identification Register 3" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_PMCIDR3_31_8,Reserved RES0." hexmask.long.byte 0x30 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree.end tree "A53SS0_CORE2" tree "A53SS0_CORE2_CTI" base ad:0x730240000 group.long 0x0++0x3 line.long 0x0 "APBADDR_CTI_CPU2_CTICONTROL,CTI Control Register" hexmask.long 0x0 1.--31. 1. "RES0_CTICONTROL_31_1,Reserved RES0." bitfld.long 0x0 0. "GLBEN,Enables or disables the CTI mapping functions. Possible values of this field are: 0 CTI mapping functions disabled. 1 CTI mapping functions enabled. When the mapping.." "0,1" group.long 0x10++0x2F line.long 0x0 "APBADDR_CTI_CPU2_CTIINTACK,CTI Output Trigger Acknowledge Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--7. 1. "ACK_N,Can be used to create soft acknowledges for output triggers" line.long 0x4 "APBADDR_CTI_CPU2_CTIAPPSET,CTI Application Trigger Set Register" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "CTIAPPSETX,Application trigger enable" line.long 0x8 "APBADDR_CTI_CPU2_CTIAPPCLEAR,CTI Application Trigger Clear Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x8 0.--3. 1. "CTIAPPCLEARX,Application trigger disable" line.long 0xC "APBADDR_CTI_CPU2_CTIAPPPULSE,CTI Application Pulse Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0xC 0.--3. 1. "CTIAPPPULSEX,Generate event pulse on ECT channel ." line.long 0x10 "APBADDR_CTI_CPU2_CTIINEN0,CTI Input Trigger to Output Channel Enable Register 0" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x10 0.--3. 1. "INENX,Input trigger 0 to output channel enable" line.long 0x14 "APBADDR_CTI_CPU2_CTIINEN1,CTI Input Trigger to Output Channel Enable Register 1" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x14 0.--3. 1. "INENX,Input trigger 1 to output channel enable" line.long 0x18 "APBADDR_CTI_CPU2_CTIINEN2,CTI Input Trigger to Output Channel Enable Register 2" hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x18 0.--3. 1. "INENX,Input trigger 2 to output channel enable" line.long 0x1C "APBADDR_CTI_CPU2_CTIINEN3,CTI Input Trigger to Output Channel Enable Register 3" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x1C 0.--3. 1. "INENX,Input trigger 3 to output channel enable" line.long 0x20 "APBADDR_CTI_CPU2_CTIINEN4,CTI Input Trigger to Output Channel Enable Register 4" hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x20 0.--3. 1. "INENX,Input trigger 4 to output channel enable" line.long 0x24 "APBADDR_CTI_CPU2_CTIINEN5,CTI Input Trigger to Output Channel Enable Register 5" hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x24 0.--3. 1. "INENX,Input trigger 5 to output channel enable" line.long 0x28 "APBADDR_CTI_CPU2_CTIINEN6,CTI Input Trigger to Output Channel Enable Register 6" hexmask.long 0x28 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x28 0.--3. 1. "INENX,Input trigger 6 to output channel enable" line.long 0x2C "APBADDR_CTI_CPU2_CTIINEN7,CTI Input Trigger to Output Channel Enable Register 7" hexmask.long 0x2C 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x2C 0.--3. 1. "INENX,Input trigger 7 to output channel enable" group.long 0xA0++0x1F line.long 0x0 "APBADDR_CTI_CPU2_CTIOUTEN0,CTI Input Channel to Output Trigger Enable Register 0" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--3. 1. "OUTENX,Input channel to output trigger 0 enable" line.long 0x4 "APBADDR_CTI_CPU2_CTIOUTEN1,CTI Input Channel to Output Trigger Enable Register 1" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "OUTENX,Input channel to output trigger 1 enable" line.long 0x8 "APBADDR_CTI_CPU2_CTIOUTEN2,CTI Input Channel to Output Trigger Enable Register 2" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x8 0.--3. 1. "OUTENX,Input channel to output trigger 2 enable" line.long 0xC "APBADDR_CTI_CPU2_CTIOUTEN3,CTI Input Channel to Output Trigger Enable Register 3" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0xC 0.--3. 1. "OUTENX,Input channel to output trigger 3 enable" line.long 0x10 "APBADDR_CTI_CPU2_CTIOUTEN4,CTI Input Channel to Output Trigger Enable Register 4" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x10 0.--3. 1. "OUTENX,Input channel to output trigger 4 enable" line.long 0x14 "APBADDR_CTI_CPU2_CTIOUTEN5,CTI Input Channel to Output Trigger Enable Register 5" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x14 0.--3. 1. "OUTENX,Input channel to output trigger 5 enable" line.long 0x18 "APBADDR_CTI_CPU2_CTIOUTEN6,CTI Input Channel to Output Trigger Enable Register 6" hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x18 0.--3. 1. "OUTENX,Input channel to output trigger 6 enable" line.long 0x1C "APBADDR_CTI_CPU2_CTIOUTEN7,CTI Input Channel to Output Trigger Enable Register 7" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x1C 0.--3. 1. "OUTENX,Input channel to output trigger 7 enable" group.long 0x130++0x17 line.long 0x0 "APBADDR_CTI_CPU2_CTITRIGINSTATUS,CTI Trigger In Status Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--7. 1. "TRINN,Provides the status of the trigger inputs" line.long 0x4 "APBADDR_CTI_CPU2_CTITRIGOUTSTATUS,CTI Trigger Out Status Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--7. 1. "TROUTN,Provides the status of the trigger outputs" line.long 0x8 "APBADDR_CTI_CPU2_CTICHINSTATUS,CTI Channel In Status Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x8 0.--3. 1. "CHINN,Provides the raw status of the ECT channel inputs to the CTI" line.long 0xC "APBADDR_CTI_CPU2_CTICHOUTSTATUS,CTI Channel Out Status Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0xC 0.--3. 1. "CHOUTN,Provides the status of the ECT channel outputs from the CTI" line.long 0x10 "APBADDR_CTI_CPU2_CTIGATE,CTI Channel Gate Enable Register" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x10 0.--3. 1. "GATEX,Determines whether events on channels propagate through the CTM to other ECT components or from the CTM into the CTI" line.long 0x14 "APBADDR_CTI_CPU2_ASICCTL,CTI External Multiplexor Control register" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_ASICCTL_31_8,Reserved RES0." hexmask.long.byte 0x14 0.--7. 1. "ASICCTL,IMPLEMENTATION DEFINED ASIC control. Provides a control for external multiplexing of additional triggers into the CTI.If external multiplexing of trigger signals is implemented then the number of multiplexed signals on each trigger must be.." group.long 0xF00++0x3 line.long 0x0 "APBADDR_CTI_CPU2_CTIITCTRL,CTI Integration mode Control Register" hexmask.long 0x0 1.--31. 1. "RES0_CTIITCTRL_31_1,Reserved RES0." bitfld.long 0x0 0. "IME,Integration mode enable. When IME == 1 the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED. 0 Normal operation." "0,1" group.long 0xFA0++0x5F line.long 0x0 "APBADDR_CTI_CPU2_CTICLAIMSET,CTI Claim Set" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--3. 1. "CLAIMX,CLAIM tag set bit" line.long 0x4 "APBADDR_CTI_CPU2_CTICLAIMCLR,CTI Claim Clear" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "CLAIMX,Clear CLAIM tag" line.long 0x8 "APBADDR_CTI_CPU2_CTIDEVAFF0,CTI Device Affinity Register 0" hexmask.long 0x8 0.--31. 1. "CTIDEVAFF0,MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0xC "APBADDR_CTI_CPU2_CTIDEVAFF1,CTI Device Affinity Register 1" hexmask.long 0xC 0.--31. 1. "CTIDEVAFF1,MPIDR_EL1 high half. Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x10 "APBADDR_CTI_CPU2_CTILAR,CTI Lock Access Register" hexmask.long 0x10 0.--31. 1. "KEY,Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register locks the lock disabling write.." line.long 0x14 "APBADDR_CTI_CPU2_CTILSR,CTI Lock Status Register" hexmask.long 0x14 3.--31. 1. "RES0_CTILSR_31_3,Reserved RES0." bitfld.long 0x14 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" bitfld.long 0x14 1. "SLK,Software lock status for this component. For an access to LSR that is not a memory-mapped access or when the software lock is not implemented this field is RES0.For memory-mapped accesses when the software lock is implemented possible values of.." "0,1" newline bitfld.long 0x14 0. "SLI,Software lock implemented. For an access to LSR that is not a memory-mapped access this field is RAZ. For memory-mapped accesses the value of this field is IMPLEMENTATION DEFINED. Permitted values are: 0 Software lock not.." "0,1" line.long 0x18 "APBADDR_CTI_CPU2_CTIAUTHSTATUS,CTI Authentication Status Register" hexmask.long 0x18 4.--31. 1. "RES0_CTIAUTHSTATUS_31_4,Reserved RES0." bitfld.long 0x18 2.--3. "NSNID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SNID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSNID." "0,1,2,3" bitfld.long 0x18 0.--1. "NSID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSID." "0,1,2,3" line.long 0x1C "APBADDR_CTI_CPU2_CTIDEVARCH,CTI Device Architecture Register" hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For CTI this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A." "0,1" hexmask.long.byte 0x1C 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For CTI the revision defined by v8-A is 0x0.All other values are reserved." newline hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For CTI:Bits [15:12] are the architecture version 0x1.Bits [11:0] are the architecture part number 0xA14.This corresponds to CTI.." line.long 0x20 "APBADDR_CTI_CPU2_CTIDEVID2,CTI Device ID Register 2" hexmask.long 0x20 0.--31. 1. "RES0_CTIDEVID2_31_0,Reserved RES0." line.long 0x24 "APBADDR_CTI_CPU2_CTIDEVID1,CTI Device ID Register 1" hexmask.long 0x24 0.--31. 1. "RES0_CTIDEVID1_31_0,Reserved RES0." line.long 0x28 "APBADDR_CTI_CPU2_CTIDEVID,CTI Device ID Register 0" hexmask.long.byte 0x28 26.--31. 1. "RES0_CTIDEVID_31_26,Reserved RES0." bitfld.long 0x28 24.--25. "INOUT,Input/output options. Indicates presence of the input gate. If the CTM is not implemented this field is RAZ. 00 CTIGATE does not mask propagation of input events from external channels. 01.." "0,1,2,3" bitfld.long 0x28 22.--23. "RES0_CTIDEVID_23_22,Reserved RES0." "0,1,2,3" newline hexmask.long.byte 0x28 16.--21. 1. "NUMCHAN,Number of ECT channels implemented. IMPLEMENTATION DEFINED. For v8-A valid values are: 000011 3 channels [0..2] implemented. 000100 4 channels [0..3] implemented." bitfld.long 0x28 14.--15. "RES0_CTIDEVID_15_14,Reserved RES0." "0,1,2,3" hexmask.long.byte 0x28 8.--13. 1. "NUMTRIG,Number of triggers implemented. IMPLEMENTATION DEFINED. This is one more than the index of the largest trigger rather than the actual number of triggers.For v8-A valid values are: 000011 Up to 3 triggers [0..2] implemented." newline bitfld.long 0x28 5.--7. "RES0_CTIDEVID_7_5,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 0.--4. 1. "EXTMUXNUM,Maximum number of external triggers available for multiplexing into the CTI. This relates only to additional external triggers outside those defined for v8-A." line.long 0x2C "APBADDR_CTI_CPU2_CTIDEVTYPE,CTI Device Type Register" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_CTIDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x2C 4.--7. 1. "SUB,Subtype. Must read as 0x1 to indicate this is a processor component." hexmask.long.byte 0x2C 0.--3. 1. "MAJOR,Major type. Must read as 0x4 to indicate this is a cross-trigger component." line.long 0x30 "APBADDR_CTI_CPU2_CTIPIDR4,CTI Peripheral Identification Register 4" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_CTIPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x30 4.--7. 1. "SIZE,Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers." hexmask.long.byte 0x30 0.--3. 1. "DES_2,Designer JEP106 continuation code least significant nibble. For ARM Limited this field is 0b0100." line.long 0x34 "APBADDR_CTI_CPU2_CTIPIDR5,CTI Peripheral Identification Register 5" hexmask.long 0x34 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x38 "APBADDR_CTI_CPU2_CTIPIDR6,CTI Peripheral Identification Register 6" hexmask.long 0x38 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x3C "APBADDR_CTI_CPU2_CTIPIDR7,CTI Peripheral Identification Register 7" hexmask.long 0x3C 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x40 "APBADDR_CTI_CPU2_CTIPIDR0,CTI Peripheral Identification Register 0" hexmask.long.tbyte 0x40 8.--31. 1. "RES0_CTIPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x40 0.--7. 1. "PART_0,Part number least significant byte." line.long 0x44 "APBADDR_CTI_CPU2_CTIPIDR1,CTI Peripheral Identification Register 1" hexmask.long.tbyte 0x44 8.--31. 1. "RES0_CTIPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x44 4.--7. 1. "DES_0,Designer least significant nibble of JEP106 ID code. For ARM Limited this field is 0b1011." hexmask.long.byte 0x44 0.--3. 1. "PART_1,Part number most significant nibble." line.long 0x48 "APBADDR_CTI_CPU2_CTIPIDR2,CTI Peripheral Identification Register 2" hexmask.long.tbyte 0x48 8.--31. 1. "RES0_CTIPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x48 4.--7. 1. "REVISION,Part major revision. Parts can also use this field to extend Part number to 16-bits." bitfld.long 0x48 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" newline bitfld.long 0x48 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0x4C "APBADDR_CTI_CPU2_CTIPIDR3,CTI Peripheral Identification Register 3" hexmask.long.tbyte 0x4C 8.--31. 1. "RES0_CTIPIDR3_31_8,Reserved RES0." hexmask.long.byte 0x4C 4.--7. 1. "REVAND,Part minor revision. Parts using CTIPIDR2.REVISION as an extension to the Part number must use this field as a major revision number." hexmask.long.byte 0x4C 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x50 "APBADDR_CTI_CPU2_CTICIDR0,CTI Component Identification Register 0" hexmask.long.tbyte 0x50 8.--31. 1. "RES0_CTICIDR0_31_8,Reserved RES0." hexmask.long.byte 0x50 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x54 "APBADDR_CTI_CPU2_CTICIDR1,CTI Component Identification Register 1" hexmask.long.tbyte 0x54 8.--31. 1. "RES0_CTICIDR1_31_8,Reserved RES0." hexmask.long.byte 0x54 4.--7. 1. "CLASS,Component class. Reads as 0x9 debug component." hexmask.long.byte 0x54 0.--3. 1. "PRMBL_1,Preamble. RAZ." line.long 0x58 "APBADDR_CTI_CPU2_CTICIDR2,CTI Component Identification Register 2" hexmask.long.tbyte 0x58 8.--31. 1. "RES0_CTICIDR2_31_8,Reserved RES0." hexmask.long.byte 0x58 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x5C "APBADDR_CTI_CPU2_CTICIDR3,CTI Component Identification Register 3" hexmask.long.tbyte 0x5C 8.--31. 1. "RES0_CTICIDR3_31_8,Reserved RES0." hexmask.long.byte 0x5C 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree "A53SS0_CORE2_DBG" base ad:0x730210000 group.long 0x20++0x7 line.long 0x0 "APBADDR_DBG_CPU2_EDESR,External Debug Event Status Register" hexmask.long 0x0 3.--31. 1. "RES0_EDESR_31_3,Reserved RES0." bitfld.long 0x0 2. "SS,Halting step debug event pending. Possible values of this field are: 0 Reading this means that a Halting step debug event is not pending. Writing this means no action. 1 Reading this means that.." "0,1" newline bitfld.long 0x0 1. "RC,Reset catch debug event pending. Possible values of this field are: 0 Reading this means that a Reset catch debug event is not pending. Writing this means no action. 1 Reading this means that a.." "0,1" bitfld.long 0x0 0. "OSUC,OS unlock debug event pending. Possible values of this field are: 0 Reading this means that an OS unlock catch debug event is not pending. Writing this means no action. 1 Reading this means.." "0,1" line.long 0x4 "APBADDR_DBG_CPU2_EDECR,External Debug Execution Control Register" hexmask.long 0x4 3.--31. 1. "RES0_EDECR_31_3,Reserved RES0." bitfld.long 0x4 2. "SS,Halting step enable. Possible values of this field are: 0 Halting step debug event disabled. 1 Halting step debug event enabled. If the value of EDECR.SS is changed when the.." "0,1" newline bitfld.long 0x4 1. "RCE,Reset catch enable. Possible values of this field are: 0 Reset catch debug event disabled. 1 Reset catch debug event enabled." "0,1" bitfld.long 0x4 0. "OSUCE,OS unlock catch enabled. Possible values of this field are: 0 OS unlock catch debug event disabled. 1 OS unlock catch debug event enabled." "0,1" group.long 0x30++0x7 line.long 0x0 "APBADDR_DBG_CPU2_EDWAR_31_0,External Debug Watchpoint Address Register (low word)" hexmask.long 0x0 0.--31. 1. "EDWAR_31_0,Watchpoint address. The virtual data address being accessed when a watchpoint debug event was triggered and caused entry to Debug state.UNKNOWN if the processor is not in Debug state or if Debug state was entered other than for a watchpoint.." line.long 0x4 "APBADDR_DBG_CPU2_EDWAR_63_32,External Debug Watchpoint Address Register (high word)" hexmask.long 0x4 0.--31. 1. "EDWAR_63_32,Watchpoint address. The virtual data address being accessed when a watchpoint debug event was triggered and caused entry to Debug state.UNKNOWN if the processor is not in Debug state or if Debug state was entered other than for a watchpoint.." group.long 0x80++0x1B line.long 0x0 "APBADDR_DBG_CPU2_DBGDTRRX_EL0,Debug Data Transfer Register Receive" hexmask.long 0x0 0.--31. 1. "DBGDTRRX_EL0,Update DTRRX. Writes to this register update the value in DTRRX and set RXfull to 1.Reads of this register return the last value written to DTRRX and do not change RXfull." line.long 0x4 "APBADDR_DBG_CPU2_EDITR,External Debug Instruction Transfer Register" hexmask.long 0x4 0.--31. 1. "EDITR,Used in Debug state for passing instructions to the processor for execution" line.long 0x8 "APBADDR_DBG_CPU2_EDSCR,External Debug Status and Control Register" bitfld.long 0x8 31. "RES0_EDSCR_31_31,Reserved RES0." "0,1" bitfld.long 0x8 30. "RXFULL,DTRRX full. This bit is RO." "0,1" newline bitfld.long 0x8 29. "TXFULL,DTRTX full. This bit is RO." "0,1" bitfld.long 0x8 28. "ITO,EDITR overrun. This bit is RO.If the processor is not in Debug state this bit is UNKNOWN. ITO is set to 0 on entry to Debug state." "0,1" newline bitfld.long 0x8 27. "RXO,DTRRX overrun. This bit is RO." "0,1" bitfld.long 0x8 26. "TXU,DTRTX underrun. This bit is RO." "0,1" newline bitfld.long 0x8 25. "PIPEADV,Pipeline advance. Read-only. Set to 1 every time the processor pipeline retires one or more instructions. Cleared to 0 by a write to EDRCR.CSPA.The architecture does not define precisely when this bit is set to 1. It requires only that this.." "0,1" bitfld.long 0x8 24. "ITE,ITR empty. This bit is RO.If the processor is not in Debug state this bit is UNKNOWN. It is always valid in Debug state." "0,1" newline bitfld.long 0x8 22.--23. "INTDIS,Interrupt disable. Disables taking interrupts [including virtual interrupts and System Error interrupts] in Non-Debug state.If external invasive debug is disabled the value of this field is ignored.If external invasive debug is enabled the.." "0,1,2,3" bitfld.long 0x8 21. "TDA,Trap debug registers accesses." "0,1" newline bitfld.long 0x8 20. "MA,Memory access mode. Controls use of memory-access mode for accessing EDITR and the DCC. This bit is ignored if in Non-debug state and set to zero on entry to Debug state.Possible values of this field are: 0 Normal access mode.." "0,1" bitfld.long 0x8 19. "RES0_EDSCR_19_19,Reserved RES0." "0,1" newline bitfld.long 0x8 18. "NS,Non-secure status. Read-only. When in Debug state gives the current security state: 0 Secure state IsSecure[] == TRUE 1 Non-secure state IsSecure[] == FALSE. In Non-debug.." "0,1" bitfld.long 0x8 17. "RES0_EDSCR_17_17,Reserved RES0." "0,1" newline bitfld.long 0x8 16. "SDD,Secure debug disabled. This bit is RO.On entry to Debug state:If entering in Secure state SDD is set to 0.If entering in Non-secure state SDD is set to the inverse of ExternalSecureInvasiveDebugEnabled[].In Debug state the value of the SDD bit.." "0,1" bitfld.long 0x8 15. "RES0_EDSCR_15_15,Reserved RES0." "0,1" newline bitfld.long 0x8 14. "HDE,Halting debug mode enable. Possible values of this bit are: 0 Halting debug mode disabled. 1 Halting debug mode enabled." "0,1" hexmask.long.byte 0x8 10.--13. 1. "RW,Exception level register-width status. Read-only. In Debug state each bit gives the current register width status of each EL: 1111 All exception levels are AArch64 state. 1110 EL0 is AArch32.." newline bitfld.long 0x8 8.--9. "EL,Exception level. Read-only. In Debug state this gives the current EL of the processor.In Non-debug state this field is RAZ." "0,1,2,3" bitfld.long 0x8 7. "A,System Error interrupt pending. Read-only. In Debug state indicates whether a SError interrupt is pending:If HCR_EL2.{AMO TGE} = {1 0} and in Non-secure EL0 or EL1 a virtual SError interrupt.Otherwise a physical SError interrupt. 0.." "0,1" newline bitfld.long 0x8 6. "ERR,Cumulative error flag. This field is RO. It is set to 1 following exceptions in Debug state and on any signaled overrun or underrun on the DTR or EDITR." "0,1" hexmask.long.byte 0x8 0.--5. 1. "STATUS,Debug status flags. This field is RO.The possible values of this field are: 000010 Processor is in Non-debug state. 000001 Processor is restarting [exiting Debug state]." line.long 0xC "APBADDR_DBG_CPU2_DBGDTRTX_EL0,Debug Data Transfer Register Transmit" hexmask.long 0xC 0.--31. 1. "DBGDTRTX_EL0,Return DTRTX. Reads of this register return the value in DTRTX and clear TXfull to 0.Writes of this register update the value in DTRTX and do not change TXfull." line.long 0x10 "APBADDR_DBG_CPU2_EDRCR,External Debug Reserve Control Register" hexmask.long 0x10 5.--31. 1. "RES0_EDRCR_31_5,Reserved RES0." bitfld.long 0x10 4. "CBRRQ,Allow imprecise entry to Debug state. The actions on writing to this bit are: 0 No action. 1 Allow imprecise entry to Debug state for example by canceling pending bus accesses." "0,1" newline bitfld.long 0x10 3. "CSPA,Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The actions on writing to this bit are: 0 No action. 1 Clear the EDSCR.PipeAdv bit to 0." "0,1" bitfld.long 0x10 2. "CSE,Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The actions on writing to this bit are: 0 No action. 1 Clear the EDSCR.{TXU RXO ERR} bits and if the processor is in.." "0,1" newline bitfld.long 0x10 0.--1. "RES0_EDRCR_1_0,Reserved RES0." "0,1,2,3" line.long 0x14 "APBADDR_DBG_CPU2_EDACR,External Debug Auxiliary Control Register" hexmask.long 0x14 0.--31. 1. "RES0_EDACR_31_0,Reserved RES0" line.long 0x18 "APBADDR_DBG_CPU2_EDECCR,External Debug Exception Catch Control Register" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDECCR_31_8,Reserved RES0." hexmask.long.byte 0x18 4.--7. 1. "NSE,Coarse-grained Non-secure exception catch. Possible values of this field are: 0000 Exception catch debug event disabled for Non-secure exception levels. 0010 Exception catch debug event enabled.." newline hexmask.long.byte 0x18 0.--3. 1. "SE,Coarse-grained Secure exception catch. Possible values of this field are: 0000 Exception catch debug event disabled for Secure exception levels. 0010 Exception catch debug event enabled for.." group.long 0xA0++0xF line.long 0x0 "APBADDR_DBG_CPU2_EDPCSR_31_0,External Debug Program Counter Sample Register (low word)" hexmask.long 0x0 0.--31. 1. "EDPCSR_31_0,PC Sample low word EDPCSRlo. Bits [31:0] of the sampled instruction address value. Reading EDPCSRlo has the side-effect of updating EDCIDSR EDVIDSR and EDPCSRhi. However:If the processor is in Debug state or Sample-based profiling is.." line.long 0x4 "APBADDR_DBG_CPU2_EDCIDSR,External Debug Context ID Sample Register" hexmask.long 0x4 0.--31. 1. "CONTEXTIDR,The sampled value of CONTEXTIDR_EL1 captured on reading the low half of EDPCSR.If EL3 is implemented and using AArch32 then CONTEXTIDR is a Banked register and EDCIDSR samples the current Banked copy of CONTEXTIDR." line.long 0x8 "APBADDR_DBG_CPU2_EDVIDSR,External Debug Virtual Context Sample Register" bitfld.long 0x8 31. "NS,Non-secure state sample. Indicates the security state associated with the most recent EDPCSR sample." "0,1" bitfld.long 0x8 30. "E2,Exception level 2 status sample. Indicates whether the most recent EDPCSR sample was associated with EL2. If EDVIDSR.NS == 0 this bit is 0." "0,1" newline bitfld.long 0x8 29. "E3,Exception level 3 status sample. Indicates whether the most recent EDPCSR sample was associated with AArch64 EL3. If EDVIDSR.NS == 1 or the processor was in AArch32 state when EDPCSR was read this bit is 0." "0,1" bitfld.long 0x8 28. "HV,EDPCSR high half valid. Indicates whether bits [63:32] of the most recent EDPCSR sample are valid. If EDVIDSR.HV == 0 the value of EDPCSR[63:32] is RAZ." "0,1" newline hexmask.long.tbyte 0x8 8.--27. 1. "RES0_EDVIDSR_27_8,Reserved RES0." hexmask.long.byte 0x8 0.--7. 1. "VMID,VMID sample. The value of VTTBR_EL2.VMID associated with the most recent EDPCSR sample. If EDVIDSR.NS == 0 or EDVIDSR.E2 == 1 this field is RAZ." line.long 0xC "APBADDR_DBG_CPU2_EDPCSR_63_32,External Debug Program Counter Sample Register (high word)" hexmask.long 0xC 0.--31. 1. "EDPCSR_63_32,PC Sample high word EDPCSRhi. If EDVIDSR.HV == 0 then this field is RAZ otherwise bits [63:32] of the sampled PC." group.long 0x300++0x3 line.long 0x0 "APBADDR_DBG_CPU2_OSLAR_EL1,OS Lock Access Register" hexmask.long 0x0 1.--31. 1. "RES0_OSLAR_EL1_31_1,Reserved RES0." bitfld.long 0x0 0. "OSLK,On writes to OSLAR_EL1 bit[0] is copied to the OS lock.Use EDPRSR.OSLK to check the current status of the lock." "0,1" group.long 0x310++0x7 line.long 0x0 "APBADDR_DBG_CPU2_EDPRCR,External Debug Power/Reset Control Register" hexmask.long 0x0 4.--31. 1. "RES0_EDPRCR_31_4,Reserved RES0." bitfld.long 0x0 3. "COREPURQ,Core powerup request. Allows a debugger to request that the power controller power up the core enabling access to the debug register in the Core power domain. The actions on writing to this bit are: 0 No effect." "0,1" newline bitfld.long 0x0 2. "RES0_EDPRCR_2_2,Reserved RES0." "0,1" bitfld.long 0x0 1. "CWRR,Warm reset request. Write only bit that reads as zero. The actions on writing to this bit are: 0 No action. 1 Request Warm reset. The processor ignores writes to this bit if.." "0,1" newline bitfld.long 0x0 0. "CORENPDRQ,Core no powerdown request. Requests emulation of powerdown. Possible values of this bit are: 0 On a powerdown request the system powers down the Core power domain. 1 On a powerdown.." "0,1" line.long 0x4 "APBADDR_DBG_CPU2_EDPRSR,External Debug Processor Status Register" hexmask.long.tbyte 0x4 12.--31. 1. "RES0_EDPRSR_31_12,Reserved RES0." bitfld.long 0x4 11. "SDR,Sticky debug restart. Set to 1 when the processor exits Debug state and cleared to 0 following reads of EDPRSR. 0 The processor has not restarted since EDPRSR was last read. 1 The processor has.." "0,1" newline bitfld.long 0x4 10. "SPMAD,Sticky EPMAD error. Set to 1 if an access returns an error because AllowExternalPMUAccess[] == FALSE. 0 No accesses to the external performance monitors registers have failed since EDPRSR was last read. 1.." "0,1" bitfld.long 0x4 9. "EPMAD,External performance monitors access disable status. 0 External performance monitors access enabled. 1 External performance monitors access disabled. If external performance.." "0,1" newline bitfld.long 0x4 8. "SDAD,Sticky EDAD error. Set to 1 if an access returns an error because AllowExternalDebugAccess[] == FALSE. 0 No accesses to the external debug registers have failed since EDPRSR was last read. 1.." "0,1" bitfld.long 0x4 7. "EDAD,External debug access disable status. 0 External debug access enabled. 1 External debug access disabled. This bit is UNKNOWN on reads if either of EDPRSR.{DLK R} is 1 or.." "0,1" newline bitfld.long 0x4 6. "DLK,OS Double Lock status bit. 0 OSDLR_EL1.DLK == 0 or EDPRCR.CORENPDRQ == 1 or the processor is in Debug state. 1 OSDLR_EL1.DLK == 1 and EDPRCR.CORENPDRQ == 0 and the processor is in Non-debug.." "0,1" bitfld.long 0x4 5. "OSLK,OS lock status bit. A read of this bit returns the value of OSLSR_EL1.OSLK.This bit is UNKNOWN on reads if either of EDPRSR.{DLK R} is 1 or EDPRSR.PU is 0." "0,1" newline bitfld.long 0x4 4. "HALTED,Halted status bit. Possible values are: 0 EDSCR.STATUS is 0b000010 [processor in Non-debug state]. 1 EDSCR.STATUS is not 0b000010. This bit is UNKNOWN on reads if EDPRSR.PU.." "0,1" bitfld.long 0x4 3. "SR,Sticky core reset status bit. Possible values are: 0 The non-debug logic of the processor is not in reset state and has not been reset since the last time EDPRSR was read. 1 The non-debug logic.." "0,1" newline bitfld.long 0x4 2. "R,Core reset status bit. Possible values are: 0 The non-debug logic of the processor is not in reset state. 1 The non-debug logic of the processor is in reset state. This bit is.." "0,1" bitfld.long 0x4 1. "SPD,Sticky core power-down status bit.This bit is set to 1 on Cold reset to indicate the state of the debug registers has been lost. Since a Cold reset is required on powering up the processor this usually indicates the Core power domain has been.." "0,1" newline bitfld.long 0x4 0. "PU,Core power-up status bit. Indicates whether the Core power domain debug registers can be accessed: 0 Core is in a low-power or power-down state where the debug registers cannot be accessed. 1.." "0,1" group.long 0x400++0xB line.long 0x0 "APBADDR_DBG_CPU2_DBGBVR0_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR0_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR0_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU2_DBGBVR0_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR0_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR0_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU2_DBGBCR0_EL1,Debug Breakpoint Control Register 0" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR0_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR0_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR0_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x410++0xB line.long 0x0 "APBADDR_DBG_CPU2_DBGBVR1_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR1_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR1_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU2_DBGBVR1_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR1_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR1_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU2_DBGBCR1_EL1,Debug Breakpoint Control Register 1" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR1_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR1_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR1_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x420++0xB line.long 0x0 "APBADDR_DBG_CPU2_DBGBVR2_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR2_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR2_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU2_DBGBVR2_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR2_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR2_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU2_DBGBCR2_EL1,Debug Breakpoint Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR2_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR2_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR2_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x430++0xB line.long 0x0 "APBADDR_DBG_CPU2_DBGBVR3_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR3_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR3_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU2_DBGBVR3_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR3_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR3_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU2_DBGBCR3_EL1,Debug Breakpoint Control Register 3" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR3_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR3_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR3_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x440++0xB line.long 0x0 "APBADDR_DBG_CPU2_DBGBVR4_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR4_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR4_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU2_DBGBVR4_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR4_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR4_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU2_DBGBCR4_EL1,Debug Breakpoint Control Register 4" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR4_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR4_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR4_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x450++0xB line.long 0x0 "APBADDR_DBG_CPU2_DBGBVR5_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR5_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR5_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU2_DBGBVR5_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR5_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR5_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU2_DBGBCR5_EL1,Debug Breakpoint Control Register 5" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR5_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR5_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR5_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x800++0xB line.long 0x0 "APBADDR_DBG_CPU2_DBGWVR0_EL1_31_0,Debug Watchpoint Value Register 0" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR0_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU2_DBGWVR0_EL1_63_32,Debug Watchpoint Extended Value Register 0" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU2_DBGWCR0_EL1,Debug Watchpoint Control Register 0" bitfld.long 0x8 29.--31. "RES0_DBGWCR0_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR0_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0x810++0xB line.long 0x0 "APBADDR_DBG_CPU2_DBGWVR1_EL1_31_0,Debug Watchpoint Value Register 1" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR1_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU2_DBGWVR1_EL1_63_32,Debug Watchpoint Extended Value Register 1" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU2_DBGWCR1_EL1,Debug Watchpoint Control Register 1" bitfld.long 0x8 29.--31. "RES0_DBGWCR1_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR1_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0x820++0xB line.long 0x0 "APBADDR_DBG_CPU2_DBGWVR2_EL1_31_0,Debug Watchpoint Value Register 2" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR2_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU2_DBGWVR2_EL1_63_32,Debug Watchpoint Extended Value Register 2" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU2_DBGWCR2_EL1,Debug Watchpoint Control Register 2" bitfld.long 0x8 29.--31. "RES0_DBGWCR2_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR2_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0x830++0xB line.long 0x0 "APBADDR_DBG_CPU2_DBGWVR3_EL1_31_0,Debug Watchpoint Value Register 3" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR3_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU2_DBGWVR3_EL1_63_32,Debug Watchpoint Extended Value Register 3" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU2_DBGWCR3_EL1,Debug Watchpoint Control Register 3" bitfld.long 0x8 29.--31. "RES0_DBGWCR3_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR3_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0xD00++0x3 line.long 0x0 "APBADDR_DBG_CPU2_MIDR_EL1,Main ID Register" hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,The Implementer code. This field must hold an implementer code that has been assigned by ARM." hexmask.long.byte 0x0 20.--23. 1. "VARIANT,An IMPLEMENTATION DEFINED variant number. Typically this field is used to distinguish between different product variants or major revisions of a product." newline hexmask.long.byte 0x0 16.--19. 1. "ARCHITECTURE" hexmask.long.word 0x0 4.--15. 1. "PARTNUM,An IMPLEMENTATION DEFINED primary part number for the device. On processors implemented by ARM if the top four bits of the primary part number are 0x0 or 0x7 the variant and architecture are encoded differently" newline hexmask.long.byte 0x0 0.--3. 1. "REVISION,An IMPLEMENTATION DEFINED revision number for the device" group.long 0xD20++0x3F line.long 0x0 "APBADDR_DBG_CPU2_ID_AA64PFR0_EL1_31_0,Processor Feature Register 0 (low word)" hexmask.long.byte 0x0 28.--31. 1. "RES0_ID_AA64PFR0_EL1_31_0_31_28,Reserved RES0." hexmask.long.byte 0x0 24.--27. 1. "GIC,GIC system register interface. Permitted values are: 0000 No GIC system registers are supported. 0001 GICv3 system registers are supported. All other values are reserved." newline hexmask.long.byte 0x0 20.--23. 1. "ADVSIMD,Advanced SIMD. Permitted values are: 0000 Advanced SIMD is implemented. 1111 Advanced SIMD is not implemented. All other values are reserved." hexmask.long.byte 0x0 16.--19. 1. "FP,Floating-point. Permitted values are: 0000 Floating-point is implemented. 1111 Floating-point is not implemented. All other values are reserved." newline hexmask.long.byte 0x0 12.--15. 1. "EL3,EL3 exception level handling. Permitted values are: 0000 EL3 is not implemented. 0001 EL3 can be executed in AArch64 state only. 0010 EL3 can be executed.." hexmask.long.byte 0x0 8.--11. 1. "EL2,EL2 exception level handling. Permitted values are: 0000 EL2 is not implemented. 0001 EL2 can be executed in AArch64 state only. 0010 EL2 can be executed.." newline hexmask.long.byte 0x0 4.--7. 1. "EL1,EL1 exception level handling. Permitted values are: 0000 EL1 is not implemented. 0001 EL1 can be executed in AArch64 state only. 0010 EL1 can be executed.." hexmask.long.byte 0x0 0.--3. 1. "EL0,EL0 exception level handling. Permitted values are: 0000 EL0 is not implemented. 0001 EL0 can be executed in AArch64 state only. 0010 EL0 can be executed.." line.long 0x4 "APBADDR_DBG_CPU2_ID_AA64PFR0_EL1_63_32,Processor Feature Register 0 (high word)" hexmask.long 0x4 0.--31. 1. "RES0_ID_AA64PFR0_EL1_63_32_31_0,Reserved RES0." line.long 0x8 "APBADDR_DBG_CPU2_ID_AA64DFR0_EL1_31_0,Debug Feature Register 0 (low word)" hexmask.long.byte 0x8 28.--31. 1. "CTX_CMPS,Number of breakpoints that are context-aware minus 1. These are the highest numbered breakpoints." hexmask.long.byte 0x8 24.--27. 1. "RES0_ID_AA64DFR0_EL1_31_0_27_24,Reserved RES0." newline hexmask.long.byte 0x8 20.--23. 1. "WRPS,Number of watchpoints minus 1. The value of 0b0000 is reserved." hexmask.long.byte 0x8 16.--19. 1. "RES0_ID_AA64DFR0_EL1_31_0_19_16,Reserved RES0." newline hexmask.long.byte 0x8 12.--15. 1. "BRPS,Number of breakpoints minus 1. The value of 0b0000 is reserved." hexmask.long.byte 0x8 8.--11. 1. "PMUVER,Performance Monitors extension version. Indicates whether system register interface to Performance Monitors extension is implemented. Permitted values are: 0000 Performance Monitors extension system registers not implemented." newline hexmask.long.byte 0x8 4.--7. 1. "TRACEVER,Trace extension. Indicates whether system register interface to Trace extension is implemented. Permitted values are: 0000 Trace extension system registers not implemented. 0001 Trace.." hexmask.long.byte 0x8 0.--3. 1. "DEBUGVER,Debug architecture version. Indicates presence of v8-A debug architecture. 0110 v8-A debug architecture. All other values are reserved." line.long 0xC "APBADDR_DBG_CPU2_ID_AA64DFR0_EL1_63_32,Debug Feature Register 0 (high word)" hexmask.long 0xC 0.--31. 1. "RES0_ID_AA64DFR0_EL1_63_32_31_0,Reserved RES0." line.long 0x10 "APBADDR_DBG_CPU2_ID_AA64ISAR0_EL1_31_0,Instruction Set Attribute Register 0 (low word)" hexmask.long.word 0x10 20.--31. 1. "RES0_ID_AA64ISAR0_EL1_31_0_31_20,Reserved RES0." hexmask.long.byte 0x10 16.--19. 1. "CRC32,CRC32 instructions in AArch64. Possible values of this field are: 0000 No CRC32 instructions implemented. 0001 CRC32B CRC32H CRC32W CRC32X CRC32CB CRC32CH CRC32CW and CRC32CX.." newline hexmask.long.byte 0x10 12.--15. 1. "SHA2,SHA2 instructions in AArch64. Possible values of this field are: 0000 No SHA2 instructions implemented. 0001 SHA256H SHA256H2 SHA256SU0 and SHA256SU1 instructions implemented." hexmask.long.byte 0x10 8.--11. 1. "SHA1,SHA1 instructions in AArch64. Possible values of this field are: 0000 No SHA1 instructions implemented. 0001 SHA1C SHA1P SHA1M SHA1H SHA1SU0 and SHA1SU1 instructions implemented." newline hexmask.long.byte 0x10 4.--7. 1. "AES,AES instructions in AArch64. Possible values of this field are: 0000 No AES instructions implemented. 0001 AESE AESD AESMC and AESIMC instructions implemented. 0010.." hexmask.long.byte 0x10 0.--3. 1. "RES0_ID_AA64ISAR0_EL1_31_0_3_0,Reserved RES0." line.long 0x14 "APBADDR_DBG_CPU2_ID_AA64ISAR0_EL1_63_32,Instruction Set Attribute Register 0 (high word)" hexmask.long 0x14 0.--31. 1. "RES0_ID_AA64ISAR0_EL1_63_32_31_0,Reserved RES0." line.long 0x18 "APBADDR_DBG_CPU2_ID_AA64MMFR0_EL1_31_0,Memory Model Feature Register 0 (low word)" hexmask.long.byte 0x18 28.--31. 1. "TGRAN4,Support for 4 Kbyte memory translation granule size. Permitted values are: 0000 4 KB granule supported. 1111 4 KB granule not supported. All other values are reserved." hexmask.long.byte 0x18 24.--27. 1. "TGRAN64,Support for 64 Kbyte memory translation granule size. Permitted values are: 0000 64 KB granule supported. 1111 64 KB granule not supported. All other values are reserved." newline hexmask.long.byte 0x18 20.--23. 1. "TGRAN16,Support for 16 Kbyte memory translation granule size. Permitted values are: 0000 16 KB granule not supported. 0001 16 KB granule supported. All other values are reserved." hexmask.long.byte 0x18 16.--19. 1. "BIGENDEL0,Mixed-endian support at EL0 only. Permitted values are: 0000 No mixed-endian support at EL0. The SCTLR_EL1.E0E bit has a fixed value. 0001 Mixed-endian support at EL0. The SCTLR_EL1.E0E.." newline hexmask.long.byte 0x18 12.--15. 1. "SNSMEM,Secure versus Non-secure Memory distinction. Permitted values are: 0000 Does not support a distinction between Secure and Non-secure Memory. 0001 Does support a distinction between Secure.." hexmask.long.byte 0x18 8.--11. 1. "BIGEND,Mixed-endian configuration support. Permitted values are: 0000 No mixed-endian support. The SCTLR_ELx.EE bits have a fixed value. See the BigEndEL0 field bits[19:16] for whether EL0 supports mixed-endian." newline hexmask.long.byte 0x18 4.--7. 1. "ASIDBITS,Number of ASID bits. Permitted values are: 0000 8 bits. 0010 16 bits. All other values are reserved." hexmask.long.byte 0x18 0.--3. 1. "PARANGE,Physical Address range supported. Permitted values are: 0000 32 bits 4 GB. 0001 36 bits 64 GB. 0010 40 bits 1 TB. 0011.." line.long 0x1C "APBADDR_DBG_CPU2_ID_AA64MMFR0_EL1_63_32,Memory Model Feature Register 0 (high word)" hexmask.long 0x1C 0.--31. 1. "RES0_ID_AA64MMFR0_EL1_63_32_31_0,Reserved RES0." line.long 0x20 "APBADDR_DBG_CPU2_ID_AA64PFR1_EL1_31_0,Processor Feature Register 1 (low word)" hexmask.long 0x20 0.--31. 1. "RES0_ID_AA64PFR1_EL1_31_0_31_0,Reserved RES0." line.long 0x24 "APBADDR_DBG_CPU2_ID_AA64PFR1_EL1_63_32,Processor Feature Register 1 (high word)" hexmask.long 0x24 0.--31. 1. "RES0_ID_AA64PFR1_EL1_63_32_31_0,Reserved RES0." line.long 0x28 "APBADDR_DBG_CPU2_ID_AA64DFR1_EL1_31_0,Auxiliary Feature Register 1 (low word)" hexmask.long 0x28 0.--31. 1. "RES0_ID_AA64DFR1_EL1_31_0_31_0,Reserved RES0." line.long 0x2C "APBADDR_DBG_CPU2_ID_AA64DFR1_EL1_63_32,Auxiliary Feature Register 1 (high word)" hexmask.long 0x2C 0.--31. 1. "RES0_ID_AA64DFR1_EL1_63_32_31_0,Reserved RES0." line.long 0x30 "APBADDR_DBG_CPU2_ID_AA64ISAR1_EL1_31_0,Instruction Set Attribute Register 1 (low word)" hexmask.long 0x30 0.--31. 1. "RES0_ID_AA64ISAR1_EL1_31_0_31_0,Reserved RES0." line.long 0x34 "APBADDR_DBG_CPU2_ID_AA64ISAR1_EL1_63_32,Instruction Set Attribute Register 1 (high word)" hexmask.long 0x34 0.--31. 1. "RES0_ID_AA64ISAR1_EL1_63_32_31_0,Reserved RES0." line.long 0x38 "APBADDR_DBG_CPU2_ID_AA64MMFR1_EL1_31_0,Memory Model Feature Register 1 (low word)" hexmask.long 0x38 0.--31. 1. "RES0_ID_AA64MMFR1_EL1_31_0_31_0,Reserved RES0." line.long 0x3C "APBADDR_DBG_CPU2_ID_AA64MMFR1_EL1_63_32,Memory Model Feature Register 1 (high word)" hexmask.long 0x3C 0.--31. 1. "RES0_ID_AA64MMFR1_EL1_63_32_31_0,Reserved RES0." group.long 0xF00++0x3 line.long 0x0 "APBADDR_DBG_CPU2_EDITCTRL,External Debug Integration mode Control Register" hexmask.long 0x0 1.--31. 1. "RES0_EDITCTRL_31_1,Reserved RES0." bitfld.long 0x0 0. "IME,Integration mode enable. When IME == 1 the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED. 0 Normal operation." "0,1" group.long 0xFA0++0x33 line.long 0x0 "APBADDR_DBG_CPU2_DBGCLAIMSET_EL1,Debug Claim Tag Set Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_DBGCLAIMSET_EL1_31_8,Reserved RAZ/SBZ. Software can rely on these bits reading as zero and must use a should-be-zero policy on writes. Implementations must ignore writes." hexmask.long.byte 0x0 0.--7. 1. "CLAIM,Claim set bits. RAO.Writing a 1 to one of these bits sets the corresponding CLAIM bit to 1. This is an indirect write to the CLAIM bits.A single write operation can set multiple bits to 1. Writing 0 to one of these bits has no effect." line.long 0x4 "APBADDR_DBG_CPU2_DBGCLAIMCLR_EL1,Debug Claim Tag Clear Register" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_DBGCLAIMCLR_EL1_31_8,Reserved RAZ/SBZ. Software can rely on these bits reading as zero and must use a should-be-zero policy on writes. Implementations must ignore writes." hexmask.long.byte 0x4 0.--7. 1. "CLAIM,Claim clear bits. Reading this field returns the current value of the CLAIM bits.Writing a 1 to one of these bits clears the corresponding CLAIM bit to 0. This is an indirect write to the CLAIM bits.A single write operation can clear multiple bits.." line.long 0x8 "APBADDR_DBG_CPU2_EDDEVAFF0,External Debug Device Affinity Register 0" hexmask.long 0x8 0.--31. 1. "EDDEVAFF0,MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0xC "APBADDR_DBG_CPU2_EDDEVAFF1,External Debug Device Affinity Register 1" hexmask.long 0xC 0.--31. 1. "EDDEVAFF1,MPIDR_EL1 high half. Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x10 "APBADDR_DBG_CPU2_EDLAR,External Debug Lock Access Register" hexmask.long 0x10 0.--31. 1. "KEY,Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register locks the lock disabling write.." line.long 0x14 "APBADDR_DBG_CPU2_EDLSR,External Debug Lock Status Register" hexmask.long 0x14 3.--31. 1. "RES0_EDLSR_31_3,Reserved RES0." bitfld.long 0x14 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" newline bitfld.long 0x14 1. "SLK,Software lock status for this component. For an access to LSR that is not a memory-mapped access or when the software lock is not implemented this field is RES0.For memory-mapped accesses when the software lock is implemented possible values of.." "0,1" bitfld.long 0x14 0. "SLI,Software lock implemented. For an access to LSR that is not a memory-mapped access this field is RAZ. For memory-mapped accesses the value of this field is IMPLEMENTATION DEFINED. Permitted values are: 0 Software lock not.." "0,1" line.long 0x18 "APBADDR_DBG_CPU2_DBGAUTHSTATUS_EL1,Debug Authentication Status register" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_DBGAUTHSTATUS_EL1_31_8,Reserved RES0." bitfld.long 0x18 6.--7. "SNID,Secure non-invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Non-secure. 10 Implemented and disabled." "0,1,2,3" newline bitfld.long 0x18 4.--5. "SID,Secure invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Non-secure. 10 Implemented and disabled." "0,1,2,3" bitfld.long 0x18 2.--3. "NSNID,Non-secure non-invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Secure. 10 Implemented and disabled." "0,1,2,3" newline bitfld.long 0x18 0.--1. "NSID,Non-secure invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Secure. 10 Implemented and disabled." "0,1,2,3" line.long 0x1C "APBADDR_DBG_CPU2_EDDEVARCH,External Debug Device Architecture Register" hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For debug this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A." "0,1" newline hexmask.long.byte 0x1C 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For debug the revision defined by v8-A is 0x0.All other values are reserved." hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For debug:Bits [15:12] are the architecture version 0x6.Bits [11:0] are the architecture part number 0xA15.This corresponds to debug.." line.long 0x20 "APBADDR_DBG_CPU2_EDDEVID2,External Debug Device ID Register 2" hexmask.long 0x20 0.--31. 1. "RES0_EDDEVID2_31_0,Reserved RES0." line.long 0x24 "APBADDR_DBG_CPU2_EDDEVID1,External Debug Device ID Register 1" hexmask.long 0x24 4.--31. 1. "RES0_EDDEVID1_31_4,Reserved RES0." hexmask.long.byte 0x24 0.--3. 1. "PCSROFFSET,This field indicates the offset applied to PC samples returned by reads of EDPCSR. Permitted values of this field in v8-A are: 0000 EDPCSR not implemented. 0010 EDPCSR implemented and.." line.long 0x28 "APBADDR_DBG_CPU2_EDDEVID,External Debug Device ID Register 0" hexmask.long.byte 0x28 28.--31. 1. "RES0_EDDEVID_31_28,Reserved RES0." hexmask.long.byte 0x28 24.--27. 1. "AUXREGS,Indicates support for Auxiliary registers. Permitted values for this field are: 0000 None supported. 0001 Support for External Debug Auxiliary Control Register EDACR. All.." newline hexmask.long.tbyte 0x28 4.--23. 1. "RES0_EDDEVID_23_4,Reserved RES0." hexmask.long.byte 0x28 0.--3. 1. "PCSAMPLE,Indicates the level of Sample-based profiling support using external debug registers 40 through 43. Permitted values of this field in v8-A are: 0000 Architecture-defined form of Sample-based profiling not implemented." line.long 0x2C "APBADDR_DBG_CPU2_EDDEVTYPE,External Debug Device Type Register" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_EDDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x2C 4.--7. 1. "SUB,Subtype. Must read as 0x1 to indicate this is a processor component." newline hexmask.long.byte 0x2C 0.--3. 1. "MAJOR,Major type. Must read as 0x5 to indicate this is a debug logic component." line.long 0x30 "APBADDR_DBG_CPU2_EDPIDR4,External Debug Peripheral Identification Register 4" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_EDPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x30 4.--7. 1. "SIZE,Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers." newline hexmask.long.byte 0x30 0.--3. 1. "DES_2,Designer JEP106 continuation code least significant nibble. For ARM Limited this field is 0b0100." group.long 0xFE0++0x1F line.long 0x0 "APBADDR_DBG_CPU2_EDPIDR0,External Debug Peripheral Identification Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_EDPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x0 0.--7. 1. "PART_0,Part number least significant byte." line.long 0x4 "APBADDR_DBG_CPU2_EDPIDR1,External Debug Peripheral Identification Register 1" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_EDPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x4 4.--7. 1. "DES_0,Designer least significant nibble of JEP106 ID code. For ARM Limited this field is 0b1011." newline hexmask.long.byte 0x4 0.--3. 1. "PART_1,Part number most significant nibble." line.long 0x8 "APBADDR_DBG_CPU2_EDPIDR2,External Debug Peripheral Identification Register 2" hexmask.long.tbyte 0x8 8.--31. 1. "RES0_EDPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x8 4.--7. 1. "REVISION,Part major revision. Parts can also use this field to extend Part number to 16-bits." newline bitfld.long 0x8 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" bitfld.long 0x8 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0xC "APBADDR_DBG_CPU2_EDPIDR3,External Debug Peripheral Identification Register 3" hexmask.long.tbyte 0xC 8.--31. 1. "RES0_EDPIDR3_31_8,Reserved RES0." hexmask.long.byte 0xC 4.--7. 1. "REVAND,Part minor revision. Parts using EDPIDR2.REVISION as an extension to the Part number must use this field as a major revision number." newline hexmask.long.byte 0xC 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x10 "APBADDR_DBG_CPU2_EDCIDR0,External Debug Component Identification Register 0" hexmask.long.tbyte 0x10 8.--31. 1. "RES0_EDCIDR0_31_8,Reserved RES0." hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x14 "APBADDR_DBG_CPU2_EDCIDR1,External Debug Component Identification Register 1" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_EDCIDR1_31_8,Reserved RES0." hexmask.long.byte 0x14 4.--7. 1. "CLASS,Component class. Reads as 0x9 debug component." newline hexmask.long.byte 0x14 0.--3. 1. "PRMBL_1,Preamble. RAZ." line.long 0x18 "APBADDR_DBG_CPU2_EDCIDR2,External Debug Component Identification Register 2" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDCIDR2_31_8,Reserved RES0." hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x1C "APBADDR_DBG_CPU2_EDCIDR3,External Debug Component Identification Register 3" hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_EDCIDR3_31_8,Reserved RES0." hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree "A53SS0_CORE2_ECC_AGGR" base ad:0x718C00 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_CORE2_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_CORE2_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_CORE2_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR_CORE2_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_CORE2_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_CORE2_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 26. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 25. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 24. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 23. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_CORE2_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 26. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_CORE2_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 26. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_CORE2_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_CORE2_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 26. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 25. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 24. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 23. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_CORE2_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 26. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_CORE2_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 26. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_CORE2_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_CORE2_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_CORE2_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_CORE2_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "A53SS0_CORE2_ETM" base ad:0x730230000 group.long 0x4++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCPRGCTLR,Programming Control Register" hexmask.long 0x0 1.--31. 1. "RES0_TRCPRGCTLR_31_1,Reserved RES0." bitfld.long 0x0 0. "EN,Trace unit enable bit. Possible values are: 0 The trace unit is disabled. All trace resources are inactive and no trace is generated. 1 The trace unit is enabled." "0,1" group.long 0xC++0x7 line.long 0x0 "APBADDR_ETM_CPU2_TRCSTATR,Status Register" hexmask.long 0x0 2.--31. 1. "RES0_TRCSTATR_31_2,Reserved RES0." bitfld.long 0x0 1. "PMSTABLE,Programmer's model stable bit: 0 The programmer's model is not stable. 1 The programmer's model is stable. When polled the trace unit trace registers return stable data." "0,1" bitfld.long 0x0 0. "IDLE,Idle status bit: 0 The trace unit is not idle. 1 The trace unit is idle. The trace unit is idle when all of the following are true:TRCPRGCTLR.EN==0 or the OS Lock is.." "0,1" line.long 0x4 "APBADDR_ETM_CPU2_TRCCONFIGR,Trace Configuration Register" hexmask.long.word 0x4 18.--31. 1. "RES0_TRCCONFIGR_31_18,Reserved RES0." bitfld.long 0x4 17. "DV,Data value tracing bit: 0 Data value tracing is disabled. 1 Data value tracing is enabled when INSTP0 is not 0b00. TRCIDR0.TRCDATA indicates whether this bit is supported. If.." "0,1" bitfld.long 0x4 16. "DA,Data address tracing bit: 0 Data address tracing is disabled. 1 Data address tracing is enabled when INSTP0 is not 0b00. TRCIDR0.TRCDATA indicates whether this bit is.." "0,1" newline bitfld.long 0x4 15. "RES0_TRCCONFIGR_15_15,Reserved RES0." "0,1" bitfld.long 0x4 13.--14. "QE,Q element enable field: 00 Q elements are disabled. 01 Q elements with instruction counts are enabled. Q elements without instruction counts are disabled. 11.." "0,1,2,3" bitfld.long 0x4 12. "RS,Return stack enable bit. 0 Return stack is disabled. 1 Return stack is enabled. TRCIDR0.RETSTACK indicates whether this bit is supported. If it is not supported then this bit.." "0,1" newline bitfld.long 0x4 11. "TS,Global timestamp tracing bit: 0 Global timestamp tracing is disabled. 1 Global timestamp tracing is enabled. TRCTSCTLR controls the insertion of timestamps in the trace." "0,1" bitfld.long 0x4 8.--10. "COND,Conditional instruction tracing bit. The permitted values are: 000 Conditional instruction tracing is disabled. 001 Conditional load instructions are traced. 010.." "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "VMID,VMID tracing bit: 0 VMID tracing is disabled. 1 VMID tracing is enabled. TRCIDR2.VMIDSIZE indicates whether this bit is supported. If it is not supported then this bit is RES0." "0,1" newline bitfld.long 0x4 6. "CID,Context ID tracing bit: 0 Context ID tracing is disabled. 1 Context ID tracing is enabled. TRCIDR2.CIDSIZE indicates whether this bit is supported. If it is not supported then.." "0,1" bitfld.long 0x4 5. "RES0_TRCCONFIGR_5_5,Reserved RES0." "0,1" bitfld.long 0x4 4. "CCI,Cycle counting instruction trace bit: 0 Cycle counting in the instruction trace is disabled. 1 Cycle counting in the instruction trace is enabled. TRCCCCTLR controls the threshold value for.." "0,1" newline bitfld.long 0x4 3. "BB,Branch broadcast mode bit: 0 Branch broadcast mode is disabled. 1 Branch broadcast mode is enabled. TRCBBCTLR controls which regions of memory are enabled to use branch broadcasting." "0,1" bitfld.long 0x4 1.--2. "INSTP0,Instruction P0 bit. This field controls whether load and store instructions are traced as P0 instructions: 00 Do not trace load and store instructions as P0 instructions. 01 Trace load.." "0,1,2,3" bitfld.long 0x4 0. "RES1_TRCCONFIGR_0_0,Reserved RES1." "0,1" group.long 0x18++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCAUXCTLR,Auxiliary Control Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_TRCAUXCTLR_31_8,Reserved RES0" bitfld.long 0x0 7. "COREIFEN,Keep core interface enabled regardless of trace enable register state" "0,1" bitfld.long 0x0 6. "RES0_TRCAUXCTLR_6_6,Reserved RES0" "0,1" newline bitfld.long 0x0 5. "AUTHNOFLUSH,Do not flush trace on de-assertion of authentication inputs. When this bit is set to 1 the trace unit behavior deviates from architecturally-specified behavior." "0,1" bitfld.long 0x0 4. "TSNODELAY,Do not delay timestamp insertion based on FIFO depth." "0,1" bitfld.long 0x0 3. "SYNCDELAY,Delay periodic synchronization if FIFO is more than half-full." "0,1" newline bitfld.long 0x0 2. "OVFLW,Force an overflow if synchronization is not completed when second synchronization becomes due. When this bit is set to 1 the trace unit behavior deviates from architecturally-specified behavior." "0,1" bitfld.long 0x0 1. "IDLEACK,Force idle-drain acknowledge high CPU does not wait for trace to drain before entering WFX state. When this bit is set to 1 trace unit behavior deviates from architecturally-specified behavior." "0,1" bitfld.long 0x0 0. "AFREADY,Always respond to AFREADY immediately. Does not have any interaction with FIFO draining even in WFI state." "0,1" group.long 0x20++0x7 line.long 0x0 "APBADDR_ETM_CPU2_TRCEVENTCTL0R,Event Control 0 Register" bitfld.long 0x0 31. "TYPE3,Selects the resource type for trace event 3" "0,1" bitfld.long 0x0 28.--30. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--27. 1. "SEL3,Selects the resource number based on the value of TYPE3" newline bitfld.long 0x0 23. "TYPE2,Selects the resource type for trace event 2" "0,1" bitfld.long 0x0 20.--22. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--19. 1. "SEL2,Selects the resource number based on the value of TYPE2" newline bitfld.long 0x0 15. "TYPE1,Selects the resource type for trace event 1" "0,1" bitfld.long 0x0 12.--14. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "SEL1,Selects the resource number based on the value of TYPE1" newline bitfld.long 0x0 7. "TYPE0,Selects the resource type for trace event 0" "0,1" bitfld.long 0x0 4.--6. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "SEL0,Selects the resource number based on the value of TYPE0" line.long 0x4 "APBADDR_ETM_CPU2_TRCEVENTCTL1R,Event Control 1 Register" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved RES0" bitfld.long 0x4 12. "LPOVERRIDE,Low power state behavior override" "0,1" bitfld.long 0x4 11. "ATB,ATB trigger enable" "0,1" newline hexmask.long.byte 0x4 4.--10. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "EN,One bit per event to enable generation of an event element in the instruction trace stream when the selected event occurs" group.long 0x2C++0x17 line.long 0x0 "APBADDR_ETM_CPU2_TRCSTALLCTLR,Stall Control Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved RES0" bitfld.long 0x0 8. "ISTALL,Controls if the trace unit can stall the processor when the instruction trace buffer space is less than LEVEL" "0,1" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved RES0" newline bitfld.long 0x0 2.--3. "LEVEL,The field can support 4 monotonic levels from 0b00 to 0b11" "0,1,2,3" bitfld.long 0x0 0.--1. "RESERVED,Reserved RES0" "0,1,2,3" line.long 0x4 "APBADDR_ETM_CPU2_TRCTSCTLR,Global Timestamp Control Register" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_TRCTSCTLR_31_8,Reserved RES0." hexmask.long.byte 0x4 0.--7. 1. "EVENT,An event selector. When the selected event is triggered the trace unit inserts a global timestamp into the trace streams." line.long 0x8 "APBADDR_ETM_CPU2_TRCSYNCPR,Synchronization Period Register" hexmask.long 0x8 5.--31. 1. "RES0_TRCSYNCPR_31_5,Reserved RES0." hexmask.long.byte 0x8 0.--4. 1. "PERIOD,Controls how many bytes of trace the sum of instruction and data that a trace unit can generate before a periodic trace synchronization request occurs. The number of bytes is always a power of two and the permitted values are: 00000.." line.long 0xC "APBADDR_ETM_CPU2_TRCCCCTLR,Cycle Count Control Register" hexmask.long.tbyte 0xC 12.--31. 1. "RES0_TRCCCCTLR_31_12,Reserved RES0." hexmask.long.word 0xC 0.--11. 1. "THRESHOLD,Sets the threshold value for instruction trace cycle counting.The minimum threshold value that can be programmed into THRESHOLD is given in TRCIDR3.CCITMIN.Writing a value of zero might cause UNPREDICTABLE behaviour." line.long 0x10 "APBADDR_ETM_CPU2_TRCBBCTLR,Branch Broadcast Control Register" hexmask.long.tbyte 0x10 9.--31. 1. "RES0_TRCBBCTLR_31_9,Reserved RES0." bitfld.long 0x10 8. "MODE,Mode bit: 0 Exclude mode. Branch broadcasting is not enabled in the address range that RANGE defines. If RANGE==0 then branch broadcasting is enabled for the entire memory map. 1 Include mode." "0,1" hexmask.long.byte 0x10 0.--7. 1. "RANGE,Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each bit represents an address range comparator pair so bit[n] controls the selection of address range comparator pair n. If bit[n] is: 0.." line.long 0x14 "APBADDR_ETM_CPU2_TRCTRACEIDR,Trace ID Register" hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x14 0.--6. 1. "TRACEID,Trace ID value. When only instruction tracing is enabled this provides the trace ID." group.long 0x80++0xB line.long 0x0 "APBADDR_ETM_CPU2_TRCVICTLR,ViewInst Main Control Register" hexmask.long.byte 0x0 24.--31. 1. "RES0_TRCVICTLR_31_24,Reserved RES0." hexmask.long.byte 0x0 20.--23. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Non-secure state for exception level n." hexmask.long.byte 0x0 16.--19. 1. "EXLEVEL_S,In Secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Secure state for exception level n. 1.." newline hexmask.long.byte 0x0 12.--15. 1. "RES0_TRCVICTLR_15_12,Reserved RES0." bitfld.long 0x0 11. "TRCERR,If TRCIDR3.TRCERR==1 this bit controls whether a trace unit must trace a system error exception: 0 The trace unit does not trace a system error exception unless it traces the exception or instruction immediately prior to the.." "0,1" bitfld.long 0x0 10. "TRCRESET,Controls whether a trace unit must trace a Reset exception: 0 The trace unit does not trace a Reset exception unless it traces the exception or instruction immediately prior to the Reset exception. 1.." "0,1" newline bitfld.long 0x0 9. "SSSTATUS,IF TRCIDR4.NUMACPAIRS>0 or TRCIDR.NUMPC>0 this bit returns the status of the start-stop logic: 0 The start-stop logic is in the stopped state. 1 The start-stop logic is in the started.." "0,1" bitfld.long 0x0 8. "RES0_TRCVICTLR_8_8,Reserved RES0." "0,1" hexmask.long.byte 0x0 0.--7. 1. "EVENT,An event selector. [TODO: Add the bit assignments for EVENT fields into the descriptions directly?]" line.long 0x4 "APBADDR_ETM_CPU2_TRCVIIECTLR,ViewInst Include-Exclude Control Register" hexmask.long.byte 0x4 24.--31. 1. "RES0_TRCVIIECTLR_31_24,Reserved RES0." hexmask.long.byte 0x4 16.--23. 1. "EXCLUDE,0 1 The implemented width of the field n is IMPLEMENTATION DEFINED and is set by the value of TRCIDR4.NUMACPAIRS. Unimplemented bits are RAZ/WI." hexmask.long.byte 0x4 8.--15. 1. "RES0_TRCVIIECTLR_15_8,Reserved RES0." newline hexmask.long.byte 0x4 0.--7. 1. "INCLUDE,Include range field. Selects which address range comparator pairs are in use with ViewInst include control. Each bit represents an address range comparator pair so bit[m] controls the selection of address range comparator pair m. If bit[m] is:.." line.long 0x8 "APBADDR_ETM_CPU2_TRCVISSCTLR,ViewInst Start-Stop Control Register" hexmask.long.word 0x8 16.--31. 1. "STOP,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of stopping trace. Each bit represents a single address comparator so bit[m] controls the selection of single address comparator m-16. If bit[m].." hexmask.long.word 0x8 0.--15. 1. "START,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of starting trace. Each bit represents a single address comparator so bit[n] controls the selection of single address comparator n. If bit[n] is:.." group.long 0x100++0xB line.long 0x0 "APBADDR_ETM_CPU2_TRCSEQEVR0,Sequencer State Transition Control Registers 0" hexmask.long.word 0x0 16.--31. 1. "RES0_TRCSEQEVR0_31_16,Reserved RES0." hexmask.long.byte 0x0 8.--15. 1. "B_N,Backward field. Contains an event number. When the event occurs then the sequencer state moves from state n+1 to state n.For example for TRCSEQEVR2 if B2==0x14 then when event 0x14 occurs the sequencer moves from state 3 to state 2." hexmask.long.byte 0x0 0.--7. 1. "F_N,Forward field. Contains an event number. When the event occurs then the sequencer state moves from state n to state n+1.For example for TRCSEQEVR1 if F1==0x12 then when event 0x12 occurs the sequencer moves from state 1 to state 2." line.long 0x4 "APBADDR_ETM_CPU2_TRCSEQEVR1,Sequencer State Transition Control Registers 1" hexmask.long.word 0x4 16.--31. 1. "RES0_TRCSEQEVR1_31_16,Reserved RES0." hexmask.long.byte 0x4 8.--15. 1. "B_N,Backward field. Contains an event number. When the event occurs then the sequencer state moves from state n+1 to state n.For example for TRCSEQEVR2 if B2==0x14 then when event 0x14 occurs the sequencer moves from state 3 to state 2." hexmask.long.byte 0x4 0.--7. 1. "F_N,Forward field. Contains an event number. When the event occurs then the sequencer state moves from state n to state n+1.For example for TRCSEQEVR1 if F1==0x12 then when event 0x12 occurs the sequencer moves from state 1 to state 2." line.long 0x8 "APBADDR_ETM_CPU2_TRCSEQEVR2,Sequencer State Transition Control Registers 2" hexmask.long.word 0x8 16.--31. 1. "RES0_TRCSEQEVR2_31_16,Reserved RES0." hexmask.long.byte 0x8 8.--15. 1. "B_N,Backward field. Contains an event number. When the event occurs then the sequencer state moves from state n+1 to state n.For example for TRCSEQEVR2 if B2==0x14 then when event 0x14 occurs the sequencer moves from state 3 to state 2." hexmask.long.byte 0x8 0.--7. 1. "F_N,Forward field. Contains an event number. When the event occurs then the sequencer state moves from state n to state n+1.For example for TRCSEQEVR1 if F1==0x12 then when event 0x12 occurs the sequencer moves from state 1 to state 2." group.long 0x118++0xB line.long 0x0 "APBADDR_ETM_CPU2_TRCSEQRSTEVR,Sequencer Reset Control Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_TRCSEQRSTEVR_31_8,Reserved RES0." hexmask.long.byte 0x0 0.--7. 1. "RST,Contains an event number. When the event occurs then the sequencer state moves to state 0." line.long 0x4 "APBADDR_ETM_CPU2_TRCSEQSTR,Sequencer State Register" hexmask.long 0x4 2.--31. 1. "RES0_TRCSEQSTR_31_2,Reserved RES0." bitfld.long 0x4 0.--1. "STATE,Sets or returns the state of the sequencer: 00 State 0. 01 State 1. 10 State 2. 11 State 3." "0,1,2,3" line.long 0x8 "APBADDR_ETM_CPU2_TRCEXTINSELR,External Input Select Register" bitfld.long 0x8 29.--31. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "SEL3,Selects an event from the external input bus for External Input Resource 3." bitfld.long 0x8 21.--23. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 16.--20. 1. "SEL2,Selects an event from the external input bus for External Input Resource 2" bitfld.long 0x8 13.--15. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--12. 1. "SEL1,Selects an event from the external input bus for External Input Resource 1" newline bitfld.long 0x8 5.--7. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--4. 1. "SEL0,Selects an event from the external input bus for External Input Resource 0" group.long 0x140++0x7 line.long 0x0 "APBADDR_ETM_CPU2_TRCCNTRLDVR0,Counter Reload Value Registers 0" hexmask.long.word 0x0 16.--31. 1. "RES0_TRCCNTRLDVR0_31_16,Reserved RES0." hexmask.long.word 0x0 0.--15. 1. "VALUE_N,Contains the reload value for counter . When a reload event occurs for counter then the trace unit copies the VALUE field into counter ." line.long 0x4 "APBADDR_ETM_CPU2_TRCCNTRLDVR1,Counter Reload Value Registers 1" hexmask.long.word 0x4 16.--31. 1. "RES0_TRCCNTRLDVR1_31_16,Reserved RES0." hexmask.long.word 0x4 0.--15. 1. "VALUE_N,Contains the reload value for counter . When a reload event occurs for counter then the trace unit copies the VALUE field into counter ." group.long 0x150++0x7 line.long 0x0 "APBADDR_ETM_CPU2_TRCCNTCTLR0,Counter Control Register 0" hexmask.long.word 0x0 18.--31. 1. "RES0_TRCCNTCTLR0_31_18,Reserved RES0." bitfld.long 0x0 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter decrements when a reload event occurs for counter : 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit.." "0,1" bitfld.long 0x0 16. "RLDSELF_N,Controls whether a reload event occurs for counter when counter reaches zero: 0 The trace unit does not generate a reload event. 1 The trace unit generates a reload event for.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter ." hexmask.long.byte 0x0 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter to decrement." line.long 0x4 "APBADDR_ETM_CPU2_TRCCNTCTLR1,Counter Control Register 1" hexmask.long.word 0x4 18.--31. 1. "RES0_TRCCNTCTLR1_31_18,Reserved RES0." bitfld.long 0x4 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter decrements when a reload event occurs for counter : 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit.." "0,1" bitfld.long 0x4 16. "RLDSELF_N,Controls whether a reload event occurs for counter when counter reaches zero: 0 The trace unit does not generate a reload event. 1 The trace unit generates a reload event for.." "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter ." hexmask.long.byte 0x4 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter to decrement." group.long 0x160++0x7 line.long 0x0 "APBADDR_ETM_CPU2_TRCCNTVR0,Counter Value Registers 0" hexmask.long.word 0x0 16.--31. 1. "RES0_TRCCNTVR0_31_16,Reserved RES0." hexmask.long.word 0x0 0.--15. 1. "VALUE_N,Contains the count value of counter ." line.long 0x4 "APBADDR_ETM_CPU2_TRCCNTVR1,Counter Value Registers 1" hexmask.long.word 0x4 16.--31. 1. "RES0_TRCCNTVR1_31_16,Reserved RES0." hexmask.long.word 0x4 0.--15. 1. "VALUE_N,Contains the count value of counter ." group.long 0x180++0x17 line.long 0x0 "APBADDR_ETM_CPU2_TRCIDR8,ID Register 8" hexmask.long 0x0 0.--31. 1. "MAXSPEC,Indicates the maximum speculation depth of the instruction trace stream. This is the maximum number of P0 elements in the trace stream that can be speculative at any time." line.long 0x4 "APBADDR_ETM_CPU2_TRCIDR9,ID Register 9" hexmask.long 0x4 0.--31. 1. "NUMP0KEY,Indicates the number of P0 right-hand keys that the trace unit can use. A value of 0 or 1 indicates one P0 key." line.long 0x8 "APBADDR_ETM_CPU2_TRCIDR10,ID Register 10" hexmask.long 0x8 0.--31. 1. "NUMP1KEY,Indicates the number of P1 right-hand keys that the trace unit can use. The number includes normal and special keys." line.long 0xC "APBADDR_ETM_CPU2_TRCIDR11,ID Register 11" hexmask.long 0xC 0.--31. 1. "NUMP1SPC,Indicates the number of special P1 right-hand keys that the trace unit can use." line.long 0x10 "APBADDR_ETM_CPU2_TRCIDR12,ID Register 12" hexmask.long 0x10 0.--31. 1. "NUMCONDKEY,Indicates the number of conditional instruction right-hand keys that the trace unit can use. The number includes normal and special keys." line.long 0x14 "APBADDR_ETM_CPU2_TRCIDR13,ID Register 13" hexmask.long 0x14 0.--31. 1. "NUMCONDSPC,Indicates the number of special conditional instruction right-hand keys that the trace unit can use." group.long 0x1C0++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCIMSPEC0,Implementation Specific Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_TRCIMSPEC0_31_8,Reserved RES0." hexmask.long.byte 0x0 4.--7. 1. "EN,If SUPPORT is not 0b0000 controls whether the IMPLEMENTATION DEFINED features are enabled. The permitted values are: 0000 The IMPLEMENTATION DEFINED features are not enabled. The trace unit must behave as if the IMPLEMENTATION.." hexmask.long.byte 0x0 0.--3. 1. "SUPPORT,Indicates whether the implementation supports IMPLEMENTATION DEFINED features. The permitted values are: 0000 No IMPLEMENTATION DEFINED features are supported. The EN field is RES0. and any other value which.." group.long 0x1E0++0x17 line.long 0x0 "APBADDR_ETM_CPU2_TRCIDR0,ID Register 0" bitfld.long 0x0 30.--31. "RES0_TRCIDR0_31_30,Reserved RES0." "0,1,2,3" bitfld.long 0x0 29. "COMMOPT,Conditional instruction tracing support bit. Indicates if the trace unit supports conditional instruction tracing: 0 Conditional instruction tracing is not supported. 1 Conditional.." "0,1" hexmask.long.byte 0x0 24.--28. 1. "TSSIZE,Global timestamp size field. The permitted values are: 00000 Global timestamping is not implemented. 00110 Implementation supports a maximum global timestamp of 48bits." newline hexmask.long.byte 0x0 17.--23. 1. "RES0_TRCIDR0_23_17,Reserved RES0." bitfld.long 0x0 15.--16. "QSUPP,Q element support field. The permitted values are: 00 Q element support is not implemented. TRCCONFIGR.QE is RES0. 01 Q element support is implemented and only supports Q elements with.." "0,1,2,3" bitfld.long 0x0 14. "QFILT,Q element filtering support field. The permitted values are: 0 Q element filtering is not implemented. 1 Q element filtering is implemented. TRCQCTLR is implemented. When.." "0,1" newline bitfld.long 0x0 12.--13. "CONDTYPE,Conditional tracing field. The permitted values are: 00 The trace unit indicates only if a conditional instruction is a pass or fail. 01 The trace unit provides the Current Program Status.." "0,1,2,3" bitfld.long 0x0 10.--11. "NUMEVENT,Number of events field. Indicates how many events the trace unit supports: 00 The trace unit supports 1 event. 01 The trace unit supports 2 events. 10.." "0,1,2,3" bitfld.long 0x0 9. "RETSTACK,Return stack bit. Indicates if the implementation supports a return stack: 0 Return stack is not implemented. 1 Return stack is implemented so TRCCONFIGR.RS is supported." "0,1" newline bitfld.long 0x0 8. "RES0_TRCIDR0_8_8,Reserved RES0." "0,1" bitfld.long 0x0 7. "TRCCCI,Cycle counting instruction bit. Indicates if the trace unit supports cycle counting for instructions: 0 Cycle counting in the instruction trace is not implemented. 1 Cycle counting in the.." "0,1" bitfld.long 0x0 6. "TRCCOND,Conditional instruction tracing support bit. Indicates if the trace unit supports conditional instruction tracing: 0 Conditional instruction tracing is not supported. 1 Conditional.." "0,1" newline bitfld.long 0x0 5. "TRCBB,Branch broadcast tracing support bit. Indicates if the trace unit supports branch broadcast tracing: 0 Branch broadcast tracing is not supported. 1 Branch broadcast tracing is supported so.." "0,1" bitfld.long 0x0 3.--4. "TRCDATA,Conditional tracing field. The permitted values are: 00 Data tracing is not supported. 11 Tracing of data addresses and data values is supported so TRCCONFIGR.DA TRCCONFIGR.DV .." "0,1,2,3" bitfld.long 0x0 1.--2. "INSTP0,P0 tracing support field. The permitted values are: 00 Tracing of load and store instructions as P0 elements is not supported. 11 Tracing of load and store instructions as P0 elements is.." "0,1,2,3" newline bitfld.long 0x0 0. "RES0_TRCIDR0_0_0,Reserved RES0." "0,1" line.long 0x4 "APBADDR_ETM_CPU2_TRCIDR1,ID Register 1" hexmask.long.byte 0x4 24.--31. 1. "DESIGNER,Indicates which company designed the trace unit. The permitted values are: 01000001 ARM Limited. 01000100 Digital Equipment Corporation. 01001101.." hexmask.long.byte 0x4 16.--23. 1. "RES0_TRCIDR1_23_16,Reserved RES0." hexmask.long.byte 0x4 12.--15. 1. "RES1_TRCIDR1_15_12,Reserved RES1." newline hexmask.long.byte 0x4 8.--11. 1. "TRCARCHMAJ,Indicates the major version of the ETM architecture. The permitted value is: 100 ETMv4. All other values are reserved." hexmask.long.byte 0x4 4.--7. 1. "TRCARCHMIN,Indicates the minor version of the ETM architecture. The permitted value is: 0 ETMv4 minor version 0. All other values are reserved." hexmask.long.byte 0x4 0.--3. 1. "REVISION,Returns an IMPLEMENTATION DEFINED value that identifies the revision of the trace registers and the OS Save and Restore registers.ARM recommends:That the initial implementation sets REVISION==0x0 and the field then increments for any subsequent.." line.long 0x8 "APBADDR_ETM_CPU2_TRCIDR2,ID Register 2" bitfld.long 0x8 29.--31. "RES0_TRCIDR2_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 25.--28. 1. "CCSIZE,Indicates the size of the cycle counter in bits minus 12. 0000 The cycle counter is 12 bits in length. 0001 The cycle counter is 13 bits in length. and so on up to 0b1000 .." hexmask.long.byte 0x8 20.--24. 1. "DVSIZE,Indicates the data value size in bytes. The permitted values are: 00000 Data value tracing is not supported. Therefore an implementation must also set TRCIDR0.TRCDATA==0b00. 00100 Maximum.." newline hexmask.long.byte 0x8 15.--19. 1. "DASIZE,Indicates the data address size in bytes. The permitted values are: 00000 Data address tracing is not supported. Therefore an implementation must also set TRCIDR0.TRCDATA==0b00. 00100.." hexmask.long.byte 0x8 10.--14. 1. "VMIDSIZE,Indicates the VMID size. The permitted values are: 00000 VMID tracing is not supported. 00001 Maximum of 8-bit VMID size so TRCCONFIGR.VMID is supported. All other.." hexmask.long.byte 0x8 5.--9. 1. "CIDSIZE,Indicates the Context ID size. The permitted values are: 00000 Context ID tracing is not supported. 00100 Maximum of 32-bit Context ID size so TRCCONFIGR.CID is supported." newline hexmask.long.byte 0x8 0.--4. 1. "IASIZE,Indicates the instruction address size. The permitted values are: 00100 Maximum of 32-bit address size. 01000 Maximum of 64-bit address size. All other values are reserved." line.long 0xC "APBADDR_ETM_CPU2_TRCIDR3,ID Register 3" bitfld.long 0xC 31. "NOOVERFLOW,Indicates if TRCSTALLCTLR.NOOVERFLOW is supported: 0 TRCSTALLCTLR.NOOVERFLOW is not supported or STALLCTL==0. 1 TRCSTALLCTLR.NOOVERFLOW is supported." "0,1" bitfld.long 0xC 28.--30. "NUMPROC,Indicates the number of processors available for tracing. The possible values are: 000 The trace unit can trace one processor. 001 The trace unit can trace two processors." "0,1,2,3,4,5,6,7" bitfld.long 0xC 27. "SYSSTALL,Indicates if the implementation can support stall control: 0 The system does not support stall control of the processor. 1 The system can support stall control of the processor." "0,1" newline bitfld.long 0xC 26. "STALLCTL,Indicates if TRCSTALLCTLR is supported: 0 TRCSTALLCTLR is not supported. 1 TRCSTALLCTLR is supported." "0,1" bitfld.long 0xC 25. "SYNCPR,Indicates if an implementation has a fixed synchronization period: 0 TRCSYNCPR is read-write so software can change the synchronization period. 1 TRCSYNCPR is read-only so the.." "0,1" bitfld.long 0xC 24. "TRCERR,Indicates if TRCVICTLR.TRCERR is supported: 0 TRCVICTLR.TRCERR is not supported 1 TRCVICTLR.TRCERR is supported." "0,1" newline hexmask.long.byte 0xC 20.--23. 1. "EXLEVEL_NS,In Non-secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Non-secure state exception level n is not supported so the corresponding bits in.." hexmask.long.byte 0xC 16.--19. 1. "EXLEVEL_S,In Secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Secure state exception level n is not supported so the corresponding bits in TRCACATRn.EXLEVEL_S and.." hexmask.long.byte 0xC 12.--15. 1. "RES0_TRCIDR3_15_12,Reserved RES0." newline hexmask.long.word 0xC 0.--11. 1. "CCITMIN,Indicates the minimum value that can be programmed in TRCCCCTLR.THRESHOLD.When cycle counting in the instruction trace is supported that is TRCIDR0.TRCCCI==1 then the minimum value of this field is 0x001 otherwise it is 0x000." line.long 0x10 "APBADDR_ETM_CPU2_TRCIDR4,ID Register 4" hexmask.long.byte 0x10 28.--31. 1. "NUMVMIDC,Indicates the number of VMID comparators that are available for tracing. The permitted values are: 0000 No VMID comparators are available. 0001 The implementation has one VMID comparator." hexmask.long.byte 0x10 24.--27. 1. "NUMCIDC,Indicates the number of Context ID comparators that are available for tracing. The permitted values are: 0000 No Context ID comparators are available. 0001 The implementation has one.." hexmask.long.byte 0x10 20.--23. 1. "NUMSSCC,Indicates the number of single-shot comparator controls that are available for tracing. The permitted values are: 0000 No single-shot comparator controls are available. 0001 The.." newline hexmask.long.byte 0x10 16.--19. 1. "NUMRSPAIR,Indicates the number of resource selection pairs that are available for tracing. The permitted values are: 0000 The implementation has one resource selection pair. 0001 The implementation.." hexmask.long.byte 0x10 12.--15. 1. "NUMPC,Indicates the number of processor comparator inputs that are available for tracing. The permitted values are: 0000 No processor comparator inputs are available. 0001 The implementation has.." bitfld.long 0x10 9.--11. "RES0_TRCIDR4_11_9,Reserved RES0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "SUPPDAC,Indicates if the implementation can support data address comparisons: 0 The implementation does not support data address comparisons. 1 The implementation can support data address comparisons" "0,1" hexmask.long.byte 0x10 4.--7. 1. "NUMDVC,Indicates the number of data value comparators that are available for tracing. The permitted values are: 0000 No data value comparators are available. 0001 The implementation has one data.." hexmask.long.byte 0x10 0.--3. 1. "NUMACPAIRS,Indicates the number of address comparator pairs that are available for tracing. The permitted values are: 0000 No address comparator pairs are available. 0001 The implementation has one.." line.long 0x14 "APBADDR_ETM_CPU2_TRCIDR5,ID Register 5" bitfld.long 0x14 31. "REDFUNCNTR,Indicates if the reduced function counter is implemented: 0 The reduced function counter is not supported. 1 Counter 0 is implemented as a reduced function counter." "0,1" bitfld.long 0x14 28.--30. "NUMCNTR,Indicates the number of counters that are available for tracing. The permitted values are: 000 No counters are available. 001 The implementation has one counter." "0,1,2,3,4,5,6,7" bitfld.long 0x14 25.--27. "NUMSEQSTATE,Indicates the number of sequencer states that are implemented. The permitted values are: 000 No sequencer states are implemented. 100 The implementation has four sequencer states." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 24. "RES0_TRCIDR5_24_24,Reserved RES0." "0,1" bitfld.long 0x14 23. "LPOVERRIDE,Indicates if the implementation can support low-power state override: 0 The implementation does not support low-power state override. 1 The implementation supports low-power state.." "0,1" bitfld.long 0x14 22. "ATBTRIG,Indicates if the implementation can support ATB triggers: 0 The implementation does not support ATB triggers. 1 The implementation supports ATB triggers and the TRCEVENTCTL1R.ATBTRIG field.." "0,1" newline hexmask.long.byte 0x14 16.--21. 1. "TRACEIDSIZE,Indicates the trace ID width. The permitted value is: 111 The implementation supports a 7-bit trace ID. This sets the width of the TRCTRACEIDR.TRACEID field. All other values are reserved.The CoreSight ATB.." hexmask.long.byte 0x14 12.--15. 1. "RES0_TRCIDR5_15_12,Reserved RES0." bitfld.long 0x14 9.--11. "NUMEXTINSEL,Indicates how many external input select resources are implemented. The permitted values are: 000 No external input select resources are available. If NUMEXTINSEL is zero NUMEXTIN must also be zero." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 0.--8. 1. "NUMEXTIN,Indicates how many external inputs are implemented. The permitted values are: 000000000 No external inputs are available. If NUMEXTIN is zero NUMEXTINSEL must also be zero. 000000001 The.." group.long 0x208++0x37 line.long 0x0 "APBADDR_ETM_CPU2_TRCRSCTLR2,Resource Selection Control Registers 2" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCRSCTLR2_31_22,Reserved RES0." bitfld.long 0x0 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x0 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x0 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x4 "APBADDR_ETM_CPU2_TRCRSCTLR3,Resource Selection Control Registers 3" hexmask.long.word 0x4 22.--31. 1. "RES0_TRCRSCTLR3_31_22,Reserved RES0." bitfld.long 0x4 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x4 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x4 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x4 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x8 "APBADDR_ETM_CPU2_TRCRSCTLR4,Resource Selection Control Registers 4" hexmask.long.word 0x8 22.--31. 1. "RES0_TRCRSCTLR4_31_22,Reserved RES0." bitfld.long 0x8 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x8 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x8 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0xC "APBADDR_ETM_CPU2_TRCRSCTLR5,Resource Selection Control Registers 5" hexmask.long.word 0xC 22.--31. 1. "RES0_TRCRSCTLR5_31_22,Reserved RES0." bitfld.long 0xC 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0xC 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0xC 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0xC 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x10 "APBADDR_ETM_CPU2_TRCRSCTLR6,Resource Selection Control Registers 6" hexmask.long.word 0x10 22.--31. 1. "RES0_TRCRSCTLR6_31_22,Reserved RES0." bitfld.long 0x10 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x10 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x10 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x14 "APBADDR_ETM_CPU2_TRCRSCTLR7,Resource Selection Control Registers 7" hexmask.long.word 0x14 22.--31. 1. "RES0_TRCRSCTLR7_31_22,Reserved RES0." bitfld.long 0x14 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x14 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x14 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x14 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x18 "APBADDR_ETM_CPU2_TRCRSCTLR8,Resource Selection Control Registers 8" hexmask.long.word 0x18 22.--31. 1. "RES0_TRCRSCTLR8_31_22,Reserved RES0." bitfld.long 0x18 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x18 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x18 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x18 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x1C "APBADDR_ETM_CPU2_TRCRSCTLR9,Resource Selection Control Registers 9" hexmask.long.word 0x1C 22.--31. 1. "RES0_TRCRSCTLR9_31_22,Reserved RES0." bitfld.long 0x1C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x1C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x1C 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x1C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x20 "APBADDR_ETM_CPU2_TRCRSCTLR10,Resource Selection Control Registers 10" hexmask.long.word 0x20 22.--31. 1. "RES0_TRCRSCTLR10_31_22,Reserved RES0." bitfld.long 0x20 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x20 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x20 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x20 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x24 "APBADDR_ETM_CPU2_TRCRSCTLR11,Resource Selection Control Registers 11" hexmask.long.word 0x24 22.--31. 1. "RES0_TRCRSCTLR11_31_22,Reserved RES0." bitfld.long 0x24 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x24 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x24 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x24 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x28 "APBADDR_ETM_CPU2_TRCRSCTLR12,Resource Selection Control Registers 12" hexmask.long.word 0x28 22.--31. 1. "RES0_TRCRSCTLR12_31_22,Reserved RES0." bitfld.long 0x28 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x28 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x28 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x28 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x2C "APBADDR_ETM_CPU2_TRCRSCTLR13,Resource Selection Control Registers 13" hexmask.long.word 0x2C 22.--31. 1. "RES0_TRCRSCTLR13_31_22,Reserved RES0." bitfld.long 0x2C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x2C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x2C 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x2C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x30 "APBADDR_ETM_CPU2_TRCRSCTLR14,Resource Selection Control Registers 14" hexmask.long.word 0x30 22.--31. 1. "RES0_TRCRSCTLR14_31_22,Reserved RES0." bitfld.long 0x30 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x30 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x30 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x30 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x34 "APBADDR_ETM_CPU2_TRCRSCTLR15,Resource Selection Control Registers 15" hexmask.long.word 0x34 22.--31. 1. "RES0_TRCRSCTLR15_31_22,Reserved RES0." bitfld.long 0x34 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x34 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x34 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x34 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." group.long 0x280++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCSSCCR0,Single-Shot Comparator Control Register 0" hexmask.long.byte 0x0 25.--31. 1. "RES0_TRCSSCCR0_31_25,Reserved RES0." bitfld.long 0x0 24. "RST,Controls whether the single-shot comparator resource is reset when it fires. 0 When the single-shot comparator resource fires it is not reset. 1 When the single-shot comparator resource fires .." "0,1" hexmask.long.byte 0x0 16.--23. 1. "ARC,Selects one or more address range comparators for single-shot control.Each bit represents an address range comparator pair so bit[n-16] controls the selection of address range comparator pair n-16. If bit[n-16] is: 0 The address.." newline hexmask.long.word 0x0 0.--15. 1. "SAC,Selects one or more single address comparators for single-shot control.Each bit represents a single address comparator so bit[n] controls the selection of single address comparator n. If bit[n] is: 0 The single address comparator.." group.long 0x2A0++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCSSCSR0,Single-Shot Comparator Status Register 0" bitfld.long 0x0 31. "STATUS,Single-shot status bit. Indicates if any of the comparators that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects have matched: 0 No match has occurred. 1 One or more matches has occurred. If.." "0,1" hexmask.long 0x0 3.--30. 1. "RES0_TRCSSCSR0_30_3,Reserved RES0." bitfld.long 0x0 2. "DV,Data value comparator support bit. Indicates if the trace unit supports data address with data value comparisons: 0 Single-shot data address with data value comparisons are not supported. 1.." "0,1" newline bitfld.long 0x0 1. "DA,Data address comparator support bit. Indicates if the trace unit supports data address comparisons: 0 Single-shot data address comparisons are not supported. 1 Single-shot data address.." "0,1" bitfld.long 0x0 0. "INST,Instruction address comparator support bit. Indicates if the trace unit supports instruction address comparisons: 0 Single-shot instruction address comparisons are not supported. 1 Single-shot.." "0,1" group.long 0x300++0x7 line.long 0x0 "APBADDR_ETM_CPU2_TRCOSLAR,OS Lock Access Register" hexmask.long 0x0 1.--31. 1. "RES0_TRCOSLAR_31_1,Reserved RES0." bitfld.long 0x0 0. "LOCK,OS Lock control bit: 0 Unlocks the OS Lock. 1 Locks the OS Lock. This setting disables the trace unit." "0,1" line.long 0x4 "APBADDR_ETM_CPU2_TRCOSLSR,OS Lock Status Register" hexmask.long 0x4 4.--31. 1. "RES0_TRCOSLSR_31_4,Reserved RES0." bitfld.long 0x4 3. "PRESENT,Indicates whether the OS Lock is implemented.This bit is RES1 which indicates that the OS Lock is always implemented." "0,1" bitfld.long 0x4 2. "BIT32,This bit is RES0 which indicates that software must perform a 32-bit write to update the TRCOSLAR." "0,1" newline bitfld.long 0x4 1. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked. 1 The OS Lock is locked. When the trace unit core power domain is powered down the value is UNKNOWN. The TRCPDSR indicates if.." "0,1" bitfld.long 0x4 0. "RES0_TRCOSLSR_0_0,Reserved RES0." "0,1" group.long 0x310++0x7 line.long 0x0 "APBADDR_ETM_CPU2_TRCPDCR,Power Down Control Register" hexmask.long 0x0 4.--31. 1. "RES0_TRCPDCR_31_4,Reserved RES0." bitfld.long 0x0 3. "PU,Powerup request bit: 0 The system can remove power from the trace unit. The TRCPDSR indicates if the trace unit is powered down. 1 The system must provide power to the trace unit." "0,1" bitfld.long 0x0 0.--2. "RES0_TRCPDCR_2_0,Reserved RES0." "0,1,2,3,4,5,6,7" line.long 0x4 "APBADDR_ETM_CPU2_TRCPDSR,Power Down Status Register" hexmask.long 0x4 6.--31. 1. "RES0_TRCPDSR_31_6,Reserved RES0." bitfld.long 0x4 5. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked. 1 The OS Lock is locked. The value is UNKNOWN when the trace unit core power domain is powered down that is when POWER==0." "0,1" bitfld.long 0x4 2.--4. "RES0_TRCPDSR_4_2,Reserved RES0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 1. "STICKYPD,Sticky powerdown status bit. Indicates whether the trace register state is valid: 0 If POWER==1 then the state of TRCOSLSR and the trace registers are valid. If POWER==0 then it is UNKNOWN whether the state of TRCOSLSR and the.." "0,1" bitfld.long 0x4 0. "POWER,Power status bit: 0 The trace unit core power domain is not powered. The trace registers are not accessible and they all return an error response. 1 The trace unit core power domain is.." "0,1" group.long 0x400++0x3F line.long 0x0 "APBADDR_ETM_CPU2_TRCACVR0_31_0,Address Comparator Value Registers 0 (low word)" hexmask.long 0x0 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x4 "APBADDR_ETM_CPU2_TRCACVR0_63_32,Address Comparator Value Registers 0 (high word)" hexmask.long 0x4 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x8 "APBADDR_ETM_CPU2_TRCACVR1_31_0,Address Comparator Value Registers 1 (low word)" hexmask.long 0x8 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0xC "APBADDR_ETM_CPU2_TRCACVR1_63_32,Address Comparator Value Registers 1 (high word)" hexmask.long 0xC 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x10 "APBADDR_ETM_CPU2_TRCACVR2_31_0,Address Comparator Value Registers 2 (low word)" hexmask.long 0x10 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x14 "APBADDR_ETM_CPU2_TRCACVR2_63_32,Address Comparator Value Registers 2 (high word)" hexmask.long 0x14 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x18 "APBADDR_ETM_CPU2_TRCACVR3_31_0,Address Comparator Value Registers 3 (low word)" hexmask.long 0x18 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x1C "APBADDR_ETM_CPU2_TRCACVR3_63_32,Address Comparator Value Registers 3 (high word)" hexmask.long 0x1C 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x20 "APBADDR_ETM_CPU2_TRCACVR4_31_0,Address Comparator Value Registers 4 (low word)" hexmask.long 0x20 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x24 "APBADDR_ETM_CPU2_TRCACVR4_63_32,Address Comparator Value Registers 4 (high word)" hexmask.long 0x24 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x28 "APBADDR_ETM_CPU2_TRCACVR5_31_0,Address Comparator Value Registers 5 (low word)" hexmask.long 0x28 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x2C "APBADDR_ETM_CPU2_TRCACVR5_63_32,Address Comparator Value Registers 5 (high word)" hexmask.long 0x2C 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x30 "APBADDR_ETM_CPU2_TRCACVR6_31_0,Address Comparator Value Registers 6 (low word)" hexmask.long 0x30 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x34 "APBADDR_ETM_CPU2_TRCACVR6_63_32,Address Comparator Value Registers 6 (high word)" hexmask.long 0x34 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x38 "APBADDR_ETM_CPU2_TRCACVR7_31_0,Address Comparator Value Registers 7 (low word)" hexmask.long 0x38 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x3C "APBADDR_ETM_CPU2_TRCACVR7_63_32,Address Comparator Value Registers 7 (high word)" hexmask.long 0x3C 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." group.long 0x480++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCACATR0,Address Comparator Access Type Registers 0" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR0_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR0_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x488++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCACATR1,Address Comparator Access Type Registers 1" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR1_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR1_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x490++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCACATR2,Address Comparator Access Type Registers 2" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR2_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR2_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x498++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCACATR3,Address Comparator Access Type Registers 3" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR3_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR3_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4A0++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCACATR4,Address Comparator Access Type Registers 4" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR4_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR4_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4A8++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCACATR5,Address Comparator Access Type Registers 5" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR5_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR5_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4B0++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCACATR6,Address Comparator Access Type Registers 6" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR6_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR6_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4B8++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCACATR7,Address Comparator Access Type Registers 7" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR7_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR7_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x600++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCCIDCVR0,Context ID Comparator Value Register 0" hexmask.long 0x0 0.--31. 1. "VALUE,Context ID value. The implemented width of this field is IMPLEMENTATION DEFINED and is set by TRCIDR2.CIDSIZE. Unimplemented bits are RAZ/WI.After a processor reset the ETM architecture assumes that the Context ID is zero until the processor.." group.long 0x640++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCVMIDCVR0,VMID Comparator Value Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--7. 1. "VALUE,Contains a VMID value." group.long 0x680++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCCIDCCTLR0,Context ID Comparator Control Register 0" hexmask.long 0x0 0.--31. 1. "COMP_N,Controls the mask value that the trace unit applies to TRCCIDCVRn. Each bit in this field corresponds to a byte in TRCCIDCVRn. When a bit is: 0 The trace unit includes the relevant byte in TRCCIDCVRn when it performs the Context.." group.long 0xEE4++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCITATBIDR,Integration ATB Identification Register" hexmask.long 0x0 7.--31. 1. "RES0_TRCITATBIDR_31_7,Reserved RES0" hexmask.long.byte 0x0 0.--6. 1. "ID,Drives the ATIDMn[6:0] output pins" group.long 0xEEC++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCITIDATAR,Integration Instruction ATB Data Register" hexmask.long 0x0 5.--31. 1. "RES0_TRCITIDATAR_31_5,Reserved RES0" bitfld.long 0x0 4. "ATDATAM_31,Drives the ATDATAM[31] output" "0,1" bitfld.long 0x0 3. "ATDATAM_23,Drives the ATDATAM[23] output" "0,1" newline bitfld.long 0x0 2. "ATDATAM_15,Drives the ATDATAM[15] output" "0,1" bitfld.long 0x0 1. "ATDATAM_7,Drives the ATDATAM[7] output" "0,1" bitfld.long 0x0 0. "ATDATAM_0,Drives the ATDATAM[0] output" "0,1" group.long 0xEF4++0x3 line.long 0x0 "APBADDR_ETM_CPU2_TRCITIATBINR,Integration Instruction ATB In Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved. Read undefined." bitfld.long 0x0 1. "AFVALIDM,Returns the value of the AFVALIDMn input pin" "0,1" bitfld.long 0x0 0. "ATREADYM,Returns the value of the ATREADYMn input pin" "0,1" group.long 0xEFC++0x7 line.long 0x0 "APBADDR_ETM_CPU2_TRCITIATBOUTR,Integration Instruction ATB Out Register" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved. Read undefined." bitfld.long 0x0 8.--9. "BYTES,Drives the ATBYTESMn[1:0] output pins" "0,1,2,3" hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved. Read undefined." newline bitfld.long 0x0 1. "AFREADY,Drives the AFREADYMn output pin" "0,1" bitfld.long 0x0 0. "ATVALID,Drives the ATVALIDMn output pin" "0,1" line.long 0x4 "APBADDR_ETM_CPU2_TRCITCTRL,Integration Mode Control Register" hexmask.long 0x4 1.--31. 1. "RES0_TRCITCTRL_31_1,Reserved RES0." bitfld.long 0x4 0. "ITEN,Integration mode enable bit: 0 The trace unit is not in integration mode. 1 The trace unit is in integration mode. This mode enables a debug agent to perform topology detection and.." "0,1" group.long 0xFA0++0x1F line.long 0x0 "APBADDR_ETM_CPU2_TRCCLAIMSET,Claim Tag Set Register" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--3. 1. "SET,Sets bits in the claim tag and determines the number of claim tag bits implemented." line.long 0x4 "APBADDR_ETM_CPU2_TRCCLAIMCLR,Claim Tag Clear Register" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "CLR,Clears bits in the claim tag and determines the current value of the claim tag." line.long 0x8 "APBADDR_ETM_CPU2_TRCDEVAFF0,Device Affinity Register 0" hexmask.long 0x8 0.--31. 1. "MPIDR_EL1_31_0,Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0xC "APBADDR_ETM_CPU2_TRCDEVAFF1,Device Affinity Register 1" hexmask.long 0xC 0.--31. 1. "MPIDR_EL1_63_32,Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x10 "APBADDR_ETM_CPU2_TRCLAR,Software Lock Access Register" hexmask.long 0x10 0.--31. 1. "KEY,Writing the key value 0xC5ACCE55 to this field clears the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register sets the lock disabling write accesses to this.." line.long 0x14 "APBADDR_ETM_CPU2_TRCLSR,Software Lock Status Register" hexmask.long 0x14 3.--31. 1. "RES0_TRCLSR_31_3,Reserved RES0." bitfld.long 0x14 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" bitfld.long 0x14 1. "SLK,Software lock status for this component. Possible values of this field are: 0 Lock clear. Writes are permitted to this component's registers. 1 Lock set. Writes to this component's registers.." "0,1" newline bitfld.long 0x14 0. "SLI,Software lock implemented. RAO." "0,1" line.long 0x18 "APBADDR_ETM_CPU2_TRCAUTHSTATUS,Authentication Status Register" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCAUTHSTATUS_31_8,Reserved RES0." bitfld.long 0x18 6.--7. "SNID,Indicates whether the system enables the trace unit to support Secure non-invasive debug: 00 The trace unit does not implement support for Secure non-invasive debug. 01 Reserved." "0,1,2,3" bitfld.long 0x18 4.--5. "SID,Indicates whether the trace unit supports Secure invasive debug: 00 The trace unit does not support Secure invasive debug. All other values are reserved." "0,1,2,3" newline bitfld.long 0x18 2.--3. "NSNID,Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: 00 The trace unit does not implement support for Non-secure non-invasive debug. 01 Reserved." "0,1,2,3" bitfld.long 0x18 0.--1. "NSID,Indicates whether the trace unit supports Non-secure invasive debug: 00 The trace unit does not support Non-secure invasive debug. All other values are reserved." "0,1,2,3" line.long 0x1C "APBADDR_ETM_CPU2_TRCDEVARCH,Device Architecture Register" hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For trace this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is RAO." "0,1" hexmask.long.byte 0x1C 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For trace the revision defined by ETMv4 is 0x0.All other values are reserved." newline hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For trace bits [15:12] are the architecture version 0x4; bits [11:0] are the architecture part number 0xA13.This corresponds to trace.." group.long 0xFC8++0x37 line.long 0x0 "APBADDR_ETM_CPU2_TRCDEVID,Device ID Register" hexmask.long 0x0 0.--31. 1. "DEVID,Indicates the capabilities of the trace unit. The implemented width of this field and its bit assignments are IMPLEMENTATION DEFINED. Unimplemented bits are RAZ/WI.If a component is configurable then ARM recommends that this field can also indicate.." line.long 0x4 "APBADDR_ETM_CPU2_TRCDEVTYPE,Device Type Register" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_TRCDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x4 4.--7. 1. "SUB,Returns 0x1 to indicate that the ETM generates processor trace.All other values are reserved." hexmask.long.byte 0x4 0.--3. 1. "MAIN,Returns 0x3 to indicate that the ETM is a trace source.All other values are reserved." line.long 0x8 "APBADDR_ETM_CPU2_TRCPIDR4,Peripheral Identification Register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RES0_TRCPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x8 4.--7. 1. "SIZE,Size of the component. RES0. This indicates that the ETM memory map occupies 4KB." hexmask.long.byte 0x8 0.--3. 1. "DES_2,Designer JEP106 continuation code. For ARM Limited this field is 0b0100." line.long 0xC "APBADDR_ETM_CPU2_TRCPIDR5,Peripheral Identification Register 5" hexmask.long.tbyte 0xC 8.--31. 1. "RES0_TRCPIDR5_31_8,Reserved RES0." hexmask.long.byte 0xC 0.--7. 1. "RESERVED,RES0 reserved for future use." line.long 0x10 "APBADDR_ETM_CPU2_TRCPIDR6,Peripheral Identification Register 6" hexmask.long.tbyte 0x10 8.--31. 1. "RES0_TRCPIDR6_31_8,Reserved RES0." hexmask.long.byte 0x10 0.--7. 1. "RESERVED,RES0 reserved for future use." line.long 0x14 "APBADDR_ETM_CPU2_TRCPIDR7,Peripheral Identification Register 7" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_TRCPIDR7_31_8,Reserved RES0." hexmask.long.byte 0x14 0.--7. 1. "RESERVED,RES0 reserved for future use." line.long 0x18 "APBADDR_ETM_CPU2_TRCPIDR0,Peripheral Identification Register 0" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x18 0.--7. 1. "PART_0,Part number bits[7:0]." line.long 0x1C "APBADDR_ETM_CPU2_TRCPIDR1,Peripheral Identification Register 1" hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_TRCPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x1C 4.--7. 1. "DES_0,Designer bits[3:0] of JEP106 ID code. For ARM Limited this field is 0b1011." hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part number bits[11:8]." line.long 0x20 "APBADDR_ETM_CPU2_TRCPIDR2,Peripheral Identification Register 2" hexmask.long.tbyte 0x20 8.--31. 1. "RES0_TRCPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x20 4.--7. 1. "REVISION,The IMPLEMENTATION DEFINED revision number for the ETM implementation. See also TRCIDR1.REVISION." bitfld.long 0x20 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" newline bitfld.long 0x20 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0x24 "APBADDR_ETM_CPU2_TRCPIDR3,Peripheral Identification Register 3" hexmask.long.tbyte 0x24 8.--31. 1. "RES0_TRCPIDR3_31_8,Reserved RES0." hexmask.long.byte 0x24 4.--7. 1. "REVAND,The IMPLEMENTATION DEFINED manufacturing revision number for the implementation. After silicon is available if metal fixes are necessary the manufacturer can alter the top metal layer so that this field can indicate any post-fab silicon changes." hexmask.long.byte 0x24 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x28 "APBADDR_ETM_CPU2_TRCCIDR0,Component Identification Register 0" hexmask.long.tbyte 0x28 8.--31. 1. "RES0_TRCCIDR0_31_8,Reserved RES0." hexmask.long.byte 0x28 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x2C "APBADDR_ETM_CPU2_TRCCIDR1,Component Identification Register 1" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_TRCCIDR1_31_8,Reserved RES0." hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Component class. Reads as 0x9 to indicate that the ETM is a debug component with CoreSight architecture compliant management registers." hexmask.long.byte 0x2C 0.--3. 1. "PRMBL_1,Preamble. Must read as 0x0." line.long 0x30 "APBADDR_ETM_CPU2_TRCCIDR2,Component Identification Register 2" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_TRCCIDR2_31_8,Reserved RES0." hexmask.long.byte 0x30 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x34 "APBADDR_ETM_CPU2_TRCCIDR3,Component Identification Register 3" hexmask.long.tbyte 0x34 8.--31. 1. "RES0_TRCCIDR3_31_8,Reserved RES0." hexmask.long.byte 0x34 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree "A53SS0_CORE2_PMU" base ad:0x730220000 group.long 0x0++0x3 line.long 0x0 "APBADDR_PMU_CPU2_PMEVCNTR0_EL0,Performance Monitors Event Count Register 0" hexmask.long 0x0 0.--31. 1. "PMEVCNTR0_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x8++0x3 line.long 0x0 "APBADDR_PMU_CPU2_PMEVCNTR1_EL0,Performance Monitors Event Count Register 1" hexmask.long 0x0 0.--31. 1. "PMEVCNTR1_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x10++0x3 line.long 0x0 "APBADDR_PMU_CPU2_PMEVCNTR2_EL0,Performance Monitors Event Count Register 2" hexmask.long 0x0 0.--31. 1. "PMEVCNTR2_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x18++0x3 line.long 0x0 "APBADDR_PMU_CPU2_PMEVCNTR3_EL0,Performance Monitors Event Count Register 3" hexmask.long 0x0 0.--31. 1. "PMEVCNTR3_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x20++0x3 line.long 0x0 "APBADDR_PMU_CPU2_PMEVCNTR4_EL0,Performance Monitors Event Count Register 4" hexmask.long 0x0 0.--31. 1. "PMEVCNTR4_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x28++0x3 line.long 0x0 "APBADDR_PMU_CPU2_PMEVCNTR5_EL0,Performance Monitors Event Count Register 5" hexmask.long 0x0 0.--31. 1. "PMEVCNTR5_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0xF8++0x7 line.long 0x0 "APBADDR_PMU_CPU2_PMCCNTR_EL0_31_0,Performance Monitors Cycle Counter (low word)" hexmask.long 0x0 0.--31. 1. "CCNT,Cycle count. Depending on the values of PMCR_EL0.{LC D} the cycle count increments in one of the following ways:Every processor clock cycle.Every 64th processor clock cycle.The cycle count can be reset to zero by writing 1 to PMCR_EL0.C." line.long 0x4 "APBADDR_PMU_CPU2_PMCCNTR_EL0_63_32,Performance Monitors Cycle Counter (high word)" hexmask.long 0x4 0.--31. 1. "CCNT,Cycle count. Depending on the values of PMCR_EL0.{LC D} the cycle count increments in one of the following ways:Every processor clock cycle.Every 64th processor clock cycle.The cycle count can be reset to zero by writing 1 to PMCR_EL0.C." group.long 0x400++0x17 line.long 0x0 "APBADDR_PMU_CPU2_PMEVTYPER0_EL0,Performance Monitors Event Type Register 0" bitfld.long 0x0 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x0 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x0 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x0 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x0 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x0 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x0 10.--25. 1. "RES0_PMEVTYPER0_EL0_25_10,Reserved RES0." hexmask.long.word 0x0 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x4 "APBADDR_PMU_CPU2_PMEVTYPER1_EL0,Performance Monitors Event Type Register 1" bitfld.long 0x4 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x4 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x4 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x4 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x4 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x4 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x4 10.--25. 1. "RES0_PMEVTYPER1_EL0_25_10,Reserved RES0." hexmask.long.word 0x4 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x8 "APBADDR_PMU_CPU2_PMEVTYPER2_EL0,Performance Monitors Event Type Register 2" bitfld.long 0x8 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x8 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x8 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x8 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x8 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x8 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x8 10.--25. 1. "RES0_PMEVTYPER2_EL0_25_10,Reserved RES0." hexmask.long.word 0x8 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0xC "APBADDR_PMU_CPU2_PMEVTYPER3_EL0,Performance Monitors Event Type Register 3" bitfld.long 0xC 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0xC 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0xC 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0xC 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0xC 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0xC 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0xC 10.--25. 1. "RES0_PMEVTYPER3_EL0_25_10,Reserved RES0." hexmask.long.word 0xC 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x10 "APBADDR_PMU_CPU2_PMEVTYPER4_EL0,Performance Monitors Event Type Register 4" bitfld.long 0x10 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x10 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x10 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x10 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x10 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x10 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x10 10.--25. 1. "RES0_PMEVTYPER4_EL0_25_10,Reserved RES0." hexmask.long.word 0x10 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x14 "APBADDR_PMU_CPU2_PMEVTYPER5_EL0,Performance Monitors Event Type Register 5" bitfld.long 0x14 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x14 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x14 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x14 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x14 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x14 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x14 10.--25. 1. "RES0_PMEVTYPER5_EL0_25_10,Reserved RES0." hexmask.long.word 0x14 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." group.long 0x47C++0x3 line.long 0x0 "APBADDR_PMU_CPU2_PMCCFILTR_EL0,Performance Monitors Cycle Counter Filter Register" bitfld.long 0x0 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count cycles in EL1. 1.." "0,1" bitfld.long 0x0 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count cycles in EL0. 1.." "0,1" newline bitfld.long 0x0 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P cycles in Non-secure EL1 are counted.Otherwise cycles in Non-secure EL1 are.." "0,1" bitfld.long 0x0 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U cycles in Non-secure EL0 are counted.Otherwise cycles in Non-secure EL0 are.." "0,1" newline bitfld.long 0x0 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count cycles in EL2. 1 Count cycles in EL2." "0,1" bitfld.long 0x0 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P cycles in Secure EL3 are counted.Otherwise cycles in Secure EL3.." "0,1" newline hexmask.long 0x0 0.--25. 1. "RES0_PMCCFILTR_EL0_25_0,Reserved RES0." group.long 0xC00++0x3 line.long 0x0 "APBADDR_PMU_CPU2_PMCNTENSET_EL0,Performance Monitors Count Enable Set Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 enable bit. Enables the cycle counter register. Possible values are: 0 When read means the cycle counter is disabled. When written has no effect. 1 When read means the cycle.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter enable bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: 0 When read means that PMEVCNTR is disabled. When written has no effect. 1.." group.long 0xC20++0x3 line.long 0x0 "APBADDR_PMU_CPU2_PMCNTENCLR_EL0,Performance Monitors Count Enable Clear Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 disable bit. Disables the cycle counter register. Possible values are: 0 When read means the cycle counter is disabled. When written has no effect. 1 When read means the cycle.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter disable bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: 0 When read means that PMEVCNTR is disabled. When written has no effect." group.long 0xC40++0x3 line.long 0x0 "APBADDR_PMU_CPU2_PMINTENSET_EL1,Performance Monitors Interrupt Enable Set Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow interrupt request enable bit. Possible values are: 0 When read means the cycle counter overflow interrupt request is disabled. When written has no effect. 1 When read .." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow interrupt request enable bit for PMEVCNTR_EL0.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: 0 When read means that the PMEVCNTR_EL0 event counter interrupt request is.." group.long 0xC60++0x3 line.long 0x0 "APBADDR_PMU_CPU2_PMINTENCLR_EL1,Performance Monitors Interrupt Enable Clear Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow interrupt request disable bit. Possible values are: 0 When read means the cycle counter overflow interrupt request is disabled. When written has no effect. 1 When read .." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow interrupt request disable bit for PMEVCNTR_EL0.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: 0 When read means that the PMEVCNTR_EL0 event counter interrupt request is.." group.long 0xC80++0x3 line.long 0x0 "APBADDR_PMU_CPU2_PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow bit. Possible values are: 0 When read means the cycle counter has not overflowed. When written has no effect. 1 When read means the cycle counter has overflowed. When.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow clear bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: 0 When read means that PMEVCNTR has not overflowed. When written has no effect." group.long 0xCA0++0x3 line.long 0x0 "APBADDR_PMU_CPU2_PMSWINC_EL0,Performance Monitors Software Increment Register" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--5. 1. "P_X,Event counter software increment bit for PMEVCNTR" group.long 0xCC0++0x3 line.long 0x0 "APBADDR_PMU_CPU2_PMOVSSET_EL0,Performance Monitors Overflow Flag Status Set Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow bit. Possible values are: 0 When read means the cycle counter has not overflowed. When written has no effect. 1 When read means the cycle counter has overflowed. When.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow set bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: 0 When read means that PMEVCNTR has not overflowed. When written has no effect." group.long 0xE00++0x7 line.long 0x0 "APBADDR_PMU_CPU2_PMCFGR,Performance Monitors Configuration Register" hexmask.long.word 0x0 20.--31. 1. "RES0_PMCFGR_31_20,Reserved RES0." bitfld.long 0x0 19. "UEN,User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface so this bit is RES0." "0,1" newline bitfld.long 0x0 18. "WT,This feature is not supported so this bit is RES0." "0,1" bitfld.long 0x0 17. "NA,This feature is not supported so this bit is RES0." "0,1" newline bitfld.long 0x0 16. "EX,Export supported. Value is IMPLEMENTATION DEFINED. 0 PMCR_EL0.X is RES0. 1 PMCR_EL0.X is read/write." "0,1" bitfld.long 0x0 15. "CCD,Cycle counter has prescale. This is RES1 if AArch32 is supported at any EL and RES0 otherwise. 0 PMCR_EL0.D is RES0. 1 PMCR_EL0.D is read/write." "0,1" newline bitfld.long 0x0 14. "CC,Dedicated cycle counter [counter 31] supported. This bit is RES1." "0,1" hexmask.long.byte 0x0 8.--13. 1. "SIZE,Size of counters. This field determines the spacing of counters in the memory-map.In v8-A the counters are at doubleword-aligned addresses and the largest counter is 64-bits so this field is 0b111111." newline hexmask.long.byte 0x0 0.--7. 1. "N,Number of counters implemented in addition to the cycle counter PMCCNTR_EL0. The maximum number of event counters is 31 so bits[7:5] are always RES0. 00000000 Only PMCCNTR_EL0 implemented. 00000001.." line.long 0x4 "APBADDR_PMU_CPU2_PMCR_EL0,Performance Monitors Control Register" hexmask.long.tbyte 0x4 11.--31. 1. "RES0_PMCR_EL0_31_11,Reserved RAZ/WI." hexmask.long.byte 0x4 7.--10. 1. "RES0_PMCR_EL0_10_7,Reserved RES0." newline bitfld.long 0x4 6. "LC,Long cycle counter enable. Determines which PMCCNTR_EL0 bit generates an overflow recorded by PMOVSR[31]. 0 Cycle counter overflow on increment that changes PMCCNTR_EL0[31] from 1 to 0. 1 Cycle.." "0,1" bitfld.long 0x4 5. "DP,Disable cycle counter when event counting is prohibited. The possible values of this bit are: 0 PMCCNTR_EL0 if enabled counts when event counting is prohibited. 1 PMCCNTR_EL0 does not count.." "0,1" newline bitfld.long 0x4 4. "X,Enable export of events in an IMPLEMENTATION DEFINED event stream. The possible values of this bit are: 0 Do not export events. 1 Export events where not prohibited. This bit is.." "0,1" bitfld.long 0x4 3. "D,Clock divider. The possible values of this bit are: 0 When enabled PMCCNTR_EL0 counts every clock cycle. 1 When enabled PMCCNTR_EL0 counts once every 64 clock cycles. This bit.." "0,1" newline bitfld.long 0x4 2. "C,Cycle counter reset. This bit is WO. The effects of writing to this bit are: 0 No action. 1 Reset PMCCNTR_EL0 to zero. This bit is always RAZ.Resetting PMCCNTR_EL0 does not.." "0,1" bitfld.long 0x4 1. "P,Event counter reset. This bit is WO. The effects of writing to this bit are: 0 No action. 1 Reset all event counters not including PMCCNTR_EL0 to zero. This bit is always.." "0,1" newline bitfld.long 0x4 0. "E,Enable. The possible values of this bit are: 0 All counters including PMCCNTR_EL0 are disabled. 1 All counters are enabled by PMCNTENSET_EL0. This bit is RW." "0,1" group.long 0xE20++0x7 line.long 0x0 "APBADDR_PMU_CPU2_PMCEID0_EL0,Performance Monitors Common Event Identification Register 0" hexmask.long 0x0 0.--31. 1. "CE_31_0,Common architectural and microarchitectural feature events that can be counted by the PMU event counters.For each bit described in the following table the event is implemented if the bit is set to 1 or not implemented if the bit is set to.." line.long 0x4 "APBADDR_PMU_CPU2_PMCEID1_EL0,Performance Monitors Common Event Identification Register 1" hexmask.long 0x4 1.--31. 1. "RES0_PMCEID1_EL0_31_1,Reserved RES0." bitfld.long 0x4 0. "CE_32,Common architectural and microarchitectural feature events that can be counted by the PMU event counters.For the bit described in the following table the event is implemented if the bit is set to 1 or not implemented if the bit is set to.." "0,1" group.long 0xF00++0x3 line.long 0x0 "APBADDR_PMU_CPU2_PMITCTRL,Performance Monitors Integration mode Control Register" hexmask.long 0x0 1.--31. 1. "RES0_PMITCTRL_31_1,Reserved RES0." bitfld.long 0x0 0. "IME,Integration mode enable. When IME == 1 the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED. 0 Normal operation." "0,1" group.long 0xFA8++0x17 line.long 0x0 "APBADDR_PMU_CPU2_PMDEVAFF0,Performance Monitors Device Affinity Register 0" hexmask.long 0x0 0.--31. 1. "PMDEVAFF0,MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x4 "APBADDR_PMU_CPU2_PMDEVAFF1,Performance Monitors Device Affinity Register 1" hexmask.long 0x4 0.--31. 1. "PMDEVAFF1,MPIDR_EL1 high half. Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x8 "APBADDR_PMU_CPU2_PMLAR,Performance Monitors Lock Access Register" hexmask.long 0x8 0.--31. 1. "KEY,Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register locks the lock disabling write.." line.long 0xC "APBADDR_PMU_CPU2_PMLSR,Performance Monitors Lock Status Register" hexmask.long 0xC 3.--31. 1. "RES0_PMLSR_31_3,Reserved RES0." bitfld.long 0xC 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" newline bitfld.long 0xC 1. "SLK,Software lock status for this component. For an access to LSR that is not a memory-mapped access or when the software lock is not implemented this field is RES0.For memory-mapped accesses when the software lock is implemented possible values of.." "0,1" bitfld.long 0xC 0. "SLI,Software lock implemented. For an access to LSR that is not a memory-mapped access this field is RAZ. For memory-mapped accesses the value of this field is IMPLEMENTATION DEFINED. Permitted values are: 0 Software lock not.." "0,1" line.long 0x10 "APBADDR_PMU_CPU2_PMAUTHSTATUS,Performance Monitors Authentication Status Register" hexmask.long.tbyte 0x10 8.--31. 1. "RES0_PMAUTHSTATUS_31_8,Reserved RES0." bitfld.long 0x10 6.--7. "SNID,Holds the same value as DBGAUTHSTATUS_EL1.SNID." "0,1,2,3" newline bitfld.long 0x10 4.--5. "RES0_PMAUTHSTATUS_5_4,Reserved RES0." "0,1,2,3" bitfld.long 0x10 2.--3. "NSNID,Holds the same value as DBGAUTHSTATUS_EL1.NSNID." "0,1,2,3" newline bitfld.long 0x10 0.--1. "RES0_PMAUTHSTATUS_1_0,Reserved RES0." "0,1,2,3" line.long 0x14 "APBADDR_PMU_CPU2_PMDEVARCH,Performance Monitors Device Architecture Register" hexmask.long.word 0x14 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For Performance Monitors this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x14 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A." "0,1" newline hexmask.long.byte 0x14 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For Performance Monitors the revision defined by v8-A is 0x0.All other values are reserved." hexmask.long.word 0x14 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For Performance Monitors:Bits [15:12] are the architecture version 0x2.Bits [11:0] are the architecture part number 0xA16.This.." group.long 0xFCC++0x33 line.long 0x0 "APBADDR_PMU_CPU2_PMDEVTYPE,Performance Monitors Device Type Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_PMDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x0 4.--7. 1. "SUB,Subtype. Must read as 0x1 to indicate this is a processor component." newline hexmask.long.byte 0x0 0.--3. 1. "MAJOR,Major type. Must read as 0x6 to indicate this is a performance monitor component." line.long 0x4 "APBADDR_PMU_CPU2_PMPIDR4,Performance Monitors Peripheral Identification Register 4" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_PMPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x4 4.--7. 1. "SIZE,Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers." newline hexmask.long.byte 0x4 0.--3. 1. "DES_2,Designer JEP106 continuation code least significant nibble. For ARM Limited this field is 0b0100." line.long 0x8 "APBADDR_PMU_CPU2_PMPIDR5,Performance Monitors Peripheral Identification Register 5" hexmask.long 0x8 0.--31. 1. "RESERVED,Reserved RES0" line.long 0xC "APBADDR_PMU_CPU2_PMPIDR6,Performance Monitors Peripheral Identification Register 6" hexmask.long 0xC 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x10 "APBADDR_PMU_CPU2_PMPIDR7,Performance Monitors Peripheral Identification Register 7" hexmask.long 0x10 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x14 "APBADDR_PMU_CPU2_PMPIDR0,Performance Monitors Peripheral Identification Register 0" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_PMPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x14 0.--7. 1. "PART_0,Part number least significant byte." line.long 0x18 "APBADDR_PMU_CPU2_PMPIDR1,Performance Monitors Peripheral Identification Register 1" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_PMPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x18 4.--7. 1. "DES_0,Designer least significant nibble of JEP106 ID code. For ARM Limited this field is 0b1011." newline hexmask.long.byte 0x18 0.--3. 1. "PART_1,Part number most significant nibble." line.long 0x1C "APBADDR_PMU_CPU2_PMPIDR2,Performance Monitors Peripheral Identification Register 2" hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_PMPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x1C 4.--7. 1. "REVISION,Part major revision. Parts can also use this field to extend Part number to 16-bits." newline bitfld.long 0x1C 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" bitfld.long 0x1C 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0x20 "APBADDR_PMU_CPU2_PMPIDR3,Performance Monitors Peripheral Identification Register 3" hexmask.long.tbyte 0x20 8.--31. 1. "RES0_PMPIDR3_31_8,Reserved RES0." hexmask.long.byte 0x20 4.--7. 1. "REVAND,Part minor revision. Parts using PMPIDR2.REVISION as an extension to the Part number must use this field as a major revision number." newline hexmask.long.byte 0x20 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x24 "APBADDR_PMU_CPU2_PMCIDR0,Performance Monitors Component Identification Register 0" hexmask.long.tbyte 0x24 8.--31. 1. "RES0_PMCIDR0_31_8,Reserved RES0." hexmask.long.byte 0x24 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x28 "APBADDR_PMU_CPU2_PMCIDR1,Performance Monitors Component Identification Register 1" hexmask.long.tbyte 0x28 8.--31. 1. "RES0_PMCIDR1_31_8,Reserved RES0." hexmask.long.byte 0x28 4.--7. 1. "CLASS,Component class. Reads as 0x9 debug component." newline hexmask.long.byte 0x28 0.--3. 1. "PRMBL_1,Preamble. RAZ." line.long 0x2C "APBADDR_PMU_CPU2_PMCIDR2,Performance Monitors Component Identification Register 2" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_PMCIDR2_31_8,Reserved RES0." hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x30 "APBADDR_PMU_CPU2_PMCIDR3,Performance Monitors Component Identification Register 3" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_PMCIDR3_31_8,Reserved RES0." hexmask.long.byte 0x30 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree.end tree "A53SS0_CORE3" tree "A53SS0_CORE3_CTI" base ad:0x730340000 group.long 0x0++0x3 line.long 0x0 "APBADDR_CTI_CPU3_CTICONTROL,CTI Control Register" hexmask.long 0x0 1.--31. 1. "RES0_CTICONTROL_31_1,Reserved RES0." bitfld.long 0x0 0. "GLBEN,Enables or disables the CTI mapping functions. Possible values of this field are: 0 CTI mapping functions disabled. 1 CTI mapping functions enabled. When the mapping.." "0,1" group.long 0x10++0x2F line.long 0x0 "APBADDR_CTI_CPU3_CTIINTACK,CTI Output Trigger Acknowledge Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--7. 1. "ACK_N,Can be used to create soft acknowledges for output triggers" line.long 0x4 "APBADDR_CTI_CPU3_CTIAPPSET,CTI Application Trigger Set Register" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "CTIAPPSETX,Application trigger enable" line.long 0x8 "APBADDR_CTI_CPU3_CTIAPPCLEAR,CTI Application Trigger Clear Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x8 0.--3. 1. "CTIAPPCLEARX,Application trigger disable" line.long 0xC "APBADDR_CTI_CPU3_CTIAPPPULSE,CTI Application Pulse Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0xC 0.--3. 1. "CTIAPPPULSEX,Generate event pulse on ECT channel ." line.long 0x10 "APBADDR_CTI_CPU3_CTIINEN0,CTI Input Trigger to Output Channel Enable Register 0" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x10 0.--3. 1. "INENX,Input trigger 0 to output channel enable" line.long 0x14 "APBADDR_CTI_CPU3_CTIINEN1,CTI Input Trigger to Output Channel Enable Register 1" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x14 0.--3. 1. "INENX,Input trigger 1 to output channel enable" line.long 0x18 "APBADDR_CTI_CPU3_CTIINEN2,CTI Input Trigger to Output Channel Enable Register 2" hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x18 0.--3. 1. "INENX,Input trigger 2 to output channel enable" line.long 0x1C "APBADDR_CTI_CPU3_CTIINEN3,CTI Input Trigger to Output Channel Enable Register 3" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x1C 0.--3. 1. "INENX,Input trigger 3 to output channel enable" line.long 0x20 "APBADDR_CTI_CPU3_CTIINEN4,CTI Input Trigger to Output Channel Enable Register 4" hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x20 0.--3. 1. "INENX,Input trigger 4 to output channel enable" line.long 0x24 "APBADDR_CTI_CPU3_CTIINEN5,CTI Input Trigger to Output Channel Enable Register 5" hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x24 0.--3. 1. "INENX,Input trigger 5 to output channel enable" line.long 0x28 "APBADDR_CTI_CPU3_CTIINEN6,CTI Input Trigger to Output Channel Enable Register 6" hexmask.long 0x28 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x28 0.--3. 1. "INENX,Input trigger 6 to output channel enable" line.long 0x2C "APBADDR_CTI_CPU3_CTIINEN7,CTI Input Trigger to Output Channel Enable Register 7" hexmask.long 0x2C 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x2C 0.--3. 1. "INENX,Input trigger 7 to output channel enable" group.long 0xA0++0x1F line.long 0x0 "APBADDR_CTI_CPU3_CTIOUTEN0,CTI Input Channel to Output Trigger Enable Register 0" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--3. 1. "OUTENX,Input channel to output trigger 0 enable" line.long 0x4 "APBADDR_CTI_CPU3_CTIOUTEN1,CTI Input Channel to Output Trigger Enable Register 1" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "OUTENX,Input channel to output trigger 1 enable" line.long 0x8 "APBADDR_CTI_CPU3_CTIOUTEN2,CTI Input Channel to Output Trigger Enable Register 2" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x8 0.--3. 1. "OUTENX,Input channel to output trigger 2 enable" line.long 0xC "APBADDR_CTI_CPU3_CTIOUTEN3,CTI Input Channel to Output Trigger Enable Register 3" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0xC 0.--3. 1. "OUTENX,Input channel to output trigger 3 enable" line.long 0x10 "APBADDR_CTI_CPU3_CTIOUTEN4,CTI Input Channel to Output Trigger Enable Register 4" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x10 0.--3. 1. "OUTENX,Input channel to output trigger 4 enable" line.long 0x14 "APBADDR_CTI_CPU3_CTIOUTEN5,CTI Input Channel to Output Trigger Enable Register 5" hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x14 0.--3. 1. "OUTENX,Input channel to output trigger 5 enable" line.long 0x18 "APBADDR_CTI_CPU3_CTIOUTEN6,CTI Input Channel to Output Trigger Enable Register 6" hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x18 0.--3. 1. "OUTENX,Input channel to output trigger 6 enable" line.long 0x1C "APBADDR_CTI_CPU3_CTIOUTEN7,CTI Input Channel to Output Trigger Enable Register 7" hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x1C 0.--3. 1. "OUTENX,Input channel to output trigger 7 enable" group.long 0x130++0x17 line.long 0x0 "APBADDR_CTI_CPU3_CTITRIGINSTATUS,CTI Trigger In Status Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--7. 1. "TRINN,Provides the status of the trigger inputs" line.long 0x4 "APBADDR_CTI_CPU3_CTITRIGOUTSTATUS,CTI Trigger Out Status Register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--7. 1. "TROUTN,Provides the status of the trigger outputs" line.long 0x8 "APBADDR_CTI_CPU3_CTICHINSTATUS,CTI Channel In Status Register" hexmask.long 0x8 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x8 0.--3. 1. "CHINN,Provides the raw status of the ECT channel inputs to the CTI" line.long 0xC "APBADDR_CTI_CPU3_CTICHOUTSTATUS,CTI Channel Out Status Register" hexmask.long 0xC 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0xC 0.--3. 1. "CHOUTN,Provides the status of the ECT channel outputs from the CTI" line.long 0x10 "APBADDR_CTI_CPU3_CTIGATE,CTI Channel Gate Enable Register" hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x10 0.--3. 1. "GATEX,Determines whether events on channels propagate through the CTM to other ECT components or from the CTM into the CTI" line.long 0x14 "APBADDR_CTI_CPU3_ASICCTL,CTI External Multiplexor Control register" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_ASICCTL_31_8,Reserved RES0." hexmask.long.byte 0x14 0.--7. 1. "ASICCTL,IMPLEMENTATION DEFINED ASIC control. Provides a control for external multiplexing of additional triggers into the CTI.If external multiplexing of trigger signals is implemented then the number of multiplexed signals on each trigger must be.." group.long 0xF00++0x3 line.long 0x0 "APBADDR_CTI_CPU3_CTIITCTRL,CTI Integration mode Control Register" hexmask.long 0x0 1.--31. 1. "RES0_CTIITCTRL_31_1,Reserved RES0." bitfld.long 0x0 0. "IME,Integration mode enable. When IME == 1 the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED. 0 Normal operation." "0,1" group.long 0xFA0++0x5F line.long 0x0 "APBADDR_CTI_CPU3_CTICLAIMSET,CTI Claim Set" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--3. 1. "CLAIMX,CLAIM tag set bit" line.long 0x4 "APBADDR_CTI_CPU3_CTICLAIMCLR,CTI Claim Clear" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "CLAIMX,Clear CLAIM tag" line.long 0x8 "APBADDR_CTI_CPU3_CTIDEVAFF0,CTI Device Affinity Register 0" hexmask.long 0x8 0.--31. 1. "CTIDEVAFF0,MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0xC "APBADDR_CTI_CPU3_CTIDEVAFF1,CTI Device Affinity Register 1" hexmask.long 0xC 0.--31. 1. "CTIDEVAFF1,MPIDR_EL1 high half. Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x10 "APBADDR_CTI_CPU3_CTILAR,CTI Lock Access Register" hexmask.long 0x10 0.--31. 1. "KEY,Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register locks the lock disabling write.." line.long 0x14 "APBADDR_CTI_CPU3_CTILSR,CTI Lock Status Register" hexmask.long 0x14 3.--31. 1. "RES0_CTILSR_31_3,Reserved RES0." bitfld.long 0x14 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" bitfld.long 0x14 1. "SLK,Software lock status for this component. For an access to LSR that is not a memory-mapped access or when the software lock is not implemented this field is RES0.For memory-mapped accesses when the software lock is implemented possible values of.." "0,1" newline bitfld.long 0x14 0. "SLI,Software lock implemented. For an access to LSR that is not a memory-mapped access this field is RAZ. For memory-mapped accesses the value of this field is IMPLEMENTATION DEFINED. Permitted values are: 0 Software lock not.." "0,1" line.long 0x18 "APBADDR_CTI_CPU3_CTIAUTHSTATUS,CTI Authentication Status Register" hexmask.long 0x18 4.--31. 1. "RES0_CTIAUTHSTATUS_31_4,Reserved RES0." bitfld.long 0x18 2.--3. "NSNID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SNID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSNID." "0,1,2,3" bitfld.long 0x18 0.--1. "NSID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSID." "0,1,2,3" line.long 0x1C "APBADDR_CTI_CPU3_CTIDEVARCH,CTI Device Architecture Register" hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For CTI this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A." "0,1" hexmask.long.byte 0x1C 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For CTI the revision defined by v8-A is 0x0.All other values are reserved." newline hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For CTI:Bits [15:12] are the architecture version 0x1.Bits [11:0] are the architecture part number 0xA14.This corresponds to CTI.." line.long 0x20 "APBADDR_CTI_CPU3_CTIDEVID2,CTI Device ID Register 2" hexmask.long 0x20 0.--31. 1. "RES0_CTIDEVID2_31_0,Reserved RES0." line.long 0x24 "APBADDR_CTI_CPU3_CTIDEVID1,CTI Device ID Register 1" hexmask.long 0x24 0.--31. 1. "RES0_CTIDEVID1_31_0,Reserved RES0." line.long 0x28 "APBADDR_CTI_CPU3_CTIDEVID,CTI Device ID Register 0" hexmask.long.byte 0x28 26.--31. 1. "RES0_CTIDEVID_31_26,Reserved RES0." bitfld.long 0x28 24.--25. "INOUT,Input/output options. Indicates presence of the input gate. If the CTM is not implemented this field is RAZ. 00 CTIGATE does not mask propagation of input events from external channels. 01.." "0,1,2,3" bitfld.long 0x28 22.--23. "RES0_CTIDEVID_23_22,Reserved RES0." "0,1,2,3" newline hexmask.long.byte 0x28 16.--21. 1. "NUMCHAN,Number of ECT channels implemented. IMPLEMENTATION DEFINED. For v8-A valid values are: 000011 3 channels [0..2] implemented. 000100 4 channels [0..3] implemented." bitfld.long 0x28 14.--15. "RES0_CTIDEVID_15_14,Reserved RES0." "0,1,2,3" hexmask.long.byte 0x28 8.--13. 1. "NUMTRIG,Number of triggers implemented. IMPLEMENTATION DEFINED. This is one more than the index of the largest trigger rather than the actual number of triggers.For v8-A valid values are: 000011 Up to 3 triggers [0..2] implemented." newline bitfld.long 0x28 5.--7. "RES0_CTIDEVID_7_5,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 0.--4. 1. "EXTMUXNUM,Maximum number of external triggers available for multiplexing into the CTI. This relates only to additional external triggers outside those defined for v8-A." line.long 0x2C "APBADDR_CTI_CPU3_CTIDEVTYPE,CTI Device Type Register" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_CTIDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x2C 4.--7. 1. "SUB,Subtype. Must read as 0x1 to indicate this is a processor component." hexmask.long.byte 0x2C 0.--3. 1. "MAJOR,Major type. Must read as 0x4 to indicate this is a cross-trigger component." line.long 0x30 "APBADDR_CTI_CPU3_CTIPIDR4,CTI Peripheral Identification Register 4" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_CTIPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x30 4.--7. 1. "SIZE,Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers." hexmask.long.byte 0x30 0.--3. 1. "DES_2,Designer JEP106 continuation code least significant nibble. For ARM Limited this field is 0b0100." line.long 0x34 "APBADDR_CTI_CPU3_CTIPIDR5,CTI Peripheral Identification Register 5" hexmask.long 0x34 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x38 "APBADDR_CTI_CPU3_CTIPIDR6,CTI Peripheral Identification Register 6" hexmask.long 0x38 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x3C "APBADDR_CTI_CPU3_CTIPIDR7,CTI Peripheral Identification Register 7" hexmask.long 0x3C 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x40 "APBADDR_CTI_CPU3_CTIPIDR0,CTI Peripheral Identification Register 0" hexmask.long.tbyte 0x40 8.--31. 1. "RES0_CTIPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x40 0.--7. 1. "PART_0,Part number least significant byte." line.long 0x44 "APBADDR_CTI_CPU3_CTIPIDR1,CTI Peripheral Identification Register 1" hexmask.long.tbyte 0x44 8.--31. 1. "RES0_CTIPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x44 4.--7. 1. "DES_0,Designer least significant nibble of JEP106 ID code. For ARM Limited this field is 0b1011." hexmask.long.byte 0x44 0.--3. 1. "PART_1,Part number most significant nibble." line.long 0x48 "APBADDR_CTI_CPU3_CTIPIDR2,CTI Peripheral Identification Register 2" hexmask.long.tbyte 0x48 8.--31. 1. "RES0_CTIPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x48 4.--7. 1. "REVISION,Part major revision. Parts can also use this field to extend Part number to 16-bits." bitfld.long 0x48 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" newline bitfld.long 0x48 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0x4C "APBADDR_CTI_CPU3_CTIPIDR3,CTI Peripheral Identification Register 3" hexmask.long.tbyte 0x4C 8.--31. 1. "RES0_CTIPIDR3_31_8,Reserved RES0." hexmask.long.byte 0x4C 4.--7. 1. "REVAND,Part minor revision. Parts using CTIPIDR2.REVISION as an extension to the Part number must use this field as a major revision number." hexmask.long.byte 0x4C 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x50 "APBADDR_CTI_CPU3_CTICIDR0,CTI Component Identification Register 0" hexmask.long.tbyte 0x50 8.--31. 1. "RES0_CTICIDR0_31_8,Reserved RES0." hexmask.long.byte 0x50 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x54 "APBADDR_CTI_CPU3_CTICIDR1,CTI Component Identification Register 1" hexmask.long.tbyte 0x54 8.--31. 1. "RES0_CTICIDR1_31_8,Reserved RES0." hexmask.long.byte 0x54 4.--7. 1. "CLASS,Component class. Reads as 0x9 debug component." hexmask.long.byte 0x54 0.--3. 1. "PRMBL_1,Preamble. RAZ." line.long 0x58 "APBADDR_CTI_CPU3_CTICIDR2,CTI Component Identification Register 2" hexmask.long.tbyte 0x58 8.--31. 1. "RES0_CTICIDR2_31_8,Reserved RES0." hexmask.long.byte 0x58 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x5C "APBADDR_CTI_CPU3_CTICIDR3,CTI Component Identification Register 3" hexmask.long.tbyte 0x5C 8.--31. 1. "RES0_CTICIDR3_31_8,Reserved RES0." hexmask.long.byte 0x5C 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree "A53SS0_CORE3_DBG" base ad:0x730310000 group.long 0x20++0x7 line.long 0x0 "APBADDR_DBG_CPU3_EDESR,External Debug Event Status Register" hexmask.long 0x0 3.--31. 1. "RES0_EDESR_31_3,Reserved RES0." bitfld.long 0x0 2. "SS,Halting step debug event pending. Possible values of this field are: 0 Reading this means that a Halting step debug event is not pending. Writing this means no action. 1 Reading this means that.." "0,1" newline bitfld.long 0x0 1. "RC,Reset catch debug event pending. Possible values of this field are: 0 Reading this means that a Reset catch debug event is not pending. Writing this means no action. 1 Reading this means that a.." "0,1" bitfld.long 0x0 0. "OSUC,OS unlock debug event pending. Possible values of this field are: 0 Reading this means that an OS unlock catch debug event is not pending. Writing this means no action. 1 Reading this means.." "0,1" line.long 0x4 "APBADDR_DBG_CPU3_EDECR,External Debug Execution Control Register" hexmask.long 0x4 3.--31. 1. "RES0_EDECR_31_3,Reserved RES0." bitfld.long 0x4 2. "SS,Halting step enable. Possible values of this field are: 0 Halting step debug event disabled. 1 Halting step debug event enabled. If the value of EDECR.SS is changed when the.." "0,1" newline bitfld.long 0x4 1. "RCE,Reset catch enable. Possible values of this field are: 0 Reset catch debug event disabled. 1 Reset catch debug event enabled." "0,1" bitfld.long 0x4 0. "OSUCE,OS unlock catch enabled. Possible values of this field are: 0 OS unlock catch debug event disabled. 1 OS unlock catch debug event enabled." "0,1" group.long 0x30++0x7 line.long 0x0 "APBADDR_DBG_CPU3_EDWAR_31_0,External Debug Watchpoint Address Register (low word)" hexmask.long 0x0 0.--31. 1. "EDWAR_31_0,Watchpoint address. The virtual data address being accessed when a watchpoint debug event was triggered and caused entry to Debug state.UNKNOWN if the processor is not in Debug state or if Debug state was entered other than for a watchpoint.." line.long 0x4 "APBADDR_DBG_CPU3_EDWAR_63_32,External Debug Watchpoint Address Register (high word)" hexmask.long 0x4 0.--31. 1. "EDWAR_63_32,Watchpoint address. The virtual data address being accessed when a watchpoint debug event was triggered and caused entry to Debug state.UNKNOWN if the processor is not in Debug state or if Debug state was entered other than for a watchpoint.." group.long 0x80++0x1B line.long 0x0 "APBADDR_DBG_CPU3_DBGDTRRX_EL0,Debug Data Transfer Register Receive" hexmask.long 0x0 0.--31. 1. "DBGDTRRX_EL0,Update DTRRX. Writes to this register update the value in DTRRX and set RXfull to 1.Reads of this register return the last value written to DTRRX and do not change RXfull." line.long 0x4 "APBADDR_DBG_CPU3_EDITR,External Debug Instruction Transfer Register" hexmask.long 0x4 0.--31. 1. "EDITR,Used in Debug state for passing instructions to the processor for execution" line.long 0x8 "APBADDR_DBG_CPU3_EDSCR,External Debug Status and Control Register" bitfld.long 0x8 31. "RES0_EDSCR_31_31,Reserved RES0." "0,1" bitfld.long 0x8 30. "RXFULL,DTRRX full. This bit is RO." "0,1" newline bitfld.long 0x8 29. "TXFULL,DTRTX full. This bit is RO." "0,1" bitfld.long 0x8 28. "ITO,EDITR overrun. This bit is RO.If the processor is not in Debug state this bit is UNKNOWN. ITO is set to 0 on entry to Debug state." "0,1" newline bitfld.long 0x8 27. "RXO,DTRRX overrun. This bit is RO." "0,1" bitfld.long 0x8 26. "TXU,DTRTX underrun. This bit is RO." "0,1" newline bitfld.long 0x8 25. "PIPEADV,Pipeline advance. Read-only. Set to 1 every time the processor pipeline retires one or more instructions. Cleared to 0 by a write to EDRCR.CSPA.The architecture does not define precisely when this bit is set to 1. It requires only that this.." "0,1" bitfld.long 0x8 24. "ITE,ITR empty. This bit is RO.If the processor is not in Debug state this bit is UNKNOWN. It is always valid in Debug state." "0,1" newline bitfld.long 0x8 22.--23. "INTDIS,Interrupt disable. Disables taking interrupts [including virtual interrupts and System Error interrupts] in Non-Debug state.If external invasive debug is disabled the value of this field is ignored.If external invasive debug is enabled the.." "0,1,2,3" bitfld.long 0x8 21. "TDA,Trap debug registers accesses." "0,1" newline bitfld.long 0x8 20. "MA,Memory access mode. Controls use of memory-access mode for accessing EDITR and the DCC. This bit is ignored if in Non-debug state and set to zero on entry to Debug state.Possible values of this field are: 0 Normal access mode.." "0,1" bitfld.long 0x8 19. "RES0_EDSCR_19_19,Reserved RES0." "0,1" newline bitfld.long 0x8 18. "NS,Non-secure status. Read-only. When in Debug state gives the current security state: 0 Secure state IsSecure[] == TRUE 1 Non-secure state IsSecure[] == FALSE. In Non-debug.." "0,1" bitfld.long 0x8 17. "RES0_EDSCR_17_17,Reserved RES0." "0,1" newline bitfld.long 0x8 16. "SDD,Secure debug disabled. This bit is RO.On entry to Debug state:If entering in Secure state SDD is set to 0.If entering in Non-secure state SDD is set to the inverse of ExternalSecureInvasiveDebugEnabled[].In Debug state the value of the SDD bit.." "0,1" bitfld.long 0x8 15. "RES0_EDSCR_15_15,Reserved RES0." "0,1" newline bitfld.long 0x8 14. "HDE,Halting debug mode enable. Possible values of this bit are: 0 Halting debug mode disabled. 1 Halting debug mode enabled." "0,1" hexmask.long.byte 0x8 10.--13. 1. "RW,Exception level register-width status. Read-only. In Debug state each bit gives the current register width status of each EL: 1111 All exception levels are AArch64 state. 1110 EL0 is AArch32.." newline bitfld.long 0x8 8.--9. "EL,Exception level. Read-only. In Debug state this gives the current EL of the processor.In Non-debug state this field is RAZ." "0,1,2,3" bitfld.long 0x8 7. "A,System Error interrupt pending. Read-only. In Debug state indicates whether a SError interrupt is pending:If HCR_EL2.{AMO TGE} = {1 0} and in Non-secure EL0 or EL1 a virtual SError interrupt.Otherwise a physical SError interrupt. 0.." "0,1" newline bitfld.long 0x8 6. "ERR,Cumulative error flag. This field is RO. It is set to 1 following exceptions in Debug state and on any signaled overrun or underrun on the DTR or EDITR." "0,1" hexmask.long.byte 0x8 0.--5. 1. "STATUS,Debug status flags. This field is RO.The possible values of this field are: 000010 Processor is in Non-debug state. 000001 Processor is restarting [exiting Debug state]." line.long 0xC "APBADDR_DBG_CPU3_DBGDTRTX_EL0,Debug Data Transfer Register Transmit" hexmask.long 0xC 0.--31. 1. "DBGDTRTX_EL0,Return DTRTX. Reads of this register return the value in DTRTX and clear TXfull to 0.Writes of this register update the value in DTRTX and do not change TXfull." line.long 0x10 "APBADDR_DBG_CPU3_EDRCR,External Debug Reserve Control Register" hexmask.long 0x10 5.--31. 1. "RES0_EDRCR_31_5,Reserved RES0." bitfld.long 0x10 4. "CBRRQ,Allow imprecise entry to Debug state. The actions on writing to this bit are: 0 No action. 1 Allow imprecise entry to Debug state for example by canceling pending bus accesses." "0,1" newline bitfld.long 0x10 3. "CSPA,Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The actions on writing to this bit are: 0 No action. 1 Clear the EDSCR.PipeAdv bit to 0." "0,1" bitfld.long 0x10 2. "CSE,Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The actions on writing to this bit are: 0 No action. 1 Clear the EDSCR.{TXU RXO ERR} bits and if the processor is in.." "0,1" newline bitfld.long 0x10 0.--1. "RES0_EDRCR_1_0,Reserved RES0." "0,1,2,3" line.long 0x14 "APBADDR_DBG_CPU3_EDACR,External Debug Auxiliary Control Register" hexmask.long 0x14 0.--31. 1. "RES0_EDACR_31_0,Reserved RES0" line.long 0x18 "APBADDR_DBG_CPU3_EDECCR,External Debug Exception Catch Control Register" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDECCR_31_8,Reserved RES0." hexmask.long.byte 0x18 4.--7. 1. "NSE,Coarse-grained Non-secure exception catch. Possible values of this field are: 0000 Exception catch debug event disabled for Non-secure exception levels. 0010 Exception catch debug event enabled.." newline hexmask.long.byte 0x18 0.--3. 1. "SE,Coarse-grained Secure exception catch. Possible values of this field are: 0000 Exception catch debug event disabled for Secure exception levels. 0010 Exception catch debug event enabled for.." group.long 0xA0++0xF line.long 0x0 "APBADDR_DBG_CPU3_EDPCSR_31_0,External Debug Program Counter Sample Register (low word)" hexmask.long 0x0 0.--31. 1. "EDPCSR_31_0,PC Sample low word EDPCSRlo. Bits [31:0] of the sampled instruction address value. Reading EDPCSRlo has the side-effect of updating EDCIDSR EDVIDSR and EDPCSRhi. However:If the processor is in Debug state or Sample-based profiling is.." line.long 0x4 "APBADDR_DBG_CPU3_EDCIDSR,External Debug Context ID Sample Register" hexmask.long 0x4 0.--31. 1. "CONTEXTIDR,The sampled value of CONTEXTIDR_EL1 captured on reading the low half of EDPCSR.If EL3 is implemented and using AArch32 then CONTEXTIDR is a Banked register and EDCIDSR samples the current Banked copy of CONTEXTIDR." line.long 0x8 "APBADDR_DBG_CPU3_EDVIDSR,External Debug Virtual Context Sample Register" bitfld.long 0x8 31. "NS,Non-secure state sample. Indicates the security state associated with the most recent EDPCSR sample." "0,1" bitfld.long 0x8 30. "E2,Exception level 2 status sample. Indicates whether the most recent EDPCSR sample was associated with EL2. If EDVIDSR.NS == 0 this bit is 0." "0,1" newline bitfld.long 0x8 29. "E3,Exception level 3 status sample. Indicates whether the most recent EDPCSR sample was associated with AArch64 EL3. If EDVIDSR.NS == 1 or the processor was in AArch32 state when EDPCSR was read this bit is 0." "0,1" bitfld.long 0x8 28. "HV,EDPCSR high half valid. Indicates whether bits [63:32] of the most recent EDPCSR sample are valid. If EDVIDSR.HV == 0 the value of EDPCSR[63:32] is RAZ." "0,1" newline hexmask.long.tbyte 0x8 8.--27. 1. "RES0_EDVIDSR_27_8,Reserved RES0." hexmask.long.byte 0x8 0.--7. 1. "VMID,VMID sample. The value of VTTBR_EL2.VMID associated with the most recent EDPCSR sample. If EDVIDSR.NS == 0 or EDVIDSR.E2 == 1 this field is RAZ." line.long 0xC "APBADDR_DBG_CPU3_EDPCSR_63_32,External Debug Program Counter Sample Register (high word)" hexmask.long 0xC 0.--31. 1. "EDPCSR_63_32,PC Sample high word EDPCSRhi. If EDVIDSR.HV == 0 then this field is RAZ otherwise bits [63:32] of the sampled PC." group.long 0x300++0x3 line.long 0x0 "APBADDR_DBG_CPU3_OSLAR_EL1,OS Lock Access Register" hexmask.long 0x0 1.--31. 1. "RES0_OSLAR_EL1_31_1,Reserved RES0." bitfld.long 0x0 0. "OSLK,On writes to OSLAR_EL1 bit[0] is copied to the OS lock.Use EDPRSR.OSLK to check the current status of the lock." "0,1" group.long 0x310++0x7 line.long 0x0 "APBADDR_DBG_CPU3_EDPRCR,External Debug Power/Reset Control Register" hexmask.long 0x0 4.--31. 1. "RES0_EDPRCR_31_4,Reserved RES0." bitfld.long 0x0 3. "COREPURQ,Core powerup request. Allows a debugger to request that the power controller power up the core enabling access to the debug register in the Core power domain. The actions on writing to this bit are: 0 No effect." "0,1" newline bitfld.long 0x0 2. "RES0_EDPRCR_2_2,Reserved RES0." "0,1" bitfld.long 0x0 1. "CWRR,Warm reset request. Write only bit that reads as zero. The actions on writing to this bit are: 0 No action. 1 Request Warm reset. The processor ignores writes to this bit if.." "0,1" newline bitfld.long 0x0 0. "CORENPDRQ,Core no powerdown request. Requests emulation of powerdown. Possible values of this bit are: 0 On a powerdown request the system powers down the Core power domain. 1 On a powerdown.." "0,1" line.long 0x4 "APBADDR_DBG_CPU3_EDPRSR,External Debug Processor Status Register" hexmask.long.tbyte 0x4 12.--31. 1. "RES0_EDPRSR_31_12,Reserved RES0." bitfld.long 0x4 11. "SDR,Sticky debug restart. Set to 1 when the processor exits Debug state and cleared to 0 following reads of EDPRSR. 0 The processor has not restarted since EDPRSR was last read. 1 The processor has.." "0,1" newline bitfld.long 0x4 10. "SPMAD,Sticky EPMAD error. Set to 1 if an access returns an error because AllowExternalPMUAccess[] == FALSE. 0 No accesses to the external performance monitors registers have failed since EDPRSR was last read. 1.." "0,1" bitfld.long 0x4 9. "EPMAD,External performance monitors access disable status. 0 External performance monitors access enabled. 1 External performance monitors access disabled. If external performance.." "0,1" newline bitfld.long 0x4 8. "SDAD,Sticky EDAD error. Set to 1 if an access returns an error because AllowExternalDebugAccess[] == FALSE. 0 No accesses to the external debug registers have failed since EDPRSR was last read. 1.." "0,1" bitfld.long 0x4 7. "EDAD,External debug access disable status. 0 External debug access enabled. 1 External debug access disabled. This bit is UNKNOWN on reads if either of EDPRSR.{DLK R} is 1 or.." "0,1" newline bitfld.long 0x4 6. "DLK,OS Double Lock status bit. 0 OSDLR_EL1.DLK == 0 or EDPRCR.CORENPDRQ == 1 or the processor is in Debug state. 1 OSDLR_EL1.DLK == 1 and EDPRCR.CORENPDRQ == 0 and the processor is in Non-debug.." "0,1" bitfld.long 0x4 5. "OSLK,OS lock status bit. A read of this bit returns the value of OSLSR_EL1.OSLK.This bit is UNKNOWN on reads if either of EDPRSR.{DLK R} is 1 or EDPRSR.PU is 0." "0,1" newline bitfld.long 0x4 4. "HALTED,Halted status bit. Possible values are: 0 EDSCR.STATUS is 0b000010 [processor in Non-debug state]. 1 EDSCR.STATUS is not 0b000010. This bit is UNKNOWN on reads if EDPRSR.PU.." "0,1" bitfld.long 0x4 3. "SR,Sticky core reset status bit. Possible values are: 0 The non-debug logic of the processor is not in reset state and has not been reset since the last time EDPRSR was read. 1 The non-debug logic.." "0,1" newline bitfld.long 0x4 2. "R,Core reset status bit. Possible values are: 0 The non-debug logic of the processor is not in reset state. 1 The non-debug logic of the processor is in reset state. This bit is.." "0,1" bitfld.long 0x4 1. "SPD,Sticky core power-down status bit.This bit is set to 1 on Cold reset to indicate the state of the debug registers has been lost. Since a Cold reset is required on powering up the processor this usually indicates the Core power domain has been.." "0,1" newline bitfld.long 0x4 0. "PU,Core power-up status bit. Indicates whether the Core power domain debug registers can be accessed: 0 Core is in a low-power or power-down state where the debug registers cannot be accessed. 1.." "0,1" group.long 0x400++0xB line.long 0x0 "APBADDR_DBG_CPU3_DBGBVR0_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR0_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR0_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU3_DBGBVR0_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR0_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR0_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU3_DBGBCR0_EL1,Debug Breakpoint Control Register 0" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR0_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR0_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR0_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x410++0xB line.long 0x0 "APBADDR_DBG_CPU3_DBGBVR1_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR1_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR1_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU3_DBGBVR1_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR1_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR1_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU3_DBGBCR1_EL1,Debug Breakpoint Control Register 1" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR1_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR1_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR1_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x420++0xB line.long 0x0 "APBADDR_DBG_CPU3_DBGBVR2_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR2_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR2_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU3_DBGBVR2_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR2_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR2_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU3_DBGBCR2_EL1,Debug Breakpoint Control Register 2" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR2_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR2_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR2_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x430++0xB line.long 0x0 "APBADDR_DBG_CPU3_DBGBVR3_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR3_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR3_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU3_DBGBVR3_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR3_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR3_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU3_DBGBCR3_EL1,Debug Breakpoint Control Register 3" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR3_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR3_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR3_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x440++0xB line.long 0x0 "APBADDR_DBG_CPU3_DBGBVR4_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR4_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR4_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU3_DBGBVR4_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR4_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR4_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU3_DBGBCR4_EL1,Debug Breakpoint Control Register 4" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR4_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR4_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR4_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x450++0xB line.long 0x0 "APBADDR_DBG_CPU3_DBGBVR5_EL1_31_0,Debug Breakpoint Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR5_EL1. Multiple uses of this register refer.." hexmask.long 0x0 0.--31. 1. "DBGBVR5_EL1_31_0,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x4 "APBADDR_DBG_CPU3_DBGBVR5_EL1_63_32,Debug Breakpoint Extended Value Registers. Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR5_EL1. Multiple uses of this.." hexmask.long 0x4 0.--31. 1. "DBGBVR5_EL1_63_32,Holds a virtual address or a VMID and/or a context ID for use in breakpoint matching" line.long 0x8 "APBADDR_DBG_CPU3_DBGBCR5_EL1,Debug Breakpoint Control Register 5" hexmask.long.byte 0x8 24.--31. 1. "RES0_DBGBCR5_EL1_31_24,Reserved RES0." hexmask.long.byte 0x8 20.--23. 1. "BT,Breakpoint Type. Possible values are: 0000 Unlinked instruction address match. 0001 Linked instruction address match. 0010 Unlinked context ID match." newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked address matching breakpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields." "0,1" hexmask.long.byte 0x8 9.--12. 1. "RES0_DBGBCR5_EL1_12_9,Reserved RES0." newline hexmask.long.byte 0x8 5.--8. 1. "BAS,Byte address select. Defines which half-words an address-matching breakpoint matches regardless of the instruction set and execution state. In an AArch64-only implementation this field is reserved RES1. Otherwise:BAS[2] and BAS[0] are.." bitfld.long 0x8 3.--4. "RES0_DBGBCR5_EL1_4_3,Reserved RES0." "0,1,2,3" newline bitfld.long 0x8 1.--2. "PMC,Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" bitfld.long 0x8 0. "E,Enable breakpoint DBGBVR_EL1. Possible values are: 0 Breakpoint disabled. 1 Breakpoint enabled." "0,1" group.long 0x800++0xB line.long 0x0 "APBADDR_DBG_CPU3_DBGWVR0_EL1_31_0,Debug Watchpoint Value Register 0" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR0_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU3_DBGWVR0_EL1_63_32,Debug Watchpoint Extended Value Register 0" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU3_DBGWCR0_EL1,Debug Watchpoint Control Register 0" bitfld.long 0x8 29.--31. "RES0_DBGWCR0_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR0_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0x810++0xB line.long 0x0 "APBADDR_DBG_CPU3_DBGWVR1_EL1_31_0,Debug Watchpoint Value Register 1" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR1_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU3_DBGWVR1_EL1_63_32,Debug Watchpoint Extended Value Register 1" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU3_DBGWCR1_EL1,Debug Watchpoint Control Register 1" bitfld.long 0x8 29.--31. "RES0_DBGWCR1_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR1_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0x820++0xB line.long 0x0 "APBADDR_DBG_CPU3_DBGWVR2_EL1_31_0,Debug Watchpoint Value Register 2" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR2_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU3_DBGWVR2_EL1_63_32,Debug Watchpoint Extended Value Register 2" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU3_DBGWCR2_EL1,Debug Watchpoint Control Register 2" bitfld.long 0x8 29.--31. "RES0_DBGWCR2_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR2_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0x830++0xB line.long 0x0 "APBADDR_DBG_CPU3_DBGWVR3_EL1_31_0,Debug Watchpoint Value Register 3" hexmask.long 0x0 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." bitfld.long 0x0 0.--1. "RES0_DBGWVR3_EL1_31_0_1_0,Reserved RES0." "0,1,2,3" line.long 0x4 "APBADDR_DBG_CPU3_DBGWVR3_EL1_63_32,Debug Watchpoint Extended Value Register 3" hexmask.long.word 0x4 17.--31. 1. "RESS,Reserved Sign extended. Hardwired to the value of the sign bit bit [48]. Hardware and software must treat this field as RES0 if bit[48] is 0 and as RES1 if bit[48] is 1." hexmask.long.tbyte 0x4 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR_EL1[2] == 1." line.long 0x8 "APBADDR_DBG_CPU3_DBGWCR3_EL1,Debug Watchpoint Control Register 3" bitfld.long 0x8 29.--31. "RES0_DBGWCR3_EL1_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "MASK,Address mask. Only objects up to 2GB can be watched using a single mask. 00000 No mask. 00001 Reserved. 00010 Reserved. Other values.." newline bitfld.long 0x8 21.--23. "RES0_DBGWCR3_EL1_23_21,Reserved RES0." "0,1,2,3,4,5,6,7" bitfld.long 0x8 20. "WT,Watchpoint type. Possible values are: 0 Unlinked data address match. 1 Linked data address match." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "LBN,Linked breakpoint number. For Linked data address watchpoints this specifies the index of the Context-matching breakpoint linked to." bitfld.long 0x8 14.--15. "SSC,Security state control. Determines the security states under which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields." "0,1,2,3" newline bitfld.long 0x8 13. "HMC,Higher mode control. Determines the debug perspective for deciding when a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields." "0,1" hexmask.long.byte 0x8 5.--12. 1. "BAS,Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR_EL1 is being watched.BASDescriptionxxxxxxx1Match byte at DBGWVR_EL1xxxxxx1xMatch byte at DBGWVR_EL1+1xxxxx1xxMatch.." newline bitfld.long 0x8 3.--4. "LSC,Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are: 01 Match instructions that load from a watchpointed address. 10.." "0,1,2,3" bitfld.long 0x8 1.--2. "PAC,Privilege of access control. Determines the exception level or levels at which a watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields." "0,1,2,3" newline bitfld.long 0x8 0. "E,Enable watchpoint n. Possible values are: 0 Watchpoint disabled. 1 Watchpoint enabled." "0,1" group.long 0xD00++0x3 line.long 0x0 "APBADDR_DBG_CPU3_MIDR_EL1,Main ID Register" hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,The Implementer code. This field must hold an implementer code that has been assigned by ARM." hexmask.long.byte 0x0 20.--23. 1. "VARIANT,An IMPLEMENTATION DEFINED variant number. Typically this field is used to distinguish between different product variants or major revisions of a product." newline hexmask.long.byte 0x0 16.--19. 1. "ARCHITECTURE" hexmask.long.word 0x0 4.--15. 1. "PARTNUM,An IMPLEMENTATION DEFINED primary part number for the device. On processors implemented by ARM if the top four bits of the primary part number are 0x0 or 0x7 the variant and architecture are encoded differently" newline hexmask.long.byte 0x0 0.--3. 1. "REVISION,An IMPLEMENTATION DEFINED revision number for the device" group.long 0xD20++0x3F line.long 0x0 "APBADDR_DBG_CPU3_ID_AA64PFR0_EL1_31_0,Processor Feature Register 0 (low word)" hexmask.long.byte 0x0 28.--31. 1. "RES0_ID_AA64PFR0_EL1_31_0_31_28,Reserved RES0." hexmask.long.byte 0x0 24.--27. 1. "GIC,GIC system register interface. Permitted values are: 0000 No GIC system registers are supported. 0001 GICv3 system registers are supported. All other values are reserved." newline hexmask.long.byte 0x0 20.--23. 1. "ADVSIMD,Advanced SIMD. Permitted values are: 0000 Advanced SIMD is implemented. 1111 Advanced SIMD is not implemented. All other values are reserved." hexmask.long.byte 0x0 16.--19. 1. "FP,Floating-point. Permitted values are: 0000 Floating-point is implemented. 1111 Floating-point is not implemented. All other values are reserved." newline hexmask.long.byte 0x0 12.--15. 1. "EL3,EL3 exception level handling. Permitted values are: 0000 EL3 is not implemented. 0001 EL3 can be executed in AArch64 state only. 0010 EL3 can be executed.." hexmask.long.byte 0x0 8.--11. 1. "EL2,EL2 exception level handling. Permitted values are: 0000 EL2 is not implemented. 0001 EL2 can be executed in AArch64 state only. 0010 EL2 can be executed.." newline hexmask.long.byte 0x0 4.--7. 1. "EL1,EL1 exception level handling. Permitted values are: 0000 EL1 is not implemented. 0001 EL1 can be executed in AArch64 state only. 0010 EL1 can be executed.." hexmask.long.byte 0x0 0.--3. 1. "EL0,EL0 exception level handling. Permitted values are: 0000 EL0 is not implemented. 0001 EL0 can be executed in AArch64 state only. 0010 EL0 can be executed.." line.long 0x4 "APBADDR_DBG_CPU3_ID_AA64PFR0_EL1_63_32,Processor Feature Register 0 (high word)" hexmask.long 0x4 0.--31. 1. "RES0_ID_AA64PFR0_EL1_63_32_31_0,Reserved RES0." line.long 0x8 "APBADDR_DBG_CPU3_ID_AA64DFR0_EL1_31_0,Debug Feature Register 0 (low word)" hexmask.long.byte 0x8 28.--31. 1. "CTX_CMPS,Number of breakpoints that are context-aware minus 1. These are the highest numbered breakpoints." hexmask.long.byte 0x8 24.--27. 1. "RES0_ID_AA64DFR0_EL1_31_0_27_24,Reserved RES0." newline hexmask.long.byte 0x8 20.--23. 1. "WRPS,Number of watchpoints minus 1. The value of 0b0000 is reserved." hexmask.long.byte 0x8 16.--19. 1. "RES0_ID_AA64DFR0_EL1_31_0_19_16,Reserved RES0." newline hexmask.long.byte 0x8 12.--15. 1. "BRPS,Number of breakpoints minus 1. The value of 0b0000 is reserved." hexmask.long.byte 0x8 8.--11. 1. "PMUVER,Performance Monitors extension version. Indicates whether system register interface to Performance Monitors extension is implemented. Permitted values are: 0000 Performance Monitors extension system registers not implemented." newline hexmask.long.byte 0x8 4.--7. 1. "TRACEVER,Trace extension. Indicates whether system register interface to Trace extension is implemented. Permitted values are: 0000 Trace extension system registers not implemented. 0001 Trace.." hexmask.long.byte 0x8 0.--3. 1. "DEBUGVER,Debug architecture version. Indicates presence of v8-A debug architecture. 0110 v8-A debug architecture. All other values are reserved." line.long 0xC "APBADDR_DBG_CPU3_ID_AA64DFR0_EL1_63_32,Debug Feature Register 0 (high word)" hexmask.long 0xC 0.--31. 1. "RES0_ID_AA64DFR0_EL1_63_32_31_0,Reserved RES0." line.long 0x10 "APBADDR_DBG_CPU3_ID_AA64ISAR0_EL1_31_0,Instruction Set Attribute Register 0 (low word)" hexmask.long.word 0x10 20.--31. 1. "RES0_ID_AA64ISAR0_EL1_31_0_31_20,Reserved RES0." hexmask.long.byte 0x10 16.--19. 1. "CRC32,CRC32 instructions in AArch64. Possible values of this field are: 0000 No CRC32 instructions implemented. 0001 CRC32B CRC32H CRC32W CRC32X CRC32CB CRC32CH CRC32CW and CRC32CX.." newline hexmask.long.byte 0x10 12.--15. 1. "SHA2,SHA2 instructions in AArch64. Possible values of this field are: 0000 No SHA2 instructions implemented. 0001 SHA256H SHA256H2 SHA256SU0 and SHA256SU1 instructions implemented." hexmask.long.byte 0x10 8.--11. 1. "SHA1,SHA1 instructions in AArch64. Possible values of this field are: 0000 No SHA1 instructions implemented. 0001 SHA1C SHA1P SHA1M SHA1H SHA1SU0 and SHA1SU1 instructions implemented." newline hexmask.long.byte 0x10 4.--7. 1. "AES,AES instructions in AArch64. Possible values of this field are: 0000 No AES instructions implemented. 0001 AESE AESD AESMC and AESIMC instructions implemented. 0010.." hexmask.long.byte 0x10 0.--3. 1. "RES0_ID_AA64ISAR0_EL1_31_0_3_0,Reserved RES0." line.long 0x14 "APBADDR_DBG_CPU3_ID_AA64ISAR0_EL1_63_32,Instruction Set Attribute Register 0 (high word)" hexmask.long 0x14 0.--31. 1. "RES0_ID_AA64ISAR0_EL1_63_32_31_0,Reserved RES0." line.long 0x18 "APBADDR_DBG_CPU3_ID_AA64MMFR0_EL1_31_0,Memory Model Feature Register 0 (low word)" hexmask.long.byte 0x18 28.--31. 1. "TGRAN4,Support for 4 Kbyte memory translation granule size. Permitted values are: 0000 4 KB granule supported. 1111 4 KB granule not supported. All other values are reserved." hexmask.long.byte 0x18 24.--27. 1. "TGRAN64,Support for 64 Kbyte memory translation granule size. Permitted values are: 0000 64 KB granule supported. 1111 64 KB granule not supported. All other values are reserved." newline hexmask.long.byte 0x18 20.--23. 1. "TGRAN16,Support for 16 Kbyte memory translation granule size. Permitted values are: 0000 16 KB granule not supported. 0001 16 KB granule supported. All other values are reserved." hexmask.long.byte 0x18 16.--19. 1. "BIGENDEL0,Mixed-endian support at EL0 only. Permitted values are: 0000 No mixed-endian support at EL0. The SCTLR_EL1.E0E bit has a fixed value. 0001 Mixed-endian support at EL0. The SCTLR_EL1.E0E.." newline hexmask.long.byte 0x18 12.--15. 1. "SNSMEM,Secure versus Non-secure Memory distinction. Permitted values are: 0000 Does not support a distinction between Secure and Non-secure Memory. 0001 Does support a distinction between Secure.." hexmask.long.byte 0x18 8.--11. 1. "BIGEND,Mixed-endian configuration support. Permitted values are: 0000 No mixed-endian support. The SCTLR_ELx.EE bits have a fixed value. See the BigEndEL0 field bits[19:16] for whether EL0 supports mixed-endian." newline hexmask.long.byte 0x18 4.--7. 1. "ASIDBITS,Number of ASID bits. Permitted values are: 0000 8 bits. 0010 16 bits. All other values are reserved." hexmask.long.byte 0x18 0.--3. 1. "PARANGE,Physical Address range supported. Permitted values are: 0000 32 bits 4 GB. 0001 36 bits 64 GB. 0010 40 bits 1 TB. 0011.." line.long 0x1C "APBADDR_DBG_CPU3_ID_AA64MMFR0_EL1_63_32,Memory Model Feature Register 0 (high word)" hexmask.long 0x1C 0.--31. 1. "RES0_ID_AA64MMFR0_EL1_63_32_31_0,Reserved RES0." line.long 0x20 "APBADDR_DBG_CPU3_ID_AA64PFR1_EL1_31_0,Processor Feature Register 1 (low word)" hexmask.long 0x20 0.--31. 1. "RES0_ID_AA64PFR1_EL1_31_0_31_0,Reserved RES0." line.long 0x24 "APBADDR_DBG_CPU3_ID_AA64PFR1_EL1_63_32,Processor Feature Register 1 (high word)" hexmask.long 0x24 0.--31. 1. "RES0_ID_AA64PFR1_EL1_63_32_31_0,Reserved RES0." line.long 0x28 "APBADDR_DBG_CPU3_ID_AA64DFR1_EL1_31_0,Auxiliary Feature Register 1 (low word)" hexmask.long 0x28 0.--31. 1. "RES0_ID_AA64DFR1_EL1_31_0_31_0,Reserved RES0." line.long 0x2C "APBADDR_DBG_CPU3_ID_AA64DFR1_EL1_63_32,Auxiliary Feature Register 1 (high word)" hexmask.long 0x2C 0.--31. 1. "RES0_ID_AA64DFR1_EL1_63_32_31_0,Reserved RES0." line.long 0x30 "APBADDR_DBG_CPU3_ID_AA64ISAR1_EL1_31_0,Instruction Set Attribute Register 1 (low word)" hexmask.long 0x30 0.--31. 1. "RES0_ID_AA64ISAR1_EL1_31_0_31_0,Reserved RES0." line.long 0x34 "APBADDR_DBG_CPU3_ID_AA64ISAR1_EL1_63_32,Instruction Set Attribute Register 1 (high word)" hexmask.long 0x34 0.--31. 1. "RES0_ID_AA64ISAR1_EL1_63_32_31_0,Reserved RES0." line.long 0x38 "APBADDR_DBG_CPU3_ID_AA64MMFR1_EL1_31_0,Memory Model Feature Register 1 (low word)" hexmask.long 0x38 0.--31. 1. "RES0_ID_AA64MMFR1_EL1_31_0_31_0,Reserved RES0." line.long 0x3C "APBADDR_DBG_CPU3_ID_AA64MMFR1_EL1_63_32,Memory Model Feature Register 1 (high word)" hexmask.long 0x3C 0.--31. 1. "RES0_ID_AA64MMFR1_EL1_63_32_31_0,Reserved RES0." group.long 0xF00++0x3 line.long 0x0 "APBADDR_DBG_CPU3_EDITCTRL,External Debug Integration mode Control Register" hexmask.long 0x0 1.--31. 1. "RES0_EDITCTRL_31_1,Reserved RES0." bitfld.long 0x0 0. "IME,Integration mode enable. When IME == 1 the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED. 0 Normal operation." "0,1" group.long 0xFA0++0x33 line.long 0x0 "APBADDR_DBG_CPU3_DBGCLAIMSET_EL1,Debug Claim Tag Set Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_DBGCLAIMSET_EL1_31_8,Reserved RAZ/SBZ. Software can rely on these bits reading as zero and must use a should-be-zero policy on writes. Implementations must ignore writes." hexmask.long.byte 0x0 0.--7. 1. "CLAIM,Claim set bits. RAO.Writing a 1 to one of these bits sets the corresponding CLAIM bit to 1. This is an indirect write to the CLAIM bits.A single write operation can set multiple bits to 1. Writing 0 to one of these bits has no effect." line.long 0x4 "APBADDR_DBG_CPU3_DBGCLAIMCLR_EL1,Debug Claim Tag Clear Register" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_DBGCLAIMCLR_EL1_31_8,Reserved RAZ/SBZ. Software can rely on these bits reading as zero and must use a should-be-zero policy on writes. Implementations must ignore writes." hexmask.long.byte 0x4 0.--7. 1. "CLAIM,Claim clear bits. Reading this field returns the current value of the CLAIM bits.Writing a 1 to one of these bits clears the corresponding CLAIM bit to 0. This is an indirect write to the CLAIM bits.A single write operation can clear multiple bits.." line.long 0x8 "APBADDR_DBG_CPU3_EDDEVAFF0,External Debug Device Affinity Register 0" hexmask.long 0x8 0.--31. 1. "EDDEVAFF0,MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0xC "APBADDR_DBG_CPU3_EDDEVAFF1,External Debug Device Affinity Register 1" hexmask.long 0xC 0.--31. 1. "EDDEVAFF1,MPIDR_EL1 high half. Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x10 "APBADDR_DBG_CPU3_EDLAR,External Debug Lock Access Register" hexmask.long 0x10 0.--31. 1. "KEY,Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register locks the lock disabling write.." line.long 0x14 "APBADDR_DBG_CPU3_EDLSR,External Debug Lock Status Register" hexmask.long 0x14 3.--31. 1. "RES0_EDLSR_31_3,Reserved RES0." bitfld.long 0x14 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" newline bitfld.long 0x14 1. "SLK,Software lock status for this component. For an access to LSR that is not a memory-mapped access or when the software lock is not implemented this field is RES0.For memory-mapped accesses when the software lock is implemented possible values of.." "0,1" bitfld.long 0x14 0. "SLI,Software lock implemented. For an access to LSR that is not a memory-mapped access this field is RAZ. For memory-mapped accesses the value of this field is IMPLEMENTATION DEFINED. Permitted values are: 0 Software lock not.." "0,1" line.long 0x18 "APBADDR_DBG_CPU3_DBGAUTHSTATUS_EL1,Debug Authentication Status register" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_DBGAUTHSTATUS_EL1_31_8,Reserved RES0." bitfld.long 0x18 6.--7. "SNID,Secure non-invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Non-secure. 10 Implemented and disabled." "0,1,2,3" newline bitfld.long 0x18 4.--5. "SID,Secure invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Non-secure. 10 Implemented and disabled." "0,1,2,3" bitfld.long 0x18 2.--3. "NSNID,Non-secure non-invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Secure. 10 Implemented and disabled." "0,1,2,3" newline bitfld.long 0x18 0.--1. "NSID,Non-secure invasive debug. Possible values of this field are: 00 Not implemented. EL3 is not implemented and the processor is Secure. 10 Implemented and disabled." "0,1,2,3" line.long 0x1C "APBADDR_DBG_CPU3_EDDEVARCH,External Debug Device Architecture Register" hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For debug this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A." "0,1" newline hexmask.long.byte 0x1C 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For debug the revision defined by v8-A is 0x0.All other values are reserved." hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For debug:Bits [15:12] are the architecture version 0x6.Bits [11:0] are the architecture part number 0xA15.This corresponds to debug.." line.long 0x20 "APBADDR_DBG_CPU3_EDDEVID2,External Debug Device ID Register 2" hexmask.long 0x20 0.--31. 1. "RES0_EDDEVID2_31_0,Reserved RES0." line.long 0x24 "APBADDR_DBG_CPU3_EDDEVID1,External Debug Device ID Register 1" hexmask.long 0x24 4.--31. 1. "RES0_EDDEVID1_31_4,Reserved RES0." hexmask.long.byte 0x24 0.--3. 1. "PCSROFFSET,This field indicates the offset applied to PC samples returned by reads of EDPCSR. Permitted values of this field in v8-A are: 0000 EDPCSR not implemented. 0010 EDPCSR implemented and.." line.long 0x28 "APBADDR_DBG_CPU3_EDDEVID,External Debug Device ID Register 0" hexmask.long.byte 0x28 28.--31. 1. "RES0_EDDEVID_31_28,Reserved RES0." hexmask.long.byte 0x28 24.--27. 1. "AUXREGS,Indicates support for Auxiliary registers. Permitted values for this field are: 0000 None supported. 0001 Support for External Debug Auxiliary Control Register EDACR. All.." newline hexmask.long.tbyte 0x28 4.--23. 1. "RES0_EDDEVID_23_4,Reserved RES0." hexmask.long.byte 0x28 0.--3. 1. "PCSAMPLE,Indicates the level of Sample-based profiling support using external debug registers 40 through 43. Permitted values of this field in v8-A are: 0000 Architecture-defined form of Sample-based profiling not implemented." line.long 0x2C "APBADDR_DBG_CPU3_EDDEVTYPE,External Debug Device Type Register" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_EDDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x2C 4.--7. 1. "SUB,Subtype. Must read as 0x1 to indicate this is a processor component." newline hexmask.long.byte 0x2C 0.--3. 1. "MAJOR,Major type. Must read as 0x5 to indicate this is a debug logic component." line.long 0x30 "APBADDR_DBG_CPU3_EDPIDR4,External Debug Peripheral Identification Register 4" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_EDPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x30 4.--7. 1. "SIZE,Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers." newline hexmask.long.byte 0x30 0.--3. 1. "DES_2,Designer JEP106 continuation code least significant nibble. For ARM Limited this field is 0b0100." group.long 0xFE0++0x1F line.long 0x0 "APBADDR_DBG_CPU3_EDPIDR0,External Debug Peripheral Identification Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_EDPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x0 0.--7. 1. "PART_0,Part number least significant byte." line.long 0x4 "APBADDR_DBG_CPU3_EDPIDR1,External Debug Peripheral Identification Register 1" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_EDPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x4 4.--7. 1. "DES_0,Designer least significant nibble of JEP106 ID code. For ARM Limited this field is 0b1011." newline hexmask.long.byte 0x4 0.--3. 1. "PART_1,Part number most significant nibble." line.long 0x8 "APBADDR_DBG_CPU3_EDPIDR2,External Debug Peripheral Identification Register 2" hexmask.long.tbyte 0x8 8.--31. 1. "RES0_EDPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x8 4.--7. 1. "REVISION,Part major revision. Parts can also use this field to extend Part number to 16-bits." newline bitfld.long 0x8 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" bitfld.long 0x8 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0xC "APBADDR_DBG_CPU3_EDPIDR3,External Debug Peripheral Identification Register 3" hexmask.long.tbyte 0xC 8.--31. 1. "RES0_EDPIDR3_31_8,Reserved RES0." hexmask.long.byte 0xC 4.--7. 1. "REVAND,Part minor revision. Parts using EDPIDR2.REVISION as an extension to the Part number must use this field as a major revision number." newline hexmask.long.byte 0xC 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x10 "APBADDR_DBG_CPU3_EDCIDR0,External Debug Component Identification Register 0" hexmask.long.tbyte 0x10 8.--31. 1. "RES0_EDCIDR0_31_8,Reserved RES0." hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x14 "APBADDR_DBG_CPU3_EDCIDR1,External Debug Component Identification Register 1" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_EDCIDR1_31_8,Reserved RES0." hexmask.long.byte 0x14 4.--7. 1. "CLASS,Component class. Reads as 0x9 debug component." newline hexmask.long.byte 0x14 0.--3. 1. "PRMBL_1,Preamble. RAZ." line.long 0x18 "APBADDR_DBG_CPU3_EDCIDR2,External Debug Component Identification Register 2" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDCIDR2_31_8,Reserved RES0." hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x1C "APBADDR_DBG_CPU3_EDCIDR3,External Debug Component Identification Register 3" hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_EDCIDR3_31_8,Reserved RES0." hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree "A53SS0_CORE3_ECC_AGGR" base ad:0x719000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_CORE3_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_CORE3_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_CORE3_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR_CORE3_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_CORE3_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_CORE3_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 26. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 25. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 24. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 23. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_CORE3_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 26. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_CORE3_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 26. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_CORE3_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_CORE3_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 26. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 25. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 24. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 23. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_CORE3_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 26. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_CORE3_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 26. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 25. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 24. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 23. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_CORE3_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_CORE3_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_CORE3_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_CORE3_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "A53SS0_CORE3_ETM" base ad:0x730330000 group.long 0x4++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCPRGCTLR,Programming Control Register" hexmask.long 0x0 1.--31. 1. "RES0_TRCPRGCTLR_31_1,Reserved RES0." bitfld.long 0x0 0. "EN,Trace unit enable bit. Possible values are: 0 The trace unit is disabled. All trace resources are inactive and no trace is generated. 1 The trace unit is enabled." "0,1" group.long 0xC++0x7 line.long 0x0 "APBADDR_ETM_CPU3_TRCSTATR,Status Register" hexmask.long 0x0 2.--31. 1. "RES0_TRCSTATR_31_2,Reserved RES0." bitfld.long 0x0 1. "PMSTABLE,Programmer's model stable bit: 0 The programmer's model is not stable. 1 The programmer's model is stable. When polled the trace unit trace registers return stable data." "0,1" bitfld.long 0x0 0. "IDLE,Idle status bit: 0 The trace unit is not idle. 1 The trace unit is idle. The trace unit is idle when all of the following are true:TRCPRGCTLR.EN==0 or the OS Lock is.." "0,1" line.long 0x4 "APBADDR_ETM_CPU3_TRCCONFIGR,Trace Configuration Register" hexmask.long.word 0x4 18.--31. 1. "RES0_TRCCONFIGR_31_18,Reserved RES0." bitfld.long 0x4 17. "DV,Data value tracing bit: 0 Data value tracing is disabled. 1 Data value tracing is enabled when INSTP0 is not 0b00. TRCIDR0.TRCDATA indicates whether this bit is supported. If.." "0,1" bitfld.long 0x4 16. "DA,Data address tracing bit: 0 Data address tracing is disabled. 1 Data address tracing is enabled when INSTP0 is not 0b00. TRCIDR0.TRCDATA indicates whether this bit is.." "0,1" newline bitfld.long 0x4 15. "RES0_TRCCONFIGR_15_15,Reserved RES0." "0,1" bitfld.long 0x4 13.--14. "QE,Q element enable field: 00 Q elements are disabled. 01 Q elements with instruction counts are enabled. Q elements without instruction counts are disabled. 11.." "0,1,2,3" bitfld.long 0x4 12. "RS,Return stack enable bit. 0 Return stack is disabled. 1 Return stack is enabled. TRCIDR0.RETSTACK indicates whether this bit is supported. If it is not supported then this bit.." "0,1" newline bitfld.long 0x4 11. "TS,Global timestamp tracing bit: 0 Global timestamp tracing is disabled. 1 Global timestamp tracing is enabled. TRCTSCTLR controls the insertion of timestamps in the trace." "0,1" bitfld.long 0x4 8.--10. "COND,Conditional instruction tracing bit. The permitted values are: 000 Conditional instruction tracing is disabled. 001 Conditional load instructions are traced. 010.." "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "VMID,VMID tracing bit: 0 VMID tracing is disabled. 1 VMID tracing is enabled. TRCIDR2.VMIDSIZE indicates whether this bit is supported. If it is not supported then this bit is RES0." "0,1" newline bitfld.long 0x4 6. "CID,Context ID tracing bit: 0 Context ID tracing is disabled. 1 Context ID tracing is enabled. TRCIDR2.CIDSIZE indicates whether this bit is supported. If it is not supported then.." "0,1" bitfld.long 0x4 5. "RES0_TRCCONFIGR_5_5,Reserved RES0." "0,1" bitfld.long 0x4 4. "CCI,Cycle counting instruction trace bit: 0 Cycle counting in the instruction trace is disabled. 1 Cycle counting in the instruction trace is enabled. TRCCCCTLR controls the threshold value for.." "0,1" newline bitfld.long 0x4 3. "BB,Branch broadcast mode bit: 0 Branch broadcast mode is disabled. 1 Branch broadcast mode is enabled. TRCBBCTLR controls which regions of memory are enabled to use branch broadcasting." "0,1" bitfld.long 0x4 1.--2. "INSTP0,Instruction P0 bit. This field controls whether load and store instructions are traced as P0 instructions: 00 Do not trace load and store instructions as P0 instructions. 01 Trace load.." "0,1,2,3" bitfld.long 0x4 0. "RES1_TRCCONFIGR_0_0,Reserved RES1." "0,1" group.long 0x18++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCAUXCTLR,Auxiliary Control Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_TRCAUXCTLR_31_8,Reserved RES0" bitfld.long 0x0 7. "COREIFEN,Keep core interface enabled regardless of trace enable register state" "0,1" bitfld.long 0x0 6. "RES0_TRCAUXCTLR_6_6,Reserved RES0" "0,1" newline bitfld.long 0x0 5. "AUTHNOFLUSH,Do not flush trace on de-assertion of authentication inputs. When this bit is set to 1 the trace unit behavior deviates from architecturally-specified behavior." "0,1" bitfld.long 0x0 4. "TSNODELAY,Do not delay timestamp insertion based on FIFO depth." "0,1" bitfld.long 0x0 3. "SYNCDELAY,Delay periodic synchronization if FIFO is more than half-full." "0,1" newline bitfld.long 0x0 2. "OVFLW,Force an overflow if synchronization is not completed when second synchronization becomes due. When this bit is set to 1 the trace unit behavior deviates from architecturally-specified behavior." "0,1" bitfld.long 0x0 1. "IDLEACK,Force idle-drain acknowledge high CPU does not wait for trace to drain before entering WFX state. When this bit is set to 1 trace unit behavior deviates from architecturally-specified behavior." "0,1" bitfld.long 0x0 0. "AFREADY,Always respond to AFREADY immediately. Does not have any interaction with FIFO draining even in WFI state." "0,1" group.long 0x20++0x7 line.long 0x0 "APBADDR_ETM_CPU3_TRCEVENTCTL0R,Event Control 0 Register" bitfld.long 0x0 31. "TYPE3,Selects the resource type for trace event 3" "0,1" bitfld.long 0x0 28.--30. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--27. 1. "SEL3,Selects the resource number based on the value of TYPE3" newline bitfld.long 0x0 23. "TYPE2,Selects the resource type for trace event 2" "0,1" bitfld.long 0x0 20.--22. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--19. 1. "SEL2,Selects the resource number based on the value of TYPE2" newline bitfld.long 0x0 15. "TYPE1,Selects the resource type for trace event 1" "0,1" bitfld.long 0x0 12.--14. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "SEL1,Selects the resource number based on the value of TYPE1" newline bitfld.long 0x0 7. "TYPE0,Selects the resource type for trace event 0" "0,1" bitfld.long 0x0 4.--6. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "SEL0,Selects the resource number based on the value of TYPE0" line.long 0x4 "APBADDR_ETM_CPU3_TRCEVENTCTL1R,Event Control 1 Register" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved RES0" bitfld.long 0x4 12. "LPOVERRIDE,Low power state behavior override" "0,1" bitfld.long 0x4 11. "ATB,ATB trigger enable" "0,1" newline hexmask.long.byte 0x4 4.--10. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "EN,One bit per event to enable generation of an event element in the instruction trace stream when the selected event occurs" group.long 0x2C++0x17 line.long 0x0 "APBADDR_ETM_CPU3_TRCSTALLCTLR,Stall Control Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved RES0" bitfld.long 0x0 8. "ISTALL,Controls if the trace unit can stall the processor when the instruction trace buffer space is less than LEVEL" "0,1" hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved RES0" newline bitfld.long 0x0 2.--3. "LEVEL,The field can support 4 monotonic levels from 0b00 to 0b11" "0,1,2,3" bitfld.long 0x0 0.--1. "RESERVED,Reserved RES0" "0,1,2,3" line.long 0x4 "APBADDR_ETM_CPU3_TRCTSCTLR,Global Timestamp Control Register" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_TRCTSCTLR_31_8,Reserved RES0." hexmask.long.byte 0x4 0.--7. 1. "EVENT,An event selector. When the selected event is triggered the trace unit inserts a global timestamp into the trace streams." line.long 0x8 "APBADDR_ETM_CPU3_TRCSYNCPR,Synchronization Period Register" hexmask.long 0x8 5.--31. 1. "RES0_TRCSYNCPR_31_5,Reserved RES0." hexmask.long.byte 0x8 0.--4. 1. "PERIOD,Controls how many bytes of trace the sum of instruction and data that a trace unit can generate before a periodic trace synchronization request occurs. The number of bytes is always a power of two and the permitted values are: 00000.." line.long 0xC "APBADDR_ETM_CPU3_TRCCCCTLR,Cycle Count Control Register" hexmask.long.tbyte 0xC 12.--31. 1. "RES0_TRCCCCTLR_31_12,Reserved RES0." hexmask.long.word 0xC 0.--11. 1. "THRESHOLD,Sets the threshold value for instruction trace cycle counting.The minimum threshold value that can be programmed into THRESHOLD is given in TRCIDR3.CCITMIN.Writing a value of zero might cause UNPREDICTABLE behaviour." line.long 0x10 "APBADDR_ETM_CPU3_TRCBBCTLR,Branch Broadcast Control Register" hexmask.long.tbyte 0x10 9.--31. 1. "RES0_TRCBBCTLR_31_9,Reserved RES0." bitfld.long 0x10 8. "MODE,Mode bit: 0 Exclude mode. Branch broadcasting is not enabled in the address range that RANGE defines. If RANGE==0 then branch broadcasting is enabled for the entire memory map. 1 Include mode." "0,1" hexmask.long.byte 0x10 0.--7. 1. "RANGE,Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each bit represents an address range comparator pair so bit[n] controls the selection of address range comparator pair n. If bit[n] is: 0.." line.long 0x14 "APBADDR_ETM_CPU3_TRCTRACEIDR,Trace ID Register" hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x14 0.--6. 1. "TRACEID,Trace ID value. When only instruction tracing is enabled this provides the trace ID." group.long 0x80++0xB line.long 0x0 "APBADDR_ETM_CPU3_TRCVICTLR,ViewInst Main Control Register" hexmask.long.byte 0x0 24.--31. 1. "RES0_TRCVICTLR_31_24,Reserved RES0." hexmask.long.byte 0x0 20.--23. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Non-secure state for exception level n." hexmask.long.byte 0x0 16.--19. 1. "EXLEVEL_S,In Secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Secure state for exception level n. 1.." newline hexmask.long.byte 0x0 12.--15. 1. "RES0_TRCVICTLR_15_12,Reserved RES0." bitfld.long 0x0 11. "TRCERR,If TRCIDR3.TRCERR==1 this bit controls whether a trace unit must trace a system error exception: 0 The trace unit does not trace a system error exception unless it traces the exception or instruction immediately prior to the.." "0,1" bitfld.long 0x0 10. "TRCRESET,Controls whether a trace unit must trace a Reset exception: 0 The trace unit does not trace a Reset exception unless it traces the exception or instruction immediately prior to the Reset exception. 1.." "0,1" newline bitfld.long 0x0 9. "SSSTATUS,IF TRCIDR4.NUMACPAIRS>0 or TRCIDR.NUMPC>0 this bit returns the status of the start-stop logic: 0 The start-stop logic is in the stopped state. 1 The start-stop logic is in the started.." "0,1" bitfld.long 0x0 8. "RES0_TRCVICTLR_8_8,Reserved RES0." "0,1" hexmask.long.byte 0x0 0.--7. 1. "EVENT,An event selector. [TODO: Add the bit assignments for EVENT fields into the descriptions directly?]" line.long 0x4 "APBADDR_ETM_CPU3_TRCVIIECTLR,ViewInst Include-Exclude Control Register" hexmask.long.byte 0x4 24.--31. 1. "RES0_TRCVIIECTLR_31_24,Reserved RES0." hexmask.long.byte 0x4 16.--23. 1. "EXCLUDE,0 1 The implemented width of the field n is IMPLEMENTATION DEFINED and is set by the value of TRCIDR4.NUMACPAIRS. Unimplemented bits are RAZ/WI." hexmask.long.byte 0x4 8.--15. 1. "RES0_TRCVIIECTLR_15_8,Reserved RES0." newline hexmask.long.byte 0x4 0.--7. 1. "INCLUDE,Include range field. Selects which address range comparator pairs are in use with ViewInst include control. Each bit represents an address range comparator pair so bit[m] controls the selection of address range comparator pair m. If bit[m] is:.." line.long 0x8 "APBADDR_ETM_CPU3_TRCVISSCTLR,ViewInst Start-Stop Control Register" hexmask.long.word 0x8 16.--31. 1. "STOP,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of stopping trace. Each bit represents a single address comparator so bit[m] controls the selection of single address comparator m-16. If bit[m].." hexmask.long.word 0x8 0.--15. 1. "START,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of starting trace. Each bit represents a single address comparator so bit[n] controls the selection of single address comparator n. If bit[n] is:.." group.long 0x100++0xB line.long 0x0 "APBADDR_ETM_CPU3_TRCSEQEVR0,Sequencer State Transition Control Registers 0" hexmask.long.word 0x0 16.--31. 1. "RES0_TRCSEQEVR0_31_16,Reserved RES0." hexmask.long.byte 0x0 8.--15. 1. "B_N,Backward field. Contains an event number. When the event occurs then the sequencer state moves from state n+1 to state n.For example for TRCSEQEVR2 if B2==0x14 then when event 0x14 occurs the sequencer moves from state 3 to state 2." hexmask.long.byte 0x0 0.--7. 1. "F_N,Forward field. Contains an event number. When the event occurs then the sequencer state moves from state n to state n+1.For example for TRCSEQEVR1 if F1==0x12 then when event 0x12 occurs the sequencer moves from state 1 to state 2." line.long 0x4 "APBADDR_ETM_CPU3_TRCSEQEVR1,Sequencer State Transition Control Registers 1" hexmask.long.word 0x4 16.--31. 1. "RES0_TRCSEQEVR1_31_16,Reserved RES0." hexmask.long.byte 0x4 8.--15. 1. "B_N,Backward field. Contains an event number. When the event occurs then the sequencer state moves from state n+1 to state n.For example for TRCSEQEVR2 if B2==0x14 then when event 0x14 occurs the sequencer moves from state 3 to state 2." hexmask.long.byte 0x4 0.--7. 1. "F_N,Forward field. Contains an event number. When the event occurs then the sequencer state moves from state n to state n+1.For example for TRCSEQEVR1 if F1==0x12 then when event 0x12 occurs the sequencer moves from state 1 to state 2." line.long 0x8 "APBADDR_ETM_CPU3_TRCSEQEVR2,Sequencer State Transition Control Registers 2" hexmask.long.word 0x8 16.--31. 1. "RES0_TRCSEQEVR2_31_16,Reserved RES0." hexmask.long.byte 0x8 8.--15. 1. "B_N,Backward field. Contains an event number. When the event occurs then the sequencer state moves from state n+1 to state n.For example for TRCSEQEVR2 if B2==0x14 then when event 0x14 occurs the sequencer moves from state 3 to state 2." hexmask.long.byte 0x8 0.--7. 1. "F_N,Forward field. Contains an event number. When the event occurs then the sequencer state moves from state n to state n+1.For example for TRCSEQEVR1 if F1==0x12 then when event 0x12 occurs the sequencer moves from state 1 to state 2." group.long 0x118++0xB line.long 0x0 "APBADDR_ETM_CPU3_TRCSEQRSTEVR,Sequencer Reset Control Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_TRCSEQRSTEVR_31_8,Reserved RES0." hexmask.long.byte 0x0 0.--7. 1. "RST,Contains an event number. When the event occurs then the sequencer state moves to state 0." line.long 0x4 "APBADDR_ETM_CPU3_TRCSEQSTR,Sequencer State Register" hexmask.long 0x4 2.--31. 1. "RES0_TRCSEQSTR_31_2,Reserved RES0." bitfld.long 0x4 0.--1. "STATE,Sets or returns the state of the sequencer: 00 State 0. 01 State 1. 10 State 2. 11 State 3." "0,1,2,3" line.long 0x8 "APBADDR_ETM_CPU3_TRCEXTINSELR,External Input Select Register" bitfld.long 0x8 29.--31. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "SEL3,Selects an event from the external input bus for External Input Resource 3." bitfld.long 0x8 21.--23. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 16.--20. 1. "SEL2,Selects an event from the external input bus for External Input Resource 2" bitfld.long 0x8 13.--15. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--12. 1. "SEL1,Selects an event from the external input bus for External Input Resource 1" newline bitfld.long 0x8 5.--7. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--4. 1. "SEL0,Selects an event from the external input bus for External Input Resource 0" group.long 0x140++0x7 line.long 0x0 "APBADDR_ETM_CPU3_TRCCNTRLDVR0,Counter Reload Value Registers 0" hexmask.long.word 0x0 16.--31. 1. "RES0_TRCCNTRLDVR0_31_16,Reserved RES0." hexmask.long.word 0x0 0.--15. 1. "VALUE_N,Contains the reload value for counter . When a reload event occurs for counter then the trace unit copies the VALUE field into counter ." line.long 0x4 "APBADDR_ETM_CPU3_TRCCNTRLDVR1,Counter Reload Value Registers 1" hexmask.long.word 0x4 16.--31. 1. "RES0_TRCCNTRLDVR1_31_16,Reserved RES0." hexmask.long.word 0x4 0.--15. 1. "VALUE_N,Contains the reload value for counter . When a reload event occurs for counter then the trace unit copies the VALUE field into counter ." group.long 0x150++0x7 line.long 0x0 "APBADDR_ETM_CPU3_TRCCNTCTLR0,Counter Control Register 0" hexmask.long.word 0x0 18.--31. 1. "RES0_TRCCNTCTLR0_31_18,Reserved RES0." bitfld.long 0x0 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter decrements when a reload event occurs for counter : 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit.." "0,1" bitfld.long 0x0 16. "RLDSELF_N,Controls whether a reload event occurs for counter when counter reaches zero: 0 The trace unit does not generate a reload event. 1 The trace unit generates a reload event for.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter ." hexmask.long.byte 0x0 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter to decrement." line.long 0x4 "APBADDR_ETM_CPU3_TRCCNTCTLR1,Counter Control Register 1" hexmask.long.word 0x4 18.--31. 1. "RES0_TRCCNTCTLR1_31_18,Reserved RES0." bitfld.long 0x4 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter decrements when a reload event occurs for counter : 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit.." "0,1" bitfld.long 0x4 16. "RLDSELF_N,Controls whether a reload event occurs for counter when counter reaches zero: 0 The trace unit does not generate a reload event. 1 The trace unit generates a reload event for.." "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter ." hexmask.long.byte 0x4 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter to decrement." group.long 0x160++0x7 line.long 0x0 "APBADDR_ETM_CPU3_TRCCNTVR0,Counter Value Registers 0" hexmask.long.word 0x0 16.--31. 1. "RES0_TRCCNTVR0_31_16,Reserved RES0." hexmask.long.word 0x0 0.--15. 1. "VALUE_N,Contains the count value of counter ." line.long 0x4 "APBADDR_ETM_CPU3_TRCCNTVR1,Counter Value Registers 1" hexmask.long.word 0x4 16.--31. 1. "RES0_TRCCNTVR1_31_16,Reserved RES0." hexmask.long.word 0x4 0.--15. 1. "VALUE_N,Contains the count value of counter ." group.long 0x180++0x17 line.long 0x0 "APBADDR_ETM_CPU3_TRCIDR8,ID Register 8" hexmask.long 0x0 0.--31. 1. "MAXSPEC,Indicates the maximum speculation depth of the instruction trace stream. This is the maximum number of P0 elements in the trace stream that can be speculative at any time." line.long 0x4 "APBADDR_ETM_CPU3_TRCIDR9,ID Register 9" hexmask.long 0x4 0.--31. 1. "NUMP0KEY,Indicates the number of P0 right-hand keys that the trace unit can use. A value of 0 or 1 indicates one P0 key." line.long 0x8 "APBADDR_ETM_CPU3_TRCIDR10,ID Register 10" hexmask.long 0x8 0.--31. 1. "NUMP1KEY,Indicates the number of P1 right-hand keys that the trace unit can use. The number includes normal and special keys." line.long 0xC "APBADDR_ETM_CPU3_TRCIDR11,ID Register 11" hexmask.long 0xC 0.--31. 1. "NUMP1SPC,Indicates the number of special P1 right-hand keys that the trace unit can use." line.long 0x10 "APBADDR_ETM_CPU3_TRCIDR12,ID Register 12" hexmask.long 0x10 0.--31. 1. "NUMCONDKEY,Indicates the number of conditional instruction right-hand keys that the trace unit can use. The number includes normal and special keys." line.long 0x14 "APBADDR_ETM_CPU3_TRCIDR13,ID Register 13" hexmask.long 0x14 0.--31. 1. "NUMCONDSPC,Indicates the number of special conditional instruction right-hand keys that the trace unit can use." group.long 0x1C0++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCIMSPEC0,Implementation Specific Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_TRCIMSPEC0_31_8,Reserved RES0." hexmask.long.byte 0x0 4.--7. 1. "EN,If SUPPORT is not 0b0000 controls whether the IMPLEMENTATION DEFINED features are enabled. The permitted values are: 0000 The IMPLEMENTATION DEFINED features are not enabled. The trace unit must behave as if the IMPLEMENTATION.." hexmask.long.byte 0x0 0.--3. 1. "SUPPORT,Indicates whether the implementation supports IMPLEMENTATION DEFINED features. The permitted values are: 0000 No IMPLEMENTATION DEFINED features are supported. The EN field is RES0. and any other value which.." group.long 0x1E0++0x17 line.long 0x0 "APBADDR_ETM_CPU3_TRCIDR0,ID Register 0" bitfld.long 0x0 30.--31. "RES0_TRCIDR0_31_30,Reserved RES0." "0,1,2,3" bitfld.long 0x0 29. "COMMOPT,Conditional instruction tracing support bit. Indicates if the trace unit supports conditional instruction tracing: 0 Conditional instruction tracing is not supported. 1 Conditional.." "0,1" hexmask.long.byte 0x0 24.--28. 1. "TSSIZE,Global timestamp size field. The permitted values are: 00000 Global timestamping is not implemented. 00110 Implementation supports a maximum global timestamp of 48bits." newline hexmask.long.byte 0x0 17.--23. 1. "RES0_TRCIDR0_23_17,Reserved RES0." bitfld.long 0x0 15.--16. "QSUPP,Q element support field. The permitted values are: 00 Q element support is not implemented. TRCCONFIGR.QE is RES0. 01 Q element support is implemented and only supports Q elements with.." "0,1,2,3" bitfld.long 0x0 14. "QFILT,Q element filtering support field. The permitted values are: 0 Q element filtering is not implemented. 1 Q element filtering is implemented. TRCQCTLR is implemented. When.." "0,1" newline bitfld.long 0x0 12.--13. "CONDTYPE,Conditional tracing field. The permitted values are: 00 The trace unit indicates only if a conditional instruction is a pass or fail. 01 The trace unit provides the Current Program Status.." "0,1,2,3" bitfld.long 0x0 10.--11. "NUMEVENT,Number of events field. Indicates how many events the trace unit supports: 00 The trace unit supports 1 event. 01 The trace unit supports 2 events. 10.." "0,1,2,3" bitfld.long 0x0 9. "RETSTACK,Return stack bit. Indicates if the implementation supports a return stack: 0 Return stack is not implemented. 1 Return stack is implemented so TRCCONFIGR.RS is supported." "0,1" newline bitfld.long 0x0 8. "RES0_TRCIDR0_8_8,Reserved RES0." "0,1" bitfld.long 0x0 7. "TRCCCI,Cycle counting instruction bit. Indicates if the trace unit supports cycle counting for instructions: 0 Cycle counting in the instruction trace is not implemented. 1 Cycle counting in the.." "0,1" bitfld.long 0x0 6. "TRCCOND,Conditional instruction tracing support bit. Indicates if the trace unit supports conditional instruction tracing: 0 Conditional instruction tracing is not supported. 1 Conditional.." "0,1" newline bitfld.long 0x0 5. "TRCBB,Branch broadcast tracing support bit. Indicates if the trace unit supports branch broadcast tracing: 0 Branch broadcast tracing is not supported. 1 Branch broadcast tracing is supported so.." "0,1" bitfld.long 0x0 3.--4. "TRCDATA,Conditional tracing field. The permitted values are: 00 Data tracing is not supported. 11 Tracing of data addresses and data values is supported so TRCCONFIGR.DA TRCCONFIGR.DV .." "0,1,2,3" bitfld.long 0x0 1.--2. "INSTP0,P0 tracing support field. The permitted values are: 00 Tracing of load and store instructions as P0 elements is not supported. 11 Tracing of load and store instructions as P0 elements is.." "0,1,2,3" newline bitfld.long 0x0 0. "RES0_TRCIDR0_0_0,Reserved RES0." "0,1" line.long 0x4 "APBADDR_ETM_CPU3_TRCIDR1,ID Register 1" hexmask.long.byte 0x4 24.--31. 1. "DESIGNER,Indicates which company designed the trace unit. The permitted values are: 01000001 ARM Limited. 01000100 Digital Equipment Corporation. 01001101.." hexmask.long.byte 0x4 16.--23. 1. "RES0_TRCIDR1_23_16,Reserved RES0." hexmask.long.byte 0x4 12.--15. 1. "RES1_TRCIDR1_15_12,Reserved RES1." newline hexmask.long.byte 0x4 8.--11. 1. "TRCARCHMAJ,Indicates the major version of the ETM architecture. The permitted value is: 100 ETMv4. All other values are reserved." hexmask.long.byte 0x4 4.--7. 1. "TRCARCHMIN,Indicates the minor version of the ETM architecture. The permitted value is: 0 ETMv4 minor version 0. All other values are reserved." hexmask.long.byte 0x4 0.--3. 1. "REVISION,Returns an IMPLEMENTATION DEFINED value that identifies the revision of the trace registers and the OS Save and Restore registers.ARM recommends:That the initial implementation sets REVISION==0x0 and the field then increments for any subsequent.." line.long 0x8 "APBADDR_ETM_CPU3_TRCIDR2,ID Register 2" bitfld.long 0x8 29.--31. "RES0_TRCIDR2_31_29,Reserved RES0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 25.--28. 1. "CCSIZE,Indicates the size of the cycle counter in bits minus 12. 0000 The cycle counter is 12 bits in length. 0001 The cycle counter is 13 bits in length. and so on up to 0b1000 .." hexmask.long.byte 0x8 20.--24. 1. "DVSIZE,Indicates the data value size in bytes. The permitted values are: 00000 Data value tracing is not supported. Therefore an implementation must also set TRCIDR0.TRCDATA==0b00. 00100 Maximum.." newline hexmask.long.byte 0x8 15.--19. 1. "DASIZE,Indicates the data address size in bytes. The permitted values are: 00000 Data address tracing is not supported. Therefore an implementation must also set TRCIDR0.TRCDATA==0b00. 00100.." hexmask.long.byte 0x8 10.--14. 1. "VMIDSIZE,Indicates the VMID size. The permitted values are: 00000 VMID tracing is not supported. 00001 Maximum of 8-bit VMID size so TRCCONFIGR.VMID is supported. All other.." hexmask.long.byte 0x8 5.--9. 1. "CIDSIZE,Indicates the Context ID size. The permitted values are: 00000 Context ID tracing is not supported. 00100 Maximum of 32-bit Context ID size so TRCCONFIGR.CID is supported." newline hexmask.long.byte 0x8 0.--4. 1. "IASIZE,Indicates the instruction address size. The permitted values are: 00100 Maximum of 32-bit address size. 01000 Maximum of 64-bit address size. All other values are reserved." line.long 0xC "APBADDR_ETM_CPU3_TRCIDR3,ID Register 3" bitfld.long 0xC 31. "NOOVERFLOW,Indicates if TRCSTALLCTLR.NOOVERFLOW is supported: 0 TRCSTALLCTLR.NOOVERFLOW is not supported or STALLCTL==0. 1 TRCSTALLCTLR.NOOVERFLOW is supported." "0,1" bitfld.long 0xC 28.--30. "NUMPROC,Indicates the number of processors available for tracing. The possible values are: 000 The trace unit can trace one processor. 001 The trace unit can trace two processors." "0,1,2,3,4,5,6,7" bitfld.long 0xC 27. "SYSSTALL,Indicates if the implementation can support stall control: 0 The system does not support stall control of the processor. 1 The system can support stall control of the processor." "0,1" newline bitfld.long 0xC 26. "STALLCTL,Indicates if TRCSTALLCTLR is supported: 0 TRCSTALLCTLR is not supported. 1 TRCSTALLCTLR is supported." "0,1" bitfld.long 0xC 25. "SYNCPR,Indicates if an implementation has a fixed synchronization period: 0 TRCSYNCPR is read-write so software can change the synchronization period. 1 TRCSYNCPR is read-only so the.." "0,1" bitfld.long 0xC 24. "TRCERR,Indicates if TRCVICTLR.TRCERR is supported: 0 TRCVICTLR.TRCERR is not supported 1 TRCVICTLR.TRCERR is supported." "0,1" newline hexmask.long.byte 0xC 20.--23. 1. "EXLEVEL_NS,In Non-secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Non-secure state exception level n is not supported so the corresponding bits in.." hexmask.long.byte 0xC 16.--19. 1. "EXLEVEL_S,In Secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Secure state exception level n is not supported so the corresponding bits in TRCACATRn.EXLEVEL_S and.." hexmask.long.byte 0xC 12.--15. 1. "RES0_TRCIDR3_15_12,Reserved RES0." newline hexmask.long.word 0xC 0.--11. 1. "CCITMIN,Indicates the minimum value that can be programmed in TRCCCCTLR.THRESHOLD.When cycle counting in the instruction trace is supported that is TRCIDR0.TRCCCI==1 then the minimum value of this field is 0x001 otherwise it is 0x000." line.long 0x10 "APBADDR_ETM_CPU3_TRCIDR4,ID Register 4" hexmask.long.byte 0x10 28.--31. 1. "NUMVMIDC,Indicates the number of VMID comparators that are available for tracing. The permitted values are: 0000 No VMID comparators are available. 0001 The implementation has one VMID comparator." hexmask.long.byte 0x10 24.--27. 1. "NUMCIDC,Indicates the number of Context ID comparators that are available for tracing. The permitted values are: 0000 No Context ID comparators are available. 0001 The implementation has one.." hexmask.long.byte 0x10 20.--23. 1. "NUMSSCC,Indicates the number of single-shot comparator controls that are available for tracing. The permitted values are: 0000 No single-shot comparator controls are available. 0001 The.." newline hexmask.long.byte 0x10 16.--19. 1. "NUMRSPAIR,Indicates the number of resource selection pairs that are available for tracing. The permitted values are: 0000 The implementation has one resource selection pair. 0001 The implementation.." hexmask.long.byte 0x10 12.--15. 1. "NUMPC,Indicates the number of processor comparator inputs that are available for tracing. The permitted values are: 0000 No processor comparator inputs are available. 0001 The implementation has.." bitfld.long 0x10 9.--11. "RES0_TRCIDR4_11_9,Reserved RES0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "SUPPDAC,Indicates if the implementation can support data address comparisons: 0 The implementation does not support data address comparisons. 1 The implementation can support data address comparisons" "0,1" hexmask.long.byte 0x10 4.--7. 1. "NUMDVC,Indicates the number of data value comparators that are available for tracing. The permitted values are: 0000 No data value comparators are available. 0001 The implementation has one data.." hexmask.long.byte 0x10 0.--3. 1. "NUMACPAIRS,Indicates the number of address comparator pairs that are available for tracing. The permitted values are: 0000 No address comparator pairs are available. 0001 The implementation has one.." line.long 0x14 "APBADDR_ETM_CPU3_TRCIDR5,ID Register 5" bitfld.long 0x14 31. "REDFUNCNTR,Indicates if the reduced function counter is implemented: 0 The reduced function counter is not supported. 1 Counter 0 is implemented as a reduced function counter." "0,1" bitfld.long 0x14 28.--30. "NUMCNTR,Indicates the number of counters that are available for tracing. The permitted values are: 000 No counters are available. 001 The implementation has one counter." "0,1,2,3,4,5,6,7" bitfld.long 0x14 25.--27. "NUMSEQSTATE,Indicates the number of sequencer states that are implemented. The permitted values are: 000 No sequencer states are implemented. 100 The implementation has four sequencer states." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 24. "RES0_TRCIDR5_24_24,Reserved RES0." "0,1" bitfld.long 0x14 23. "LPOVERRIDE,Indicates if the implementation can support low-power state override: 0 The implementation does not support low-power state override. 1 The implementation supports low-power state.." "0,1" bitfld.long 0x14 22. "ATBTRIG,Indicates if the implementation can support ATB triggers: 0 The implementation does not support ATB triggers. 1 The implementation supports ATB triggers and the TRCEVENTCTL1R.ATBTRIG field.." "0,1" newline hexmask.long.byte 0x14 16.--21. 1. "TRACEIDSIZE,Indicates the trace ID width. The permitted value is: 111 The implementation supports a 7-bit trace ID. This sets the width of the TRCTRACEIDR.TRACEID field. All other values are reserved.The CoreSight ATB.." hexmask.long.byte 0x14 12.--15. 1. "RES0_TRCIDR5_15_12,Reserved RES0." bitfld.long 0x14 9.--11. "NUMEXTINSEL,Indicates how many external input select resources are implemented. The permitted values are: 000 No external input select resources are available. If NUMEXTINSEL is zero NUMEXTIN must also be zero." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 0.--8. 1. "NUMEXTIN,Indicates how many external inputs are implemented. The permitted values are: 000000000 No external inputs are available. If NUMEXTIN is zero NUMEXTINSEL must also be zero. 000000001 The.." group.long 0x208++0x37 line.long 0x0 "APBADDR_ETM_CPU3_TRCRSCTLR2,Resource Selection Control Registers 2" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCRSCTLR2_31_22,Reserved RES0." bitfld.long 0x0 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x0 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x0 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x4 "APBADDR_ETM_CPU3_TRCRSCTLR3,Resource Selection Control Registers 3" hexmask.long.word 0x4 22.--31. 1. "RES0_TRCRSCTLR3_31_22,Reserved RES0." bitfld.long 0x4 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x4 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x4 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x4 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x8 "APBADDR_ETM_CPU3_TRCRSCTLR4,Resource Selection Control Registers 4" hexmask.long.word 0x8 22.--31. 1. "RES0_TRCRSCTLR4_31_22,Reserved RES0." bitfld.long 0x8 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x8 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x8 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0xC "APBADDR_ETM_CPU3_TRCRSCTLR5,Resource Selection Control Registers 5" hexmask.long.word 0xC 22.--31. 1. "RES0_TRCRSCTLR5_31_22,Reserved RES0." bitfld.long 0xC 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0xC 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0xC 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0xC 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x10 "APBADDR_ETM_CPU3_TRCRSCTLR6,Resource Selection Control Registers 6" hexmask.long.word 0x10 22.--31. 1. "RES0_TRCRSCTLR6_31_22,Reserved RES0." bitfld.long 0x10 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x10 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x10 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x14 "APBADDR_ETM_CPU3_TRCRSCTLR7,Resource Selection Control Registers 7" hexmask.long.word 0x14 22.--31. 1. "RES0_TRCRSCTLR7_31_22,Reserved RES0." bitfld.long 0x14 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x14 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x14 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x14 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x18 "APBADDR_ETM_CPU3_TRCRSCTLR8,Resource Selection Control Registers 8" hexmask.long.word 0x18 22.--31. 1. "RES0_TRCRSCTLR8_31_22,Reserved RES0." bitfld.long 0x18 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x18 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x18 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x18 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x1C "APBADDR_ETM_CPU3_TRCRSCTLR9,Resource Selection Control Registers 9" hexmask.long.word 0x1C 22.--31. 1. "RES0_TRCRSCTLR9_31_22,Reserved RES0." bitfld.long 0x1C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x1C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x1C 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x1C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x20 "APBADDR_ETM_CPU3_TRCRSCTLR10,Resource Selection Control Registers 10" hexmask.long.word 0x20 22.--31. 1. "RES0_TRCRSCTLR10_31_22,Reserved RES0." bitfld.long 0x20 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x20 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x20 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x20 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x24 "APBADDR_ETM_CPU3_TRCRSCTLR11,Resource Selection Control Registers 11" hexmask.long.word 0x24 22.--31. 1. "RES0_TRCRSCTLR11_31_22,Reserved RES0." bitfld.long 0x24 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x24 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x24 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x24 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x28 "APBADDR_ETM_CPU3_TRCRSCTLR12,Resource Selection Control Registers 12" hexmask.long.word 0x28 22.--31. 1. "RES0_TRCRSCTLR12_31_22,Reserved RES0." bitfld.long 0x28 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x28 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x28 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x28 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x2C "APBADDR_ETM_CPU3_TRCRSCTLR13,Resource Selection Control Registers 13" hexmask.long.word 0x2C 22.--31. 1. "RES0_TRCRSCTLR13_31_22,Reserved RES0." bitfld.long 0x2C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x2C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x2C 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x2C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x30 "APBADDR_ETM_CPU3_TRCRSCTLR14,Resource Selection Control Registers 14" hexmask.long.word 0x30 22.--31. 1. "RES0_TRCRSCTLR14_31_22,Reserved RES0." bitfld.long 0x30 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x30 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x30 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x30 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." line.long 0x34 "APBADDR_ETM_CPU3_TRCRSCTLR15,Resource Selection Control Registers 15" hexmask.long.word 0x34 22.--31. 1. "RES0_TRCRSCTLR15_31_22,Reserved RES0." bitfld.long 0x34 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted. 1 The combined result is inverted. If.." "0,1" bitfld.long 0x34 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted. 1 The selected resource is inverted." "0,1" newline hexmask.long.byte 0x34 16.--19. 1. "GROUP,Selects a group of resources. Possible values are: 0000 For SELECT bits 0 to 3 selects external input selector 0 to 3; other bits are reserved. 0001 For SELECT bits 0 to 7 selects processor.." hexmask.long.word 0x34 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects. Each bit represents a resource from the selected group.See the GROUP field description for details." group.long 0x280++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCSSCCR0,Single-Shot Comparator Control Register 0" hexmask.long.byte 0x0 25.--31. 1. "RES0_TRCSSCCR0_31_25,Reserved RES0." bitfld.long 0x0 24. "RST,Controls whether the single-shot comparator resource is reset when it fires. 0 When the single-shot comparator resource fires it is not reset. 1 When the single-shot comparator resource fires .." "0,1" hexmask.long.byte 0x0 16.--23. 1. "ARC,Selects one or more address range comparators for single-shot control.Each bit represents an address range comparator pair so bit[n-16] controls the selection of address range comparator pair n-16. If bit[n-16] is: 0 The address.." newline hexmask.long.word 0x0 0.--15. 1. "SAC,Selects one or more single address comparators for single-shot control.Each bit represents a single address comparator so bit[n] controls the selection of single address comparator n. If bit[n] is: 0 The single address comparator.." group.long 0x2A0++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCSSCSR0,Single-Shot Comparator Status Register 0" bitfld.long 0x0 31. "STATUS,Single-shot status bit. Indicates if any of the comparators that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects have matched: 0 No match has occurred. 1 One or more matches has occurred. If.." "0,1" hexmask.long 0x0 3.--30. 1. "RES0_TRCSSCSR0_30_3,Reserved RES0." bitfld.long 0x0 2. "DV,Data value comparator support bit. Indicates if the trace unit supports data address with data value comparisons: 0 Single-shot data address with data value comparisons are not supported. 1.." "0,1" newline bitfld.long 0x0 1. "DA,Data address comparator support bit. Indicates if the trace unit supports data address comparisons: 0 Single-shot data address comparisons are not supported. 1 Single-shot data address.." "0,1" bitfld.long 0x0 0. "INST,Instruction address comparator support bit. Indicates if the trace unit supports instruction address comparisons: 0 Single-shot instruction address comparisons are not supported. 1 Single-shot.." "0,1" group.long 0x300++0x7 line.long 0x0 "APBADDR_ETM_CPU3_TRCOSLAR,OS Lock Access Register" hexmask.long 0x0 1.--31. 1. "RES0_TRCOSLAR_31_1,Reserved RES0." bitfld.long 0x0 0. "LOCK,OS Lock control bit: 0 Unlocks the OS Lock. 1 Locks the OS Lock. This setting disables the trace unit." "0,1" line.long 0x4 "APBADDR_ETM_CPU3_TRCOSLSR,OS Lock Status Register" hexmask.long 0x4 4.--31. 1. "RES0_TRCOSLSR_31_4,Reserved RES0." bitfld.long 0x4 3. "PRESENT,Indicates whether the OS Lock is implemented.This bit is RES1 which indicates that the OS Lock is always implemented." "0,1" bitfld.long 0x4 2. "BIT32,This bit is RES0 which indicates that software must perform a 32-bit write to update the TRCOSLAR." "0,1" newline bitfld.long 0x4 1. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked. 1 The OS Lock is locked. When the trace unit core power domain is powered down the value is UNKNOWN. The TRCPDSR indicates if.." "0,1" bitfld.long 0x4 0. "RES0_TRCOSLSR_0_0,Reserved RES0." "0,1" group.long 0x310++0x7 line.long 0x0 "APBADDR_ETM_CPU3_TRCPDCR,Power Down Control Register" hexmask.long 0x0 4.--31. 1. "RES0_TRCPDCR_31_4,Reserved RES0." bitfld.long 0x0 3. "PU,Powerup request bit: 0 The system can remove power from the trace unit. The TRCPDSR indicates if the trace unit is powered down. 1 The system must provide power to the trace unit." "0,1" bitfld.long 0x0 0.--2. "RES0_TRCPDCR_2_0,Reserved RES0." "0,1,2,3,4,5,6,7" line.long 0x4 "APBADDR_ETM_CPU3_TRCPDSR,Power Down Status Register" hexmask.long 0x4 6.--31. 1. "RES0_TRCPDSR_31_6,Reserved RES0." bitfld.long 0x4 5. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked. 1 The OS Lock is locked. The value is UNKNOWN when the trace unit core power domain is powered down that is when POWER==0." "0,1" bitfld.long 0x4 2.--4. "RES0_TRCPDSR_4_2,Reserved RES0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 1. "STICKYPD,Sticky powerdown status bit. Indicates whether the trace register state is valid: 0 If POWER==1 then the state of TRCOSLSR and the trace registers are valid. If POWER==0 then it is UNKNOWN whether the state of TRCOSLSR and the.." "0,1" bitfld.long 0x4 0. "POWER,Power status bit: 0 The trace unit core power domain is not powered. The trace registers are not accessible and they all return an error response. 1 The trace unit core power domain is.." "0,1" group.long 0x400++0x3F line.long 0x0 "APBADDR_ETM_CPU3_TRCACVR0_31_0,Address Comparator Value Registers 0 (low word)" hexmask.long 0x0 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x4 "APBADDR_ETM_CPU3_TRCACVR0_63_32,Address Comparator Value Registers 0 (high word)" hexmask.long 0x4 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x8 "APBADDR_ETM_CPU3_TRCACVR1_31_0,Address Comparator Value Registers 1 (low word)" hexmask.long 0x8 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0xC "APBADDR_ETM_CPU3_TRCACVR1_63_32,Address Comparator Value Registers 1 (high word)" hexmask.long 0xC 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x10 "APBADDR_ETM_CPU3_TRCACVR2_31_0,Address Comparator Value Registers 2 (low word)" hexmask.long 0x10 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x14 "APBADDR_ETM_CPU3_TRCACVR2_63_32,Address Comparator Value Registers 2 (high word)" hexmask.long 0x14 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x18 "APBADDR_ETM_CPU3_TRCACVR3_31_0,Address Comparator Value Registers 3 (low word)" hexmask.long 0x18 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x1C "APBADDR_ETM_CPU3_TRCACVR3_63_32,Address Comparator Value Registers 3 (high word)" hexmask.long 0x1C 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x20 "APBADDR_ETM_CPU3_TRCACVR4_31_0,Address Comparator Value Registers 4 (low word)" hexmask.long 0x20 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x24 "APBADDR_ETM_CPU3_TRCACVR4_63_32,Address Comparator Value Registers 4 (high word)" hexmask.long 0x24 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x28 "APBADDR_ETM_CPU3_TRCACVR5_31_0,Address Comparator Value Registers 5 (low word)" hexmask.long 0x28 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x2C "APBADDR_ETM_CPU3_TRCACVR5_63_32,Address Comparator Value Registers 5 (high word)" hexmask.long 0x2C 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x30 "APBADDR_ETM_CPU3_TRCACVR6_31_0,Address Comparator Value Registers 6 (low word)" hexmask.long 0x30 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x34 "APBADDR_ETM_CPU3_TRCACVR6_63_32,Address Comparator Value Registers 6 (high word)" hexmask.long 0x34 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x38 "APBADDR_ETM_CPU3_TRCACVR7_31_0,Address Comparator Value Registers 7 (low word)" hexmask.long 0x38 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." line.long 0x3C "APBADDR_ETM_CPU3_TRCACVR7_63_32,Address Comparator Value Registers 7 (high word)" hexmask.long 0x3C 0.--31. 1. "ADDRESS,Address value.The address comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field then it must ignore those upper bits in the.." group.long 0x480++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCACATR0,Address Comparator Access Type Registers 0" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR0_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR0_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x488++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCACATR1,Address Comparator Access Type Registers 1" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR1_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR1_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x490++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCACATR2,Address Comparator Access Type Registers 2" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR2_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR2_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x498++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCACATR3,Address Comparator Access Type Registers 3" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR3_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR3_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4A0++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCACATR4,Address Comparator Access Type Registers 4" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR4_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR4_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4A8++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCACATR5,Address Comparator Access Type Registers 5" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR5_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR5_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4B0++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCACATR6,Address Comparator Access Type Registers 6" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR6_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR6_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x4B8++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCACATR7,Address Comparator Access Type Registers 7" hexmask.long.word 0x0 22.--31. 1. "RES0_TRCACATR7_31_22,Reserved RES0." bitfld.long 0x0 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons. 1 The trace unit uses the data.." "0,1" bitfld.long 0x0 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons. The behavior of the address range.." "0,1" newline bitfld.long 0x0 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte. 01 Halfword. 10 Word. 11 Doubleword." "0,1,2,3" bitfld.long 0x0 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison. 01 The trace unit performs a data value comparison and signals a.." "0,1,2,3" hexmask.long.byte 0x0 12.--15. 1. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n. 1.." newline hexmask.long.byte 0x0 8.--11. 1. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n. 1.." bitfld.long 0x0 7. "RES0_TRCACATR7_7_7,Reserved RES0." "0,1" bitfld.long 0x0 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0. 001 Comparator 1. 010 Comparator.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not.." "0,1,2,3" bitfld.long 0x0 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address. 01 Data load address. 10 Data store address. 11.." "0,1,2,3" group.long 0x600++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCCIDCVR0,Context ID Comparator Value Register 0" hexmask.long 0x0 0.--31. 1. "VALUE,Context ID value. The implemented width of this field is IMPLEMENTATION DEFINED and is set by TRCIDR2.CIDSIZE. Unimplemented bits are RAZ/WI.After a processor reset the ETM architecture assumes that the Context ID is zero until the processor.." group.long 0x640++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCVMIDCVR0,VMID Comparator Value Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--7. 1. "VALUE,Contains a VMID value." group.long 0x680++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCCIDCCTLR0,Context ID Comparator Control Register 0" hexmask.long 0x0 0.--31. 1. "COMP_N,Controls the mask value that the trace unit applies to TRCCIDCVRn. Each bit in this field corresponds to a byte in TRCCIDCVRn. When a bit is: 0 The trace unit includes the relevant byte in TRCCIDCVRn when it performs the Context.." group.long 0xEE4++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCITATBIDR,Integration ATB Identification Register" hexmask.long 0x0 7.--31. 1. "RES0_TRCITATBIDR_31_7,Reserved RES0" hexmask.long.byte 0x0 0.--6. 1. "ID,Drives the ATIDMn[6:0] output pins" group.long 0xEEC++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCITIDATAR,Integration Instruction ATB Data Register" hexmask.long 0x0 5.--31. 1. "RES0_TRCITIDATAR_31_5,Reserved RES0" bitfld.long 0x0 4. "ATDATAM_31,Drives the ATDATAM[31] output" "0,1" bitfld.long 0x0 3. "ATDATAM_23,Drives the ATDATAM[23] output" "0,1" newline bitfld.long 0x0 2. "ATDATAM_15,Drives the ATDATAM[15] output" "0,1" bitfld.long 0x0 1. "ATDATAM_7,Drives the ATDATAM[7] output" "0,1" bitfld.long 0x0 0. "ATDATAM_0,Drives the ATDATAM[0] output" "0,1" group.long 0xEF4++0x3 line.long 0x0 "APBADDR_ETM_CPU3_TRCITIATBINR,Integration Instruction ATB In Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved. Read undefined." bitfld.long 0x0 1. "AFVALIDM,Returns the value of the AFVALIDMn input pin" "0,1" bitfld.long 0x0 0. "ATREADYM,Returns the value of the ATREADYMn input pin" "0,1" group.long 0xEFC++0x7 line.long 0x0 "APBADDR_ETM_CPU3_TRCITIATBOUTR,Integration Instruction ATB Out Register" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reserved. Read undefined." bitfld.long 0x0 8.--9. "BYTES,Drives the ATBYTESMn[1:0] output pins" "0,1,2,3" hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved. Read undefined." newline bitfld.long 0x0 1. "AFREADY,Drives the AFREADYMn output pin" "0,1" bitfld.long 0x0 0. "ATVALID,Drives the ATVALIDMn output pin" "0,1" line.long 0x4 "APBADDR_ETM_CPU3_TRCITCTRL,Integration Mode Control Register" hexmask.long 0x4 1.--31. 1. "RES0_TRCITCTRL_31_1,Reserved RES0." bitfld.long 0x4 0. "ITEN,Integration mode enable bit: 0 The trace unit is not in integration mode. 1 The trace unit is in integration mode. This mode enables a debug agent to perform topology detection and.." "0,1" group.long 0xFA0++0x1F line.long 0x0 "APBADDR_ETM_CPU3_TRCCLAIMSET,Claim Tag Set Register" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--3. 1. "SET,Sets bits in the claim tag and determines the number of claim tag bits implemented." line.long 0x4 "APBADDR_ETM_CPU3_TRCCLAIMCLR,Claim Tag Clear Register" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x4 0.--3. 1. "CLR,Clears bits in the claim tag and determines the current value of the claim tag." line.long 0x8 "APBADDR_ETM_CPU3_TRCDEVAFF0,Device Affinity Register 0" hexmask.long 0x8 0.--31. 1. "MPIDR_EL1_31_0,Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0xC "APBADDR_ETM_CPU3_TRCDEVAFF1,Device Affinity Register 1" hexmask.long 0xC 0.--31. 1. "MPIDR_EL1_63_32,Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x10 "APBADDR_ETM_CPU3_TRCLAR,Software Lock Access Register" hexmask.long 0x10 0.--31. 1. "KEY,Writing the key value 0xC5ACCE55 to this field clears the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register sets the lock disabling write accesses to this.." line.long 0x14 "APBADDR_ETM_CPU3_TRCLSR,Software Lock Status Register" hexmask.long 0x14 3.--31. 1. "RES0_TRCLSR_31_3,Reserved RES0." bitfld.long 0x14 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" bitfld.long 0x14 1. "SLK,Software lock status for this component. Possible values of this field are: 0 Lock clear. Writes are permitted to this component's registers. 1 Lock set. Writes to this component's registers.." "0,1" newline bitfld.long 0x14 0. "SLI,Software lock implemented. RAO." "0,1" line.long 0x18 "APBADDR_ETM_CPU3_TRCAUTHSTATUS,Authentication Status Register" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCAUTHSTATUS_31_8,Reserved RES0." bitfld.long 0x18 6.--7. "SNID,Indicates whether the system enables the trace unit to support Secure non-invasive debug: 00 The trace unit does not implement support for Secure non-invasive debug. 01 Reserved." "0,1,2,3" bitfld.long 0x18 4.--5. "SID,Indicates whether the trace unit supports Secure invasive debug: 00 The trace unit does not support Secure invasive debug. All other values are reserved." "0,1,2,3" newline bitfld.long 0x18 2.--3. "NSNID,Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: 00 The trace unit does not implement support for Non-secure non-invasive debug. 01 Reserved." "0,1,2,3" bitfld.long 0x18 0.--1. "NSID,Indicates whether the trace unit supports Non-secure invasive debug: 00 The trace unit does not support Non-secure invasive debug. All other values are reserved." "0,1,2,3" line.long 0x1C "APBADDR_ETM_CPU3_TRCDEVARCH,Device Architecture Register" hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For trace this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is RAO." "0,1" hexmask.long.byte 0x1C 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For trace the revision defined by ETMv4 is 0x0.All other values are reserved." newline hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For trace bits [15:12] are the architecture version 0x4; bits [11:0] are the architecture part number 0xA13.This corresponds to trace.." group.long 0xFC8++0x37 line.long 0x0 "APBADDR_ETM_CPU3_TRCDEVID,Device ID Register" hexmask.long 0x0 0.--31. 1. "DEVID,Indicates the capabilities of the trace unit. The implemented width of this field and its bit assignments are IMPLEMENTATION DEFINED. Unimplemented bits are RAZ/WI.If a component is configurable then ARM recommends that this field can also indicate.." line.long 0x4 "APBADDR_ETM_CPU3_TRCDEVTYPE,Device Type Register" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_TRCDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x4 4.--7. 1. "SUB,Returns 0x1 to indicate that the ETM generates processor trace.All other values are reserved." hexmask.long.byte 0x4 0.--3. 1. "MAIN,Returns 0x3 to indicate that the ETM is a trace source.All other values are reserved." line.long 0x8 "APBADDR_ETM_CPU3_TRCPIDR4,Peripheral Identification Register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RES0_TRCPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x8 4.--7. 1. "SIZE,Size of the component. RES0. This indicates that the ETM memory map occupies 4KB." hexmask.long.byte 0x8 0.--3. 1. "DES_2,Designer JEP106 continuation code. For ARM Limited this field is 0b0100." line.long 0xC "APBADDR_ETM_CPU3_TRCPIDR5,Peripheral Identification Register 5" hexmask.long.tbyte 0xC 8.--31. 1. "RES0_TRCPIDR5_31_8,Reserved RES0." hexmask.long.byte 0xC 0.--7. 1. "RESERVED,RES0 reserved for future use." line.long 0x10 "APBADDR_ETM_CPU3_TRCPIDR6,Peripheral Identification Register 6" hexmask.long.tbyte 0x10 8.--31. 1. "RES0_TRCPIDR6_31_8,Reserved RES0." hexmask.long.byte 0x10 0.--7. 1. "RESERVED,RES0 reserved for future use." line.long 0x14 "APBADDR_ETM_CPU3_TRCPIDR7,Peripheral Identification Register 7" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_TRCPIDR7_31_8,Reserved RES0." hexmask.long.byte 0x14 0.--7. 1. "RESERVED,RES0 reserved for future use." line.long 0x18 "APBADDR_ETM_CPU3_TRCPIDR0,Peripheral Identification Register 0" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x18 0.--7. 1. "PART_0,Part number bits[7:0]." line.long 0x1C "APBADDR_ETM_CPU3_TRCPIDR1,Peripheral Identification Register 1" hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_TRCPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x1C 4.--7. 1. "DES_0,Designer bits[3:0] of JEP106 ID code. For ARM Limited this field is 0b1011." hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part number bits[11:8]." line.long 0x20 "APBADDR_ETM_CPU3_TRCPIDR2,Peripheral Identification Register 2" hexmask.long.tbyte 0x20 8.--31. 1. "RES0_TRCPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x20 4.--7. 1. "REVISION,The IMPLEMENTATION DEFINED revision number for the ETM implementation. See also TRCIDR1.REVISION." bitfld.long 0x20 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" newline bitfld.long 0x20 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0x24 "APBADDR_ETM_CPU3_TRCPIDR3,Peripheral Identification Register 3" hexmask.long.tbyte 0x24 8.--31. 1. "RES0_TRCPIDR3_31_8,Reserved RES0." hexmask.long.byte 0x24 4.--7. 1. "REVAND,The IMPLEMENTATION DEFINED manufacturing revision number for the implementation. After silicon is available if metal fixes are necessary the manufacturer can alter the top metal layer so that this field can indicate any post-fab silicon changes." hexmask.long.byte 0x24 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x28 "APBADDR_ETM_CPU3_TRCCIDR0,Component Identification Register 0" hexmask.long.tbyte 0x28 8.--31. 1. "RES0_TRCCIDR0_31_8,Reserved RES0." hexmask.long.byte 0x28 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x2C "APBADDR_ETM_CPU3_TRCCIDR1,Component Identification Register 1" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_TRCCIDR1_31_8,Reserved RES0." hexmask.long.byte 0x2C 4.--7. 1. "CLASS,Component class. Reads as 0x9 to indicate that the ETM is a debug component with CoreSight architecture compliant management registers." hexmask.long.byte 0x2C 0.--3. 1. "PRMBL_1,Preamble. Must read as 0x0." line.long 0x30 "APBADDR_ETM_CPU3_TRCCIDR2,Component Identification Register 2" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_TRCCIDR2_31_8,Reserved RES0." hexmask.long.byte 0x30 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x34 "APBADDR_ETM_CPU3_TRCCIDR3,Component Identification Register 3" hexmask.long.tbyte 0x34 8.--31. 1. "RES0_TRCCIDR3_31_8,Reserved RES0." hexmask.long.byte 0x34 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree "A53SS0_CORE3_PMU" base ad:0x730320000 group.long 0x0++0x3 line.long 0x0 "APBADDR_PMU_CPU3_PMEVCNTR0_EL0,Performance Monitors Event Count Register 0" hexmask.long 0x0 0.--31. 1. "PMEVCNTR0_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x8++0x3 line.long 0x0 "APBADDR_PMU_CPU3_PMEVCNTR1_EL0,Performance Monitors Event Count Register 1" hexmask.long 0x0 0.--31. 1. "PMEVCNTR1_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x10++0x3 line.long 0x0 "APBADDR_PMU_CPU3_PMEVCNTR2_EL0,Performance Monitors Event Count Register 2" hexmask.long 0x0 0.--31. 1. "PMEVCNTR2_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x18++0x3 line.long 0x0 "APBADDR_PMU_CPU3_PMEVCNTR3_EL0,Performance Monitors Event Count Register 3" hexmask.long 0x0 0.--31. 1. "PMEVCNTR3_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x20++0x3 line.long 0x0 "APBADDR_PMU_CPU3_PMEVCNTR4_EL0,Performance Monitors Event Count Register 4" hexmask.long 0x0 0.--31. 1. "PMEVCNTR4_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0x28++0x3 line.long 0x0 "APBADDR_PMU_CPU3_PMEVCNTR5_EL0,Performance Monitors Event Count Register 5" hexmask.long 0x0 0.--31. 1. "PMEVCNTR5_EL0,Event counter n. Value of event counter n where n is the number of this register and is a number from 0 to 30." group.long 0xF8++0x7 line.long 0x0 "APBADDR_PMU_CPU3_PMCCNTR_EL0_31_0,Performance Monitors Cycle Counter (low word)" hexmask.long 0x0 0.--31. 1. "CCNT,Cycle count. Depending on the values of PMCR_EL0.{LC D} the cycle count increments in one of the following ways:Every processor clock cycle.Every 64th processor clock cycle.The cycle count can be reset to zero by writing 1 to PMCR_EL0.C." line.long 0x4 "APBADDR_PMU_CPU3_PMCCNTR_EL0_63_32,Performance Monitors Cycle Counter (high word)" hexmask.long 0x4 0.--31. 1. "CCNT,Cycle count. Depending on the values of PMCR_EL0.{LC D} the cycle count increments in one of the following ways:Every processor clock cycle.Every 64th processor clock cycle.The cycle count can be reset to zero by writing 1 to PMCR_EL0.C." group.long 0x400++0x17 line.long 0x0 "APBADDR_PMU_CPU3_PMEVTYPER0_EL0,Performance Monitors Event Type Register 0" bitfld.long 0x0 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x0 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x0 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x0 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x0 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x0 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x0 10.--25. 1. "RES0_PMEVTYPER0_EL0_25_10,Reserved RES0." hexmask.long.word 0x0 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x4 "APBADDR_PMU_CPU3_PMEVTYPER1_EL0,Performance Monitors Event Type Register 1" bitfld.long 0x4 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x4 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x4 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x4 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x4 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x4 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x4 10.--25. 1. "RES0_PMEVTYPER1_EL0_25_10,Reserved RES0." hexmask.long.word 0x4 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x8 "APBADDR_PMU_CPU3_PMEVTYPER2_EL0,Performance Monitors Event Type Register 2" bitfld.long 0x8 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x8 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x8 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x8 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x8 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x8 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x8 10.--25. 1. "RES0_PMEVTYPER2_EL0_25_10,Reserved RES0." hexmask.long.word 0x8 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0xC "APBADDR_PMU_CPU3_PMEVTYPER3_EL0,Performance Monitors Event Type Register 3" bitfld.long 0xC 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0xC 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0xC 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0xC 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0xC 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0xC 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0xC 10.--25. 1. "RES0_PMEVTYPER3_EL0_25_10,Reserved RES0." hexmask.long.word 0xC 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x10 "APBADDR_PMU_CPU3_PMEVTYPER4_EL0,Performance Monitors Event Type Register 4" bitfld.long 0x10 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x10 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x10 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x10 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x10 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x10 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x10 10.--25. 1. "RES0_PMEVTYPER4_EL0_25_10,Reserved RES0." hexmask.long.word 0x10 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." line.long 0x14 "APBADDR_PMU_CPU3_PMEVTYPER5_EL0,Performance Monitors Event Type Register 5" bitfld.long 0x14 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count events in EL1. 1.." "0,1" bitfld.long 0x14 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count events in EL0. 1.." "0,1" newline bitfld.long 0x14 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Non-secure EL1 are counted.Otherwise events in Non-secure EL1 are.." "0,1" bitfld.long 0x14 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U events in Non-secure EL0 are counted.Otherwise events in Non-secure EL0 are.." "0,1" newline bitfld.long 0x14 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count events in EL2. 1 Count events in EL2." "0,1" bitfld.long 0x14 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P events in Secure EL3 are counted.Otherwise events in Secure EL3.." "0,1" newline hexmask.long.word 0x14 10.--25. 1. "RES0_PMEVTYPER5_EL0_25_10,Reserved RES0." hexmask.long.word 0x14 0.--9. 1. "EVTCOUNT,Event to count. The event number of the event that is counted by event counter PMEVCNTR_EL0.Software must program this field with an event defined by the processor or a common event defined by the architecture.If evtCount is programmed to an.." group.long 0x47C++0x3 line.long 0x0 "APBADDR_PMU_CPU3_PMCCFILTR_EL0,Performance Monitors Cycle Counter Filter Register" bitfld.long 0x0 31. "P,EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count cycles in EL1. 1.." "0,1" bitfld.long 0x0 30. "U,EL0 filtering bit. Controls counting in EL0. If EL3 is implemented then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count cycles in EL0. 1.." "0,1" newline bitfld.long 0x0 29. "NSK,Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P cycles in Non-secure EL1 are counted.Otherwise cycles in Non-secure EL1 are.." "0,1" bitfld.long 0x0 28. "NSU,Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of U cycles in Non-secure EL0 are counted.Otherwise cycles in Non-secure EL0 are.." "0,1" newline bitfld.long 0x0 27. "NSH,Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented this bit is RES0. 0 Do not count cycles in EL2. 1 Count cycles in EL2." "0,1" bitfld.long 0x0 26. "M,Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented this bit is RES0.If the value of this bit is equal to the value of P cycles in Secure EL3 are counted.Otherwise cycles in Secure EL3.." "0,1" newline hexmask.long 0x0 0.--25. 1. "RES0_PMCCFILTR_EL0_25_0,Reserved RES0." group.long 0xC00++0x3 line.long 0x0 "APBADDR_PMU_CPU3_PMCNTENSET_EL0,Performance Monitors Count Enable Set Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 enable bit. Enables the cycle counter register. Possible values are: 0 When read means the cycle counter is disabled. When written has no effect. 1 When read means the cycle.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter enable bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: 0 When read means that PMEVCNTR is disabled. When written has no effect. 1.." group.long 0xC20++0x3 line.long 0x0 "APBADDR_PMU_CPU3_PMCNTENCLR_EL0,Performance Monitors Count Enable Clear Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 disable bit. Disables the cycle counter register. Possible values are: 0 When read means the cycle counter is disabled. When written has no effect. 1 When read means the cycle.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter disable bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: 0 When read means that PMEVCNTR is disabled. When written has no effect." group.long 0xC40++0x3 line.long 0x0 "APBADDR_PMU_CPU3_PMINTENSET_EL1,Performance Monitors Interrupt Enable Set Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow interrupt request enable bit. Possible values are: 0 When read means the cycle counter overflow interrupt request is disabled. When written has no effect. 1 When read .." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow interrupt request enable bit for PMEVCNTR_EL0.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: 0 When read means that the PMEVCNTR_EL0 event counter interrupt request is.." group.long 0xC60++0x3 line.long 0x0 "APBADDR_PMU_CPU3_PMINTENCLR_EL1,Performance Monitors Interrupt Enable Clear Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow interrupt request disable bit. Possible values are: 0 When read means the cycle counter overflow interrupt request is disabled. When written has no effect. 1 When read .." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow interrupt request disable bit for PMEVCNTR_EL0.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: 0 When read means that the PMEVCNTR_EL0 event counter interrupt request is.." group.long 0xC80++0x3 line.long 0x0 "APBADDR_PMU_CPU3_PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow bit. Possible values are: 0 When read means the cycle counter has not overflowed. When written has no effect. 1 When read means the cycle counter has overflowed. When.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow clear bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: 0 When read means that PMEVCNTR has not overflowed. When written has no effect." group.long 0xCA0++0x3 line.long 0x0 "APBADDR_PMU_CPU3_PMSWINC_EL0,Performance Monitors Software Increment Register" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved RES0" hexmask.long.byte 0x0 0.--5. 1. "P_X,Event counter software increment bit for PMEVCNTR" group.long 0xCC0++0x3 line.long 0x0 "APBADDR_PMU_CPU3_PMOVSSET_EL0,Performance Monitors Overflow Flag Status Set Register" bitfld.long 0x0 31. "C,PMCCNTR_EL0 overflow bit. Possible values are: 0 When read means the cycle counter has not overflowed. When written has no effect. 1 When read means the cycle counter has overflowed. When.." "0,1" hexmask.long 0x0 0.--30. 1. "P_X,Event counter overflow set bit for PMEVCNTR.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: 0 When read means that PMEVCNTR has not overflowed. When written has no effect." group.long 0xE00++0x7 line.long 0x0 "APBADDR_PMU_CPU3_PMCFGR,Performance Monitors Configuration Register" hexmask.long.word 0x0 20.--31. 1. "RES0_PMCFGR_31_20,Reserved RES0." bitfld.long 0x0 19. "UEN,User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface so this bit is RES0." "0,1" newline bitfld.long 0x0 18. "WT,This feature is not supported so this bit is RES0." "0,1" bitfld.long 0x0 17. "NA,This feature is not supported so this bit is RES0." "0,1" newline bitfld.long 0x0 16. "EX,Export supported. Value is IMPLEMENTATION DEFINED. 0 PMCR_EL0.X is RES0. 1 PMCR_EL0.X is read/write." "0,1" bitfld.long 0x0 15. "CCD,Cycle counter has prescale. This is RES1 if AArch32 is supported at any EL and RES0 otherwise. 0 PMCR_EL0.D is RES0. 1 PMCR_EL0.D is read/write." "0,1" newline bitfld.long 0x0 14. "CC,Dedicated cycle counter [counter 31] supported. This bit is RES1." "0,1" hexmask.long.byte 0x0 8.--13. 1. "SIZE,Size of counters. This field determines the spacing of counters in the memory-map.In v8-A the counters are at doubleword-aligned addresses and the largest counter is 64-bits so this field is 0b111111." newline hexmask.long.byte 0x0 0.--7. 1. "N,Number of counters implemented in addition to the cycle counter PMCCNTR_EL0. The maximum number of event counters is 31 so bits[7:5] are always RES0. 00000000 Only PMCCNTR_EL0 implemented. 00000001.." line.long 0x4 "APBADDR_PMU_CPU3_PMCR_EL0,Performance Monitors Control Register" hexmask.long.tbyte 0x4 11.--31. 1. "RES0_PMCR_EL0_31_11,Reserved RAZ/WI." hexmask.long.byte 0x4 7.--10. 1. "RES0_PMCR_EL0_10_7,Reserved RES0." newline bitfld.long 0x4 6. "LC,Long cycle counter enable. Determines which PMCCNTR_EL0 bit generates an overflow recorded by PMOVSR[31]. 0 Cycle counter overflow on increment that changes PMCCNTR_EL0[31] from 1 to 0. 1 Cycle.." "0,1" bitfld.long 0x4 5. "DP,Disable cycle counter when event counting is prohibited. The possible values of this bit are: 0 PMCCNTR_EL0 if enabled counts when event counting is prohibited. 1 PMCCNTR_EL0 does not count.." "0,1" newline bitfld.long 0x4 4. "X,Enable export of events in an IMPLEMENTATION DEFINED event stream. The possible values of this bit are: 0 Do not export events. 1 Export events where not prohibited. This bit is.." "0,1" bitfld.long 0x4 3. "D,Clock divider. The possible values of this bit are: 0 When enabled PMCCNTR_EL0 counts every clock cycle. 1 When enabled PMCCNTR_EL0 counts once every 64 clock cycles. This bit.." "0,1" newline bitfld.long 0x4 2. "C,Cycle counter reset. This bit is WO. The effects of writing to this bit are: 0 No action. 1 Reset PMCCNTR_EL0 to zero. This bit is always RAZ.Resetting PMCCNTR_EL0 does not.." "0,1" bitfld.long 0x4 1. "P,Event counter reset. This bit is WO. The effects of writing to this bit are: 0 No action. 1 Reset all event counters not including PMCCNTR_EL0 to zero. This bit is always.." "0,1" newline bitfld.long 0x4 0. "E,Enable. The possible values of this bit are: 0 All counters including PMCCNTR_EL0 are disabled. 1 All counters are enabled by PMCNTENSET_EL0. This bit is RW." "0,1" group.long 0xE20++0x7 line.long 0x0 "APBADDR_PMU_CPU3_PMCEID0_EL0,Performance Monitors Common Event Identification Register 0" hexmask.long 0x0 0.--31. 1. "CE_31_0,Common architectural and microarchitectural feature events that can be counted by the PMU event counters.For each bit described in the following table the event is implemented if the bit is set to 1 or not implemented if the bit is set to.." line.long 0x4 "APBADDR_PMU_CPU3_PMCEID1_EL0,Performance Monitors Common Event Identification Register 1" hexmask.long 0x4 1.--31. 1. "RES0_PMCEID1_EL0_31_1,Reserved RES0." bitfld.long 0x4 0. "CE_32,Common architectural and microarchitectural feature events that can be counted by the PMU event counters.For the bit described in the following table the event is implemented if the bit is set to 1 or not implemented if the bit is set to.." "0,1" group.long 0xF00++0x3 line.long 0x0 "APBADDR_PMU_CPU3_PMITCTRL,Performance Monitors Integration mode Control Register" hexmask.long 0x0 1.--31. 1. "RES0_PMITCTRL_31_1,Reserved RES0." bitfld.long 0x0 0. "IME,Integration mode enable. When IME == 1 the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED. 0 Normal operation." "0,1" group.long 0xFA8++0x17 line.long 0x0 "APBADDR_PMU_CPU3_PMDEVAFF0,Performance Monitors Device Affinity Register 0" hexmask.long 0x0 0.--31. 1. "PMDEVAFF0,MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x4 "APBADDR_PMU_CPU3_PMDEVAFF1,Performance Monitors Device Affinity Register 1" hexmask.long 0x4 0.--31. 1. "PMDEVAFF1,MPIDR_EL1 high half. Read-only copy of the high half of MPIDR_EL1 as seen from the highest implemented exception level." line.long 0x8 "APBADDR_PMU_CPU3_PMLAR,Performance Monitors Lock Access Register" hexmask.long 0x8 0.--31. 1. "KEY,Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock enabling write accesses to this component's registers through a memory-mapped interface.Writing any other value to this register locks the lock disabling write.." line.long 0xC "APBADDR_PMU_CPU3_PMLSR,Performance Monitors Lock Status Register" hexmask.long 0xC 3.--31. 1. "RES0_PMLSR_31_3,Reserved RES0." bitfld.long 0xC 2. "NTT,Not thirty-two bit access required. RAZ." "0,1" newline bitfld.long 0xC 1. "SLK,Software lock status for this component. For an access to LSR that is not a memory-mapped access or when the software lock is not implemented this field is RES0.For memory-mapped accesses when the software lock is implemented possible values of.." "0,1" bitfld.long 0xC 0. "SLI,Software lock implemented. For an access to LSR that is not a memory-mapped access this field is RAZ. For memory-mapped accesses the value of this field is IMPLEMENTATION DEFINED. Permitted values are: 0 Software lock not.." "0,1" line.long 0x10 "APBADDR_PMU_CPU3_PMAUTHSTATUS,Performance Monitors Authentication Status Register" hexmask.long.tbyte 0x10 8.--31. 1. "RES0_PMAUTHSTATUS_31_8,Reserved RES0." bitfld.long 0x10 6.--7. "SNID,Holds the same value as DBGAUTHSTATUS_EL1.SNID." "0,1,2,3" newline bitfld.long 0x10 4.--5. "RES0_PMAUTHSTATUS_5_4,Reserved RES0." "0,1,2,3" bitfld.long 0x10 2.--3. "NSNID,Holds the same value as DBGAUTHSTATUS_EL1.NSNID." "0,1,2,3" newline bitfld.long 0x10 0.--1. "RES0_PMAUTHSTATUS_1_0,Reserved RES0." "0,1,2,3" line.long 0x14 "APBADDR_PMU_CPU3_PMDEVARCH,Performance Monitors Device Architecture Register" hexmask.long.word 0x14 21.--31. 1. "ARCHITECT,Defines the architecture of the component. For Performance Monitors this is ARM Limited.Bits [31:28] are the JEP 106 continuation code 0x4.Bits [27:21] are the JEP 106 ID code 0x3B." bitfld.long 0x14 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A." "0,1" newline hexmask.long.byte 0x14 16.--19. 1. "REVISION,Defines the architecture revision. For architectures defined by ARM this is the minor revision.For Performance Monitors the revision defined by v8-A is 0x0.All other values are reserved." hexmask.long.word 0x14 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component. For architectures defined by ARM this is further subdivided.For Performance Monitors:Bits [15:12] are the architecture version 0x2.Bits [11:0] are the architecture part number 0xA16.This.." group.long 0xFCC++0x33 line.long 0x0 "APBADDR_PMU_CPU3_PMDEVTYPE,Performance Monitors Device Type Register" hexmask.long.tbyte 0x0 8.--31. 1. "RES0_PMDEVTYPE_31_8,Reserved RES0." hexmask.long.byte 0x0 4.--7. 1. "SUB,Subtype. Must read as 0x1 to indicate this is a processor component." newline hexmask.long.byte 0x0 0.--3. 1. "MAJOR,Major type. Must read as 0x6 to indicate this is a performance monitor component." line.long 0x4 "APBADDR_PMU_CPU3_PMPIDR4,Performance Monitors Peripheral Identification Register 4" hexmask.long.tbyte 0x4 8.--31. 1. "RES0_PMPIDR4_31_8,Reserved RES0." hexmask.long.byte 0x4 4.--7. 1. "SIZE,Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers." newline hexmask.long.byte 0x4 0.--3. 1. "DES_2,Designer JEP106 continuation code least significant nibble. For ARM Limited this field is 0b0100." line.long 0x8 "APBADDR_PMU_CPU3_PMPIDR5,Performance Monitors Peripheral Identification Register 5" hexmask.long 0x8 0.--31. 1. "RESERVED,Reserved RES0" line.long 0xC "APBADDR_PMU_CPU3_PMPIDR6,Performance Monitors Peripheral Identification Register 6" hexmask.long 0xC 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x10 "APBADDR_PMU_CPU3_PMPIDR7,Performance Monitors Peripheral Identification Register 7" hexmask.long 0x10 0.--31. 1. "RESERVED,Reserved RES0" line.long 0x14 "APBADDR_PMU_CPU3_PMPIDR0,Performance Monitors Peripheral Identification Register 0" hexmask.long.tbyte 0x14 8.--31. 1. "RES0_PMPIDR0_31_8,Reserved RES0." hexmask.long.byte 0x14 0.--7. 1. "PART_0,Part number least significant byte." line.long 0x18 "APBADDR_PMU_CPU3_PMPIDR1,Performance Monitors Peripheral Identification Register 1" hexmask.long.tbyte 0x18 8.--31. 1. "RES0_PMPIDR1_31_8,Reserved RES0." hexmask.long.byte 0x18 4.--7. 1. "DES_0,Designer least significant nibble of JEP106 ID code. For ARM Limited this field is 0b1011." newline hexmask.long.byte 0x18 0.--3. 1. "PART_1,Part number most significant nibble." line.long 0x1C "APBADDR_PMU_CPU3_PMPIDR2,Performance Monitors Peripheral Identification Register 2" hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_PMPIDR2_31_8,Reserved RES0." hexmask.long.byte 0x1C 4.--7. 1. "REVISION,Part major revision. Parts can also use this field to extend Part number to 16-bits." newline bitfld.long 0x1C 3. "JEDEC,RAO. Indicates a JEP106 identity code is used." "0,1" bitfld.long 0x1C 0.--2. "DES_1,Designer most significant bits of JEP106 ID code. For ARM Limited this field is 0b011." "0,1,2,3,4,5,6,7" line.long 0x20 "APBADDR_PMU_CPU3_PMPIDR3,Performance Monitors Peripheral Identification Register 3" hexmask.long.tbyte 0x20 8.--31. 1. "RES0_PMPIDR3_31_8,Reserved RES0." hexmask.long.byte 0x20 4.--7. 1. "REVAND,Part minor revision. Parts using PMPIDR2.REVISION as an extension to the Part number must use this field as a major revision number." newline hexmask.long.byte 0x20 0.--3. 1. "CMOD,Customer modified. Indicates someone other than the Designer has modified the component." line.long 0x24 "APBADDR_PMU_CPU3_PMCIDR0,Performance Monitors Component Identification Register 0" hexmask.long.tbyte 0x24 8.--31. 1. "RES0_PMCIDR0_31_8,Reserved RES0." hexmask.long.byte 0x24 0.--7. 1. "PRMBL_0,Preamble. Must read as 0x0D." line.long 0x28 "APBADDR_PMU_CPU3_PMCIDR1,Performance Monitors Component Identification Register 1" hexmask.long.tbyte 0x28 8.--31. 1. "RES0_PMCIDR1_31_8,Reserved RES0." hexmask.long.byte 0x28 4.--7. 1. "CLASS,Component class. Reads as 0x9 debug component." newline hexmask.long.byte 0x28 0.--3. 1. "PRMBL_1,Preamble. RAZ." line.long 0x2C "APBADDR_PMU_CPU3_PMCIDR2,Performance Monitors Component Identification Register 2" hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_PMCIDR2_31_8,Reserved RES0." hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_2,Preamble. Must read as 0x05." line.long 0x30 "APBADDR_PMU_CPU3_PMCIDR3,Performance Monitors Component Identification Register 3" hexmask.long.tbyte 0x30 8.--31. 1. "RES0_PMCIDR3_31_8,Reserved RES0." hexmask.long.byte 0x30 0.--7. 1. "PRMBL_3,Preamble. Must read as 0xB1." tree.end tree.end tree "A53SS0_SS" tree "A53SS0_SS_ECC_AGGR" base ad:0x718000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_COREPAC_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_COREPAC_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_COREPAC_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR_COREPAC_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_COREPAC_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_COREPAC_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 23. "A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_COREPAC_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 23. "A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_COREPAC_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 23. "A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_COREPAC_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_COREPAC_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 23. "A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 22. "A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 21. "A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 20. "A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 19. "A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 18. "A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 17. "A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 16. "A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 15. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 14. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 13. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 12. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 11. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 10. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 9. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 8. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 7. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 6. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 5. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 4. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 3. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 2. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 1. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x4 0. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_COREPAC_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 23. "A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_COREPAC_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 23. "A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 22. "A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 21. "A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 20. "A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 19. "A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 18. "A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 17. "A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 16. "A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 15. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 14. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 13. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 12. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 11. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 10. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 9. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 8. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 7. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 6. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 5. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 4. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 3. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 2. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 1. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend" "0,1" newline bitfld.long 0x0 0. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_COREPAC_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_COREPAC_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_COREPAC_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_COREPAC_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "A53SS0_SS_ROM" base ad:0x730000000 group.long 0x0++0x3F line.long 0x0 "APBADDR_ROMV8_ROMENTRY0,ROM Table Entry Register 0 (CPU 0 Debug Component)" line.long 0x4 "APBADDR_ROMV8_ROMENTRY1,ROM Table Entry Register 1 (CPU 0 CTI Component)" line.long 0x8 "APBADDR_ROMV8_ROMENTRY2,ROM Table Entry Register 2 (CPU 0 PMU Component)" line.long 0xC "APBADDR_ROMV8_ROMENTRY3,ROM Table Entry Register 3 (CPU 0 ETM Component)" line.long 0x10 "APBADDR_ROMV8_ROMENTRY4,ROM Table Entry Register 4 (CPU 1 Debug Component)" line.long 0x14 "APBADDR_ROMV8_ROMENTRY5,ROM Table Entry Register 5 (CPU 1 CTI Component)" line.long 0x18 "APBADDR_ROMV8_ROMENTRY6,ROM Table Entry Register 6 (CPU 1 PMU Component)" line.long 0x1C "APBADDR_ROMV8_ROMENTRY7,ROM Table Entry Register 7 (CPU 1 ETM Component)" line.long 0x20 "APBADDR_ROMV8_ROMENTRY8,ROM Table Entry Register 8 (CPU 2 Debug Component)" line.long 0x24 "APBADDR_ROMV8_ROMENTRY9,ROM Table Entry Register 9 (CPU 2 CTI Component)" line.long 0x28 "APBADDR_ROMV8_ROMENTRY10,ROM Table Entry Register 10 (CPU 2 PMU Component)" line.long 0x2C "APBADDR_ROMV8_ROMENTRY11,ROM Table Entry Register 11 (CPU 2 ETM Component)" line.long 0x30 "APBADDR_ROMV8_ROMENTRY12,ROM Table Entry Register 12 (CPU 3 Debug Component)" line.long 0x34 "APBADDR_ROMV8_ROMENTRY13,ROM Table Entry Register 13 (CPU 3 CTI Component)" line.long 0x38 "APBADDR_ROMV8_ROMENTRY14,ROM Table Entry Register 14 (CPU 3 PMU Component)" line.long 0x3C "APBADDR_ROMV8_ROMENTRY15,ROM Table Entry Register 15 (CPU 3 ETM Component)" group.long 0xFD0++0x2F line.long 0x0 "APBADDR_ROMV8_ROM_PERIPHID4_VAL,ROM Peripheral ID 4" line.long 0x4 "APBADDR_ROMV8_ROM_PERIPHID5_VAL,ROM Peripheral ID 5" line.long 0x8 "APBADDR_ROMV8_ROM_PERIPHID6_VAL,ROM Peripheral ID 6" line.long 0xC "APBADDR_ROMV8_ROM_PERIPHID7_VAL,ROM Peripheral ID 7" line.long 0x10 "APBADDR_ROMV8_ROM_PERIPHID0_VAL,ROM Peripheral ID 0" line.long 0x14 "APBADDR_ROMV8_ROM_PERIPHID1_VAL,ROM Peripheral ID 1" line.long 0x18 "APBADDR_ROMV8_ROM_PERIPHID2_VAL,ROM Peripheral ID 2" line.long 0x1C "APBADDR_ROMV8_ROM_PERIPHID3_VAL,ROM Peripheral ID 3" line.long 0x20 "APBADDR_ROMV8_ROM_COMPONID0_VAL,ROM Component ID 0" line.long 0x24 "APBADDR_ROMV8_ROM_COMPONID1_VAL,ROM Component ID 1" line.long 0x28 "APBADDR_ROMV8_ROM_COMPONID2_VAL,ROM Component ID 2" line.long 0x2C "APBADDR_ROMV8_ROM_COMPONID3_VAL,ROM Component ID 3" tree.end tree.end tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "CBASS" base ad:0x0 sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "CBASS_DBG0_ERR" base ad:0x200000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,The interrupt raw status register indicates if there is null interrupt regardless of interrupt enable" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,The interrupt status register is gated by the interrupt enable" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Only when this register is set. null access will cause interrupt to be generated." bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Setting this register disables the null interrupt generation" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,Writing to EOI Register indicates that current interrupt has been serviced which then allows next interrupt to be generated" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,End Of Interrupt Register" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "CBASS_INFRA1_ERR" base ad:0x210000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,The interrupt raw status register indicates if there is null interrupt regardless of interrupt enable" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,The interrupt status register is gated by the interrupt enable" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Only when this register is set. null access will cause interrupt to be generated." bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Setting this register disables the null interrupt generation" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,Writing to EOI Register indicates that current interrupt has been serviced which then allows next interrupt to be generated" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,End Of Interrupt Register" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "CBASS_FW0_ERR" base ad:0x220000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,The interrupt raw status register indicates if there is null interrupt regardless of interrupt enable" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,The interrupt status register is gated by the interrupt enable" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Only when this register is set. null access will cause interrupt to be generated." bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Setting this register disables the null interrupt generation" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,Writing to EOI Register indicates that current interrupt has been serviced which then allows next interrupt to be generated" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,End Of Interrupt Register" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "CBASS_MCASP0_ERR" base ad:0x240000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,The interrupt raw status register indicates if there is null interrupt regardless of interrupt enable" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,The interrupt status register is gated by the interrupt enable" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Only when this register is set. null access will cause interrupt to be generated." bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Setting this register disables the null interrupt generation" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,Writing to EOI Register indicates that current interrupt has been serviced which then allows next interrupt to be generated" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,End Of Interrupt Register" tree.end endif tree "CBASS_MISC_PERI0_ERR" base ad:0x201F0000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,The interrupt raw status register indicates if there is null interrupt regardless of interrupt enable" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,The interrupt status register is gated by the interrupt enable" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Only when this register is set. null access will cause interrupt to be generated." bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Setting this register disables the null interrupt generation" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,Writing to EOI Register indicates that current interrupt has been serviced which then allows next interrupt to be generated" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,End Of Interrupt Register" tree.end sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "CBASS_CENTRAL2" base ad:0x0 tree "CBASS_CENTRAL2_ERR" base ad:0x3F012000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,The interrupt raw status register indicates if there is null interrupt regardless of interrupt enable" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,The interrupt status register is gated by the interrupt enable" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Only when this register is set. null access will cause interrupt to be generated." bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Setting this register disables the null interrupt generation" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,Writing to EOI Register indicates that current interrupt has been serviced which then allows next interrupt to be generated" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,End Of Interrupt Register" tree.end tree "CBASS_CENTRAL2_FW" base ad:0x45010000 group.long 0x800++0x7F line.long 0x0 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." tree.end tree "CBASS_CENTRAL2_GLB" base ad:0x45B04000 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "CBASS_IPCSS0" base ad:0x0 tree "CBASS_IPCSS0_ERR" base ad:0x230000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,The interrupt raw status register indicates if there is null interrupt regardless of interrupt enable" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,The interrupt status register is gated by the interrupt enable" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Only when this register is set. null access will cause interrupt to be generated." bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Setting this register disables the null interrupt generation" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,Writing to EOI Register indicates that current interrupt has been serviced which then allows next interrupt to be generated" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,End Of Interrupt Register" tree.end tree "CBASS_IPCSS0_FW" base ad:0x45028000 group.long 0x0++0xFF line.long 0x0 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 4 firewall." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 4 firewall." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 4 firewall." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 4 firewall." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 5 firewall." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 5 firewall." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 5 firewall." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 5 firewall." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 6 firewall." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 6 firewall." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 6 firewall." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 6 firewall." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 7 firewall." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 7 firewall." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 7 firewall." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_Idmss_am62a_main_0_ipcss_vbm_dst_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62a_main_0.ipcss_vbm_dst region 7 firewall." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x400++0xFF line.long 0x0 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 4 firewall." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 4 firewall." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 4 firewall." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 4 firewall." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 5 firewall." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 5 firewall." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 5 firewall." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 5 firewall." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 6 firewall." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 6 firewall." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 6 firewall." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 6 firewall." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 7 firewall." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 7 firewall." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 7 firewall." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_Isa3ss_am62a_main_0_ipcss_vbm_dst_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62a_main_0.ipcss_vbm_dst region 7 firewall." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." tree.end tree "CBASS_IPCSS0_GLB" base ad:0x45B01000 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree.end endif tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "CBASS0" base ad:0x0 tree "CBASS0_ERR" base ad:0x3A000000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,The interrupt raw status register indicates if there is null interrupt regardless of interrupt enable" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,The interrupt status register is gated by the interrupt enable" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Only when this register is set. null access will cause interrupt to be generated." bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Setting this register disables the null interrupt generation" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,Writing to EOI Register indicates that current interrupt has been serviced which then allows next interrupt to be generated" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,End Of Interrupt Register" tree.end tree "CBASS0_FW" base ad:0x45000000 group.long 0x0++0xFF line.long 0x0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 4 firewall." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 4 firewall." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 4 firewall." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 4 firewall." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 5 firewall." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 5 firewall." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 5 firewall." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 5 firewall." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 6 firewall." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 6 firewall." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 6 firewall." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 6 firewall." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 7 firewall." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 7 firewall." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 7 firewall." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_hpt_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss_hpt region 7 firewall." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x400++0x1FF line.long 0x0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 4 firewall." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 4 firewall." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 4 firewall." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 4 firewall." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 5 firewall." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 5 firewall." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 5 firewall." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 5 firewall." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 6 firewall." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 6 firewall." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 6 firewall." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 6 firewall." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 7 firewall." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 7 firewall." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 7 firewall." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 7 firewall." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x100 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_8_control,The FW Region 8 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 8 firewall." bitfld.long 0x100 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x100 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x100 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x100 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x104 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_8_permission_0,The FW Region 8 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 8 firewall." hexmask.long.byte 0x104 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x104 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x104 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x104 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x104 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x104 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x104 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x104 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x104 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x104 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x104 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x104 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x104 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x104 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x104 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x108 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_8_permission_1,The FW Region 8 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 8 firewall." hexmask.long.byte 0x108 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x108 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x108 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x108 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x108 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x108 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x108 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x108 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x108 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x108 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x108 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x108 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x108 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x108 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x108 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_8_permission_2,The FW Region 8 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 8 firewall." hexmask.long.byte 0x10C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x10C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x10C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x10C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x10C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x10C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x10C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x10C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x10C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x10C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x10C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x10C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x10C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x110 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_8_start_address_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 8 firewall." hexmask.long.tbyte 0x110 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x110 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x114 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_8_start_address_h,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 8 firewall." hexmask.long.word 0x114 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x118 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_8_end_address_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 8 firewall." hexmask.long.tbyte 0x118 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x118 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x11C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_8_end_address_h,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 8 firewall." hexmask.long.word 0x11C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x120 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_9_control,The FW Region 9 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 9 firewall." bitfld.long 0x120 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x120 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x120 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x120 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x124 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_9_permission_0,The FW Region 9 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 9 firewall." hexmask.long.byte 0x124 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x124 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x124 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x124 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x124 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x124 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x124 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x124 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x124 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x124 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x124 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x124 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x124 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x124 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x124 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x128 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_9_permission_1,The FW Region 9 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 9 firewall." hexmask.long.byte 0x128 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x128 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x128 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x128 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x128 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x128 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x128 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x128 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x128 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x128 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x128 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x128 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x128 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x128 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x128 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x12C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_9_permission_2,The FW Region 9 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 9 firewall." hexmask.long.byte 0x12C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x12C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x12C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x12C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x12C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x12C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x12C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x12C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x12C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x12C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x12C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x12C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x12C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x130 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_9_start_address_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 9 firewall." hexmask.long.tbyte 0x130 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x130 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x134 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_9_start_address_h,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 9 firewall." hexmask.long.word 0x134 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x138 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_9_end_address_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 9 firewall." hexmask.long.tbyte 0x138 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x138 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x13C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_9_end_address_h,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 9 firewall." hexmask.long.word 0x13C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x140 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_10_control,The FW Region 10 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 10 firewall." bitfld.long 0x140 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x140 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x140 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x140 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x144 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_10_permission_0,The FW Region 10 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 10 firewall." hexmask.long.byte 0x144 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x144 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x144 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x144 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x144 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x144 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x144 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x144 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x144 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x144 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x144 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x144 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x144 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x144 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x144 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x148 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_10_permission_1,The FW Region 10 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 10 firewall." hexmask.long.byte 0x148 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x148 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x148 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x148 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x148 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x148 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x148 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x148 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x148 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x148 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x148 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x148 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x148 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x148 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x148 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x14C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_10_permission_2,The FW Region 10 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 10 firewall." hexmask.long.byte 0x14C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x14C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x14C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x14C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x14C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x14C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x14C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x14C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x14C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x14C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x14C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x14C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x14C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x150 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_10_start_address_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 10 firewall." hexmask.long.tbyte 0x150 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x150 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x154 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_10_start_address_h,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 10 firewall." hexmask.long.word 0x154 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x158 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_10_end_address_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 10 firewall." hexmask.long.tbyte 0x158 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x158 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x15C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_10_end_address_h,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 10 firewall." hexmask.long.word 0x15C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x160 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_11_control,The FW Region 11 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 11 firewall." bitfld.long 0x160 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x160 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x160 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x160 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x164 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_11_permission_0,The FW Region 11 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 11 firewall." hexmask.long.byte 0x164 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x164 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x164 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x164 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x164 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x164 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x164 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x164 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x164 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x164 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x164 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x164 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x164 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x164 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x164 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x168 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_11_permission_1,The FW Region 11 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 11 firewall." hexmask.long.byte 0x168 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x168 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x168 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x168 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x168 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x168 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x168 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x168 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x168 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x168 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x168 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x168 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x168 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x168 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x168 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x16C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_11_permission_2,The FW Region 11 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 11 firewall." hexmask.long.byte 0x16C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x16C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x16C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x16C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x16C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x16C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x16C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x16C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x16C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x16C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x16C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x16C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x16C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x170 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_11_start_address_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 11 firewall." hexmask.long.tbyte 0x170 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x170 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x174 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_11_start_address_h,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 11 firewall." hexmask.long.word 0x174 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x178 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_11_end_address_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 11 firewall." hexmask.long.tbyte 0x178 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x178 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x17C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_11_end_address_h,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 11 firewall." hexmask.long.word 0x17C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x180 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_12_control,The FW Region 12 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 12 firewall." bitfld.long 0x180 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x180 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x180 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x180 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x184 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_12_permission_0,The FW Region 12 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 12 firewall." hexmask.long.byte 0x184 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x184 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x184 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x184 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x184 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x184 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x184 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x184 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x184 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x184 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x184 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x184 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x184 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x184 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x184 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x188 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_12_permission_1,The FW Region 12 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 12 firewall." hexmask.long.byte 0x188 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x188 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x188 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x188 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x188 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x188 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x188 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x188 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x188 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x188 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x188 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x188 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x188 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x188 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x188 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x18C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_12_permission_2,The FW Region 12 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 12 firewall." hexmask.long.byte 0x18C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x18C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x18C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x18C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x18C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x18C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x18C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x18C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x18C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x18C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x18C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x18C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x18C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x190 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_12_start_address_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 12 firewall." hexmask.long.tbyte 0x190 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x190 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x194 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_12_start_address_h,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 12 firewall." hexmask.long.word 0x194 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x198 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_12_end_address_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 12 firewall." hexmask.long.tbyte 0x198 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x198 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x19C "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_12_end_address_h,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 12 firewall." hexmask.long.word 0x19C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1A0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_13_control,The FW Region 13 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 13 firewall." bitfld.long 0x1A0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x1A0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1A0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x1A0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1A4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_13_permission_0,The FW Region 13 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 13 firewall." hexmask.long.byte 0x1A4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1A4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1A4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1A4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1A8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_13_permission_1,The FW Region 13 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 13 firewall." hexmask.long.byte 0x1A8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1A8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1A8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1A8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1AC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_13_permission_2,The FW Region 13 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 13 firewall." hexmask.long.byte 0x1AC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1AC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1AC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1AC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1AC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1AC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1B0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_13_start_address_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 13 firewall." hexmask.long.tbyte 0x1B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x1B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1B4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_13_start_address_h,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 13 firewall." hexmask.long.word 0x1B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1B8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_13_end_address_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 13 firewall." hexmask.long.tbyte 0x1B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x1B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1BC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_13_end_address_h,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 13 firewall." hexmask.long.word 0x1BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1C0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_14_control,The FW Region 14 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 14 firewall." bitfld.long 0x1C0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x1C0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1C0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x1C0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1C4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_14_permission_0,The FW Region 14 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 14 firewall." hexmask.long.byte 0x1C4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1C4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1C4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1C4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1C8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_14_permission_1,The FW Region 14 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 14 firewall." hexmask.long.byte 0x1C8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1C8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1C8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1C8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1CC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_14_permission_2,The FW Region 14 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 14 firewall." hexmask.long.byte 0x1CC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1CC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1CC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1CC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1CC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1CC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1D0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_14_start_address_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 14 firewall." hexmask.long.tbyte 0x1D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x1D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1D4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_14_start_address_h,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 14 firewall." hexmask.long.word 0x1D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1D8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_14_end_address_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 14 firewall." hexmask.long.tbyte 0x1D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x1D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1DC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_14_end_address_h,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 14 firewall." hexmask.long.word 0x1DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1E0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_15_control,The FW Region 15 Control Register defines the control fields for the slave Isam62a_ddr_wrap_main_0.ddrss region 15 firewall." bitfld.long 0x1E0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x1E0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1E0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x1E0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1E4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_15_permission_0,The FW Region 15 Permission 0 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 15 firewall." hexmask.long.byte 0x1E4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1E4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1E4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1E4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1E8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_15_permission_1,The FW Region 15 Permission 1 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 15 firewall." hexmask.long.byte 0x1E8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1E8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1E8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1E8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1EC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_15_permission_2,The FW Region 15 Permission 2 Register defines the permissions for the slave Isam62a_ddr_wrap_main_0.ddrss region 15 firewall." hexmask.long.byte 0x1EC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1EC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1EC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1EC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1EC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1EC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1F0 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_15_start_address_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_ddr_wrap_main_0.ddrss region 15 firewall." hexmask.long.tbyte 0x1F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x1F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1F4 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_15_start_address_h,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_ddr_wrap_main_0.ddrss region 15 firewall." hexmask.long.word 0x1F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1F8 "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_15_end_address_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 15 firewall." hexmask.long.tbyte 0x1F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x1F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1FC "FW_REGS_Isam62a_ddr_wrap_main_0_ddrss_fw_region_15_end_address_h,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_ddr_wrap_main_0.ddrss region 15 firewall." hexmask.long.word 0x1FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x800++0xFF line.long 0x0 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 0.." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 0.." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 0.." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region.." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 1.." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 1.." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 1.." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region.." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 2.." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 2.." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 2.." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region.." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 3.." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 3.." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 3.." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region.." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 4.." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 4.." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 4.." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region.." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 5.." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 5.." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 5.." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region.." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 6.." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 6.." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 6.." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region.." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 7.." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 7.." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 7.." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region.." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0xC00++0x7F line.long 0x0 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x1000++0xFF line.long 0x0 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 4 firewall." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 4 firewall." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 4 firewall." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 4 firewall." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 5 firewall." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 5 firewall." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 5 firewall." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 5 firewall." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 6 firewall." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 6 firewall." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 6 firewall." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 6 firewall." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 7 firewall." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 7 firewall." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 7 firewall." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_Isam62a_c7xv_wrap_main_0_soc_c7xv_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_c7xv_wrap_main_0.soc_c7xv region 7 firewall." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x1400++0xFF line.long 0x0 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Isam62a_vpac_wrap_main_0.mem_slv region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Isam62a_vpac_wrap_main_0.mem_slv region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Isam62a_vpac_wrap_main_0.mem_slv region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Isam62a_vpac_wrap_main_0.mem_slv region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Isam62a_vpac_wrap_main_0.mem_slv region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 4 firewall." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 4 firewall." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 4 firewall." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 4 firewall." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Isam62a_vpac_wrap_main_0.mem_slv region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 5 firewall." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 5 firewall." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 5 firewall." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 5 firewall." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Isam62a_vpac_wrap_main_0.mem_slv region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 6 firewall." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 6 firewall." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 6 firewall." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 6 firewall." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Isam62a_vpac_wrap_main_0.mem_slv region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.mem_slv region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 7 firewall." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_vpac_wrap_main_0.mem_slv region 7 firewall." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 7 firewall." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_Isam62a_vpac_wrap_main_0_mem_slv_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_vpac_wrap_main_0.mem_slv region 7 firewall." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x1800++0xFF line.long 0x0 "FW_REGS_Igpmc_main_0_gpmc_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Igpmc_main_0.gpmc region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_Igpmc_main_0_gpmc_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Igpmc_main_0.gpmc region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_Igpmc_main_0_gpmc_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Igpmc_main_0.gpmc region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_Igpmc_main_0_gpmc_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Igpmc_main_0.gpmc region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_Igpmc_main_0_gpmc_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Igpmc_main_0.gpmc region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_Igpmc_main_0_gpmc_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Igpmc_main_0.gpmc region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_Igpmc_main_0_gpmc_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Igpmc_main_0.gpmc region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_Igpmc_main_0_gpmc_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Igpmc_main_0.gpmc region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_Igpmc_main_0_gpmc_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Igpmc_main_0.gpmc region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_Igpmc_main_0_gpmc_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Igpmc_main_0.gpmc region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_Igpmc_main_0_gpmc_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Igpmc_main_0.gpmc region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_Igpmc_main_0_gpmc_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Igpmc_main_0.gpmc region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_Igpmc_main_0_gpmc_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Igpmc_main_0.gpmc region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_Igpmc_main_0_gpmc_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Igpmc_main_0.gpmc region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_Igpmc_main_0_gpmc_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Igpmc_main_0.gpmc region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_Igpmc_main_0_gpmc_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Igpmc_main_0.gpmc region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_Igpmc_main_0_gpmc_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Igpmc_main_0.gpmc region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_Igpmc_main_0_gpmc_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Igpmc_main_0.gpmc region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_Igpmc_main_0_gpmc_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Igpmc_main_0.gpmc region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_Igpmc_main_0_gpmc_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Igpmc_main_0.gpmc region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_Igpmc_main_0_gpmc_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Igpmc_main_0.gpmc region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_Igpmc_main_0_gpmc_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Igpmc_main_0.gpmc region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_Igpmc_main_0_gpmc_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Igpmc_main_0.gpmc region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_Igpmc_main_0_gpmc_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Igpmc_main_0.gpmc region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_Igpmc_main_0_gpmc_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Igpmc_main_0.gpmc region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_Igpmc_main_0_gpmc_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Igpmc_main_0.gpmc region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_Igpmc_main_0_gpmc_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Igpmc_main_0.gpmc region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_Igpmc_main_0_gpmc_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Igpmc_main_0.gpmc region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_Igpmc_main_0_gpmc_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Igpmc_main_0.gpmc region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_Igpmc_main_0_gpmc_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Igpmc_main_0.gpmc region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_Igpmc_main_0_gpmc_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Igpmc_main_0.gpmc region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_Igpmc_main_0_gpmc_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Igpmc_main_0.gpmc region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_Igpmc_main_0_gpmc_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Igpmc_main_0.gpmc region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_Igpmc_main_0_gpmc_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Igpmc_main_0.gpmc region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_Igpmc_main_0_gpmc_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Igpmc_main_0.gpmc region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_Igpmc_main_0_gpmc_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Igpmc_main_0.gpmc region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_Igpmc_main_0_gpmc_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Igpmc_main_0.gpmc region 4 firewall." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_Igpmc_main_0_gpmc_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Igpmc_main_0.gpmc region 4 firewall." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_Igpmc_main_0_gpmc_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Igpmc_main_0.gpmc region 4 firewall." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_Igpmc_main_0_gpmc_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Igpmc_main_0.gpmc region 4 firewall." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_Igpmc_main_0_gpmc_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Igpmc_main_0.gpmc region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_Igpmc_main_0_gpmc_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Igpmc_main_0.gpmc region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_Igpmc_main_0_gpmc_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Igpmc_main_0.gpmc region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_Igpmc_main_0_gpmc_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Igpmc_main_0.gpmc region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_Igpmc_main_0_gpmc_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Igpmc_main_0.gpmc region 5 firewall." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_Igpmc_main_0_gpmc_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Igpmc_main_0.gpmc region 5 firewall." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_Igpmc_main_0_gpmc_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Igpmc_main_0.gpmc region 5 firewall." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_Igpmc_main_0_gpmc_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Igpmc_main_0.gpmc region 5 firewall." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_Igpmc_main_0_gpmc_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Igpmc_main_0.gpmc region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_Igpmc_main_0_gpmc_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Igpmc_main_0.gpmc region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_Igpmc_main_0_gpmc_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Igpmc_main_0.gpmc region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_Igpmc_main_0_gpmc_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Igpmc_main_0.gpmc region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_Igpmc_main_0_gpmc_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Igpmc_main_0.gpmc region 6 firewall." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_Igpmc_main_0_gpmc_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Igpmc_main_0.gpmc region 6 firewall." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_Igpmc_main_0_gpmc_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Igpmc_main_0.gpmc region 6 firewall." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_Igpmc_main_0_gpmc_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Igpmc_main_0.gpmc region 6 firewall." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_Igpmc_main_0_gpmc_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Igpmc_main_0.gpmc region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_Igpmc_main_0_gpmc_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Igpmc_main_0.gpmc region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_Igpmc_main_0_gpmc_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Igpmc_main_0.gpmc region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_Igpmc_main_0_gpmc_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Igpmc_main_0.gpmc region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_Igpmc_main_0_gpmc_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Igpmc_main_0.gpmc region 7 firewall." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_Igpmc_main_0_gpmc_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Igpmc_main_0.gpmc region 7 firewall." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_Igpmc_main_0_gpmc_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Igpmc_main_0.gpmc region 7 firewall." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_Igpmc_main_0_gpmc_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Igpmc_main_0.gpmc region 7 firewall." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x1C00++0xFF line.long 0x0 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Ifss_ul_main_0.fss_s0 region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Ifss_ul_main_0.fss_s0 region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Ifss_ul_main_0.fss_s0 region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ifss_ul_main_0.fss_s0 region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Ifss_ul_main_0.fss_s0 region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Ifss_ul_main_0.fss_s0 region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Ifss_ul_main_0.fss_s0 region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Ifss_ul_main_0.fss_s0 region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ifss_ul_main_0.fss_s0 region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Ifss_ul_main_0.fss_s0 region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Ifss_ul_main_0.fss_s0 region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Ifss_ul_main_0.fss_s0 region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Ifss_ul_main_0.fss_s0 region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ifss_ul_main_0.fss_s0 region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Ifss_ul_main_0.fss_s0 region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Ifss_ul_main_0.fss_s0 region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Ifss_ul_main_0.fss_s0 region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Ifss_ul_main_0.fss_s0 region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ifss_ul_main_0.fss_s0 region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Ifss_ul_main_0.fss_s0 region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Ifss_ul_main_0.fss_s0 region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Ifss_ul_main_0.fss_s0 region 4 firewall." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Ifss_ul_main_0.fss_s0 region 4 firewall." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ifss_ul_main_0.fss_s0 region 4 firewall." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Ifss_ul_main_0.fss_s0 region 4 firewall." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Ifss_ul_main_0.fss_s0 region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Ifss_ul_main_0.fss_s0 region 5 firewall." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Ifss_ul_main_0.fss_s0 region 5 firewall." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ifss_ul_main_0.fss_s0 region 5 firewall." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Ifss_ul_main_0.fss_s0 region 5 firewall." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Ifss_ul_main_0.fss_s0 region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Ifss_ul_main_0.fss_s0 region 6 firewall." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Ifss_ul_main_0.fss_s0 region 6 firewall." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ifss_ul_main_0.fss_s0 region 6 firewall." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Ifss_ul_main_0.fss_s0 region 6 firewall." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Ifss_ul_main_0.fss_s0 region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Ifss_ul_main_0.fss_s0 region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Ifss_ul_main_0.fss_s0 region 7 firewall." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Ifss_ul_main_0.fss_s0 region 7 firewall." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ifss_ul_main_0.fss_s0 region 7 firewall." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_Ifss_ul_main_0_fss_s0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Ifss_ul_main_0.fss_s0 region 7 firewall." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x2000++0x1FF line.long 0x0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 0.." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 1.." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 2.." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 3.." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 4.." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 5.." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 6.." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 7.." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x100 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_8_control,The FW Region 8 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 8.." bitfld.long 0x100 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x100 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x100 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x100 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x104 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_8_permission_0,The FW Region 8 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x104 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x104 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x104 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x104 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x104 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x104 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x104 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x104 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x104 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x104 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x104 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x104 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x104 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x104 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x104 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x108 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_8_permission_1,The FW Region 8 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x108 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x108 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x108 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x108 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x108 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x108 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x108 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x108 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x108 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x108 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x108 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x108 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x108 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x108 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x108 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_8_permission_2,The FW Region 8 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x10C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x10C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x10C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x10C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x10C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x10C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x10C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x10C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x10C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x10C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x10C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x10C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x10C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x110 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_8_start_address_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x110 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x110 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x114 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_8_start_address_h,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x114 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x118 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_8_end_address_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x118 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x118 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x11C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_8_end_address_h,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x11C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x120 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_9_control,The FW Region 9 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 9.." bitfld.long 0x120 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x120 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x120 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x120 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x124 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_9_permission_0,The FW Region 9 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x124 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x124 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x124 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x124 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x124 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x124 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x124 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x124 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x124 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x124 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x124 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x124 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x124 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x124 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x124 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x128 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_9_permission_1,The FW Region 9 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x128 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x128 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x128 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x128 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x128 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x128 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x128 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x128 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x128 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x128 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x128 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x128 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x128 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x128 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x128 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x12C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_9_permission_2,The FW Region 9 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region.." hexmask.long.byte 0x12C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x12C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x12C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x12C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x12C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x12C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x12C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x12C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x12C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x12C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x12C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x12C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x12C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x130 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_9_start_address_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x130 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x130 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x134 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_9_start_address_h,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x134 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x138 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_9_end_address_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x138 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x138 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x13C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_9_end_address_h,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x13C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x140 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_10_control,The FW Region 10 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 10.." bitfld.long 0x140 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x140 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x140 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x140 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x144 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_10_permission_0,The FW Region 10 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x144 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x144 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x144 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x144 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x144 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x144 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x144 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x144 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x144 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x144 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x144 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x144 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x144 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x144 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x144 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x148 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_10_permission_1,The FW Region 10 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x148 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x148 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x148 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x148 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x148 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x148 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x148 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x148 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x148 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x148 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x148 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x148 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x148 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x148 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x148 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x14C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_10_permission_2,The FW Region 10 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x14C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x14C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x14C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x14C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x14C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x14C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x14C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x14C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x14C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x14C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x14C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x14C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x14C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x150 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_10_start_address_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x150 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x150 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x154 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_10_start_address_h,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x154 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x158 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_10_end_address_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x158 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x158 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x15C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_10_end_address_h,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x15C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x160 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_11_control,The FW Region 11 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 11.." bitfld.long 0x160 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x160 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x160 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x160 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x164 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_11_permission_0,The FW Region 11 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x164 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x164 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x164 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x164 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x164 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x164 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x164 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x164 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x164 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x164 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x164 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x164 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x164 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x164 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x164 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x168 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_11_permission_1,The FW Region 11 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x168 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x168 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x168 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x168 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x168 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x168 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x168 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x168 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x168 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x168 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x168 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x168 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x168 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x168 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x168 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x16C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_11_permission_2,The FW Region 11 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x16C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x16C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x16C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x16C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x16C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x16C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x16C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x16C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x16C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x16C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x16C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x16C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x16C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x170 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_11_start_address_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x170 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x170 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x174 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_11_start_address_h,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x174 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x178 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_11_end_address_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x178 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x178 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x17C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_11_end_address_h,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x17C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x180 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_12_control,The FW Region 12 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 12.." bitfld.long 0x180 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x180 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x180 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x180 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x184 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_12_permission_0,The FW Region 12 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x184 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x184 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x184 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x184 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x184 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x184 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x184 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x184 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x184 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x184 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x184 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x184 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x184 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x184 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x184 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x188 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_12_permission_1,The FW Region 12 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x188 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x188 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x188 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x188 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x188 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x188 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x188 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x188 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x188 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x188 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x188 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x188 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x188 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x188 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x188 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x18C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_12_permission_2,The FW Region 12 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x18C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x18C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x18C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x18C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x18C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x18C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x18C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x18C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x18C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x18C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x18C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x18C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x18C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x190 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_12_start_address_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x190 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x190 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x194 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_12_start_address_h,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x194 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x198 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_12_end_address_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x198 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x198 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x19C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_12_end_address_h,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x19C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1A0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_13_control,The FW Region 13 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 13.." bitfld.long 0x1A0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x1A0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1A0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x1A0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1A4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_13_permission_0,The FW Region 13 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x1A4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1A4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1A4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1A4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1A8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_13_permission_1,The FW Region 13 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x1A8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1A8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1A8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1A8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1AC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_13_permission_2,The FW Region 13 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x1AC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1AC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1AC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1AC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1AC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1AC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1B0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_13_start_address_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x1B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x1B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1B4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_13_start_address_h,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x1B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1B8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_13_end_address_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x1B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x1B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1BC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_13_end_address_h,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x1BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1C0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_14_control,The FW Region 14 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 14.." bitfld.long 0x1C0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x1C0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1C0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x1C0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1C4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_14_permission_0,The FW Region 14 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x1C4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1C4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1C4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1C4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1C8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_14_permission_1,The FW Region 14 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x1C8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1C8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1C8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1C8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1CC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_14_permission_2,The FW Region 14 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x1CC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1CC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1CC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1CC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1CC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1CC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1D0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_14_start_address_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x1D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x1D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1D4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_14_start_address_h,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x1D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1D8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_14_end_address_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x1D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x1D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1DC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_14_end_address_h,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x1DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1E0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_15_control,The FW Region 15 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv region 15.." bitfld.long 0x1E0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x1E0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1E0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x1E0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1E4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_15_permission_0,The FW Region 15 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x1E4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1E4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1E4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1E4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1E8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_15_permission_1,The FW Region 15 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x1E8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1E8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1E8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1E8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1EC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_15_permission_2,The FW Region 15 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0.slv.." hexmask.long.byte 0x1EC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1EC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1EC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1EC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1EC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1EC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1F0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_15_start_address_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x1F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x1F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1F4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_15_start_address_h,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x1F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1F8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_15_end_address_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x1F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x1F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1FC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_misc_peri_cbass_data_l0_fw_region_15_end_address_h,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x1FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x2400++0x5FF line.long 0x0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x100 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_control,The FW Region 8 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall." bitfld.long 0x100 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x100 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x100 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x100 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x104 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_permission_0,The FW Region 8 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall." hexmask.long.byte 0x104 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x104 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x104 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x104 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x104 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x104 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x104 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x104 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x104 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x104 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x104 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x104 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x104 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x104 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x104 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x108 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_permission_1,The FW Region 8 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall." hexmask.long.byte 0x108 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x108 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x108 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x108 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x108 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x108 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x108 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x108 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x108 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x108 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x108 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x108 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x108 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x108 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x108 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_permission_2,The FW Region 8 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall." hexmask.long.byte 0x10C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x10C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x10C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x10C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x10C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x10C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x10C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x10C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x10C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x10C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x10C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x10C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x10C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x110 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_start_address_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall." hexmask.long.tbyte 0x110 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x110 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x114 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_start_address_h,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall." hexmask.long.word 0x114 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x118 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_end_address_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall." hexmask.long.tbyte 0x118 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x118 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x11C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_end_address_h,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall." hexmask.long.word 0x11C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x120 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_control,The FW Region 9 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall." bitfld.long 0x120 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x120 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x120 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x120 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x124 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_permission_0,The FW Region 9 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall." hexmask.long.byte 0x124 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x124 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x124 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x124 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x124 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x124 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x124 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x124 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x124 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x124 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x124 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x124 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x124 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x124 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x124 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x128 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_permission_1,The FW Region 9 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall." hexmask.long.byte 0x128 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x128 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x128 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x128 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x128 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x128 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x128 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x128 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x128 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x128 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x128 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x128 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x128 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x128 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x128 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x12C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_permission_2,The FW Region 9 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall." hexmask.long.byte 0x12C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x12C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x12C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x12C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x12C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x12C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x12C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x12C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x12C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x12C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x12C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x12C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x12C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x130 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_start_address_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall." hexmask.long.tbyte 0x130 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x130 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x134 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_start_address_h,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall." hexmask.long.word 0x134 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x138 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_end_address_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall." hexmask.long.tbyte 0x138 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x138 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x13C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_end_address_h,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall." hexmask.long.word 0x13C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x140 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_control,The FW Region 10 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall." bitfld.long 0x140 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x140 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x140 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x140 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x144 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_permission_0,The FW Region 10 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall." hexmask.long.byte 0x144 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x144 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x144 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x144 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x144 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x144 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x144 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x144 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x144 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x144 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x144 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x144 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x144 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x144 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x144 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x148 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_permission_1,The FW Region 10 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall." hexmask.long.byte 0x148 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x148 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x148 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x148 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x148 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x148 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x148 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x148 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x148 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x148 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x148 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x148 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x148 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x148 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x148 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x14C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_permission_2,The FW Region 10 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall." hexmask.long.byte 0x14C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x14C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x14C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x14C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x14C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x14C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x14C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x14C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x14C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x14C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x14C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x14C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x14C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x150 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_start_address_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall." hexmask.long.tbyte 0x150 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x150 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x154 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_start_address_h,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall." hexmask.long.word 0x154 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x158 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_end_address_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall." hexmask.long.tbyte 0x158 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x158 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x15C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_end_address_h,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall." hexmask.long.word 0x15C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x160 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_control,The FW Region 11 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall." bitfld.long 0x160 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x160 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x160 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x160 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x164 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_permission_0,The FW Region 11 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall." hexmask.long.byte 0x164 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x164 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x164 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x164 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x164 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x164 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x164 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x164 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x164 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x164 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x164 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x164 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x164 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x164 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x164 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x168 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_permission_1,The FW Region 11 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall." hexmask.long.byte 0x168 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x168 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x168 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x168 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x168 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x168 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x168 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x168 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x168 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x168 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x168 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x168 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x168 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x168 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x168 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x16C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_permission_2,The FW Region 11 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall." hexmask.long.byte 0x16C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x16C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x16C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x16C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x16C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x16C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x16C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x16C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x16C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x16C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x16C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x16C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x16C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x170 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_start_address_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall." hexmask.long.tbyte 0x170 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x170 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x174 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_start_address_h,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall." hexmask.long.word 0x174 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x178 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_end_address_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall." hexmask.long.tbyte 0x178 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x178 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x17C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_end_address_h,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall." hexmask.long.word 0x17C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x180 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_control,The FW Region 12 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall." bitfld.long 0x180 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x180 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x180 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x180 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x184 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_permission_0,The FW Region 12 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall." hexmask.long.byte 0x184 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x184 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x184 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x184 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x184 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x184 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x184 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x184 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x184 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x184 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x184 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x184 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x184 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x184 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x184 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x188 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_permission_1,The FW Region 12 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall." hexmask.long.byte 0x188 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x188 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x188 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x188 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x188 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x188 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x188 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x188 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x188 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x188 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x188 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x188 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x188 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x188 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x188 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x18C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_permission_2,The FW Region 12 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall." hexmask.long.byte 0x18C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x18C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x18C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x18C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x18C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x18C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x18C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x18C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x18C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x18C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x18C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x18C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x18C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x190 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_start_address_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall." hexmask.long.tbyte 0x190 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x190 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x194 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_start_address_h,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall." hexmask.long.word 0x194 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x198 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_end_address_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall." hexmask.long.tbyte 0x198 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x198 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x19C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_end_address_h,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall." hexmask.long.word 0x19C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1A0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_control,The FW Region 13 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall." bitfld.long 0x1A0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x1A0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1A0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x1A0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1A4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_permission_0,The FW Region 13 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall." hexmask.long.byte 0x1A4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1A4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1A4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1A4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1A8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_permission_1,The FW Region 13 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall." hexmask.long.byte 0x1A8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1A8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1A8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1A8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1AC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_permission_2,The FW Region 13 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall." hexmask.long.byte 0x1AC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1AC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1AC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1AC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1AC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1AC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1B0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_start_address_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall." hexmask.long.tbyte 0x1B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x1B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1B4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_start_address_h,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall." hexmask.long.word 0x1B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1B8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_end_address_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall." hexmask.long.tbyte 0x1B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x1B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1BC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_end_address_h,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall." hexmask.long.word 0x1BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1C0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_control,The FW Region 14 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall." bitfld.long 0x1C0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x1C0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1C0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x1C0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1C4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_permission_0,The FW Region 14 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall." hexmask.long.byte 0x1C4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1C4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1C4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1C4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1C8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_permission_1,The FW Region 14 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall." hexmask.long.byte 0x1C8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1C8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1C8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1C8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1CC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_permission_2,The FW Region 14 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall." hexmask.long.byte 0x1CC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1CC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1CC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1CC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1CC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1CC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1D0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_start_address_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall." hexmask.long.tbyte 0x1D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x1D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1D4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_start_address_h,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall." hexmask.long.word 0x1D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1D8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_end_address_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall." hexmask.long.tbyte 0x1D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x1D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1DC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_end_address_h,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall." hexmask.long.word 0x1DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1E0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_control,The FW Region 15 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall." bitfld.long 0x1E0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x1E0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1E0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x1E0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1E4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_permission_0,The FW Region 15 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall." hexmask.long.byte 0x1E4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1E4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1E4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1E4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1E8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_permission_1,The FW Region 15 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall." hexmask.long.byte 0x1E8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1E8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1E8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1E8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1EC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_permission_2,The FW Region 15 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall." hexmask.long.byte 0x1EC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1EC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1EC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1EC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1EC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1EC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1F0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_start_address_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall." hexmask.long.tbyte 0x1F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x1F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1F4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_start_address_h,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall." hexmask.long.word 0x1F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1F8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_end_address_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall." hexmask.long.tbyte 0x1F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x1F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1FC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_end_address_h,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall." hexmask.long.word 0x1FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x200 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_control,The FW Region 16 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall." bitfld.long 0x200 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x200 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x200 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x200 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x204 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_permission_0,The FW Region 16 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall." hexmask.long.byte 0x204 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x204 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x204 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x204 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x204 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x204 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x204 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x204 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x204 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x204 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x204 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x204 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x204 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x204 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x204 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x204 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x204 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x208 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_permission_1,The FW Region 16 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall." hexmask.long.byte 0x208 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x208 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x208 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x208 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x208 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x208 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x208 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x208 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x208 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x208 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x208 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x208 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x208 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x208 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x208 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x208 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x208 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x20C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_permission_2,The FW Region 16 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall." hexmask.long.byte 0x20C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x20C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x20C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x20C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x20C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x20C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x20C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x20C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x20C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x20C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x20C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x20C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x20C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x20C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x20C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x20C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x20C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x210 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_start_address_l,The FW Region 16 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall." hexmask.long.tbyte 0x210 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x210 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x214 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_start_address_h,The FW Region 16 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall." hexmask.long.word 0x214 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x218 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_end_address_l,The FW Region 16 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall." hexmask.long.tbyte 0x218 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x218 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x21C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_end_address_h,The FW Region 16 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall." hexmask.long.word 0x21C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x220 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_control,The FW Region 17 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall." bitfld.long 0x220 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x220 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x220 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x220 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x224 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_permission_0,The FW Region 17 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall." hexmask.long.byte 0x224 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x224 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x224 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x224 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x224 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x224 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x224 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x224 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x224 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x224 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x224 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x224 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x224 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x224 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x224 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x224 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x224 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x228 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_permission_1,The FW Region 17 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall." hexmask.long.byte 0x228 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x228 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x228 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x228 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x228 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x228 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x228 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x228 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x228 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x228 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x228 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x228 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x228 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x228 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x228 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x228 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x228 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x22C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_permission_2,The FW Region 17 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall." hexmask.long.byte 0x22C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x22C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x22C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x22C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x22C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x22C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x22C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x22C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x22C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x22C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x22C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x22C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x22C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x22C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x22C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x22C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x22C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x230 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_start_address_l,The FW Region 17 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall." hexmask.long.tbyte 0x230 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x230 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x234 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_start_address_h,The FW Region 17 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall." hexmask.long.word 0x234 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x238 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_end_address_l,The FW Region 17 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall." hexmask.long.tbyte 0x238 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x238 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x23C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_end_address_h,The FW Region 17 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall." hexmask.long.word 0x23C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x240 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_control,The FW Region 18 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall." bitfld.long 0x240 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x240 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x240 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x240 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x244 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_permission_0,The FW Region 18 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall." hexmask.long.byte 0x244 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x244 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x244 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x244 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x244 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x244 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x244 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x244 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x244 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x244 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x244 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x244 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x244 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x244 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x244 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x244 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x244 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x248 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_permission_1,The FW Region 18 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall." hexmask.long.byte 0x248 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x248 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x248 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x248 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x248 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x248 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x248 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x248 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x248 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x248 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x248 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x248 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x248 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x248 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x248 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x248 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x248 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x24C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_permission_2,The FW Region 18 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall." hexmask.long.byte 0x24C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x24C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x24C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x24C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x24C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x250 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_start_address_l,The FW Region 18 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall." hexmask.long.tbyte 0x250 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x250 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x254 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_start_address_h,The FW Region 18 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall." hexmask.long.word 0x254 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x258 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_end_address_l,The FW Region 18 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall." hexmask.long.tbyte 0x258 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x258 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x25C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_end_address_h,The FW Region 18 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall." hexmask.long.word 0x25C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x260 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_control,The FW Region 19 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall." bitfld.long 0x260 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x260 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x260 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x260 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x264 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_permission_0,The FW Region 19 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall." hexmask.long.byte 0x264 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x264 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x264 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x264 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x264 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x264 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x264 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x264 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x264 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x264 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x264 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x264 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x264 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x264 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x264 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x264 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x264 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x268 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_permission_1,The FW Region 19 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall." hexmask.long.byte 0x268 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x268 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x268 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x268 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x268 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x268 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x268 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x268 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x268 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x268 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x268 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x268 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x268 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x268 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x268 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x268 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x268 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x26C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_permission_2,The FW Region 19 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall." hexmask.long.byte 0x26C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x26C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x26C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x26C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x26C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x26C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x26C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x26C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x26C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x26C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x26C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x26C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x26C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x26C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x26C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x26C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x26C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x270 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_start_address_l,The FW Region 19 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall." hexmask.long.tbyte 0x270 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x270 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x274 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_start_address_h,The FW Region 19 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall." hexmask.long.word 0x274 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x278 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_end_address_l,The FW Region 19 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall." hexmask.long.tbyte 0x278 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x278 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x27C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_end_address_h,The FW Region 19 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall." hexmask.long.word 0x27C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x280 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_control,The FW Region 20 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall." bitfld.long 0x280 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x280 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x280 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x280 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x284 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_permission_0,The FW Region 20 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall." hexmask.long.byte 0x284 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x284 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x284 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x284 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x284 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x284 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x284 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x284 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x284 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x284 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x284 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x284 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x284 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x284 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x284 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x284 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x284 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x288 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_permission_1,The FW Region 20 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall." hexmask.long.byte 0x288 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x288 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x288 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x288 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x288 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x288 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x288 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x288 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x288 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x288 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x288 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x288 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x288 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x288 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x288 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x288 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x288 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_permission_2,The FW Region 20 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall." hexmask.long.byte 0x28C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x28C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x28C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x28C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x28C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x290 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_start_address_l,The FW Region 20 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall." hexmask.long.tbyte 0x290 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x290 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x294 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_start_address_h,The FW Region 20 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall." hexmask.long.word 0x294 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x298 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_end_address_l,The FW Region 20 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall." hexmask.long.tbyte 0x298 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x298 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x29C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_end_address_h,The FW Region 20 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall." hexmask.long.word 0x29C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x2A0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_control,The FW Region 21 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall." bitfld.long 0x2A0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x2A0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x2A0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x2A0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x2A4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_permission_0,The FW Region 21 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall." hexmask.long.byte 0x2A4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2A4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2A4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2A4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2A4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2A4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2A8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_permission_1,The FW Region 21 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall." hexmask.long.byte 0x2A8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2A8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2A8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2A8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2A8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2A8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2AC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_permission_2,The FW Region 21 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall." hexmask.long.byte 0x2AC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2AC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2AC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2AC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2AC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2AC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2B0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_start_address_l,The FW Region 21 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall." hexmask.long.tbyte 0x2B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x2B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x2B4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_start_address_h,The FW Region 21 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall." hexmask.long.word 0x2B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x2B8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_end_address_l,The FW Region 21 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall." hexmask.long.tbyte 0x2B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x2B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x2BC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_end_address_h,The FW Region 21 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall." hexmask.long.word 0x2BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x2C0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_control,The FW Region 22 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall." bitfld.long 0x2C0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x2C0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x2C0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x2C0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x2C4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_permission_0,The FW Region 22 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall." hexmask.long.byte 0x2C4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2C4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_permission_1,The FW Region 22 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall." hexmask.long.byte 0x2C8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2C8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2CC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_permission_2,The FW Region 22 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall." hexmask.long.byte 0x2CC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2CC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2CC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2CC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2CC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2CC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2D0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_start_address_l,The FW Region 22 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall." hexmask.long.tbyte 0x2D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x2D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x2D4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_start_address_h,The FW Region 22 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall." hexmask.long.word 0x2D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x2D8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_end_address_l,The FW Region 22 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall." hexmask.long.tbyte 0x2D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x2D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x2DC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_end_address_h,The FW Region 22 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall." hexmask.long.word 0x2DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x2E0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_control,The FW Region 23 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall." bitfld.long 0x2E0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x2E0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x2E0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x2E0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x2E4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_permission_0,The FW Region 23 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall." hexmask.long.byte 0x2E4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2E4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2E4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2E4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2E4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2E4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2E8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_permission_1,The FW Region 23 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall." hexmask.long.byte 0x2E8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2E8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2E8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2E8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2E8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2E8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2EC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_permission_2,The FW Region 23 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall." hexmask.long.byte 0x2EC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2EC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2EC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2EC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2EC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2EC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2F0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_start_address_l,The FW Region 23 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall." hexmask.long.tbyte 0x2F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x2F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x2F4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_start_address_h,The FW Region 23 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall." hexmask.long.word 0x2F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x2F8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_end_address_l,The FW Region 23 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall." hexmask.long.tbyte 0x2F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x2F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x2FC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_end_address_h,The FW Region 23 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall." hexmask.long.word 0x2FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x300 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_24_control,The FW Region 24 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 24 firewall." bitfld.long 0x300 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x300 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x300 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x300 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x304 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_24_permission_0,The FW Region 24 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 24 firewall." hexmask.long.byte 0x304 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x304 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x304 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x304 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x304 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x304 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x304 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x304 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x304 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x304 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x304 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x304 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x304 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x304 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x304 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x304 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x304 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x308 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_24_permission_1,The FW Region 24 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 24 firewall." hexmask.long.byte 0x308 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x308 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x308 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x308 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x308 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x308 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x308 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x308 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x308 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x308 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x308 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x308 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x308 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x308 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x308 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x308 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x308 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_24_permission_2,The FW Region 24 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 24 firewall." hexmask.long.byte 0x30C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x30C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x30C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x30C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x30C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x30C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x30C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x30C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x30C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x30C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x30C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x30C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x30C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x30C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x30C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x30C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x30C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x310 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_24_start_address_l,The FW Region 24 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 24 firewall." hexmask.long.tbyte 0x310 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x310 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x314 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_24_start_address_h,The FW Region 24 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 24 firewall." hexmask.long.word 0x314 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x318 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_24_end_address_l,The FW Region 24 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 24 firewall." hexmask.long.tbyte 0x318 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x318 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x31C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_24_end_address_h,The FW Region 24 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 24 firewall." hexmask.long.word 0x31C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x320 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_25_control,The FW Region 25 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 25 firewall." bitfld.long 0x320 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x320 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x320 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x320 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x324 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_25_permission_0,The FW Region 25 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 25 firewall." hexmask.long.byte 0x324 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x324 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x324 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x324 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x324 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x324 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x324 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x324 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x324 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x324 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x324 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x324 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x324 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x324 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x324 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x324 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x324 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x328 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_25_permission_1,The FW Region 25 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 25 firewall." hexmask.long.byte 0x328 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x328 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x328 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x328 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x328 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x328 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x328 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x328 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x328 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x328 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x328 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x328 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x328 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x328 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x328 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x328 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x328 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x32C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_25_permission_2,The FW Region 25 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 25 firewall." hexmask.long.byte 0x32C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x32C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x32C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x32C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x32C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x32C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x32C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x32C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x32C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x32C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x32C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x32C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x32C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x32C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x32C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x32C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x32C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x330 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_25_start_address_l,The FW Region 25 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 25 firewall." hexmask.long.tbyte 0x330 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x330 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x334 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_25_start_address_h,The FW Region 25 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 25 firewall." hexmask.long.word 0x334 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x338 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_25_end_address_l,The FW Region 25 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 25 firewall." hexmask.long.tbyte 0x338 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x338 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x33C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_25_end_address_h,The FW Region 25 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 25 firewall." hexmask.long.word 0x33C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x340 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_26_control,The FW Region 26 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 26 firewall." bitfld.long 0x340 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x340 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x340 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x340 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x344 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_26_permission_0,The FW Region 26 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 26 firewall." hexmask.long.byte 0x344 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x344 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x344 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x344 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x344 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x344 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x344 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x344 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x344 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x344 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x344 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x344 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x344 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x344 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x344 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x344 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x344 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x348 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_26_permission_1,The FW Region 26 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 26 firewall." hexmask.long.byte 0x348 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x348 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x348 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x348 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x348 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x348 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x348 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x348 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x348 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x348 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x348 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x348 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x348 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x348 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x348 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x348 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x348 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x34C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_26_permission_2,The FW Region 26 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 26 firewall." hexmask.long.byte 0x34C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x34C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x34C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x34C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x34C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x34C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x34C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x34C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x34C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x34C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x34C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x34C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x34C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x34C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x34C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x34C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x34C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x350 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_26_start_address_l,The FW Region 26 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 26 firewall." hexmask.long.tbyte 0x350 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x350 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x354 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_26_start_address_h,The FW Region 26 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 26 firewall." hexmask.long.word 0x354 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x358 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_26_end_address_l,The FW Region 26 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 26 firewall." hexmask.long.tbyte 0x358 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x358 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x35C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_26_end_address_h,The FW Region 26 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 26 firewall." hexmask.long.word 0x35C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x360 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_27_control,The FW Region 27 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 27 firewall." bitfld.long 0x360 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x360 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x360 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x360 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x364 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_27_permission_0,The FW Region 27 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 27 firewall." hexmask.long.byte 0x364 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x364 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x364 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x364 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x364 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x364 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x364 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x364 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x364 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x364 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x364 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x364 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x364 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x364 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x364 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x364 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x364 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x368 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_27_permission_1,The FW Region 27 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 27 firewall." hexmask.long.byte 0x368 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x368 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x368 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x368 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x368 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x368 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x368 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x368 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x368 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x368 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x368 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x368 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x368 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x368 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x368 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x368 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x368 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x36C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_27_permission_2,The FW Region 27 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 27 firewall." hexmask.long.byte 0x36C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x36C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x36C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x36C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x36C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x36C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x36C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x36C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x36C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x36C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x36C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x36C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x36C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x36C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x36C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x36C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x36C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x370 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_27_start_address_l,The FW Region 27 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 27 firewall." hexmask.long.tbyte 0x370 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x370 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x374 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_27_start_address_h,The FW Region 27 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 27 firewall." hexmask.long.word 0x374 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x378 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_27_end_address_l,The FW Region 27 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 27 firewall." hexmask.long.tbyte 0x378 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x378 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x37C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_27_end_address_h,The FW Region 27 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 27 firewall." hexmask.long.word 0x37C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x380 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_28_control,The FW Region 28 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 28 firewall." bitfld.long 0x380 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x380 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x380 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x380 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x384 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_28_permission_0,The FW Region 28 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 28 firewall." hexmask.long.byte 0x384 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x384 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x384 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x384 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x384 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x384 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x384 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x384 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x384 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x384 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x384 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x384 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x384 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x384 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x384 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x384 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x384 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x388 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_28_permission_1,The FW Region 28 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 28 firewall." hexmask.long.byte 0x388 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x388 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x388 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x388 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x388 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x388 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x388 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x388 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x388 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x388 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x388 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x388 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x388 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x388 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x388 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x388 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x388 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x38C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_28_permission_2,The FW Region 28 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 28 firewall." hexmask.long.byte 0x38C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x38C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x38C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x38C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x38C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x38C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x38C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x38C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x38C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x38C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x38C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x38C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x38C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x38C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x38C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x38C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x38C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x390 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_28_start_address_l,The FW Region 28 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 28 firewall." hexmask.long.tbyte 0x390 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x390 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x394 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_28_start_address_h,The FW Region 28 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 28 firewall." hexmask.long.word 0x394 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x398 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_28_end_address_l,The FW Region 28 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 28 firewall." hexmask.long.tbyte 0x398 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x398 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x39C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_28_end_address_h,The FW Region 28 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 28 firewall." hexmask.long.word 0x39C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x3A0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_29_control,The FW Region 29 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 29 firewall." bitfld.long 0x3A0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x3A0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x3A0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x3A0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x3A4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_29_permission_0,The FW Region 29 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 29 firewall." hexmask.long.byte 0x3A4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x3A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x3A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x3A4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x3A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x3A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x3A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x3A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x3A4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x3A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x3A4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x3A4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x3A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x3A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3A4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x3A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x3A8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_29_permission_1,The FW Region 29 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 29 firewall." hexmask.long.byte 0x3A8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x3A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x3A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x3A8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x3A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x3A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x3A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x3A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x3A8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x3A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x3A8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x3A8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x3A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x3A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3A8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x3A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x3AC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_29_permission_2,The FW Region 29 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 29 firewall." hexmask.long.byte 0x3AC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x3AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x3AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x3AC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x3AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x3AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x3AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x3AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x3AC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x3AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x3AC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x3AC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x3AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x3AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3AC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x3AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x3B0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_29_start_address_l,The FW Region 29 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 29 firewall." hexmask.long.tbyte 0x3B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x3B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x3B4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_29_start_address_h,The FW Region 29 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 29 firewall." hexmask.long.word 0x3B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x3B8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_29_end_address_l,The FW Region 29 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 29 firewall." hexmask.long.tbyte 0x3B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x3B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3BC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_29_end_address_h,The FW Region 29 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 29 firewall." hexmask.long.word 0x3BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x3C0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_30_control,The FW Region 30 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 30 firewall." bitfld.long 0x3C0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x3C0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x3C0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x3C0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x3C4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_30_permission_0,The FW Region 30 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 30 firewall." hexmask.long.byte 0x3C4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x3C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x3C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x3C4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x3C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x3C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x3C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x3C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x3C4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x3C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x3C4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x3C4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x3C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x3C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3C4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x3C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x3C8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_30_permission_1,The FW Region 30 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 30 firewall." hexmask.long.byte 0x3C8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x3C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x3C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x3C8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x3C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x3C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x3C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x3C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x3C8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x3C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x3C8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x3C8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x3C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x3C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3C8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x3C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x3CC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_30_permission_2,The FW Region 30 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 30 firewall." hexmask.long.byte 0x3CC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x3CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x3CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x3CC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x3CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x3CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x3CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x3CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x3CC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x3CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x3CC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x3CC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x3CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x3CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3CC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x3CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x3D0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_30_start_address_l,The FW Region 30 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 30 firewall." hexmask.long.tbyte 0x3D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x3D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x3D4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_30_start_address_h,The FW Region 30 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 30 firewall." hexmask.long.word 0x3D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x3D8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_30_end_address_l,The FW Region 30 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 30 firewall." hexmask.long.tbyte 0x3D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x3D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3DC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_30_end_address_h,The FW Region 30 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 30 firewall." hexmask.long.word 0x3DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x3E0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_31_control,The FW Region 31 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 31 firewall." bitfld.long 0x3E0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x3E0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x3E0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x3E0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x3E4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_31_permission_0,The FW Region 31 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 31 firewall." hexmask.long.byte 0x3E4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x3E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x3E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x3E4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x3E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x3E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x3E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x3E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x3E4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x3E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x3E4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x3E4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x3E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x3E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3E4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x3E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x3E8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_31_permission_1,The FW Region 31 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 31 firewall." hexmask.long.byte 0x3E8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x3E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x3E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x3E8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x3E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x3E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x3E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x3E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x3E8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x3E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x3E8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x3E8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x3E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x3E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3E8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x3E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x3EC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_31_permission_2,The FW Region 31 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 31 firewall." hexmask.long.byte 0x3EC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x3EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x3EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x3EC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x3EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x3EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x3EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x3EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x3EC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x3EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x3EC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x3EC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x3EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x3EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x3EC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x3EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x3F0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_31_start_address_l,The FW Region 31 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 31 firewall." hexmask.long.tbyte 0x3F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x3F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x3F4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_31_start_address_h,The FW Region 31 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 31 firewall." hexmask.long.word 0x3F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x3F8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_31_end_address_l,The FW Region 31 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 31 firewall." hexmask.long.tbyte 0x3F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x3F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3FC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_31_end_address_h,The FW Region 31 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 31 firewall." hexmask.long.word 0x3FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x400 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall." bitfld.long 0x400 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x400 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x400 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x400 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x404 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall." hexmask.long.byte 0x404 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x404 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x404 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x404 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x404 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x404 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x404 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x404 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x404 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x404 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x404 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x404 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x404 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x404 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x404 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x404 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x404 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x408 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall." hexmask.long.byte 0x408 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x408 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x408 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x408 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x408 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x408 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x408 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x408 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x408 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x408 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x408 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x408 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x408 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x408 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x408 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x408 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x408 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x40C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall." hexmask.long.byte 0x40C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x40C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x40C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x40C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x40C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x40C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x40C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x40C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x40C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x40C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x40C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x40C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x40C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x40C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x40C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x40C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x40C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x410 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall." hexmask.long.tbyte 0x410 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x410 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x414 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall." hexmask.long.word 0x414 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x418 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall." hexmask.long.tbyte 0x418 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x418 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x41C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall." hexmask.long.word 0x41C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x420 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall." bitfld.long 0x420 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x420 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x420 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x420 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x424 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall." hexmask.long.byte 0x424 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x424 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x424 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x424 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x424 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x424 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x424 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x424 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x424 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x424 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x424 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x424 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x424 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x424 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x424 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x424 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x424 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x428 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall." hexmask.long.byte 0x428 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x428 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x428 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x428 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x428 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x428 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x428 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x428 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x428 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x428 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x428 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x428 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x428 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x428 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x428 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x428 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x428 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x42C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall." hexmask.long.byte 0x42C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x42C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x42C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x42C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x42C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x42C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x42C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x42C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x42C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x42C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x42C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x42C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x42C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x42C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x42C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x42C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x42C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x430 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall." hexmask.long.tbyte 0x430 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x430 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x434 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall." hexmask.long.word 0x434 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x438 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall." hexmask.long.tbyte 0x438 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x438 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x43C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall." hexmask.long.word 0x43C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x440 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall." bitfld.long 0x440 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x440 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x440 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x440 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x444 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall." hexmask.long.byte 0x444 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x444 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x444 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x444 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x444 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x444 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x444 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x444 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x444 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x444 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x444 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x444 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x444 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x444 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x444 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x444 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x444 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x448 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall." hexmask.long.byte 0x448 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x448 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x448 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x448 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x448 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x448 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x448 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x448 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x448 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x448 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x448 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x448 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x448 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x448 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x448 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x448 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x448 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x44C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall." hexmask.long.byte 0x44C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x44C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x44C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x44C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x44C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x450 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall." hexmask.long.tbyte 0x450 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x450 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x454 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall." hexmask.long.word 0x454 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x458 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall." hexmask.long.tbyte 0x458 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x458 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x45C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall." hexmask.long.word 0x45C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x460 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall." bitfld.long 0x460 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x460 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x460 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x460 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x464 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall." hexmask.long.byte 0x464 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x464 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x464 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x464 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x464 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x464 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x464 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x464 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x464 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x464 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x464 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x464 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x464 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x464 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x464 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x464 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x464 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x468 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall." hexmask.long.byte 0x468 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x468 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x468 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x468 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x468 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x468 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x468 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x468 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x468 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x468 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x468 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x468 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x468 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x468 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x468 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x468 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x468 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x46C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall." hexmask.long.byte 0x46C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x46C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x46C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x46C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x46C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x46C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x46C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x46C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x46C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x46C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x46C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x46C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x46C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x46C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x46C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x46C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x46C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x470 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall." hexmask.long.tbyte 0x470 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x470 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x474 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall." hexmask.long.word 0x474 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x478 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall." hexmask.long.tbyte 0x478 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x478 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x47C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall." hexmask.long.word 0x47C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x480 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall." bitfld.long 0x480 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x480 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x480 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x480 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x484 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall." hexmask.long.byte 0x484 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x484 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x484 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x484 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x484 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x484 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x484 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x484 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x484 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x484 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x484 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x484 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x484 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x484 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x484 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x484 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x484 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x488 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall." hexmask.long.byte 0x488 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x488 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x488 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x488 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x488 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x488 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x488 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x488 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x488 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x488 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x488 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x488 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x488 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x488 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x488 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x488 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x488 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall." hexmask.long.byte 0x48C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x48C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x48C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x48C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x48C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x490 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall." hexmask.long.tbyte 0x490 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x490 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x494 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall." hexmask.long.word 0x494 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x498 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall." hexmask.long.tbyte 0x498 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x498 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x49C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall." hexmask.long.word 0x49C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x4A0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall." bitfld.long 0x4A0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x4A0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x4A0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x4A0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4A4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall." hexmask.long.byte 0x4A4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4A4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4A4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4A4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4A4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4A4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4A8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall." hexmask.long.byte 0x4A8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4A8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4A8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4A8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4A8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4A8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4AC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall." hexmask.long.byte 0x4AC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4AC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4AC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4AC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4AC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4AC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4B0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall." hexmask.long.tbyte 0x4B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x4B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x4B4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall." hexmask.long.word 0x4B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x4B8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall." hexmask.long.tbyte 0x4B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x4B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x4BC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall." hexmask.long.word 0x4BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x4C0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall." bitfld.long 0x4C0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x4C0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x4C0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x4C0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4C4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall." hexmask.long.byte 0x4C4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4C4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall." hexmask.long.byte 0x4C8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4C8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4CC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall." hexmask.long.byte 0x4CC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4CC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4CC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4CC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4CC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4CC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4D0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall." hexmask.long.tbyte 0x4D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x4D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x4D4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall." hexmask.long.word 0x4D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x4D8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall." hexmask.long.tbyte 0x4D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x4D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x4DC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall." hexmask.long.word 0x4DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x4E0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall." bitfld.long 0x4E0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x4E0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x4E0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x4E0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4E4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall." hexmask.long.byte 0x4E4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4E4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4E4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4E4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4E4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4E4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4E8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall." hexmask.long.byte 0x4E8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4E8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4E8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4E8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4E8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4E8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4EC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall." hexmask.long.byte 0x4EC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4EC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4EC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4EC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4EC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4EC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4F0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall." hexmask.long.tbyte 0x4F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x4F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x4F4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall." hexmask.long.word 0x4F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x4F8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall." hexmask.long.tbyte 0x4F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x4F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x4FC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall." hexmask.long.word 0x4FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x500 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_8_control,The FW Region 8 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 8 firewall." bitfld.long 0x500 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x500 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x500 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x500 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x504 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_8_permission_0,The FW Region 8 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 8 firewall." hexmask.long.byte 0x504 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x504 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x504 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x504 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x504 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x504 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x504 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x504 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x504 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x504 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x504 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x504 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x504 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x504 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x504 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x504 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x504 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x508 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_8_permission_1,The FW Region 8 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 8 firewall." hexmask.long.byte 0x508 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x508 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x508 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x508 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x508 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x508 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x508 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x508 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x508 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x508 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x508 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x508 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x508 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x508 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x508 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x508 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x508 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_8_permission_2,The FW Region 8 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 8 firewall." hexmask.long.byte 0x50C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x50C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x50C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x50C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x50C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x50C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x50C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x50C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x50C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x50C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x50C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x50C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x50C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x50C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x50C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x50C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x50C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x510 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_8_start_address_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 8 firewall." hexmask.long.tbyte 0x510 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x510 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x514 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_8_start_address_h,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 8 firewall." hexmask.long.word 0x514 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x518 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_8_end_address_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 8 firewall." hexmask.long.tbyte 0x518 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x518 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x51C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_8_end_address_h,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 8 firewall." hexmask.long.word 0x51C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x520 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_9_control,The FW Region 9 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 9 firewall." bitfld.long 0x520 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x520 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x520 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x520 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x524 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_9_permission_0,The FW Region 9 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 9 firewall." hexmask.long.byte 0x524 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x524 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x524 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x524 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x524 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x524 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x524 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x524 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x524 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x524 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x524 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x524 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x524 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x524 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x524 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x524 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x524 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x528 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_9_permission_1,The FW Region 9 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 9 firewall." hexmask.long.byte 0x528 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x528 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x528 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x528 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x528 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x528 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x528 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x528 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x528 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x528 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x528 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x528 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x528 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x528 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x528 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x528 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x528 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x52C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_9_permission_2,The FW Region 9 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 9 firewall." hexmask.long.byte 0x52C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x52C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x52C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x52C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x52C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x52C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x52C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x52C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x52C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x52C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x52C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x52C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x52C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x52C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x52C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x52C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x52C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x530 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_9_start_address_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 9 firewall." hexmask.long.tbyte 0x530 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x530 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x534 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_9_start_address_h,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 9 firewall." hexmask.long.word 0x534 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x538 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_9_end_address_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 9 firewall." hexmask.long.tbyte 0x538 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x538 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x53C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_9_end_address_h,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 9 firewall." hexmask.long.word 0x53C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x540 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_10_control,The FW Region 10 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 10 firewall." bitfld.long 0x540 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x540 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x540 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x540 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x544 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_10_permission_0,The FW Region 10 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 10 firewall." hexmask.long.byte 0x544 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x544 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x544 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x544 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x544 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x544 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x544 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x544 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x544 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x544 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x544 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x544 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x544 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x544 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x544 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x544 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x544 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x548 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_10_permission_1,The FW Region 10 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 10 firewall." hexmask.long.byte 0x548 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x548 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x548 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x548 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x548 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x548 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x548 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x548 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x548 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x548 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x548 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x548 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x548 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x548 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x548 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x548 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x548 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x54C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_10_permission_2,The FW Region 10 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 10 firewall." hexmask.long.byte 0x54C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x54C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x54C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x54C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x54C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x54C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x54C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x54C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x54C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x54C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x54C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x54C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x54C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x54C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x54C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x54C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x54C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x550 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_10_start_address_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 10 firewall." hexmask.long.tbyte 0x550 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x550 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x554 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_10_start_address_h,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 10 firewall." hexmask.long.word 0x554 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x558 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_10_end_address_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 10 firewall." hexmask.long.tbyte 0x558 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x558 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x55C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_10_end_address_h,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 10 firewall." hexmask.long.word 0x55C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x560 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_11_control,The FW Region 11 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 11 firewall." bitfld.long 0x560 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x560 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x560 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x560 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x564 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_11_permission_0,The FW Region 11 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 11 firewall." hexmask.long.byte 0x564 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x564 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x564 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x564 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x564 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x564 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x564 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x564 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x564 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x564 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x564 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x564 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x564 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x564 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x564 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x564 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x564 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x568 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_11_permission_1,The FW Region 11 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 11 firewall." hexmask.long.byte 0x568 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x568 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x568 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x568 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x568 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x568 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x568 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x568 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x568 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x568 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x568 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x568 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x568 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x568 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x568 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x568 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x568 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x56C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_11_permission_2,The FW Region 11 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 11 firewall." hexmask.long.byte 0x56C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x56C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x56C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x56C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x56C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x56C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x56C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x56C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x56C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x56C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x56C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x56C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x56C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x56C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x56C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x56C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x56C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x570 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_11_start_address_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 11 firewall." hexmask.long.tbyte 0x570 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x570 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x574 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_11_start_address_h,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 11 firewall." hexmask.long.word 0x574 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x578 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_11_end_address_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 11 firewall." hexmask.long.tbyte 0x578 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x578 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x57C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_11_end_address_h,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 11 firewall." hexmask.long.word 0x57C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x580 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_12_control,The FW Region 12 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 12 firewall." bitfld.long 0x580 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x580 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x580 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x580 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x584 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_12_permission_0,The FW Region 12 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 12 firewall." hexmask.long.byte 0x584 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x584 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x584 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x584 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x584 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x584 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x584 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x584 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x584 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x584 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x584 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x584 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x584 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x584 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x584 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x584 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x584 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x588 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_12_permission_1,The FW Region 12 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 12 firewall." hexmask.long.byte 0x588 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x588 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x588 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x588 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x588 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x588 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x588 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x588 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x588 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x588 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x588 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x588 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x588 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x588 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x588 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x588 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x588 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x58C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_12_permission_2,The FW Region 12 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 12 firewall." hexmask.long.byte 0x58C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x58C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x58C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x58C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x58C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x58C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x58C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x58C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x58C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x58C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x58C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x58C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x58C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x58C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x58C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x58C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x58C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x590 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_12_start_address_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 12 firewall." hexmask.long.tbyte 0x590 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x590 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x594 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_12_start_address_h,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 12 firewall." hexmask.long.word 0x594 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x598 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_12_end_address_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 12 firewall." hexmask.long.tbyte 0x598 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x598 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x59C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_12_end_address_h,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 12 firewall." hexmask.long.word 0x59C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x5A0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_13_control,The FW Region 13 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 13 firewall." bitfld.long 0x5A0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x5A0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x5A0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x5A0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x5A4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_13_permission_0,The FW Region 13 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 13 firewall." hexmask.long.byte 0x5A4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x5A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x5A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x5A4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x5A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x5A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x5A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x5A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x5A4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x5A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x5A4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x5A4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x5A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x5A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5A4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x5A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x5A8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_13_permission_1,The FW Region 13 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 13 firewall." hexmask.long.byte 0x5A8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x5A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x5A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x5A8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x5A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x5A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x5A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x5A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x5A8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x5A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x5A8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x5A8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x5A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x5A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5A8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x5A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x5AC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_13_permission_2,The FW Region 13 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 13 firewall." hexmask.long.byte 0x5AC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x5AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x5AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x5AC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x5AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x5AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x5AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x5AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x5AC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x5AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x5AC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x5AC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x5AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x5AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5AC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x5AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x5B0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_13_start_address_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 13 firewall." hexmask.long.tbyte 0x5B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x5B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x5B4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_13_start_address_h,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 13 firewall." hexmask.long.word 0x5B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x5B8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_13_end_address_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 13 firewall." hexmask.long.tbyte 0x5B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x5B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5BC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_13_end_address_h,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 13 firewall." hexmask.long.word 0x5BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x5C0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_14_control,The FW Region 14 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 14 firewall." bitfld.long 0x5C0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x5C0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x5C0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x5C0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x5C4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_14_permission_0,The FW Region 14 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 14 firewall." hexmask.long.byte 0x5C4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x5C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x5C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x5C4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x5C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x5C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x5C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x5C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x5C4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x5C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x5C4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x5C4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x5C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x5C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5C4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x5C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x5C8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_14_permission_1,The FW Region 14 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 14 firewall." hexmask.long.byte 0x5C8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x5C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x5C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x5C8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x5C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x5C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x5C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x5C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x5C8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x5C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x5C8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x5C8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x5C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x5C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5C8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x5C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x5CC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_14_permission_2,The FW Region 14 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 14 firewall." hexmask.long.byte 0x5CC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x5CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x5CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x5CC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x5CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x5CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x5CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x5CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x5CC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x5CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x5CC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x5CC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x5CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x5CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5CC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x5CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x5D0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_14_start_address_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 14 firewall." hexmask.long.tbyte 0x5D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x5D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x5D4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_14_start_address_h,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 14 firewall." hexmask.long.word 0x5D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x5D8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_14_end_address_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 14 firewall." hexmask.long.tbyte 0x5D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x5D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5DC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_14_end_address_h,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 14 firewall." hexmask.long.word 0x5DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x5E0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_15_control,The FW Region 15 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 15 firewall." bitfld.long 0x5E0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x5E0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x5E0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x5E0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x5E4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_15_permission_0,The FW Region 15 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 15 firewall." hexmask.long.byte 0x5E4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x5E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x5E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x5E4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x5E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x5E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x5E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x5E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x5E4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x5E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x5E4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x5E4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x5E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x5E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5E4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x5E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x5E8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_15_permission_1,The FW Region 15 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 15 firewall." hexmask.long.byte 0x5E8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x5E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x5E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x5E8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x5E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x5E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x5E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x5E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x5E8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x5E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x5E8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x5E8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x5E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x5E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5E8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x5E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x5EC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_15_permission_2,The FW Region 15 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 15 firewall." hexmask.long.byte 0x5EC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x5EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x5EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x5EC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x5EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x5EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x5EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x5EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x5EC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x5EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x5EC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x5EC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x5EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x5EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x5EC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x5EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x5F0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_15_start_address_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 15 firewall." hexmask.long.tbyte 0x5F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x5F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x5F4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_15_start_address_h,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 15 firewall." hexmask.long.word 0x5F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x5F8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_15_end_address_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 15 firewall." hexmask.long.tbyte 0x5F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x5F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5FC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_15_end_address_h,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 15 firewall." hexmask.long.word 0x5FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x2C00++0x1FF line.long 0x0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x100 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_control,The FW Region 8 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall." bitfld.long 0x100 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x100 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x100 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x100 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x104 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_permission_0,The FW Region 8 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall." hexmask.long.byte 0x104 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x104 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x104 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x104 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x104 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x104 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x104 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x104 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x104 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x104 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x104 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x104 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x104 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x104 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x104 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x108 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_permission_1,The FW Region 8 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall." hexmask.long.byte 0x108 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x108 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x108 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x108 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x108 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x108 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x108 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x108 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x108 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x108 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x108 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x108 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x108 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x108 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x108 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_permission_2,The FW Region 8 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall." hexmask.long.byte 0x10C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x10C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x10C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x10C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x10C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x10C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x10C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x10C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x10C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x10C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x10C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x10C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x10C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x110 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_start_address_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall." hexmask.long.tbyte 0x110 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x110 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x114 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_start_address_h,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall." hexmask.long.word 0x114 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x118 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_end_address_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall." hexmask.long.tbyte 0x118 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x118 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x11C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_end_address_h,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall." hexmask.long.word 0x11C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x120 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_control,The FW Region 9 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall." bitfld.long 0x120 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x120 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x120 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x120 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x124 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_permission_0,The FW Region 9 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall." hexmask.long.byte 0x124 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x124 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x124 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x124 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x124 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x124 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x124 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x124 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x124 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x124 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x124 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x124 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x124 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x124 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x124 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x128 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_permission_1,The FW Region 9 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall." hexmask.long.byte 0x128 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x128 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x128 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x128 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x128 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x128 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x128 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x128 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x128 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x128 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x128 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x128 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x128 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x128 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x128 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x12C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_permission_2,The FW Region 9 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall." hexmask.long.byte 0x12C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x12C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x12C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x12C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x12C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x12C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x12C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x12C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x12C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x12C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x12C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x12C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x12C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x130 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_start_address_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall." hexmask.long.tbyte 0x130 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x130 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x134 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_start_address_h,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall." hexmask.long.word 0x134 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x138 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_end_address_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall." hexmask.long.tbyte 0x138 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x138 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x13C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_end_address_h,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall." hexmask.long.word 0x13C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x140 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_control,The FW Region 10 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall." bitfld.long 0x140 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x140 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x140 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x140 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x144 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_permission_0,The FW Region 10 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall." hexmask.long.byte 0x144 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x144 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x144 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x144 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x144 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x144 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x144 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x144 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x144 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x144 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x144 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x144 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x144 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x144 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x144 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x148 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_permission_1,The FW Region 10 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall." hexmask.long.byte 0x148 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x148 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x148 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x148 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x148 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x148 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x148 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x148 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x148 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x148 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x148 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x148 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x148 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x148 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x148 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x14C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_permission_2,The FW Region 10 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall." hexmask.long.byte 0x14C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x14C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x14C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x14C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x14C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x14C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x14C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x14C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x14C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x14C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x14C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x14C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x14C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x150 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_start_address_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall." hexmask.long.tbyte 0x150 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x150 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x154 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_start_address_h,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall." hexmask.long.word 0x154 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x158 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_end_address_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall." hexmask.long.tbyte 0x158 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x158 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x15C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_end_address_h,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall." hexmask.long.word 0x15C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x160 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_control,The FW Region 11 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall." bitfld.long 0x160 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x160 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x160 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x160 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x164 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_permission_0,The FW Region 11 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall." hexmask.long.byte 0x164 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x164 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x164 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x164 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x164 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x164 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x164 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x164 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x164 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x164 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x164 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x164 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x164 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x164 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x164 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x168 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_permission_1,The FW Region 11 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall." hexmask.long.byte 0x168 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x168 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x168 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x168 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x168 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x168 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x168 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x168 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x168 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x168 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x168 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x168 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x168 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x168 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x168 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x16C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_permission_2,The FW Region 11 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall." hexmask.long.byte 0x16C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x16C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x16C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x16C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x16C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x16C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x16C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x16C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x16C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x16C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x16C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x16C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x16C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x170 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_start_address_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall." hexmask.long.tbyte 0x170 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x170 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x174 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_start_address_h,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall." hexmask.long.word 0x174 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x178 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_end_address_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall." hexmask.long.tbyte 0x178 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x178 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x17C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_end_address_h,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall." hexmask.long.word 0x17C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x180 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_control,The FW Region 12 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall." bitfld.long 0x180 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x180 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x180 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x180 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x184 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_permission_0,The FW Region 12 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall." hexmask.long.byte 0x184 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x184 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x184 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x184 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x184 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x184 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x184 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x184 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x184 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x184 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x184 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x184 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x184 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x184 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x184 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x188 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_permission_1,The FW Region 12 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall." hexmask.long.byte 0x188 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x188 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x188 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x188 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x188 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x188 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x188 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x188 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x188 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x188 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x188 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x188 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x188 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x188 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x188 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x18C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_permission_2,The FW Region 12 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall." hexmask.long.byte 0x18C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x18C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x18C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x18C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x18C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x18C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x18C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x18C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x18C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x18C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x18C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x18C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x18C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x190 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_start_address_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall." hexmask.long.tbyte 0x190 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x190 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x194 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_start_address_h,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall." hexmask.long.word 0x194 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x198 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_end_address_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall." hexmask.long.tbyte 0x198 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x198 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x19C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_end_address_h,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall." hexmask.long.word 0x19C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1A0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_control,The FW Region 13 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall." bitfld.long 0x1A0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x1A0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1A0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x1A0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1A4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_permission_0,The FW Region 13 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall." hexmask.long.byte 0x1A4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1A4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1A4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1A4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1A8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_permission_1,The FW Region 13 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall." hexmask.long.byte 0x1A8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1A8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1A8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1A8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1AC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_permission_2,The FW Region 13 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall." hexmask.long.byte 0x1AC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1AC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1AC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1AC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1AC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1AC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1B0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_start_address_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall." hexmask.long.tbyte 0x1B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x1B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1B4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_start_address_h,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall." hexmask.long.word 0x1B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1B8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_end_address_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall." hexmask.long.tbyte 0x1B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x1B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1BC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_end_address_h,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall." hexmask.long.word 0x1BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1C0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_control,The FW Region 14 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall." bitfld.long 0x1C0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x1C0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1C0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x1C0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1C4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_permission_0,The FW Region 14 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall." hexmask.long.byte 0x1C4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1C4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1C4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1C4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1C8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_permission_1,The FW Region 14 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall." hexmask.long.byte 0x1C8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1C8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1C8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1C8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1CC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_permission_2,The FW Region 14 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall." hexmask.long.byte 0x1CC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1CC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1CC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1CC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1CC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1CC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1D0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_start_address_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall." hexmask.long.tbyte 0x1D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x1D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1D4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_start_address_h,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall." hexmask.long.word 0x1D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1D8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_end_address_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall." hexmask.long.tbyte 0x1D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x1D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1DC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_end_address_h,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall." hexmask.long.word 0x1DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1E0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_control,The FW Region 15 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall." bitfld.long 0x1E0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x1E0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1E0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x1E0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1E4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_permission_0,The FW Region 15 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall." hexmask.long.byte 0x1E4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1E4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1E4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1E4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1E8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_permission_1,The FW Region 15 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall." hexmask.long.byte 0x1E8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1E8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1E8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1E8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1EC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_permission_2,The FW Region 15 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall." hexmask.long.byte 0x1EC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1EC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1EC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1EC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1EC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1EC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1F0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_start_address_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall." hexmask.long.tbyte 0x1F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x1F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1F4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_start_address_h,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall." hexmask.long.word 0x1F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1F8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_end_address_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall." hexmask.long.tbyte 0x1F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x1F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1FC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_end_address_h,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall." hexmask.long.word 0x1FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x3400++0x1F line.long 0x0 "FW_REGS_Imcrc64_main_0_s_cfg_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Imcrc64_main_0.s_cfg region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_Imcrc64_main_0_s_cfg_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Imcrc64_main_0.s_cfg region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_Imcrc64_main_0_s_cfg_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Imcrc64_main_0.s_cfg region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_Imcrc64_main_0_s_cfg_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Imcrc64_main_0.s_cfg region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_Imcrc64_main_0_s_cfg_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Imcrc64_main_0.s_cfg region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_Imcrc64_main_0_s_cfg_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Imcrc64_main_0.s_cfg region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_Imcrc64_main_0_s_cfg_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imcrc64_main_0.s_cfg region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_Imcrc64_main_0_s_cfg_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Imcrc64_main_0.s_cfg region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x3800++0xFF line.long 0x0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 0.." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 0.." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 0.." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 1.." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 1.." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 1.." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 2.." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 2.." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 2.." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 3.." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 3.." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 3.." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 4.." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 4.." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 4.." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 5.." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 5.." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 5.." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 6.." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 6.." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 6.." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 7.." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 7.." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0.slv region 7.." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_export_am62a_main_data_cbass_to_am62a_main_mcasp_cbass_data_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x3C00++0x1FF line.long 0x0 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 4 firewall." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 4 firewall." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 4 firewall." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 4 firewall." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 5 firewall." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 5 firewall." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 5 firewall." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 5 firewall." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 6 firewall." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 6 firewall." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 6 firewall." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 6 firewall." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 7 firewall." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 7 firewall." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 7 firewall." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 7 firewall." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x100 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_8_control,The FW Region 8 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 8 firewall." bitfld.long 0x100 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x100 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x100 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x100 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x104 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_8_permission_0,The FW Region 8 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 8 firewall." hexmask.long.byte 0x104 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x104 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x104 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x104 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x104 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x104 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x104 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x104 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x104 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x104 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x104 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x104 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x104 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x104 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x104 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x108 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_8_permission_1,The FW Region 8 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 8 firewall." hexmask.long.byte 0x108 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x108 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x108 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x108 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x108 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x108 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x108 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x108 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x108 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x108 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x108 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x108 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x108 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x108 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x108 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_8_permission_2,The FW Region 8 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 8 firewall." hexmask.long.byte 0x10C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x10C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x10C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x10C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x10C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x10C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x10C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x10C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x10C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x10C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x10C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x10C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x10C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x110 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_8_start_address_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 8 firewall." hexmask.long.tbyte 0x110 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x110 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x114 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_8_start_address_h,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 8 firewall." hexmask.long.word 0x114 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x118 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_8_end_address_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 8 firewall." hexmask.long.tbyte 0x118 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x118 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x11C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_8_end_address_h,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 8 firewall." hexmask.long.word 0x11C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x120 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_9_control,The FW Region 9 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 9 firewall." bitfld.long 0x120 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x120 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x120 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x120 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x124 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_9_permission_0,The FW Region 9 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 9 firewall." hexmask.long.byte 0x124 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x124 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x124 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x124 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x124 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x124 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x124 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x124 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x124 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x124 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x124 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x124 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x124 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x124 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x124 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x128 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_9_permission_1,The FW Region 9 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 9 firewall." hexmask.long.byte 0x128 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x128 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x128 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x128 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x128 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x128 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x128 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x128 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x128 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x128 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x128 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x128 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x128 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x128 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x128 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x12C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_9_permission_2,The FW Region 9 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 9 firewall." hexmask.long.byte 0x12C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x12C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x12C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x12C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x12C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x12C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x12C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x12C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x12C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x12C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x12C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x12C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x12C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x130 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_9_start_address_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 9 firewall." hexmask.long.tbyte 0x130 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x130 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x134 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_9_start_address_h,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 9 firewall." hexmask.long.word 0x134 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x138 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_9_end_address_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 9 firewall." hexmask.long.tbyte 0x138 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x138 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x13C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_9_end_address_h,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 9 firewall." hexmask.long.word 0x13C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x140 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_10_control,The FW Region 10 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 10 firewall." bitfld.long 0x140 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x140 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x140 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x140 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x144 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_10_permission_0,The FW Region 10 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 10 firewall." hexmask.long.byte 0x144 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x144 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x144 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x144 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x144 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x144 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x144 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x144 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x144 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x144 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x144 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x144 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x144 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x144 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x144 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x148 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_10_permission_1,The FW Region 10 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 10 firewall." hexmask.long.byte 0x148 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x148 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x148 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x148 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x148 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x148 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x148 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x148 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x148 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x148 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x148 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x148 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x148 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x148 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x148 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x14C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_10_permission_2,The FW Region 10 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 10 firewall." hexmask.long.byte 0x14C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x14C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x14C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x14C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x14C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x14C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x14C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x14C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x14C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x14C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x14C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x14C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x14C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x150 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_10_start_address_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 10 firewall." hexmask.long.tbyte 0x150 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x150 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x154 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_10_start_address_h,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 10 firewall." hexmask.long.word 0x154 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x158 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_10_end_address_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 10 firewall." hexmask.long.tbyte 0x158 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x158 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x15C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_10_end_address_h,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 10 firewall." hexmask.long.word 0x15C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x160 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_11_control,The FW Region 11 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 11 firewall." bitfld.long 0x160 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x160 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x160 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x160 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x164 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_11_permission_0,The FW Region 11 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 11 firewall." hexmask.long.byte 0x164 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x164 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x164 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x164 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x164 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x164 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x164 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x164 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x164 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x164 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x164 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x164 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x164 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x164 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x164 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x168 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_11_permission_1,The FW Region 11 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 11 firewall." hexmask.long.byte 0x168 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x168 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x168 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x168 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x168 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x168 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x168 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x168 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x168 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x168 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x168 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x168 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x168 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x168 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x168 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x16C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_11_permission_2,The FW Region 11 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 11 firewall." hexmask.long.byte 0x16C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x16C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x16C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x16C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x16C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x16C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x16C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x16C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x16C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x16C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x16C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x16C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x16C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x170 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_11_start_address_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 11 firewall." hexmask.long.tbyte 0x170 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x170 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x174 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_11_start_address_h,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 11 firewall." hexmask.long.word 0x174 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x178 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_11_end_address_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 11 firewall." hexmask.long.tbyte 0x178 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x178 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x17C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_11_end_address_h,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 11 firewall." hexmask.long.word 0x17C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x180 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_12_control,The FW Region 12 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 12 firewall." bitfld.long 0x180 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x180 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x180 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x180 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x184 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_12_permission_0,The FW Region 12 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 12 firewall." hexmask.long.byte 0x184 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x184 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x184 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x184 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x184 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x184 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x184 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x184 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x184 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x184 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x184 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x184 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x184 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x184 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x184 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x188 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_12_permission_1,The FW Region 12 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 12 firewall." hexmask.long.byte 0x188 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x188 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x188 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x188 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x188 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x188 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x188 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x188 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x188 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x188 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x188 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x188 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x188 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x188 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x188 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x18C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_12_permission_2,The FW Region 12 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 12 firewall." hexmask.long.byte 0x18C 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x18C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x18C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x18C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x18C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x18C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x18C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x18C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x18C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x18C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x18C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x18C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x18C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x190 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_12_start_address_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 12 firewall." hexmask.long.tbyte 0x190 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x190 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x194 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_12_start_address_h,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 12 firewall." hexmask.long.word 0x194 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x198 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_12_end_address_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 12 firewall." hexmask.long.tbyte 0x198 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x198 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x19C "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_12_end_address_h,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 12 firewall." hexmask.long.word 0x19C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1A0 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_13_control,The FW Region 13 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 13 firewall." bitfld.long 0x1A0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x1A0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1A0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x1A0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1A4 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_13_permission_0,The FW Region 13 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 13 firewall." hexmask.long.byte 0x1A4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1A4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1A4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1A4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1A8 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_13_permission_1,The FW Region 13 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 13 firewall." hexmask.long.byte 0x1A8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1A8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1A8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1A8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1A8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1AC "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_13_permission_2,The FW Region 13 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 13 firewall." hexmask.long.byte 0x1AC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1AC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1AC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1AC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1AC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1AC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1B0 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_13_start_address_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 13 firewall." hexmask.long.tbyte 0x1B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x1B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1B4 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_13_start_address_h,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 13 firewall." hexmask.long.word 0x1B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1B8 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_13_end_address_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 13 firewall." hexmask.long.tbyte 0x1B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x1B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1BC "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_13_end_address_h,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 13 firewall." hexmask.long.word 0x1BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1C0 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_14_control,The FW Region 14 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 14 firewall." bitfld.long 0x1C0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x1C0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1C0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x1C0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1C4 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_14_permission_0,The FW Region 14 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 14 firewall." hexmask.long.byte 0x1C4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1C4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1C4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1C4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1C8 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_14_permission_1,The FW Region 14 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 14 firewall." hexmask.long.byte 0x1C8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1C8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1C8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1C8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1C8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1CC "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_14_permission_2,The FW Region 14 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 14 firewall." hexmask.long.byte 0x1CC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1CC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1CC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1CC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1CC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1CC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1D0 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_14_start_address_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 14 firewall." hexmask.long.tbyte 0x1D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x1D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1D4 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_14_start_address_h,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 14 firewall." hexmask.long.word 0x1D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1D8 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_14_end_address_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 14 firewall." hexmask.long.tbyte 0x1D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x1D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1DC "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_14_end_address_h,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 14 firewall." hexmask.long.word 0x1DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1E0 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_15_control,The FW Region 15 Control Register defines the control fields for the slave Imsram2kx256e_main_0.slv region 15 firewall." bitfld.long 0x1E0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" newline bitfld.long 0x1E0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1E0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" newline hexmask.long.byte 0x1E0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1E4 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_15_permission_0,The FW Region 15 Permission 0 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 15 firewall." hexmask.long.byte 0x1E4 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1E4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1E4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1E4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1E8 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_15_permission_1,The FW Region 15 Permission 1 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 15 firewall." hexmask.long.byte 0x1E8 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1E8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1E8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1E8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1E8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1EC "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_15_permission_2,The FW Region 15 Permission 2 Register defines the permissions for the slave Imsram2kx256e_main_0.slv region 15 firewall." hexmask.long.byte 0x1EC 16.--23. 1. "PRIV_ID,Allowed privid." newline bitfld.long 0x1EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" newline bitfld.long 0x1EC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" newline bitfld.long 0x1EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" newline bitfld.long 0x1EC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" newline bitfld.long 0x1EC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1EC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" newline bitfld.long 0x1EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" newline bitfld.long 0x1EC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1F0 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_15_start_address_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave Imsram2kx256e_main_0.slv region 15 firewall." hexmask.long.tbyte 0x1F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." newline hexmask.long.word 0x1F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1F4 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_15_start_address_h,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave Imsram2kx256e_main_0.slv region 15 firewall." hexmask.long.word 0x1F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1F8 "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_15_end_address_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave Imsram2kx256e_main_0.slv region 15 firewall." hexmask.long.tbyte 0x1F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." newline hexmask.long.word 0x1F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1FC "FW_REGS_Imsram2kx256e_main_0_slv_fw_region_15_end_address_h,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave Imsram2kx256e_main_0.slv region 15 firewall." hexmask.long.word 0x1FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." tree.end tree "CBASS0_GLB" base ad:0x45B08000 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree "CBASS0_ISC" base ad:0x45820000 group.long 0x400++0x3 line.long 0x0 "ISC_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x410++0x13 line.long 0x0 "ISC_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r region 0.." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r region 0.." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r region.." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x800++0x3 line.long 0x0 "ISC_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x810++0x13 line.long 0x0 "ISC_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w region 0.." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w region 0.." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w region.." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x1400++0x3 line.long 0x0 "ISC_REGS_Ik3_led2vbus_main_0_vbusp_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_led2vbus_main_0.vbusp region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x1410++0x13 line.long 0x0 "ISC_REGS_Ik3_led2vbus_main_0_vbusp_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_led2vbus_main_0.vbusp region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_led2vbus_main_0_vbusp_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_led2vbus_main_0.vbusp region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_led2vbus_main_0_vbusp_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_led2vbus_main_0.vbusp region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_led2vbus_main_0_vbusp_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_led2vbus_main_0.vbusp region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_led2vbus_main_0_vbusp_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_led2vbus_main_0.vbusp region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x1800++0x3 line.long 0x0 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x1810++0x13 line.long 0x0 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x1C00++0x3 line.long 0x0 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x1C10++0x13 line.long 0x0 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x2000++0x3 line.long 0x0 "ISC_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Igic500ss_1_4_main_0.mem_wr_vbusm region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x2010++0x13 line.long 0x0 "ISC_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Igic500ss_1_4_main_0.mem_wr_vbusm region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Igic500ss_1_4_main_0.mem_wr_vbusm region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Igic500ss_1_4_main_0.mem_wr_vbusm region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Igic500ss_1_4_main_0.mem_wr_vbusm region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Igic500ss_1_4_main_0.mem_wr_vbusm region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x2400++0x3 line.long 0x0 "ISC_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Igic500ss_1_4_main_0.mem_rd_vbusm region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x2410++0x13 line.long 0x0 "ISC_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Igic500ss_1_4_main_0.mem_rd_vbusm region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Igic500ss_1_4_main_0.mem_rd_vbusm region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Igic500ss_1_4_main_0.mem_rd_vbusm region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Igic500ss_1_4_main_0.mem_rd_vbusm region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Igic500ss_1_4_main_0.mem_rd_vbusm region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x2800++0x3 line.long 0x0 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd8ss_main_0.emmcsdss_rd region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x2810++0x13 line.long 0x0 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd8ss_main_0.emmcsdss_rd region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd8ss_main_0.emmcsdss_rd region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd8ss_main_0.emmcsdss_rd region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd8ss_main_0.emmcsdss_rd region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd8ss_main_0.emmcsdss_rd region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x2C00++0x3 line.long 0x0 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd8ss_main_0.emmcsdss_wr region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x2C10++0x13 line.long 0x0 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd8ss_main_0.emmcsdss_wr region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd8ss_main_0.emmcsdss_wr region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd8ss_main_0.emmcsdss_wr region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd8ss_main_0.emmcsdss_wr region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd8ss_main_0.emmcsdss_wr region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x3000++0x3 line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x3010++0x13 line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_rd region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x3400++0x3 line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x3410++0x13 line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_wr region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x3800++0x3 line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd4ss_main_1.emmcsdss_wr region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x3810++0x13 line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd4ss_main_1.emmcsdss_wr region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd4ss_main_1.emmcsdss_wr region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd4ss_main_1.emmcsdss_wr region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd4ss_main_1.emmcsdss_wr region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd4ss_main_1.emmcsdss_wr region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x3C00++0x3 line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd4ss_main_1.emmcsdss_rd region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x3C10++0x13 line.long 0x0 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd4ss_main_1.emmcsdss_rd region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd4ss_main_1.emmcsdss_rd region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd4ss_main_1.emmcsdss_rd region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd4ss_main_1.emmcsdss_rd region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd4ss_main_1.emmcsdss_rd region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x4000++0x3 line.long 0x0 "ISC_REGS_Iusb2ss_16ffc_main_0_mstw0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iusb2ss_16ffc_main_0.mstw0 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x4010++0x13 line.long 0x0 "ISC_REGS_Iusb2ss_16ffc_main_0_mstw0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb2ss_16ffc_main_0.mstw0 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb2ss_16ffc_main_0_mstw0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iusb2ss_16ffc_main_0.mstw0 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb2ss_16ffc_main_0_mstw0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb2ss_16ffc_main_0.mstw0 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb2ss_16ffc_main_0_mstw0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iusb2ss_16ffc_main_0.mstw0 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb2ss_16ffc_main_0_mstw0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iusb2ss_16ffc_main_0.mstw0 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x4400++0x3 line.long 0x0 "ISC_REGS_Iusb2ss_16ffc_main_0_mstr0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iusb2ss_16ffc_main_0.mstr0 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x4410++0x13 line.long 0x0 "ISC_REGS_Iusb2ss_16ffc_main_0_mstr0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb2ss_16ffc_main_0.mstr0 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb2ss_16ffc_main_0_mstr0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iusb2ss_16ffc_main_0.mstr0 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb2ss_16ffc_main_0_mstr0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb2ss_16ffc_main_0.mstr0 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb2ss_16ffc_main_0_mstr0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iusb2ss_16ffc_main_0.mstr0 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb2ss_16ffc_main_0_mstr0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iusb2ss_16ffc_main_0.mstr0 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x4800++0x3 line.long 0x0 "ISC_REGS_Iusb2ss_16ffc_main_1_mstr0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iusb2ss_16ffc_main_1.mstr0 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x4810++0x13 line.long 0x0 "ISC_REGS_Iusb2ss_16ffc_main_1_mstr0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb2ss_16ffc_main_1.mstr0 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb2ss_16ffc_main_1_mstr0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iusb2ss_16ffc_main_1.mstr0 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb2ss_16ffc_main_1_mstr0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb2ss_16ffc_main_1.mstr0 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb2ss_16ffc_main_1_mstr0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iusb2ss_16ffc_main_1.mstr0 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb2ss_16ffc_main_1_mstr0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iusb2ss_16ffc_main_1.mstr0 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x4C00++0x3 line.long 0x0 "ISC_REGS_Iusb2ss_16ffc_main_1_mstw0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iusb2ss_16ffc_main_1.mstw0 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x4C10++0x13 line.long 0x0 "ISC_REGS_Iusb2ss_16ffc_main_1_mstw0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb2ss_16ffc_main_1.mstw0 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Iusb2ss_16ffc_main_1_mstw0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iusb2ss_16ffc_main_1.mstw0 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Iusb2ss_16ffc_main_1_mstw0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb2ss_16ffc_main_1.mstw0 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Iusb2ss_16ffc_main_1_mstw0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iusb2ss_16ffc_main_1.mstw0 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Iusb2ss_16ffc_main_1_mstw0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iusb2ss_16ffc_main_1.mstw0 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x5000++0x3 line.long 0x0 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_dss_ul_main_0.vbusm_dma region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x5010++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_dss_ul_main_0.vbusm_dma region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x5030++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_dss_ul_main_0.vbusm_dma region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x5050++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_dss_ul_main_0.vbusm_dma region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x5070++0x13 line.long 0x0 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_dss_ul_main_0.vbusm_dma region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x5400++0x3 line.long 0x0 "ISC_REGS_Isa3ss_am62a_main_0_ctxcach_ext_dma_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Isa3ss_am62a_main_0.ctxcach_ext_dma region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x5410++0x13 line.long 0x0 "ISC_REGS_Isa3ss_am62a_main_0_ctxcach_ext_dma_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Isa3ss_am62a_main_0.ctxcach_ext_dma region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isa3ss_am62a_main_0_ctxcach_ext_dma_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Isa3ss_am62a_main_0.ctxcach_ext_dma region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isa3ss_am62a_main_0_ctxcach_ext_dma_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Isa3ss_am62a_main_0.ctxcach_ext_dma region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isa3ss_am62a_main_0_ctxcach_ext_dma_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Isa3ss_am62a_main_0.ctxcach_ext_dma region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isa3ss_am62a_main_0_ctxcach_ext_dma_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Isa3ss_am62a_main_0.ctxcach_ext_dma region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x5800++0x3 line.long 0x0 "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_w_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_jpgenc_e5010_main_0.m_vbusm_w region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x5810++0x13 line.long 0x0 "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_w_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_jpgenc_e5010_main_0.m_vbusm_w region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_w_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_jpgenc_e5010_main_0.m_vbusm_w region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_w_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_jpgenc_e5010_main_0.m_vbusm_w region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_w_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_jpgenc_e5010_main_0.m_vbusm_w region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_w_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_jpgenc_e5010_main_0.m_vbusm_w region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x5C00++0x3 line.long 0x0 "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_r_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_jpgenc_e5010_main_0.m_vbusm_r region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x5C10++0x13 line.long 0x0 "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_r_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_jpgenc_e5010_main_0.m_vbusm_r region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_r_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_jpgenc_e5010_main_0.m_vbusm_r region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_r_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_jpgenc_e5010_main_0.m_vbusm_r region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_r_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_jpgenc_e5010_main_0.m_vbusm_r region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_r_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_jpgenc_e5010_main_0.m_vbusm_r region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x5C30++0x13 line.long 0x0 "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_r_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_jpgenc_e5010_main_0.m_vbusm_r region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_r_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_jpgenc_e5010_main_0.m_vbusm_r region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_r_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_jpgenc_e5010_main_0.m_vbusm_r region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_r_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_jpgenc_e5010_main_0.m_vbusm_r region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_r_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_jpgenc_e5010_main_0.m_vbusm_r region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6000++0x3 line.long 0x0 "ISC_REGS_Idmss_csi_am62a_main_0_bcdma_memr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Idmss_csi_am62a_main_0.bcdma_memr region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6010++0x13 line.long 0x0 "ISC_REGS_Idmss_csi_am62a_main_0_bcdma_memr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Idmss_csi_am62a_main_0.bcdma_memr region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Idmss_csi_am62a_main_0_bcdma_memr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Idmss_csi_am62a_main_0.bcdma_memr region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Idmss_csi_am62a_main_0_bcdma_memr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Idmss_csi_am62a_main_0.bcdma_memr region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Idmss_csi_am62a_main_0_bcdma_memr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Idmss_csi_am62a_main_0.bcdma_memr region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Idmss_csi_am62a_main_0_bcdma_memr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Idmss_csi_am62a_main_0.bcdma_memr region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6400++0x3 line.long 0x0 "ISC_REGS_Idmss_csi_am62a_main_0_bcdma_memw_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Idmss_csi_am62a_main_0.bcdma_memw region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6410++0x13 line.long 0x0 "ISC_REGS_Idmss_csi_am62a_main_0_bcdma_memw_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Idmss_csi_am62a_main_0.bcdma_memw region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Idmss_csi_am62a_main_0_bcdma_memw_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Idmss_csi_am62a_main_0.bcdma_memw region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Idmss_csi_am62a_main_0_bcdma_memw_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Idmss_csi_am62a_main_0.bcdma_memw region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Idmss_csi_am62a_main_0_bcdma_memw_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Idmss_csi_am62a_main_0.bcdma_memw region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Idmss_csi_am62a_main_0_bcdma_memw_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Idmss_csi_am62a_main_0.bcdma_memw region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6800++0x3 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6810++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6830++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6850++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6870++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6890++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6C00++0x3 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6C10++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6C30++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6C50++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6C70++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x6C90++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 4 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 4 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 4 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 4 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async region 5 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x7000++0x3 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x7010++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x7400++0x3 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x7410++0x13 line.long 0x0 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x7800++0x3 line.long 0x0 "ISC_REGS_Isam62a_c7xv_wrap_main_0_c7xv_soc_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Isam62a_c7xv_wrap_main_0.c7xv_soc region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x7810++0x13 line.long 0x0 "ISC_REGS_Isam62a_c7xv_wrap_main_0_c7xv_soc_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Isam62a_c7xv_wrap_main_0.c7xv_soc region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isam62a_c7xv_wrap_main_0_c7xv_soc_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Isam62a_c7xv_wrap_main_0.c7xv_soc region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isam62a_c7xv_wrap_main_0_c7xv_soc_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Isam62a_c7xv_wrap_main_0.c7xv_soc region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isam62a_c7xv_wrap_main_0_c7xv_soc_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Isam62a_c7xv_wrap_main_0.c7xv_soc region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isam62a_c7xv_wrap_main_0_c7xv_soc_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Isam62a_c7xv_wrap_main_0.c7xv_soc region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x7830++0x13 line.long 0x0 "ISC_REGS_Isam62a_c7xv_wrap_main_0_c7xv_soc_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Isam62a_c7xv_wrap_main_0.c7xv_soc region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isam62a_c7xv_wrap_main_0_c7xv_soc_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Isam62a_c7xv_wrap_main_0.c7xv_soc region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isam62a_c7xv_wrap_main_0_c7xv_soc_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Isam62a_c7xv_wrap_main_0.c7xv_soc region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isam62a_c7xv_wrap_main_0_c7xv_soc_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Isam62a_c7xv_wrap_main_0.c7xv_soc region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isam62a_c7xv_wrap_main_0_c7xv_soc_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Isam62a_c7xv_wrap_main_0.c7xv_soc region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x7C00++0x3 line.long 0x0 "ISC_REGS_Isam62a_vpac_wrap_main_0_data_mst_0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Isam62a_vpac_wrap_main_0.data_mst_0 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x7C10++0x13 line.long 0x0 "ISC_REGS_Isam62a_vpac_wrap_main_0_data_mst_0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Isam62a_vpac_wrap_main_0.data_mst_0 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isam62a_vpac_wrap_main_0_data_mst_0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Isam62a_vpac_wrap_main_0.data_mst_0 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isam62a_vpac_wrap_main_0_data_mst_0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Isam62a_vpac_wrap_main_0.data_mst_0 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isam62a_vpac_wrap_main_0_data_mst_0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Isam62a_vpac_wrap_main_0.data_mst_0 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isam62a_vpac_wrap_main_0_data_mst_0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Isam62a_vpac_wrap_main_0.data_mst_0 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x8000++0x3 line.long 0x0 "ISC_REGS_Isam62a_vpac_wrap_main_0_ldc0_m_mst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Isam62a_vpac_wrap_main_0.ldc0_m_mst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x8010++0x13 line.long 0x0 "ISC_REGS_Isam62a_vpac_wrap_main_0_ldc0_m_mst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Isam62a_vpac_wrap_main_0.ldc0_m_mst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isam62a_vpac_wrap_main_0_ldc0_m_mst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Isam62a_vpac_wrap_main_0.ldc0_m_mst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isam62a_vpac_wrap_main_0_ldc0_m_mst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Isam62a_vpac_wrap_main_0.ldc0_m_mst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isam62a_vpac_wrap_main_0_ldc0_m_mst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Isam62a_vpac_wrap_main_0.ldc0_m_mst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isam62a_vpac_wrap_main_0_ldc0_m_mst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Isam62a_vpac_wrap_main_0.ldc0_m_mst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x8400++0x3 line.long 0x0 "ISC_REGS_Isam62a_vpac_wrap_main_0_data_mst_1_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Isam62a_vpac_wrap_main_0.data_mst_1 region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" newline bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x8410++0x13 line.long 0x0 "ISC_REGS_Isam62a_vpac_wrap_main_0_data_mst_1_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Isam62a_vpac_wrap_main_0.data_mst_1 region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Isam62a_vpac_wrap_main_0_data_mst_1_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Isam62a_vpac_wrap_main_0.data_mst_1 region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Isam62a_vpac_wrap_main_0_data_mst_1_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Isam62a_vpac_wrap_main_0.data_mst_1 region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Isam62a_vpac_wrap_main_0_data_mst_1_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Isam62a_vpac_wrap_main_0.data_mst_1 region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Isam62a_vpac_wrap_main_0_data_mst_1_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Isam62a_vpac_wrap_main_0.data_mst_1 region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" newline bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" newline hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" newline bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." tree.end tree "CBASS0_QOS" base ad:0x45D20000 group.long 0x400++0x7 line.long 0x0 "QOS_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x500++0x3 line.long 0x0 "QOS_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_map0,The Map Register defines the fields for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x800++0x7 line.long 0x0 "QOS_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x900++0x3 line.long 0x0 "QOS_REGS_Isam62a_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_map0,The Map Register defines the fields for the master Isam62a_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x1800++0x7 line.long 0x0 "QOS_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Idebugss_k3_wrap_cv0_main_0.vbusmw for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Idebugss_k3_wrap_cv0_main_0.vbusmw for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x1900++0x3 line.long 0x0 "QOS_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_map0,The Map Register defines the fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmw per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x1C00++0x7 line.long 0x0 "QOS_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Idebugss_k3_wrap_cv0_main_0.vbusmr for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Idebugss_k3_wrap_cv0_main_0.vbusmr for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x1D00++0x3 line.long 0x0 "QOS_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_map0,The Map Register defines the fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmr per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x2000++0x7 line.long 0x0 "QOS_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Igic500ss_1_4_main_0.mem_wr_vbusm for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Igic500ss_1_4_main_0.mem_wr_vbusm for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x2100++0x3 line.long 0x0 "QOS_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_map0,The Map Register defines the fields for the master Igic500ss_1_4_main_0.mem_wr_vbusm per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x2400++0x7 line.long 0x0 "QOS_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Igic500ss_1_4_main_0.mem_rd_vbusm for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Igic500ss_1_4_main_0.mem_rd_vbusm for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x2500++0x3 line.long 0x0 "QOS_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_map0,The Map Register defines the fields for the master Igic500ss_1_4_main_0.mem_rd_vbusm per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x2800++0x7 line.long 0x0 "QOS_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Iemmcsd8ss_main_0.emmcsdss_rd for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Iemmcsd8ss_main_0.emmcsdss_rd for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x2900++0x3 line.long 0x0 "QOS_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_map0,The Map Register defines the fields for the master Iemmcsd8ss_main_0.emmcsdss_rd per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x2C00++0x7 line.long 0x0 "QOS_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Iemmcsd8ss_main_0.emmcsdss_wr for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Iemmcsd8ss_main_0.emmcsdss_wr for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x2D00++0x3 line.long 0x0 "QOS_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_map0,The Map Register defines the fields for the master Iemmcsd8ss_main_0.emmcsdss_wr per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x3000++0x7 line.long 0x0 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_rd for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_rd for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x3100++0x3 line.long 0x0 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_map0,The Map Register defines the fields for the master Iemmcsd4ss_main_0.emmcsdss_rd per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x3400++0x7 line.long 0x0 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_wr for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_0.emmcsdss_wr for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x3500++0x3 line.long 0x0 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_map0,The Map Register defines the fields for the master Iemmcsd4ss_main_0.emmcsdss_wr per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x3800++0x7 line.long 0x0 "QOS_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_1.emmcsdss_wr for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_1.emmcsdss_wr for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x3900++0x3 line.long 0x0 "QOS_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_map0,The Map Register defines the fields for the master Iemmcsd4ss_main_1.emmcsdss_wr per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x3C00++0x7 line.long 0x0 "QOS_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_1.emmcsdss_rd for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Iemmcsd4ss_main_1.emmcsdss_rd for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x3D00++0x3 line.long 0x0 "QOS_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_map0,The Map Register defines the fields for the master Iemmcsd4ss_main_1.emmcsdss_rd per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x4000++0x7 line.long 0x0 "QOS_REGS_Iusb2ss_16ffc_main_0_mstw0_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Iusb2ss_16ffc_main_0.mstw0 for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iusb2ss_16ffc_main_0_mstw0_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Iusb2ss_16ffc_main_0.mstw0 for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x4100++0x3 line.long 0x0 "QOS_REGS_Iusb2ss_16ffc_main_0_mstw0_map0,The Map Register defines the fields for the master Iusb2ss_16ffc_main_0.mstw0 per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x4400++0x7 line.long 0x0 "QOS_REGS_Iusb2ss_16ffc_main_0_mstr0_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Iusb2ss_16ffc_main_0.mstr0 for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iusb2ss_16ffc_main_0_mstr0_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Iusb2ss_16ffc_main_0.mstr0 for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x4500++0x3 line.long 0x0 "QOS_REGS_Iusb2ss_16ffc_main_0_mstr0_map0,The Map Register defines the fields for the master Iusb2ss_16ffc_main_0.mstr0 per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x4800++0x7 line.long 0x0 "QOS_REGS_Iusb2ss_16ffc_main_1_mstr0_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Iusb2ss_16ffc_main_1.mstr0 for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iusb2ss_16ffc_main_1_mstr0_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Iusb2ss_16ffc_main_1.mstr0 for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x4900++0x3 line.long 0x0 "QOS_REGS_Iusb2ss_16ffc_main_1_mstr0_map0,The Map Register defines the fields for the master Iusb2ss_16ffc_main_1.mstr0 per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x4C00++0x7 line.long 0x0 "QOS_REGS_Iusb2ss_16ffc_main_1_mstw0_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Iusb2ss_16ffc_main_1.mstw0 for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Iusb2ss_16ffc_main_1_mstw0_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Iusb2ss_16ffc_main_1.mstw0 for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x4D00++0x3 line.long 0x0 "QOS_REGS_Iusb2ss_16ffc_main_1_mstw0_map0,The Map Register defines the fields for the master Iusb2ss_16ffc_main_1.mstw0 per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x5000++0x7 line.long 0x0 "QOS_REGS_Ik3_dss_ul_main_0_vbusm_dma_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Ik3_dss_ul_main_0.vbusm_dma for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_dss_ul_main_0_vbusm_dma_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Ik3_dss_ul_main_0.vbusm_dma for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x5100++0xF line.long 0x0 "QOS_REGS_Ik3_dss_ul_main_0_vbusm_dma_map0,The Map Register defines the fields for the master Ik3_dss_ul_main_0.vbusm_dma per channel." hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ik3_dss_ul_main_0_vbusm_dma_map1,The Map Register defines the fields for the master Ik3_dss_ul_main_0.vbusm_dma per channel." hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ik3_dss_ul_main_0_vbusm_dma_map2,The Map Register defines the fields for the master Ik3_dss_ul_main_0.vbusm_dma per channel." hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Ik3_dss_ul_main_0_vbusm_dma_map3,The Map Register defines the fields for the master Ik3_dss_ul_main_0.vbusm_dma per channel." hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x5400++0x7 line.long 0x0 "QOS_REGS_Isa3ss_am62a_main_0_ctxcach_ext_dma_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Isa3ss_am62a_main_0.ctxcach_ext_dma for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Isa3ss_am62a_main_0_ctxcach_ext_dma_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Isa3ss_am62a_main_0.ctxcach_ext_dma for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x5500++0x3 line.long 0x0 "QOS_REGS_Isa3ss_am62a_main_0_ctxcach_ext_dma_map0,The Map Register defines the fields for the master Isa3ss_am62a_main_0.ctxcach_ext_dma per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x5800++0x7 line.long 0x0 "QOS_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_w_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Ik3_jpgenc_e5010_main_0.m_vbusm_w for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_w_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Ik3_jpgenc_e5010_main_0.m_vbusm_w for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x5900++0x3 line.long 0x0 "QOS_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_w_map0,The Map Register defines the fields for the master Ik3_jpgenc_e5010_main_0.m_vbusm_w per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x5C00++0x7 line.long 0x0 "QOS_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_r_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Ik3_jpgenc_e5010_main_0.m_vbusm_r for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_r_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Ik3_jpgenc_e5010_main_0.m_vbusm_r for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x5D00++0x7 line.long 0x0 "QOS_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_r_map0,The Map Register defines the fields for the master Ik3_jpgenc_e5010_main_0.m_vbusm_r per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ik3_jpgenc_e5010_main_0_m_vbusm_r_map1,The Map Register defines the fields for the master Ik3_jpgenc_e5010_main_0.m_vbusm_r per channel." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x6800++0x7 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x6900++0x13 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_map0,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_map1,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async per channel." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_map2,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async per channel." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_map3,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async per channel." bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_r_async_map4,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_r_async per channel." bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x6C00++0x7 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x6D00++0x13 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_map0,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_map1,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async per channel." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_map2,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async per channel." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0xC "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_map3,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async per channel." bitfld.long 0xC 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0xC 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0xC 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x10 "QOS_REGS_Ik3_vpu_wave521cl_main_0_pri_m_vbusm_w_async_map4,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.pri_m_vbusm_w_async per channel." bitfld.long 0x10 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x10 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x10 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x7000++0x7 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x7100++0x3 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_r_async_map0,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_r_async per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x7400++0x7 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x7500++0x3 line.long 0x0 "QOS_REGS_Ik3_vpu_wave521cl_main_0_sec_m_vbusm_w_async_map0,The Map Register defines the fields for the master Ik3_vpu_wave521cl_main_0.sec_m_vbusm_w_async per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x7800++0x7 line.long 0x0 "QOS_REGS_Isam62a_c7xv_wrap_main_0_c7xv_soc_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Isam62a_c7xv_wrap_main_0.c7xv_soc for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Isam62a_c7xv_wrap_main_0_c7xv_soc_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Isam62a_c7xv_wrap_main_0.c7xv_soc for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x7900++0x7 line.long 0x0 "QOS_REGS_Isam62a_c7xv_wrap_main_0_c7xv_soc_map0,The Map Register defines the fields for the master Isam62a_c7xv_wrap_main_0.c7xv_soc per channel." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Isam62a_c7xv_wrap_main_0_c7xv_soc_map1,The Map Register defines the fields for the master Isam62a_c7xv_wrap_main_0.c7xv_soc per channel." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x8000++0x7 line.long 0x0 "QOS_REGS_Isam62a_vpac_wrap_main_0_ldc0_m_mst_slv_grp_0_grp_map1,The Group Map Register defines the final orderid for the master Isam62a_vpac_wrap_main_0.ldc0_m_mst for group slv_grp_0." hexmask.long.byte 0x0 28.--31. 1. "ORDERID7,orderid signal for 7." hexmask.long.byte 0x0 24.--27. 1. "ORDERID6,orderid signal for 6." hexmask.long.byte 0x0 20.--23. 1. "ORDERID5,orderid signal for 5." hexmask.long.byte 0x0 16.--19. 1. "ORDERID4,orderid signal for 4." hexmask.long.byte 0x0 12.--15. 1. "ORDERID3,orderid signal for 3." newline hexmask.long.byte 0x0 8.--11. 1. "ORDERID2,orderid signal for 2." hexmask.long.byte 0x0 4.--7. 1. "ORDERID1,orderid signal for 1." hexmask.long.byte 0x0 0.--3. 1. "ORDERID0,orderid signal for 0." line.long 0x4 "QOS_REGS_Isam62a_vpac_wrap_main_0_ldc0_m_mst_slv_grp_0_grp_map2,The Group Map Register defines the final orderid for the master Isam62a_vpac_wrap_main_0.ldc0_m_mst for group slv_grp_0." hexmask.long.byte 0x4 28.--31. 1. "ORDERID15,orderid signal for 7." hexmask.long.byte 0x4 24.--27. 1. "ORDERID14,orderid signal for 6." hexmask.long.byte 0x4 20.--23. 1. "ORDERID13,orderid signal for 5." hexmask.long.byte 0x4 16.--19. 1. "ORDERID12,orderid signal for 4." hexmask.long.byte 0x4 12.--15. 1. "ORDERID11,orderid signal for 3." newline hexmask.long.byte 0x4 8.--11. 1. "ORDERID10,orderid signal for 2." hexmask.long.byte 0x4 4.--7. 1. "ORDERID9,orderid signal for 1." hexmask.long.byte 0x4 0.--3. 1. "ORDERID8,orderid signal for 0." group.long 0x8100++0xB line.long 0x0 "QOS_REGS_Isam62a_vpac_wrap_main_0_ldc0_m_mst_map0,The Map Register defines the fields for the master Isam62a_vpac_wrap_main_0.ldc0_m_mst per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x4 "QOS_REGS_Isam62a_vpac_wrap_main_0_ldc0_m_mst_map1,The Map Register defines the fields for the master Isam62a_vpac_wrap_main_0.ldc0_m_mst per channel." bitfld.long 0x4 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x4 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x4 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" line.long 0x8 "QOS_REGS_Isam62a_vpac_wrap_main_0_ldc0_m_mst_map2,The Map Register defines the fields for the master Isam62a_vpac_wrap_main_0.ldc0_m_mst per channel." bitfld.long 0x8 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x8 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x8 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" tree.end tree.end tree "CMP_EVENT_INTROUTER0_INTR_ROUTER_CFG" base ad:0xA30000 rgroup.long 0x0++0x3 line.long 0x0 "INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.byte 0x0 0.--4. 1. "MUX_CNTL,Mux control for interrupt N" tree.end tree "CODEC" base ad:0x0 tree "CODEC_RS_BW_LIMITER2_REGS" base ad:0x30408000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,PID function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" group.long 0x4++0x3 line.long 0x0 "REGS_CTRL,This register controls the overall behavior of the rate limiter module" bitfld.long 0x0 4. "REGION_FILTER_EN,Enable the region filter which will only apply the bandwith and transaction limits to the configured address regions" "0,1" bitfld.long 0x0 3. "WR_TXN_ENABLE,Enable limiting maximum outstanding write transactions" "0,1" bitfld.long 0x0 2. "RD_TXN_ENABLE,Enable limiting maximum outstanding read transactions" "0,1" bitfld.long 0x0 1. "WR_BW_ENABLE,Enable write bandwidth limiting" "0,1" bitfld.long 0x0 0. "RD_BW_ENABLE,Enable read bandwidth limiting" "0,1" group.long 0x100++0xB line.long 0x0 "REGS_RD_BW_CIR,Read Bandwidth Committed Information Rate" hexmask.long 0x0 0.--31. 1. "CIR,Committed Information Rate" line.long 0x4 "REGS_RD_BW_PIR,Read Bandwidth Peak Information Rate" hexmask.long 0x4 0.--31. 1. "PIR,Peak Information Rate" line.long 0x8 "REGS_RD_BW_BURST_OFFSET,Read Bandwidth Burst Offset" hexmask.long.word 0x8 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity. Peak Information Rate will still apply" rgroup.long 0x10C++0x3 line.long 0x0 "REGS_RD_BW_INFO,Read Bandwidth State machine information. Primarly for verification purposes" bitfld.long 0x0 0.--1. "COLOR,Read Bandwidth three-color marker output from rategen submodule" "0,1,2,3" group.long 0x120++0x7 line.long 0x0 "REGS_RD_BW_STATS,Read Bandwidth Statistics Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable read bandwidth statistics" "0,1" line.long 0x4 "REGS_RD_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR" hexmask.long 0x4 0.--31. 1. "THRESHOLD,Read bandwidth stats threshold in bytes. Note that this is total bytes unlike CIR and PIR. CIR and PIR are based on a rolling window and the statistics threshold is based on a fixed window. This will still take into account DDR bytes used so.." rgroup.long 0x128++0x13 line.long 0x0 "REGS_RD_BW_WINDOWS_CNT,Read Bandwidth Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Read bandwidth window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_RD_BW_CIR_CNT,Read Bandwidth Statistics - CIR Count" hexmask.long 0x4 0.--31. 1. "VAL,The total number of statistics windows in which Read Commit Information Rate occurred. Note that if PIR is set to a lower value than CIR or if the burst offset feature is used this will also count times that PIR is reached." line.long 0x8 "REGS_RD_BW_PIR_CNT,Read Bandwidth Statistics - PIR Count" hexmask.long 0x8 0.--31. 1. "VAL,The total number of statistics windows in which Read Peak Information Rate occurred" line.long 0xC "REGS_RD_BW_THRSHLD_CNT,Read Bandwidth Statistics - Threshold Count" hexmask.long 0xC 0.--31. 1. "VAL,The total number of statistics windows in which Read bytes transferred exceeded the statistics threshold" line.long 0x10 "REGS_RD_BYTES_MAX,The maximum number of bytes seen in a single statitsics window. This can be compared with the window size to calculate the maximum bandwidth seen" hexmask.long 0x10 0.--31. 1. "VAL,Max number of bytes in a single window. This number accounts for DDR bandwidth consumed not simply the accumulation of the packet bytecnt values across a window. The max bandwidth calculation is the total bytes value in this MMR divided by the.." group.long 0x300++0x3 line.long 0x0 "REGS_RD_TXN,The maximum number of outstanding read transactions the rate limiter will allow" hexmask.long.word 0x0 0.--15. 1. "LIMIT,The maximum number of outstanding read transactions allowed. NOTE: This cannot be programmed to a zero. If a zero is written it will default to the reset value of 16'd64 as a limit of zero outstanding transactions would hang the interface." rgroup.long 0x30C++0x3 line.long 0x0 "REGS_RD_TXN_INFO,Read Transaction State machine information. Primarly for verification purposes" hexmask.long.byte 0x0 0.--6. 1. "OCC,Read transaction scoreboard occupancy" group.long 0x320++0x7 line.long 0x0 "REGS_RD_TXN_STATS,Read Transaction Stats Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable read transaction statistics" "0,1" line.long 0x4 "REGS_RD_TXN_STATS_THRSHLD,A statistics threshold separate from the read transaction limit" hexmask.long.word 0x4 0.--15. 1. "THRESHOLD,Read transaction statistics threshold. The threshold can be set to any value though it will saturate at the outstanding transaction limit if it is set to a value greater than the programmed outstanding read transaction limit" rgroup.long 0x328++0x17 line.long 0x0 "REGS_RD_TXN_WINDOWS_CNT,Read Transaction Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Read transaction window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_RD_TXN_LMT_CNT,Read Transaction Statistics - number of windows in which the outstanding transaction limit was reached" hexmask.long 0x4 0.--31. 1. "VAL,The number of statistics windows in which the outstanding read transaction limit was reached" line.long 0x8 "REGS_RD_TXN_THRSHLD_CNT,Read Transaction Statistics - number of windows in which the statistics threshold was reached" hexmask.long 0x8 0.--31. 1. "VAL,The number of statistics windows in which the number of outstanding read transactions was greater than or equal to the threshold in RD_TXN_STATS_THRSHLD" line.long 0xC "REGS_RD_TXN_LIMIT_TOTAL,Read Transaction Statistics - Cycles at Outstanding Read Transactions Limit" hexmask.long 0xC 0.--31. 1. "VAL,The total number of cycles with the read transactions outstanding at the programmed limit since statistics collection began" line.long 0x10 "REGS_RD_TXN_THRSHLD_TOTAL,Read Transaction Statistics - Cycles at the Statistics Threshold" hexmask.long 0x10 0.--31. 1. "VAL,The total number of cycles with read transactions outstanding greater than or equal to the statistics threshold in RD_TXN_STATS_THRSHLD since statistics collection began" line.long 0x14 "REGS_RD_TXN_MAX,Read Transaction Statistics - Max Observed Outstanding Read Transactions" hexmask.long.word 0x14 0.--15. 1. "VAL,The maximum outstanding read transactions at any point in time regardless of the programmed limit" tree.end tree "CODEC_WS_BW_LIMITER3_REGS" base ad:0x30401000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,PID function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" group.long 0x4++0x3 line.long 0x0 "REGS_CTRL,This register controls the overall behavior of the rate limiter module" bitfld.long 0x0 4. "REGION_FILTER_EN,Enable the region filter which will only apply the bandwith and transaction limits to the configured address regions" "0,1" bitfld.long 0x0 3. "WR_TXN_ENABLE,Enable limiting maximum outstanding write transactions" "0,1" bitfld.long 0x0 2. "RD_TXN_ENABLE,Enable limiting maximum outstanding read transactions" "0,1" bitfld.long 0x0 1. "WR_BW_ENABLE,Enable write bandwidth limiting" "0,1" bitfld.long 0x0 0. "RD_BW_ENABLE,Enable read bandwidth limiting" "0,1" group.long 0x200++0xB line.long 0x0 "REGS_WR_BW_CIR,Write Bandwidth Committed Information Rate" hexmask.long 0x0 0.--31. 1. "CIR,Committed Information Rate" line.long 0x4 "REGS_WR_BW_PIR,Write Bandwidth Peak Information Rate" hexmask.long 0x4 0.--31. 1. "PIR,Peak Information Rate" line.long 0x8 "REGS_WR_BW_BURST_OFFSET,Write Bandwidth Burst Offset" hexmask.long.word 0x8 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity. Peak Information Rate will still apply" rgroup.long 0x20C++0x3 line.long 0x0 "REGS_WR_BW_INFO,Write Bandwidth State machine information. Primarly for verification purposes" bitfld.long 0x0 0.--1. "COLOR,Write Bandwidth three-color marker output from rategen submodule" "0,1,2,3" group.long 0x220++0x7 line.long 0x0 "REGS_WR_BW_STATS,Write Bandwidth Statistics Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable write bandwidth statistics" "0,1" line.long 0x4 "REGS_WR_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR" hexmask.long 0x4 0.--31. 1. "THRESHOLD,Write bandwidth stats threshold in bytes. Note that this is total bytes unlike CIR and PIR. CIR and PIR are based on a rolling window and the statistics threshold is based on a fixed window. This will still take into account DDR bytes used .." rgroup.long 0x228++0x13 line.long 0x0 "REGS_WR_BW_WINDOWS_CNT,Write Bandwidth Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Write bandwidth window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_WR_BW_CIR_CNT,Write Bandwidth Statistics - CIR Count" hexmask.long 0x4 0.--31. 1. "VAL,The total number of statistics windows in which Write Commit Information Rate occurred. Note that if PIR is set to a lower value than CIR or if the burst offset feature is used this will also count times that PIR is reached." line.long 0x8 "REGS_WR_BW_PIR_CNT,Write Bandwidth Statistics - PIR Count" hexmask.long 0x8 0.--31. 1. "VAL,The total number of statistics windows in which Write Peak Information Rate occurred" line.long 0xC "REGS_WR_BW_THRSHLD_CNT,Write Bandwidth Statistics - Threshold Count" hexmask.long 0xC 0.--31. 1. "VAL,The total number of statistics windows in which Write bytes transferred exceeded the statistics threshold" line.long 0x10 "REGS_WR_BYTES_MAX,The maximum number of bytes seen in a single statitsics window. This can be compared with the window size to calculate the maximum bandwidth seen" hexmask.long 0x10 0.--31. 1. "VAL,Max number of bytes in a single window. This number accounts for DDR bandwidth consumed not simply the accumulation of the packet bytecnt values across a window. The max bandwidth calculation is the total bytes value in this MMR divided by the.." group.long 0x400++0x3 line.long 0x0 "REGS_WR_TXN,The maximum number of outstanding write transactions the rate limiter will allow" hexmask.long.word 0x0 0.--15. 1. "LIMIT,The maximum number of outstanding write transactions allowed. NOTE: This cannot be programmed to a zero. If a zero is written it will default to the reset value of 16'd64 as a limit of zero outstanding transactions would hang the interface." rgroup.long 0x40C++0x3 line.long 0x0 "REGS_WR_TXN_INFO,Write Transaction State machine information. Primarly for verification purposes" hexmask.long.byte 0x0 0.--6. 1. "OCC,Write transaction scoreboard occupancy" group.long 0x420++0x7 line.long 0x0 "REGS_WR_TXN_STATS,Write Transaction Stats Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable write transaction statistics" "0,1" line.long 0x4 "REGS_WR_TXN_STATS_THRSHLD,A statistics threshold separate from the write transaction limit" hexmask.long.word 0x4 0.--15. 1. "THRESHOLD,Write transaction statistics threshold. The threshold can be set to any value though it will saturate at the outstanding transaction limit if it is set to a value greater than the programmed outstanding write transaction limit" rgroup.long 0x428++0x17 line.long 0x0 "REGS_WR_TXN_WINDOWS_CNT,Write Transaction Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Write transaction window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_WR_TXN_LMT_CNT,Write Transaction Statistics - number of windows in which the outstanding transaction limit was reached" hexmask.long 0x4 0.--31. 1. "VAL,The number of statistics windows in which the outstanding write transaction limit was reached" line.long 0x8 "REGS_WR_TXN_THRSHLD_CNT,Write Transaction Statistics - number of windows in which the statistics threshold was reached" hexmask.long 0x8 0.--31. 1. "VAL,The number of statistics windows in which the number of outstanding write transactions was greater than or equal to the threshold in WR_TXN_STATS_THRSHLD" line.long 0xC "REGS_WR_TXN_LIMIT_TOTAL,Write Transaction Statistics - Cycles at Outstanding Write Transactions Limit" hexmask.long 0xC 0.--31. 1. "VAL,The total number of cycles with the write transactions outstanding at the programmed limit since statistics collection began" line.long 0x10 "REGS_WR_TXN_THRSHLD_TOTAL,Write Transaction Statistics - Cycles at the Statistics Threshold" hexmask.long 0x10 0.--31. 1. "VAL,The total number of cycles with write transactions outstanding greater than or equal to the statistics threshold in WR_TXN_STATS_THRSHLD since statistics collection began" line.long 0x14 "REGS_WR_TXN_MAX,Write Transaction Statistics - Max Observed Outstanding Write Transactions" hexmask.long.word 0x14 0.--15. 1. "VAL,The maximum outstanding write transactions at any point in time regardless of the programmed limit" tree.end tree.end tree "CODEC0_VPU" base ad:0x30210000 wgroup.long 0x0++0x3 line.long 0x0 "VPU_REGS_VPU_PO_CONF,Power On Configuration" bitfld.long 0x0 3. "USE_PO_CONF,Host processor should set 0 when initialization" "0,1" bitfld.long 0x0 0. "DEBUGMODE,Power on Debug Mode" "0,1" rgroup.long 0x4++0x7 line.long 0x0 "VPU_REGS_VCPU_CUR_PC,Current PC" hexmask.long 0x0 0.--31. 1. "CUR_PC,PC value represents the address of instruction which is executed in V-CPU" line.long 0x4 "VPU_REGS_VCPU_CUR_LR,Current LR" hexmask.long 0x4 0.--31. 1. "CUR_LR,Current LR (Link Register) to find out caller address" group.long 0xC++0x3 line.long 0x0 "VPU_REGS_VPU_PDBG_STEP_MASK,V-CPU Debugger Step Mask" bitfld.long 0x0 0. "STEP_MASK_ENABLE,Interrupt Disable at step for debugger" "0,1" wgroup.long 0x10++0xF line.long 0x0 "VPU_REGS_VPU_PDBG_CTRL,V-CPU Debugger Control" bitfld.long 0x0 3. "IMMBRK,Immediate break" "0,1" bitfld.long 0x0 2. "STABLEBRK,Stable break" "0,1" bitfld.long 0x0 1. "RESUME,Resume" "0,1" newline bitfld.long 0x0 0. "STEP,Step" "0,1" line.long 0x4 "VPU_REGS_VPU_PDBG_IDX_REG,V-CPU Debugger Index" bitfld.long 0x4 9. "RDDBG,Read Operation Request" "0,1" bitfld.long 0x4 8. "WRDBG,Write Operation Request" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DBGIDX,Debug Index" line.long 0x8 "VPU_REGS_VPU_PDBG_WDATA_REG,V-CPU Debugger Write Data" hexmask.long 0x8 0.--31. 1. "VPU_PDBG_WDATA_REG,Write data to the debugger" line.long 0xC "VPU_REGS_VPU_PDBG_RDATA_REG,V-CPU Debugger Read Data" hexmask.long 0xC 0.--31. 1. "VPU_PDBG_RDATA_REG,Read data to the debugger" group.long 0x20++0x7 line.long 0x0 "VPU_REGS_VPU_FIO_CTRL_ADDR,FastIO Control/Address" rbitfld.long 0x0 31. "READY,Ready for the transaction" "0,1" bitfld.long 0x0 16. "RW_FLAG,Read/Write transaction control" "0,1" hexmask.long.word 0x0 0.--15. 1. "FIO_ADDR,FIO Address" line.long 0x4 "VPU_REGS_VPU_FIO_DATA,FastIO Data" hexmask.long 0x4 0.--31. 1. "FIO_DATA,FIO DATA" group.long 0x30++0x3 line.long 0x0 "VPU_REGS_VPU_VINT_REASON_USR,Interrupt Reason User" bitfld.long 0x0 15. "BSEMPTY_INTR_USER,Bitstream empty feeding request interrupt" "0,1" bitfld.long 0x0 14. "CMDE_INTR_USER,QUERY command done interrupt" "0,1" bitfld.long 0x0 13. "CMDD_INTR_USER,Low latency interrupt. Valid if low latency feature is enabled." "0,1" newline bitfld.long 0x0 10. "REL_SRC_INTR_USER,Release source buffer interrupt. Valid only if feature of release src buf is enabled" "0,1" bitfld.long 0x0 9. "CMD9_INTR_USER,ENC_SET_PARAM command done interrupt" "0,1" bitfld.long 0x0 8. "CMD8_INTR_USER,DEC_PIC/ENC_PIC command done interrupt" "0,1" newline bitfld.long 0x0 7. "CMD7_INTR_USER,SET_FRAMEBUFFER command done interrupt" "0,1" bitfld.long 0x0 6. "CMD6_INTR_USER,INIT_SEQ command done interrupt" "0,1" bitfld.long 0x0 5. "CMD5_INTR_USER,DESTROY_INSTANCE command done interrupt" "0,1" newline bitfld.long 0x0 4. "CMD4_INTR_USER,FLUSH_INSTANCE command done interrupt" "0,1" bitfld.long 0x0 3. "CMD3_INTR_USER,CREATE_INSTANCE command done interrupt" "0,1" bitfld.long 0x0 2. "CMD2_INTR_USER,SLEEP_VPU command done interrupt" "0,1" newline bitfld.long 0x0 1. "CMD1_INTR_USER,WAKE_VPU command done interrupt" "0,1" bitfld.long 0x0 0. "CMD0_INTR_USER,INIT_VPU command done interrupt" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "VPU_REGS_VPU_VINT_REASON_CLR,Interrupt Reason Clear" bitfld.long 0x0 15. "BSEMPTY_CLR,Bitstream empty bitstream feeding request interrupt clear" "0,1" bitfld.long 0x0 14. "CMDE_CLR,QUERY command done interrupt clear" "0,1" bitfld.long 0x0 13. "CMDD_CLR,Low Latency interrupt clear. Valid only if low latency feature is enabled" "0,1" newline bitfld.long 0x0 11. "INSUFFICIENT_VLC_BUFFER,VLC buffer realloc request interrupt enable. Valid only if VLC BUFFER CUSTOMIZATION features in VPU" "0,1" bitfld.long 0x0 10. "REL_SRC_CLR,Release source buffer interrupt. Valid only if the feature of release src buf is enabled" "0,1" bitfld.long 0x0 9. "CMD9_CLR,ENC_SET_PARAM command done interrupt clear" "0,1" newline bitfld.long 0x0 8. "CMD8_CLR,DEC_PIC/ENC_PIC command done interrupt clear" "0,1" bitfld.long 0x0 7. "CMD7_CLR,SET_FRAMEBUFFER command done interrupt clear" "0,1" bitfld.long 0x0 6. "CMD6_CLR,INIT_SEQ command done interrupt clear" "0,1" newline bitfld.long 0x0 5. "CMD5_CLR,DESTROY_INSTANCE command done interrupt clear" "0,1" bitfld.long 0x0 4. "CMD4_CLR,FLSUH_INSTANCE command done interrupt clear" "0,1" bitfld.long 0x0 3. "CMD3_CLR,CREATE_INSTANCE command done interrupt clear" "0,1" newline bitfld.long 0x0 2. "CMD2_CLR,SLEEP_VPU command done interrupt clear" "0,1" bitfld.long 0x0 1. "CMD1_CLR,WAKE_VPU command done interrupt clear" "0,1" bitfld.long 0x0 0. "CMD0_CLR,INIT_VPU command done interrupt clear" "0,1" group.long 0x38++0x3 line.long 0x0 "VPU_REGS_VPU_HOST_INT_REQ,Host Interrupt Request" bitfld.long 0x0 0. "HINTREQ,If this is set to 1 an interrupt named HOST interrupt is sent to VPU." "0,1" rgroup.long 0x3C++0x3 line.long 0x0 "VPU_REGS_VPU_VINT_CLEAR,VPU Interrupt Clear" bitfld.long 0x0 0. "VINTREQ,Clear VPU interrupt." "0,1" group.long 0x40++0x3 line.long 0x0 "VPU_REGS_VPU_HINT_CLEAR,Host Interrupt Clear" bitfld.long 0x0 0. "HINTCLR,Check Host Command Interrupt is cleared." "0,1" rgroup.long 0x44++0x3 line.long 0x0 "VPU_REGS_VPU_VPU_INT_STS,VPU Interrupt Status" bitfld.long 0x0 0. "VPU_VPU_INT_STS,Interrupt Status" "0,1" group.long 0x48++0xB line.long 0x0 "VPU_REGS_VPU_VINT_ENABLE,VPU Interrupt Enable" bitfld.long 0x0 15. "CMDF_EN,UPDATE_BS command done interrupt enable" "0,1" bitfld.long 0x0 14. "CMDE_EN,QUERY command done interrupt enable" "0,1" bitfld.long 0x0 13. "CMDD_EN,Low latency interrupt enable" "0,1" newline bitfld.long 0x0 11. "INSUFFICIENT_VLC_BUFFER,VLC Buffer Realloc request interrupt enable. Valid only if VLC BUFFER CUSTOMIZATION feature in VPU" "0,1" bitfld.long 0x0 10. "REL_SRC_EN,Release Source buffer interrupt enable. Valid only if feature of release src buf is enabled." "0,1" bitfld.long 0x0 9. "CMD9_EN,ENC_SET_PARAM command done interrupt enable" "0,1" newline bitfld.long 0x0 8. "CMD8_EN,DEC_PIC/ENC_PIC command done interrupt enable" "0,1" bitfld.long 0x0 7. "CMD7_EN,SET_FRAMEBUFFER command done interrupt enable" "0,1" bitfld.long 0x0 6. "CMD6_EN,SET_FRAMEBUFFER command done interrupt enable" "0,1" newline bitfld.long 0x0 5. "CMD5_EN,DESTROY_INSTANCE command done interrupt enable" "0,1" bitfld.long 0x0 4. "CMD4_EN,FLUSH INSTANCE command done interrupt enable" "0,1" bitfld.long 0x0 3. "CMD3_EN,CREATE INSTANCE command done interrupt enable" "0,1" newline bitfld.long 0x0 2. "CMD2_EN,SLEEP_VPU command done interrupt enable" "0,1" bitfld.long 0x0 1. "CMD1_EN,WAKE_VPU command done interrupt enable" "0,1" bitfld.long 0x0 0. "CMD0_EN,INIT_VPU command done interrupt enable" "0,1" line.long 0x4 "VPU_REGS_VPU_VINT_REASON,VPU Interrupt Reason" bitfld.long 0x4 15. "BSEMPTY_INTR,Bitstream empty bitstream feeding request." "0,1" bitfld.long 0x4 14. "CMDE_INTR,QUERY command done interrupt" "0,1" bitfld.long 0x4 13. "CMDD_INTR,Low latency interrupt" "0,1" newline bitfld.long 0x4 11. "INSUFFICIENT_VLC_BUFFER,VLC Buffer realloc request interrupt. Valid only if VLC BUFFER CUSTOMIZATION feature in VPU" "0,1" bitfld.long 0x4 10. "REL_SRC_INTR,Release source buffer Interrupt. Valid only if the feature of release src buf is enabled" "0,1" bitfld.long 0x4 9. "CMD9_INTR,ENC_SET_PARAM command done interrupt" "0,1" newline bitfld.long 0x4 8. "CMD8_INTR,DEC_PIC/ENC_PIC command done interrupt" "0,1" bitfld.long 0x4 7. "CMD7_INTR,SET_FRAMEBUFFER command done interrupt" "0,1" bitfld.long 0x4 6. "CMD6_INTR,INIT_SEQ command done interrupt" "0,1" newline bitfld.long 0x4 5. "CMD5_INTR,DESTROY_INSTANCE command done interrupt" "0,1" bitfld.long 0x4 4. "CMD4_INTR,FLUSH_INSTANCE command done interrupt" "0,1" bitfld.long 0x4 3. "CMD3_INTR,CREATE_INSTANCE command done interrupt" "0,1" newline bitfld.long 0x4 2. "CMD2_INTR,SLEEP_VPU command done interrupt" "0,1" bitfld.long 0x4 1. "CMD1_INTR,WAKE_VPU command done interrupt" "0,1" bitfld.long 0x4 0. "CMD0_INTR,INIT_VPU command done interrupt" "0,1" line.long 0x8 "VPU_REGS_VPU_RESET_REQ,VPU Reset Request" bitfld.long 0x8 26. "VCRST_REQ,CCLK domain for V-CPU Reset request" "0,1" bitfld.long 0x8 25. "VBRST_REQ,BCLK domain for V-CPU Reset request" "0,1" bitfld.long 0x8 24. "VARST_REQ,ACLK domain for V-CPU Reset request" "0,1" newline hexmask.long.byte 0x8 16.--19. 1. "ARST_REQ,ACLK domain reset request for each vCORE" hexmask.long.byte 0x8 8.--11. 1. "BRST_REQ,BCLK domain reset request for each vCORE" hexmask.long.byte 0x8 0.--3. 1. "CRST_REQ,CCLK domain reset request for each vCORE" rgroup.long 0x54++0x3 line.long 0x0 "VPU_REGS_VPU_RESET_STATUS,VPU Reset Status" bitfld.long 0x0 26. "VCRST_STS,CCLK domain for V-CPU reset status" "0,1" bitfld.long 0x0 25. "VBRST_STS,BCLK domain for V-CPU reset status" "0,1" bitfld.long 0x0 24. "VARST_STS,ACLK domain for V-CPU reset status" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "ARST_STS,ACLK domain for each V-Core reset status" hexmask.long.byte 0x0 8.--15. 1. "BRST_STS,BCLK domain for each V-Core reset status" hexmask.long.byte 0x0 0.--7. 1. "CRST_STS,CCLK domain for each V-Core reset status" wgroup.long 0x58++0x3 line.long 0x0 "VPU_REGS_VCPU_RESTART,V-CPU Restart Request" bitfld.long 0x0 0. "VCPU_RESTART_FIELD,This register restarts V-CPU from the reset vector without clearing H/W logic" "0,1" group.long 0x5C++0x17 line.long 0x0 "VPU_REGS_VPU_CLK_MASK,VPU Clock Control" bitfld.long 0x0 26. "CCLK_CPU_EN,CCLK domain for V-CPU Gating" "0,1" bitfld.long 0x0 25. "BCLK_CPU_EN,BCLK domain for V-CPU Gating" "0,1" bitfld.long 0x0 24. "ACLK_CPU_EN,ACLK domain for V-CPU Gating" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "ACLK_EN,ACLK domain for V-Core Gating" hexmask.long.byte 0x0 8.--15. 1. "BCLK_EN,BCLK domain for V-Core Gating" hexmask.long.byte 0x0 0.--7. 1. "CCLK_EN,CCLK domain for V-Core Gating" line.long 0x4 "VPU_REGS_VPU_REMAP_CTRL,Remap Control" rbitfld.long 0x4 31. "REMAP_GLOBEN,Set 1 if you want to change the [30:12] part of this register" "0,1" hexmask.long.byte 0x4 20.--23. 1. "AXIID_PROC,Upper AXI-ID for processor bus to distinguish guest OS" hexmask.long.byte 0x4 16.--19. 1. "ENDIAN,Endianness for memory access" newline hexmask.long.byte 0x4 12.--15. 1. "REMAP_IDX,Remap index" bitfld.long 0x4 11. "REMAP_PAGE_SIZE_EN,Set 1 if you want to change the REMAP_PSIZE field" "0,1" hexmask.long.word 0x4 0.--8. 1. "REMAP_PSIZE,Remap Page Size" line.long 0x8 "VPU_REGS_VPU_REMAP_VADDR,Remap Virutal Address" hexmask.long.tbyte 0x8 12.--31. 1. "VPU_REMAP_VADDR,Remap region base address in virtual address space." line.long 0xC "VPU_REGS_VPU_REMAP_PADDR,Remap Physical Address" hexmask.long.tbyte 0xC 12.--31. 1. "VPU_REMAP_PADDR,Real address (physical address) as a pair of virtual address." line.long 0x10 "VPU_REGS_VPU_REMAP_CORE_START,VPU Start Request" bitfld.long 0x10 0. "VPU_REMAP_CORE_START,It starts VPU after initial setting has been done." "0,1" line.long 0x14 "VPU_REGS_VPU_BUSY_STATUS,VPU Busy Status" bitfld.long 0x14 0. "VPU_BUSY_STATUS,Command Reentrance Check [0]" "0,1" rgroup.long 0x74++0x7 line.long 0x0 "VPU_REGS_VPU_HALT_STATUS,VPU Halt Status" bitfld.long 0x0 4. "VPU_HALT_STATUS,V-CPU is on the HALT Status" "0,1" hexmask.long.byte 0x0 0.--3. 1. "VPU_HALT_STATUS_DEBUG,For debugging" line.long 0x4 "VPU_REGS_VPU_VCPU_STATUS,VCPU STATUS" hexmask.long.word 0x4 0.--14. 1. "VPU_VCPU_STATUS,If [15:0] is 0x0040 V-CPU is on the halt status.Thus the value returns 0x40 power for VPU can be turnned-off" group.long 0x7C++0x3 line.long 0x0 "VPU_REGS_RSVD,RSVD" rgroup.long 0x80++0x3 line.long 0x0 "VPU_REGS_RET_FIO_STATUS,RETURN FIO STATUS" hexmask.long 0x0 0.--31. 1. "RESERVED,RET FIO STATUS" rgroup.long 0x90++0xB line.long 0x0 "VPU_REGS_RET_PRODUCT_NAME,HW product name" bitfld.long 0x0 0.--2. "HW_NAME,VPU hardware product name" "0,1,2,3,4,5,6,7" line.long 0x4 "VPU_REGS_RET_PRODUCT_VERSION,HW product version" bitfld.long 0x4 0.--2. "HW_VERSION,VPU hardware product version" "0,1,2,3,4,5,6,7" line.long 0x8 "VPU_REGS_RET_VCPU_CONFIG0,Configuration Information 0" hexmask.long 0x8 0.--31. 1. "RESERVED,Configuration Information 0" rgroup.long 0x98++0x3 line.long 0x0 "VPU_REGS_RET_VCPU_CONFIG1,Configuration Information 0" hexmask.long 0x0 4.--31. 1. "RESERVED,Configuration Information 0" bitfld.long 0x0 3. "AVC_DEC_EN,AVC decoder Enable" "0,1" bitfld.long 0x0 2. "HEVC_DEC_EN,HEVC decoder Enable" "0,1" newline bitfld.long 0x0 1. "AVC_ENC_EN,AVC encoder Enable" "0,1" bitfld.long 0x0 0. "HEVC_ENC_EN,HEVC encoder Enable" "0,1" rgroup.long 0xA0++0x23 line.long 0x0 "VPU_REGS_RET_CODEC_STD,Standard Definition" hexmask.long 0x0 0.--31. 1. "CODEC_STD,General Configuration Information - Internal Use only" line.long 0x4 "VPU_REGS_RET_CONF_DATE,Configuration Date" hexmask.long 0x4 0.--31. 1. "HW_DATE,The date that the hardware has been configured in YYYYMMDD. Internal Use only." line.long 0x8 "VPU_REGS_RET_CONF_REVISION,The revision of H/W configuration" hexmask.long 0x8 0.--31. 1. "HW_VERSION,Revision Number when the hardware has been configured. Internal Use only" line.long 0xC "VPU_REGS_RET_CONF_TYPE,The define value of H/W configuration" hexmask.long 0xC 0.--31. 1. "HW_TYPE,The define value used in hardware configuration. Internal Use only." line.long 0x10 "VPU_REGS_RET_VCORE0_CFG,Configuration Information of VCORE0" hexmask.long 0x10 0.--31. 1. "CONFIG_VCORE0,The VCORE0 configuration information. Internal Use only" line.long 0x14 "VPU_REGS_RET_VCORE1_CFG,Configuration Information of VCORE1" hexmask.long 0x14 0.--31. 1. "CONFIG_VCORE1,The VCORE1 configuration information. Internal Use only" line.long 0x18 "VPU_REGS_RET_VCORE2_CFG,Configuration Information of VCORE2" hexmask.long 0x18 0.--31. 1. "CONFIG_VCORE2,The VCORE2 configuration information. Internal Use only" line.long 0x1C "VPU_REGS_RET_VCORE3_CFG,Configuration Information of VCORE3" hexmask.long 0x1C 0.--31. 1. "CONFIG_VCORE3,The VCORE3 configuration information. Internal Use only" line.long 0x20 "VPU_REGS_VPU_RET_VCORE_PRESET,Number of VCOREs present" hexmask.long.byte 0x20 0.--3. 1. "VCORE_PRESENT,Each bit represent turn-on VCORE" tree.end tree "COMPUTE_CLUSTER0_PBIST_0_PBIST" base ad:0x330000 group.long 0x0++0x7F line.long 0x0 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF0L" hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF1L" hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF2L" hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF3L" hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF4L" hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF5L" hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF6L" hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF7L" hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF8L" hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF9L" hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF10L" hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF11L" hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF12L" hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF13L" hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF14L" hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF15L" hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF0U" hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF1U" hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF2U" hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF3U" hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF4U" hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF5U" hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF6U" hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF7U" hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF8U" hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF9U" hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF10U" hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF11U" hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF12U" hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF13U" hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF14U" hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF15U" hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" group.long 0x100++0x27 line.long 0x0 "K3_PBIST_4C28P_4BIT_WRAP_REGS_A0" hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "K3_PBIST_4C28P_4BIT_WRAP_REGS_A1" hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "K3_PBIST_4C28P_4BIT_WRAP_REGS_A2" hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "K3_PBIST_4C28P_4BIT_WRAP_REGS_A3" hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "K3_PBIST_4C28P_4BIT_WRAP_REGS_L0" hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "K3_PBIST_4C28P_4BIT_WRAP_REGS_L1" hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "K3_PBIST_4C28P_4BIT_WRAP_REGS_L2" hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "K3_PBIST_4C28P_4BIT_WRAP_REGS_L3" hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "K3_PBIST_4C28P_4BIT_WRAP_REGS_D" hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "K3_PBIST_4C28P_4BIT_WRAP_REGS_E" hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" group.long 0x130++0x3F line.long 0x0 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CA0" hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CA1" hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CA2" hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "K3_PBIST_4C28P_4BIT_WRAP_REGS_CA3" hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CL0" hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CL1" hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CL2" hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "K3_PBIST_4C28P_4BIT_WRAP_REGS_CL3" hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "K3_PBIST_4C28P_4BIT_WRAP_REGS_I0" hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "K3_PBIST_4C28P_4BIT_WRAP_REGS_I1" hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "K3_PBIST_4C28P_4BIT_WRAP_REGS_I2" hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "K3_PBIST_4C28P_4BIT_WRAP_REGS_I3" hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RAMT" hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" newline bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "K3_PBIST_4C28P_4BIT_WRAP_REGS_DLR" hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" newline bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" newline bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CMS" hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "K3_PBIST_4C28P_4BIT_WRAP_REGS_STR" bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" newline bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" group.quad 0x170++0x7 line.quad 0x0 "K3_PBIST_4C28P_4BIT_WRAP_REGS_SCR" hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" newline hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" group.long 0x178++0x13 line.long 0x0 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CSR" hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "K3_PBIST_4C28P_4BIT_WRAP_REGS_FDLY" hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "K3_PBIST_4C28P_4BIT_WRAP_REGS_PACT" bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "K3_PBIST_4C28P_4BIT_WRAP_REGS_PID" hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "K3_PBIST_4C28P_4BIT_WRAP_REGS_OVER" bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "K3_PBIST_4C28P_4BIT_WRAP_REGS_FSRF" bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "K3_PBIST_4C28P_4BIT_WRAP_REGS_FSRC" hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "K3_PBIST_4C28P_4BIT_WRAP_REGS_FSRA" hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "K3_PBIST_4C28P_4BIT_WRAP_REGS_FSRDL0" hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "K3_PBIST_4C28P_4BIT_WRAP_REGS_FSRDL1" hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "K3_PBIST_4C28P_4BIT_WRAP_REGS_MARGIN_MODE" bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "K3_PBIST_4C28P_4BIT_WRAP_REGS_WRENZ" bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "K3_PBIST_4C28P_4BIT_WRAP_REGS_PAGE_PGS" bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" group.long 0x1C0++0x7 line.long 0x0 "K3_PBIST_4C28P_4BIT_WRAP_REGS_ROM" bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "K3_PBIST_4C28P_4BIT_WRAP_REGS_ALGO" hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" group.quad 0x1C8++0x7 line.quad 0x0 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RINFO" hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" newline hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree "CPSW0" base ad:0x0 tree "CPSW0_ECC" base ad:0x704000 rgroup.long 0x0++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_ECC_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1" bitfld.long 0x4 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1" bitfld.long 0x4 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1" newline bitfld.long 0x4 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1" bitfld.long 0x4 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1" bitfld.long 0x4 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1" newline bitfld.long 0x4 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1" bitfld.long 0x4 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1" bitfld.long 0x4 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1" newline bitfld.long 0x4 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1" bitfld.long 0x4 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1" bitfld.long 0x4 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1" newline bitfld.long 0x4 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1" bitfld.long 0x4 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1" bitfld.long 0x4 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1" newline bitfld.long 0x4 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1" bitfld.long 0x4 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1" bitfld.long 0x4 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1" newline bitfld.long 0x4 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1" newline bitfld.long 0x0 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1" bitfld.long 0x0 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1" newline bitfld.long 0x0 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1" bitfld.long 0x0 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1" newline bitfld.long 0x0 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1" newline bitfld.long 0x0 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1" bitfld.long 0x0 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1" newline bitfld.long 0x0 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1" bitfld.long 0x0 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1" newline bitfld.long 0x0 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_ECC_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1" bitfld.long 0x4 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1" bitfld.long 0x4 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1" newline bitfld.long 0x4 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1" bitfld.long 0x4 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1" bitfld.long 0x4 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1" newline bitfld.long 0x4 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1" bitfld.long 0x4 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1" bitfld.long 0x4 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1" newline bitfld.long 0x4 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1" bitfld.long 0x4 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1" bitfld.long 0x4 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1" newline bitfld.long 0x4 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1" bitfld.long 0x4 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1" bitfld.long 0x4 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1" newline bitfld.long 0x4 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1" bitfld.long 0x4 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1" bitfld.long 0x4 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1" newline bitfld.long 0x4 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1" newline bitfld.long 0x0 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1" bitfld.long 0x0 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1" newline bitfld.long 0x0 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1" bitfld.long 0x0 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1" newline bitfld.long 0x0 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_ECC_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1" bitfld.long 0x0 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1" bitfld.long 0x0 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1" newline bitfld.long 0x0 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1" bitfld.long 0x0 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1" bitfld.long 0x0 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1" newline bitfld.long 0x0 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1" bitfld.long 0x0 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1" bitfld.long 0x0 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1" newline bitfld.long 0x0 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1" bitfld.long 0x0 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1" bitfld.long 0x0 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1" newline bitfld.long 0x0 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1" bitfld.long 0x0 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1" bitfld.long 0x0 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1" newline bitfld.long 0x0 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1" bitfld.long 0x0 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1" bitfld.long 0x0 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1" newline bitfld.long 0x0 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" group.long 0x200++0xF line.long 0x0 "CPSW_NUSS_VBUSP_ECC_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_ECC_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "CPSW_NUSS_VBUSP_ECC_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "CPSW_NUSS_VBUSP_ECC_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "CPSW0_NUSS" base ad:0x8000000 rgroup.long 0x0++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_CPSW_NUSS_IDVER_REG,ID Version Register" hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification value" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" group.long 0x4++0x13 line.long 0x0 "CPSW_NUSS_VBUSP_SYNCE_COUNT_REG,SyncE Count Register" hexmask.long 0x0 0.--31. 1. "SYNCE_CNT,Sync E Count Value" line.long 0x4 "CPSW_NUSS_VBUSP_SYNCE_MUX_REG,SyncE Mux Register" hexmask.long.byte 0x4 0.--5. 1. "SYNCE_SEL,Sync E Select Value" line.long 0x8 "CPSW_NUSS_VBUSP_CONTROL_REG,Control Register" bitfld.long 0x8 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode: 0=The low power indicate state includes gating off the CPPI_GCLK to the CPSW 1=The low power indicate state does not gate the clock to the CPSW" "0: The low power indicate state includes gating off..,1: The low power indicate state does not gate the.." newline bitfld.long 0x8 0. "EEE_EN,Energy Efficient Ethernet Enable: 0=EEE is disabled 1=EEE is enabled" "0: EEE is disabled,1: EEE is enabled" line.long 0xC "CPSW_NUSS_VBUSP_SGMII_NON_FIBER_MODE_REG,SGMII NON FIBER Mode Register" bitfld.long 0xC 0.--1. "SGMII_NON_FIBER_MODE,This register bit goes to the CPSGMII mode input only" "0,1,2,3" line.long 0x10 "CPSW_NUSS_VBUSP_SERDES_RESET_ISO_REG,SyncE Mux Register" bitfld.long 0x10 0.--1. "SERDES_RESET_ISO,These bits control whether the SERDES ignores the hard reset for isolation or not" "0,1,2,3" rgroup.long 0x1C++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_SUBSSYSTEM_STATUS_REG,Subsystem Status Register" bitfld.long 0x0 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_SUBSYSTEM_CONFIG_REG,Subsystem Configuration Register" hexmask.long.byte 0x4 20.--27. 1. "XGMII,The Number of XGMII Ports included in the CPSW_NUSS" newline bitfld.long 0x4 19. "QSGMII,QSGMII is included in the CPSW_NUSS" "0,1" newline bitfld.long 0x4 18. "SGMII,SGMII is included in the CPSW_NUSS" "0,1" newline bitfld.long 0x4 17. "RGMII,RGMII is included in the CPSW_NUSS" "0,1" newline bitfld.long 0x4 16. "RMII,RMII is included in the CPSW_NUSS" "0,1" newline hexmask.long.byte 0x4 8.--12. 1. "NUM_GENF,The number of CPTS GENF outputs" newline hexmask.long.byte 0x4 0.--7. 1. "NUM_PORTS,The total number of ports including the host port 0" rgroup.long 0x30++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_RGMII1_STATUS_REG,RGMII1 Status Register" bitfld.long 0x0 3. "FULLDUPLEX,Rgmii1 full dulex: 0=Half-duplex 1=Full-duplex" "0: Half-duplex,1: Full-duplex" newline bitfld.long 0x0 1.--2. "SPEED,Rgmii1 speed: 00=10Mbps 01=100Mbps 10=1000Mbps 11=reserved" "0: 10Mbps,1: 100Mbps,?,?" newline bitfld.long 0x0 0. "LINK,Rgmii1 link indicator: 0=Link is down 1=Link is up" "0: Link is down,1: Link is up" line.long 0x4 "CPSW_NUSS_VBUSP_RGMII2_STATUS_REG,RGMII2 Status Register" bitfld.long 0x4 3. "FULLDUPLEX,Rgmii2 full dulex: 0=Half-duplex 1=Full-duplex" "0: Half-duplex,1: Full-duplex" newline bitfld.long 0x4 1.--2. "SPEED,Rgmii2 speed: 00=10Mbps 01=100Mbps 10=1000Mbps 11=reserved" "0: 10Mbps,1: 100Mbps,?,?" newline bitfld.long 0x4 0. "LINK,Rgmii2 link indicator: 0=Link is down 1=Link is up" "0: Link is down,1: Link is up" rgroup.long 0x100++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_SGMII_IDVER_REG,SGMII IDVER register" hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,MODULE value" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" group.long 0x104++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_SOFT_RESET_REG,SGMII Soft Reset Register" bitfld.long 0x0 1. "RT_SOFT_RESET,Transmit and receive software reset" "0,1" newline bitfld.long 0x0 0. "SOFT_RESET,Software reset" "0,1" group.long 0x110++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_CONTROL_REG,SGMII Control Register" bitfld.long 0x0 6. "TEST_PATTERN_EN,Test pattern enable" "0,1" newline bitfld.long 0x0 5. "MASTER,Master mode" "0,1" newline bitfld.long 0x0 4. "LOOPBACK,Loopback mode" "0,1" newline bitfld.long 0x0 3. "MR_NP_LOADED,Next page loaded" "0,1" newline bitfld.long 0x0 2. "FAST_LINK_TIMER,Fast link timer" "0,1" newline bitfld.long 0x0 1. "MR_AN_RESTART,Auto-negotiation restart" "0,1" newline bitfld.long 0x0 0. "MR_AN_ENABLE,Auto-negotiation enable" "0,1" rgroup.long 0x114++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_STATUS_REG,SGMII Status Register" bitfld.long 0x0 5. "FIB_SIG_DETECT,Fiber signal detect" "0,1" newline bitfld.long 0x0 4. "LOCK,Lock" "0,1" newline bitfld.long 0x0 3. "MR_PAGE_RX,Next page received" "0,1" newline bitfld.long 0x0 2. "MR_AN_COMPLETE,Auto-negotiation complete" "0,1" newline bitfld.long 0x0 1. "AN_ERROR,Auto-negotiation error" "0,1" newline bitfld.long 0x0 0. "LINK,Link indicator" "0,1" group.long 0x118++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_MR_ADV_ABILITY_REG,SGMII MR Advertized Ability Register" hexmask.long.word 0x0 0.--15. 1. "MR_ADV_ABILITY,Advertised ability" line.long 0x4 "CPSW_NUSS_VBUSP_MR_NP_TX_REG,SGMII Next Pate Transmit Register" hexmask.long.word 0x4 0.--15. 1. "MR_NP_TX,Next page transmit" rgroup.long 0x120++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_MR_LP_ADV_ABILITY_REG,SGMII Link Partner Advertized Ability Register" hexmask.long.word 0x0 0.--15. 1. "MR_LP_ADV_ABILITY,Link partner advertised ability" line.long 0x4 "CPSW_NUSS_VBUSP_MR_LP_NP_RX_REG,SGMII Link Partner Next Page Receive Register" hexmask.long.word 0x4 0.--15. 1. "MR_LP_NP_RX,Link Partner Next Page Received" group.long 0x140++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_DIAG_CLEAR_REG,SGMII Diagnostics Clear Register" bitfld.long 0x0 0. "DIAG_CLEAR,Diagnostics clear" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_DIAG_CONTROL_REG,SGMII Diagnostics Control Register" bitfld.long 0x4 4.--6. "DIAG_SM_SEL,Diagnostic select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--1. "DIAG_EDGE_SEL,Diagnostics hold signals edge select" "0,1,2,3" rgroup.long 0x148++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_DIAG_STATUS_REG,SGMII Diagnostics Status Register" hexmask.long.word 0x0 0.--15. 1. "DIAG_STATUS,Diagnostics status" rgroup.long 0xF00++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_MDIO_VERSION_REG,MDIO Version Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0xF04++0x7 line.long 0x0 "CPSW_NUSS_VBUSP_CONTROL_REG,MDIO Control Register" rbitfld.long 0x0 31. "IDLE,MDIO state machine idle" "0,1" newline bitfld.long 0x0 30. "ENABLE,Enable control" "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "HIGHEST_USER_CHANNEL,Highest user channel" newline bitfld.long 0x0 20. "PREAMBLE,Preamble disable" "0,1" newline bitfld.long 0x0 19. "FAULT,Fault indicator" "0,1" newline bitfld.long 0x0 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1" newline bitfld.long 0x0 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "CLKDIV,Clock divider" line.long 0x4 "CPSW_NUSS_VBUSP_ALIVE_REG,MDIO Alive Register" hexmask.long 0x4 0.--31. 1. "ALIVE,MDIO alive" rgroup.long 0xF0C++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_LINK_REG,MDIO Link Register" hexmask.long 0x0 0.--31. 1. "LINK,MDIO link state" group.long 0xF10++0x37 line.long 0x0 "CPSW_NUSS_VBUSP_LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register" bitfld.long 0x0 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3" line.long 0x4 "CPSW_NUSS_VBUSP_LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register" bitfld.long 0x4 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3" line.long 0x8 "CPSW_NUSS_VBUSP_LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register" bitfld.long 0x8 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1" line.long 0xC "CPSW_NUSS_VBUSP_LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register" bitfld.long 0xC 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1" line.long 0x10 "CPSW_NUSS_VBUSP_USER_INT_RAW_REG,MDIO User Interrupt Raw Register" bitfld.long 0x10 0.--1. "USERINTRAW,User interrupt raw" "0,1,2,3" line.long 0x14 "CPSW_NUSS_VBUSP_USER_INT_MASKED_REG,MDIO User Interrupt Masked Register" bitfld.long 0x14 0.--1. "USERINTMASKED,User interrupt masked" "0,1,2,3" line.long 0x18 "CPSW_NUSS_VBUSP_USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register" bitfld.long 0x18 0.--1. "USERINTMASKSET,MDIO user interrupt mask set" "0,1,2,3" line.long 0x1C "CPSW_NUSS_VBUSP_USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register" bitfld.long 0x1C 0.--1. "USERINTMASKCLR,MDIO user interrupt mask clear" "0,1,2,3" line.long 0x20 "CPSW_NUSS_VBUSP_MANUAL_IF_REG,MDIO Manual Interface Register" bitfld.long 0x20 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1" newline bitfld.long 0x20 1. "MDIO_OE,MDIO Output Enable" "0,1" newline bitfld.long 0x20 0. "MDIO_PIN,MDIO Pin" "0,1" line.long 0x24 "CPSW_NUSS_VBUSP_POLL_REG,MDIO Poll Register" bitfld.long 0x24 31. "MANUALMODE,MDIO Manual Mode" "0,1" newline bitfld.long 0x24 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1" newline hexmask.long.byte 0x24 0.--7. 1. "IPG,MDIO IPG" line.long 0x28 "CPSW_NUSS_VBUSP_POLL_EN_REG,MDIO Poll Enable Register" hexmask.long 0x28 0.--31. 1. "POLL_EN,MDIO Poll Enable" line.long 0x2C "CPSW_NUSS_VBUSP_CLAUS45_REG,MDIO Clause45 Register" hexmask.long 0x2C 0.--31. 1. "CLAUSE45,MDIO Clause 45" line.long 0x30 "CPSW_NUSS_VBUSP_USER_ADDR0_REG,MDIO Address 0 Register" hexmask.long.word 0x30 0.--15. 1. "USER_ADDR0,MDIO USER Address 0" line.long 0x34 "CPSW_NUSS_VBUSP_USER_ADDR1_REG,MDIO Address 1 Register" hexmask.long.word 0x34 0.--15. 1. "USER_ADDR1,MDIO USER Address 1" rgroup.long 0x1000++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_REVISION,Revision Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTLVER,RTL revisions" newline bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision" group.long 0x1010++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_eoi_reg,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector" rgroup.long 0x1014++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_intr_vector_reg,Interrupt Vector Register" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR,Interrupt Vector Register" group.long 0x1100++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_enable_reg_out_pulse_0,Enable Register 0" bitfld.long 0x0 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA,Enable Set for out_pulse_en_stat_penda" "0,1" newline bitfld.long 0x0 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA,Enable Set for out_pulse_en_mdio_penda" "0,1" newline bitfld.long 0x0 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA,Enable Set for out_pulse_en_evnt_penda" "0,1" group.long 0x1300++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_enable_clr_reg_out_pulse_0,Enable Clear Register 0" bitfld.long 0x0 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA_CLR,Enable Clear for out_pulse_en_stat_penda" "0,1" newline bitfld.long 0x0 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA_CLR,Enable Clear for out_pulse_en_mdio_penda" "0,1" newline bitfld.long 0x0 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA_CLR,Enable Clear for out_pulse_en_evnt_penda" "0,1" rgroup.long 0x1500++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_status_reg_out_pulse_0,Status Register 0" bitfld.long 0x0 2. "STATUS_OUT_PULSE_STAT_PENDA,Status for out_pulse_en_stat_penda" "0,1" newline bitfld.long 0x0 1. "STATUS_OUT_PULSE_MDIO_PENDA,Status for out_pulse_en_mdio_penda" "0,1" newline bitfld.long 0x0 0. "STATUS_OUT_PULSE_EVNT_PENDA,Status for out_pulse_en_evnt_penda" "0,1" rgroup.long 0x1A80++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_intr_vector_reg_out_pulse,Interrupt Vector for out_pulse" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR_OUT_PULSE,Interrupt Vector" rgroup.long 0x20000++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_CPSW_ID_VER_REG,CPSW ID Version" hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification Value" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL Version Value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor Version Value" group.long 0x20004++0x3 line.long 0x0 "CPSW_NUSS_VBUSP_CONTROL_REG,CPSW Switch Control" bitfld.long 0x0 31. "ECC_CRC_MODE,ECC CRC Mode" "0,1" newline bitfld.long 0x0 19. "CUT_THRU_ENABLE,Cut-Thru enable" "0,1" newline bitfld.long 0x0 18. "EST_ENABLE,Intersperced Express Traffic enable" "0,1" newline bitfld.long 0x0 17. "IET_ENABLE,Intersperced Express Traffic enable" "0,1" newline bitfld.long 0x0 16. "EEE_ENABLE,Energy Efficient Ethernet enable" "0,1" newline bitfld.long 0x0 15. "P0_RX_PASS_CRC_ERR,Port 0 Pass Received CRC errors" "0,1" newline bitfld.long 0x0 14. "P0_RX_PAD,Port 0 Receive Short Packet Pad" "0,1" newline bitfld.long 0x0 13. "P0_TX_CRC_REMOVE,Port 0 Transmit CRC remove" "0,1" newline bitfld.long 0x0 12. "P0_TX_CRC_TYPE,Port 0 Transmit CRC Type" "0,1" newline bitfld.long 0x0 11. "P8_PASS_PRI_TAGGED,Port 8 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 10. "P7_PASS_PRI_TAGGED,Port 7 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 9. "P6_PASS_PRI_TAGGED,Port 6 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 8. "P5_PASS_PRI_TAGGED,Port 5 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 7. "P4_PASS_PRI_TAGGED,Port 4 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 6. "P3_PASS_PRI_TAGGED,Port 3 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 5. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 4. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 3. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "0,1" newline bitfld.long 0x0 2. "P0_ENABLE,Port 0 Enable" "0,1" newline bitfld.long 0x0 1. "VLAN_AWARE,VLAN Aware Mode" "0,1" newline bitfld.long 0x0 0. "S_CN_SWITCH,VLAN Aware Mode" "0,1" group.long 0x20010++0x17 line.long 0x0 "CPSW_NUSS_VBUSP_EM_CONTROL_REG,CPSW Emulation Control" bitfld.long 0x0 1. "SOFT,Emulation Soft Bit" "0,1" newline bitfld.long 0x0 0. "FREE,Emulation Free Bit" "0,1" line.long 0x4 "CPSW_NUSS_VBUSP_STAT_PORT_EN_REG,CPSW Statistics Port Enable" bitfld.long 0x4 8. "P8_STAT_EN,Port 8 Statistics Enable" "0,1" newline bitfld.long 0x4 7. "P7_STAT_EN,Port 7 Statistics Enable" "0,1" newline bitfld.long 0x4 6. "P6_STAT_EN,Port 6 Statistics Enable" "0,1" newline bitfld.long 0x4 5. "P5_STAT_EN,Port 5 Statistics Enable" "0,1" newline bitfld.long 0x4 4. "P4_STAT_EN,Port 4 Statistics Enable" "0,1" newline bitfld.long 0x4 3. "P3_STAT_EN,Port 3 Statistics Enable" "0,1" newline bitfld.long 0x4 2. "P2_STAT_EN,Port 2 Statistics Enable" "0,1" newline bitfld.long 0x4 1. "P1_STAT_EN,Port 1 Statistics Enable" "0,1" newline bitfld.long 0x4 0. "P0_STAT_EN,Port 0 Statistics Enable" "0,1" line.long 0x8 "CPSW_NUSS_VBUSP_PTYPE_REG,CPSW Transmit Priority Type" bitfld.long 0x8 16. "P8_PTYPE_ESC,Port 8 Priority Type Escalate" "0,1" newline bitfld.long 0x8 15. "P7_PTYPE_ESC,Port 7 Priority Type Escalate" "0,1" newline bitfld.long 0x8 14. "P6_PTYPE_ESC,Port 6 Priority Type Escalate" "0,1" newline bitfld.long 0x8 13. "P5_PTYPE_ESC,Port 5 Priority Type Escalate" "0,1" newline bitfld.long 0x8 12. "P4_PTYPE_ESC,Port 4 Priority Type Escalate" "0,1" newline bitfld.long 0x8 11. "P3_PTYPE_ESC,Port 3 Priority Type Escalate" "0,1" newline bitfld.long 0x8 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate" "0,1" newline bitfld.long 0x8 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "0,1" newline bitfld.long 0x8 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "0,1" newline hexmask.long.byte 0x8 0.--4. 1. "ESC_PRI_LD_VAL,Escalate Priority Load Value" line.long 0xC "CPSW_NUSS_VBUSP_SOFT_IDLE_REG,CPSW Software Idle" bitfld.long 0xC 0. "SOFT_IDLE,Software Idle" "0,1" line.long 0x10 "CPSW_NUSS_VBUSP_THRU_RATE_REG,CPSW Thru Rate" hexmask.long.byte 0x10 12.--15. 1. "SL_RX_THRU_RATE,Switch FIFO receive through rate" newline hexmask.long.byte 0x10 0.--3. 1. "P0_RX_THRU_RATE,CPPI FIFO receive through rate" line.long 0x14 "CPSW_NUSS_VBUSP_GAP_THRESH_REG,CPSW Transmit FIFO Short Gap Threshold" hexmask.long.byte 0x14 0.--4. 1. "GAP_THRESH,Short Gap Threshold" group.long 0x2002C++0x1B line.long 0x0 "CPSW_NUSS_VBUSP_EEE_PRESCALE_REG,CPSW Energy Efficient Ethernet Prescale Value" hexmask.long.word 0x0 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value" line.long 0x4 "CPSW_NUSS_VBUSP_TX_G_OFLOW_THRESH_SET_REG,CPSW PFC Tx Global Out Flow Threshold Set" hexmask.long.byte 0x4 28.--31. 1. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" newline hexmask.long.byte 0x4 24.--27. 1. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" newline hexmask.long.byte 0x4 20.--23. 1. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" newline hexmask.long.byte 0x4 16.--19. 1. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" newline hexmask.long.byte 0x4 12.--15. 1. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" newline hexmask.long.byte 0x4 8.--11. 1. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" newline hexmask.long.byte 0x4 4.--7. 1. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" newline hexmask.long.byte 0x4 0.--3. 1. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" line.long 0x8 "CPSW_NUSS_VBUSP_TX_G_OFLOW_THRESH_CLR_REG,CPSW PFC Tx Global Out Flow Threshold Clear" hexmask.long.byte 0x8 28.--31. 1. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" newline hexmask.long.byte 0x8 24.--27. 1. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" newline hexmask.long.byte 0x8 20.--23. 1. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" newline hexmask.long.byte 0x8 16.--19. 1. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" newline hexmask.long.byte 0x8 12.--15. 1. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" newline hexmask.long.byte 0x8 8.--11. 1. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" newline hexmask.long.byte 0x8 4.--7. 1. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" newline hexmask.long.byte 0x8 0.--3. 1. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" line.long 0xC "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_SET_L_REG,CPSW PFC Global Tx Buffer Threshold Set Low" hexmask.long.byte 0xC 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3" newline hexmask.long.byte 0xC 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2" newline hexmask.long.byte 0xC 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1" newline hexmask.long.byte 0xC 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0" line.long 0x10 "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_SET_H_REG,CPSW PFC Global Tx Buffer Threshold Set High" hexmask.long.byte 0x10 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7" newline hexmask.long.byte 0x10 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6" newline hexmask.long.byte 0x10 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5" newline hexmask.long.byte 0x10 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4" line.long 0x14 "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_CLR_L_REG,CPSW PFC Global Tx Buffer Threshold Clear Low" hexmask.long.byte 0x14 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3" newline hexmask.long.byte 0x14 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2" newline hexmask.long.byte 0x14 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1" newline hexmask.long.byte 0x14 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0" line.long 0x18 "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_CLR_H_REG,CPSW PFC Global Tx Buffer Threshold Clear High" hexmask.long.byte 0x18 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7" newline hexmask.long.byte 0x18 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6" newline hexmask.long.byte 0x18 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5" newline hexmask.long.byte 0x18 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4" group.long 0x20050++0x13 line.long 0x0 "CPSW_NUSS_VBUSP_VLAN_LTYPE_REG,VLAN Length/type" hexmask.long.word 0x0 16.--31. 1. "VLAN_LTYPE_OUTER,Outer VLAN LType" newline hexmask.long.word 0x0 0.--15. 1. "VLAN_LTYPE_INNER,Inner VLAN LType" line.long 0x4 "CPSW_NUSS_VBUSP_EST_TS_DOMAIN_REG,Enhanced Scheduled Traffic Host Event Domain" hexmask.long.byte 0x4 0.--7. 1. "EST_TS_DOMAIN,Enhanced Scheduled Traffic Host Event Domain" line.long 0x8 "CPSW_NUSS_VBUSP_CUT_THRESHOLD_REG,Cut-thru Threshold" hexmask.long.byte 0x8 0.--3. 1. "CUT_THRESH,Cut-thru Threshold" line.long 0xC "CPSW_NUSS_VBUSP_FREQUENCY_REG,CPSW CPPI_CLK Frequency in Mhz" hexmask.long.word 0xC 0.--9. 1. "CUT_THRESH,CPSW CPPI_CLK Frequency in Mhz" line.long 0x10 "CPSW_NUSS_VBUSP_IET_HOLD_CNT_LD_VAL_REG,IET Hold Count Load Value for cut thru packets" hexmask.long.byte 0x10 0.--7. 1. "IET_HOLD_CNT_LD_VAL,IET_HOLD_CNT_LD_VAL" group.long 0x20100++0x1F line.long 0x0 "CPSW_NUSS_VBUSP_TX_PRI0_MAXLEN_REG,Transmit Priority 0 Maximum Length" hexmask.long.word 0x0 0.--13. 1. "TX_PRI0_MAXLEN,Transmit Priority 0 Maximum Length" line.long 0x4 "CPSW_NUSS_VBUSP_TX_PRI1_MAXLEN_REG,Transmit Priority 1 Maximum Length" hexmask.long.word 0x4 0.--13. 1. "TX_PRI1_MAXLEN,Transmit Priority 1 Maximum Length" line.long 0x8 "CPSW_NUSS_VBUSP_TX_PRI2_MAXLEN_REG,Transmit Priority 2 Maximum Length" hexmask.long.word 0x8 0.--13. 1. "TX_PRI2_MAXLEN,Transmit Priority 2 Maximum Length" line.long 0xC "CPSW_NUSS_VBUSP_TX_PRI3_MAXLEN_REG,Transmit Priority 3 Maximum Length" hexmask.long.word 0xC 0.--13. 1. "TX_PRI3_MAXLEN,Transmit Priority 3 Maximum Length" line.long 0x10 "CPSW_NUSS_VBUSP_TX_PRI4_MAXLEN_REG,Transmit Priority 4 Maximum Length" hexmask.long.word 0x10 0.--13. 1. "TX_PRI4_MAXLEN,Transmit Priority 4 Maximum Length" line.long 0x14 "CPSW_NUSS_VBUSP_TX_PRI5_MAXLEN_REG,Transmit Priority 5 Maximum Length" hexmask.long.word 0x14 0.--13. 1. "TX_PRI5_MAXLEN,Transmit Priority 5 Maximum Length" line.long 0x18 "CPSW_NUSS_VBUSP_TX_PRI6_MAXLEN_REG,Transmit Priority 6 Maximum Length" hexmask.long.word 0x18 0.--13. 1. "TX_PRI6_MAXLEN,Transmit Priority 6 Maximum Length" line.long 0x1C "CPSW_NUSS_VBUSP_TX_PRI7_MAXLEN_REG,Transmit Priority 7 Maximum Length" hexmask.long.word 0x1C 0.--13. 1. "TX_PRI7_MAXLEN,Transmit Priority 7 Maximum Length" tree.end tree.end tree "CSI_RX_IF0" base ad:0x0 tree "CSI_RX_IF0_CP_INTD_CFG_INTD_CFG" base ad:0x30100000 rgroup.long 0x0++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_REVISION,Revision Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTLVER,RTL revisions" newline bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision" group.long 0x10++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_eoi_reg,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector" rgroup.long 0x14++0x3 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg,Interrupt Vector Register" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR,Interrupt Vector Register" group.long 0x100++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_0,Enable Register 0" bitfld.long 0x0 4. "ENABLE_LEVEL_EN_INT_VP1_ERROVERFLOW,Enable Set for level_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x0 3. "ENABLE_LEVEL_EN_INT_VP1_ERRINLNFRM,Enable Set for level_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x0 2. "ENABLE_LEVEL_EN_INT_VP0_ERROVERFLOW,Enable Set for level_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x0 1. "ENABLE_LEVEL_EN_INT_VP0_ERRINLNFRM,Enable Set for level_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x0 0. "ENABLE_LEVEL_EN_FIFO_OVERFLOW,Enable Set for level_en_fifo_overflow" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_0,Enable Register 1" bitfld.long 0x4 4. "ENABLE_PULSE_EN_INT_VP1_ERROVERFLOW,Enable Set for pulse_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x4 3. "ENABLE_PULSE_EN_INT_VP1_ERRINLNFRM,Enable Set for pulse_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x4 2. "ENABLE_PULSE_EN_INT_VP0_ERROVERFLOW,Enable Set for pulse_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x4 1. "ENABLE_PULSE_EN_INT_VP0_ERRINLNFRM,Enable Set for pulse_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x4 0. "ENABLE_PULSE_EN_FIFO_OVERFLOW,Enable Set for pulse_en_fifo_overflow" "0,1" group.long 0x300++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_0,Enable Clear Register 0" bitfld.long 0x0 4. "ENABLE_LEVEL_EN_INT_VP1_ERROVERFLOW_CLR,Enable Clear for level_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x0 3. "ENABLE_LEVEL_EN_INT_VP1_ERRINLNFRM_CLR,Enable Clear for level_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x0 2. "ENABLE_LEVEL_EN_INT_VP0_ERROVERFLOW_CLR,Enable Clear for level_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x0 1. "ENABLE_LEVEL_EN_INT_VP0_ERRINLNFRM_CLR,Enable Clear for level_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x0 0. "ENABLE_LEVEL_EN_FIFO_OVERFLOW_CLR,Enable Clear for level_en_fifo_overflow" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_0,Enable Clear Register 1" bitfld.long 0x4 4. "ENABLE_PULSE_EN_INT_VP1_ERROVERFLOW_CLR,Enable Clear for pulse_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x4 3. "ENABLE_PULSE_EN_INT_VP1_ERRINLNFRM_CLR,Enable Clear for pulse_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x4 2. "ENABLE_PULSE_EN_INT_VP0_ERROVERFLOW_CLR,Enable Clear for pulse_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x4 1. "ENABLE_PULSE_EN_INT_VP0_ERRINLNFRM_CLR,Enable Clear for pulse_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x4 0. "ENABLE_PULSE_EN_FIFO_OVERFLOW_CLR,Enable Clear for pulse_en_fifo_overflow" "0,1" group.long 0x500++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_0,Status Register 0" bitfld.long 0x0 4. "STATUS_LEVEL_INT_VP1_ERROVERFLOW,Status write 1 to set for level_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x0 3. "STATUS_LEVEL_INT_VP1_ERRINLNFRM,Status write 1 to set for level_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x0 2. "STATUS_LEVEL_INT_VP0_ERROVERFLOW,Status write 1 to set for level_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x0 1. "STATUS_LEVEL_INT_VP0_ERRINLNFRM,Status write 1 to set for level_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x0 0. "STATUS_LEVEL_FIFO_OVERFLOW,Status write 1 to set for level_en_fifo_overflow" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_0,Status Register 1" bitfld.long 0x4 4. "STATUS_PULSE_INT_VP1_ERROVERFLOW,Status write 1 to set for pulse_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x4 3. "STATUS_PULSE_INT_VP1_ERRINLNFRM,Status write 1 to set for pulse_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x4 2. "STATUS_PULSE_INT_VP0_ERROVERFLOW,Status write 1 to set for pulse_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x4 1. "STATUS_PULSE_INT_VP0_ERRINLNFRM,Status write 1 to set for pulse_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x4 0. "STATUS_PULSE_FIFO_OVERFLOW,Status write 1 to set for pulse_en_fifo_overflow" "0,1" group.long 0x700++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_0,Status Clear Register 0" bitfld.long 0x0 4. "STATUS_LEVEL_INT_VP1_ERROVERFLOW_CLR,Status write 1 to clear for level_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x0 3. "STATUS_LEVEL_INT_VP1_ERRINLNFRM_CLR,Status write 1 to clear for level_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x0 2. "STATUS_LEVEL_INT_VP0_ERROVERFLOW_CLR,Status write 1 to clear for level_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x0 1. "STATUS_LEVEL_INT_VP0_ERRINLNFRM_CLR,Status write 1 to clear for level_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x0 0. "STATUS_LEVEL_FIFO_OVERFLOW_CLR,Status write 1 to clear for level_en_fifo_overflow" "0,1" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_0,Status Clear Register 1" bitfld.long 0x4 4. "STATUS_PULSE_INT_VP1_ERROVERFLOW_CLR,Status write 1 to clear for pulse_en_int_vp1_erroverflow" "0,1" newline bitfld.long 0x4 3. "STATUS_PULSE_INT_VP1_ERRINLNFRM_CLR,Status write 1 to clear for pulse_en_int_vp1_errInLnFrm" "0,1" newline bitfld.long 0x4 2. "STATUS_PULSE_INT_VP0_ERROVERFLOW_CLR,Status write 1 to clear for pulse_en_int_vp0_erroverflow" "0,1" newline bitfld.long 0x4 1. "STATUS_PULSE_INT_VP0_ERRINLNFRM_CLR,Status write 1 to clear for pulse_en_int_vp0_errInLnFrm" "0,1" newline bitfld.long 0x4 0. "STATUS_PULSE_FIFO_OVERFLOW_CLR,Status write 1 to clear for pulse_en_fifo_overflow" "0,1" rgroup.long 0xA80++0x7 line.long 0x0 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level,Interrupt Vector for level" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR_LEVEL,Interrupt Vector" line.long 0x4 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse,Interrupt Vector for pulse" hexmask.long 0x4 0.--31. 1. "INTR_VECTOR_PULSE,Interrupt Vector" tree.end tree "CSI_RX_IF0_ECC_AGGR_CFG" base ad:0x70E000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 7. "VP1_FIFO_RAMECC_PEND,Interrupt Pending Status for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x4 6. "VP0_FIFO_RAMECC_PEND,Interrupt Pending Status for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x4 5. "RAM_RAMECC3_PEND,Interrupt Pending Status for ram_ramecc3_pend" "0,1" newline bitfld.long 0x4 4. "RAM_RAMECC2_PEND,Interrupt Pending Status for ram_ramecc2_pend" "0,1" bitfld.long 0x4 3. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1" bitfld.long 0x4 2. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1" newline bitfld.long 0x4 1. "PSIL_FIFO_RAMECC_PEND,Interrupt Pending Status for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 7. "VP1_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x0 6. "VP0_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x0 5. "RAM_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc3_pend" "0,1" newline bitfld.long 0x0 4. "RAM_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc2_pend" "0,1" bitfld.long 0x0 3. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 2. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1" newline bitfld.long 0x0 1. "PSIL_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 7. "VP1_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x0 6. "VP0_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x0 5. "RAM_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc3_pend" "0,1" newline bitfld.long 0x0 4. "RAM_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc2_pend" "0,1" bitfld.long 0x0 3. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 2. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1" newline bitfld.long 0x0 1. "PSIL_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 7. "VP1_FIFO_RAMECC_PEND,Interrupt Pending Status for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x4 6. "VP0_FIFO_RAMECC_PEND,Interrupt Pending Status for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x4 5. "RAM_RAMECC3_PEND,Interrupt Pending Status for ram_ramecc3_pend" "0,1" newline bitfld.long 0x4 4. "RAM_RAMECC2_PEND,Interrupt Pending Status for ram_ramecc2_pend" "0,1" bitfld.long 0x4 3. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1" bitfld.long 0x4 2. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1" newline bitfld.long 0x4 1. "PSIL_FIFO_RAMECC_PEND,Interrupt Pending Status for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x4 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 7. "VP1_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x0 6. "VP0_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x0 5. "RAM_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc3_pend" "0,1" newline bitfld.long 0x0 4. "RAM_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc2_pend" "0,1" bitfld.long 0x0 3. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 2. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1" newline bitfld.long 0x0 1. "PSIL_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 7. "VP1_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp1_fifo_ramecc_pend" "0,1" bitfld.long 0x0 6. "VP0_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp0_fifo_ramecc_pend" "0,1" bitfld.long 0x0 5. "RAM_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc3_pend" "0,1" newline bitfld.long 0x0 4. "RAM_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc2_pend" "0,1" bitfld.long 0x0 3. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1" bitfld.long 0x0 2. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1" newline bitfld.long 0x0 1. "PSIL_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for psil_fifo_ramecc_pend" "0,1" bitfld.long 0x0 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "CSI_RX_IF0_RX_SHIM_VBUSP_MMR_CSI2RXIF" base ad:0x30102000 rgroup.long 0x0++0x3 line.long 0x0 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_csirx_id,nothing" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" newline bitfld.long 0x0 8.--10. "MAJREV,major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom revision" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,min revision" group.long 0x8++0xB line.long 0x0 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_vp0,Video Port 0 configuration" bitfld.long 0x0 31. "EN_CFG,Video Port enable. Disable:drops pixel data Enable: start on VS captures and sends frame data. Will force ih and iw size by zero pad or trunc. When 1 prevents writing rest of fields in this register." "0,1" hexmask.long.word 0x0 16.--28. 1. "IH_CFG,(U13) input height in units of lines. Only writable when vp0_en_cfg=0. writes blockes when vp0_en_cfg=1" hexmask.long.word 0x0 0.--12. 1. "IW_CFG,(U13) input width in units of RAW data samples. Max usable value determined by populated line buffer RAM size. Only writable when vp0_en_cfg=0. writes blockes when vp0_en_cfg=1. You should read this value first and if set to 0 then you should.." line.long 0x4 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_vp1,Video Port 1 configuration" bitfld.long 0x4 31. "EN_CFG,Video Port enable. Disable:drops pixel data Enable: start on VS captures and sends frame data. Will force ih and iw size by zero pad or trunc. When 1 prevents writing rest of fields in this register." "0,1" hexmask.long.word 0x4 16.--28. 1. "IH_CFG,(U13) input height in units of lines. Only writable when vp0_en_cfg=0. writes blovkes when vp1_en_cfg=1" hexmask.long.word 0x4 0.--12. 1. "IW_CFG,(U13) input width in units of RAW data samples. Max usable value determined by populated line buffer RAM size. Only writable when vp1_en_cfg=0. writes blockes when vp1_en_cfg=1. You should read this value first and if set to 0 then you should.." line.long 0x8 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_cntl,control register for csi rx wrapper" rbitfld.long 0x8 11. "STREAM3_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" rbitfld.long 0x8 10. "STREAM2_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" rbitfld.long 0x8 9. "STREAM1_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" rbitfld.long 0x8 8. "STREAM0_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1" newline bitfld.long 0x8 0. "PIXEL_RESET,reset for the pixeal interface. 0-reset 1 not in reset. this shoud be asserted till after you program the csi controller configuration registers" "0,1" group.long 0x20++0xB line.long 0x0 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_dmaCntx,DMA Channel Context. Configuration for each of 32 possible channel contexts. Illegal to program 2 chanCntx with same extraction values." bitfld.long 0x0 31. "EN_CFG,DMA context is enabled. Will extract channel if input matches dataType and VirtualChan" "0,1" bitfld.long 0x0 29. "RSV0,reserved" "0,1" bitfld.long 0x0 26.--27. "YUV422_MODE_CFG,yuv422 mode 00:UYVY 01:VYUY 10:YUYV 11:YVYU" "0: UYVY,1: VYUY,?,?" bitfld.long 0x0 24. "DUAL_PCK_CFG,dual packed format extraction for 8 bits or less" "0,1" newline bitfld.long 0x0 20.--21. "SIZE_CFG,data size shift when unpacking 00=8 01=16 10=32 11=RSVD" "0: 8,1: 16,?,?" bitfld.long 0x0 18. "PCK12_CFG,12-bit packing enable" "0,1" hexmask.long.byte 0x0 6.--9. 1. "VIRTCH_CFG,CSI virtual channel index. Supplied by MIPI CSI protocol to DPHY. For CSIver1.3 program 2MSb==0" hexmask.long.byte 0x0 0.--5. 1. "DATTYP_CFG,CSI data type index. Supplied by MIPI CSI protocol to DPHY" line.long 0x4 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_psi_cfg0,psi configuration register0" hexmask.long.word 0x4 16.--31. 1. "DST_TAG,psi dst tag" hexmask.long.word 0x4 0.--15. 1. "SRC_TAG,psi source tag" line.long 0x8 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_psi_cfg1,psi configuration register1" hexmask.long.byte 0x8 8.--11. 1. "PS_FLAGS,ps flags" hexmask.long.byte 0x8 0.--4. 1. "PKT_TYPE,psi packet type" tree.end tree "CSI_RX_IF0_VBUS2APB_WRAP_VBUSP_APB_CSI2RX" base ad:0x30101000 rgroup.long 0x0++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_device_config,This register provides information related to the current configuration." bitfld.long 0x0 31. "STREAM3_MONITOR_PRESENT,Pixel stream 3 Monitor present 1 = implemented" "?,1: implemented" newline bitfld.long 0x0 29.--30. "STREAM3_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle. Default will be 1 pixel per clock. 00 -> 1.." "0: 1 pixel per clock,1: 2 pixels per clock,?,?" newline bitfld.long 0x0 27.--28. "STREAM3_FIFO_MODE,Stream 3 FIFO Mode." "0,1,2,3" newline bitfld.long 0x0 26. "STREAM2_MONITOR_PRESENT,Pixel stream 2 Monitor present 1 = implemented" "?,1: implemented" newline bitfld.long 0x0 24.--25. "STREAM2_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle. Default will be 1 pixel per clock. 00 -> 1.." "0: 1 pixel per clock,1: 2 pixels per clock,?,?" newline bitfld.long 0x0 22.--23. "STREAM2_FIFO_MODE,Stream 2 FIFO Mode." "0,1,2,3" newline bitfld.long 0x0 21. "STREAM1_MONITOR_PRESENT,Pixel stream 1 Monitor present 1 = implemented" "?,1: implemented" newline bitfld.long 0x0 19.--20. "STREAM1_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle. Default will be 1 pixel per clock. 00 -> 1.." "0: 1 pixel per clock,1: 2 pixels per clock,?,?" newline bitfld.long 0x0 17.--18. "STREAM1_FIFO_MODE,Stream 1 FIFO Mode." "0,1,2,3" newline bitfld.long 0x0 16. "STREAM0_MONITOR_PRESENT,Pixel stream 0 Monitor present 1 = implemented" "?,1: implemented" newline bitfld.long 0x0 14.--15. "STREAM0_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle. Default will be 1 pixel per clock. 00 -> 1.." "0: 1 pixel per clock,1: 2 pixels per clock,?,?" newline bitfld.long 0x0 12.--13. "STREAM0_FIFO_MODE,Stream 0 FIFO Mode." "0,1,2,3" newline bitfld.long 0x0 10. "ASF_CONFIG,Additional Safety Features [ASF] Configuration: 0 = None; 1 = Full ASF." "0: None,1: Full ASF" newline bitfld.long 0x0 9. "VCX_CONFIG,Extended Virtual Channel [VCX] Configuration: 0 = 4 VCs; 1 = 16 VCs" "0: 4 VCs,1: 16 VCs" newline bitfld.long 0x0 7.--8. "DATAPATH_SIZE,Internal Datapath width 00 - 32 bit 01 - 64bit 10 - 16 bit 11 - 8 Bits." "0,1,2,3" newline bitfld.long 0x0 4.--6. "NUM_STREAMS,Number of Stream interfaces [1-4]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "CDNS_PHY_PRESENT,Cadence DPDHY present 1 = Yes" "?,1: Yes" newline bitfld.long 0x0 0.--2. "MAX_LANE_NB,Max Number of Lanes [1-4]" "0,1,2,3,4,5,6,7" group.long 0x4++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_soft_reset,CSI2 Slave Controller Individual Soft Reset for Front and Protocol blocks." bitfld.long 0x0 1. "PROTOCOL,writing 1'b1 will apply a synchronous soft reset to the protocol module" "0,1" newline bitfld.long 0x0 0. "FRONT,writing 1'b1 will apply a synchronous soft reset to the Front module" "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_static_cfg,Configuration register to set the physical/logical DPHY lane mapping." bitfld.long 0x4 28.--30. "DL3_MAP,physical mapping of logical data lane 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24.--26. "DL2_MAP,physical mapping of logical data lane 2." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20.--22. "DL1_MAP,physical mapping of logical data lane 1." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "DL0_MAP,physical mapping of logical data lane 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "LANE_NB,The number of lanes" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "V2P0_SUPPORT_ENABLE,Support extended VC up to 16 virtual channels [4-bits] and RAW16/20. as per CSI2RX v2.0. Default is up to 4 virtual channels [3-bits] as per CSI2RX v1.3" "0,1" newline bitfld.long 0x4 0.--1. "SEL,selection of DPHY used as input of CSI2RX module" "0,1,2,3" group.long 0x10++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_bypass_cfg,Error detection event flag configuration." bitfld.long 0x0 2. "DATA_ID,Enables Data ID error bypass for stream outputs. When enabled Data ID errors in packets are signalled as interrupt events however the data is still passed to the pixel/packed data outputs. The system must decide to.." "0,1" newline bitfld.long 0x0 1. "ECC,Enables ECC error bypass for stream outputs. When enabled CRC errors in packets are signalled as interrupt events however the data is still passed to the pixel/packed data outputs. The system must decide to mask of use the.." "0,1" newline bitfld.long 0x0 0. "CRC,Enables CRC error bypass for stream outputs. When enabled CRC errors in packets are signalled as interrupt events however the data is still passed to the pixel/packed data outputs. The system must decide to mask of use the.." "0,1" group.long 0x18++0x17 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_monitor_irqs,Information type Interrupt status (non-error conditions)" bitfld.long 0x0 31. "STREAM3_LINE_CNT_ERROR_IRQ,Stream 3 Line count error interrupt" "0,1" newline bitfld.long 0x0 30. "STREAM3_FRAME_MISMATCH_IRQ,Stream 3 Frame mismatch error interrupt" "0,1" newline bitfld.long 0x0 29. "STREAM3_FRAME_CNT_ERROR_IRQ,Stream 3 Frame count error interrupt" "0,1" newline bitfld.long 0x0 28. "STREAM3_FCC_STOP_IRQ,Stream 3 FCC stop interrupt" "0,1" newline bitfld.long 0x0 27. "STREAM3_FCC_START_IRQ,Stream 3 FCC start interrupt" "0,1" newline bitfld.long 0x0 26. "STREAM3_FRAME_IRQ,Stream 3 Frame interrupt" "0,1" newline bitfld.long 0x0 25. "STREAM3_LB_IRQ,Stream 3 Line/byte interrupt" "0,1" newline bitfld.long 0x0 24. "STREAM3_TIMER_IRQ,Stream 3 Timer interrupt" "0,1" newline bitfld.long 0x0 23. "STREAM2_LINE_CNT_ERROR_IRQ,Stream 2 Line count error interrupt" "0,1" newline bitfld.long 0x0 22. "STREAM2_FRAME_MISMATCH_IRQ,Stream 2 Frame mismatch error interrupt" "0,1" newline bitfld.long 0x0 21. "STREAM2_FRAME_CNT_ERROR_IRQ,Stream 2 Frame count error interrupt" "0,1" newline bitfld.long 0x0 20. "STREAM2_FCC_STOP_IRQ,Stream 2 FCC stop interrupt" "0,1" newline bitfld.long 0x0 19. "STREAM2_FCC_START_IRQ,Stream 2 FCC start interrupt" "0,1" newline bitfld.long 0x0 18. "STREAM2_FRAME_IRQ,Stream 2 Frame interrupt" "0,1" newline bitfld.long 0x0 17. "STREAM2_LB_IRQ,Stream 2 Line/byte interrupt" "0,1" newline bitfld.long 0x0 16. "STREAM2_TIMER_IRQ,Stream 2 Timer interrupt" "0,1" newline bitfld.long 0x0 15. "STREAM1_LINE_CNT_ERROR_IRQ,Stream 1 Line count error interrupt" "0,1" newline bitfld.long 0x0 14. "STREAM1_FRAME_MISMATCH_IRQ,Stream 1 Frame mismatch error interrupt" "0,1" newline bitfld.long 0x0 13. "STREAM1_FRAME_CNT_ERROR_IRQ,Stream 1 Frame count error interrupt" "0,1" newline bitfld.long 0x0 12. "STREAM1_FCC_STOP_IRQ,Stream 1 FCC stop interrupt" "0,1" newline bitfld.long 0x0 11. "STREAM1_FCC_START_IRQ,Stream 1 FCC start interrupt" "0,1" newline bitfld.long 0x0 10. "STREAM1_FRAME_IRQ,Stream 1 Frame interrupt" "0,1" newline bitfld.long 0x0 9. "STREAM1_LB_IRQ,Stream 1 Line/byte interrupt" "0,1" newline bitfld.long 0x0 8. "STREAM1_TIMER_IRQ,Stream 1 Timer interrupt" "0,1" newline bitfld.long 0x0 7. "STREAM0_LINE_CNT_ERROR_IRQ,Stream 0 Line count error interrupt" "0,1" newline bitfld.long 0x0 6. "STREAM0_FRAME_MISMATCH_IRQ,Stream 0 Frame mismatch error interrupt" "0,1" newline bitfld.long 0x0 5. "STREAM0_FRAME_CNT_ERROR_IRQ,Stream 0 Frame count error interrupt" "0,1" newline bitfld.long 0x0 4. "STREAM0_FCC_STOP_IRQ,Stream 0 FCC stop interrupt" "0,1" newline bitfld.long 0x0 3. "STREAM0_FCC_START_IRQ,Stream 0 FCC start interrupt" "0,1" newline bitfld.long 0x0 2. "STREAM0_FRAME_IRQ,Stream 0 Frame interrupt" "0,1" newline bitfld.long 0x0 1. "STREAM0_LB_IRQ,Stream 0 Line/byte interrupt" "0,1" newline bitfld.long 0x0 0. "STREAM0_TIMER_IRQ,Stream 0 Timer interrupt" "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_monitor_irqs_mask_cfg,Monitor interrupt mask. Bit addressable mask register in order to independently enable" bitfld.long 0x4 31. "STREAM3_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 3 Line count error." "0,1" newline bitfld.long 0x4 30. "STREAM3_FRAME_MISMATCH_IRQM,Interrupt mask for stream 3 Frame mismatch error." "0,1" newline bitfld.long 0x4 29. "STREAM3_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 3 Frame count error." "0,1" newline bitfld.long 0x4 28. "STREAM3_FCC_STOP_IRQM,Interrupt mask for stream 3 FCC stop." "0,1" newline bitfld.long 0x4 27. "STREAM3_FCC_START_IRQM,Interrupt mask for stream 3 FCC start." "0,1" newline bitfld.long 0x4 26. "STREAM3_FRAME_IRQM,Interrupt mask for stream 3 Frame." "0,1" newline bitfld.long 0x4 25. "STREAM3_LB_IRQM,Interrupt mask for stream 3 Line/byte." "0,1" newline bitfld.long 0x4 24. "STREAM3_TIMER_IRQM,Interrupt mask stream 3 Timer" "0,1" newline bitfld.long 0x4 23. "STREAM2_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 2 Line count error." "0,1" newline bitfld.long 0x4 22. "STREAM2_FRAME_MISMATCH_IRQM,Interrupt mask for stream 2 Frame mismatch error." "0,1" newline bitfld.long 0x4 21. "STREAM2_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 2 Frame count error." "0,1" newline bitfld.long 0x4 20. "STREAM2_FCC_STOP_IRQM,Interrupt mask for stream 2 FCC stop." "0,1" newline bitfld.long 0x4 19. "STREAM2_FCC_START_IRQM,Interrupt mask for stream 2 FCC start." "0,1" newline bitfld.long 0x4 18. "STREAM2_FRAME_IRQM,Interrupt mask for stream 2 Frame." "0,1" newline bitfld.long 0x4 17. "STREAM2_LB_IRQM,Interrupt mask for stream 2 Line/byte." "0,1" newline bitfld.long 0x4 16. "STREAM2_TIMER_IRQM,Interrupt mask stream 2 Timer" "0,1" newline bitfld.long 0x4 15. "STREAM1_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 1 Line count error." "0,1" newline bitfld.long 0x4 14. "STREAM1_FRAME_MISMATCH_IRQM,Interrupt mask for stream 1 Frame mismatch error." "0,1" newline bitfld.long 0x4 13. "STREAM1_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 1 Frame count error." "0,1" newline bitfld.long 0x4 12. "STREAM1_FCC_STOP_IRQM,Interrupt mask for stream 1 FCC stop." "0,1" newline bitfld.long 0x4 11. "STREAM1_FCC_START_IRQM,Interrupt mask for stream 1 FCC start." "0,1" newline bitfld.long 0x4 10. "STREAM1_FRAME_IRQM,Interrupt mask for stream 1 Frame." "0,1" newline bitfld.long 0x4 9. "STREAM1_LB_IRQM,Interrupt mask for stream 1 Line/byte." "0,1" newline bitfld.long 0x4 8. "STREAM1_TIMER_IRQM,Interrupt mask stream 1 Timer" "0,1" newline bitfld.long 0x4 7. "STREAM0_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 0 Line count error." "0,1" newline bitfld.long 0x4 6. "STREAM0_FRAME_MISMATCH_IRQM,Interrupt mask for stream 0 Frame mismatch error." "0,1" newline bitfld.long 0x4 5. "STREAM0_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 0 Frame count error." "0,1" newline bitfld.long 0x4 4. "STREAM0_FCC_STOP_IRQM,Interrupt mask for stream 0 FCC stop." "0,1" newline bitfld.long 0x4 3. "STREAM0_FCC_START_IRQM,Interrupt mask for stream 0 FCC start." "0,1" newline bitfld.long 0x4 2. "STREAM0_FRAME_IRQM,Interrupt mask for stream 0 Frame." "0,1" newline bitfld.long 0x4 1. "STREAM0_LB_IRQM,Interrupt mask for stream 0 Line/byte." "0,1" newline bitfld.long 0x4 0. "STREAM0_TIMER_IRQM,Interrupt mask stream 0 Timer" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_info_irqs,Information type Interrupt status (non-error conditions)" bitfld.long 0x8 14. "STREAM3_ABORT_IRQ,Stream 3 Abort process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 13. "STREAM3_STOP_IRQ,Stream 3 Stop process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 12. "STREAM2_ABORT_IRQ,Stream 2 Abort process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 11. "STREAM2_STOP_IRQ,Stream 2 Stop process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 10. "STREAM1_ABORT_IRQ,Stream 1 Abort process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 9. "STREAM1_STOP_IRQ,Stream 1 Stop process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 8. "STREAM0_ABORT_IRQ,Stream 0 Abort process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 7. "STREAM0_STOP_IRQ,Stream 0 Stop process complete. Apply a Soft reset before re-enabling the stream." "0,1" newline bitfld.long 0x8 6. "SP_GENERIC_RCVD_IRQ,A generic short packet has been received." "0,1" newline bitfld.long 0x8 5. "DESKEW_ENTRY_IRQ,Either clock or any datalane has entered deskew" "0,1" newline bitfld.long 0x8 4. "ECC_SPARES_NONZERO_IRQ,Bits 7:6 of the ECC byte are non-zero. Indicates non compliance with the MIPI specification although the core will continue to operate as normal." "0,1" newline bitfld.long 0x8 3. "WAKEUP_IRQ,Wake-up interrupt." "0,1" newline bitfld.long 0x8 2. "SLEEP_IRQ,Sleep interrupt." "0,1" newline bitfld.long 0x8 1. "LP_RCVD_IRQ,Long Packet received by the protocol module" "0,1" newline bitfld.long 0x8 0. "SP_RCVD_IRQ,Short Packet received by the protocol module" "0,1" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_info_irqs_mask_cfg,Information interrupt mask. Bit addressable mask register in order to independently enable" bitfld.long 0xC 14. "STREAM3_ABORT_IRQM,Interrupt mask for stream 3 Abort process." "0,1" newline bitfld.long 0xC 13. "STREAM3_STOP_IRQM,Interrupt mask for Stream 3 Stop process complete." "0,1" newline bitfld.long 0xC 12. "STREAM2_ABORT_IRQM,Interrupt mask for stream 2 Abort process." "0,1" newline bitfld.long 0xC 11. "STREAM2_STOP_IRQM,Interrupt mask for Stream 2 Stop process complete." "0,1" newline bitfld.long 0xC 10. "STREAM1_ABORT_IRQM,Interrupt mask for stream 1 Abort process." "0,1" newline bitfld.long 0xC 9. "STREAM1_STOP_IRQM,Interrupt mask for Stream 1 Stop process complete." "0,1" newline bitfld.long 0xC 8. "STREAM0_ABORT_IRQM,Interrupt mask for stream 0 Abort process." "0,1" newline bitfld.long 0xC 7. "STREAM0_STOP_IRQM,Interrupt mask for Stream 0 Stop process complete." "0,1" newline bitfld.long 0xC 6. "SP_GENERIC_RCVD_IRQM,Interrupt mask for Generic Short Packet received" "0,1" newline bitfld.long 0xC 5. "DESKEW_ENTRY_IRQM,Interrupt mask for Deskew entry check" "0,1" newline bitfld.long 0xC 4. "ECC_SPARES_NONZERO_IRQM,Interrupt mask for ECC spares check" "0,1" newline bitfld.long 0xC 3. "WAKEUP_IRQM,Interrupt mask for Wake-up interrupt." "0,1" newline bitfld.long 0xC 2. "SLEEP_IRQM,Interrupt mask for Sleep interrupt." "0,1" newline bitfld.long 0xC 1. "LP_RCVD_IRQM,Interrupt mask for Long Packet received flag" "0,1" newline bitfld.long 0xC 0. "SP_RCVD_IRQM,Interrupt mask for Short Packet received" "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_irqs,Datapath error interrupt status." bitfld.long 0x10 19. "STREAM3_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[19] -> Stream 3 overflow" "0,1" newline bitfld.long 0x10 18. "STREAM2_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[18] -> Stream 2 overflow" "0,1" newline bitfld.long 0x10 17. "STREAM1_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[17] -> Stream 1 overflow" "0,1" newline bitfld.long 0x10 16. "STREAM0_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[16] -> Stream 0 overflow" "0,1" newline bitfld.long 0x10 12. "FRONT_TRUNC_HDR_IRQ,A truncated header [short or Long] has been received" "0,1" newline bitfld.long 0x10 11. "PROT_TRUNCATED_PACKET_IRQ,A truncated Long packet has been received. Too few/many bytes" "0,1" newline bitfld.long 0x10 10. "FRONT_LP_NO_PAYLOAD_IRQ,A truncated Long packet has been received. No payload" "0,1" newline bitfld.long 0x10 9. "SP_INVALID_RCVD_IRQ,A reserved or invalid short packet has been received" "0,1" newline bitfld.long 0x10 8. "INVALID_ACCESS_IRQ,Invalid access to the configuration register space." "0,1" newline bitfld.long 0x10 7. "DATA_ID_IRQ,Data ID error has been detected in the header packet" "0,1" newline bitfld.long 0x10 6. "HEADER_CORRECTED_ECC_IRQ,ECC error has been detected and corrected." "0,1" newline bitfld.long 0x10 5. "HEADER_ECC_IRQ,Unrecoverable ECC error has been detected." "0,1" newline bitfld.long 0x10 4. "PAYLOAD_CRC_IRQ,CRC error has been detected." "0,1" newline bitfld.long 0x10 0. "FRONT_FIFO_OVERFLOW_IRQ,Overflow detected in resynchronization FIFO between DPHY Lane Management and Protocol blocks. This will occur if sys_clk is not fast enough and should be increased since the byte clock frequency is fixed" "0,1" line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_irqs_mask_cfg,Datapath error interrupt enable Bits. This register is used to independently enable each event" bitfld.long 0x14 19. "STREAM3_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[19] -> Stream 3 overflow" "0,1" newline bitfld.long 0x14 18. "STREAM2_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[18] -> Stream 2 overflow" "0,1" newline bitfld.long 0x14 17. "STREAM1_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[17] -> Stream 1 overflow" "0,1" newline bitfld.long 0x14 16. "STREAM0_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[16] -> Stream 0 overflow" "0,1" newline bitfld.long 0x14 12. "FRONT_TRUNC_HDR_IRQM,Interrupt enable bit for truncated hdr." "0,1" newline bitfld.long 0x14 11. "PROT_TRUNCATED_PACKET_IRQM,Interrupt enable bit for long packet payload with too many/few bytes" "0,1" newline bitfld.long 0x14 10. "FRONT_LP_NO_PAYLOAD_IRQM,Interrupt enable bit for long packet header received with no payload" "0,1" newline bitfld.long 0x14 9. "SP_INVALID_RCVD_IRQM,Interrupt enable bit for invalid short packet" "0,1" newline bitfld.long 0x14 8. "INVALID_ACCESS_IRQM,Interrupt enable bit for error_irqs_invalid_access." "0,1" newline bitfld.long 0x14 7. "DATA_ID_IRQM,Interrupt enable bit for error_irqs_data_id" "0,1" newline bitfld.long 0x14 6. "HEADER_CORRECTED_ECC_IRQM,Interrupt enable bit for error_irqs_header_corrected_ecc" "0,1" newline bitfld.long 0x14 5. "HEADER_ECC_IRQM,Interrupt enable bit for error_irqs_header_ecc" "0,1" newline bitfld.long 0x14 4. "PAYLOAD_CRC_IRQM,Interrupt enable bit for error_irqs_payload_crc" "0,1" newline bitfld.long 0x14 0. "FRONT_FIFO_OVERFLOW_IRQM,Interrupt enable bit for error_irqs_front_fifo_overflow" "0,1" group.long 0x40++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_lane_control,DPHY lane control for data and clock lanes enables and resets" bitfld.long 0x0 16. "CL_RESET,DPHY Clock lane Reset" "0,1" newline bitfld.long 0x0 15. "DL3_RESET,DPHY data lane 3 Reset" "0,1" newline bitfld.long 0x0 14. "DL2_RESET,DPHY data lane 2 Reset" "0,1" newline bitfld.long 0x0 13. "DL1_RESET,DPHY data lane 1 Reset" "0,1" newline bitfld.long 0x0 12. "DL0_RESET,DPHY data lane 0 Reset" "0,1" newline bitfld.long 0x0 4. "CL_ENABLE,DPHY Clock lane Enable" "0,1" newline bitfld.long 0x0 3. "DL3_ENABLE,DPHY data lane 3 Enable" "0,1" newline bitfld.long 0x0 2. "DL2_ENABLE,DPHY data lane 2 Enable" "0,1" newline bitfld.long 0x0 1. "DL1_ENABLE,DPHY data lane 1 Enable" "0,1" newline bitfld.long 0x0 0. "DL0_ENABLE,DPHY data lane 0 Enable" "0,1" rgroup.long 0x48++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_status,DPHY Clock and Data Lane mode status" bitfld.long 0x0 22. "DL3_RXULPSESC,DPHY Data lane 3 ULPS Esc" "0,1" newline bitfld.long 0x0 21. "DL3_ULPSACTIVENOT,DPHY Data lane 3 ULPSActiveNot" "0,1" newline bitfld.long 0x0 20. "DL3_STOPSTATE,DPHY Data lane 3 Stop State" "0,1" newline bitfld.long 0x0 18. "DL2_RXULPSESC,DPHY Data lane 2 ULPS Esc" "0,1" newline bitfld.long 0x0 17. "DL2_ULPSACTIVENOT,DPHY Data lane 2 ULPSActiveNot" "0,1" newline bitfld.long 0x0 16. "DL2_STOPSTATE,DPHY Data lane 2 Stop State" "0,1" newline bitfld.long 0x0 14. "DL1_RXULPSESC,DPHY Data lane 1 ULPS Esc" "0,1" newline bitfld.long 0x0 13. "DL1_ULPSACTIVENOT,DPHY Data lane 1 ULPSActiveNot" "0,1" newline bitfld.long 0x0 12. "DL1_STOPSTATE,DPHY Data lane 1 Stop State" "0,1" newline bitfld.long 0x0 10. "DL0_RXULPSESC,DPHY Data lane 0 ULPS Esc" "0,1" newline bitfld.long 0x0 9. "DL0_ULPSACTIVENOT,DPHY Data lane 0 ULPSActiveNot" "0,1" newline bitfld.long 0x0 8. "DL0_STOPSTATE,DPHY Data lane 0 Stop State" "0,1" newline bitfld.long 0x0 2. "CL_RXULPSCLKNOT,DPHY Clock lane RxULPSClkNot" "0,1" newline bitfld.long 0x0 1. "CL_ULPSACTIVENOT,DPHY Clock lane ULPSActiveNot" "0,1" newline bitfld.long 0x0 0. "CL_STOPSTATE,DPHY Clock lane Stop State" "0,1" group.long 0x4C++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_err_status_irq,DPHY error interrupt status" bitfld.long 0x0 20. "DL3_ERRSOTHS_IRQ,DPHY Data lane 3 ErrSotHS" "0,1" newline bitfld.long 0x0 16. "DL2_ERRSOTHS_IRQ,DPHY Data lane 2 ErrSotHS" "0,1" newline bitfld.long 0x0 12. "DL1_ERRSOTHS_IRQ,DPHY Data lane 1 ErrSotHS" "0,1" newline bitfld.long 0x0 8. "DL0_ERRSOTHS_IRQ,DPHY Data lane 0 ErrSotHS" "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_err_irq_mask_cfg,DPHY error interrupt status" bitfld.long 0x4 20. "DL3_ERRSOTHS_IRQM,DPHY Data lane 3 ErrSotHS mask" "0,1" newline bitfld.long 0x4 16. "DL2_ERRSOTHS_IRQM,DPHY Data lane 2 ErrSotHS mask" "0,1" newline bitfld.long 0x4 12. "DL1_ERRSOTHS_IRQM,DPHY Data lane 1 ErrSotHS mask" "0,1" newline bitfld.long 0x4 8. "DL0_ERRSOTHS_IRQM,DPHY Data lane 0 ErrSotHS mask" "0,1" rgroup.long 0x60++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_integration_debug,Used to observe the current data field. extracted by the protocol block from the last" hexmask.long.byte 0x0 28.--31. 1. "PROT_FSM_STATE,csi2rx_fsm_state 0x1: WAIT_FOR_PACKET 0x2: PAYLOAD_DATA 0x4: PACKET_FOOTER_CHECK" newline hexmask.long.byte 0x0 22.--25. 1. "PROT_VC,Protocol Virtual Channel" newline hexmask.long.byte 0x0 16.--21. 1. "PROT_DT,Protocol Datatype" newline hexmask.long.word 0x0 0.--15. 1. "PROT_WORD_COUNT,Protocol Word Count [Data Field]" rgroup.long 0x74++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_debug,Error condition debug. After an error is detected by the CSI2RX. this register indicates which virtual channel." hexmask.long.word 0x0 16.--31. 1. "DATA_FIELD,Indicates the Data Field for an invalid CRC/ECC/Data ID" newline hexmask.long.byte 0x0 6.--9. 1. "VC,Indicates the Virtual Channel for a invalid CRC/ECC/Data ID" newline hexmask.long.byte 0x0 0.--5. 1. "DT,Indicates the Data Type for a invalid CRC/ECC/Data ID" group.long 0x80++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_test_generic,Generic test control and status register that controls and reads primary I/O." hexmask.long.word 0x0 16.--31. 1. "STATUS,Test status - Directly reflects after resynchronisation into the pclk domain the state of 'test_generic_status' primary inputs." newline hexmask.long.word 0x0 0.--15. 1. "CTRL,Test control - Directly controls primary outputs 'test_generic_ctrl'" group.long 0x100++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_ctrl,CSI2RX Stream Data output datapath control." bitfld.long 0x0 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately. This may corrupt the output protocol. stream_abort_irq is generated on completion of the abort operation." "0,1" newline bitfld.long 0x0 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame. If the command is issued during frame blanking then the datapath will immediately stop streaming.." "0,1" newline bitfld.long 0x0 0. "START,Writing 1 in this register enables the corresponding datapath output. It will start streaming data at the start of the next frame that complies with the output configuration. stream_status[31] running indicates when data.." "0,1" rgroup.long 0x104++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_status,CSI2 Slave Controller Status. Contains useful debug information such as" bitfld.long 0x0 31. "RUNNING,The Stream is enabled" "0,1" newline bitfld.long 0x0 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "STREAM_FSM,Output to Stream FSM states: 0x0: STREAM_IDLE 0x1: STREAM_WAIT_CTRL_DATA // Expecting control data next 0x2: STREAM_CTRL // Check contents of Ctrl packet and extract header.." newline bitfld.long 0x0 0.--1. "PROTOCOL_FSM,Input to Stream FSM states: 0x0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL 0x3: PROT_DATA" "0: PROT_IDLE,1: PROT_WAIT_CTRL,2: PROT_CTRL,3: PROT_DATA" group.long 0x108++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration." hexmask.long.word 0x0 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] ->.." newline bitfld.long 0x0 15. "ENABLE_DT1,Enable processing of dt1" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DATATYPE_SELECT1,Second data type format that this stream will process" newline bitfld.long 0x0 7. "ENABLE_DT0,Enable processing of dt0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "DATATYPE_SELECT0,First data type format that this stream will process" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration." hexmask.long.word 0x4 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled. This setting is only used when fifo_mode is set for Large Buffer operation" newline bitfld.long 0x4 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type. 0 - No bypass 1 - unpack as RAW6 2 - unpack as RAW7 3 - unpack as RAW8 4 - unpack as RAW10 5 - unpack as.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates. Refer to Use Case descriptions for further guidance on FIFO sizing and.." "0: Full Line Buffer,1: Large Buffer [Fill Level Controlled],?,?" newline bitfld.long 0x4 4.--5. "NUM_PIXELS,Number of pixels to output from the stream. Valid values are 1 2 4 and 8. The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be.." "0: 1 pixel per clock,1: 2 pixels per clock,?,?" newline bitfld.long 0x4 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output. By default LS and LE short packets are not required and HYSC_VALID will be generated from the start and end of payload data." "0,1" newline bitfld.long 0x4 0. "INTERFACE_MODE,Select the output configuration. Pixel = 0 [default] Packed = 1" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_ctrl,Stream Monitor configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low. 0x0000 means truncated.." newline bitfld.long 0x8 15. "FRAME_MON_EN,Enables monitor. This bit must only be set high after the frame_mon_vc and frame_length have been set." "0,1" newline hexmask.long.byte 0x8 11.--14. 1. "FRAME_MON_VC,Indicates virtual channel for monitor. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low." newline bitfld.long 0x8 10. "TIMER_EOF,Select the starting point of the timer: 0x0: Start of Frame event on selected virtual channel 0x1: End of Frame event on selected virtual channel. This value must not change while timer_en is enabled" "0: Start of Frame event on selected virtual channel,1: End of Frame event on selected virtual channel" newline bitfld.long 0x8 9. "TIMER_EN,Enables timer based interrupt. This bit must only be set high after the timer_eof and timer_vc have been set." "0,1" newline hexmask.long.byte 0x8 5.--8. 1. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt. This value must not change while timer_en is enabled." newline bitfld.long 0x8 4. "LB_EN,Enables line/byte counter. This bit must only be set high after the lb_vc line_count and byte_count have been set." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt. This value must not change while lb_en is enabled" rgroup.long 0x114++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_frame,Stream Monitor Frame." hexmask.long.word 0x0 16.--31. 1. "PACKET_SIZE,Size of the current payload" newline hexmask.long.word 0x0 0.--15. 1. "NB,Number of the last frame processed." group.long 0x118++0x13 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_lb,Stream Monitor Line." hexmask.long.word 0x0 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt. [First line of a Frame is line number 0]" newline hexmask.long.word 0x0 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt. [First byte of a line is byte number 0]" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_timer,Stream Timer." hexmask.long 0x4 0.--24. 1. "COUNT,Number of clock cycles" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fcc_cfg,Stream Frame Capture Control configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface. [0x0000 will be continuous frames.]" newline hexmask.long.word 0x8 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface. [0x0000 will be the current frame.]" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fcc_ctrl,Stream Frame Capture Counter control." hexmask.long.word 0xC 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed" newline hexmask.long.byte 0xC 1.--4. 1. "FCC_VC,Indicates which VC should be used to generate FCC interrupts. This value must not change while fcc_en is enabled" newline bitfld.long 0xC 0. "FCC_EN,Frame Capture Counter enable." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fifo_fill_lvl,Stream FIFO fill level monitor. This can operate in 2 modes:" bitfld.long 0x10 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0: Fill level detection disabled,1: Mode 1,?,?" newline hexmask.long.word 0x10 0.--9. 1. "COUNT,Peak fill level of FIFO." group.long 0x200++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_ctrl,CSI2RX Stream Data output datapath control." bitfld.long 0x0 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately. This may corrupt the output protocol. stream_abort_irq is generated on completion of the abort operation." "0,1" newline bitfld.long 0x0 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame. If the command is issued during frame blanking then the datapath will immediately stop streaming.." "0,1" newline bitfld.long 0x0 0. "START,Writing 1 in this register enables the corresponding datapath output. It will start streaming data at the start of the next frame that complies with the output configuration. stream_status[31] running indicates when data.." "0,1" rgroup.long 0x204++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_status,CSI2 Slave Controller Status. Contains useful debug information such as" bitfld.long 0x0 31. "RUNNING,The Stream is enabled" "0,1" newline bitfld.long 0x0 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "STREAM_FSM,Output to Stream FSM states: 0x0: STREAM_IDLE 0x1: STREAM_WAIT_CTRL_DATA // Expecting control data next 0x2: STREAM_CTRL // Check contents of Ctrl packet and extract header.." newline bitfld.long 0x0 0.--1. "PROTOCOL_FSM,Input to Stream FSM states: 0x0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL 0x3: PROT_DATA" "0: PROT_IDLE,1: PROT_WAIT_CTRL,2: PROT_CTRL,3: PROT_DATA" group.long 0x208++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration." hexmask.long.word 0x0 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] ->.." newline bitfld.long 0x0 15. "ENABLE_DT1,Enable processing of dt1" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DATATYPE_SELECT1,Second data type format that this stream will process" newline bitfld.long 0x0 7. "ENABLE_DT0,Enable processing of dt0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "DATATYPE_SELECT0,First data type format that this stream will process" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration." hexmask.long.word 0x4 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled. This setting is only used when fifo_mode is set for Large Buffer operation" newline bitfld.long 0x4 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type. 0 - No bypass 1 - unpack as RAW6 2 - unpack as RAW7 3 - unpack as RAW8 4 - unpack as RAW10 5 - unpack as.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates. Refer to Use Case descriptions for further guidance on FIFO sizing and.." "0: Full Line Buffer,1: Large Buffer [Fill Level Controlled],?,?" newline bitfld.long 0x4 4.--5. "NUM_PIXELS,Number of pixels to output from the stream. Valid values are 1 2 4 and 8. The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be.." "0: 1 pixel per clock,1: 2 pixels per clock,?,?" newline bitfld.long 0x4 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output. By default LS and LE short packets are not required and HYSC_VALID will be generated from the start and end of payload data." "0,1" newline bitfld.long 0x4 0. "INTERFACE_MODE,Select the output configuration. Pixel = 0 [default] Packed = 1" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_ctrl,Stream Monitor configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low. 0x0000 means truncated.." newline bitfld.long 0x8 15. "FRAME_MON_EN,Enables monitor. This bit must only be set high after the frame_mon_vc and frame_length have been set." "0,1" newline hexmask.long.byte 0x8 11.--14. 1. "FRAME_MON_VC,Indicates virtual channel for monitor. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low." newline bitfld.long 0x8 10. "TIMER_EOF,Select the starting point of the timer: 0x0: Start of Frame event on selected virtual channel 0x1: End of Frame event on selected virtual channel. This value must not change while timer_en is enabled" "0: Start of Frame event on selected virtual channel,1: End of Frame event on selected virtual channel" newline bitfld.long 0x8 9. "TIMER_EN,Enables timer based interrupt. This bit must only be set high after the timer_eof and timer_vc have been set." "0,1" newline hexmask.long.byte 0x8 5.--8. 1. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt. This value must not change while timer_en is enabled." newline bitfld.long 0x8 4. "LB_EN,Enables line/byte counter. This bit must only be set high after the lb_vc line_count and byte_count have been set." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt. This value must not change while lb_en is enabled" rgroup.long 0x214++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_frame,Stream Monitor Frame." hexmask.long.word 0x0 16.--31. 1. "PACKET_SIZE,Size of the current payload" newline hexmask.long.word 0x0 0.--15. 1. "NB,Number of the last frame processed." group.long 0x218++0x13 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_lb,Stream Monitor Line." hexmask.long.word 0x0 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt. [First line of a Frame is line number 0]" newline hexmask.long.word 0x0 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt. [First byte of a line is byte number 0]" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_timer,Stream Timer." hexmask.long 0x4 0.--24. 1. "COUNT,Number of clock cycles" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fcc_cfg,Stream Frame Capture Control configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface. [0x0000 will be continuous frames.]" newline hexmask.long.word 0x8 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface. [0x0000 will be the current frame.]" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fcc_ctrl,Stream Frame Capture Counter control." hexmask.long.word 0xC 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed" newline hexmask.long.byte 0xC 1.--4. 1. "FCC_VC,Indicates which VC should be used to generate FCC interrupts. This value must not change while fcc_en is enabled" newline bitfld.long 0xC 0. "FCC_EN,Frame Capture Counter enable." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fifo_fill_lvl,Stream FIFO fill level monitor. This can operate in 2 modes:" bitfld.long 0x10 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0: Fill level detection disabled,1: Mode 1,?,?" newline hexmask.long.word 0x10 0.--9. 1. "COUNT,Peak fill level of FIFO." group.long 0x300++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_ctrl,CSI2RX Stream Data output datapath control." bitfld.long 0x0 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately. This may corrupt the output protocol. stream_abort_irq is generated on completion of the abort operation." "0,1" newline bitfld.long 0x0 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame. If the command is issued during frame blanking then the datapath will immediately stop streaming.." "0,1" newline bitfld.long 0x0 0. "START,Writing 1 in this register enables the corresponding datapath output. It will start streaming data at the start of the next frame that complies with the output configuration. stream_status[31] running indicates when data.." "0,1" rgroup.long 0x304++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_status,CSI2 Slave Controller Status. Contains useful debug information such as" bitfld.long 0x0 31. "RUNNING,The Stream is enabled" "0,1" newline bitfld.long 0x0 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "STREAM_FSM,Output to Stream FSM states: 0x0: STREAM_IDLE 0x1: STREAM_WAIT_CTRL_DATA // Expecting control data next 0x2: STREAM_CTRL // Check contents of Ctrl packet and extract header.." newline bitfld.long 0x0 0.--1. "PROTOCOL_FSM,Input to Stream FSM states: 0x0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL 0x3: PROT_DATA" "0: PROT_IDLE,1: PROT_WAIT_CTRL,2: PROT_CTRL,3: PROT_DATA" group.long 0x308++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration." hexmask.long.word 0x0 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] ->.." newline bitfld.long 0x0 15. "ENABLE_DT1,Enable processing of dt1" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DATATYPE_SELECT1,Second data type format that this stream will process" newline bitfld.long 0x0 7. "ENABLE_DT0,Enable processing of dt0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "DATATYPE_SELECT0,First data type format that this stream will process" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration." hexmask.long.word 0x4 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled. This setting is only used when fifo_mode is set for Large Buffer operation" newline bitfld.long 0x4 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type. 0 - No bypass 1 - unpack as RAW6 2 - unpack as RAW7 3 - unpack as RAW8 4 - unpack as RAW10 5 - unpack as.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates. Refer to Use Case descriptions for further guidance on FIFO sizing and.." "0: Full Line Buffer,1: Large Buffer [Fill Level Controlled],?,?" newline bitfld.long 0x4 4.--5. "NUM_PIXELS,Number of pixels to output from the stream. Valid values are 1 2 4 and 8. The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be.." "0: 1 pixel per clock,1: 2 pixels per clock,?,?" newline bitfld.long 0x4 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output. By default LS and LE short packets are not required and HYSC_VALID will be generated from the start and end of payload data." "0,1" newline bitfld.long 0x4 0. "INTERFACE_MODE,Select the output configuration. Pixel = 0 [default] Packed = 1" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_ctrl,Stream Monitor configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low. 0x0000 means truncated.." newline bitfld.long 0x8 15. "FRAME_MON_EN,Enables monitor. This bit must only be set high after the frame_mon_vc and frame_length have been set." "0,1" newline hexmask.long.byte 0x8 11.--14. 1. "FRAME_MON_VC,Indicates virtual channel for monitor. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low." newline bitfld.long 0x8 10. "TIMER_EOF,Select the starting point of the timer: 0x0: Start of Frame event on selected virtual channel 0x1: End of Frame event on selected virtual channel. This value must not change while timer_en is enabled" "0: Start of Frame event on selected virtual channel,1: End of Frame event on selected virtual channel" newline bitfld.long 0x8 9. "TIMER_EN,Enables timer based interrupt. This bit must only be set high after the timer_eof and timer_vc have been set." "0,1" newline hexmask.long.byte 0x8 5.--8. 1. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt. This value must not change while timer_en is enabled." newline bitfld.long 0x8 4. "LB_EN,Enables line/byte counter. This bit must only be set high after the lb_vc line_count and byte_count have been set." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt. This value must not change while lb_en is enabled" rgroup.long 0x314++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_frame,Stream Monitor Frame." hexmask.long.word 0x0 16.--31. 1. "PACKET_SIZE,Size of the current payload" newline hexmask.long.word 0x0 0.--15. 1. "NB,Number of the last frame processed." group.long 0x318++0x13 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_lb,Stream Monitor Line." hexmask.long.word 0x0 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt. [First line of a Frame is line number 0]" newline hexmask.long.word 0x0 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt. [First byte of a line is byte number 0]" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_timer,Stream Timer." hexmask.long 0x4 0.--24. 1. "COUNT,Number of clock cycles" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fcc_cfg,Stream Frame Capture Control configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface. [0x0000 will be continuous frames.]" newline hexmask.long.word 0x8 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface. [0x0000 will be the current frame.]" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fcc_ctrl,Stream Frame Capture Counter control." hexmask.long.word 0xC 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed" newline hexmask.long.byte 0xC 1.--4. 1. "FCC_VC,Indicates which VC should be used to generate FCC interrupts. This value must not change while fcc_en is enabled" newline bitfld.long 0xC 0. "FCC_EN,Frame Capture Counter enable." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fifo_fill_lvl,Stream FIFO fill level monitor. This can operate in 2 modes:" bitfld.long 0x10 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0: Fill level detection disabled,1: Mode 1,?,?" newline hexmask.long.word 0x10 0.--9. 1. "COUNT,Peak fill level of FIFO." group.long 0x400++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_ctrl,CSI2RX Stream Data output datapath control." bitfld.long 0x0 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1" newline bitfld.long 0x0 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately. This may corrupt the output protocol. stream_abort_irq is generated on completion of the abort operation." "0,1" newline bitfld.long 0x0 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame. If the command is issued during frame blanking then the datapath will immediately stop streaming.." "0,1" newline bitfld.long 0x0 0. "START,Writing 1 in this register enables the corresponding datapath output. It will start streaming data at the start of the next frame that complies with the output configuration. stream_status[31] running indicates when data.." "0,1" rgroup.long 0x404++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_status,CSI2 Slave Controller Status. Contains useful debug information such as" bitfld.long 0x0 31. "RUNNING,The Stream is enabled" "0,1" newline bitfld.long 0x0 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "STREAM_FSM,Output to Stream FSM states: 0x0: STREAM_IDLE 0x1: STREAM_WAIT_CTRL_DATA // Expecting control data next 0x2: STREAM_CTRL // Check contents of Ctrl packet and extract header.." newline bitfld.long 0x0 0.--1. "PROTOCOL_FSM,Input to Stream FSM states: 0x0: PROT_IDLE 0x1: PROT_WAIT_CTRL 0x2: PROT_CTRL 0x3: PROT_DATA" "0: PROT_IDLE,1: PROT_WAIT_CTRL,2: PROT_CTRL,3: PROT_DATA" group.long 0x408++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration." hexmask.long.word 0x0 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] ->.." newline bitfld.long 0x0 15. "ENABLE_DT1,Enable processing of dt1" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DATATYPE_SELECT1,Second data type format that this stream will process" newline bitfld.long 0x0 7. "ENABLE_DT0,Enable processing of dt0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "DATATYPE_SELECT0,First data type format that this stream will process" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration." hexmask.long.word 0x4 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled. This setting is only used when fifo_mode is set for Large Buffer operation" newline bitfld.long 0x4 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type. 0 - No bypass 1 - unpack as RAW6 2 - unpack as RAW7 3 - unpack as RAW8 4 - unpack as RAW10 5 - unpack as.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates. Refer to Use Case descriptions for further guidance on FIFO sizing and.." "0: Full Line Buffer,1: Large Buffer [Fill Level Controlled],?,?" newline bitfld.long 0x4 4.--5. "NUM_PIXELS,Number of pixels to output from the stream. Valid values are 1 2 4 and 8. The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be.." "0: 1 pixel per clock,1: 2 pixels per clock,?,?" newline bitfld.long 0x4 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output. By default LS and LE short packets are not required and HYSC_VALID will be generated from the start and end of payload data." "0,1" newline bitfld.long 0x4 0. "INTERFACE_MODE,Select the output configuration. Pixel = 0 [default] Packed = 1" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_ctrl,Stream Monitor configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low. 0x0000 means truncated.." newline bitfld.long 0x8 15. "FRAME_MON_EN,Enables monitor. This bit must only be set high after the frame_mon_vc and frame_length have been set." "0,1" newline hexmask.long.byte 0x8 11.--14. 1. "FRAME_MON_VC,Indicates virtual channel for monitor. This value must not change while monitor is enabled i.e. it must only be changed when the frame_mon_en bit is low." newline bitfld.long 0x8 10. "TIMER_EOF,Select the starting point of the timer: 0x0: Start of Frame event on selected virtual channel 0x1: End of Frame event on selected virtual channel. This value must not change while timer_en is enabled" "0: Start of Frame event on selected virtual channel,1: End of Frame event on selected virtual channel" newline bitfld.long 0x8 9. "TIMER_EN,Enables timer based interrupt. This bit must only be set high after the timer_eof and timer_vc have been set." "0,1" newline hexmask.long.byte 0x8 5.--8. 1. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt. This value must not change while timer_en is enabled." newline bitfld.long 0x8 4. "LB_EN,Enables line/byte counter. This bit must only be set high after the lb_vc line_count and byte_count have been set." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt. This value must not change while lb_en is enabled" rgroup.long 0x414++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_frame,Stream Monitor Frame." hexmask.long.word 0x0 16.--31. 1. "PACKET_SIZE,Size of the current payload" newline hexmask.long.word 0x0 0.--15. 1. "NB,Number of the last frame processed." group.long 0x418++0x13 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_lb,Stream Monitor Line." hexmask.long.word 0x0 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt. [First line of a Frame is line number 0]" newline hexmask.long.word 0x0 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt. [First byte of a line is byte number 0]" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_timer,Stream Timer." hexmask.long 0x4 0.--24. 1. "COUNT,Number of clock cycles" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fcc_cfg,Stream Frame Capture Control configuration." hexmask.long.word 0x8 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface. [0x0000 will be continuous frames.]" newline hexmask.long.word 0x8 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface. [0x0000 will be the current frame.]" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fcc_ctrl,Stream Frame Capture Counter control." hexmask.long.word 0xC 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed" newline hexmask.long.byte 0xC 1.--4. 1. "FCC_VC,Indicates which VC should be used to generate FCC interrupts. This value must not change while fcc_en is enabled" newline bitfld.long 0xC 0. "FCC_EN,Frame Capture Counter enable." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fifo_fill_lvl,Stream FIFO fill level monitor. This can operate in 2 modes:" bitfld.long 0x10 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0: Fill level detection disabled,1: Mode 1,?,?" newline hexmask.long.word 0x10 0.--9. 1. "COUNT,Peak fill level of FIFO." group.long 0x900++0x13 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_status,ASF Interrupt Status Register. This register indicates the source of ASF interrupts. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this register the.." hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x0 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x0 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x0 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x0 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x0 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x0 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_raw_status,ASF Interrupt Raw Status Register. A bit set in this raw register indicates a source of ASF fault in the corresponding feature. Writing to either raw or masked status registers. clear both.." hexmask.long 0x4 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x4 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1" newline bitfld.long 0x4 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1" newline bitfld.long 0x4 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x4 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_mask,The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked. All bits are set at reset. Clear the individual bit to enable the corresponding interrupt." hexmask.long 0x8 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x8 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1" newline bitfld.long 0x8 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt." "0,1" newline bitfld.long 0x8 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0x8 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0x8 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt." "0,1" line.long 0xC "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_test,The ASF interrupt test register emulate hardware even. Write one to individual bit to trigger single event in (masked and raw) status registers according to mask and will generate interrupt accordingly." hexmask.long 0xC 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0xC 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1" newline bitfld.long 0xC 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt." "0,1" newline bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt." "0,1" newline bitfld.long 0xC 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt." "0,1" newline bitfld.long 0xC 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt." "0,1" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt." "0,1" newline bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt." "0,1" line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_fatal_nonfatal_select,The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered. If the bit of the event will be set to one then.." hexmask.long 0x10 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1" newline bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal." "0,1" newline bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal." "0,1" newline bitfld.long 0x10 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal." "0,1" newline bitfld.long 0x10 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal." "0,1" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal." "0,1" newline bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal." "0,1" rgroup.long 0x920++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_corr_fault_status,Status register for SRAM correctable fault. These fields are updated whenever asf_sram_corr_fault input is active." hexmask.long.byte 0x0 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x0 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault." line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_uncorr_fault_status,Status register for SRAM uncorrectable fault. These fields are updated whenever asf_sram_uncorr_fault input is active." hexmask.long.byte 0x4 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault." newline hexmask.long.tbyte 0x4 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault." group.long 0x928++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_fault_stats,Statistics register for SRAM faults. Note that this register clears when software writes to any field." hexmask.long.word 0x0 16.--31. 1. "RESERVED,Reserved read as 0 ignored on write." newline hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented. Count value will saturate at 0xffff." group.long 0x930++0xB line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_ctrl,Control register to configure the ASF transaction timeout monitors." bitfld.long 0x0 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor." line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_fault_mask,Control register to mask out ASF transaction timeout faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt.." bitfld.long 0x4 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask register for each ASF transaction timeout fault source." "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_fault_status,Status register for transaction timeouts fault. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit." bitfld.long 0x8 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for transaction timeouts faults." "0,1" group.long 0x940++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_protocol_fault_mask,Control register to mask out ASF Protocol faults from triggering interrupts. On reset. all bits are set to mask out all sources. Clear the corresponding bit to enable the interrupt source. The.." bitfld.long 0x0 13. "ASF_PROTOCOL_FAULT_13_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 12. "ASF_PROTOCOL_FAULT_12_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 11. "ASF_PROTOCOL_FAULT_11_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 10. "ASF_PROTOCOL_FAULT_10_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 9. "ASF_PROTOCOL_FAULT_9_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 8. "ASF_PROTOCOL_FAULT_8_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 7. "ASF_PROTOCOL_FAULT_7_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 6. "ASF_PROTOCOL_FAULT_6_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_FAULT_5_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 4. "ASF_PROTOCOL_FAULT_4_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 3. "ASF_PROTOCOL_FAULT_3_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 2. "ASF_PROTOCOL_FAULT_2_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 1. "ASF_PROTOCOL_FAULT_1_MASK,Mask register for each ASF protocol fault source." "0,1" newline bitfld.long 0x0 0. "ASF_PROTOCOL_FAULT_0_MASK,Mask register for each ASF protocol fault source." "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_protocol_fault_status,Status register for protocol faults. If a fault occurs the revelant status bit will be set to 1. Each bit can be cleared by software writing 1 to each bit" bitfld.long 0x4 13. "ASF_PROTOCOL_FAULT_13_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 12. "ASF_PROTOCOL_FAULT_12_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 11. "ASF_PROTOCOL_FAULT_11_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 10. "ASF_PROTOCOL_FAULT_10_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 9. "ASF_PROTOCOL_FAULT_9_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 8. "ASF_PROTOCOL_FAULT_8_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 7. "ASF_PROTOCOL_FAULT_7_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 6. "ASF_PROTOCOL_FAULT_6_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_FAULT_5_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 4. "ASF_PROTOCOL_FAULT_4_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 3. "ASF_PROTOCOL_FAULT_3_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 2. "ASF_PROTOCOL_FAULT_2_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 1. "ASF_PROTOCOL_FAULT_1_STATUS,Status bits for protocol faults." "0,1" newline bitfld.long 0x4 0. "ASF_PROTOCOL_FAULT_0_STATUS,Status bits for protocol faults." "0,1" rgroup.long 0xFFC++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_id_prod_ver,This register is hard-coded in order to allow software to identify the product and its" hexmask.long.word 0x0 16.--31. 1. "PRODUCT_ID,Product Identification Number [IP5022/IP5022A]." newline hexmask.long.word 0x0 0.--15. 1. "VERSION_ID,Product Version Number [R200]." tree.end tree.end tree "CTRL_MMR0_CFG0" base ad:0x100000 rgroup.long 0x0++0x3 line.long 0x0 "CFG0_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16" newline hexmask.long.byte 0x0 11.--15. 1. "PID_MISC" newline bitfld.long 0x0 8.--10. "PID_MAJOR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR" rgroup.long 0x8++0x3 line.long 0x0 "CFG0_MMR_CFG1" bitfld.long 0x0 31. "MMR_CFG1_PROXY_EN,Proxy addressing activated" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions" group.long 0x100++0x3 line.long 0x0 "CFG0_IPC_SET0" hexmask.long 0x0 4.--31. 1. "IPC_SET0_IPC_SRC_SET,Read returns current value Write: 0 - No effect 1 - Sets both corresponding IPC_CLR and the IPC_SET bits" newline bitfld.long 0x0 0. "IPC_SET0_IPC_SET,Read returns 0 Write: 0 - No effect 1 - Sets both corresponding IPC_CLR and the IPC_SET bits" "0,1" group.long 0x180++0x3 line.long 0x0 "CFG0_IPC_CLR0" hexmask.long 0x0 4.--31. 1. "IPC_CLR0_IPC_SRC_CLR,Read returns current value Write: 0 - No effect 1 - Clears both corresponding IPC_CLR and the IPC_SET bits" newline bitfld.long 0x0 0. "IPC_CLR0_IPC_CLR,Read returns current value Write: 0 - No effect 1 - Clears both corresponding IPC_CLR and the IPC_SET bits" "0,1" group.long 0x1008++0x1B line.long 0x0 "CFG0_LOCK0_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK0_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" line.long 0x8 "CFG0_intr_raw_status" bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "CFG0_intr_enabled_status_clear" bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "CFG0_intr_enable" bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "CFG0_intr_enable_clear" bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "CFG0_eoi" hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0xB line.long 0x0 "CFG0_fault_address" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." line.long 0x4 "CFG0_fault_type_status" bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.." line.long 0x8 "CFG0_fault_attr_status" hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID." newline hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID." wgroup.long 0x1030++0x3 line.long 0x0 "CFG0_fault_clear" bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" rgroup.long 0x1100++0x1B line.long 0x0 "CFG0_CLAIMREG_P0_R0_READONLY" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0_READONLY,Claim bits for Partition 0" line.long 0x4 "CFG0_CLAIMREG_P0_R1_READONLY" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P0_R1_READONLY,Claim bits for Partition 0" line.long 0x8 "CFG0_CLAIMREG_P0_R2_READONLY" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P0_R2_READONLY,Claim bits for Partition 0" line.long 0xC "CFG0_CLAIMREG_P0_R3_READONLY" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P0_R3_READONLY,Claim bits for Partition 0" line.long 0x10 "CFG0_CLAIMREG_P0_R4_READONLY" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P0_R4_READONLY,Claim bits for Partition 0" line.long 0x14 "CFG0_CLAIMREG_P0_R5_READONLY" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P0_R5_READONLY,Claim bits for Partition 0" line.long 0x18 "CFG0_CLAIMREG_P0_R6_READONLY" hexmask.long 0x18 0.--31. 1. "CLAIMREG_P0_R6_READONLY,Claim bits for Partition 0" rgroup.long 0x2000++0x3 line.long 0x0 "CFG0_PID_PROXY" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16_PROXY" newline hexmask.long.byte 0x0 11.--15. 1. "PID_MISC_PROXY" newline bitfld.long 0x0 8.--10. "PID_MAJOR_PROXY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM_PROXY" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR_PROXY" rgroup.long 0x2008++0x3 line.long 0x0 "CFG0_MMR_CFG1_PROXY" bitfld.long 0x0 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing activated" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions" group.long 0x2100++0x3 line.long 0x0 "CFG0_IPC_SET0_PROXY" hexmask.long 0x0 4.--31. 1. "IPC_SET0_IPC_SRC_SET_PROXY,Read returns current value Write: 0 - No effect 1 - Sets both corresponding IPC_CLR and the IPC_SET bits" newline bitfld.long 0x0 0. "IPC_SET0_IPC_SET_PROXY,Read returns 0 Write: 0 - No effect 1 - Sets both corresponding IPC_CLR and the IPC_SET bits" "0,1" group.long 0x2180++0x3 line.long 0x0 "CFG0_IPC_CLR0_PROXY" hexmask.long 0x0 4.--31. 1. "IPC_CLR0_IPC_SRC_CLR_PROXY,Read returns current value Write: 0 - No effect 1 - Clears both corresponding IPC_CLR and the IPC_SET bits" newline bitfld.long 0x0 0. "IPC_CLR0_IPC_CLR_PROXY,Read returns current value Write: 0 - No effect 1 - Clears both corresponding IPC_CLR and the IPC_SET bits" "0,1" group.long 0x3008++0x1B line.long 0x0 "CFG0_LOCK0_KICK0_PROXY" hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK0_KICK1_PROXY" hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1_PROXY,- KICK1 component" line.long 0x8 "CFG0_intr_raw_status_PROXY" bitfld.long 0x8 3. "PROXY_ERR_PROXY,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "KICK_ERR_PROXY,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR_PROXY,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "PROT_ERR_PROXY,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "CFG0_intr_enabled_status_clear_PROXY" bitfld.long 0xC 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "ENABLED_PROT_ERR_PROXY,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "CFG0_intr_enable_PROXY" bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "CFG0_intr_enable_clear_PROXY" bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "CFG0_eoi_PROXY" hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x3024++0xB line.long 0x0 "CFG0_fault_address_PROXY" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR_PROXY,Fault Address." line.long 0x4 "CFG0_fault_type_status_PROXY" bitfld.long 0x4 6. "FAULT_NS_PROXY,Non-secure access." "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE_PROXY,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv =.." line.long 0x8 "CFG0_fault_attr_status_PROXY" hexmask.long.word 0x8 20.--31. 1. "FAULT_XID_PROXY,XID." newline hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID." wgroup.long 0x3030++0x3 line.long 0x0 "CFG0_fault_clear_PROXY" bitfld.long 0x0 0. "FAULT_CLR_PROXY,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" group.long 0x3100++0x1B line.long 0x0 "CFG0_CLAIMREG_P0_R0" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0,Claim bits for Partition 0" line.long 0x4 "CFG0_CLAIMREG_P0_R1" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P0_R1,Claim bits for Partition 0" line.long 0x8 "CFG0_CLAIMREG_P0_R2" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P0_R2,Claim bits for Partition 0" line.long 0xC "CFG0_CLAIMREG_P0_R3" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P0_R3,Claim bits for Partition 0" line.long 0x10 "CFG0_CLAIMREG_P0_R4" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P0_R4,Claim bits for Partition 0" line.long 0x14 "CFG0_CLAIMREG_P0_R5" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P0_R5,Claim bits for Partition 0" line.long 0x18 "CFG0_CLAIMREG_P0_R6" hexmask.long 0x18 0.--31. 1. "CLAIMREG_P0_R6,Claim bits for Partition 0" group.long 0x4044++0x7 line.long 0x0 "CFG0_ENET1_CTRL" bitfld.long 0x0 4. "ENET1_CTRL_RGMII_ID_MODE,Port1 RGMII internal transmit delay selection 0 - Internal transmit delay 1 - No intenal transmit delay" "0,1" newline bitfld.long 0x0 0.--2. "ENET1_CTRL_PORT_MODE_SEL,Selects Ethernet switch Port1 interface Field values (others are reserved): 3'b000 - GMII/MII (not supported) 3'b001 - RMII 3'b010 - RGMII 3'b011 - SGMII (not supported) 3'b100 - QSGMII (not supported) 3'b101 - XFI (not.." "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_ENET2_CTRL" bitfld.long 0x4 4. "ENET2_CTRL_RGMII_ID_MODE,Port2 RGMII internal transmit delay selection 0 - Internal transmit delay 1 - No intenal transmit delay" "0,1" newline bitfld.long 0x4 0.--2. "ENET2_CTRL_PORT_MODE_SEL,Selects Ethernet switch Port2 interface Field values (others are reserved): 3'b000 - GMII/MII (not supported) 3'b001 - RMII 3'b010 - RGMII 3'b011 - SGMII (not supported) 3'b100 - QSGMII (not supported) 3'b101 - XFI (not.." "0,1,2,3,4,5,6,7" group.long 0x4130++0x3 line.long 0x0 "CFG0_EPWM_TB_CLKEN" bitfld.long 0x0 2. "EPWM_TB_CLKEN_EPWM2_TB_CLKEN,Activates Timebase Clock of EPWM2 When Set" "0,1" newline bitfld.long 0x0 1. "EPWM_TB_CLKEN_EPWM1_TB_CLKEN,Activates Timebase Clock of EPWM1 When Set" "0,1" newline bitfld.long 0x0 0. "EPWM_TB_CLKEN_EPWM0_TB_CLKEN,Activates Timebase Clock of EPWM0 When Set" "0,1" group.long 0x4140++0xB line.long 0x0 "CFG0_EPWM0_CTRL" bitfld.long 0x0 8.--10. "EPWM0_CTRL_SYNCIN_SEL,Selects the source of the EPWM0 synchronization input Field values (others are reserved): 3'b000 - EPWM0_SYNCIN Pin 3'b001 - None 3'b010 - Time Sync Router 19 3'b011 - Compare Event Router 32 undefined - undefined 3'b100 - None.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "EPWM0_CTRL_EALLOW,Activate write access to EPWM tripzone registers 0 - Deactivated 1 - Activated" "0,1" line.long 0x4 "CFG0_EPWM1_CTRL" bitfld.long 0x4 4. "EPWM1_CTRL_EALLOW,Activate write access to EPWM tripzone registers 0 - Deactivated 1 - Activated" "0,1" line.long 0x8 "CFG0_EPWM2_CTRL" bitfld.long 0x8 4. "EPWM2_CTRL_EALLOW,Activate write access to EPWM tripzone registers 0 - Deactivated 1 - Activated" "0,1" group.long 0x4180++0xB line.long 0x0 "CFG0_EQEP0_CTRL" hexmask.long.byte 0x0 0.--4. 1. "EQEP0_CTRL_SOCA_SEL,Selects the source of SOCA input for EQEP0 Field values (others are reserved): undefined - undefined undefined - undefined 5'b00010 - EPWM SOCA_OUT 5'b00011 - EPWM SOCB_OUT 5'b00100 - MCU_TIMER0 PWM 5'b00101 - MCU_TIMER1 PWM.." line.long 0x4 "CFG0_EQEP1_CTRL" hexmask.long.byte 0x4 0.--4. 1. "EQEP1_CTRL_SOCA_SEL,Selects the source of SOCA input for EQEP1 Field values (others are reserved): undefined - undefined undefined - undefined 5'b00010 - EPWM SOCA_OUT 5'b00011 - EPWM SOCB_OUT 5'b00100 - MCU_TIMER0 PWM 5'b00101 - MCU_TIMER1 PWM.." line.long 0x8 "CFG0_EQEP2_CTRL" hexmask.long.byte 0x8 0.--4. 1. "EQEP2_CTRL_SOCA_SEL,Selects the source of SOCA input for EQEP2 Field values (others are reserved): undefined - undefined undefined - undefined 5'b00010 - EPWM SOCA_OUT 5'b00011 - EPWM SOCB_OUT 5'b00100 - MCU_TIMER0 PWM 5'b00101 - MCU_TIMER1 PWM.." rgroup.long 0x41A0++0x3 line.long 0x0 "CFG0_EQEP_STAT" bitfld.long 0x0 2. "EQEP_STAT_PHASE_ERR2,EQEP2 Phase error status 0 - No error 1 - Phase error occurred" "0,1" newline bitfld.long 0x0 1. "EQEP_STAT_PHASE_ERR1,EQEP1 Phase error status 0 - No error 1 - Phase error occurred" "0,1" newline bitfld.long 0x0 0. "EQEP_STAT_PHASE_ERR0,EQEP0 Phase error status 0 - No error 1 - Phase error occurred" "0,1" group.long 0x4204++0x3 line.long 0x0 "CFG0_TIMER1_CTRL" bitfld.long 0x0 8. "TIMER1_CTRL_CASCADE_EN,Activates cascading of TIMER1 to TIMER0" "0,1" group.long 0x420C++0x3 line.long 0x0 "CFG0_TIMER3_CTRL" bitfld.long 0x0 8. "TIMER3_CTRL_CASCADE_EN,Activates cascading of TIMER3 to TIMER2" "0,1" group.long 0x4214++0x3 line.long 0x0 "CFG0_TIMER5_CTRL" bitfld.long 0x0 8. "TIMER5_CTRL_CASCADE_EN,Activates cascading of TIMER5 to TIMER4" "0,1" group.long 0x421C++0x3 line.long 0x0 "CFG0_TIMER7_CTRL" bitfld.long 0x0 8. "TIMER7_CTRL_CASCADE_EN,Activates cascading of TIMER7 to TIMER6" "0,1" group.long 0x4300++0x3 line.long 0x0 "CFG0_C7XV_CTRL0" bitfld.long 0x0 15. "C7XV_CTRL0_ORD15,Ordering Rule for Order ID 15 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 14. "C7XV_CTRL0_ORD14,Ordering Rule for Order ID 14 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 13. "C7XV_CTRL0_ORD13,Ordering Rule for Order ID 13 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 12. "C7XV_CTRL0_ORD12,Ordering Rule for Order ID 12 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 11. "C7XV_CTRL0_ORD11,Ordering Rule for Order ID 11 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 10. "C7XV_CTRL0_ORD10,Ordering Rule for Order ID 10 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 9. "C7XV_CTRL0_ORD9,Ordering Rule for Order ID 9 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 8. "C7XV_CTRL0_ORD8,Ordering Rule for Order ID 8 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 7. "C7XV_CTRL0_ORD7,Ordering Rule for Order ID 7 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 6. "C7XV_CTRL0_ORD6,Ordering Rule for Order ID 6 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 5. "C7XV_CTRL0_ORD5,Ordering Rule for Order ID 5 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 4. "C7XV_CTRL0_ORD4,Ordering Rule for Order ID 4 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 3. "C7XV_CTRL0_ORD3,Ordering Rule for Order ID 3 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 2. "C7XV_CTRL0_ORD2,Ordering Rule for Order ID 2 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 1. "C7XV_CTRL0_ORD1,Ordering Rule for Order ID 1 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 0. "C7XV_CTRL0_ORD0,Ordering Rule for Order ID 0 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" rgroup.long 0x44C0++0xB line.long 0x0 "CFG0_EMMC0_STAT" bitfld.long 0x0 0. "EMMC0_STAT_SIG1P8_EN,Status of 1.8V Signal Activate from EMMC0 Module" "0,1" line.long 0x4 "CFG0_EMMC1_STAT" bitfld.long 0x4 0. "EMMC1_STAT_SIG1P8_EN,Status of 1.8V Signal Activate from EMMC1 Module" "0,1" line.long 0x8 "CFG0_EMMC2_STAT" bitfld.long 0x8 0. "EMMC2_STAT_SIG1P8_EN,Status of 1.8V Signal Activate from EMMC2 Module" "0,1" group.long 0x4700++0x3 line.long 0x0 "CFG0_FSS_CTRL" bitfld.long 0x0 8. "FSS_CTRL_S0_BOOT_SIZE,Selects the size of the boot block to be used for the S0 (OSPI0) flash interface 0 - S0 boot size is 64 MB 1 - S0 boot size is 128 MB" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "FSS_CTRL_S0_BOOT_SEG,Selects the boot block to be used for the S0 (OSPI0) flash interface. If the s0_boot_size is 128 MB then only bits [4:0] of this field are used. Care must be taken to account for the address translation as to not fall off or wrap.." rgroup.long 0x4750++0x3 line.long 0x0 "CFG0_DCC_STAT" bitfld.long 0x0 17. "DCC_STAT_MCU_DCC1_INTR_DONE,MCU_DCC1 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 16. "DCC_STAT_MCU_DCC0_INTR_DONE,MCU_DCC0 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 6. "DCC_STAT_DCC6_INTR_DONE,DCC6 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 5. "DCC_STAT_DCC5_INTR_DONE,DCC5 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 4. "DCC_STAT_DCC4_INTR_DONE,DCC4 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 3. "DCC_STAT_DCC3_INTR_DONE,DCC3 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 2. "DCC_STAT_DCC2_INTR_DONE,DCC2 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 1. "DCC_STAT_DCC1_INTR_DONE,DCC1 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 0. "DCC_STAT_DCC0_INTR_DONE,DCC0 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" group.long 0x5008++0x7 line.long 0x0 "CFG0_LOCK1_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK1_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1,- KICK1 component" rgroup.long 0x5100++0x3B line.long 0x0 "CFG0_CLAIMREG_P1_R0_READONLY" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0_READONLY,Claim bits for Partition 1" line.long 0x4 "CFG0_CLAIMREG_P1_R1_READONLY" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1_READONLY,Claim bits for Partition 1" line.long 0x8 "CFG0_CLAIMREG_P1_R2_READONLY" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2_READONLY,Claim bits for Partition 1" line.long 0xC "CFG0_CLAIMREG_P1_R3_READONLY" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P1_R3_READONLY,Claim bits for Partition 1" line.long 0x10 "CFG0_CLAIMREG_P1_R4_READONLY" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P1_R4_READONLY,Claim bits for Partition 1" line.long 0x14 "CFG0_CLAIMREG_P1_R5_READONLY" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P1_R5_READONLY,Claim bits for Partition 1" line.long 0x18 "CFG0_CLAIMREG_P1_R6_READONLY" hexmask.long 0x18 0.--31. 1. "CLAIMREG_P1_R6_READONLY,Claim bits for Partition 1" line.long 0x1C "CFG0_CLAIMREG_P1_R7_READONLY" hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P1_R7_READONLY,Claim bits for Partition 1" line.long 0x20 "CFG0_CLAIMREG_P1_R8_READONLY" hexmask.long 0x20 0.--31. 1. "CLAIMREG_P1_R8_READONLY,Claim bits for Partition 1" line.long 0x24 "CFG0_CLAIMREG_P1_R9_READONLY" hexmask.long 0x24 0.--31. 1. "CLAIMREG_P1_R9_READONLY,Claim bits for Partition 1" line.long 0x28 "CFG0_CLAIMREG_P1_R10_READONLY" hexmask.long 0x28 0.--31. 1. "CLAIMREG_P1_R10_READONLY,Claim bits for Partition 1" line.long 0x2C "CFG0_CLAIMREG_P1_R11_READONLY" hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P1_R11_READONLY,Claim bits for Partition 1" line.long 0x30 "CFG0_CLAIMREG_P1_R12_READONLY" hexmask.long 0x30 0.--31. 1. "CLAIMREG_P1_R12_READONLY,Claim bits for Partition 1" line.long 0x34 "CFG0_CLAIMREG_P1_R13_READONLY" hexmask.long 0x34 0.--31. 1. "CLAIMREG_P1_R13_READONLY,Claim bits for Partition 1" line.long 0x38 "CFG0_CLAIMREG_P1_R14_READONLY" hexmask.long 0x38 0.--31. 1. "CLAIMREG_P1_R14_READONLY,Claim bits for Partition 1" group.long 0x6044++0x7 line.long 0x0 "CFG0_ENET1_CTRL_PROXY" bitfld.long 0x0 4. "ENET1_CTRL_RGMII_ID_MODE_PROXY,Port1 RGMII internal transmit delay selection 0 - Internal transmit delay 1 - No intenal transmit delay" "0,1" newline bitfld.long 0x0 0.--2. "ENET1_CTRL_PORT_MODE_SEL_PROXY,Selects Ethernet switch Port1 interface Field values (others are reserved): 3'b000 - GMII/MII (not supported) 3'b001 - RMII 3'b010 - RGMII 3'b011 - SGMII (not supported) 3'b100 - QSGMII (not supported) 3'b101 - XFI (not.." "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_ENET2_CTRL_PROXY" bitfld.long 0x4 4. "ENET2_CTRL_RGMII_ID_MODE_PROXY,Port2 RGMII internal transmit delay selection 0 - Internal transmit delay 1 - No intenal transmit delay" "0,1" newline bitfld.long 0x4 0.--2. "ENET2_CTRL_PORT_MODE_SEL_PROXY,Selects Ethernet switch Port2 interface Field values (others are reserved): 3'b000 - GMII/MII (not supported) 3'b001 - RMII 3'b010 - RGMII 3'b011 - SGMII (not supported) 3'b100 - QSGMII (not supported) 3'b101 - XFI (not.." "0,1,2,3,4,5,6,7" group.long 0x6130++0x3 line.long 0x0 "CFG0_EPWM_TB_CLKEN_PROXY" bitfld.long 0x0 2. "EPWM_TB_CLKEN_EPWM2_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM2 When Set" "0,1" newline bitfld.long 0x0 1. "EPWM_TB_CLKEN_EPWM1_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM1 When Set" "0,1" newline bitfld.long 0x0 0. "EPWM_TB_CLKEN_EPWM0_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM0 When Set" "0,1" group.long 0x6140++0xB line.long 0x0 "CFG0_EPWM0_CTRL_PROXY" bitfld.long 0x0 8.--10. "EPWM0_CTRL_SYNCIN_SEL_PROXY,Selects the source of the EPWM0 synchronization input Field values (others are reserved): 3'b000 - EPWM0_SYNCIN Pin 3'b001 - None 3'b010 - Time Sync Router 19 3'b011 - Compare Event Router 32 undefined - undefined 3'b100 -.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "EPWM0_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers 0 - Deactivated 1 - Activated" "0,1" line.long 0x4 "CFG0_EPWM1_CTRL_PROXY" bitfld.long 0x4 4. "EPWM1_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers 0 - Deactivated 1 - Activated" "0,1" line.long 0x8 "CFG0_EPWM2_CTRL_PROXY" bitfld.long 0x8 4. "EPWM2_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers 0 - Deactivated 1 - Activated" "0,1" group.long 0x6180++0xB line.long 0x0 "CFG0_EQEP0_CTRL_PROXY" hexmask.long.byte 0x0 0.--4. 1. "EQEP0_CTRL_SOCA_SEL_PROXY,Selects the source of SOCA input for EQEP0 Field values (others are reserved): undefined - undefined undefined - undefined 5'b00010 - EPWM SOCA_OUT 5'b00011 - EPWM SOCB_OUT 5'b00100 - MCU_TIMER0 PWM 5'b00101 - MCU_TIMER1 PWM.." line.long 0x4 "CFG0_EQEP1_CTRL_PROXY" hexmask.long.byte 0x4 0.--4. 1. "EQEP1_CTRL_SOCA_SEL_PROXY,Selects the source of SOCA input for EQEP1 Field values (others are reserved): undefined - undefined undefined - undefined 5'b00010 - EPWM SOCA_OUT 5'b00011 - EPWM SOCB_OUT 5'b00100 - MCU_TIMER0 PWM 5'b00101 - MCU_TIMER1 PWM.." line.long 0x8 "CFG0_EQEP2_CTRL_PROXY" hexmask.long.byte 0x8 0.--4. 1. "EQEP2_CTRL_SOCA_SEL_PROXY,Selects the source of SOCA input for EQEP2 Field values (others are reserved): undefined - undefined undefined - undefined 5'b00010 - EPWM SOCA_OUT 5'b00011 - EPWM SOCB_OUT 5'b00100 - MCU_TIMER0 PWM 5'b00101 - MCU_TIMER1 PWM.." rgroup.long 0x61A0++0x3 line.long 0x0 "CFG0_EQEP_STAT_PROXY" bitfld.long 0x0 2. "EQEP_STAT_PHASE_ERR2_PROXY,EQEP2 Phase error status 0 - No error 1 - Phase error occurred" "0,1" newline bitfld.long 0x0 1. "EQEP_STAT_PHASE_ERR1_PROXY,EQEP1 Phase error status 0 - No error 1 - Phase error occurred" "0,1" newline bitfld.long 0x0 0. "EQEP_STAT_PHASE_ERR0_PROXY,EQEP0 Phase error status 0 - No error 1 - Phase error occurred" "0,1" group.long 0x6204++0x3 line.long 0x0 "CFG0_TIMER1_CTRL_PROXY" bitfld.long 0x0 8. "TIMER1_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER1 to TIMER0" "0,1" group.long 0x620C++0x3 line.long 0x0 "CFG0_TIMER3_CTRL_PROXY" bitfld.long 0x0 8. "TIMER3_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER3 to TIMER2" "0,1" group.long 0x6214++0x3 line.long 0x0 "CFG0_TIMER5_CTRL_PROXY" bitfld.long 0x0 8. "TIMER5_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER5 to TIMER4" "0,1" group.long 0x621C++0x3 line.long 0x0 "CFG0_TIMER7_CTRL_PROXY" bitfld.long 0x0 8. "TIMER7_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER7 to TIMER6" "0,1" group.long 0x6300++0x3 line.long 0x0 "CFG0_C7XV_CTRL0_PROXY" bitfld.long 0x0 15. "C7XV_CTRL0_ORD15_PROXY,Ordering Rule for Order ID 15 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 14. "C7XV_CTRL0_ORD14_PROXY,Ordering Rule for Order ID 14 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 13. "C7XV_CTRL0_ORD13_PROXY,Ordering Rule for Order ID 13 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 12. "C7XV_CTRL0_ORD12_PROXY,Ordering Rule for Order ID 12 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 11. "C7XV_CTRL0_ORD11_PROXY,Ordering Rule for Order ID 11 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 10. "C7XV_CTRL0_ORD10_PROXY,Ordering Rule for Order ID 10 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 9. "C7XV_CTRL0_ORD9_PROXY,Ordering Rule for Order ID 9 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 8. "C7XV_CTRL0_ORD8_PROXY,Ordering Rule for Order ID 8 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 7. "C7XV_CTRL0_ORD7_PROXY,Ordering Rule for Order ID 7 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 6. "C7XV_CTRL0_ORD6_PROXY,Ordering Rule for Order ID 6 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 5. "C7XV_CTRL0_ORD5_PROXY,Ordering Rule for Order ID 5 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 4. "C7XV_CTRL0_ORD4_PROXY,Ordering Rule for Order ID 4 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 3. "C7XV_CTRL0_ORD3_PROXY,Ordering Rule for Order ID 3 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 2. "C7XV_CTRL0_ORD2_PROXY,Ordering Rule for Order ID 2 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 1. "C7XV_CTRL0_ORD1_PROXY,Ordering Rule for Order ID 1 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" newline bitfld.long 0x0 0. "C7XV_CTRL0_ORD0_PROXY,Ordering Rule for Order ID 0 Field values (others are reserved): 1'b1 - RELAXED_R_TO_W 1'b0 - RELAXED_READ" "0,1" rgroup.long 0x64C0++0xB line.long 0x0 "CFG0_EMMC0_STAT_PROXY" bitfld.long 0x0 0. "EMMC0_STAT_SIG1P8_EN_PROXY,Status of 1.8V Signal Activate from EMMC0 Module" "0,1" line.long 0x4 "CFG0_EMMC1_STAT_PROXY" bitfld.long 0x4 0. "EMMC1_STAT_SIG1P8_EN_PROXY,Status of 1.8V Signal Activate from EMMC1 Module" "0,1" line.long 0x8 "CFG0_EMMC2_STAT_PROXY" bitfld.long 0x8 0. "EMMC2_STAT_SIG1P8_EN_PROXY,Status of 1.8V Signal Activate from EMMC2 Module" "0,1" group.long 0x6700++0x3 line.long 0x0 "CFG0_FSS_CTRL_PROXY" bitfld.long 0x0 8. "FSS_CTRL_S0_BOOT_SIZE_PROXY,Selects the size of the boot block to be used for the S0 (OSPI0) flash interface 0 - S0 boot size is 64 MB 1 - S0 boot size is 128 MB" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "FSS_CTRL_S0_BOOT_SEG_PROXY,Selects the boot block to be used for the S0 (OSPI0) flash interface. If the s0_boot_size is 128 MB then only bits [4:0] of this field are used. Care must be taken to account for the address translation as to not fall off or.." rgroup.long 0x6750++0x3 line.long 0x0 "CFG0_DCC_STAT_PROXY" bitfld.long 0x0 17. "DCC_STAT_MCU_DCC1_INTR_DONE_PROXY,MCU_DCC1 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 16. "DCC_STAT_MCU_DCC0_INTR_DONE_PROXY,MCU_DCC0 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 6. "DCC_STAT_DCC6_INTR_DONE_PROXY,DCC6 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 5. "DCC_STAT_DCC5_INTR_DONE_PROXY,DCC5 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 4. "DCC_STAT_DCC4_INTR_DONE_PROXY,DCC4 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 3. "DCC_STAT_DCC3_INTR_DONE_PROXY,DCC3 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 2. "DCC_STAT_DCC2_INTR_DONE_PROXY,DCC2 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 1. "DCC_STAT_DCC1_INTR_DONE_PROXY,DCC1 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" newline bitfld.long 0x0 0. "DCC_STAT_DCC0_INTR_DONE_PROXY,DCC0 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending" "0: No Interrupt Pending,1: Interrupt Pending" group.long 0x7008++0x7 line.long 0x0 "CFG0_LOCK1_KICK0_PROXY" hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK1_KICK1_PROXY" hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1_PROXY,- KICK1 component" group.long 0x7100++0x3B line.long 0x0 "CFG0_CLAIMREG_P1_R0" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0,Claim bits for Partition 1" line.long 0x4 "CFG0_CLAIMREG_P1_R1" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1,Claim bits for Partition 1" line.long 0x8 "CFG0_CLAIMREG_P1_R2" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2,Claim bits for Partition 1" line.long 0xC "CFG0_CLAIMREG_P1_R3" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P1_R3,Claim bits for Partition 1" line.long 0x10 "CFG0_CLAIMREG_P1_R4" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P1_R4,Claim bits for Partition 1" line.long 0x14 "CFG0_CLAIMREG_P1_R5" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P1_R5,Claim bits for Partition 1" line.long 0x18 "CFG0_CLAIMREG_P1_R6" hexmask.long 0x18 0.--31. 1. "CLAIMREG_P1_R6,Claim bits for Partition 1" line.long 0x1C "CFG0_CLAIMREG_P1_R7" hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P1_R7,Claim bits for Partition 1" line.long 0x20 "CFG0_CLAIMREG_P1_R8" hexmask.long 0x20 0.--31. 1. "CLAIMREG_P1_R8,Claim bits for Partition 1" line.long 0x24 "CFG0_CLAIMREG_P1_R9" hexmask.long 0x24 0.--31. 1. "CLAIMREG_P1_R9,Claim bits for Partition 1" line.long 0x28 "CFG0_CLAIMREG_P1_R10" hexmask.long 0x28 0.--31. 1. "CLAIMREG_P1_R10,Claim bits for Partition 1" line.long 0x2C "CFG0_CLAIMREG_P1_R11" hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P1_R11,Claim bits for Partition 1" line.long 0x30 "CFG0_CLAIMREG_P1_R12" hexmask.long 0x30 0.--31. 1. "CLAIMREG_P1_R12,Claim bits for Partition 1" line.long 0x34 "CFG0_CLAIMREG_P1_R13" hexmask.long 0x34 0.--31. 1. "CLAIMREG_P1_R13,Claim bits for Partition 1" line.long 0x38 "CFG0_CLAIMREG_P1_R14" hexmask.long 0x38 0.--31. 1. "CLAIMREG_P1_R14,Claim bits for Partition 1" group.long 0x8000++0x3 line.long 0x0 "CFG0_OBSCLK0_CTRL" bitfld.long 0x0 24. "OBSCLK0_CTRL_OUT_MUX_SEL,OBSCLK pin output mux selection. Note HFOSC0_CLK is a direct output from the HFOSC0 distinct from HFOSC0_CLKOUT. Note when HFOSC0_CLK is selected (1'b1) the MCU_OBSCLK_CTRL_clk_sel field must be programmed to 5'b11111." "0,1" newline bitfld.long 0x0 16. "OBSCLK0_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the OBSCLK0 divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "OBSCLK0_CTRL_CLK_DIV,OBSCLK0 output divider Divides the selected clock by clkdiv+1 for output to the OBSCLK0 pins. Supports divide by 1 to 256 (default to 1). To load the new divider value the clk_div_ld bit must be cleared and then set to 1." newline hexmask.long.byte 0x0 0.--4. 1. "OBSCLK0_CTRL_CLK_SEL,OBSCLK0 clock source selection. Selects the source of the clock to be divided by the OBSCLK0 divider and output on the OBSCLK0 pin. Field values (others are reserved): 5'b00000 - MAIN_PLL0_HSDIV0_CLKOUT 5'b00001 -.." group.long 0x8010++0x3 line.long 0x0 "CFG0_CLKOUT_CTRL" bitfld.long 0x0 0. "CLKOUT_CTRL_CLK_SEL,Selects CLKOUT clock source Field values (others are reserved): 1'b0 - MAIN_PLL2_HSDIV1_CLKOUT / 5 1'b1 - MAIN_PLL2_HSDIV1_CLKOUT / 10" "0,1" group.long 0x8060++0xB line.long 0x0 "CFG0_MAIN_PLL0_CLKSEL" bitfld.long 0x0 31. "MAIN_PLL0_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL0. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL0_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to activate bypass software override. This bit is set (1'b0) when a MAIN warm reset occurs to keep MAIN PLL0 from being bypassed .." "0: Exit bypass mode,1: Maintain bypass mode" line.long 0x4 "CFG0_MAIN_PLL1_CLKSEL" bitfld.long 0x4 31. "MAIN_PLL1_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL1 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x4 23. "MAIN_PLL1_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL1 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behaviot. Because.." "0,1" line.long 0x8 "CFG0_MAIN_PLL2_CLKSEL" bitfld.long 0x8 31. "MAIN_PLL2_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL2 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x8 23. "MAIN_PLL2_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL2 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behaviot. Because.." "0,1" group.long 0x8074++0x3 line.long 0x0 "CFG0_MAIN_PLL5_CLKSEL" bitfld.long 0x0 31. "MAIN_PLL5_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL5. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL5_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to activate bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL5 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" group.long 0x807C++0x7 line.long 0x0 "CFG0_MAIN_PLL7_CLKSEL" bitfld.long 0x0 31. "MAIN_PLL7_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL7. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL7_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to activate bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL7 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" line.long 0x4 "CFG0_MAIN_PLL8_CLKSEL" bitfld.long 0x4 31. "MAIN_PLL8_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL8. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x4 23. "MAIN_PLL8_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to activate bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL8 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" group.long 0x8090++0x3 line.long 0x0 "CFG0_MAIN_PLL12_CLKSEL" bitfld.long 0x0 31. "MAIN_PLL12_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL12. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL12_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to activate bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL12 in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" group.long 0x80A4++0x3 line.long 0x0 "CFG0_MAIN_PLL17_CLKSEL" bitfld.long 0x0 31. "MAIN_PLL17_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL17 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL17_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL17 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behaviot. Because.." "0,1" group.long 0x8140++0x3 line.long 0x0 "CFG0_CPSW_CLKSEL" bitfld.long 0x0 0.--2. "CPSW_CLKSEL_CPTS_CLKSEL,Selects the clock source for the CPSW Ethernet switch Common Platform Time Stamp module Field values (others are reserved): 3'b000 - MAIN_PLL2_HSDIV5_CLKOUT 3'b001 - MAIN_PLL0_HSDIV6_CLKOUT 3'b010 - CP_GEMAC_CPTS0_RFT_CLK (Pin).." "0,1,2,3,4,5,6,7" group.long 0x8160++0x3 line.long 0x0 "CFG0_EMMC0_CLKSEL" bitfld.long 0x0 16. "EMMC0_CLKSEL_EMMCSD_IO_CLKLB_SEL,Selects IO Pad Loopback for the MMC Module Field values (others are reserved): 1'b0 - Loopback from Unbonded Pad MMCSD0_CLKLB 1'b1 - Loopback from IO Pin MMCSD0_CLK" "0,1" newline bitfld.long 0x0 0. "EMMC0_CLKSEL_EMMCSD_REFCLK_SEL,Selects the functional clock for the MMC Module Field values (others are reserved): 1'b0 - MAIN_PLL0_HSDIV5_CLKOUT 1'b1 - MAIN_PLL2_HSDIV2_CLKOUT" "0,1" group.long 0x8168++0x7 line.long 0x0 "CFG0_EMMC1_CLKSEL" bitfld.long 0x0 16. "EMMC1_CLKSEL_EMMCSD_IO_CLKLB_SEL,Selects IO Pad Loopback for the MMC Module Field values (others are reserved): 1'b0 - Loopback from Unbonded Pad MMCSD1_CLKLB 1'b1 - Loopback from IO Pin MMCSD1_CLK" "0,1" newline bitfld.long 0x0 0. "EMMC1_CLKSEL_EMMCSD_REFCLK_SEL,Selects the functional clock for the MMC Module Field values (others are reserved): 1'b0 - MAIN_PLL0_HSDIV5_CLKOUT 1'b1 - MAIN_PLL2_HSDIV2_CLKOUT" "0,1" line.long 0x4 "CFG0_EMMC2_CLKSEL" bitfld.long 0x4 16. "EMMC2_CLKSEL_EMMCSD_IO_CLKLB_SEL,Selects IO Pad Loopback for the MMC Module Field values (others are reserved): 1'b0 - Loopback from Unbonded Pad MMCSD2_CLKLB 1'b1 - Loopback from IO Pin MMCSD2_CLK" "0,1" newline bitfld.long 0x4 0. "EMMC2_CLKSEL_EMMCSD_REFCLK_SEL,Selects the functional clock for the MMC Module Field values (others are reserved): 1'b0 - MAIN_PLL0_HSDIV5_CLKOUT 1'b1 - MAIN_PLL2_HSDIV2_CLKOUT" "0,1" group.long 0x8180++0x3 line.long 0x0 "CFG0_GPMC_CLKSEL" bitfld.long 0x0 0. "GPMC_CLKSEL_CLK_SEL,Selects the GPMC clock source: Field values (others are reserved): 1'b0 - MAIN_PLL0_HSDIV3_CLKOUT 1'b1 - MAIN_PLL2_HSDIV7_CLKOUT" "0,1" group.long 0x81B0++0x1F line.long 0x0 "CFG0_TIMER0_CLKSEL" hexmask.long.byte 0x0 0.--3. 1. "TIMER0_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 - CLK_12M_RC.." line.long 0x4 "CFG0_TIMER1_CLKSEL" hexmask.long.byte 0x4 0.--3. 1. "TIMER1_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 - CLK_12M_RC.." line.long 0x8 "CFG0_TIMER2_CLKSEL" hexmask.long.byte 0x8 0.--3. 1. "TIMER2_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 - CLK_12M_RC.." line.long 0xC "CFG0_TIMER3_CLKSEL" hexmask.long.byte 0xC 0.--3. 1. "TIMER3_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 - CLK_12M_RC.." line.long 0x10 "CFG0_TIMER4_CLKSEL" hexmask.long.byte 0x10 0.--3. 1. "TIMER4_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 - CLK_12M_RC.." line.long 0x14 "CFG0_TIMER5_CLKSEL" hexmask.long.byte 0x14 0.--3. 1. "TIMER5_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 - CLK_12M_RC.." line.long 0x18 "CFG0_TIMER6_CLKSEL" hexmask.long.byte 0x18 0.--3. 1. "TIMER6_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 - CLK_12M_RC.." line.long 0x1C "CFG0_TIMER7_CLKSEL" hexmask.long.byte 0x1C 0.--3. 1. "TIMER7_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 - CLK_12M_RC.." group.long 0x8200++0xB line.long 0x0 "CFG0_SPI0_CLKSEL" bitfld.long 0x0 16. "SPI0_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection Field values (others are reserved): 1'b0 - Internal Loopback 1'b1 - External Loopback" "0,1" line.long 0x4 "CFG0_SPI1_CLKSEL" bitfld.long 0x4 16. "SPI1_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection Field values (others are reserved): 1'b0 - Internal Loopback 1'b1 - External Loopback" "0,1" line.long 0x8 "CFG0_SPI2_CLKSEL" bitfld.long 0x8 16. "SPI2_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection Field values (others are reserved): 1'b0 - Internal Loopback 1'b1 - External Loopback" "0,1" group.long 0x8240++0x1B line.long 0x0 "CFG0_USART0_CLK_CTRL" bitfld.long 0x0 16. "USART0_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART0 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0x0 0.--1. "USART0_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (others are reserved): 2'b00 - Divide by 1 2'b01 -.." "0,1,2,3" line.long 0x4 "CFG0_USART1_CLK_CTRL" bitfld.long 0x4 16. "USART1_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART1 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0x4 0.--1. "USART1_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (others are reserved): 2'b00 - Divide by 1 2'b01 -.." "0,1,2,3" line.long 0x8 "CFG0_USART2_CLK_CTRL" bitfld.long 0x8 16. "USART2_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART2 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0x8 0.--1. "USART2_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (others are reserved): 2'b00 - Divide by 1 2'b01 -.." "0,1,2,3" line.long 0xC "CFG0_USART3_CLK_CTRL" bitfld.long 0xC 16. "USART3_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART3 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0xC 0.--1. "USART3_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (others are reserved): 2'b00 - Divide by 1 2'b01 -.." "0,1,2,3" line.long 0x10 "CFG0_USART4_CLK_CTRL" bitfld.long 0x10 16. "USART4_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART4 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0x10 0.--1. "USART4_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (others are reserved): 2'b00 - Divide by 1 2'b01 -.." "0,1,2,3" line.long 0x14 "CFG0_USART5_CLK_CTRL" bitfld.long 0x14 16. "USART5_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART5 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0x14 0.--1. "USART5_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (others are reserved): 2'b00 - Divide by 1 2'b01 -.." "0,1,2,3" line.long 0x18 "CFG0_USART6_CLK_CTRL" bitfld.long 0x18 16. "USART6_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART6 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value.." "0,1" newline bitfld.long 0x18 0.--1. "USART6_CLK_CTRL_CLK_DIV,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (others are reserved): 2'b00 - Divide by 1 2'b01 -.." "0,1,2,3" group.long 0x8280++0x1B line.long 0x0 "CFG0_USART0_CLKSEL" bitfld.long 0x0 0. "USART0_CLKSEL_CLK_SEL,Selects the clock source for UART0: Field values (others are reserved): 1'b0 - MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See USART0_CLK_CTRL) 1'b1 - MAIN_PLL1_HSDIV1_CLKOUT" "0,1" line.long 0x4 "CFG0_USART1_CLKSEL" bitfld.long 0x4 0. "USART1_CLKSEL_CLK_SEL,Selects the clock source for UART1: Field values (others are reserved): 1'b0 - MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See USART1_CLK_CTRL) 1'b1 - MAIN_PLL1_HSDIV1_CLKOUT" "0,1" line.long 0x8 "CFG0_USART2_CLKSEL" bitfld.long 0x8 0. "USART2_CLKSEL_CLK_SEL,Selects the clock source for UART2: Field values (others are reserved): 1'b0 - MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See USART2_CLK_CTRL) 1'b1 - MAIN_PLL1_HSDIV1_CLKOUT" "0,1" line.long 0xC "CFG0_USART3_CLKSEL" bitfld.long 0xC 0. "USART3_CLKSEL_CLK_SEL,Selects the clock source for UART3: Field values (others are reserved): 1'b0 - MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See USART3_CLK_CTRL) 1'b1 - MAIN_PLL1_HSDIV1_CLKOUT" "0,1" line.long 0x10 "CFG0_USART4_CLKSEL" bitfld.long 0x10 0. "USART4_CLKSEL_CLK_SEL,Selects the clock source for UART4: Field values (others are reserved): 1'b0 - MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See USART4_CLK_CTRL) 1'b1 - MAIN_PLL1_HSDIV1_CLKOUT" "0,1" line.long 0x14 "CFG0_USART5_CLKSEL" bitfld.long 0x14 0. "USART5_CLKSEL_CLK_SEL,Selects the clock source for UART5: Field values (others are reserved): 1'b0 - MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See USART5_CLK_CTRL) 1'b1 - MAIN_PLL1_HSDIV1_CLKOUT" "0,1" line.long 0x18 "CFG0_USART6_CLKSEL" bitfld.long 0x18 0. "USART6_CLKSEL_CLK_SEL,Selects the clock source for UART6: Field values (others are reserved): 1'b0 - MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See USART6_CLK_CTRL) 1'b1 - MAIN_PLL1_HSDIV1_CLKOUT" "0,1" group.long 0x82E0++0x7 line.long 0x0 "CFG0_AUDIO_REFCLK0_CTRL" bitfld.long 0x0 15. "AUDIO_REFCLK0_CTRL_CLKOUT_EN,AUDIO_REFCLK 0 output activate Field values (others are reserved): 1'b0 - Input Clock 1'b1 - Output Clock" "0,1" newline bitfld.long 0x0 0.--2. "AUDIO_REFCLK0_CTRL_CLK_SEL,Selects the source of AUDIO_REFCLK0 Field values (others are reserved): 3'b000 - MCASP0_AHCLKR 3'b001 - MCASP1_AHCLKR 3'b010 - MCASP2_AHCLKR 3'b011 - MCASP0_AHCLKX 3'b100 - MCASP1_AHCLKX 3'b101 - MCASP2_AHCLKX 3'b110 -.." "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_AUDIO_REFCLK1_CTRL" bitfld.long 0x4 15. "AUDIO_REFCLK1_CTRL_CLKOUT_EN,AUDIO_REFCLK 1 output activate Field values (others are reserved): 1'b0 - Input Clock 1'b1 - Output Clock" "0,1" newline bitfld.long 0x4 0.--2. "AUDIO_REFCLK1_CTRL_CLK_SEL,Selects the source of AUDIO_REFCLK1 Field values (others are reserved): 3'b000 - MCASP0_AHCLKR 3'b001 - MCASP1_AHCLKR 3'b010 - MCASP2_AHCLKR 3'b011 - MCASP0_AHCLKX 3'b100 - MCASP1_AHCLKX 3'b101 - MCASP2_AHCLKX 3'b110 -.." "0,1,2,3,4,5,6,7" group.long 0x8300++0x3 line.long 0x0 "CFG0_DPI0_CLK_CTRL" bitfld.long 0x0 9. "DPI0_CLK_CTRL_SYNC_CLK_INVDIS,Clock edge select for DPI0 sync outputs 0 - HSYNC and VSYNC are driven on the falling edge of clk 1 - HSYNC and VSYNC are driven on the rising edge of clk Note that this value should align with the programmed value of the.." "0,1" newline bitfld.long 0x0 8. "DPI0_CLK_CTRL_DATA_CLK_INVDIS,Clock edge select for DPI0 data outputs 0 - DATA and DE are driven on the falling edge of clk 1 - DATA and DE are driven on the rising edge of clk Note that this value should align with the programmed valueof the DSS.." "0,1" group.long 0x8320++0x3 line.long 0x0 "CFG0_DSS_DISPC0_CLKSEL1" bitfld.long 0x0 0. "DSS_DISPC0_CLKSEL1_DPI_PCLK,DPI pixel Clock Source Field values (others are reserved): 1'b0 - MAIN_PLL17_HSDIV0_CLKOUT 1'b1 - VOUT0_EXTPCLKIN" "0,1" group.long 0x8330++0xB line.long 0x0 "CFG0_MCASP0_CLKSEL" bitfld.long 0x0 0. "MCASP0_CLKSEL_AUXCLK_SEL,Selects the AUXCLK input source for McASP0 Field values (others are reserved): 1'b0 - MAIN_PLL2_HSDIV8_CLKOUT 1'b1 - MAIN_PLL1_HSDIV6_CLKOUT" "0,1" line.long 0x4 "CFG0_MCASP1_CLKSEL" bitfld.long 0x4 0. "MCASP1_CLKSEL_AUXCLK_SEL,Selects the AUXCLK input source for McASP0 Field values (others are reserved): 1'b0 - MAIN_PLL2_HSDIV8_CLKOUT 1'b1 - MAIN_PLL1_HSDIV6_CLKOUT" "0,1" line.long 0x8 "CFG0_MCASP2_CLKSEL" bitfld.long 0x8 0. "MCASP2_CLKSEL_AUXCLK_SEL,Selects the AUXCLK input source for McASP0 Field values (others are reserved): 1'b0 - MAIN_PLL2_HSDIV8_CLKOUT 1'b1 - MAIN_PLL1_HSDIV6_CLKOUT" "0,1" group.long 0x8350++0xB line.long 0x0 "CFG0_MCASP0_AHCLKSEL" bitfld.long 0x0 8.--9. "MCASP0_AHCLKSEL_AHCLKX_SEL,Selects the AHCLKX input source for McASP0 Field values (others are reserved): 2'b00 - EXT_REFCLK1 (pin) 2'b01 - HFOSC0_CLKOUT 2'b10 - AUDIO_EXT_REFCLK0_IN 2'b11 - AUDIO_EXT_REFCLK1_IN" "0,1,2,3" newline bitfld.long 0x0 0.--1. "MCASP0_AHCLKSEL_AHCLKR_SEL,Selects the AHCLKR input source for McASP0 Field values (others are reserved): 2'b00 - EXT_REFCLK1 (pin) 2'b01 - HFOSC0_CLKOUT 2'b10 - AUDIO_EXT_REFCLK0_IN 2'b11 - AUDIO_EXT_REFCLK1_IN" "0,1,2,3" line.long 0x4 "CFG0_MCASP1_AHCLKSEL" bitfld.long 0x4 8.--9. "MCASP1_AHCLKSEL_AHCLKX_SEL,Selects the AHCLKX input source for McASP1 Field values (others are reserved): 2'b00 - EXT_REFCLK1 (pin) 2'b01 - HFOSC0_CLKOUT 2'b10 - AUDIO_EXT_REFCLK0_IN 2'b11 - AUDIO_EXT_REFCLK1_IN" "0,1,2,3" newline bitfld.long 0x4 0.--1. "MCASP1_AHCLKSEL_AHCLKR_SEL,Selects the AHCLKR input source for McASP1 Field values (others are reserved): 2'b00 - EXT_REFCLK1 (pin) 2'b01 - HFOSC0_CLKOUT 2'b10 - AUDIO_EXT_REFCLK0_IN 2'b11 - AUDIO_EXT_REFCLK1_IN" "0,1,2,3" line.long 0x8 "CFG0_MCASP2_AHCLKSEL" bitfld.long 0x8 8.--9. "MCASP2_AHCLKSEL_AHCLKX_SEL,Selects the AHCLKX input source for McASP2 Field values (others are reserved): 2'b00 - EXT_REFCLK1 (pin) 2'b01 - HFOSC0_CLKOUT 2'b10 - AUDIO_EXT_REFCLK0_IN 2'b11 - AUDIO_EXT_REFCLK1_IN" "0,1,2,3" newline bitfld.long 0x8 0.--1. "MCASP2_AHCLKSEL_AHCLKR_SEL,Selects the AHCLKR input source for McASP2 Field values (others are reserved): 2'b00 - EXT_REFCLK1 (pin) 2'b01 - HFOSC0_CLKOUT 2'b10 - AUDIO_EXT_REFCLK0_IN 2'b11 - AUDIO_EXT_REFCLK1_IN" "0,1,2,3" group.long 0x8380++0x13 line.long 0x0 "CFG0_WWD0_CLKSEL" bitfld.long 0x0 31. "WWD0_CLKSEL_WRTLOCK,When set locks WWD0_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x0 0.--1. "WWD0_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - DEVICE_CLKOUT_32K 2'b10 - CLK_12M_RC 2'b11 - CLK_32K" "0,1,2,3" line.long 0x4 "CFG0_WWD1_CLKSEL" bitfld.long 0x4 31. "WWD1_CLKSEL_WRTLOCK,When set locks WWD1_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x4 0.--1. "WWD1_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - DEVICE_CLKOUT_32K 2'b10 - CLK_12M_RC 2'b11 - CLK_32K" "0,1,2,3" line.long 0x8 "CFG0_WWD2_CLKSEL" bitfld.long 0x8 31. "WWD2_CLKSEL_WRTLOCK,When set locks WWD2_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x8 0.--1. "WWD2_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - DEVICE_CLKOUT_32K 2'b10 - CLK_12M_RC 2'b11 - CLK_32K" "0,1,2,3" line.long 0xC "CFG0_WWD3_CLKSEL" bitfld.long 0xC 31. "WWD3_CLKSEL_WRTLOCK,When set locks WWD3_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0xC 0.--1. "WWD3_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - DEVICE_CLKOUT_32K 2'b10 - CLK_12M_RC 2'b11 - CLK_32K" "0,1,2,3" line.long 0x10 "CFG0_WWD4_CLKSEL" bitfld.long 0x10 31. "WWD4_CLKSEL_WRTLOCK,When set locks WWD4_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x10 0.--1. "WWD4_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - DEVICE_CLKOUT_32K 2'b10 - CLK_12M_RC 2'b11 - CLK_32K" "0,1,2,3" group.long 0x8480++0x3 line.long 0x0 "CFG0_MCAN0_CLKSEL" bitfld.long 0x0 0.--1. "MCAN0_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection Field values (others are reserved): 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 2'b10 - EXT_REFCLK1 (pin) 2'b11 - HFOSC0_CLKOUT" "0,1,2,3" group.long 0x8500++0x3 line.long 0x0 "CFG0_OSPI0_CLKSEL" bitfld.long 0x0 4. "OSPI0_CLKSEL_LOOPCLK_SEL,OBSPI0 Loopback clock source Field values (others are reserved): 1'b0 - Board Level Loopback 1'b1 - Internal Loopback" "0,1" newline bitfld.long 0x0 0. "OSPI0_CLKSEL_CLK_SEL,OSPI0 reference clock selection Field values (others are reserved): 1'b0 - MAIN_PLL0_HSDIV1_CLKOUT 1'b1 - MAIN_PLL1_HSDIV5_CLKOUT" "0,1" group.long 0x9008++0x7 line.long 0x0 "CFG0_LOCK2_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK2_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK2_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK2_KICK1,- KICK1 component" rgroup.long 0x9100++0x2B line.long 0x0 "CFG0_CLAIMREG_P2_R0_READONLY" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P2_R0_READONLY,Claim bits for Partition 2" line.long 0x4 "CFG0_CLAIMREG_P2_R1_READONLY" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P2_R1_READONLY,Claim bits for Partition 2" line.long 0x8 "CFG0_CLAIMREG_P2_R2_READONLY" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P2_R2_READONLY,Claim bits for Partition 2" line.long 0xC "CFG0_CLAIMREG_P2_R3_READONLY" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P2_R3_READONLY,Claim bits for Partition 2" line.long 0x10 "CFG0_CLAIMREG_P2_R4_READONLY" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P2_R4_READONLY,Claim bits for Partition 2" line.long 0x14 "CFG0_CLAIMREG_P2_R5_READONLY" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P2_R5_READONLY,Claim bits for Partition 2" line.long 0x18 "CFG0_CLAIMREG_P2_R6_READONLY" hexmask.long 0x18 0.--31. 1. "CLAIMREG_P2_R6_READONLY,Claim bits for Partition 2" line.long 0x1C "CFG0_CLAIMREG_P2_R7_READONLY" hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P2_R7_READONLY,Claim bits for Partition 2" line.long 0x20 "CFG0_CLAIMREG_P2_R8_READONLY" hexmask.long 0x20 0.--31. 1. "CLAIMREG_P2_R8_READONLY,Claim bits for Partition 2" line.long 0x24 "CFG0_CLAIMREG_P2_R9_READONLY" hexmask.long 0x24 0.--31. 1. "CLAIMREG_P2_R9_READONLY,Claim bits for Partition 2" line.long 0x28 "CFG0_CLAIMREG_P2_R10_READONLY" hexmask.long 0x28 0.--31. 1. "CLAIMREG_P2_R10_READONLY,Claim bits for Partition 2" group.long 0xA000++0x3 line.long 0x0 "CFG0_OBSCLK0_CTRL_PROXY" bitfld.long 0x0 24. "OBSCLK0_CTRL_OUT_MUX_SEL_PROXY,OBSCLK pin output mux selection. Note HFOSC0_CLK is a direct output from the HFOSC0 distinct from HFOSC0_CLKOUT. Note when HFOSC0_CLK is selected (1'b1) the MCU_OBSCLK_CTRL_clk_sel field must be programmed to.." "0,1" newline bitfld.long 0x0 16. "OBSCLK0_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the OBSCLK0 divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "OBSCLK0_CTRL_CLK_DIV_PROXY,OBSCLK0 output divider Divides the selected clock by clkdiv+1 for output to the OBSCLK0 pins. Supports divide by 1 to 256 (default to 1). To load the new divider value the clk_div_ld bit must be cleared and then set to 1." newline hexmask.long.byte 0x0 0.--4. 1. "OBSCLK0_CTRL_CLK_SEL_PROXY,OBSCLK0 clock source selection. Selects the source of the clock to be divided by the OBSCLK0 divider and output on the OBSCLK0 pin. Field values (others are reserved): 5'b00000 - MAIN_PLL0_HSDIV0_CLKOUT 5'b00001 -.." group.long 0xA010++0x3 line.long 0x0 "CFG0_CLKOUT_CTRL_PROXY" bitfld.long 0x0 0. "CLKOUT_CTRL_CLK_SEL_PROXY,Selects CLKOUT clock source Field values (others are reserved): 1'b0 - MAIN_PLL2_HSDIV1_CLKOUT / 5 1'b1 - MAIN_PLL2_HSDIV1_CLKOUT / 10" "0,1" group.long 0xA060++0xB line.long 0x0 "CFG0_MAIN_PLL0_CLKSEL_PROXY" bitfld.long 0x0 31. "MAIN_PLL0_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL0. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL0_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to activate bypass software override. This bit is set (1'b0) when a MAIN warm reset occurs to keep MAIN PLL0 from being.." "0: Exit bypass mode,1: Maintain bypass mode" line.long 0x4 "CFG0_MAIN_PLL1_CLKSEL_PROXY" bitfld.long 0x4 31. "MAIN_PLL1_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL1 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x4 23. "MAIN_PLL1_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL1 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behaviot." "0,1" line.long 0x8 "CFG0_MAIN_PLL2_CLKSEL_PROXY" bitfld.long 0x8 31. "MAIN_PLL2_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL2 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x8 23. "MAIN_PLL2_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL2 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behaviot." "0,1" group.long 0xA074++0x3 line.long 0x0 "CFG0_MAIN_PLL5_CLKSEL_PROXY" bitfld.long 0x0 31. "MAIN_PLL5_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL5. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL5_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to activate bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL5 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" group.long 0xA07C++0x7 line.long 0x0 "CFG0_MAIN_PLL7_CLKSEL_PROXY" bitfld.long 0x0 31. "MAIN_PLL7_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL7. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL7_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to activate bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL7 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" line.long 0x4 "CFG0_MAIN_PLL8_CLKSEL_PROXY" bitfld.long 0x4 31. "MAIN_PLL8_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL8. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x4 23. "MAIN_PLL8_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to activate bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL8 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" group.long 0xA090++0x3 line.long 0x0 "CFG0_MAIN_PLL12_CLKSEL_PROXY" bitfld.long 0x0 31. "MAIN_PLL12_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL12. This bit must not be set until after the corresponding byp_warm_rst bit has.." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL12_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to activate bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL12 in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" group.long 0xA0A4++0x3 line.long 0x0 "CFG0_MAIN_PLL17_CLKSEL_PROXY" bitfld.long 0x0 31. "MAIN_PLL17_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL17 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled." "0,1" newline bitfld.long 0x0 23. "MAIN_PLL17_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL17 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behaviot." "0,1" group.long 0xA140++0x3 line.long 0x0 "CFG0_CPSW_CLKSEL_PROXY" bitfld.long 0x0 0.--2. "CPSW_CLKSEL_CPTS_CLKSEL_PROXY,Selects the clock source for the CPSW Ethernet switch Common Platform Time Stamp module Field values (others are reserved): 3'b000 - MAIN_PLL2_HSDIV5_CLKOUT 3'b001 - MAIN_PLL0_HSDIV6_CLKOUT 3'b010 - CP_GEMAC_CPTS0_RFT_CLK.." "0,1,2,3,4,5,6,7" group.long 0xA160++0x3 line.long 0x0 "CFG0_EMMC0_CLKSEL_PROXY" bitfld.long 0x0 16. "EMMC0_CLKSEL_EMMCSD_IO_CLKLB_SEL_PROXY,Selects IO Pad Loopback for the MMC Module Field values (others are reserved): 1'b0 - Loopback from Unbonded Pad MMCSD0_CLKLB 1'b1 - Loopback from IO Pin MMCSD0_CLK" "0,1" newline bitfld.long 0x0 0. "EMMC0_CLKSEL_EMMCSD_REFCLK_SEL_PROXY,Selects the functional clock for the MMC Module Field values (others are reserved): 1'b0 - MAIN_PLL0_HSDIV5_CLKOUT 1'b1 - MAIN_PLL2_HSDIV2_CLKOUT" "0,1" group.long 0xA168++0x7 line.long 0x0 "CFG0_EMMC1_CLKSEL_PROXY" bitfld.long 0x0 16. "EMMC1_CLKSEL_EMMCSD_IO_CLKLB_SEL_PROXY,Selects IO Pad Loopback for the MMC Module Field values (others are reserved): 1'b0 - Loopback from Unbonded Pad MMCSD1_CLKLB 1'b1 - Loopback from IO Pin MMCSD1_CLK" "0,1" newline bitfld.long 0x0 0. "EMMC1_CLKSEL_EMMCSD_REFCLK_SEL_PROXY,Selects the functional clock for the MMC Module Field values (others are reserved): 1'b0 - MAIN_PLL0_HSDIV5_CLKOUT 1'b1 - MAIN_PLL2_HSDIV2_CLKOUT" "0,1" line.long 0x4 "CFG0_EMMC2_CLKSEL_PROXY" bitfld.long 0x4 16. "EMMC2_CLKSEL_EMMCSD_IO_CLKLB_SEL_PROXY,Selects IO Pad Loopback for the MMC Module Field values (others are reserved): 1'b0 - Loopback from Unbonded Pad MMCSD2_CLKLB 1'b1 - Loopback from IO Pin MMCSD2_CLK" "0,1" newline bitfld.long 0x4 0. "EMMC2_CLKSEL_EMMCSD_REFCLK_SEL_PROXY,Selects the functional clock for the MMC Module Field values (others are reserved): 1'b0 - MAIN_PLL0_HSDIV5_CLKOUT 1'b1 - MAIN_PLL2_HSDIV2_CLKOUT" "0,1" group.long 0xA180++0x3 line.long 0x0 "CFG0_GPMC_CLKSEL_PROXY" bitfld.long 0x0 0. "GPMC_CLKSEL_CLK_SEL_PROXY,Selects the GPMC clock source: Field values (others are reserved): 1'b0 - MAIN_PLL0_HSDIV3_CLKOUT 1'b1 - MAIN_PLL2_HSDIV7_CLKOUT" "0,1" group.long 0xA1B0++0x1F line.long 0x0 "CFG0_TIMER0_CLKSEL_PROXY" hexmask.long.byte 0x0 0.--3. 1. "TIMER0_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 -.." line.long 0x4 "CFG0_TIMER1_CLKSEL_PROXY" hexmask.long.byte 0x4 0.--3. 1. "TIMER1_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 -.." line.long 0x8 "CFG0_TIMER2_CLKSEL_PROXY" hexmask.long.byte 0x8 0.--3. 1. "TIMER2_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 -.." line.long 0xC "CFG0_TIMER3_CLKSEL_PROXY" hexmask.long.byte 0xC 0.--3. 1. "TIMER3_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 -.." line.long 0x10 "CFG0_TIMER4_CLKSEL_PROXY" hexmask.long.byte 0x10 0.--3. 1. "TIMER4_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 -.." line.long 0x14 "CFG0_TIMER5_CLKSEL_PROXY" hexmask.long.byte 0x14 0.--3. 1. "TIMER5_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 -.." line.long 0x18 "CFG0_TIMER6_CLKSEL_PROXY" hexmask.long.byte 0x18 0.--3. 1. "TIMER6_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 -.." line.long 0x1C "CFG0_TIMER7_CLKSEL_PROXY" hexmask.long.byte 0x1C 0.--3. 1. "TIMER7_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 4'b0000 - HFOSC0_CLKOUT 4'b0001 - DEVICE_CLKOUT_32K 4'b0010 - MAIN_PLL0_HSDIV7_CLKOUT 4'b0011 -.." group.long 0xA200++0xB line.long 0x0 "CFG0_SPI0_CLKSEL_PROXY" bitfld.long 0x0 16. "SPI0_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection Field values (others are reserved): 1'b0 - Internal Loopback 1'b1 - External Loopback" "0,1" line.long 0x4 "CFG0_SPI1_CLKSEL_PROXY" bitfld.long 0x4 16. "SPI1_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection Field values (others are reserved): 1'b0 - Internal Loopback 1'b1 - External Loopback" "0,1" line.long 0x8 "CFG0_SPI2_CLKSEL_PROXY" bitfld.long 0x8 16. "SPI2_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection Field values (others are reserved): 1'b0 - Internal Loopback 1'b1 - External Loopback" "0,1" group.long 0xA240++0x1B line.long 0x0 "CFG0_USART0_CLK_CTRL_PROXY" bitfld.long 0x0 16. "USART0_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART0 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0x0 0.--1. "USART0_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (others are reserved): 2'b00 - Divide by 1.." "0,1,2,3" line.long 0x4 "CFG0_USART1_CLK_CTRL_PROXY" bitfld.long 0x4 16. "USART1_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART1 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0x4 0.--1. "USART1_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (others are reserved): 2'b00 - Divide by 1.." "0,1,2,3" line.long 0x8 "CFG0_USART2_CLK_CTRL_PROXY" bitfld.long 0x8 16. "USART2_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART2 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0x8 0.--1. "USART2_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (others are reserved): 2'b00 - Divide by 1.." "0,1,2,3" line.long 0xC "CFG0_USART3_CLK_CTRL_PROXY" bitfld.long 0xC 16. "USART3_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART3 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0xC 0.--1. "USART3_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (others are reserved): 2'b00 - Divide by 1.." "0,1,2,3" line.long 0x10 "CFG0_USART4_CLK_CTRL_PROXY" bitfld.long 0x10 16. "USART4_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART4 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0x10 0.--1. "USART4_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (others are reserved): 2'b00 - Divide by 1.." "0,1,2,3" line.long 0x14 "CFG0_USART5_CLK_CTRL_PROXY" bitfld.long 0x14 16. "USART5_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART5 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0x14 0.--1. "USART5_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (others are reserved): 2'b00 - Divide by 1.." "0,1,2,3" line.long 0x18 "CFG0_USART6_CLK_CTRL_PROXY" bitfld.long 0x18 16. "USART6_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART6 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div.." "0,1" newline bitfld.long 0x18 0.--1. "USART6_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. Field values (others are reserved): 2'b00 - Divide by 1.." "0,1,2,3" group.long 0xA280++0x1B line.long 0x0 "CFG0_USART0_CLKSEL_PROXY" bitfld.long 0x0 0. "USART0_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART0: Field values (others are reserved): 1'b0 - MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See USART0_CLK_CTRL) 1'b1 - MAIN_PLL1_HSDIV1_CLKOUT" "0,1" line.long 0x4 "CFG0_USART1_CLKSEL_PROXY" bitfld.long 0x4 0. "USART1_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART1: Field values (others are reserved): 1'b0 - MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See USART1_CLK_CTRL) 1'b1 - MAIN_PLL1_HSDIV1_CLKOUT" "0,1" line.long 0x8 "CFG0_USART2_CLKSEL_PROXY" bitfld.long 0x8 0. "USART2_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART2: Field values (others are reserved): 1'b0 - MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See USART2_CLK_CTRL) 1'b1 - MAIN_PLL1_HSDIV1_CLKOUT" "0,1" line.long 0xC "CFG0_USART3_CLKSEL_PROXY" bitfld.long 0xC 0. "USART3_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART3: Field values (others are reserved): 1'b0 - MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See USART3_CLK_CTRL) 1'b1 - MAIN_PLL1_HSDIV1_CLKOUT" "0,1" line.long 0x10 "CFG0_USART4_CLKSEL_PROXY" bitfld.long 0x10 0. "USART4_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART4: Field values (others are reserved): 1'b0 - MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See USART4_CLK_CTRL) 1'b1 - MAIN_PLL1_HSDIV1_CLKOUT" "0,1" line.long 0x14 "CFG0_USART5_CLKSEL_PROXY" bitfld.long 0x14 0. "USART5_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART5: Field values (others are reserved): 1'b0 - MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See USART5_CLK_CTRL) 1'b1 - MAIN_PLL1_HSDIV1_CLKOUT" "0,1" line.long 0x18 "CFG0_USART6_CLKSEL_PROXY" bitfld.long 0x18 0. "USART6_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART6: Field values (others are reserved): 1'b0 - MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See USART6_CLK_CTRL) 1'b1 - MAIN_PLL1_HSDIV1_CLKOUT" "0,1" group.long 0xA2E0++0x7 line.long 0x0 "CFG0_AUDIO_REFCLK0_CTRL_PROXY" bitfld.long 0x0 15. "AUDIO_REFCLK0_CTRL_CLKOUT_EN_PROXY,AUDIO_REFCLK 0 output activate Field values (others are reserved): 1'b0 - Input Clock 1'b1 - Output Clock" "0,1" newline bitfld.long 0x0 0.--2. "AUDIO_REFCLK0_CTRL_CLK_SEL_PROXY,Selects the source of AUDIO_REFCLK0 Field values (others are reserved): 3'b000 - MCASP0_AHCLKR 3'b001 - MCASP1_AHCLKR 3'b010 - MCASP2_AHCLKR 3'b011 - MCASP0_AHCLKX 3'b100 - MCASP1_AHCLKX 3'b101 - MCASP2_AHCLKX 3'b110 -.." "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_AUDIO_REFCLK1_CTRL_PROXY" bitfld.long 0x4 15. "AUDIO_REFCLK1_CTRL_CLKOUT_EN_PROXY,AUDIO_REFCLK 1 output activate Field values (others are reserved): 1'b0 - Input Clock 1'b1 - Output Clock" "0,1" newline bitfld.long 0x4 0.--2. "AUDIO_REFCLK1_CTRL_CLK_SEL_PROXY,Selects the source of AUDIO_REFCLK1 Field values (others are reserved): 3'b000 - MCASP0_AHCLKR 3'b001 - MCASP1_AHCLKR 3'b010 - MCASP2_AHCLKR 3'b011 - MCASP0_AHCLKX 3'b100 - MCASP1_AHCLKX 3'b101 - MCASP2_AHCLKX 3'b110 -.." "0,1,2,3,4,5,6,7" group.long 0xA300++0x3 line.long 0x0 "CFG0_DPI0_CLK_CTRL_PROXY" bitfld.long 0x0 9. "DPI0_CLK_CTRL_SYNC_CLK_INVDIS_PROXY,Clock edge select for DPI0 sync outputs 0 - HSYNC and VSYNC are driven on the falling edge of clk 1 - HSYNC and VSYNC are driven on the rising edge of clk Note that this value should align with the programmed value of.." "0,1" newline bitfld.long 0x0 8. "DPI0_CLK_CTRL_DATA_CLK_INVDIS_PROXY,Clock edge select for DPI0 data outputs 0 - DATA and DE are driven on the falling edge of clk 1 - DATA and DE are driven on the rising edge of clk Note that this value should align with the programmed valueof the DSS.." "0,1" group.long 0xA320++0x3 line.long 0x0 "CFG0_DSS_DISPC0_CLKSEL1_PROXY" bitfld.long 0x0 0. "DSS_DISPC0_CLKSEL1_DPI_PCLK_PROXY,DPI pixel Clock Source Field values (others are reserved): 1'b0 - MAIN_PLL17_HSDIV0_CLKOUT 1'b1 - VOUT0_EXTPCLKIN" "0,1" group.long 0xA330++0xB line.long 0x0 "CFG0_MCASP0_CLKSEL_PROXY" bitfld.long 0x0 0. "MCASP0_CLKSEL_AUXCLK_SEL_PROXY,Selects the AUXCLK input source for McASP0 Field values (others are reserved): 1'b0 - MAIN_PLL2_HSDIV8_CLKOUT 1'b1 - MAIN_PLL1_HSDIV6_CLKOUT" "0,1" line.long 0x4 "CFG0_MCASP1_CLKSEL_PROXY" bitfld.long 0x4 0. "MCASP1_CLKSEL_AUXCLK_SEL_PROXY,Selects the AUXCLK input source for McASP0 Field values (others are reserved): 1'b0 - MAIN_PLL2_HSDIV8_CLKOUT 1'b1 - MAIN_PLL1_HSDIV6_CLKOUT" "0,1" line.long 0x8 "CFG0_MCASP2_CLKSEL_PROXY" bitfld.long 0x8 0. "MCASP2_CLKSEL_AUXCLK_SEL_PROXY,Selects the AUXCLK input source for McASP0 Field values (others are reserved): 1'b0 - MAIN_PLL2_HSDIV8_CLKOUT 1'b1 - MAIN_PLL1_HSDIV6_CLKOUT" "0,1" group.long 0xA350++0xB line.long 0x0 "CFG0_MCASP0_AHCLKSEL_PROXY" bitfld.long 0x0 8.--9. "MCASP0_AHCLKSEL_AHCLKX_SEL_PROXY,Selects the AHCLKX input source for McASP0 Field values (others are reserved): 2'b00 - EXT_REFCLK1 (pin) 2'b01 - HFOSC0_CLKOUT 2'b10 - AUDIO_EXT_REFCLK0_IN 2'b11 - AUDIO_EXT_REFCLK1_IN" "0,1,2,3" newline bitfld.long 0x0 0.--1. "MCASP0_AHCLKSEL_AHCLKR_SEL_PROXY,Selects the AHCLKR input source for McASP0 Field values (others are reserved): 2'b00 - EXT_REFCLK1 (pin) 2'b01 - HFOSC0_CLKOUT 2'b10 - AUDIO_EXT_REFCLK0_IN 2'b11 - AUDIO_EXT_REFCLK1_IN" "0,1,2,3" line.long 0x4 "CFG0_MCASP1_AHCLKSEL_PROXY" bitfld.long 0x4 8.--9. "MCASP1_AHCLKSEL_AHCLKX_SEL_PROXY,Selects the AHCLKX input source for McASP1 Field values (others are reserved): 2'b00 - EXT_REFCLK1 (pin) 2'b01 - HFOSC0_CLKOUT 2'b10 - AUDIO_EXT_REFCLK0_IN 2'b11 - AUDIO_EXT_REFCLK1_IN" "0,1,2,3" newline bitfld.long 0x4 0.--1. "MCASP1_AHCLKSEL_AHCLKR_SEL_PROXY,Selects the AHCLKR input source for McASP1 Field values (others are reserved): 2'b00 - EXT_REFCLK1 (pin) 2'b01 - HFOSC0_CLKOUT 2'b10 - AUDIO_EXT_REFCLK0_IN 2'b11 - AUDIO_EXT_REFCLK1_IN" "0,1,2,3" line.long 0x8 "CFG0_MCASP2_AHCLKSEL_PROXY" bitfld.long 0x8 8.--9. "MCASP2_AHCLKSEL_AHCLKX_SEL_PROXY,Selects the AHCLKX input source for McASP2 Field values (others are reserved): 2'b00 - EXT_REFCLK1 (pin) 2'b01 - HFOSC0_CLKOUT 2'b10 - AUDIO_EXT_REFCLK0_IN 2'b11 - AUDIO_EXT_REFCLK1_IN" "0,1,2,3" newline bitfld.long 0x8 0.--1. "MCASP2_AHCLKSEL_AHCLKR_SEL_PROXY,Selects the AHCLKR input source for McASP2 Field values (others are reserved): 2'b00 - EXT_REFCLK1 (pin) 2'b01 - HFOSC0_CLKOUT 2'b10 - AUDIO_EXT_REFCLK0_IN 2'b11 - AUDIO_EXT_REFCLK1_IN" "0,1,2,3" group.long 0xA380++0x13 line.long 0x0 "CFG0_WWD0_CLKSEL_PROXY" bitfld.long 0x0 31. "WWD0_CLKSEL_WRTLOCK_PROXY,When set locks WWD0_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x0 0.--1. "WWD0_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - DEVICE_CLKOUT_32K 2'b10 - CLK_12M_RC 2'b11 - CLK_32K" "0,1,2,3" line.long 0x4 "CFG0_WWD1_CLKSEL_PROXY" bitfld.long 0x4 31. "WWD1_CLKSEL_WRTLOCK_PROXY,When set locks WWD1_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x4 0.--1. "WWD1_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - DEVICE_CLKOUT_32K 2'b10 - CLK_12M_RC 2'b11 - CLK_32K" "0,1,2,3" line.long 0x8 "CFG0_WWD2_CLKSEL_PROXY" bitfld.long 0x8 31. "WWD2_CLKSEL_WRTLOCK_PROXY,When set locks WWD2_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x8 0.--1. "WWD2_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - DEVICE_CLKOUT_32K 2'b10 - CLK_12M_RC 2'b11 - CLK_32K" "0,1,2,3" line.long 0xC "CFG0_WWD3_CLKSEL_PROXY" bitfld.long 0xC 31. "WWD3_CLKSEL_WRTLOCK_PROXY,When set locks WWD3_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0xC 0.--1. "WWD3_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - DEVICE_CLKOUT_32K 2'b10 - CLK_12M_RC 2'b11 - CLK_32K" "0,1,2,3" line.long 0x10 "CFG0_WWD4_CLKSEL_PROXY" bitfld.long 0x10 31. "WWD4_CLKSEL_WRTLOCK_PROXY,When set locks WWD4_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x10 0.--1. "WWD4_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - DEVICE_CLKOUT_32K 2'b10 - CLK_12M_RC 2'b11 - CLK_32K" "0,1,2,3" group.long 0xA480++0x3 line.long 0x0 "CFG0_MCAN0_CLKSEL_PROXY" bitfld.long 0x0 0.--1. "MCAN0_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection Field values (others are reserved): 2'b00 - MAIN_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 2'b10 - EXT_REFCLK1 (pin) 2'b11 - HFOSC0_CLKOUT" "0,1,2,3" group.long 0xA500++0x3 line.long 0x0 "CFG0_OSPI0_CLKSEL_PROXY" bitfld.long 0x0 4. "OSPI0_CLKSEL_LOOPCLK_SEL_PROXY,OBSPI0 Loopback clock source Field values (others are reserved): 1'b0 - Board Level Loopback 1'b1 - Internal Loopback" "0,1" newline bitfld.long 0x0 0. "OSPI0_CLKSEL_CLK_SEL_PROXY,OSPI0 reference clock selection Field values (others are reserved): 1'b0 - MAIN_PLL0_HSDIV1_CLKOUT 1'b1 - MAIN_PLL1_HSDIV5_CLKOUT" "0,1" group.long 0xB008++0x7 line.long 0x0 "CFG0_LOCK2_KICK0_PROXY" hexmask.long 0x0 0.--31. 1. "LOCK2_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK2_KICK1_PROXY" hexmask.long 0x4 0.--31. 1. "LOCK2_KICK1_PROXY,- KICK1 component" group.long 0xB100++0x2B line.long 0x0 "CFG0_CLAIMREG_P2_R0" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P2_R0,Claim bits for Partition 2" line.long 0x4 "CFG0_CLAIMREG_P2_R1" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P2_R1,Claim bits for Partition 2" line.long 0x8 "CFG0_CLAIMREG_P2_R2" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P2_R2,Claim bits for Partition 2" line.long 0xC "CFG0_CLAIMREG_P2_R3" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P2_R3,Claim bits for Partition 2" line.long 0x10 "CFG0_CLAIMREG_P2_R4" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P2_R4,Claim bits for Partition 2" line.long 0x14 "CFG0_CLAIMREG_P2_R5" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P2_R5,Claim bits for Partition 2" line.long 0x18 "CFG0_CLAIMREG_P2_R6" hexmask.long 0x18 0.--31. 1. "CLAIMREG_P2_R6,Claim bits for Partition 2" line.long 0x1C "CFG0_CLAIMREG_P2_R7" hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P2_R7,Claim bits for Partition 2" line.long 0x20 "CFG0_CLAIMREG_P2_R8" hexmask.long 0x20 0.--31. 1. "CLAIMREG_P2_R8,Claim bits for Partition 2" line.long 0x24 "CFG0_CLAIMREG_P2_R9" hexmask.long 0x24 0.--31. 1. "CLAIMREG_P2_R9,Claim bits for Partition 2" line.long 0x28 "CFG0_CLAIMREG_P2_R10" hexmask.long 0x28 0.--31. 1. "CLAIMREG_P2_R10,Claim bits for Partition 2" group.long 0x10500++0x3 line.long 0x0 "CFG0_MAIN_PLL_TEST_CLKSEL" bitfld.long 0x0 17. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL17,Selects the alternate clock source for MAIN PLL17 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" newline bitfld.long 0x0 12. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL12,Selects the alternate clock source for MAIN PLL12 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" newline bitfld.long 0x0 8. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL8,Selects the alternate clock source for MAIN PLL8 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" newline bitfld.long 0x0 7. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL7,Selects the alternate clock source for MAIN PLL7 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" newline bitfld.long 0x0 5. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL5,Selects the alternate clock source for MAIN PLL5 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" newline bitfld.long 0x0 2. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL2,Selects the alternate clock source for MAIN PLL2 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" newline bitfld.long 0x0 1. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL1,Selects the alternate clock source for MAIN PLL1 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" newline bitfld.long 0x0 0. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL0,Selects the alternate clock source for MAIN PLL0 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" group.long 0x11008++0x7 line.long 0x0 "CFG0_LOCK4_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK4_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK4_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK4_KICK1,- KICK1 component" rgroup.long 0x11100++0x2B line.long 0x0 "CFG0_CLAIMREG_P4_R0_READONLY" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P4_R0_READONLY,Claim bits for Partition 4" line.long 0x4 "CFG0_CLAIMREG_P4_R1_READONLY" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P4_R1_READONLY,Claim bits for Partition 4" line.long 0x8 "CFG0_CLAIMREG_P4_R2_READONLY" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P4_R2_READONLY,Claim bits for Partition 4" line.long 0xC "CFG0_CLAIMREG_P4_R3_READONLY" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P4_R3_READONLY,Claim bits for Partition 4" line.long 0x10 "CFG0_CLAIMREG_P4_R4_READONLY" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P4_R4_READONLY,Claim bits for Partition 4" line.long 0x14 "CFG0_CLAIMREG_P4_R5_READONLY" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P4_R5_READONLY,Claim bits for Partition 4" line.long 0x18 "CFG0_CLAIMREG_P4_R6_READONLY" hexmask.long 0x18 0.--31. 1. "CLAIMREG_P4_R6_READONLY,Claim bits for Partition 4" line.long 0x1C "CFG0_CLAIMREG_P4_R7_READONLY" hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P4_R7_READONLY,Claim bits for Partition 4" line.long 0x20 "CFG0_CLAIMREG_P4_R8_READONLY" hexmask.long 0x20 0.--31. 1. "CLAIMREG_P4_R8_READONLY,Claim bits for Partition 4" line.long 0x24 "CFG0_CLAIMREG_P4_R9_READONLY" hexmask.long 0x24 0.--31. 1. "CLAIMREG_P4_R9_READONLY,Claim bits for Partition 4" line.long 0x28 "CFG0_CLAIMREG_P4_R10_READONLY" hexmask.long 0x28 0.--31. 1. "CLAIMREG_P4_R10_READONLY,Claim bits for Partition 4" group.long 0x12500++0x3 line.long 0x0 "CFG0_MAIN_PLL_TEST_CLKSEL_PROXY" bitfld.long 0x0 17. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL17_PROXY,Selects the alternate clock source for MAIN PLL17 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" newline bitfld.long 0x0 12. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL12_PROXY,Selects the alternate clock source for MAIN PLL12 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" newline bitfld.long 0x0 8. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL8_PROXY,Selects the alternate clock source for MAIN PLL8 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" newline bitfld.long 0x0 7. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL7_PROXY,Selects the alternate clock source for MAIN PLL7 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" newline bitfld.long 0x0 5. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL5_PROXY,Selects the alternate clock source for MAIN PLL5 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" newline bitfld.long 0x0 2. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL2_PROXY,Selects the alternate clock source for MAIN PLL2 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" newline bitfld.long 0x0 1. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL1_PROXY,Selects the alternate clock source for MAIN PLL1 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" newline bitfld.long 0x0 0. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL0_PROXY,Selects the alternate clock source for MAIN PLL0 Field values (others are reserved): 1'b0 - HFOSC0_CLKOUT 1'b1 - EXT_REFCLK1 pin" "0,1" group.long 0x13008++0x7 line.long 0x0 "CFG0_LOCK4_KICK0_PROXY" hexmask.long 0x0 0.--31. 1. "LOCK4_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK4_KICK1_PROXY" hexmask.long 0x4 0.--31. 1. "LOCK4_KICK1_PROXY,- KICK1 component" group.long 0x13100++0x2B line.long 0x0 "CFG0_CLAIMREG_P4_R0" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P4_R0,Claim bits for Partition 4" line.long 0x4 "CFG0_CLAIMREG_P4_R1" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P4_R1,Claim bits for Partition 4" line.long 0x8 "CFG0_CLAIMREG_P4_R2" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P4_R2,Claim bits for Partition 4" line.long 0xC "CFG0_CLAIMREG_P4_R3" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P4_R3,Claim bits for Partition 4" line.long 0x10 "CFG0_CLAIMREG_P4_R4" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P4_R4,Claim bits for Partition 4" line.long 0x14 "CFG0_CLAIMREG_P4_R5" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P4_R5,Claim bits for Partition 4" line.long 0x18 "CFG0_CLAIMREG_P4_R6" hexmask.long 0x18 0.--31. 1. "CLAIMREG_P4_R6,Claim bits for Partition 4" line.long 0x1C "CFG0_CLAIMREG_P4_R7" hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P4_R7,Claim bits for Partition 4" line.long 0x20 "CFG0_CLAIMREG_P4_R8" hexmask.long 0x20 0.--31. 1. "CLAIMREG_P4_R8,Claim bits for Partition 4" line.long 0x24 "CFG0_CLAIMREG_P4_R9" hexmask.long 0x24 0.--31. 1. "CLAIMREG_P4_R9,Claim bits for Partition 4" line.long 0x28 "CFG0_CLAIMREG_P4_R10" hexmask.long 0x28 0.--31. 1. "CLAIMREG_P4_R10,Claim bits for Partition 4" group.long 0x19008++0x7 line.long 0x0 "CFG0_LOCK6_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK6_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK6_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK6_KICK1,- KICK1 component" rgroup.long 0x19100++0x23 line.long 0x0 "CFG0_CLAIMREG_P6_R0_READONLY" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P6_R0_READONLY,Claim bits for Partition 6" line.long 0x4 "CFG0_CLAIMREG_P6_R1_READONLY" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P6_R1_READONLY,Claim bits for Partition 6" line.long 0x8 "CFG0_CLAIMREG_P6_R2_READONLY" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P6_R2_READONLY,Claim bits for Partition 6" line.long 0xC "CFG0_CLAIMREG_P6_R3_READONLY" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P6_R3_READONLY,Claim bits for Partition 6" line.long 0x10 "CFG0_CLAIMREG_P6_R4_READONLY" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P6_R4_READONLY,Claim bits for Partition 6" line.long 0x14 "CFG0_CLAIMREG_P6_R5_READONLY" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P6_R5_READONLY,Claim bits for Partition 6" line.long 0x18 "CFG0_CLAIMREG_P6_R6_READONLY" hexmask.long 0x18 0.--31. 1. "CLAIMREG_P6_R6_READONLY,Claim bits for Partition 6" line.long 0x1C "CFG0_CLAIMREG_P6_R7_READONLY" hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P6_R7_READONLY,Claim bits for Partition 6" line.long 0x20 "CFG0_CLAIMREG_P6_R8_READONLY" hexmask.long 0x20 0.--31. 1. "CLAIMREG_P6_R8_READONLY,Claim bits for Partition 6" group.long 0x1B008++0x7 line.long 0x0 "CFG0_LOCK6_KICK0_PROXY" hexmask.long 0x0 0.--31. 1. "LOCK6_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK6_KICK1_PROXY" hexmask.long 0x4 0.--31. 1. "LOCK6_KICK1_PROXY,- KICK1 component" group.long 0x1B100++0x23 line.long 0x0 "CFG0_CLAIMREG_P6_R0" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P6_R0,Claim bits for Partition 6" line.long 0x4 "CFG0_CLAIMREG_P6_R1" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P6_R1,Claim bits for Partition 6" line.long 0x8 "CFG0_CLAIMREG_P6_R2" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P6_R2,Claim bits for Partition 6" line.long 0xC "CFG0_CLAIMREG_P6_R3" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P6_R3,Claim bits for Partition 6" line.long 0x10 "CFG0_CLAIMREG_P6_R4" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P6_R4,Claim bits for Partition 6" line.long 0x14 "CFG0_CLAIMREG_P6_R5" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P6_R5,Claim bits for Partition 6" line.long 0x18 "CFG0_CLAIMREG_P6_R6" hexmask.long 0x18 0.--31. 1. "CLAIMREG_P6_R6,Claim bits for Partition 6" line.long 0x1C "CFG0_CLAIMREG_P6_R7" hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P6_R7,Claim bits for Partition 6" line.long 0x20 "CFG0_CLAIMREG_P6_R8" hexmask.long 0x20 0.--31. 1. "CLAIMREG_P6_R8,Claim bits for Partition 6" tree.end tree "DCC" base ad:0x0 tree "DCC0" base ad:0x800000 group.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." group.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." group.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" group.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC1" base ad:0x804000 group.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." group.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." group.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" group.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC2" base ad:0x808000 group.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." group.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." group.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" group.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC3" base ad:0x80C000 group.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." group.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." group.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" group.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC4" base ad:0x810000 group.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." group.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." group.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" group.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC5" base ad:0x814000 group.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." group.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." group.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" group.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "DCC6" base ad:0x818000 group.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." group.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." group.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" group.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree.end tree "DDR32SS0" base ad:0x0 tree "DDR32SS0_REGS_SS_CFG_SSCFG" base ad:0xF300000 rgroup.long 0x0++0x3 line.long 0x0 "REGS__SS_CFG__SSCFG_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem." hexmask.long.word 0x0 16.--31. 1. "MOD_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version" newline bitfld.long 0x0 8.--10. "MAJ_REV,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MIN_REV,Minor revision" group.long 0x4++0x3 line.long 0x0 "REGS__SS_CFG__SSCFG_SS_CTL_REG,The Subsystem Control Register contains fields for control functions required for submodules in the subsystem." bitfld.long 0x0 0. "PHY_PLL_BYPASS,Cadence PHY De-Skew PLL bypass. Write 1 to bypass PLL." "0,1" group.long 0x20++0x1F line.long 0x0 "REGS__SS_CFG__SSCFG_V2A_CTL_REG,The VBUSM2AXI Control register contains control functions required for the VBUSM2AXI submodule." hexmask.long.byte 0x0 22.--27. 1. "TOTAL_CMD_THRESH,Total command threshold. The VBUSM2AXI bridge will block all commands to DDR when the total number of commands sent to the Cadence controller is greater than this value. The reset value of this field is optimal; however it can be.." newline hexmask.long.byte 0x0 17.--21. 1. "WR_LO_BLK_THR,Write data threshold in 32 byte quantas. The VBUSM2AXI bridge will block all Low Priority Thread writes to DDR when the total number of write data bytes sent to the Cadence controller is greater than this value. The reset value of this.." newline hexmask.long.byte 0x0 12.--16. 1. "CRIT_THRESH,Critical threshold. The VBUSM2AXI bridge will block all Low Priority Thread traffic to DDR when the total number of commands sent to the Cadence controller is greater than this value. The reset value of this field is optimal; however it can.." newline bitfld.long 0x0 10. "SDRAM_3QT,Setting this field to a 1 will modify SDRAM Index to be 3/4 its programmed value to support 3 6 12 and 24 GB sizes." "0,1" newline hexmask.long.byte 0x0 5.--9. 1. "SDRAM_IDX,SDRAM Index = log2(connected SDRAM size) - 16. The sdram_idx describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues. Max size supported is.." newline hexmask.long.byte 0x0 0.--4. 1. "REGION_IDX,Region Index = log2(CBA region size) - 16. The region_idx describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues. Max size supported is.." line.long 0x4 "REGS__SS_CFG__SSCFG_V2A_R1_MAT_REG,The Range 1 Match Register allows a single master to a range of masters to change their priority mapping. This allows selective masters to be increased or decreased in effective priority. Range 1 Match Register uses the.." bitfld.long 0x4 31. "RANGE1_RANGEEN_A,The range1_rangeen_a enables the RouteID AND'd with range1_mask_a to match the range1_routeid_a" "0,1" newline bitfld.long 0x4 28.--30. "RANGE1_MASK_A,The range1_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 16.--27. 1. "RANGE1_ROUTEID_A,The range1_routeid_a is the value that is compared to the RouteID arriving on the command interface" newline bitfld.long 0x4 15. "RANGE1_RANGEEN_B,The range1_rangeen_b enables the RouteID AND'd with range1_mask_b to match the range1_routeid_b" "0,1" newline bitfld.long 0x4 12.--14. "RANGE1_MASK_B,The range1_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 0.--11. 1. "RANGE1_ROUTEID_B,The range1_routeid_b is the value that is compared to the RouteID arriving on the command interface" line.long 0x8 "REGS__SS_CFG__SSCFG_V2A_R2_MAT_REG,The Range 2 Match Register allows a single master to a range of masters to change their priority mapping. This allows selective masters to be increased or decreased in effective priority. Range 2 Match Register uses the.." bitfld.long 0x8 31. "RANGE2_RANGEEN_A,The range2_rangeen_a enables the RouteID AND'd with range2_mask_a to match the range2_routeid_a" "0,1" newline bitfld.long 0x8 28.--30. "RANGE2_MASK_A,The range2_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--27. 1. "RANGE2_ROUTEID_A,The range2_routeid_a is the value that is compared to the RouteID arriving on the command interface" newline bitfld.long 0x8 15. "RANGE2_RANGEEN_B,The range2_rangeen_b enables the RouteID AND'd with range2_mask_b to match the range2_routeid_b" "0,1" newline bitfld.long 0x8 12.--14. "RANGE2_MASK_B,The range2_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 0.--11. 1. "RANGE2_ROUTEID_B,The range2_routeid_b is the value that is compared to the RouteID arriving on the command interface" line.long 0xC "REGS__SS_CFG__SSCFG_V2A_R3_MAT_REG,The Range 3 Match Register allows a single master to a range of masters to change their priority mapping. This allows selective masters to be increased or decreased in effective priority. Range 3 Match Register uses the.." bitfld.long 0xC 31. "RANGE3_RANGEEN_A,The range3_rangeen_a enables the RouteID AND'd with range3_mask_a to match the range3_routeid_a" "0,1" newline bitfld.long 0xC 28.--30. "RANGE3_MASK_A,The range3_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC 16.--27. 1. "RANGE3_ROUTEID_A,The range3_routeid_a is the value that is compared to the RouteID arriving on the command interface" newline bitfld.long 0xC 15. "RANGE3_RANGEEN_B,The range3_rangeen_b enables the RouteID AND'd with range3_mask_b to match the range3_routeid_b" "0,1" newline bitfld.long 0xC 12.--14. "RANGE3_MASK_B,The range3_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC 0.--11. 1. "RANGE3_ROUTEID_B,The range3_routeid_b is the value that is compared to the RouteID arriving on the command interface" line.long 0x10 "REGS__SS_CFG__SSCFG_V2A_LPT_DEF_PRI_MAP_REG,The LPT Default Priority Mapping Register is the default map for the inbound VBUSM priority on the Low Priority Thread to the AXI priority." bitfld.long 0x10 28.--30. "LPT_PRIMAP0,The field contains AXI priority value for VBUSM priority 0. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x10 24.--26. "LPT_PRIMAP1,The field contains AXI priority value for VBUSM priority 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x10 20.--22. "LPT_PRIMAP2,The field contains AXI priority value for VBUSM priority 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x10 16.--18. "LPT_PRIMAP3,The field contains AXI priority value for VBUSM priority 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x10 12.--14. "LPT_PRIMAP4,The field contains AXI priority value for VBUSM priority 4. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x10 8.--10. "LPT_PRIMAP5,The field contains AXI priority value for VBUSM priority 5. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x10 4.--6. "LPT_PRIMAP6,The field contains AXI priority value for VBUSM priority 6. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x10 0.--2. "LPT_PRIMAP7,The field contains AXI priority value for VBUSM priority 7. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" line.long 0x14 "REGS__SS_CFG__SSCFG_V2A_LPT_R1_PRI_MAP_REG,The LPT Range 1 Priority Mapping Register is used to map the inbound VBUSM priority on the Low Priority Thread to AXI priority when a RouteID match 1 occurs. This allows the priority level to be changed from the.." bitfld.long 0x14 28.--30. "LPT_RANGE1_PRIMAP0,The field contains AXI priority value for VBUSM priority 0 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x14 24.--26. "LPT_RANGE1_PRIMAP1,The field contains AXI priority value for VBUSM priority 1 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x14 20.--22. "LPT_RANGE1_PRIMAP2,The field contains AXI priority value for VBUSM priority 2 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x14 16.--18. "LPT_RANGE1_PRIMAP3,The field contains AXI priority value for VBUSM priority 3 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x14 12.--14. "LPT_RANGE1_PRIMAP4,The field contains AXI priority value for VBUSM priority 4 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x14 8.--10. "LPT_RANGE1_PRIMAP5,The field contains AXI priority value for VBUSM priority 5 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x14 4.--6. "LPT_RANGE1_PRIMAP6,The field contains AXI priority value for VBUSM priority 6 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x14 0.--2. "LPT_RANGE1_PRIMAP7,The field contains AXI priority value for VBUSM priority 7 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" line.long 0x18 "REGS__SS_CFG__SSCFG_V2A_LPT_R2_PRI_MAP_REG,The LPT Range 2 Priority Mapping Register is used to map the inbound VBUSM priority on the Low Priority Thread to AXI priority when a RouteID match 2 occurs. This allows the priority level to be changed from the.." bitfld.long 0x18 28.--30. "LPT_RANGE2_PRIMAP0,The field contains AXI priority value for VBUSM priority 0 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x18 24.--26. "LPT_RANGE2_PRIMAP1,The field contains AXI priority value for VBUSM priority 1 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x18 20.--22. "LPT_RANGE2_PRIMAP2,The field contains AXI priority value for VBUSM priority 2 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x18 16.--18. "LPT_RANGE2_PRIMAP3,The field contains AXI priority value for VBUSM priority 3 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x18 12.--14. "LPT_RANGE2_PRIMAP4,The field contains AXI priority value for VBUSM priority 4 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x18 8.--10. "LPT_RANGE2_PRIMAP5,The field contains AXI priority value for VBUSM priority 5 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x18 4.--6. "LPT_RANGE2_PRIMAP6,The field contains AXI priority value for VBUSM priority 6 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x18 0.--2. "LPT_RANGE2_PRIMAP7,The field contains AXI priority value for VBUSM priority 7 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" line.long 0x1C "REGS__SS_CFG__SSCFG_V2A_LPT_R3_PRI_MAP_REG,The LPT Range 3 Priority Mapping Register is used to map the inbound VBUSM priority on the Low Priority Thread to AXI priority when a RouteID match 3 occurs. This allows the priority level to be changed from the.." bitfld.long 0x1C 28.--30. "LPT_RANGE3_PRIMAP0,The field contains AXI priority value for VBUSM priority 0 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x1C 24.--26. "LPT_RANGE3_PRIMAP1,The field contains AXI priority value for VBUSM priority 1 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x1C 20.--22. "LPT_RANGE3_PRIMAP2,The field contains AXI priority value for VBUSM priority 2 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x1C 16.--18. "LPT_RANGE3_PRIMAP3,The field contains AXI priority value for VBUSM priority 3 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x1C 12.--14. "LPT_RANGE3_PRIMAP4,The field contains AXI priority value for VBUSM priority 4 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x1C 8.--10. "LPT_RANGE3_PRIMAP5,The field contains AXI priority value for VBUSM priority 5 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x1C 4.--6. "LPT_RANGE3_PRIMAP6,The field contains AXI priority value for VBUSM priority 6 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x1C 0.--2. "LPT_RANGE3_PRIMAP7,The field contains AXI priority value for VBUSM priority 7 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" group.long 0x4C++0x13 line.long 0x0 "REGS__SS_CFG__SSCFG_V2A_HPT_DEF_PRI_MAP_REG,The HPT Default Priority Mapping Register is the default map for the inbound VBUSM priority on the High Priority Thread to the AXI priority." bitfld.long 0x0 28.--30. "HPT_PRIMAP0,The field contains AXI priority value for VBUSM priority 0. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x0 24.--26. "HPT_PRIMAP1,The field contains AXI priority value for VBUSM priority 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x0 20.--22. "HPT_PRIMAP2,The field contains AXI priority value for VBUSM priority 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x0 16.--18. "HPT_PRIMAP3,The field contains AXI priority value for VBUSM priority 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x0 12.--14. "HPT_PRIMAP4,The field contains AXI priority value for VBUSM priority 4. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x0 8.--10. "HPT_PRIMAP5,The field contains AXI priority value for VBUSM priority 5. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x0 4.--6. "HPT_PRIMAP6,The field contains AXI priority value for VBUSM priority 6. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x0 0.--2. "HPT_PRIMAP7,The field contains AXI priority value for VBUSM priority 7. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" line.long 0x4 "REGS__SS_CFG__SSCFG_V2A_HPT_R1_PRI_MAP_REG,The HPT Range 1 Priority Mapping Register is used to map the inbound VBUSM priority on the High Priority Thread to AXI priority when a RouteID match 1 occurs. This allows the priority level to be changed from.." bitfld.long 0x4 28.--30. "HPT_RANGE1_PRIMAP0,The field contains AXI priority value for VBUSM priority 0 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x4 24.--26. "HPT_RANGE1_PRIMAP1,The field contains AXI priority value for VBUSM priority 1 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x4 20.--22. "HPT_RANGE1_PRIMAP2,The field contains AXI priority value for VBUSM priority 2 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x4 16.--18. "HPT_RANGE1_PRIMAP3,The field contains AXI priority value for VBUSM priority 3 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x4 12.--14. "HPT_RANGE1_PRIMAP4,The field contains AXI priority value for VBUSM priority 4 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x4 8.--10. "HPT_RANGE1_PRIMAP5,The field contains AXI priority value for VBUSM priority 5 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x4 4.--6. "HPT_RANGE1_PRIMAP6,The field contains AXI priority value for VBUSM priority 6 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x4 0.--2. "HPT_RANGE1_PRIMAP7,The field contains AXI priority value for VBUSM priority 7 for range match 1. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" line.long 0x8 "REGS__SS_CFG__SSCFG_V2A_HPT_R2_PRI_MAP_REG,The HPT Range 2 Priority Mapping Register is used to map the inbound VBUSM priority on the High Priority Thread to AXI priority when a RouteID match 2 occurs. This allows the priority level to be changed from.." bitfld.long 0x8 28.--30. "HPT_RANGE2_PRIMAP0,The field contains AXI priority value for VBUSM priority 0 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x8 24.--26. "HPT_RANGE2_PRIMAP1,The field contains AXI priority value for VBUSM priority 1 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x8 20.--22. "HPT_RANGE2_PRIMAP2,The field contains AXI priority value for VBUSM priority 2 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x8 16.--18. "HPT_RANGE2_PRIMAP3,The field contains AXI priority value for VBUSM priority 3 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x8 12.--14. "HPT_RANGE2_PRIMAP4,The field contains AXI priority value for VBUSM priority 4 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x8 8.--10. "HPT_RANGE2_PRIMAP5,The field contains AXI priority value for VBUSM priority 5 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x8 4.--6. "HPT_RANGE2_PRIMAP6,The field contains AXI priority value for VBUSM priority 6 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0x8 0.--2. "HPT_RANGE2_PRIMAP7,The field contains AXI priority value for VBUSM priority 7 for range match 2. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" line.long 0xC "REGS__SS_CFG__SSCFG_V2A_HPT_R3_PRI_MAP_REG,The HPT Range 3 Priority Mapping Register is used to map the inbound VBUSM priority on the High Priority Thread to AXI priority when a RouteID match 3 occurs. This allows the priority level to be changed from.." bitfld.long 0xC 28.--30. "HPT_RANGE3_PRIMAP0,The field contains AXI priority value for VBUSM priority 0 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0xC 24.--26. "HPT_RANGE3_PRIMAP1,The field contains AXI priority value for VBUSM priority 1 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0xC 20.--22. "HPT_RANGE3_PRIMAP2,The field contains AXI priority value for VBUSM priority 2 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0xC 16.--18. "HPT_RANGE3_PRIMAP3,The field contains AXI priority value for VBUSM priority 3 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0xC 12.--14. "HPT_RANGE3_PRIMAP4,The field contains AXI priority value for VBUSM priority 4 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0xC 8.--10. "HPT_RANGE3_PRIMAP5,The field contains AXI priority value for VBUSM priority 5 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0xC 4.--6. "HPT_RANGE3_PRIMAP6,The field contains AXI priority value for VBUSM priority 6 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" newline bitfld.long 0xC 0.--2. "HPT_RANGE3_PRIMAP7,The field contains AXI priority value for VBUSM priority 7 for range match 3. 0=highest priority. 7=lowest priority" "0: highest priority,?,?,?,?,?,?,7: lowest priority" line.long 0x10 "REGS__SS_CFG__SSCFG_V2A_OLD_CMD_PR_REG" bitfld.long 0x10 31. "HPT_PRI_EQUAL,Setting to 1 will disable priority-based arbitration among the HPT commands." "0,1" newline bitfld.long 0x10 16. "OLD_CMD_PR_MODE,Oldest Command Priority Raise mode. Setting to 0 will count LPT commands sent while oldest command is waiting. Setting to 1 will count all commands sent while oldest command is waiting." "0,1" newline hexmask.long.word 0x10 0.--9. 1. "OLD_CMD_PR_THRESH,Oldest Command Priority Raise threshold. Number of commands sent in a row before the oldest command in the command FIFO is forwarded." group.long 0x68++0xB line.long 0x0 "REGS__SS_CFG__SSCFG_V2A_LEAKY_THRESH_REG" hexmask.long.byte 0x0 0.--7. 1. "SYS_LEAKY_THRESH,System Leaky Bucket threshold. Number of HPT commands sent in a row before a single LPT command is forwarded. A programmed value less than 0x4 will result in this field being reset to 0xFF." line.long 0x4 "REGS__SS_CFG__SSCFG_V2A_DRAIN_THRESH_REG" hexmask.long.word 0x4 0.--9. 1. "SYS_DRAIN_THRESH,System Drain threshold. Number of commands sent to the Cadence controller after which controller drain will be enabled. A programmed value less than 0x020 will result in this field being reset to 0x3FF." line.long 0x8 "REGS__SS_CFG__SSCFG_V2A_AERR_LOG1_REG,The Address Error Log 1 register displays the RouteID and lsb of the address for the first VBUSM command that was outside the programmed addressing range. Writing a 0x1 will clear all fields. Writing any other value.." hexmask.long.word 0x8 16.--31. 1. "AERR_ADDR_LSB,Address[15:0] of the VBUSM command" newline hexmask.long.word 0x8 0.--11. 1. "AERR_ROUTE_ID,RouteID of the VBUSM write command" rgroup.long 0x74++0x3 line.long 0x0 "REGS__SS_CFG__SSCFG_V2A_AERR_LOG2_REG,The Address Error Log 2 registers displays the msb of the address for the first VBUSM command that was outside the programmed addressing range. This register will be cleared upon writing the Address Error Log 1.." hexmask.long 0x0 0.--31. 1. "AERR_ADDR_MSB,Address[34:16] of the VBUSM command" group.long 0x9C++0x13 line.long 0x0 "REGS__SS_CFG__SSCFG_V2A_BUS_TO" hexmask.long.tbyte 0x0 0.--23. 1. "BUS_TIMER,AXI bus timeout value. Number of DDR clock cycles after which the VBUSM2AXI bridge times out if a hang on the controller AXI interface is detected. A value of N will be equal to N x 16 clocks. Writing a 0 will disable the timeout feature." line.long 0x4 "REGS__SS_CFG__SSCFG_V2A_INT_RAW_REG" bitfld.long 0x4 5. "ECCM1BERR,Raw status of SDRAM ECC multi 1-bit errors in same SDRAM burst. Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 4. "ECC2BERR,Raw status of SDRAM ECC 2-bit error. Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 3. "ECC1BERR,Raw status of SDRAM ECC 1-bit error. Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 2. "TOERR,Raw status of VBUSM2AXI interrupt for controller AXI interface timeout. Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" newline bitfld.long 0x4 1. "AERR,Raw status of VBUSM2AXI interrupt for VBUSM address outside the programmed range. Write 1 to set the (raw) status mostly for debug. Writing a 0 has no effect." "0,1" line.long 0x8 "REGS__SS_CFG__SSCFG_V2A_INT_STAT_REG" bitfld.long 0x8 5. "ECCM1BERR,Enabled status of SDRAM ECC multi 1-bit errors in same SDRAM burst. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 4. "ECC2BERR,Enabled status of SDRAM ECC 2-bit error. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 3. "ECC1BERR,Enabled status of SDRAM ECC 1-bit error. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "TOERR,Enabled status of VBUSM2AXI interrupt for controller AXI interface timeout. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "AERR,Enabled status of VBUSM2AXI interrupt for VBUSM address outside the programmed range. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared i.e. even if not enabled). Writing a 0 has no effect." "0,1" line.long 0xC "REGS__SS_CFG__SSCFG_V2A_INT_SET_REG" bitfld.long 0xC 5. "ECCM1BERR_EN,Enable set for SDRAM ECC multi 1-bit errors in same SDRAM burst. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 4. "ECC2BERR_EN,Enable set for SDRAM ECC 2-bit error. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 3. "ECC1BERR_EN,Enable set for SDRAM ECC 1-bit error. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "TOERR_EN,Enable set for VBUSM2AXI interrupt for controller AXI interface timeout. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "AERR_EN,Enable set for VBUSM2AXI interrupt for VBUSM address outside the programmed range. Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" line.long 0x10 "REGS__SS_CFG__SSCFG_V2A_INT_CLR_REG" bitfld.long 0x10 5. "ECCM1BERR_EN,Enable clear for SDRAM ECC multi 1-bit errors in same SDRAM burst. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 4. "ECC2BERR_EN,Enable clear for SDRAM ECC 2-bit error. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 3. "ECC1BERR_EN,Enable clear for SDRAM ECC 1-bit error. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 2. "TOERR_EN,Enable clear for VBUSM2AXI interrupt for controller AXI interface timeout. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "AERR_EN,Enable clear for VBUSM2AXI interrupt for VBUSM address outside the programmed range. Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" wgroup.long 0xB0++0x3 line.long 0x0 "REGS__SS_CFG__SSCFG_V2A_EOI_REG" bitfld.long 0x0 0.--1. "EOI,Software End Of Interrupt (EOI) control. Write 0 for aerr/toerr interrupt. Write 1 for ecc1b interrupt. Write 2 for ecc2b interrupt. This field always reads 0 (no EOI memory)." "0,1,2,3" group.long 0x100++0x3 line.long 0x0 "REGS__SS_CFG__SSCFG_PERF_CNT_SEL_REG,The Performance Counter Select register is used to select the statistic type to be counted in the corresponding Performance Counter register." hexmask.long.byte 0x0 24.--29. 1. "CNT4_SEL,Statistic select for Performance Counter 4 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every.." newline hexmask.long.byte 0x0 16.--21. 1. "CNT3_SEL,Statistic select for Performance Counter 3 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every.." newline hexmask.long.byte 0x0 8.--13. 1. "CNT2_SEL,Statistic select for Performance Counter 2 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every.." newline hexmask.long.byte 0x0 0.--5. 1. "CNT1_SEL,Statistic select for Performance Counter 1 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every.." rgroup.long 0x104++0xF line.long 0x0 "REGS__SS_CFG__SSCFG_PERF_CNT1_REG" hexmask.long 0x0 0.--31. 1. "CNT1,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register." line.long 0x4 "REGS__SS_CFG__SSCFG_PERF_CNT2_REG" hexmask.long 0x4 0.--31. 1. "CNT2,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register." line.long 0x8 "REGS__SS_CFG__SSCFG_PERF_CNT3_REG" hexmask.long 0x8 0.--31. 1. "CNT3,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register." line.long 0xC "REGS__SS_CFG__SSCFG_PERF_CNT4_REG" hexmask.long 0xC 0.--31. 1. "CNT4,Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register." group.long 0x120++0xB line.long 0x0 "REGS__SS_CFG__SSCFG_ECC_CTRL_REG" hexmask.long.byte 0x0 8.--11. 1. "COR_ECC_THRESH,Threshold for 1-bit ECC errors in multiple data words in an SDRAM burst that create an uncorrected error fault indication. Value of 0/1 means 2 or more 1-bit errors in multiple data words will result in an uncorrected error fault.." newline bitfld.long 0x0 4. "WR_ALLOC,When set to 1 an unassigned ECC cache-line will be allocated for a write with routeID that do not match any of the mapped routeID's." "0,1" newline bitfld.long 0x0 2. "ECC_CK,Set 1 to enable ECC verification for read accesses when ecc_en=1. The value of this field is ignored when ecc_en=0. This bit must be set and kept static before using DDR." "0,1" newline bitfld.long 0x0 1. "RMW_EN,Read modify write enable. Set 1 to enable RMW functionality for sub-quanta accesses when ecc_en=1. This bit must be set to 1 if ecc_en is set to a 1 to ensure subquanta accesses to DRAM do not result in ECC errors. This bit must be set and kept.." "0,1" newline bitfld.long 0x0 0. "ECC_EN,DRAM ECC enable. Setting a 1 causes ECC to be written to DRAM. This bit must be set and kept static before using DDR." "0,1" line.long 0x4 "REGS__SS_CFG__SSCFG_ECC_RID_INDX_REG" hexmask.long.byte 0x4 0.--5. 1. "ECCRID_ADR,This index specifies the ECC cache entry number that the eccrid_val is mapped to." line.long 0x8 "REGS__SS_CFG__SSCFG_ECC_RID_VAL_REG" bitfld.long 0x8 15. "ECCRID_VAL_VLD,A 1 in this field indicates that value in eccrid_val is valid." "0,1" newline hexmask.long.word 0x8 0.--11. 1. "ECCRID_VAL,RouteID value written or read." group.long 0x130++0x17 line.long 0x0 "REGS__SS_CFG__SSCFG_ECC_R0_STR_ADDR_REG" hexmask.long.tbyte 0x0 0.--18. 1. "ECC_STR_ADR_0,Start caddress[34:16] for ECC range 0. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR." line.long 0x4 "REGS__SS_CFG__SSCFG_ECC_R0_END_ADDR_REG" hexmask.long.tbyte 0x4 0.--18. 1. "ECC_END_ADR_0,End caddress[34:16] for ECC range 0. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR." line.long 0x8 "REGS__SS_CFG__SSCFG_ECC_R1_STR_ADDR_REG" hexmask.long.tbyte 0x8 0.--18. 1. "ECC_STR_ADR_1,Start caddress[34:16] for ECC range 1. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR." line.long 0xC "REGS__SS_CFG__SSCFG_ECC_R1_END_ADDR_REG" hexmask.long.tbyte 0xC 0.--18. 1. "ECC_END_ADR_1,End caddress[34:16] for ECC range 1. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR." line.long 0x10 "REGS__SS_CFG__SSCFG_ECC_R2_STR_ADDR_REG" hexmask.long.tbyte 0x10 0.--18. 1. "ECC_STR_ADR_2,Start caddress[34:16] for ECC range 2. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR." line.long 0x14 "REGS__SS_CFG__SSCFG_ECC_R2_END_ADDR_REG" hexmask.long.tbyte 0x14 0.--18. 1. "ECC_END_ADR_2,End caddress[34:16] for ECC range 2. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR." group.long 0x150++0xB line.long 0x0 "REGS__SS_CFG__SSCFG_ECC_1B_ERR_CNT_REG" hexmask.long.word 0x0 0.--15. 1. "ECC_1B_ERR_CNT,16-bit counter that displays number of 1-bit ECC errors on SDRAM data. Writing a 0x1 will clear this count. Writing any other value has no effect." line.long 0x4 "REGS__SS_CFG__SSCFG_ECC_1B_ERR_THRSH_REG" hexmask.long.word 0x4 0.--15. 1. "ECC_1B_ERR_THRSH,ECC 1-bit error threshold. The bridge will generate an interrupt when the ECC 1-bit error count is equal to or greater than this threshold. A value of 0 will disable the generation of interrupt." line.long 0x8 "REGS__SS_CFG__SSCFG_ECC_1B_ERR_ADR_LOG_REG" hexmask.long 0x8 0.--30. 1. "ECC_1B_ERR_ADR,ECC 1-bit error address. 32-byte aligned address that had the 1-bit ECC error. This field displays the first address logged in the 2 deep logging FIFO. Writing a 0x1 will pop the top element of the FIFO. Writing any other value has no.." rgroup.long 0x15C++0x3 line.long 0x0 "REGS__SS_CFG__SSCFG_ECC_1B_ERR_MSK_LOG_REG" hexmask.long.byte 0x0 0.--7. 1. "ECC_1B_ERR_MSK,ECC 1-bit error mask. Mask for the 64-byte data block that had the 1-bit ECC errors. Each bit represents an ECC quanta (8 bytes) in the 64-byte data block starting at address specified by ecc_1b_err_adr. Value of 1 on the bit represents an.." group.long 0x160++0x3 line.long 0x0 "REGS__SS_CFG__SSCFG_ECC_2B_ERR_ADR_LOG_REG" hexmask.long 0x0 0.--30. 1. "ECC_2B_ERR_ADR,ECC 2-bit error address. 32-byte aligned address that had the 2-bit ECC error. Writing a 0x1 will clear this field and the ecc_2b_err_msk field. Writing any other value has no effect." rgroup.long 0x164++0x3 line.long 0x0 "REGS__SS_CFG__SSCFG_ECC_2B_ERR_MSK_LOG_REG" hexmask.long.byte 0x0 0.--7. 1. "ECC_2B_ERR_MSK,ECC 2-bit error mask. Mask for the 64-byte data block that had the 2-bit ECC errors. Each bit represents an ECC quanta (8 bytes) in the 64-byte data block starting at address specified by ecc_2b_err_adr. Value of 1 on the bit represents an.." group.long 0x184++0x2F line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL1_REG" hexmask.long.byte 0x0 24.--31. 1. "JTAG_DATAOUT_TSEL_RD_SEL,Controls jtag_dataout_tsel_rd_sel port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." newline hexmask.long.byte 0x0 16.--23. 1. "JTAG_DATAOUT_TSEL_WR_SEL,Controls jtag_dataout_tsel_wr_sel port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." newline hexmask.long.byte 0x0 8.--15. 1. "JTAG_DATAOUT_TSEL_ADDR_SEL,Controls jtag_dataout_tsel_addr_sel port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." newline bitfld.long 0x0 7. "JTAG_DATAOUT_TSEL_ADDR_EN,Controls jtag_dataout_tsel_addr_en port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x0 6. "JTAG_DATAOUT_TSEL_EN,Controls jtag_dataout_tsel_en port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x0 5. "JTAG_ENABLE_TERM,Controls jtag_enable_term port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x0 4. "JTAG_ENABLE_OE,Controls jtag_enable_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x0 3. "JTAG_ENABLE_IE,Controls jtag_enable_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x0 2. "JTAG_ENABLE_DRIVE,Controls jtag_enable_drive port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x0 1. "JTAG_ENABLE,Controls jtag_enable port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x0 0. "HVM_TEST_EN,1=Enable HVM test functionality. 0=Disable HVM test functionality. Setting a 1 will enable control of PHY ports using PHY Test Control registers and will enable 50 MHz clock to the jtag_dataout_pad_dslice_io_cfg[1] .." "0: Disable HVM test functionality,1: Enable HVM test functionality" line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL2_REG" bitfld.long 0x4 31. "JTAG_DATAOUT_PAD_ADR_IO_CFG0,Controls jtag_dataout_pad_adr_io_cfg[0] port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x4 30. "JTAG_DATAOUT_PAD_ACS_IO_CFG0,Controls jtag_dataout_pad_acs_io_cfg[0] port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x4 29. "JTAG_DATAOUT_PAD_DSLICE_IO_CFG2,Controls jtag_dataout_pad_dslice_io_cfg[2] port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x4 28. "JTAG_DATAOUT_PAD_DSLICE_IO_CFG0,Controls jtag_dataout_pad_dslice_io_cfg[0] port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x4 27. "JTAG_DATAOUT_ATB_EN,Controls jtag_dataout_atb_en port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline hexmask.long.word 0x4 15.--26. 1. "JTAG_DATAOUT_VREF_CTRL_DQ,Controls jtag_dataout_vref_ctrl_dq port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." newline hexmask.long.word 0x4 6.--14. 1. "JTAG_DATAOUT_PHY_RX_CAL_CODE,Controls jtag_dataout_phy_rx_cal_code port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." newline hexmask.long.byte 0x4 0.--5. 1. "JTAG_DATAOUT_PHY_DSLICE_PAD_RX_CTLE_SETTING,Controls jtag_dataout_phy_dslice_pad_rx_ctle_setting port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." line.long 0x8 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL3_REG" hexmask.long.word 0x8 16.--31. 1. "JTAG_DATAOUT_ATB_CTRL,Controls jtag_dataout_atb_ctrl port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." newline hexmask.long.word 0x8 0.--15. 1. "JTAG_DATAOUT_PAD_ATB_CTRL,Controls jtag_dataout_pad_atb_ctrl port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." line.long 0xC "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL4_REG" bitfld.long 0xC 31. "JTAG_DATAOUT_ERROR_N_OE,Controls jtag_dataout_error_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0xC 30. "JTAG_DATAOUT_PARITY_IN_OE,Controls jtag_dataout_parity_in_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0xC 28.--29. "JTAG_DATAOUT_ODT_OE,Controls jtag_dataout_odt_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3" newline hexmask.long.word 0xC 14.--27. 1. "JTAG_DATAOUT_ADDRESS_OE,Controls jtag_dataout_address_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." newline bitfld.long 0xC 12.--13. "JTAG_DATAOUT_BANK_OE,Controls jtag_dataout_bank_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3" newline bitfld.long 0xC 10.--11. "JTAG_DATAOUT_BG_OE,Controls jtag_dataout_bg_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3" newline bitfld.long 0xC 9. "JTAG_DATAOUT_WE_N_OE,Controls jtag_dataout_we_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0xC 8. "JTAG_DATAOUT_CAS_N_OE,Controls jtag_dataout_cas_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0xC 7. "JTAG_DATAOUT_RAS_N_OE,Controls jtag_dataout_ras_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0xC 6. "JTAG_DATAOUT_ACT_N_OE,Controls jtag_dataout_act_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0xC 4.--5. "JTAG_DATAOUT_CS_N_OE,Controls jtag_dataout_cs_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3" newline bitfld.long 0xC 3. "JTAG_DATAOUT_MEM_CLK_0_OE,Controls jtag_dataout_mem_clk_0_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0xC 1.--2. "JTAG_DATAOUT_CKE_OE,Controls jtag_dataout_cke_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3" newline bitfld.long 0xC 0. "JTAG_DATAOUT_RESET_N_OE,Controls jtag_dataout_reset_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" line.long 0x10 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL5_REG" hexmask.long 0x10 0.--31. 1. "JTAG_DATAOUT_DATA_OE,Controls jtag_dataout_data_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." line.long 0x14 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL6_REG" bitfld.long 0x14 31. "JTAG_DATAOUT_ERROR_N,Controls jtag_dataout_error_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x14 30. "JTAG_DATAOUT_PARITY_IN,Controls jtag_dataout_parity_in port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x14 28.--29. "JTAG_DATAOUT_ODT,Controls jtag_dataout_odt port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3" newline hexmask.long.word 0x14 14.--27. 1. "JTAG_DATAOUT_ADDRESS,Controls jtag_dataout_address port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." newline bitfld.long 0x14 12.--13. "JTAG_DATAOUT_BANK,Controls jtag_dataout_bank port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3" newline bitfld.long 0x14 10.--11. "JTAG_DATAOUT_BG,Controls jtag_dataout_bg port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3" newline bitfld.long 0x14 9. "JTAG_DATAOUT_WE_N,Controls jtag_dataout_we_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x14 8. "JTAG_DATAOUT_CAS_N,Controls jtag_dataout_cas_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x14 7. "JTAG_DATAOUT_RAS_N,Controls jtag_dataout_ras_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x14 6. "JTAG_DATAOUT_ACT_N,Controls jtag_dataout_act_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x14 4.--5. "JTAG_DATAOUT_CS_N,Controls jtag_dataout_cs_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3" newline bitfld.long 0x14 3. "JTAG_DATAOUT_MEM_CLK_0,Controls jtag_dataout_mem_clk_0 port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x14 1.--2. "JTAG_DATAOUT_CKE,Controls jtag_dataout_cke port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3" newline bitfld.long 0x14 0. "JTAG_DATAOUT_RESET_N,Controls jtag_dataout_reset_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" line.long 0x18 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL7_REG" hexmask.long 0x18 0.--31. 1. "JTAG_DATAOUT_DATA,Controls jtag_dataout_data port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." line.long 0x1C "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL8_REG" bitfld.long 0x1C 31. "JTAG_DATAOUT_ERROR_N_IE,Controls jtag_dataout_error_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x1C 30. "JTAG_DATAOUT_PARITY_IN_IE,Controls jtag_dataout_parity_in_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x1C 28.--29. "JTAG_DATAOUT_ODT_IE,Controls jtag_dataout_odt_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3" newline hexmask.long.word 0x1C 14.--27. 1. "JTAG_DATAOUT_ADDRESS_IE,Controls jtag_dataout_address_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." newline bitfld.long 0x1C 12.--13. "JTAG_DATAOUT_BANK_IE,Controls jtag_dataout_bank_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3" newline bitfld.long 0x1C 10.--11. "JTAG_DATAOUT_BG_IE,Controls jtag_dataout_bg_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3" newline bitfld.long 0x1C 9. "JTAG_DATAOUT_WE_N_IE,Controls jtag_dataout_we_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x1C 8. "JTAG_DATAOUT_CAS_N_IE,Controls jtag_dataout_cas_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x1C 7. "JTAG_DATAOUT_RAS_N_IE,Controls jtag_dataout_ras_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x1C 6. "JTAG_DATAOUT_ACT_N_IE,Controls jtag_dataout_act_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x1C 4.--5. "JTAG_DATAOUT_CS_N_IE,Controls jtag_dataout_cs_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3" newline bitfld.long 0x1C 3. "JTAG_DATAOUT_MEM_CLK_0_IE,Controls jtag_dataout_mem_clk_0_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" newline bitfld.long 0x1C 1.--2. "JTAG_DATAOUT_CKE_IE,Controls jtag_dataout_cke_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1,2,3" newline bitfld.long 0x1C 0. "JTAG_DATAOUT_RESET_N_IE,Controls jtag_dataout_reset_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." "0,1" line.long 0x20 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL9_REG" hexmask.long 0x20 0.--31. 1. "JTAG_DATAOUT_DATA_IE,Controls jtag_dataout_data_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." line.long 0x24 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL10_REG" hexmask.long.byte 0x24 0.--7. 1. "HVM_CLK_DIV,Divfactor to divide ddrss_ddr_pll_clk to generate PCLK for HVM tests when ddrss_bs_mode=0 and hvm_test_en=1. 0=div by 1 1=div by 2 and so on." line.long 0x28 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL11_REG" hexmask.long.byte 0x28 24.--27. 1. "JTAG_DATAOUT_DQS_IE,Controls jtag_dataout_dqs_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." newline hexmask.long.byte 0x28 20.--23. 1. "JTAG_DATAOUT_DQS,Controls jtag_dataout_dqs port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." newline hexmask.long.byte 0x28 16.--19. 1. "JTAG_DATAOUT_DQS_OE,Controls jtag_dataout_dqs_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." newline hexmask.long.byte 0x28 8.--11. 1. "JTAG_DATAOUT_DM_IE,Controls jtag_dataout_dm_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." newline hexmask.long.byte 0x28 4.--7. 1. "JTAG_DATAOUT_DM,Controls jtag_dataout_dm port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." newline hexmask.long.byte 0x28 0.--3. 1. "JTAG_DATAOUT_DM_OE,Controls jtag_dataout_dm_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." line.long 0x2C "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL12_REG" hexmask.long.word 0x2C 0.--15. 1. "JTAG_DATAOUT_PHY_DSLICE_PAD_BOOSTPN_SETTING,Controls jtag_dataout_phy_dslice_pad_boostpn_setting port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1." rgroup.long 0x1C0++0xB line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_TEST_STAT1_REG" bitfld.long 0x0 31. "JTAG_DATAIN_ERROR_N,Displays value of jtag_datain_error_n port on the PHY." "0,1" newline bitfld.long 0x0 30. "JTAG_DATAIN_PARITY_IN,Displays value of jtag_datain_parity_in port on the PHY." "0,1" newline bitfld.long 0x0 28.--29. "JTAG_DATAIN_ODT,Displays value of jtag_datain_odt port on the PHY." "0,1,2,3" newline hexmask.long.word 0x0 14.--27. 1. "JTAG_DATAIN_ADDRESS,Displays value of jtag_datain_address port on the PHY." newline bitfld.long 0x0 12.--13. "JTAG_DATAIN_BANK,Displays value of jtag_datain_bank port on the PHY." "0,1,2,3" newline bitfld.long 0x0 10.--11. "JTAG_DATAIN_BG,Displays value of jtag_datain_bg port on the PHY." "0,1,2,3" newline bitfld.long 0x0 9. "JTAG_DATAIN_WE_N,Displays value of jtag_datain_we_n port on the PHY." "0,1" newline bitfld.long 0x0 8. "JTAG_DATAIN_CAS_N,Displays value of jtag_datain_cas_n port on the PHY." "0,1" newline bitfld.long 0x0 7. "JTAG_DATAIN_RAS_N,Displays value of jtag_datain_ras_n port on the PHY." "0,1" newline bitfld.long 0x0 6. "JTAG_DATAIN_ACT_N,Displays value of jtag_datain_act_n port on the PHY." "0,1" newline bitfld.long 0x0 4.--5. "JTAG_DATAIN_CS_N,Displays value of jtag_datain_cs_n port on the PHY." "0,1,2,3" newline bitfld.long 0x0 3. "JTAG_DATAIN_MEM_CLK_0,Displays value of jtag_datain_mem_clk_0 port on the PHY." "0,1" newline bitfld.long 0x0 1.--2. "JTAG_DATAIN_CKE,Displays value of jtag_datain_cke port on the PHY." "0,1,2,3" newline bitfld.long 0x0 0. "JTAG_DATAIN_RESET_N,Displays value of jtag_datain_reset_n port on the PHY." "0,1" line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_TEST_STAT2_REG" hexmask.long 0x4 0.--31. 1. "JTAG_DATAIN_DATA,Displays value of jtag_datain_data port on the PHY." line.long 0x8 "REGS__SS_CFG__SSCFG_PHY_TEST_STAT3_REG" hexmask.long.byte 0x8 8.--11. 1. "JTAG_DATAIN_DQS,Displays value of jtag_datain_dqs port on the PHY." newline hexmask.long.byte 0x8 0.--3. 1. "JTAG_DATAIN_DM,Displays value of jtag_datain_dm port on the PHY." tree.end tree.end tree "DFTSS0" base ad:0x500000 group.long 0x1E0++0x13 line.long 0x0 "MEM_PACT,This register is equivalent to pbist active in the PBIST controller" bitfld.long 0x0 0. "PACK,Enable to start the fail-processing state machine. At reset diag_clk to all controllers is enabled but it is disabled when 1 is written to this register. If 0 is written to the register at any time processing of failures stops and the combiner.." "0,1" line.long 0x4 "MEM_FAIL_DELAY,This register is equivalent to FDLY in the PBIST controller" hexmask.long.byte 0x4 0.--7. 1. "FDLY,This register makes sure that there is delay between processing fails from different controllers." line.long 0x8 "MEM_PBIST_ID,This register is equivalent to PBIST_ID in the PBIST controller" hexmask.long.byte 0x8 0.--3. 1. "PBISTID,The combiner is treated as a pbist controller. The register is written to when any controllers PBIST_ID registers is written to or when a separate combiners ID is written to." line.long 0xC "MEM_STATUS,This register shows fail status at any time during testing" hexmask.long 0xC 0.--31. 1. "STATUS,Fail values are loaded into this register based on the MASK0 register. If any bit of MASK0 is set to 0 then the corresponding controllers fail signal is set to 1 in the STATUS register. The size of this register is NO_OF_CTL - 1. This register is.." line.long 0x10 "MEM_MASK0,This register is used to determine which controllers are enabled for datalogging" hexmask.long 0x10 0.--31. 1. "ENABLE,This register must be programmed before starting any tests. Each bit with a value of 1 in this 32-bit register enables the corresponding controller for datalogging. This register gates all incoming status signals from controllers. At reset all.." group.long 0x1F0++0x3 line.long 0x0 "MEM_MASK1,This register enables PBIST controllers for ROM testing" hexmask.long 0x0 0.--31. 1. "ENABLE,Must be programmed before kicking off ROM based testing. Each bit with a value of 1 in this 32-bit register enables the corresponding ROM interface. This register gates tmode_pbist_rom signal. At reset all controllers are enabled for ROM-based.." group.long 0x1F0++0x3 line.long 0x0 "MEM_MASK2,This register enables pbist controllers for VLCT reads" hexmask.long 0x0 0.--31. 1. "EANBLE,Must be programmed before asserting read for any of the controllers. Each bit with a value of 1 in this 32-bit register enables the read request for the corresponding controller. You can consider the register as one-hot as only one controller can.." tree.end tree "DMASS0" base ad:0x0 tree "DMASS0_BCDMA_0_BCDMA_BCHAN" base ad:0x48420000 group.long 0x0++0x3 line.long 0x0 "BCDMA_BCHAN_CFG,The Channel Configuration Register is used to initialize static mode settings for the Block Copy DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW to.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." hexmask.long.byte 0x0 16.--19. 1. "CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-11 = RESERVED 12.." newline bitfld.long 0x0 10.--11. "BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes All other values are reserved The optimal burst size setting is 64 Bytes to maximize utilization of the channel FIFOs." "0: 32 Bytes,1: 64 Bytes All other values are reserved The..,?,?" group.long 0x64++0x3 line.long 0x0 "BCDMA_BCHAN_PRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." group.long 0x80++0x3 line.long 0x0 "BCDMA_BCHAN_ST_SCHED,The Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this.." bitfld.long 0x0 0.--1. "PRIORITY,Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx/Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end tree "DMASS0_BCDMA_0_BCDMA_BCHANRT" base ad:0x4C000000 group.long 0x0++0x3 line.long 0x0 "BCDMA_BCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" group.long 0x8++0x3 line.long 0x0 "BCDMA_BCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel. This register.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0xF line.long 0x0 "BCDMA_BCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "BCDMA_BCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" bitfld.long 0x4 8. "TDNULL,Channel is trying to teardown and has met conditions" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule a transaction" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,The channel is active" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" line.long 0x8 "BCDMA_BCHANRT_TRT_STATUS2,The Status Register provides a read only view of channel status bits." bitfld.long 0x8 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x8 30. "RXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x8 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x8 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x8 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x8 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x8 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x8 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x8 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x8 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x8 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x8 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0xC "BCDMA_BCHANRT_TRT_STATUS3,The Status Register provides a read only view of channel status bits." bitfld.long 0xC 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0xC 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" bitfld.long 0xC 24. "FIFO_BUSY,The fifo has data" "0,1" group.long 0x80++0x3 line.long 0x0 "BCDMA_BCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" group.long 0x100++0x3 line.long 0x0 "BCDMA_BCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" group.long 0x400++0x3 line.long 0x0 "BCDMA_BCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." group.long 0x408++0x3 line.long 0x0 "BCDMA_BCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." group.long 0x410++0x3 line.long 0x0 "BCDMA_BCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end tree "DMASS0_BCDMA_0_BCDMA_CRED" base ad:0x45812000 group.long 0x0++0x3 line.long 0x0 "BCDMA_CRED_CRED_CRED,The Credentials Register provides credentials to be used when performing memory accesses using this flow." bitfld.long 0x0 26. "SECURE,Secure attribute" "0,1" bitfld.long 0x0 24.--25. "PRIV,Privelege attribute" "0,1,2,3" hexmask.long.byte 0x0 16.--23. 1. "PRIVID,Privelege ID attribute" tree.end tree "DMASS0_BCDMA_0_BCDMA_GCFG" base ad:0x485C0100 rgroup.long 0x0++0x3 line.long 0x0 "BCDMA_GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" group.long 0x4++0x7 line.long 0x0 "BCDMA_GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "BCDMA_GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" group.long 0x10++0x3 line.long 0x0 "BCDMA_GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "BCDMA_GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" newline bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" newline bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" newline bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "BCDMA_GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "BCDMA_GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "BCDMA_GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "BCDMA_GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" group.long 0x60++0x7 line.long 0x0 "BCDMA_GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "BCDMA_GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" group.long 0x78++0x7 line.long 0x0 "BCDMA_GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "BCDMA_GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end tree "DMASS0_BCDMA_0_BCDMA_RCHAN" base ad:0x484C2000 group.long 0x0++0x3 line.long 0x0 "BCDMA_RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 =.." newline bitfld.long 0x0 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel. This field is only used when the channel is in split UTC mode. The values are encoded as follows: 0 = Long packets are treated as.." "0: Long packets are treated as exceptions and..,1: Long packets are ignored and the next TR will be.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes only if the channel buffer size is greater than 128 bytes 2 = 128 Bytes only if the channel buffer size is greater than 192 bytes.." "0: 32 Bytes,1: 64 Bytes only if the channel buffer size is..,2: 128 Bytes only if the channel buffer size is..,3: 256 bytes only if the channel buffer size is.." group.long 0x64++0x7 line.long 0x0 "BCDMA_RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "BCDMA_RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." group.long 0x80++0x3 line.long 0x0 "BCDMA_RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this.." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end tree "DMASS0_BCDMA_0_BCDMA_RCHANRT" base ad:0x4A820000 group.long 0x0++0x3 line.long 0x0 "BCDMA_RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 1. "RX_STARVATION,Rx starvation. This bit is set if the port receives a packet and the ring is empty. The bit clears when the doorbell is written with a positive value." "0,1" rbitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" group.long 0x8++0x3 line.long 0x0 "BCDMA_RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel. This register.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "BCDMA_RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "BCDMA_RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to send data" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has active transactions" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" group.long 0x80++0x3 line.long 0x0 "BCDMA_RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" group.long 0x200++0x3F line.long 0x0 "BCDMA_RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "BCDMA_RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "BCDMA_RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "BCDMA_RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "BCDMA_RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "BCDMA_RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "BCDMA_RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "BCDMA_RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "BCDMA_RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "BCDMA_RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "BCDMA_RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "BCDMA_RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "BCDMA_RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "BCDMA_RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "BCDMA_RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "BCDMA_RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." group.long 0x400++0x3 line.long 0x0 "BCDMA_RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." group.long 0x408++0x3 line.long 0x0 "BCDMA_RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." group.long 0x410++0x3 line.long 0x0 "BCDMA_RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end tree "DMASS0_BCDMA_0_BCDMA_RING" base ad:0x48600000 group.long 0x40++0xB line.long 0x0 "BCDMA_RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this register will reset.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "BCDMA_RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this register will reset.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "BCDMA_RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and reset the pointers." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end tree "DMASS0_BCDMA_0_BCDMA_RINGRT" base ad:0x4BC00000 group.long 0x10++0x3 line.long 0x0 "BCDMA_RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." group.long 0x18++0x3 line.long 0x0 "BCDMA_RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can be.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." group.long 0x1010++0x3 line.long 0x0 "BCDMA_RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." group.long 0x1018++0x3 line.long 0x0 "BCDMA_RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can be.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end tree "DMASS0_BCDMA_0_BCDMA_TCHAN" base ad:0x484A4000 group.long 0x0++0x3 line.long 0x0 "BCDMA_TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0-9 = RESERVED.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 = 32 Bytes 1 = 64 Bytes All other values are reserved The optimal burst size setting is 64 Bytes to maximize utilization of the channel FIFOs." "0: 32 Bytes,1: 64 Bytes All other values are reserved The..,?,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" group.long 0x64++0x7 line.long 0x0 "BCDMA_TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "BCDMA_TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." group.long 0x70++0x3 line.long 0x0 "BCDMA_TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be artificially reduced.." hexmask.long.byte 0x0 0.--7. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width (tstrm_wdth) the maximum value varies by channel class (ultra-high.." group.long 0x80++0x3 line.long 0x0 "BCDMA_TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this.." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end tree "DMASS0_BCDMA_0_BCDMA_TCHANRT" base ad:0x4AA40000 group.long 0x0++0x3 line.long 0x0 "BCDMA_TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" newline bitfld.long 0x0 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the.." "0,1" rbitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" group.long 0x8++0x3 line.long 0x0 "BCDMA_TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel. This register.." bitfld.long 0x0 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1" rgroup.long 0x40++0x7 line.long 0x0 "BCDMA_TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" newline bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" newline bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" newline bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "BCDMA_TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to do teardown" "0,1" newline bitfld.long 0x4 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" group.long 0x80++0x3 line.long 0x0 "BCDMA_TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" group.long 0x200++0x3F line.long 0x0 "BCDMA_TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "BCDMA_TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "BCDMA_TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "BCDMA_TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "BCDMA_TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "BCDMA_TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "BCDMA_TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "BCDMA_TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "BCDMA_TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "BCDMA_TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "BCDMA_TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "BCDMA_TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "BCDMA_TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "BCDMA_TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "BCDMA_TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "BCDMA_TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." group.long 0x400++0x3 line.long 0x0 "BCDMA_TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." group.long 0x408++0x3 line.long 0x0 "BCDMA_TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." group.long 0x410++0x3 line.long 0x0 "BCDMA_TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end tree "DMASS0_ECC_AGGR_0_ECCAGGR" base ad:0x3F005000 rgroup.long 0x0++0x3 line.long 0x0 "ECCAGGR_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECCAGGR_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECCAGGR_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECCAGGR_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECCAGGR_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECCAGGR_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 27. "MSRAM_RAMECC0_PEND,Interrupt Pending Status for msram_ramecc0_pend" "0,1" bitfld.long 0x4 26. "SEC_PROXY_BUFRAM_RAMECC_PEND,Interrupt Pending Status for sec_proxy_bufram_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "SEC_PROXY_STRAM_RAMECC_PEND,Interrupt Pending Status for sec_proxy_stram_ramecc_pend" "0,1" bitfld.long 0x4 24. "RINGACC_STRAM_RAMECC_PEND,Interrupt Pending Status for ringacc_stram_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "MAP_RAMECC_PEND,Interrupt Pending Status for map_ramecc_pend" "0,1" bitfld.long 0x4 22. "SR_RAMECC_PEND,Interrupt Pending Status for sr_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "BCDMA_RNGOCC_RAMECC_PEND,Interrupt Pending Status for bcdma_rngocc_ramecc_pend" "0,1" bitfld.long 0x4 20. "BCDMA_STS_RAMECC1_PEND,Interrupt Pending Status for bcdma_sts_ramecc1_pend" "0,1" newline bitfld.long 0x4 19. "BCDMA_STS_RAMECC0_PEND,Interrupt Pending Status for bcdma_sts_ramecc0_pend" "0,1" bitfld.long 0x4 18. "BCDMA_RPCF2_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf2_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "BCDMA_RPCF1_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 16. "BCDMA_RPCF0_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "BCDMA_TPCF1_RAMECC_PEND,Interrupt Pending Status for bcdma_tpcf1_ramecc_pend" "0,1" bitfld.long 0x4 14. "BCDMA_TPCF0_RAMECC_PEND,Interrupt Pending Status for bcdma_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "PCFD1_RAMECC_PEND,Interrupt Pending Status for pcfd1_ramecc_pend" "0,1" bitfld.long 0x4 12. "PCFD0_RAMECC_PEND,Interrupt Pending Status for pcfd0_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "BCDMA_STATE_RAMECC_PEND,Interrupt Pending Status for bcdma_state_ramecc_pend" "0,1" bitfld.long 0x4 10. "BCDMA_CFG_RAMECC_PEND,Interrupt Pending Status for bcdma_cfg_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "PKTDMA_RNGOCC_RAMECC_PEND,Interrupt Pending Status for pktdma_rngocc_ramecc_pend" "0,1" bitfld.long 0x4 8. "PKTDMA_STS_RAMECC1_PEND,Interrupt Pending Status for pktdma_sts_ramecc1_pend" "0,1" newline bitfld.long 0x4 7. "PKTDMA_STS_RAMECC0_PEND,Interrupt Pending Status for pktdma_sts_ramecc0_pend" "0,1" bitfld.long 0x4 6. "PKTDMA_RPCF2_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf2_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PKTDMA_RPCF1_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 4. "PKTDMA_RPCF0_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PKTDMA_TPCF1_RAMECC_PEND,Interrupt Pending Status for pktdma_tpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "PKTDMA_TPCF0_RAMECC_PEND,Interrupt Pending Status for pktdma_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "PKTDMA_STATE_RAMECC_PEND,Interrupt Pending Status for pktdma_state_ramecc_pend" "0,1" bitfld.long 0x4 0. "PKTDMA_CFG_RAMECC_PEND,Interrupt Pending Status for pktdma_cfg_ramecc_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECCAGGR_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 27. "MSRAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for msram_ramecc0_pend" "0,1" bitfld.long 0x0 26. "SEC_PROXY_BUFRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sec_proxy_bufram_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "SEC_PROXY_STRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sec_proxy_stram_ramecc_pend" "0,1" bitfld.long 0x0 24. "RINGACC_STRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for ringacc_stram_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "MAP_RAMECC_ENABLE_SET,Interrupt Enable Set Register for map_ramecc_pend" "0,1" bitfld.long 0x0 22. "SR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sr_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "BCDMA_RNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rngocc_ramecc_pend" "0,1" bitfld.long 0x0 20. "BCDMA_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for bcdma_sts_ramecc1_pend" "0,1" newline bitfld.long 0x0 19. "BCDMA_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for bcdma_sts_ramecc0_pend" "0,1" bitfld.long 0x0 18. "BCDMA_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf2_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "BCDMA_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 16. "BCDMA_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "BCDMA_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_tpcf1_ramecc_pend" "0,1" bitfld.long 0x0 14. "BCDMA_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "PCFD1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pcfd1_ramecc_pend" "0,1" bitfld.long 0x0 12. "PCFD0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pcfd0_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "BCDMA_STATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_state_ramecc_pend" "0,1" bitfld.long 0x0 10. "BCDMA_CFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_cfg_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "PKTDMA_RNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rngocc_ramecc_pend" "0,1" bitfld.long 0x0 8. "PKTDMA_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for pktdma_sts_ramecc1_pend" "0,1" newline bitfld.long 0x0 7. "PKTDMA_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for pktdma_sts_ramecc0_pend" "0,1" bitfld.long 0x0 6. "PKTDMA_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf2_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PKTDMA_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 4. "PKTDMA_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PKTDMA_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_tpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "PKTDMA_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "PKTDMA_STATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_state_ramecc_pend" "0,1" bitfld.long 0x0 0. "PKTDMA_CFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_cfg_ramecc_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECCAGGR_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 27. "MSRAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for msram_ramecc0_pend" "0,1" bitfld.long 0x0 26. "SEC_PROXY_BUFRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sec_proxy_bufram_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "SEC_PROXY_STRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sec_proxy_stram_ramecc_pend" "0,1" bitfld.long 0x0 24. "RINGACC_STRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ringacc_stram_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "MAP_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for map_ramecc_pend" "0,1" bitfld.long 0x0 22. "SR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sr_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "BCDMA_RNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rngocc_ramecc_pend" "0,1" bitfld.long 0x0 20. "BCDMA_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_sts_ramecc1_pend" "0,1" newline bitfld.long 0x0 19. "BCDMA_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_sts_ramecc0_pend" "0,1" bitfld.long 0x0 18. "BCDMA_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf2_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "BCDMA_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 16. "BCDMA_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "BCDMA_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_tpcf1_ramecc_pend" "0,1" bitfld.long 0x0 14. "BCDMA_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "PCFD1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pcfd1_ramecc_pend" "0,1" bitfld.long 0x0 12. "PCFD0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pcfd0_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "BCDMA_STATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_state_ramecc_pend" "0,1" bitfld.long 0x0 10. "BCDMA_CFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_cfg_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "PKTDMA_RNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rngocc_ramecc_pend" "0,1" bitfld.long 0x0 8. "PKTDMA_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_sts_ramecc1_pend" "0,1" newline bitfld.long 0x0 7. "PKTDMA_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_sts_ramecc0_pend" "0,1" bitfld.long 0x0 6. "PKTDMA_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf2_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PKTDMA_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 4. "PKTDMA_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PKTDMA_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_tpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "PKTDMA_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "PKTDMA_STATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_state_ramecc_pend" "0,1" bitfld.long 0x0 0. "PKTDMA_CFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_cfg_ramecc_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECCAGGR_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECCAGGR_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 27. "MSRAM_RAMECC0_PEND,Interrupt Pending Status for msram_ramecc0_pend" "0,1" bitfld.long 0x4 26. "SEC_PROXY_BUFRAM_RAMECC_PEND,Interrupt Pending Status for sec_proxy_bufram_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "SEC_PROXY_STRAM_RAMECC_PEND,Interrupt Pending Status for sec_proxy_stram_ramecc_pend" "0,1" bitfld.long 0x4 24. "RINGACC_STRAM_RAMECC_PEND,Interrupt Pending Status for ringacc_stram_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "MAP_RAMECC_PEND,Interrupt Pending Status for map_ramecc_pend" "0,1" bitfld.long 0x4 22. "SR_RAMECC_PEND,Interrupt Pending Status for sr_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "BCDMA_RNGOCC_RAMECC_PEND,Interrupt Pending Status for bcdma_rngocc_ramecc_pend" "0,1" bitfld.long 0x4 20. "BCDMA_STS_RAMECC1_PEND,Interrupt Pending Status for bcdma_sts_ramecc1_pend" "0,1" newline bitfld.long 0x4 19. "BCDMA_STS_RAMECC0_PEND,Interrupt Pending Status for bcdma_sts_ramecc0_pend" "0,1" bitfld.long 0x4 18. "BCDMA_RPCF2_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf2_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "BCDMA_RPCF1_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 16. "BCDMA_RPCF0_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "BCDMA_TPCF1_RAMECC_PEND,Interrupt Pending Status for bcdma_tpcf1_ramecc_pend" "0,1" bitfld.long 0x4 14. "BCDMA_TPCF0_RAMECC_PEND,Interrupt Pending Status for bcdma_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "PCFD1_RAMECC_PEND,Interrupt Pending Status for pcfd1_ramecc_pend" "0,1" bitfld.long 0x4 12. "PCFD0_RAMECC_PEND,Interrupt Pending Status for pcfd0_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "BCDMA_STATE_RAMECC_PEND,Interrupt Pending Status for bcdma_state_ramecc_pend" "0,1" bitfld.long 0x4 10. "BCDMA_CFG_RAMECC_PEND,Interrupt Pending Status for bcdma_cfg_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "PKTDMA_RNGOCC_RAMECC_PEND,Interrupt Pending Status for pktdma_rngocc_ramecc_pend" "0,1" bitfld.long 0x4 8. "PKTDMA_STS_RAMECC1_PEND,Interrupt Pending Status for pktdma_sts_ramecc1_pend" "0,1" newline bitfld.long 0x4 7. "PKTDMA_STS_RAMECC0_PEND,Interrupt Pending Status for pktdma_sts_ramecc0_pend" "0,1" bitfld.long 0x4 6. "PKTDMA_RPCF2_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf2_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "PKTDMA_RPCF1_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 4. "PKTDMA_RPCF0_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "PKTDMA_TPCF1_RAMECC_PEND,Interrupt Pending Status for pktdma_tpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "PKTDMA_TPCF0_RAMECC_PEND,Interrupt Pending Status for pktdma_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "PKTDMA_STATE_RAMECC_PEND,Interrupt Pending Status for pktdma_state_ramecc_pend" "0,1" bitfld.long 0x4 0. "PKTDMA_CFG_RAMECC_PEND,Interrupt Pending Status for pktdma_cfg_ramecc_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECCAGGR_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 27. "MSRAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for msram_ramecc0_pend" "0,1" bitfld.long 0x0 26. "SEC_PROXY_BUFRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sec_proxy_bufram_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "SEC_PROXY_STRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sec_proxy_stram_ramecc_pend" "0,1" bitfld.long 0x0 24. "RINGACC_STRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for ringacc_stram_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "MAP_RAMECC_ENABLE_SET,Interrupt Enable Set Register for map_ramecc_pend" "0,1" bitfld.long 0x0 22. "SR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sr_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "BCDMA_RNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rngocc_ramecc_pend" "0,1" bitfld.long 0x0 20. "BCDMA_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for bcdma_sts_ramecc1_pend" "0,1" newline bitfld.long 0x0 19. "BCDMA_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for bcdma_sts_ramecc0_pend" "0,1" bitfld.long 0x0 18. "BCDMA_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf2_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "BCDMA_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 16. "BCDMA_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "BCDMA_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_tpcf1_ramecc_pend" "0,1" bitfld.long 0x0 14. "BCDMA_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "PCFD1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pcfd1_ramecc_pend" "0,1" bitfld.long 0x0 12. "PCFD0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pcfd0_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "BCDMA_STATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_state_ramecc_pend" "0,1" bitfld.long 0x0 10. "BCDMA_CFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_cfg_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "PKTDMA_RNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rngocc_ramecc_pend" "0,1" bitfld.long 0x0 8. "PKTDMA_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for pktdma_sts_ramecc1_pend" "0,1" newline bitfld.long 0x0 7. "PKTDMA_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for pktdma_sts_ramecc0_pend" "0,1" bitfld.long 0x0 6. "PKTDMA_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf2_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PKTDMA_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 4. "PKTDMA_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PKTDMA_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_tpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "PKTDMA_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "PKTDMA_STATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_state_ramecc_pend" "0,1" bitfld.long 0x0 0. "PKTDMA_CFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_cfg_ramecc_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECCAGGR_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 27. "MSRAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for msram_ramecc0_pend" "0,1" bitfld.long 0x0 26. "SEC_PROXY_BUFRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sec_proxy_bufram_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "SEC_PROXY_STRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sec_proxy_stram_ramecc_pend" "0,1" bitfld.long 0x0 24. "RINGACC_STRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ringacc_stram_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "MAP_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for map_ramecc_pend" "0,1" bitfld.long 0x0 22. "SR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sr_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "BCDMA_RNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rngocc_ramecc_pend" "0,1" bitfld.long 0x0 20. "BCDMA_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_sts_ramecc1_pend" "0,1" newline bitfld.long 0x0 19. "BCDMA_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_sts_ramecc0_pend" "0,1" bitfld.long 0x0 18. "BCDMA_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf2_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "BCDMA_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 16. "BCDMA_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "BCDMA_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_tpcf1_ramecc_pend" "0,1" bitfld.long 0x0 14. "BCDMA_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "PCFD1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pcfd1_ramecc_pend" "0,1" bitfld.long 0x0 12. "PCFD0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pcfd0_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "BCDMA_STATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_state_ramecc_pend" "0,1" bitfld.long 0x0 10. "BCDMA_CFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_cfg_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "PKTDMA_RNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rngocc_ramecc_pend" "0,1" bitfld.long 0x0 8. "PKTDMA_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_sts_ramecc1_pend" "0,1" newline bitfld.long 0x0 7. "PKTDMA_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_sts_ramecc0_pend" "0,1" bitfld.long 0x0 6. "PKTDMA_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf2_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "PKTDMA_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 4. "PKTDMA_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "PKTDMA_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_tpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "PKTDMA_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_tpcf0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "PKTDMA_STATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_state_ramecc_pend" "0,1" bitfld.long 0x0 0. "PKTDMA_CFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_cfg_ramecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECCAGGR_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECCAGGR_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECCAGGR_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECCAGGR_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "DMASS0_INTAGGR_0_INTAGGR_CFG" base ad:0x48110000 rgroup.quad 0x0++0x17 line.quad 0x0 "INTAGGR_CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "INTAGGR_CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "INTAGGR_CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end tree "DMASS0_INTAGGR_0_INTAGGR_GCNTCFG" base ad:0x48220000 group.quad 0x0++0x7 line.quad 0x0 "INTAGGR_GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end tree "DMASS0_INTAGGR_0_INTAGGR_GCNTRTI" base ad:0x4A000000 group.quad 0x0++0x7 line.quad 0x0 "INTAGGR_GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a count has been processed by.." hexmask.quad.long 0x0 0.--31. 1. "CCNT,Current count. This field is incremented by the event count for each message received with this event on the Counted ETL Interface. On write this field will be decremented by the value written. Writing a value greater than the current count is.." tree.end tree "DMASS0_INTAGGR_0_INTAGGR_IMAP" base ad:0x48100000 group.quad 0x0++0x7 line.quad 0x0 "INTAGGR_IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto." hexmask.quad.word 0x0 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in." hexmask.quad.byte 0x0 0.--5. 1. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in." tree.end tree "DMASS0_INTAGGR_0_INTAGGR_INTR" base ad:0x48000000 group.quad 0x0++0x27 line.quad 0x0 "INTAGGR_INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt output." hexmask.quad 0x0 0.--63. 1. "INTR_ENABLE,Interrupt enable set value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x8 "INTAGGR_INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual interrupt output." hexmask.quad 0x8 0.--63. 1. "INTR_ENABLE,Interrupt enable clear value. On writes set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register." line.quad 0x10 "INTAGGR_INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x10 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set" line.quad 0x18 "INTAGGR_INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt." hexmask.quad 0x18 0.--63. 1. "INTR_STATUS,Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared" line.quad 0x20 "INTAGGR_INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt." hexmask.quad 0x20 0.--63. 1. "INTR_STATUSM,Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers" tree.end tree "DMASS0_INTAGGR_0_INTAGGR_L2G" base ad:0x48120000 group.quad 0x0++0x7 line.quad 0x0 "INTAGGR_L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane. Both pulse and rising edge local event types are supported. With pulsed events. the event count is determined by.." bitfld.quad 0x0 31. "MODE,Local event detection mode. This field is set to 0 for pulsed events and to 1 for rising edge eventss" "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end tree "DMASS0_INTAGGR_0_INTAGGR_MCAST" base ad:0x48210000 group.quad 0x0++0x7 line.quad 0x0 "INTAGGR_MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this register. which is.." bitfld.quad 0x0 63. "IRQMODE1,IRQ Mode Flag 1. When set this register act like a mapper with bitnum in 37:32 and regnum in 46:38." "0,1" hexmask.quad.word 0x0 32.--47. 1. "GEVIDX1,Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable." bitfld.quad 0x0 31. "IRQMODE0,IRQ Mode Flag 0. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "GEVIDX0,Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable." tree.end tree "DMASS0_INTAGGR_0_INTAGGR_UNMAP" base ad:0x48180000 group.quad 0x8000++0x7 line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." group.quad 0x9000++0x7 line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." group.quad 0xA000++0x7 line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." group.quad 0xB000++0x7 line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." group.quad 0xC000++0x7 line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." group.quad 0xD000++0x7 line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." group.quad 0x10000++0x7 line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." group.quad 0x11000++0x7 line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." group.quad 0x12000++0x7 line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." group.quad 0x13000++0x7 line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." group.quad 0x14000++0x7 line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." group.quad 0x15000++0x7 line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." group.quad 0x16000++0x7 line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." group.quad 0x17000++0x7 line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." group.quad 0x18000++0x7 line.quad 0x0 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag." bitfld.quad 0x0 31. "IRQMODE,IRQ Mode Flag. When set this register act like a mapper with bitnum in 5:0 and regnum in 14:6." "0,1" hexmask.quad.word 0x0 0.--15. 1. "UMAPIDX,Global event index. This field specifies the index of the outgoing global event. Set to 0xFFFF to disable." tree.end tree "DMASS0_PKTDMA_0_PKTDMA_CRED" base ad:0x45810000 group.long 0x0++0x3 line.long 0x0 "PKTDMA_CRED_CRED_CRED,The Credentials Register provides credentials to be used when performing memory accesses using this flow." bitfld.long 0x0 31. "CHK_SECURE,Check secure control bit" "0,1" bitfld.long 0x0 26. "SECURE,Secure attribute" "0,1" bitfld.long 0x0 24.--25. "PRIV,Privelege attribute" "0,1,2,3" hexmask.long.byte 0x0 16.--23. 1. "PRIVID,Privelege ID attribute" tree.end tree "DMASS0_PKTDMA_0_PKTDMA_GCFG" base ad:0x485C0000 rgroup.long 0x0++0x3 line.long 0x0 "PKTDMA_GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" group.long 0x4++0x7 line.long 0x0 "PKTDMA_GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the PKTDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported" line.long 0x4 "PKTDMA_GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" group.long 0x10++0x3 line.long 0x0 "PKTDMA_GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" group.long 0x20++0x7 line.long 0x0 "PKTDMA_GCFG_CAP0,The Capabilities Register 0 specifies which standard features this PKTDMA instance supports." line.long 0x4 "PKTDMA_GCFG_CAP1,The Capabilities Register 1 specifies which standard features this PKTDMA instance supports." rgroup.long 0x28++0xB line.long 0x0 "PKTDMA_GCFG_CAP2,The Capabilities Register 2 specifies how many resources this PKTDMA instance supports." hexmask.long.word 0x0 18.--26. 1. "RCHAN_CNT,Rx internal channel count" hexmask.long.word 0x0 0.--8. 1. "TCHAN_CNT,Tx internal channel count" line.long 0x4 "PKTDMA_GCFG_CAP3,The Capabilities Register 3 specifies how many resources this PKTDMA instance supports." hexmask.long.word 0x4 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count" hexmask.long.word 0x4 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count" hexmask.long.word 0x4 0.--13. 1. "RFLOW_CNT,Rx flow table entry count" line.long 0x8 "PKTDMA_GCFG_CAP4,The Capabilities Register 4 specifies how many resources this PKTDMA instance supports." hexmask.long.word 0x8 0.--13. 1. "TFLOW_CNT,Tx flow table entry count" group.long 0x60++0x7 line.long 0x0 "PKTDMA_GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x0 31. "NOGATE_RDU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 30. "NOGATE_RDU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 29. "NOGATE_RDU1,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 28. "NOGATE_RDU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 27. "NOGATE_TDU3,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 26. "NOGATE_TDU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 25. "NOGATE_TDU1,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 24. "NOGATE_TDU0,When set inhibits automatic gating of clock." "0,1" hexmask.long.word 0x0 13.--23. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 12. "NOGATE_RDEC,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x0 9.--11. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "NOGATE_SDEC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 5.--7. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "NOGATE_WARB,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 1.--3. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "NOGATE_CARB,When set inhibits automatic gating of clock." "0,1" line.long 0x4 "PKTDMA_GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_RSVD12,Reserved PM signals." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_RSVD11,Reserved PM signals." "0,1" bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 26. "NOGATE_RSVD10,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 23. "NOGATE_RSVD9,Reserved PM signals." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 19.--21. "NOGATE_RSVD8,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 16.--17. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" bitfld.long 0x4 15. "NOGATE_RFLOWFW,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 14. "NOGATE_RSVD6,Reserved PM signals." "0,1" newline bitfld.long 0x4 13. "NOGATE_RCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 12. "NOGATE_TCU,When set inhibits automatic gating of clock." "0,1" hexmask.long.word 0x4 0.--11. 1. "NOGATE_RSVD5,Reserved PM signals." group.long 0x78++0x3 line.long 0x0 "PKTDMA_GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" rgroup.long 0x7C++0x3 line.long 0x0 "PKTDMA_GCFG_DBGD,This register provides read only debug data" hexmask.long 0x0 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" group.long 0x88++0x3 line.long 0x0 "PKTDMA_GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check. Values in this register will remain persistent once an exception has been detected until the pend bit.." bitfld.long 0x0 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet. Once this bit is set the remaining fields in this register will not be modified. SW is required to write this bit to 0 to allow another.." "0,1" hexmask.long.word 0x0 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet" hexmask.long.word 0x0 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received" tree.end tree "DMASS0_PKTDMA_0_PKTDMA_RCHAN" base ad:0x484C0000 group.long 0x0++0x3 line.long 0x0 "PKTDMA_RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel. This register may only be written when the channel is disabled (rx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." hexmask.long.byte 0x0 16.--19. 1. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 2 = Channel.." newline bitfld.long 0x0 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 1 = 64 Bytes 2 = 128 Bytes All other values are reserved" "?,1: 64 Bytes,2: 128 Bytes All other values are reserved,?" group.long 0x64++0x7 line.long 0x0 "PKTDMA_RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "PKTDMA_RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." group.long 0x80++0x3 line.long 0x0 "PKTDMA_RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this.." bitfld.long 0x0 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end tree "DMASS0_PKTDMA_0_PKTDMA_RCHANRT" base ad:0x4A800000 group.long 0x0++0x3 line.long 0x0 "PKTDMA_RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "RX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in overflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete. This field should be cleared when a channel is initialized. This field will be set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared when the channel is disabled and re-enabled." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "PKTDMA_RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "RRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "RXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" newline bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" newline bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "PKTDMA_RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "RX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1" bitfld.long 0x4 24. "FIFO_BUSY,The fifo has data" "0,1" bitfld.long 0x4 7. "CHANNEL_OK,The channel is trying to schedule work" "0,1" newline bitfld.long 0x4 6. "CHANNEL_BUSY,The channel has active work" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" group.long 0x80++0x3 line.long 0x0 "PKTDMA_RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Rx state mapping table" group.long 0x200++0x3F line.long 0x0 "PKTDMA_RCHANRT_RRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "PKTDMA_RCHANRT_RRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "PKTDMA_RCHANRT_RRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "PKTDMA_RCHANRT_RRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "PKTDMA_RCHANRT_RRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "PKTDMA_RCHANRT_RRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "PKTDMA_RCHANRT_RRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "PKTDMA_RCHANRT_RRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "PKTDMA_RCHANRT_RRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "PKTDMA_RCHANRT_RRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "PKTDMA_RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "PKTDMA_RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "PKTDMA_RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "PKTDMA_RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "PKTDMA_RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "PKTDMA_RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." group.long 0x400++0xB line.long 0x0 "PKTDMA_RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." line.long 0x4 "PKTDMA_RCHANRT_RRT_DCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x4 0.--31. 1. "DCNT,Current dropped packet count for the channel." line.long 0x8 "PKTDMA_RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x8 0.--31. 1. "BCNT,Current completed payload byte count for the channel." group.long 0x410++0x3 line.long 0x0 "PKTDMA_RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end tree "DMASS0_PKTDMA_0_PKTDMA_RFLOW" base ad:0x48430000 group.long 0x0++0x3 line.long 0x0 "PKTDMA_RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow. The fields in this register can only be changed when all of the DMA channels that use this flow have been disabled. The fields in.." bitfld.long 0x0 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will clear the Extended Packet Info Present bit in.." "0,1" bitfld.long 0x0 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor. If this bit is clear the port DMA will set the PS word count to 0 in the PD and will drop any PS words.." "0,1" bitfld.long 0x0 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor starvation) occurs. 0 = Starvation errors result in dropping packet and incrementing dropped packet.." "0: Starvation errors result in dropping packet and..,1: Starvation errors result in the channel waiting.." hexmask.long.word 0x0 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the.." tree.end tree "DMASS0_PKTDMA_0_PKTDMA_RING" base ad:0x485E0000 group.long 0x40++0xB line.long 0x0 "PKTDMA_RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this register will reset.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Ring base address (LSBs)" line.long 0x4 "PKTDMA_RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to 0x8. A write to this register will reset.." hexmask.long.byte 0x4 16.--19. 1. "ASEL,Ring base address select" hexmask.long.byte 0x4 0.--3. 1. "ADDR_HI,Ring base address (MSBs)" line.long 0x8 "PKTDMA_RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and reset the pointers." bitfld.long 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "RING_ELSIZE" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." tree.end tree "DMASS0_PKTDMA_0_PKTDMA_RINGRT" base ad:0x4B800000 group.long 0x10++0x3 line.long 0x0 "PKTDMA_RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." group.long 0x18++0x3 line.long 0x0 "PKTDMA_RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can be.." hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." group.long 0x1010++0x3 line.long 0x0 "PKTDMA_RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation." bitfld.long 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." group.long 0x1018++0x3 line.long 0x0 "PKTDMA_RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can be.." bitfld.long 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" hexmask.long.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end tree "DMASS0_PKTDMA_0_PKTDMA_TCHAN" base ad:0x484A0000 group.long 0x0++0x3 line.long 0x0 "PKTDMA_TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0)." bitfld.long 0x0 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.long 0x0 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended.." "0: DMA controller will pass extended packet info..,1: DMA controller will filter extended packet info.." newline bitfld.long 0x0 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in.." "0: DMA controller will pass PS words if present in..,1: DMA controller will filter PS words" newline hexmask.long.byte 0x0 16.--19. 1. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 2 = Channel.." newline bitfld.long 0x0 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel. 0 1 = 64 Bytes 2 = 128 Bytes All other values are reserved" "?,1: 64 Bytes,2: 128 Bytes All other values are reserved,?" newline bitfld.long 0x0 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral. 0 = return immediately once all.." "0: return immediately once all traffic is complete..,1: wait until remote peer sends back a completion.." newline bitfld.long 0x0 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet" "0: TD packet is sent,1: Suppress sending TD packet" group.long 0x64++0x7 line.long 0x0 "PKTDMA_TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface." bitfld.long 0x0 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel." line.long 0x4 "PKTDMA_TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register." hexmask.long.word 0x4 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel." group.long 0x70++0x3 line.long 0x0 "PKTDMA_TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time. the FIFO depth can be artificially reduced.." hexmask.long.byte 0x0 0.--7. 1. "FDEPTH,FIFO Depth: This field contains the number of Tx FIFO bytes which will be allowed to be stored for the channel. The minimum value is equal to the PSI-L interface data path width but must be greater than 32 bytes + the burst size the maximum.." group.long 0x80++0x3 line.long 0x0 "PKTDMA_TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this.." bitfld.long 0x0 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority.." "0: High priority,1: Medium,2: Medium,3: Low priority Arbitration between bins is.." tree.end tree "DMASS0_PKTDMA_0_PKTDMA_TCHANRT" base ad:0x4AA00000 group.long 0x0++0x3 line.long 0x0 "PKTDMA_TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation." bitfld.long 0x0 31. "TX_ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared by.." bitfld.long 0x0 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" bitfld.long 0x0 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately." "0,1" bitfld.long 0x0 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0." "0,1" rgroup.long 0x40++0x7 line.long 0x0 "PKTDMA_TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits." bitfld.long 0x0 31. "TRING_PEND,The channel ring has a descriptor" "0,1" bitfld.long 0x0 30. "TXQ_PEND,The channel fifo is available" "0,1" bitfld.long 0x0 29. "PKTID_AVAIL,The channel has an available packet id" "0,1" bitfld.long 0x0 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1" newline bitfld.long 0x0 25. "BUSY,The channel is busy" "0,1" bitfld.long 0x0 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1" bitfld.long 0x0 23. "IN_PACKET,The channel is currently in a packet" "0,1" bitfld.long 0x0 22. "OK,The channel is ready to be scheduled" "0,1" newline bitfld.long 0x0 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1" bitfld.long 0x0 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1" bitfld.long 0x0 17. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x0 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1" line.long 0x4 "PKTDMA_TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits." bitfld.long 0x4 31. "TX_REQS,The channel is sending a schedule request" "0,1" bitfld.long 0x4 26. "SOP_WAVAIL,The FIFO has space for the start of a packet" "0,1" bitfld.long 0x4 25. "MOP_WAVAIL,The FIFO has space for the middle of a packet" "0,1" bitfld.long 0x4 24. "WAVAIL,The fifo has space for a burst size" "0,1" newline bitfld.long 0x4 8. "TDNULL,The channel has met the conditions to attempt to teardown" "0,1" bitfld.long 0x4 7. "CHANNEL_OK,The channel is trying to schedule work" "0,1" bitfld.long 0x4 6. "CHANNEL_BUSY,The channel has active work" "0,1" bitfld.long 0x4 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1" group.long 0x80++0x3 line.long 0x0 "PKTDMA_TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel. These registers are provided so that the Host can determine the potential cause of an error or exception condition which was reported by the.." hexmask.long 0x0 0.--31. 1. "STATE_INFO,See Tx state mapping table" group.long 0x200++0x3F line.long 0x0 "PKTDMA_TCHANRT_TRT_PEER0,This register provides access to the remote peer's realtime register at 0x400." hexmask.long 0x0 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x4 "PKTDMA_TCHANRT_TRT_PEER1,This register provides access to the remote peer's realtime register at 0x401." hexmask.long 0x4 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x8 "PKTDMA_TCHANRT_TRT_PEER2,This register provides access to the remote peer's realtime register at 0x402." hexmask.long 0x8 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0xC "PKTDMA_TCHANRT_TRT_PEER3,This register provides access to the remote peer's realtime register at 0x403." hexmask.long 0xC 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x10 "PKTDMA_TCHANRT_TRT_PEER4,This register provides access to the remote peer's realtime register at 0x404." hexmask.long 0x10 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x14 "PKTDMA_TCHANRT_TRT_PEER5,This register provides access to the remote peer's realtime register at 0x405." hexmask.long 0x14 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x18 "PKTDMA_TCHANRT_TRT_PEER6,This register provides access to the remote peer's realtime register at 0x406." hexmask.long 0x18 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x1C "PKTDMA_TCHANRT_TRT_PEER7,This register provides access to the remote peer's realtime register at 0x407." hexmask.long 0x1C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x20 "PKTDMA_TCHANRT_TRT_PEER8,This register provides access to the remote peer's realtime register at 0x408." hexmask.long 0x20 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x24 "PKTDMA_TCHANRT_TRT_PEER9,This register provides access to the remote peer's realtime register at 0x409." hexmask.long 0x24 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x28 "PKTDMA_TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A." hexmask.long 0x28 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x2C "PKTDMA_TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B." hexmask.long 0x2C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x30 "PKTDMA_TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C." hexmask.long 0x30 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x34 "PKTDMA_TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D." hexmask.long 0x34 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x38 "PKTDMA_TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E." hexmask.long 0x38 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." line.long 0x3C "PKTDMA_TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F." hexmask.long 0x3C 0.--31. 1. "PEER_DATA,Peer realtime register data (varies by paired peer)." group.long 0x400++0x3 line.long 0x0 "PKTDMA_TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "PCNT,Current completed packet count for the channel." group.long 0x408++0x3 line.long 0x0 "PKTDMA_TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "BCNT,Current completed payload byte count for the channel." group.long 0x410++0x3 line.long 0x0 "PKTDMA_TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel." hexmask.long 0x0 0.--31. 1. "SBCNT,Current started byte count for the channel." tree.end tree "DMASS0_PSILCFG_0_PSILCFG_PROXY" base ad:0x48130000 rgroup.long 0x0++0x3 line.long 0x0 "PSILCFG_PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" group.long 0x10++0x3 line.long 0x0 "PSILCFG_PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" group.long 0x100++0xB line.long 0x0 "PSILCFG_PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "PSILCFG_PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "PSILCFG_PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" group.long 0x140++0x3 line.long 0x0 "PSILCFG_PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end tree "DMASS0_PSILSS_0_ETLSW_MMRS" base ad:0x48230000 rgroup.long 0x0++0x7 line.long 0x0 "ETLSW_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "ETLSW_MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." group.long 0x10++0x3 line.long 0x0 "ETLSW_MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "ETLSW_MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." group.long 0x40++0x3 line.long 0x0 "ETLSW_MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end tree "DMASS0_PSILSS_0_PSILSS_MMRS" base ad:0x48140000 rgroup.long 0x0++0x7 line.long 0x0 "PSILSS_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "PSILSS_MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." group.long 0x10++0x3 line.long 0x0 "PSILSS_MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "PSILSS_MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." group.long 0x40++0x3 line.long 0x0 "PSILSS_MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end tree "DMASS0_RINGACC_0_RINGACC_CFG" base ad:0x49800000 group.long 0x40++0x13 line.long 0x0 "RINGACC_CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of the ring. or to.." hexmask.long 0x0 0.--31. 1. "ADDR_LO,Tx Ring base address (LSBs)" line.long 0x4 "RINGACC_CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned to the element size of the ring. or to.." hexmask.long.word 0x4 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)" line.long 0x8 "RINGACC_CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies.." bitfld.long 0x8 30.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3" bitfld.long 0x8 24.--26. "ELSIZE,Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED" "0: 4 bytes,1: 8 bytes,2: 16 bytes,3: 32 bytes,4: 64 bytes,5: 128 bytes,6: 256 bytes,7: RESERVED" hexmask.long.tbyte 0x8 0.--19. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number." line.long 0xC "RINGACC_CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring." hexmask.long.word 0xC 0.--15. 1. "EVT,Defines the event for this ring or queue." line.long 0x10 "RINGACC_CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access." bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the.." "0: bypass and use the orderid from the source..,1: use the orderid MMR field value for the.." hexmask.long.byte 0x10 0.--3. 1. "ORDERID,Defines the bus orderid value for this ring or queue." tree.end tree "DMASS0_RINGACC_0_RINGACC_GCFG" base ad:0x48240000 rgroup.long 0x0++0x3 line.long 0x0 "RINGACC_GCFG_revision,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" group.long 0x10++0x3 line.long 0x0 "RINGACC_GCFG_trace_ctl,Trace Control Register" bitfld.long 0x0 31. "EN,Trace enable 0 = disable 1 = enable." "0: disable,1: enable" bitfld.long 0x0 30. "ALL_QUEUES,Trace everything 0 = only the selected queue 1 = every queue." "0: only the selected queue,1: every queue" bitfld.long 0x0 29. "MSG,Trace message data 0 = include only the operation 1 = include message data." "0: include only the operation,1: include message data" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue number when tracing a single queue." group.long 0x20++0x3 line.long 0x0 "RINGACC_GCFG_overflow,Overflow Queue Register" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue to send overflow messages. A value of 0xffff will disable the overflow function." group.long 0x40++0x3 line.long 0x0 "RINGACC_GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error." hexmask.long.word 0x0 0.--15. 1. "EVT,Event to send when detecting a bus error." rgroup.long 0x44++0x3 line.long 0x0 "RINGACC_GCFG_error_log,Error Log Register. A read of this register will clear the pending error log event and allow a new error to be captured. It does not clear the contents of this register which are only valid while the error event is pending." bitfld.long 0x0 31. "PUSH,Bus error was caused by a push. 0 = pop. 1 = push." "0: pop,1: push" hexmask.long.word 0x0 0.--15. 1. "QUEUE,Queue that received the bus error." tree.end tree "DMASS0_RINGACC_0_RINGACC_RT" base ad:0x49000000 group.long 0x10++0x3 line.long 0x0 "RINGACC_RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field can be added to a ring with a single write operation." hexmask.long.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." group.long 0x18++0xF line.long 0x0 "RINGACC_RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for the ring which can be used.." hexmask.long.tbyte 0x0 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0x4 "RINGACC_RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel." hexmask.long.tbyte 0x4 0.--19. 1. "INDX,Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." line.long 0x8 "RINGACC_RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring. The contents of each of these registers are unary ORed in order to create a pending signal for.." hexmask.long.tbyte 0x8 0.--20. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." line.long 0xC "RINGACC_RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel." hexmask.long.tbyte 0xC 0.--19. 1. "INDX,Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size.." tree.end tree.end tree "DMASS1" base ad:0x0 tree "DMASS1_BCDMA_0_BCDMA_GCFG" base ad:0x4E230000 rgroup.long 0x0++0x3 line.long 0x0 "BCDMA_GCFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" group.long 0x4++0x7 line.long 0x0 "BCDMA_GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system." hexmask.long.word 0x0 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported." line.long 0x4 "BCDMA_GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted." bitfld.long 0x4 1. "SOFT,Soft" "0,1" bitfld.long 0x4 0. "FREE,Free" "0,1" group.long 0x10++0x3 line.long 0x0 "BCDMA_GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" rgroup.long 0x20++0x13 line.long 0x0 "BCDMA_GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports." bitfld.long 0x0 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1" bitfld.long 0x0 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1" bitfld.long 0x0 17. "EOL,EOL field is supported" "0,1" bitfld.long 0x0 16. "STATIC,STATIC field is supported" "0,1" bitfld.long 0x0 15. "TYPE15,Type 15 TR is supported" "0,1" newline bitfld.long 0x0 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.long 0x0 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.long 0x0 12. "TYPE12,Type 12 TR is supported" "0,1" bitfld.long 0x0 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.long 0x0 10. "TYPE10,Type 10 TR is supported" "0,1" newline bitfld.long 0x0 9. "TYPE9,Type 9 TR is supported" "0,1" bitfld.long 0x0 8. "TYPE8,Type 8 TR is supported" "0,1" bitfld.long 0x0 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.long 0x0 6. "TYPE6,Type 6 TR is supported" "0,1" bitfld.long 0x0 5. "TYPE5,Type 5 TR is supported" "0,1" newline bitfld.long 0x0 4. "TYPE4,Type 4 TR is supported" "0,1" bitfld.long 0x0 3. "TYPE3,Type 3 TR is supported" "0,1" bitfld.long 0x0 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.long 0x0 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.long 0x0 0. "TYPE0,Type 0 TR is supported" "0,1" line.long 0x4 "BCDMA_GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports." bitfld.long 0x4 3. "SECTR,Maximum second TR function that is supported" "0,1" bitfld.long 0x4 2. "DFMT,Maximum data reformatting function that is supported" "0,1" bitfld.long 0x4 1. "ELTYPE,Maximum element type value that is supported." "0,1" bitfld.long 0x4 0. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1" line.long 0x8 "BCDMA_GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports." hexmask.long.word 0x8 18.--26. 1. "RCHAN_CNT,Rx split channel count" hexmask.long.word 0x8 9.--17. 1. "TCHAN_CNT,Tx split channel count" hexmask.long.word 0x8 0.--8. 1. "CHAN_CNT,BC channel count" line.long 0xC "BCDMA_GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports." hexmask.long.word 0xC 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count" hexmask.long.word 0xC 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count" line.long 0x10 "BCDMA_GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports." hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count" hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count" hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count" hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count" group.long 0x60++0x7 line.long 0x0 "BCDMA_GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks" hexmask.long.tbyte 0x0 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals." bitfld.long 0x0 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 12.--13. "NOGATE_RSVD3,Reserved PM signals." "0,1,2,3" bitfld.long 0x0 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 8.--10. "NOGATE_RSVD2,Reserved PM signals." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "NOGATE_WARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 4.--6. "NOGATE_RSVD1,Reserved PM signals." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "NOGATE_CARB3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 2. "NOGATE_CARB2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x0 0.--1. "NOGATE_RSVD0,Reserved PM signals." "0,1,2,3" line.long 0x4 "BCDMA_GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks" bitfld.long 0x4 31. "NOGATE_EDC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 30. "NOGATE_STATS,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 29. "NOGATE_PROXY,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 27. "NOGATE_P2P,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 26. "NOGATE_RSVD8,Reserved PM signals." "0,1" bitfld.long 0x4 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 23. "NOGATE_RPCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 22. "NOGATE_TPCF,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 21. "NOGATE_PCF,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 19.--20. "NOGATE_RSVD7,Reserved PM signals." "0,1,2,3" bitfld.long 0x4 18. "NOGATE_CFG,When set inhibits automatic gating of clock." "0,1" hexmask.long.byte 0x4 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals." bitfld.long 0x4 10. "NOGATE_TRCU,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 9. "NOGATE_RSVD5,Reserved PM signals." "0,1" bitfld.long 0x4 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 7. "NOGATE_RWU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 6. "NOGATE_RWU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 5. "NOGATE_RWU1,When set inhibits automatic gating of clock." "0,1" newline bitfld.long 0x4 4. "NOGATE_RWU0,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 3. "NOGATE_TRU3,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 2. "NOGATE_TRU2,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 1. "NOGATE_TRU1,When set inhibits automatic gating of clock." "0,1" bitfld.long 0x4 0. "NOGATE_TRU0,When set inhibits automatic gating of clock." "0,1" group.long 0x78++0x7 line.long 0x0 "BCDMA_GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register" bitfld.long 0x0 31. "DBG_EN,Debug enable" "0,1" hexmask.long.byte 0x0 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from" hexmask.long.byte 0x0 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers" line.long 0x4 "BCDMA_GCFG_DBGD,This register provides read only debug data" hexmask.long 0x4 0.--31. 1. "DBG_DATA,Provides debug information from various internal units. The value which is read back depends on which unit and register are selected in the Debug Address Register" tree.end tree "DMASS1_ECC_AGGR_0_ECCAGGR" base ad:0x3F006000 rgroup.long 0x0++0x3 line.long 0x0 "ECCAGGR_REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECCAGGR_REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECCAGGR_REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECCAGGR_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECCAGGR_REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECCAGGR_REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 8. "MAP_RAMECC_PEND,Interrupt Pending Status for map_ramecc_pend" "0,1" bitfld.long 0x4 7. "SR_RAMECC_PEND,Interrupt Pending Status for sr_ramecc_pend" "0,1" bitfld.long 0x4 6. "BCDMA_RNGOCC_RAMECC_PEND,Interrupt Pending Status for bcdma_rngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "BCDMA_STS_RAMECC1_PEND,Interrupt Pending Status for bcdma_sts_ramecc1_pend" "0,1" bitfld.long 0x4 4. "BCDMA_RPCF2_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf2_ramecc_pend" "0,1" bitfld.long 0x4 3. "BCDMA_RPCF1_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "BCDMA_RPCF0_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "BCDMA_STATE_RAMECC_PEND,Interrupt Pending Status for bcdma_state_ramecc_pend" "0,1" bitfld.long 0x4 0. "BCDMA_CFG_RAMECC_PEND,Interrupt Pending Status for bcdma_cfg_ramecc_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECCAGGR_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 8. "MAP_RAMECC_ENABLE_SET,Interrupt Enable Set Register for map_ramecc_pend" "0,1" bitfld.long 0x0 7. "SR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sr_ramecc_pend" "0,1" bitfld.long 0x0 6. "BCDMA_RNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rngocc_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "BCDMA_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for bcdma_sts_ramecc1_pend" "0,1" bitfld.long 0x0 4. "BCDMA_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf2_ramecc_pend" "0,1" bitfld.long 0x0 3. "BCDMA_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "BCDMA_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "BCDMA_STATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_state_ramecc_pend" "0,1" bitfld.long 0x0 0. "BCDMA_CFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_cfg_ramecc_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECCAGGR_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 8. "MAP_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for map_ramecc_pend" "0,1" bitfld.long 0x0 7. "SR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sr_ramecc_pend" "0,1" bitfld.long 0x0 6. "BCDMA_RNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rngocc_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "BCDMA_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_sts_ramecc1_pend" "0,1" bitfld.long 0x0 4. "BCDMA_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf2_ramecc_pend" "0,1" bitfld.long 0x0 3. "BCDMA_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "BCDMA_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "BCDMA_STATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_state_ramecc_pend" "0,1" bitfld.long 0x0 0. "BCDMA_CFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_cfg_ramecc_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECCAGGR_REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECCAGGR_REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 8. "MAP_RAMECC_PEND,Interrupt Pending Status for map_ramecc_pend" "0,1" bitfld.long 0x4 7. "SR_RAMECC_PEND,Interrupt Pending Status for sr_ramecc_pend" "0,1" bitfld.long 0x4 6. "BCDMA_RNGOCC_RAMECC_PEND,Interrupt Pending Status for bcdma_rngocc_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "BCDMA_STS_RAMECC1_PEND,Interrupt Pending Status for bcdma_sts_ramecc1_pend" "0,1" bitfld.long 0x4 4. "BCDMA_RPCF2_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf2_ramecc_pend" "0,1" bitfld.long 0x4 3. "BCDMA_RPCF1_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "BCDMA_RPCF0_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "BCDMA_STATE_RAMECC_PEND,Interrupt Pending Status for bcdma_state_ramecc_pend" "0,1" bitfld.long 0x4 0. "BCDMA_CFG_RAMECC_PEND,Interrupt Pending Status for bcdma_cfg_ramecc_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECCAGGR_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 8. "MAP_RAMECC_ENABLE_SET,Interrupt Enable Set Register for map_ramecc_pend" "0,1" bitfld.long 0x0 7. "SR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sr_ramecc_pend" "0,1" bitfld.long 0x0 6. "BCDMA_RNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rngocc_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "BCDMA_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for bcdma_sts_ramecc1_pend" "0,1" bitfld.long 0x0 4. "BCDMA_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf2_ramecc_pend" "0,1" bitfld.long 0x0 3. "BCDMA_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "BCDMA_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "BCDMA_STATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_state_ramecc_pend" "0,1" bitfld.long 0x0 0. "BCDMA_CFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_cfg_ramecc_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECCAGGR_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 8. "MAP_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for map_ramecc_pend" "0,1" bitfld.long 0x0 7. "SR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sr_ramecc_pend" "0,1" bitfld.long 0x0 6. "BCDMA_RNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rngocc_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "BCDMA_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_sts_ramecc1_pend" "0,1" bitfld.long 0x0 4. "BCDMA_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf2_ramecc_pend" "0,1" bitfld.long 0x0 3. "BCDMA_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "BCDMA_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "BCDMA_STATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_state_ramecc_pend" "0,1" bitfld.long 0x0 0. "BCDMA_CFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_cfg_ramecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECCAGGR_REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECCAGGR_REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECCAGGR_REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECCAGGR_REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "DMASS1_INTAGGR_0_INTAGGR_CFG" base ad:0x4E0C0000 rgroup.quad 0x0++0x17 line.quad 0x0 "INTAGGR_CFG_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.quad.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.quad.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.quad.byte 0x0 0.--5. 1. "REVMIN,Minor revision" line.quad 0x8 "INTAGGR_CFG_INTCAP,The IntCap Register contains information on virtual interrupts." hexmask.quad.word 0x8 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count" hexmask.quad.word 0x8 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers" line.quad 0x10 "INTAGGR_CFG_AUXCAP,The AuxCap Register contains information on additional capabilities." hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers. Not all registers in the range are necessarily valid." hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers" hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation" hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers" tree.end tree "DMASS1_PSILCFG_0_PSILCFG_PROXY" base ad:0x4E260000 rgroup.long 0x0++0x3 line.long 0x0 "PSILCFG_PROXY_REVISION,The Revision Register contains the major and minor revisions for the module." hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" group.long 0x10++0x3 line.long 0x0 "PSILCFG_PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy." bitfld.long 0x0 31. "TOUT,Timeout occurred. When set indicates that a timeout has occurred on a config access. Once set this bit is persistent until manually cleared" "0,1" hexmask.long.word 0x0 0.--15. 1. "TOUT_CNT,Timeout period. Specifies how many cycles to wait before closing up a conifiguration read or write transaction and asserting the tout bit" group.long 0x100++0xB line.long 0x0 "PSILCFG_PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction." bitfld.long 0x0 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1" bitfld.long 0x0 30. "PROXY_DIR,Direction of configuration transaction" "0,1" bitfld.long 0x0 29. "PROXY_TOUT,Indication that a timeout occurred. This bit should be written to 0 on each new transaction." "0,1" hexmask.long.word 0x0 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent" line.long 0x4 "PSILCFG_PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction." hexmask.long.byte 0x4 28.--31. 1. "PROXY_BYTEN,Byte enables to use for configuration read or write" hexmask.long.word 0x4 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction" line.long 0x8 "PSILCFG_PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction." hexmask.long 0x8 0.--31. 1. "PROXY_WDATA,Configuration data word to be written" group.long 0x140++0x3 line.long 0x0 "PSILCFG_PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction." hexmask.long 0x0 0.--31. 1. "PROXY_RDATA,Configuration data word that was read" tree.end tree "DMASS1_PSILSS_0_PSILSS_MMRS" base ad:0x4E220000 rgroup.long 0x0++0x7 line.long 0x0 "PSILSS_MMRS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "PSILSS_MMRS_config,The Config Register shows configured params." hexmask.long.word 0x4 0.--15. 1. "ENDPOINTS,Number of endpoints supported." group.long 0x10++0x3 line.long 0x0 "PSILSS_MMRS_event,The Event Register defines the event to produce for a link down event." hexmask.long.word 0x0 0.--15. 1. "EVT,The event to produce." rgroup.long 0x20++0x3 line.long 0x0 "PSILSS_MMRS_link,The Link Register shows the current status of the endpoint links." hexmask.long 0x0 0.--31. 1. "STATUS,The status of the endpoint links." group.long 0x40++0x3 line.long 0x0 "PSILSS_MMRS_down,The Link Down Register shows which links are down for the endpoints." hexmask.long 0x0 0.--31. 1. "STATUS,The down status of the endpoint links." tree.end tree.end tree "DPHY" base ad:0x0 tree "DPHY_RX0_MMR_SLV_K3_DPHY_WRAP" base ad:0x30111000 group.long 0x0++0x3 line.long 0x0 "MMR__SLV__K3_DPHY_WRAP_REGS_lane,lane control and status" rbitfld.long 0x0 31. "RXCLKACTIVEHSCLK,Receiver high speed clock active: Driven active when the receiver high speed clock is active. 1'b0: Receiver high speed clock not active 1'b1: Receiver high speed clock active" "0: Receiver high speed clock not active,1: Receiver high speed clock active" newline rbitfld.long 0x0 30. "CMN_READY,Common ready indication: Indicates the completion of the startup process of the common module. Once this signal is driven active the PMA lanes may be released from reset. 1'b0 : Indicates that the startup process for the common components is.." "0: Indicates that the startup process for the..,1: Indicates that the startup process for the.." newline bitfld.long 0x0 26. "PSO_DISABLE,Disable power shut off: Disables the ability to switch off the analog switched power islands in the lane when in the ultra low power state. 1'b0: Power islands are switched off and on under the normal control of the escape mode process." "0: Power islands are switched off and on under the..,1: Power island shutoff functions disabled" newline bitfld.long 0x0 24. "PSO_CMN,Disable power shut off: Power Shutoff signal for CMN 1 : CMN is power OFF 0 : CMN is power ON" "0: CMN is power ON,1: CMN is power OFF" newline bitfld.long 0x0 23. "LANE_RSTB_CMN,SW reset for CMN. 0:asserted 1:released" "0: asserted,1: released" newline hexmask.long.byte 0x0 16.--22. 1. "PSM_CLOCK_FREQ,PMA state machine clock frequency divider control: This signal specifies a divider value used to create an internal divided clock that is a function of the psm_clock clock. This signal must be driven with a value such that the frequency of.." newline bitfld.long 0x0 9.--11. "IPCONFIG_CMN,This signal decides which clock lane acts as master clock lane to all data lanes. Needed only for RX IP. Bit[2]: Reserved CASE {Bit[1] Bit[0]}: 00: Left RX clk lane provides clock to all left and right data lanes. 01: Left RX clk lane.." "0: Left RX clk lane provides clock to all left and..,1: Left RX clk lane provides clock to all right..,?,?,?,?,?,?" newline bitfld.long 0x0 8. "CLK_SWAPDPDN_DL_L_3,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped,1: Swapped" newline bitfld.long 0x0 7. "CLK_SWAPDPDN_DL_L_2,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped,1: Swapped" newline bitfld.long 0x0 6. "DATA_SWAPDPDN_DL_L_3,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped,1: Swapped" newline bitfld.long 0x0 5. "DATA_SWAPDPDN_DL_L_2,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped,1: Swapped" newline bitfld.long 0x0 4. "CLK_SWAPDPDN_DL_L_1,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped,1: Swapped" newline bitfld.long 0x0 3. "CLK_SWAPDPDN_DL_L_0,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped,1: Swapped" newline bitfld.long 0x0 2. "DATA_SWAPDPDN_DL_L_1,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped,1: Swapped" newline bitfld.long 0x0 1. "DATA_SWAPDPDN_DL_L_0,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped,1: Swapped" newline bitfld.long 0x0 0. "CLK_SWAPDPDN_CL_L,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped. 1'b0: Not swapped 1'b1: Swapped" "0: Not swapped,1: Swapped" tree.end tree "DPHY_RX0_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX" base ad:0x30110000 group.long 0x20++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT2,CMN_DIG_TBIT2" bitfld.long 0x0 10. "O_CMN_RX_MODE_EN,Enable CMN RX related StateMachines" "0,1" bitfld.long 0x0 9. "O_CMN_TX_MODE_EN,Enable CMN TX related StateMachines" "0,1" newline hexmask.long.byte 0x0 1.--8. 1. "O_SSM_WAIT_BGCAL_EN,Wait time for Calibrations enable after bandgap is enabled [in us]" bitfld.long 0x0 0. "O_CMN_SSM_EN,Enable CMN startup state machine" "0,1" group.long 0x40++0x3 line.long 0x0 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT10,CMN_DIG_TBIT10" hexmask.long.byte 0x0 20.--27. 1. "O_ANA_PLL_BYTECLK_DIV,Byteclk divider value" hexmask.long.word 0x0 10.--19. 1. "O_ANA_PLL_GM_PWM_DIV_LOW,Low division value setting for the gm PWM control divider" newline hexmask.long.word 0x0 0.--9. 1. "O_ANA_PLL_GM_PWM_DIV_HIGH,High division value setting for the gm PWM control divider" group.long 0x4C++0x7 line.long 0x0 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT13,CMN_DIG_TBIT13" hexmask.long.word 0x0 22.--31. 1. "O_ANA_PLL_FB_DIV_LOW_TM,forced value for pll_fb_div_clk_low" bitfld.long 0x0 21. "O_ANA_PLL_FB_DIV_LOW_TM_SEL,pll_fb_div_clk_low forced from test registers" "0,1" newline hexmask.long.word 0x0 11.--20. 1. "O_ANA_PLL_FB_DIV_HIGH_TM,forced value for pll_fb_div_clk_high" bitfld.long 0x0 10. "O_ANA_PLL_FB_DIV_HIGH_TM_SEL,pll_fb_div_clk_high forced from test registers" "0,1" line.long 0x4 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT14,CMN_DIG_TBIT14" hexmask.long.byte 0x4 7.--12. 1. "O_ANA_PLL_OP_DIV_TM,forced value for op_div" bitfld.long 0x4 6. "O_ANA_PLL_OP_DIV_TM_SEL,op_div forced from test registers" "0,1" newline hexmask.long.byte 0x4 1.--5. 1. "O_ANA_PLL_IP_DIV_TM,forced value for ip_div" bitfld.long 0x4 0. "O_ANA_PLL_IP_DIV_TM_SEL,ip_div forced from test registers" "0,1" group.long 0xB00++0xF line.long 0x0 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT0,PHY_BAND_CONTROL" hexmask.long.byte 0x0 5.--9. 1. "BAND_CTL_REG_R,Data Rate [80_100] MHz" hexmask.long.byte 0x0 0.--4. 1. "BAND_CTL_REG_L,Data Rate [80_100] MHz" line.long 0x4 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT1,PHY_PSM_CONFIG" hexmask.long.byte 0x4 1.--8. 1. "PSM_CLOCK_FREQ,psm_clock freq value" bitfld.long 0x4 0. "PSM_CLOCK_FREQ_EN,take psm_clock_freq from tbit" "0,1" line.long 0x8 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT2,PHY_PI_PH2_DL_CONFIG" hexmask.long.byte 0x8 28.--31. 1. "POWER_SW_2_TIME_DL_R_3,power_sw_2_time_dl_r_3" hexmask.long.byte 0x8 24.--27. 1. "POWER_SW_2_TIME_DL_R_2,power_sw_2_time_dl_r_2" newline hexmask.long.byte 0x8 20.--23. 1. "POWER_SW_2_TIME_DL_R_1,power_sw_2_time_dl_r_1" hexmask.long.byte 0x8 16.--19. 1. "POWER_SW_2_TIME_DL_R_0,power_sw_2_time_dl_r_0" newline hexmask.long.byte 0x8 12.--15. 1. "POWER_SW_2_TIME_DL_L_3,power_sw_2_time_dl_l_3" hexmask.long.byte 0x8 8.--11. 1. "POWER_SW_2_TIME_DL_L_2,power_sw_2_time_dl_l_2" newline hexmask.long.byte 0x8 4.--7. 1. "POWER_SW_2_TIME_DL_L_1,power_sw_2_time_dl_l_1" hexmask.long.byte 0x8 0.--3. 1. "POWER_SW_2_TIME_DL_L_0,power_sw_2_time_dl_l_0" line.long 0xC "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT3,PHY_PI_PH2_CL_CMN_CONFIG" hexmask.long.byte 0xC 8.--11. 1. "POWER_SW_2_TIME_CMN,power_sw_2_time_cmn" hexmask.long.byte 0xC 4.--7. 1. "POWER_SW_2_TIME_CL_R,power_sw_2_time_cl_r" newline hexmask.long.byte 0xC 0.--3. 1. "POWER_SW_2_TIME_CL_L,power_sw_2_time_cl_l" tree.end tree.end tree "DSS0" base ad:0x0 tree "DSS0_COMMON" base ad:0x30200000 rgroup.long 0x4++0x3 line.long 0x0 "COMMON_DSS_REVISION,This register contains the K3_DSS revision number" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID Field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Revision" bitfld.long 0x0 8.--10. "REVMAJOR,Major Revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Revision" group.long 0x8++0x3 line.long 0x0 "COMMON_DSS_SYSCONFIG,This register controls various parameters related to software reset and IP idle" hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED4,Write 0's for future compatibility. Read returns 0" hexmask.long.byte 0x0 8.--13. 1. "RESERVED3,Write 0's for future compatibility. Read returns 0" rbitfld.long 0x0 6.--7. "RESERVED2,Write 0's for future compatibility. Read returns 0" "0,1,2,3" newline bitfld.long 0x0 5. "WARMRESET,Warm reset. Setting this bit to 1 triggers a module warm reset. The bit is automatically reset by the hardware. During read it always returns 0. The warm reset keeps the configuration registers unchanged" "0,1" bitfld.long 0x0 3.--4. "IDLEMODE,Deprecated" "0,1,2,3" rbitfld.long 0x0 2. "RESERVED1,Write 0's for future compatibility. Read returns 0" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Setting this bit to 1 triggers a module reset. The bit is automatically reset by the hardware. During read it always returns 0" "0,1" bitfld.long 0x0 0. "AUTOCLKGATING,Internal clock gating strategy" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "COMMON_DSS_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x0 9. "DISPC_IDLE_STATUS,Idle status of DISPC" "0,1" bitfld.long 0x0 5. "OLDI_RESETDONE,Reset status of OLDI" "0,1" bitfld.long 0x0 1.--2. "DISPC_VP_RESETDONE,Reset status of VP pixel clock domain" "0,1,2,3" newline bitfld.long 0x0 0. "DISPC_FUNC_RESETDONE,Reset status of DISPC Functional clock domain" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "COMMON_DISPC_IRQ_EOI,End-Of-Interrupt register. to be used if pulse interrupts are used" bitfld.long 0x0 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1" group.long 0x28++0xB line.long 0x0 "COMMON_DISPC_IRQSTATUS_RAW,RAW Interrupt status. Raw status is set even if interrupt is not enabled. Write 1 to set the RAW status" bitfld.long 0x0 4.--5. "VID_IRQ,VID IRQ STATUS. Register indicates the VIDEO pipeline[s] interrupt events" "0,1,2,3" bitfld.long 0x0 0.--1. "VP_IRQ,VP IRQ STATUS. Register indicates the Video Port[s] interrupt events" "0,1,2,3" line.long 0x4 "COMMON_DISPC_IRQSTATUS,Interrupt status. Enabled status. isn't set unless event is enabled. Write 1 to clear the status after interrupt has been serviced. RAW status also gets cleared. i.e. even if not enabled" bitfld.long 0x4 4.--5. "VID_IRQ,VID IRQ STATUS. Register indicates the VIDEO pipeline[s] interrupt events" "0,1,2,3" bitfld.long 0x4 0.--1. "VP_IRQ,VP IRQ STATUS. Register indicates the Video Port[s] interrupt events" "0,1,2,3" line.long 0x8 "COMMON_DISPC_IRQENABLE_SET,SET Interrupt enable. Write 1 to set interrupt enable. Readout equal to corresponding _CLR register" bitfld.long 0x8 4.--5. "SET_VID_IRQ,VID IRQ" "0,1,2,3" bitfld.long 0x8 0.--1. "SET_VP_IRQ,VP IRQ" "0,1,2,3" group.long 0x40++0xB line.long 0x0 "COMMON_DISPC_IRQENABLE_CLR,CLR Interrupt enable. Write 1 to clear interrupt enable" bitfld.long 0x0 4.--5. "CLR_VID_IRQ,VID IRQ" "0,1,2,3" bitfld.long 0x0 0.--1. "CLR_VP_IRQ,VP IRQ" "0,1,2,3" line.long 0x4 "COMMON_VID_IRQENABLE_0,This register allows to mask/unmask the VID_0 internal sources of interrupt. on an event-by-event basis" bitfld.long 0x4 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x4 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x4 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x8 "COMMON_VID_IRQENABLE_1,This register allows to mask/unmask the VIDL_0 internal sources of interrupt. on an event-by-event basis" bitfld.long 0x8 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x8 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x8 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" group.long 0x58++0x7 line.long 0x0 "COMMON_VID_IRQSTATUS_0,This register groups all the status of the VID_0 internal events that generate an interrupt. Write 1 to a clear a bit field" bitfld.long 0x0 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x0 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x0 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x4 "COMMON_VID_IRQSTATUS_1,This register groups all the status of the VIDL_0 internal events that generate an interrupt. Write 1 to a clear a bit field" bitfld.long 0x4 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x4 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x4 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" group.long 0x70++0x7 line.long 0x0 "COMMON_VP_IRQENABLE_0,This register allows to mask/unmask the VP_0 internal sources of interrupt. on an event-by-event basis" bitfld.long 0x0 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x0 11. "VPSYNC_EN,Go bit clear event" "0,1" bitfld.long 0x0 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" newline hexmask.long.byte 0x0 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" bitfld.long 0x0 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" bitfld.long 0x0 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" newline bitfld.long 0x0 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x0 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" bitfld.long 0x0 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" newline bitfld.long 0x0 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x4 "COMMON_VP_IRQENABLE_1,This register allows to mask/unmask the VP_1 internal sources of interrupt. on an event-by-event basis" bitfld.long 0x4 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x4 11. "VPSYNC_EN,Go bit clear event" "0,1" bitfld.long 0x4 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" newline hexmask.long.byte 0x4 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" bitfld.long 0x4 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" bitfld.long 0x4 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" newline bitfld.long 0x4 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x4 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" bitfld.long 0x4 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" newline bitfld.long 0x4 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" group.long 0x7C++0x7 line.long 0x0 "COMMON_VP_IRQSTATUS_0,This register groups all the status of the VP_0 internal events that generate an interrupt. Write 1 to a given bit resets this bit" bitfld.long 0x0 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x0 11. "VPSYNC_IRQ,Go bit clear event" "0,1" bitfld.long 0x0 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" newline hexmask.long.byte 0x0 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" bitfld.long 0x0 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" bitfld.long 0x0 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" newline bitfld.long 0x0 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x0 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" bitfld.long 0x0 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" newline bitfld.long 0x0 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x4 "COMMON_VP_IRQSTATUS_1,This register groups all the status of the VP_1 internal events that generate an interrupt. Write 1 to a given bit resets this bit" bitfld.long 0x4 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x4 11. "VPSYNC_IRQ,Go bit clear event" "0,1" bitfld.long 0x4 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" newline hexmask.long.byte 0x4 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" bitfld.long 0x4 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" bitfld.long 0x4 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" newline bitfld.long 0x4 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x4 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" bitfld.long 0x4 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" newline bitfld.long 0x4 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" group.long 0x90++0x13 line.long 0x0 "COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE,MFLAG control register" bitfld.long 0x0 6. "MFLAG_START,MFLAG_START for DMA master port" "0,1" bitfld.long 0x0 0.--1. "MFLAG_CTRL,MFLAG_CTRL for DMA master port" "0,1,2,3" line.long 0x4 "COMMON_DISPC_GLOBAL_OUTPUT_ENABLE,DISPC global output enable register. The ENABLE or GO bit for a particular output port is set when either the corresponding bit in this register is set or the corresponding bit within the sub-module is set. This register.." bitfld.long 0x4 16.--18. "VP_GO,Global GO Command for the VP[2:0] output. It is used to synchronize the pipelines associated with the VP output. wr: immediate" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "VP_ENABLE,Global VP[2:0] Enable" "0,1,2,3,4,5,6,7" line.long 0x8 "COMMON_DISPC_GLOBAL_BUFFER,The register configures the DMA buffers allocations to the pipelines for DMA" bitfld.long 0x8 31. "BUFFERFILLING,Controls if the DMA buffers are re-filled only when the LOW threshold is reached or if all DMA buffers are re-filled when at least one of them reaches the LOW threshold" "0,1" bitfld.long 0x8 3.--5. "VIDL1_BUFFER,VIDL1 DMA buffer allocation to one of the pipelines" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "VID_BUFFER,VID DMA buffer allocation to one of the pipelines" "0,1,2,3,4,5,6,7" line.long 0xC "COMMON_DSS_CBA_CFG,This register contains CBA specific config bits in DSS" bitfld.long 0xC 6.--8. "RESERVED1,Reserved : TI internal" "0,1,2,3,4,5,6,7" bitfld.long 0xC 3.--5. "PRI_HI,The value sent out on the PRI_HI bus from DSS to CBA Indicates the priority level for high-priority [MFLAG] transactions. Value of 0x0 indicates highest priority Value of 0x7 indicates lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--2. "PRI_LO,The value sent out on the PRI_LO bus from DSS to CBA Indicates the priority level for normal [non-MFLAG] transactions. Value of 0x0 indicates highest priority Value of 0x7 indicates lowest priority" "0,1,2,3,4,5,6,7" line.long 0x10 "COMMON_DISPC_DBG_CONTROL,DISPC debug status control register" hexmask.long.byte 0x10 1.--8. 1. "DBGMUXSEL,Mux select for the debug status" bitfld.long 0x10 0. "DBGEN,Enable debug ports" "0,1" rgroup.long 0xA4++0x3 line.long 0x0 "COMMON_DISPC_DBG_STATUS,DISPC debug status register" hexmask.long 0x0 0.--31. 1. "DBGOUT,Debug status" group.long 0xA8++0x7 line.long 0x0 "COMMON_DISPC_CLKGATING_DISABLE,Register to control clock gating at DISPC sub-module level" bitfld.long 0x0 18.--19. "VP,Clock gating control for VP[2:0]" "0,1,2,3" bitfld.long 0x0 14.--15. "OVR,Clock gating control for OVR[2:0]" "0,1,2,3" bitfld.long 0x0 3.--4. "VID,Clock gating control for VID" "0,1,2,3" newline bitfld.long 0x0 0. "DMA,Clock gating control for DMA" "0,1" line.long 0x4 "COMMON_DISPC_SECURE_DISABLE,Disable security settings throughout DSS IP. COMMON_1.DISPC_SECURE bits are honoured only if COMMON.DISPC_SECURE_DISABLE =0" bitfld.long 0x4 0. "SECURE_DISABLE,Secure disable bit" "0,1" tree.end tree "DSS0_COMMON1" base ad:0x30201000 group.long 0x24++0xF line.long 0x0 "COMMON1_DISPC_IRQ_EOI,End Of Interrupt number" hexmask.long 0x0 1.--31. 1. "RESERVED" bitfld.long 0x0 0. "EOI,Software End Of Interrupt [EOI] control if pulse interrupts are used. Write 1 to acknowledge interrupt" "0,1" line.long 0x4 "COMMON1_DISPC_IRQSTATUS_RAW,RAW Interrupt status. Raw status is set even if interrupt is not enabled. Write 1 to set the RAW status" bitfld.long 0x4 4.--5. "VID_IRQ,VID IRQ STATUS. Register indicates the VIDEO pipeline[s] interrupt events" "0,1,2,3" bitfld.long 0x4 0.--1. "VP_IRQ,VP IRQ STATUS. Register indicates the Video Port[s] interrupt events" "0,1,2,3" line.long 0x8 "COMMON1_DISPC_IRQSTATUS,Interrupt status. Enabled status. isn't set unless event is enabled. Write 1 to clear the status after interrupt has been serviced. RAW status also gets cleared. i.e. even if not enabled" bitfld.long 0x8 4.--5. "VID_IRQ,VID IRQ STATUS. Register indicates the VIDEO pipeline[s] interrupt events" "0,1,2,3" bitfld.long 0x8 0.--1. "VP_IRQ,VP IRQ STATUS. Register indicates the Video Port[s] interrupt events" "0,1,2,3" line.long 0xC "COMMON1_DISPC_IRQENABLE_SET,SET Interrupt enable. Write 1 to set interrupt enable. Readout equal to corresponding _CLR register" bitfld.long 0xC 4.--5. "SET_VID_IRQ,VID IRQ" "0,1,2,3" bitfld.long 0xC 0.--1. "SET_VP_IRQ,VP IRQ" "0,1,2,3" group.long 0x40++0xB line.long 0x0 "COMMON1_DISPC_IRQENABLE_CLR,CLR Interrupt enable. Write 1 to clear interrupt enable" bitfld.long 0x0 4.--5. "CLR_VID_IRQ,VID IRQ" "0,1,2,3" bitfld.long 0x0 0.--1. "CLR_VP_IRQ,VP IRQ" "0,1,2,3" line.long 0x4 "COMMON1_VID_IRQENABLE_0,This register allows to mask/unmask the VID_0 internal sources of interrupt. on an event-by-event basis" bitfld.long 0x4 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x4 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x4 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x8 "COMMON1_VID_IRQENABLE_1,This register allows to mask/unmask the VIDL_0 internal sources of interrupt. on an event-by-event basis" bitfld.long 0x8 2. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x8 1. "VIDENDWINDOW_EN,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x8 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" group.long 0x54++0xB line.long 0x0 "COMMON1_DISPC_SECURE,Security bit settings for different DISPC sub-modules" bitfld.long 0x0 15.--16. "OVR_SECURE,Secure bit for OVR" "0,1,2,3" bitfld.long 0x0 4.--5. "VID_SECURE,Secure bit for VID" "0,1,2,3" bitfld.long 0x0 0.--1. "VP_SECURE,Secure bit for VP [Unused in K3_DSS]" "0,1,2,3" line.long 0x4 "COMMON1_VID_IRQSTATUS_0,This register groups all the status of the VID_0 internal events that generate an interrupt. Write 1 to a clear a bit field" bitfld.long 0x4 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x4 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x4 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" line.long 0x8 "COMMON1_VID_IRQSTATUS_1,This register groups all the status of the VID_0 internal events that generate an interrupt. Write 1 to a clear a bit field" bitfld.long 0x8 2. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" "0,1" bitfld.long 0x8 1. "VIDENDWINDOW_IRQ,Video End Window. This is raised by the DMA engine when the full video data has been sent to the pipeline" "0,1" bitfld.long 0x8 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow. This is raised when the DMA buffer does not have the data requested by the Video pipeline" "0,1" group.long 0x70++0x7 line.long 0x0 "COMMON1_VP_IRQENABLE_0,This register allows to mask/unmask the VP_0 internal sources of interrupt. on an event-by-event basis" bitfld.long 0x0 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x0 11. "VPSYNC_EN,Go bit clear event" "0,1" bitfld.long 0x0 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x0 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" newline bitfld.long 0x0 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" bitfld.long 0x0 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x0 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x0 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" newline bitfld.long 0x0 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" bitfld.long 0x0 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" line.long 0x4 "COMMON1_VP_IRQENABLE_1,This register allows to mask/unmask the VP_1 internal sources of interrupt. on an event-by-event basis" bitfld.long 0x4 12. "DUMMY_EN,Dummy IRQ for future use" "0,1" bitfld.long 0x4 11. "VPSYNC_EN,Go bit clear event" "0,1" bitfld.long 0x4 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x4 6.--9. 1. "SAFETYREGION_EN,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" newline bitfld.long 0x4 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1" bitfld.long 0x4 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1" bitfld.long 0x4 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x4 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1" newline bitfld.long 0x4 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1" bitfld.long 0x4 0. "VPFRAMEDONE_EN,Frame Done for Video Port. VP output has been disabled by user. All the data have been sent" "0,1" group.long 0x7C++0x7 line.long 0x0 "COMMON1_VP_IRQSTATUS_0,This register groups all the status of the VP_0 internal events that generate an interrupt. Write 1 to a given bit resets this bit" bitfld.long 0x0 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x0 11. "VPSYNC_IRQ,Go bit clear event" "0,1" bitfld.long 0x0 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x0 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" newline bitfld.long 0x0 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" bitfld.long 0x0 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x0 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x0 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" newline bitfld.long 0x0 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" bitfld.long 0x0 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" line.long 0x4 "COMMON1_VP_IRQSTATUS_1,This register groups all the status of the VP_1 internal events that generate an interrupt. Write 1 to a given bit resets this bit" bitfld.long 0x4 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1" bitfld.long 0x4 11. "VPSYNC_IRQ,Go bit clear event" "0,1" bitfld.long 0x4 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ. Non-secure OVR/VP connected to secure VID" "0,1" hexmask.long.byte 0x4 6.--9. 1. "SAFETYREGION_IRQ,Safety Feature IRQ. This is raised when FrameFreeze is detected or data mismatch occurs within the safety region" newline bitfld.long 0x4 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1" bitfld.long 0x4 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with VP output" "0,1" bitfld.long 0x4 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number. It indicates that the scan of the display has reached the programmed user line number" "0,1" bitfld.long 0x4 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field. For interlace mode only" "0,1" newline bitfld.long 0x4 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output. It is used as VSYNC_EVEN in case of interlace mode" "0,1" bitfld.long 0x4 0. "VPFRAMEDONE_IRQ,Frame Done for VP. VP output has been disabled by user All the data have been sent" "0,1" tree.end tree "DSS0_OVR1" base ad:0x30207000 group.long 0x0++0x3 line.long 0x0 "OVR1_CONFIG,The control register configures the Display Controller module for the VP output. Shadow register" hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED1" rbitfld.long 0x0 13. "RESERVED3" "0,1" rbitfld.long 0x0 12. "RESERVED2" "0,1" bitfld.long 0x0 11. "TCKLCDSELECTION,Transparency Color Key Selection" "0,1" bitfld.long 0x0 10. "TCKLCDENABLE,Transparency Color Key Enable" "0,1" newline hexmask.long.byte 0x0 2.--9. 1. "RESERVED" bitfld.long 0x0 1. "COLORBAREN,Enable the Color-Bar" "0,1" rbitfld.long 0x0 0. "RESERVED6" "0,1" group.long 0x8++0x27 line.long 0x0 "OVR1_DEFAULT_COLOR,The control register configures the default solid background color LSB[31:0]. Shadow register" hexmask.long 0x0 0.--31. 1. "DEFAULTCOLOR,32-bit LSB of ARGB background color" line.long 0x4 "OVR1_DEFAULT_COLOR2,The control register configures the default solid background color MSB[47:32]. Shadow register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "DEFAULTCOLOR,16-bit MSB of ARGB background color" line.long 0x8 "OVR1_TRANS_COLOR_MAX,The register sets the max transparency color value for the overlays. Shadow register" hexmask.long 0x8 0.--31. 1. "TRANSCOLORKEY,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format" line.long 0xC "OVR1_TRANS_COLOR_MAX2,The register sets the max transparency color value for the overlays. Shadow register" hexmask.long 0xC 4.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--3. 1. "TRANSCOLORKEY,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" line.long 0x10 "OVR1_TRANS_COLOR_MIN,The register sets the min transparency color value for the overlays. Shadow register" hexmask.long 0x10 0.--31. 1. "TRANSCOLORKEY,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format" line.long 0x14 "OVR1_TRANS_COLOR_MIN2,The register sets the min transparency color value for the overlays. Shadow register" hexmask.long 0x14 4.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--3. 1. "TRANSCOLORKEY,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" line.long 0x18 "OVR1_ATTRIBUTES_0,The register configures the attributes of layer-0. ZORDER= 0. of the Overlay manager. Shadow register" rbitfld.long 0x18 31. "RESERVED1" "0,1" hexmask.long.word 0x18 19.--30. 1. "POSY,Y position of the layer. Encoded value [from 0 to 4095] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" rbitfld.long 0x18 18. "RESERVED" "0,1" hexmask.long.word 0x18 6.--17. 1. "POSX,X position of the layer. Encoded value [from 0 to 4095] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" rbitfld.long 0x18 5. "RESERVED2" "0,1" newline hexmask.long.byte 0x18 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x18 0. "ENABLE,Layer Enable" "0,1" line.long 0x1C "OVR1_ATTRIBUTES_1,The register configures the attributes of layer-1. ZORDER= 1. of the Overlay manager. Shadow register" rbitfld.long 0x1C 31. "RESERVED1" "0,1" hexmask.long.word 0x1C 19.--30. 1. "POSY,Y position of the layer. Encoded value [from 0 to 4095] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" rbitfld.long 0x1C 18. "RESERVED" "0,1" hexmask.long.word 0x1C 6.--17. 1. "POSX,X position of the layer. Encoded value [from 0 to 4095] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" rbitfld.long 0x1C 5. "RESERVED2" "0,1" newline hexmask.long.byte 0x1C 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x1C 0. "ENABLE,Layer Enable" "0,1" line.long 0x20 "OVR1_ATTRIBUTES_2,The register configures the attributes of layer-2. ZORDER= 2. of the Overlay manager. Shadow register" rbitfld.long 0x20 31. "RESERVED1" "0,1" hexmask.long.word 0x20 19.--30. 1. "POSY,Y position of the layer. Encoded value [from 0 to 4095] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" rbitfld.long 0x20 18. "RESERVED" "0,1" hexmask.long.word 0x20 6.--17. 1. "POSX,X position of the layer. Encoded value [from 0 to 4095] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" rbitfld.long 0x20 5. "RESERVED2" "0,1" newline hexmask.long.byte 0x20 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x20 0. "ENABLE,Layer Enable" "0,1" line.long 0x24 "OVR1_ATTRIBUTES_3,The register configures the attributes of layer-3. ZORDER= 3. of the Overlay manager. Shadow register" rbitfld.long 0x24 31. "RESERVED1" "0,1" hexmask.long.word 0x24 19.--30. 1. "POSY,Y position of the layer. Encoded value [from 0 to 4095] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" rbitfld.long 0x24 18. "RESERVED" "0,1" hexmask.long.word 0x24 6.--17. 1. "POSX,X position of the layer. Encoded value [from 0 to 4095] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" rbitfld.long 0x24 5. "RESERVED2" "0,1" newline hexmask.long.byte 0x24 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x24 0. "ENABLE,Layer Enable" "0,1" tree.end tree "DSS0_OVR2" base ad:0x30208000 group.long 0x0++0x3 line.long 0x0 "OVR2_CONFIG,The control register configures the Display Controller module for the VP output. Shadow register" hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED1" rbitfld.long 0x0 13. "RESERVED3" "0,1" rbitfld.long 0x0 12. "RESERVED2" "0,1" bitfld.long 0x0 11. "TCKLCDSELECTION,Transparency Color Key Selection" "0,1" bitfld.long 0x0 10. "TCKLCDENABLE,Transparency Color Key Enable" "0,1" newline hexmask.long.byte 0x0 2.--9. 1. "RESERVED" bitfld.long 0x0 1. "COLORBAREN,Enable the Color-Bar" "0,1" rbitfld.long 0x0 0. "RESERVED6" "0,1" group.long 0x8++0x27 line.long 0x0 "OVR2_DEFAULT_COLOR,The control register configures the default solid background color LSB[31:0]. Shadow register" hexmask.long 0x0 0.--31. 1. "DEFAULTCOLOR,32-bit LSB of ARGB background color" line.long 0x4 "OVR2_DEFAULT_COLOR2,The control register configures the default solid background color MSB[47:32]. Shadow register" hexmask.long.word 0x4 16.--31. 1. "RESERVED" hexmask.long.word 0x4 0.--15. 1. "DEFAULTCOLOR,16-bit MSB of ARGB background color" line.long 0x8 "OVR2_TRANS_COLOR_MAX,The register sets the max transparency color value for the overlays. Shadow register" hexmask.long 0x8 0.--31. 1. "TRANSCOLORKEY,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format" line.long 0xC "OVR2_TRANS_COLOR_MAX2,The register sets the max transparency color value for the overlays. Shadow register" hexmask.long 0xC 4.--31. 1. "RESERVED" hexmask.long.byte 0xC 0.--3. 1. "TRANSCOLORKEY,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" line.long 0x10 "OVR2_TRANS_COLOR_MIN,The register sets the min transparency color value for the overlays. Shadow register" hexmask.long 0x10 0.--31. 1. "TRANSCOLORKEY,LSB[31:0]. Transparency Color Key Value in 36-bit RGB format" line.long 0x14 "OVR2_TRANS_COLOR_MIN2,The register sets the min transparency color value for the overlays. Shadow register" hexmask.long 0x14 4.--31. 1. "RESERVED" hexmask.long.byte 0x14 0.--3. 1. "TRANSCOLORKEY,MSB[35:32]. Transparency Color Key Value in 36-bit RGB format" line.long 0x18 "OVR2_ATTRIBUTES_0,The register configures the attributes of layer-0. ZORDER= 0. of the Overlay manager. Shadow register" rbitfld.long 0x18 31. "RESERVED1" "0,1" hexmask.long.word 0x18 19.--30. 1. "POSY,Y position of the layer. Encoded value [from 0 to 4095] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" rbitfld.long 0x18 18. "RESERVED" "0,1" hexmask.long.word 0x18 6.--17. 1. "POSX,X position of the layer. Encoded value [from 0 to 4095] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" rbitfld.long 0x18 5. "RESERVED2" "0,1" newline hexmask.long.byte 0x18 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x18 0. "ENABLE,Layer Enable" "0,1" line.long 0x1C "OVR2_ATTRIBUTES_1,The register configures the attributes of layer-1. ZORDER= 1. of the Overlay manager. Shadow register" rbitfld.long 0x1C 31. "RESERVED1" "0,1" hexmask.long.word 0x1C 19.--30. 1. "POSY,Y position of the layer. Encoded value [from 0 to 4095] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" rbitfld.long 0x1C 18. "RESERVED" "0,1" hexmask.long.word 0x1C 6.--17. 1. "POSX,X position of the layer. Encoded value [from 0 to 4095] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" rbitfld.long 0x1C 5. "RESERVED2" "0,1" newline hexmask.long.byte 0x1C 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x1C 0. "ENABLE,Layer Enable" "0,1" line.long 0x20 "OVR2_ATTRIBUTES_2,The register configures the attributes of layer-2. ZORDER= 2. of the Overlay manager. Shadow register" rbitfld.long 0x20 31. "RESERVED1" "0,1" hexmask.long.word 0x20 19.--30. 1. "POSY,Y position of the layer. Encoded value [from 0 to 4095] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" rbitfld.long 0x20 18. "RESERVED" "0,1" hexmask.long.word 0x20 6.--17. 1. "POSX,X position of the layer. Encoded value [from 0 to 4095] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" rbitfld.long 0x20 5. "RESERVED2" "0,1" newline hexmask.long.byte 0x20 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x20 0. "ENABLE,Layer Enable" "0,1" line.long 0x24 "OVR2_ATTRIBUTES_3,The register configures the attributes of layer-3. ZORDER= 3. of the Overlay manager. Shadow register" rbitfld.long 0x24 31. "RESERVED1" "0,1" hexmask.long.word 0x24 19.--30. 1. "POSY,Y position of the layer. Encoded value [from 0 to 4095] to specify the Y position of the layer on the screen. The line at the top has the Y-position 0" rbitfld.long 0x24 18. "RESERVED" "0,1" hexmask.long.word 0x24 6.--17. 1. "POSX,X position of the layer. Encoded value [from 0 to 4095] to specify the X position of the layer on the screen. The first pixel on the left of the screen has the X-position 0" rbitfld.long 0x24 5. "RESERVED2" "0,1" newline hexmask.long.byte 0x24 1.--4. 1. "CHANNELIN,Input channel connected to Layer" bitfld.long 0x24 0. "ENABLE,Layer Enable" "0,1" tree.end tree "DSS0_VID" base ad:0x30206000 group.long 0x0++0x37 line.long 0x0 "VID_ACCUH_0,The register configures the resize accumulator init values for horizontal up/down-sampling of the video window. DISPC_VIDx_ACCU__0 & DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field polarity. This register.." hexmask.long.tbyte 0x0 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x4 "VID_ACCUH_1,The register configures the resize accumulator init values for horizontal up/down-sampling of the video window. DISPC_VIDx_ACCU__0 & DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field polarity. This register.." hexmask.long.tbyte 0x4 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x8 "VID_ACCUH2_0,The register configures the resize accumulator init value for horizontal up/down-sampling of the video window. DISPC_VID n_ACCU2__0 & DISPC_VID n_ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity. This.." hexmask.long.tbyte 0x8 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0xC "VID_ACCUH2_1,The register configures the resize accumulator init value for horizontal up/down-sampling of the video window. DISPC_VID n_ACCU2__0 & DISPC_VID n_ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity. This.." hexmask.long.tbyte 0xC 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value" line.long 0x10 "VID_ACCUV_0,The register configures the resize accumulator init values for horizontal and vertical up/down-sampling of the video window. DISPC_VIDx_ACCU__0 & DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field polarity." hexmask.long.tbyte 0x10 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x14 "VID_ACCUV_1,The register configures the resize accumulator init values for horizontal and vertical up/down-sampling of the video window. DISPC_VIDx_ACCU__0 & DISPC_VIDx_ACCU__1 for ping-pong mechanism with external trigger. based on the field polarity." hexmask.long.tbyte 0x14 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x18 "VID_ACCUV2_0,The register configures the resize accumulator init value for vertical up/down-sampling of the video window. ACCU2__0 & ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity. It is used for U/V components for.." hexmask.long.tbyte 0x18 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x1C "VID_ACCUV2_1,The register configures the resize accumulator init value for vertical up/down-sampling of the video window. ACCU2__0 & ACCU2__1 for ping-pong mechanism with external trigger. based on the field polarity. It is used for U/V components for.." hexmask.long.tbyte 0x1C 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value" line.long 0x20 "VID_ATTRIBUTES,The register configures the attributes of the video window. Shadow register" bitfld.long 0x20 31. "LUMAKEYENABLE,Enable Luma Key transparency matching" "0,1" bitfld.long 0x20 30. "GAMMAINVERSION,Inverse Gamma support [using the CLUT table]" "0,1" newline bitfld.long 0x20 28. "PREMULTIPLYALPHA,The field configures the DISPC VID to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data" "0,1" bitfld.long 0x20 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "0,1" newline bitfld.long 0x20 23. "ARBITRATION,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipelines. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there are only normal.." "0,1" bitfld.long 0x20 21. "VERTICALTAPS,Video Vertical Resize Tap Number. The vertical poly-phase filter can be configured in 3-tap or 5-tap configuration. According to the number of taps the maximum input picture width is double while using 3-tap compared to 5-tap" "0,1" newline bitfld.long 0x20 19. "BUFPRELOAD,Video Preload Value" "0,1" rbitfld.long 0x20 18. "RESERVED7,Write 0's for future compatibility. Reads return 0" "0,1" newline bitfld.long 0x20 17. "SELFREFRESHAUTO,Automatic self refresh mode" "0,1" bitfld.long 0x20 12. "FLIP,Describes the frame buffer flip operation" "0,1" newline bitfld.long 0x20 11. "FULLRANGE,Color Space Conversion full range setting" "0,1" bitfld.long 0x20 10. "NIBBLEMODE,Video Nibble mode [only for 1- 2- and 4-bpp]" "0,1" newline bitfld.long 0x20 9. "COLORCONVENABLE,Enable the color space conversion. The HW does not enable/disable the conversion based on the pixel format" "0,1" bitfld.long 0x20 7.--8. "RESIZEENABLE,Video Resize Enable" "0,1,2,3" newline hexmask.long.byte 0x20 1.--6. 1. "FORMAT,Video Format. It defines the pixel format when fetching the video frame buffer" bitfld.long 0x20 0. "ENABLE,Video pipeline Enable" "0,1" line.long 0x24 "VID_ATTRIBUTES2,The register configures the attributes of the video window. Shadow register" hexmask.long.byte 0x24 26.--30. 1. "TAGS,Number of OCP TAGS to be used for the pipeline [from 0x0 to 0xF]. A value of 0x0 means only a single tag will be used. A value of 0xF means all 16 tags can be used" bitfld.long 0x24 10. "YUV_ALIGN,Alignment [MSB or LSB align] for unpacked 10b/12b YUV data" "0,1" newline bitfld.long 0x24 9. "YUV_MODE,Mode of packing for YUV data [only for 10b/12b formats]" "0,1" bitfld.long 0x24 7.--8. "YUV_SIZE,Size of YUV data 8b/10b/12b" "0,1,2,3" newline bitfld.long 0x24 4.--6. "VC1_RANGE_CBCR,Defines the VC1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7" bitfld.long 0x24 1.--3. "VC1_RANGE_Y,Defines the VC1 range value for the Y component from 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "VC1ENABLE,Enable/disable the VC1 range mapping processing. The bit-field is ignored if the format is not one of the supported YUV formats" "0,1" line.long 0x28 "VID_BA_0,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV. this is the BA. In case of two plane YUV. this is the BA_Y. In case of two plane RGB565-A8. this is the BA_Alpha. BA__0 & BA__1 for.." hexmask.long 0x28 0.--31. 1. "BA,Video base address. Base address of the video buffer [Aligned on pixel size boundary except for the following. In case of RGB24 packed format 4-pixel alignment is required. In case of YUV422 2-pixel alignment is required. In case of YUV420 byte.." line.long 0x2C "VID_BA_1,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV. this is the BA. In case of two plane YUV. this is the BA_Y. In case of two plane RGB565-A8. this is the BA_Alpha. BA__0 & BA__1 for.." hexmask.long 0x2C 0.--31. 1. "BA,Video base address. Base address of the video buffer [Aligned on pixel size boundary except for the following. In case of RGB24 packed format 4-pixel alignment is required. In case of YUV422 2-pixel alignment is required. In case of YUV420 byte.." line.long 0x30 "VID_BA_UV_0,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger. based on the field polarity otherwise.." hexmask.long 0x30 0.--31. 1. "BA,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV420-NV12" line.long 0x34 "VID_BA_UV_1,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger. based on the field polarity otherwise.." hexmask.long 0x34 0.--31. 1. "BA,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV420-NV12" rgroup.long 0x38++0x3 line.long 0x0 "VID_BUF_SIZE_STATUS,The register returns the Video buffer size for the video pipeline" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x0 0.--15. 1. "BUFSIZE,Video DMA buffer Size in number of 128-bits" group.long 0x3C++0x1C3 line.long 0x0 "VID_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline. Shadow register" hexmask.long.word 0x0 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold. Number of 128-bits defining the threshold value" hexmask.long.word 0x0 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer Low Threshold. Number of 128-bits defining the threshold value" line.long 0x4 "VID_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x4 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x4 16.--26. 1. "C01,C01 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x4 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x4 0.--10. 1. "C00,C00 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x8 "VID_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x8 16.--26. 1. "C10,C10 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x8 0.--10. 1. "C02,C02 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0xC "VID_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0xC 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0xC 16.--26. 1. "C12,C12 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0xC 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0xC 0.--10. 1. "C11,C11 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x10 "VID_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "VID_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.tbyte 0x14 11.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x18 "VID_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset. Encoded signed value [from -4096 to 4095]" line.long 0x1C "VID_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]" line.long 0x20 "VID_FIRH,The register configures the resize factor for horizontal up/down-sampling of the video window. It is used for ARGB and Y setting. Shadow register" hexmask.long.tbyte 0x20 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter. The value 0 is invalid" line.long 0x24 "VID_FIRH2,The register configures the resize factor for horizontal up/down-sampling of the video window. It is used for U/V components for YUV 422 and 420 input formats. It is not used if input format is any RGB format. Shadow register" hexmask.long.tbyte 0x24 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter for Cb and Cr. The value 0 is invalid" line.long 0x28 "VID_FIRV,The register configures the resize factor for vertical up/down-sampling of the video window. It is used for ARGB and Y setting. Shadow register" hexmask.long.tbyte 0x28 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter. The value 0 is invalid" line.long 0x2C "VID_FIRV2,The register configures the resize factor for vertical up/down-sampling of the video window. It is used for U/V components for YUV420 input format. It is not used when the input format is any RGB format or YUV422 format. Shadow register." hexmask.long.tbyte 0x2C 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter for Cb and Cr. The value 0 is invalid" line.long 0x30 "VID_FIR_COEF_H0_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x30 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 0" line.long 0x34 "VID_FIR_COEF_H0_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x34 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 1" line.long 0x38 "VID_FIR_COEF_H0_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x38 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 2" line.long 0x3C "VID_FIR_COEF_H0_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x3C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 3" line.long 0x40 "VID_FIR_COEF_H0_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x40 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 4" line.long 0x44 "VID_FIR_COEF_H0_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x44 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 5" line.long 0x48 "VID_FIR_COEF_H0_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x48 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 6" line.long 0x4C "VID_FIR_COEF_H0_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x4C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 7" line.long 0x50 "VID_FIR_COEF_H0_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x50 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 8" line.long 0x54 "VID_FIR_COEF_H0_C_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x54 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 0" line.long 0x58 "VID_FIR_COEF_H0_C_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x58 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 1" line.long 0x5C "VID_FIR_COEF_H0_C_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x5C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 2" line.long 0x60 "VID_FIR_COEF_H0_C_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x60 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 3" line.long 0x64 "VID_FIR_COEF_H0_C_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x64 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 4" line.long 0x68 "VID_FIR_COEF_H0_C_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x68 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 5" line.long 0x6C "VID_FIR_COEF_H0_C_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x6C 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 6" line.long 0x70 "VID_FIR_COEF_H0_C_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x70 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 7" line.long 0x74 "VID_FIR_COEF_H0_C_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x74 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 8" line.long 0x78 "VID_FIR_COEF_H12_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x78 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 0" hexmask.long.word 0x78 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 0" line.long 0x7C "VID_FIR_COEF_H12_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x7C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 1" hexmask.long.word 0x7C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 1" line.long 0x80 "VID_FIR_COEF_H12_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x80 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 2" hexmask.long.word 0x80 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 2" line.long 0x84 "VID_FIR_COEF_H12_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x84 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 3" hexmask.long.word 0x84 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 3" line.long 0x88 "VID_FIR_COEF_H12_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x88 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 4" hexmask.long.word 0x88 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 4" line.long 0x8C "VID_FIR_COEF_H12_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x8C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 5" hexmask.long.word 0x8C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 5" line.long 0x90 "VID_FIR_COEF_H12_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x90 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 6" hexmask.long.word 0x90 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 6" line.long 0x94 "VID_FIR_COEF_H12_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x94 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 7" hexmask.long.word 0x94 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 7" line.long 0x98 "VID_FIR_COEF_H12_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x98 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 8" hexmask.long.word 0x98 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 8" line.long 0x9C "VID_FIR_COEF_H12_9,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x9C 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 9" hexmask.long.word 0x9C 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 9" line.long 0xA0 "VID_FIR_COEF_H12_10,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xA0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 10" hexmask.long.word 0xA0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 10" line.long 0xA4 "VID_FIR_COEF_H12_11,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xA4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 11" hexmask.long.word 0xA4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 11" line.long 0xA8 "VID_FIR_COEF_H12_12,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xA8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 12" hexmask.long.word 0xA8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 12" line.long 0xAC "VID_FIR_COEF_H12_13,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xAC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 13" hexmask.long.word 0xAC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 13" line.long 0xB0 "VID_FIR_COEF_H12_14,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xB0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 14" hexmask.long.word 0xB0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 14" line.long 0xB4 "VID_FIR_COEF_H12_15,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xB4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 15" hexmask.long.word 0xB4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 15" line.long 0xB8 "VID_FIR_COEF_H12_C_0,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xB8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 0" hexmask.long.word 0xB8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 0" line.long 0xBC "VID_FIR_COEF_H12_C_1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xBC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 1" hexmask.long.word 0xBC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 1" line.long 0xC0 "VID_FIR_COEF_H12_C_2,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xC0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 2" hexmask.long.word 0xC0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 2" line.long 0xC4 "VID_FIR_COEF_H12_C_3,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xC4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 3" hexmask.long.word 0xC4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 3" line.long 0xC8 "VID_FIR_COEF_H12_C_4,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xC8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 4" hexmask.long.word 0xC8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 4" line.long 0xCC "VID_FIR_COEF_H12_C_5,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xCC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 5" hexmask.long.word 0xCC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 5" line.long 0xD0 "VID_FIR_COEF_H12_C_6,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xD0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 6" hexmask.long.word 0xD0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 6" line.long 0xD4 "VID_FIR_COEF_H12_C_7,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xD4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 7" hexmask.long.word 0xD4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 7" line.long 0xD8 "VID_FIR_COEF_H12_C_8,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xD8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 8" hexmask.long.word 0xD8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 8" line.long 0xDC "VID_FIR_COEF_H12_C_9,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xDC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 9" hexmask.long.word 0xDC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 9" line.long 0xE0 "VID_FIR_COEF_H12_C_10,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xE0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 10" hexmask.long.word 0xE0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 10" line.long 0xE4 "VID_FIR_COEF_H12_C_11,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xE4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 11" hexmask.long.word 0xE4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 11" line.long 0xE8 "VID_FIR_COEF_H12_C_12,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xE8 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 12" hexmask.long.word 0xE8 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 12" line.long 0xEC "VID_FIR_COEF_H12_C_13,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xEC 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 13" hexmask.long.word 0xEC 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 13" line.long 0xF0 "VID_FIR_COEF_H12_C_14,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xF0 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 14" hexmask.long.word 0xF0 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 14" line.long 0xF4 "VID_FIR_COEF_H12_C_15,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when.." hexmask.long.word 0xF4 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 15" hexmask.long.word 0xF4 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 15" line.long 0xF8 "VID_FIR_COEF_V0_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xF8 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 0" line.long 0xFC "VID_FIR_COEF_V0_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0xFC 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 1" line.long 0x100 "VID_FIR_COEF_V0_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x100 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 2" line.long 0x104 "VID_FIR_COEF_V0_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x104 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 3" line.long 0x108 "VID_FIR_COEF_V0_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x108 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 4" line.long 0x10C "VID_FIR_COEF_V0_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x10C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 5" line.long 0x110 "VID_FIR_COEF_V0_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x110 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 6" line.long 0x114 "VID_FIR_COEF_V0_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x114 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 7" line.long 0x118 "VID_FIR_COEF_V0_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x118 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 8" line.long 0x11C "VID_FIR_COEF_V0_C_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x11C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 0" line.long 0x120 "VID_FIR_COEF_V0_C_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x120 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 1" line.long 0x124 "VID_FIR_COEF_V0_C_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x124 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 2" line.long 0x128 "VID_FIR_COEF_V0_C_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x128 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 3" line.long 0x12C "VID_FIR_COEF_V0_C_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x12C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 4" line.long 0x130 "VID_FIR_COEF_V0_C_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x130 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 5" line.long 0x134 "VID_FIR_COEF_V0_C_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x134 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 6" line.long 0x138 "VID_FIR_COEF_V0_C_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x138 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 7" line.long 0x13C "VID_FIR_COEF_V0_C_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x13C 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 8" line.long 0x140 "VID_FIR_COEF_V12_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x140 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 0" hexmask.long.word 0x140 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 0" line.long 0x144 "VID_FIR_COEF_V12_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x144 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 1" hexmask.long.word 0x144 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 1" line.long 0x148 "VID_FIR_COEF_V12_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x148 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 2" hexmask.long.word 0x148 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 2" line.long 0x14C "VID_FIR_COEF_V12_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x14C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 3" hexmask.long.word 0x14C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 3" line.long 0x150 "VID_FIR_COEF_V12_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x150 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 4" hexmask.long.word 0x150 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 4" line.long 0x154 "VID_FIR_COEF_V12_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x154 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 5" hexmask.long.word 0x154 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 5" line.long 0x158 "VID_FIR_COEF_V12_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x158 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 6" hexmask.long.word 0x158 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 6" line.long 0x15C "VID_FIR_COEF_V12_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x15C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 7" hexmask.long.word 0x15C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 7" line.long 0x160 "VID_FIR_COEF_V12_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x160 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 8" hexmask.long.word 0x160 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 8" line.long 0x164 "VID_FIR_COEF_V12_9,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x164 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 9" hexmask.long.word 0x164 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 9" line.long 0x168 "VID_FIR_COEF_V12_10,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x168 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 10" hexmask.long.word 0x168 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 10" line.long 0x16C "VID_FIR_COEF_V12_11,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x16C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 11" hexmask.long.word 0x16C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 11" line.long 0x170 "VID_FIR_COEF_V12_12,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x170 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 12" hexmask.long.word 0x170 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 12" line.long 0x174 "VID_FIR_COEF_V12_13,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x174 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 13" hexmask.long.word 0x174 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 13" line.long 0x178 "VID_FIR_COEF_V12_14,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x178 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 14" hexmask.long.word 0x178 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 14" line.long 0x17C "VID_FIR_COEF_V12_15,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases. It is used for ARGB and Y setting. Shadow register" hexmask.long.word 0x17C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 15" hexmask.long.word 0x17C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 15" line.long 0x180 "VID_FIR_COEF_V12_C_0,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x180 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 0" hexmask.long.word 0x180 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 0" line.long 0x184 "VID_FIR_COEF_V12_C_1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x184 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 1" hexmask.long.word 0x184 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 1" line.long 0x188 "VID_FIR_COEF_V12_C_2,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x188 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 2" hexmask.long.word 0x188 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 2" line.long 0x18C "VID_FIR_COEF_V12_C_3,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x18C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 3" hexmask.long.word 0x18C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 3" line.long 0x190 "VID_FIR_COEF_V12_C_4,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x190 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 4" hexmask.long.word 0x190 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 4" line.long 0x194 "VID_FIR_COEF_V12_C_5,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x194 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 5" hexmask.long.word 0x194 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 5" line.long 0x198 "VID_FIR_COEF_V12_C_6,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x198 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 6" hexmask.long.word 0x198 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 6" line.long 0x19C "VID_FIR_COEF_V12_C_7,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x19C 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 7" hexmask.long.word 0x19C 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 7" line.long 0x1A0 "VID_FIR_COEF_V12_C_8,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x1A0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 8" hexmask.long.word 0x1A0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 8" line.long 0x1A4 "VID_FIR_COEF_V12_C_9,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x1A4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 9" hexmask.long.word 0x1A4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 9" line.long 0x1A8 "VID_FIR_COEF_V12_C_10,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x1A8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 10" hexmask.long.word 0x1A8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 10" line.long 0x1AC "VID_FIR_COEF_V12_C_11,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x1AC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 11" hexmask.long.word 0x1AC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 11" line.long 0x1B0 "VID_FIR_COEF_V12_C_12,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x1B0 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 12" hexmask.long.word 0x1B0 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 12" line.long 0x1B4 "VID_FIR_COEF_V12_C_13,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x1B4 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 13" hexmask.long.word 0x1B4 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 13" line.long 0x1B8 "VID_FIR_COEF_V12_C_14,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x1B8 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 14" hexmask.long.word 0x1B8 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 14" line.long 0x1BC "VID_FIR_COEF_V12_C_15,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15. It is used for Crb and Cr setting. It is used only when the.." hexmask.long.word 0x1BC 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 15" hexmask.long.word 0x1BC 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 15" line.long 0x1C0 "VID_GLOBAL_ALPHA,The register defines the global alpha value for the video pipeline. Shadow register" hexmask.long.byte 0x1C0 0.--7. 1. "GLOBALALPHA,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 corresponds to fully opaque" group.long 0x208++0xB line.long 0x0 "VID_MFLAG_THRESHOLD,MFLAG_THRESHOLD Register" hexmask.long.word 0x0 16.--31. 1. "HT_MFLAG,MFlag High Threshold" hexmask.long.word 0x0 0.--15. 1. "LT_MFLAG,MFlag Low Threshold" line.long 0x4 "VID_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer before up/down-scaling. Shadow register" hexmask.long.word 0x4 16.--27. 1. "MEMSIZEY,Number of lines of the video picture Encoded value [from 1 to 4096] to specify the number of lines of the video picture in memory [program to value minus one] When predecimation is set the value represents the size of the image after.." hexmask.long.word 0x4 0.--11. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value [from 1 to 4096] to specify the number of pixels of the video picture in memory [program to value minus one]. The size is limited to the size of the line buffer of the vertical sampling block.." line.long 0x8 "VID_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window. Shadow register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.byte 0x8 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels Encoded unsigned value [from 1 to 255] to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid The value 1 means next pixel The value 1+n*bpp means increment.." group.long 0x218++0xB line.long 0x0 "VID_PRELOAD,The register configures the DMA buffer of the video pipeline. Shadow register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x0 0.--11. 1. "PRELOAD,DMA buffer preload value Number of 128-bit words defining the preload value" line.long 0x4 "VID_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window. For YUV420 formats this corresponds to the Y Buffer. Shadow register" hexmask.long 0x4 0.--31. 1. "ROWINC,Number of bytes to increment at the end of the row Encoded signed value [from -2^31-1 to 2^31] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value.." line.long 0x8 "VID_SIZE,The register configures the size of the video window. Shadow register" hexmask.long.word 0x8 16.--27. 1. "SIZEY,Number of lines of the video window Encoded value [from 1 to 4096] to specify the number of lines of the video window [program size -1]" hexmask.long.word 0x8 0.--11. 1. "SIZEX,Number of pixels of the video window Encoded value [from 1 to 4096] to specify the number of pixels of the video window [program size -1]" group.long 0x22C++0x13 line.long 0x0 "VID_BA_EXT_0,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 : For.." hexmask.long.word 0x0 0.--15. 1. "BA_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x4 "VID_BA_EXT_1,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 : For.." hexmask.long.word 0x4 0.--15. 1. "BA_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x8 "VID_BA_UV_EXT_0,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger. based on the field polarity. Shadow register" hexmask.long.word 0x8 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0xC "VID_BA_UV_EXT_1,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger. based on the field polarity. Shadow register" hexmask.long.word 0xC 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x10 "VID_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x10 19.--31. 1. "POSTOFFSET3,Row-3 post-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x10 3.--15. 1. "POSTOFFSET2,Row-2 post-offset. Encoded signed value [from -4096 to 4095]" group.long 0x248++0x3 line.long 0x0 "VID_ROW_INC_UV,The register configures the number of bytes to increment at the end of the row for the UV buffer associated with the video window for YUV420 formats. For non-YUV420 formats this register is unused. Shadow register" hexmask.long 0x0 0.--31. 1. "ROWINC,Number of bytes to increment at the end of the row Encoded signed value [from -2^31-1 to 2^31] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid The value 1 means next pixel. The value.." wgroup.long 0x260++0x3F line.long 0x0 "VID_CLUT_0,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x0 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x0 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x0 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x0 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x4 "VID_CLUT_1,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x4 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x4 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x4 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x4 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x8 "VID_CLUT_2,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x8 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x8 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x8 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x8 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0xC "VID_CLUT_3,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0xC 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0xC 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0xC 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0xC 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x10 "VID_CLUT_4,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x10 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x10 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x10 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x10 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x14 "VID_CLUT_5,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x14 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x14 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x14 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x14 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x18 "VID_CLUT_6,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x18 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x18 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x18 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x18 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x1C "VID_CLUT_7,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x1C 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x1C 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x1C 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x1C 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x20 "VID_CLUT_8,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x20 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x20 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x20 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x20 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x24 "VID_CLUT_9,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x24 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x24 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x24 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x24 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x28 "VID_CLUT_10,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x28 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x28 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x28 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x28 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x2C "VID_CLUT_11,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x2C 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x2C 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x2C 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x2C 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x30 "VID_CLUT_12,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x30 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x30 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x30 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x30 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x34 "VID_CLUT_13,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x34 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x34 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x34 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x34 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x38 "VID_CLUT_14,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x38 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x38 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x38 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x38 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x3C "VID_CLUT_15,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x3C 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x3C 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x3C 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x3C 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" group.long 0x2A0++0x3 line.long 0x0 "VID_SAFETY_ATTRIBUTES,The register configures the safety sub-region. Shadow register" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED" bitfld.long 0x0 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x0 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur. Note: The freeze frame counter is cleared on reset -OR- MISR.." bitfld.long 0x0 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x0 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" bitfld.long 0x0 0. "ENABLE,Safety check Enable for the region. Note: Transition from 0 to 1 clears the signature register" "0,1" rgroup.long 0x2A4++0x3 line.long 0x0 "VID_SAFETY_CAPT_SIGNATURE,The register captures the signature from the MISR of the safety sub-region. Shadow register" hexmask.long 0x0 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" group.long 0x2A8++0x13 line.long 0x0 "VID_SAFETY_POSITION,The register configures the position of the safety sub-region. Shadow register" hexmask.long.word 0x0 16.--27. 1. "POSY,Y position of the safety sub-region. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0" hexmask.long.word 0x0 0.--11. 1. "POSX,X position of the safety sub-region. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x4 "VID_SAFETY_REF_SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" hexmask.long 0x4 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" line.long 0x8 "VID_SAFETY_SIZE,The register configures the size of the safety sub-region. Shadow register" hexmask.long.word 0x8 16.--27. 1. "SIZEY,Height of the safety sub-region. Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen. One line height region has value of 0" hexmask.long.word 0x8 0.--11. 1. "SIZEX,Width of the safety sub-region. Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen. One pixel wide region has value of 0" line.long 0xC "VID_SAFETY_LFSR_SEED,The register configures the seed [initial value] of the MISR. Otherwise. the MISR is initialized with 0xFFFF_FFFF. Shadow register" hexmask.long 0xC 0.--31. 1. "SEED,The register configures the seed [initial value] of the MISR. Otherwise the MISR is initialized with 0xFFFF_FFFF. Shadow register" line.long 0x10 "VID_LUMAKEY,The register configures the LUMA KEY transparency min and max values. Shadow register" hexmask.long.byte 0x10 28.--31. 1. "RESERVED1,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 16.--27. 1. "LUMAKEYMAX,12b luma_key_max value" newline hexmask.long.byte 0x10 12.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 0.--11. 1. "LUMAKEYMIN,12b luma_key_min value" tree.end tree "DSS0_VIDL1" base ad:0x30202000 group.long 0x20++0x17 line.long 0x0 "VIDL1_ATTRIBUTES,The register configures the attributes of the video window. Shadow register" bitfld.long 0x0 31. "LUMAKEYENABLE,Enable Luma Key transparency matching" "0,1" bitfld.long 0x0 30. "GAMMAINVERSION,Inverse Gamma support [using the CLUT table]" "0,1" bitfld.long 0x0 28. "PREMULTIPLYALPHA,The field configures the DISPC VID to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data" "0,1" newline bitfld.long 0x0 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "0,1" bitfld.long 0x0 23. "ARBITRATION,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipelines. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there are only normal.." "0,1" rbitfld.long 0x0 21. "RESERVED3,Write 0's for future compatibility. Reads return 0" "0,1" newline bitfld.long 0x0 19. "BUFPRELOAD,Video Preload Value" "0,1" rbitfld.long 0x0 18. "RESERVED7,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 17. "SELFREFRESHAUTO,Automatic self refresh mode" "0,1" newline bitfld.long 0x0 12. "FLIP,Describes the frame buffer flip operation" "0,1" bitfld.long 0x0 11. "FULLRANGE,Color Space Conversion full range setting" "0,1" bitfld.long 0x0 10. "NIBBLEMODE,Video Nibble mode [only for 1- 2- and 4-bpp]" "0,1" newline bitfld.long 0x0 9. "COLORCONVENABLE,Enable the color space conversion. The HW does not enable/disable the conversion based on the pixel format" "0,1" rbitfld.long 0x0 7.--8. "RESERVED8,Write 0's for future compatibility. Reads return 0" "0,1,2,3" hexmask.long.byte 0x0 1.--6. 1. "FORMAT,Video Format. It defines the pixel format when fetching the video frame buffer" newline bitfld.long 0x0 0. "ENABLE,Video pipeline Enable" "0,1" line.long 0x4 "VIDL1_ATTRIBUTES2,The register configures the attributes of the video window. Shadow register" hexmask.long.byte 0x4 26.--30. 1. "TAGS,Number of OCP TAGS to be used for the pipeline [from 0x0 to 0xF]. A value of 0x0 means only a single tag will be used. A value of 0xF means all 16 tags can be used" bitfld.long 0x4 10. "YUV_ALIGN,Alignment [MSB or LSB align] for unpacked 10b/12b YUV data" "0,1" bitfld.long 0x4 9. "YUV_MODE,Mode of packing for YUV data [only for 10b/12b formats]" "0,1" newline bitfld.long 0x4 7.--8. "YUV_SIZE,Size of YUV data 8b/10b/12b" "0,1,2,3" bitfld.long 0x4 4.--6. "VC1_RANGE_CBCR,Defines the VC1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7" bitfld.long 0x4 1.--3. "VC1_RANGE_Y,Defines the VC1 range value for the Y component from 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "VC1ENABLE,Enable/disable the VC1 range mapping processing. The bit-field is ignored if the format is not one of the supported YUV formats" "0,1" line.long 0x8 "VIDL1_BA_0,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV. this is the BA. In case of two plane YUV. this is the BA_Y. In case of two plane RGB565-A8. this is the BA_Alpha. BA__0 & BA__1 for.." hexmask.long 0x8 0.--31. 1. "BA,Video base address. Base address of the video buffer [Aligned on pixel size boundary except for the following. In case of RGB24 packed format 4-pixel alignment is required. In case of YUV422 2-pixel alignment is required. In case of YUV420 byte.." line.long 0xC "VIDL1_BA_1,The register configures the base address of the single video buffer. In case of single plane ARGB or YUV. this is the BA. In case of two plane YUV. this is the BA_Y. In case of two plane RGB565-A8. this is the BA_Alpha. BA__0 & BA__1 for.." hexmask.long 0xC 0.--31. 1. "BA,Video base address. Base address of the video buffer [Aligned on pixel size boundary except for the following. In case of RGB24 packed format 4-pixel alignment is required. In case of YUV422 2-pixel alignment is required. In case of YUV420 byte.." line.long 0x10 "VIDL1_BA_UV_0,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger. based on the field polarity.." hexmask.long 0x10 0.--31. 1. "BA,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV420-NV12" line.long 0x14 "VIDL1_BA_UV_1,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window. BA_UV__0 & BA_UV__1 for ping-pong mechanism with external trigger. based on the field polarity.." hexmask.long 0x14 0.--31. 1. "BA,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV420-NV12" rgroup.long 0x38++0x3 line.long 0x0 "VIDL1_BUF_SIZE_STATUS,The register returns the Video buffer size for the video pipeline" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x0 0.--15. 1. "BUFSIZE,Video DMA buffer Size in number of 128-bits" group.long 0x3C++0x1F line.long 0x0 "VIDL1_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline. Shadow register" hexmask.long.word 0x0 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold. Number of 128-bits defining the threshold value" hexmask.long.word 0x0 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer Low Threshold. Number of 128-bits defining the threshold value" line.long 0x4 "VIDL1_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x4 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x4 16.--26. 1. "C01,C01 Coefficient. Encoded signed value [from -1024 to 1023]" hexmask.long.byte 0x4 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x4 0.--10. 1. "C00,C00 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x8 "VIDL1_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x8 16.--26. 1. "C10,C10 Coefficient. Encoded signed value [from -1024 to 1023]" hexmask.long.byte 0x8 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x8 0.--10. 1. "C02,C02 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0xC "VIDL1_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0xC 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0xC 16.--26. 1. "C12,C12 Coefficient. Encoded signed value [from -1024 to 1023]" hexmask.long.byte 0xC 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0xC 0.--10. 1. "C11,C11 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x10 "VIDL1_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient. Encoded signed value [from -1024 to 1023]" hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "VIDL1_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.tbyte 0x14 11.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x18 "VIDL1_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset. Encoded signed value [from -4096 to 4095]" line.long 0x1C "VIDL1_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]" group.long 0x1FC++0x3 line.long 0x0 "VIDL1_GLOBAL_ALPHA,The register defines the global alpha value for the video pipeline. Shadow register" hexmask.long.byte 0x0 0.--7. 1. "GLOBALALPHA,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 corresponds to fully opaque" group.long 0x208++0xB line.long 0x0 "VIDL1_MFLAG_THRESHOLD,MFLAG_THRESHOLD Register" hexmask.long.word 0x0 16.--31. 1. "HT_MFLAG,MFLAG High Threshold" hexmask.long.word 0x0 0.--15. 1. "LT_MFLAG,MFLAG Low Threshold" line.long 0x4 "VIDL1_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer before up/down-scaling. Shadow register" hexmask.long.word 0x4 16.--27. 1. "MEMSIZEY,Number of lines of the video picture Encoded value [from 1 to 4096] to specify the number of lines of the video picture in memory [program to value minus one]. When predecimation is set the value represents the size of the image after.." hexmask.long.word 0x4 0.--11. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value [from 1 to 4096] to specify the number of pixels of the video picture in memory [program to value minus one]. The size is limited to the size of the line buffer of the vertical sampling block.." line.long 0x8 "VIDL1_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window. Shadow register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.byte 0x8 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels Encoded unsigned value [from 1 to 255] to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid The value 1 means next pixel The value 1+n*bpp means increment.." group.long 0x218++0x7 line.long 0x0 "VIDL1_PRELOAD,The register configures the DMA buffer of the video pipeline. Shadow register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x0 0.--11. 1. "PRELOAD,DMA buffer preload value. Number of 128-bit words defining the preload value" line.long 0x4 "VIDL1_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window. For YUV420 formats this corresponds to the Y Buffer. Shadow register" hexmask.long 0x4 0.--31. 1. "ROWINC,Number of bytes to increment at the end of the row Encoded signed value [from -2^31-1 to 2^31] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value.." group.long 0x22C++0x13 line.long 0x0 "VIDL1_BA_EXT_0,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 : For.." hexmask.long.word 0x0 0.--15. 1. "BA_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x4 "VIDL1_BA_EXT_1,The register configures the 16-bit base address extension. It is the base-address of the single video buffer for single plane ARGB or YUV. For the Y buffer for two plane YUV. For the Alpha buffer for two plane RGB565-A8. 0 & 1 : For.." hexmask.long.word 0x4 0.--15. 1. "BA_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x8 "VIDL1_BA_UV_EXT_0,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger. based on the field polarity. Shadow register" hexmask.long.word 0x8 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0xC "VIDL1_BA_UV_EXT_1,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8. 0 & 1 : For ping-pong mechanism with external trigger. based on the field polarity. Shadow register" hexmask.long.word 0xC 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]. Addr extension to make the address space 48b wide" line.long 0x10 "VIDL1_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x10 19.--31. 1. "POSTOFFSET3,Row-3 post-offset. Encoded signed value [from -4096 to 4095]" hexmask.long.word 0x10 3.--15. 1. "POSTOFFSET2,Row-2 post-offset. Encoded signed value [from -4096 to 4095]" group.long 0x248++0x3 line.long 0x0 "VIDL1_ROW_INC_UV,The register configures the number of bytes to increment at the end of the row for the UV buffer associated with the video window for YUV420 formats. For non-YUV420 formats this register is unused. Shadow register" hexmask.long 0x0 0.--31. 1. "ROWINC,Number of bytes to increment at the end of the row Encoded signed value [from -2^31-1 to 2^31] to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid The value 1 means next pixel. The value.." wgroup.long 0x260++0x3F line.long 0x0 "VIDL1_CLUT_0,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x0 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x0 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x0 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x0 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x4 "VIDL1_CLUT_1,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x4 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x4 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x4 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x4 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x8 "VIDL1_CLUT_2,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x8 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x8 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x8 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x8 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0xC "VIDL1_CLUT_3,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0xC 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0xC 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0xC 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0xC 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x10 "VIDL1_CLUT_4,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x10 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x10 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x10 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x10 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x14 "VIDL1_CLUT_5,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x14 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x14 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x14 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x14 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x18 "VIDL1_CLUT_6,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x18 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x18 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x18 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x18 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x1C "VIDL1_CLUT_7,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x1C 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x1C 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x1C 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x1C 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x20 "VIDL1_CLUT_8,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x20 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x20 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x20 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x20 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x24 "VIDL1_CLUT_9,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x24 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x24 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x24 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x24 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x28 "VIDL1_CLUT_10,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x28 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x28 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x28 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x28 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x2C "VIDL1_CLUT_11,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x2C 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x2C 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x2C 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x2C 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x30 "VIDL1_CLUT_12,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x30 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x30 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x30 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x30 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x34 "VIDL1_CLUT_13,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x34 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x34 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x34 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x34 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x38 "VIDL1_CLUT_14,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x38 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x38 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x38 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x38 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" line.long 0x3C "VIDL1_CLUT_15,The register configures the Color Look Up Table CLUT for VID pipeline. CLUT is used in conjunction with bitmap formats" hexmask.long.byte 0x3C 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" hexmask.long.byte 0x3C 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX" hexmask.long.byte 0x3C 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX" newline hexmask.long.byte 0x3C 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX" group.long 0x2A0++0x3 line.long 0x0 "VIDL1_SAFETY_ATTRIBUTES,The register configures the safety sub-region. Shadow register" bitfld.long 0x0 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" hexmask.long.byte 0x0 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur. Note: The freeze frame counter is cleared on reset -OR- MISR.." bitfld.long 0x0 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x0 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" bitfld.long 0x0 0. "ENABLE,Safety check Enable for the region. Note: Transition from 0 to 1 clears the signature register" "0,1" rgroup.long 0x2A4++0x3 line.long 0x0 "VIDL1_SAFETY_CAPT_SIGNATURE,The register captures the signature from the MISR of the safety sub-region. Shadow register" hexmask.long 0x0 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" group.long 0x2A8++0x13 line.long 0x0 "VIDL1_SAFETY_POSITION,The register configures the position of the safety sub-region. Shadow register" hexmask.long.word 0x0 16.--27. 1. "POSY,Y position of the safety sub-region. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen. The first line on the top of the screen has the Y-position 0" hexmask.long.word 0x0 0.--11. 1. "POSX,X position of the safety sub-region. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen. The first pixel on the left of the screen has the X-position 0" line.long 0x4 "VIDL1_SAFETY_REF_SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" hexmask.long 0x4 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region. Shadow register" line.long 0x8 "VIDL1_SAFETY_SIZE,The register configures the size of the safety sub-region. Shadow register" hexmask.long.word 0x8 16.--27. 1. "SIZEY,Height of the safety sub-region. Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen. One line height region has value of 0" hexmask.long.word 0x8 0.--11. 1. "SIZEX,Width of the safety sub-region. Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen. One pixel wide region has value of 0" line.long 0xC "VIDL1_SAFETY_LFSR_SEED,The register configures the seed [initial value] of the MISR. Otherwise. the MISR is initialized with 0xFFFF_FFFF. Shadow register" hexmask.long 0xC 0.--31. 1. "SEED,The register configures the seed [initial value] of the MISR. Otherwise the MISR is initialized with 0xFFFF_FFFF. Shadow register" line.long 0x10 "VIDL1_LUMAKEY,The register configures the LUMA KEY transparency min and max values. Shadow register" hexmask.long.byte 0x10 28.--31. 1. "RESERVED1,Write 0's for future compatibility Reads return 0" hexmask.long.word 0x10 16.--27. 1. "LUMAKEYMAX,12b luma_key_max value" hexmask.long.byte 0x10 12.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x10 0.--11. 1. "LUMAKEYMIN,12b luma_key_min value" tree.end tree "DSS0_VP1" base ad:0x3020A000 group.long 0x0++0x1F line.long 0x0 "VP1_CONFIG,The control register configures the Display Controller module for the VP output. Shadow register." hexmask.long.byte 0x0 27.--31. 1. "RESERVED3" newline bitfld.long 0x0 26. "COLORCONVPOS,Determines the position of the COLORCONV module" "0,1" newline bitfld.long 0x0 25. "FULLRANGE,Color Space Conversion full range setting" "0,1" newline bitfld.long 0x0 24. "COLORCONVENABLE,Enable the color space conversion. The coefficients and offsets used are all programmable and controlled by CPR_COEFF_* and CPR_OFFSET_* registers" "0,1" newline bitfld.long 0x0 23. "FIDFIRST,Selects the first field to output in case of interlace mode. In case of progressive mode the value is not used" "0,1" newline bitfld.long 0x0 22. "OUTPUTMODEENABLE,Selects between progressive and interlace mode for the VP output" "0,1" newline bitfld.long 0x0 21. "BT1120ENABLE,Selects BT-1120 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output" "0,1" newline bitfld.long 0x0 20. "BT656ENABLE,Selects BT-656 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output" "0,1" newline rbitfld.long 0x0 17.--19. "RESERVED2,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "BUFFERHANDSHAKE,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 15. "CPR,Deprecated. Always write 0" "0,1" newline hexmask.long.byte 0x0 9.--14. 1. "RESERVED1,Write 0's for future compatibility Reads return 0" newline bitfld.long 0x0 8. "EXTERNALSYNCEN,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 7. "VSYNCGATED,VSYNC Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 6. "HSYNCGATED,HSYNC Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 5. "PIXELCLOCKGATED,Pixel Clock Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 4. "PIXELDATAGATED,Pixel Data Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 3. "HDMIMODE,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 2. "GAMMAENABLE,Enable the gamma Shadow bit-field" "0,1" newline bitfld.long 0x0 1. "DATAENABLEGATED,DE Gated Enable Shadow bit-field" "0,1" newline bitfld.long 0x0 0. "PIXELGATED,Pixel Gated Enable. Shadow bit-field" "0,1" line.long 0x4 "VP1_CONTROL,The control register configures the Display Controller module for the VP output" bitfld.long 0x4 30.--31. "SPATIALTEMPORALDITHERINGFRAMES,Spatial/Temporal dithering number of frames for the VP output Shadow bit-field" "0,1,2,3" newline rbitfld.long 0x4 27.--29. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 25.--26. "TDMUNUSEDBITS,State of unused bits [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 23.--24. "TDMCYCLEFORMAT,Cycle format [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 21.--22. "TDMPARALLELMODE,Output Interface width [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 20. "TDMENABLE,Enable the multiple cycle format for the VP output Shadow bit-field" "0,1" newline rbitfld.long 0x4 17.--19. "RESERVED1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 14.--16. "HT,Hold Time for output. Shadow bit-field. Encoded value [from 1 to 8] to specify the number of external digital clock periods to hold the data [programmed value = value minus one]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 13. "RESERVED3" "0,1" newline rbitfld.long 0x4 12. "RESERVED6" "0,1" newline bitfld.long 0x4 11. "STALLMODE,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 8.--10. "DATALINES,Width of the data bus on VP output Shadow bit-field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "STDITHERENABLE,Spatial Temporal dithering enable for the VP output Shadow bit-field" "0,1" newline bitfld.long 0x4 6. "DPIENABLE,Enable the DPI output. wr:immediate" "0,1" newline bitfld.long 0x4 5. "GOBIT,GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output wr:immediate" "0,1" newline bitfld.long 0x4 4. "M8B,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 3. "STN,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 2. "MONOCOLOR,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 1. "VPPROGLINENUMBERMODULO,Enable the modulo of the line number interrupt generation" "0,1" newline bitfld.long 0x4 0. "ENABLE,Enable the video port output. wr:immediate" "0,1" line.long 0x8 "VP1_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x8 16.--26. 1. "C01,C01 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x8 0.--10. 1. "C00,C00 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0xC "VP1_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0xC 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0xC 16.--26. 1. "C10,C10 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0xC 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0xC 0.--10. 1. "C02,C02 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x10 "VP1_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x10 16.--26. 1. "C12,C12 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x10 0.--10. 1. "C11,C11 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "VP1_DATA_CYCLE_0,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x14 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x14 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x14 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x14 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" line.long 0x18 "VP1_DATA_CYCLE_1,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x18 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x18 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x18 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x18 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x18 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" line.long 0x1C "VP1_DATA_CYCLE_2,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x1C 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x1C 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x1C 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x1C 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" group.long 0x44++0x3 line.long 0x0 "VP1_LINE_NUMBER,The control register indicates the panel display line number for the interrupt and the DMA request. Shadow register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--11. 1. "LINENUMBER,LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs" group.long 0x4C++0x33 line.long 0x0 "VP1_POL_FREQ,The register configures the signal configuration. Shadow register" hexmask.long.word 0x0 19.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline bitfld.long 0x0 18. "ALIGN,Defines the alignment between HSYNC and VSYNC assertion" "0,1" newline bitfld.long 0x0 17. "ONOFF,HSYNC/VSYNC Pixel clock Control On/Off" "0,1" newline bitfld.long 0x0 16. "RF,Program HSYNC/VSYNC Rise or Fall" "0,1" newline bitfld.long 0x0 15. "IEO,Invert output enable" "0,1" newline bitfld.long 0x0 14. "IPC,Invert pixel clock" "0,1" newline bitfld.long 0x0 13. "IHS,Invert HSYNC" "0,1" newline bitfld.long 0x0 12. "IVS,Invert VSYNC" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "ACBI,AC Bias Pin transitions per interrupt Value [from 0 to 15] used to specify the number of AC Bias pin transitions" newline hexmask.long.byte 0x0 0.--7. 1. "ACB,AC Bias Pin Frequency Value [from 0 to 255] used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the.." line.long 0x4 "VP1_SIZE_SCREEN,The register configures the panel size horizontal and vertical. Shadow register. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." hexmask.long.byte 0x4 28.--31. 1. "RESERVED1" newline hexmask.long.word 0x4 16.--27. 1. "LPP,Lines per panel Encoded value [from 1 to 4096] to specify the number of lines per panel [program to value minus one]" newline bitfld.long 0x4 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field" "0,1,2,3" newline rbitfld.long 0x4 12.--13. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "PPL,Pixels per line Encoded value [from 1 to 4096] to specify the number of pixels contains within each line on the display [program to value minus one]. In STALL mode any value is valid In non-STALL mode only values multiple of 8 pixels are valid" line.long 0x8 "VP1_TIMING_H,The register configures the timing logic for the HSYNC signal. Shadow register" hexmask.long.word 0x8 20.--31. 1. "HBP,Horizontal Back Porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display [program to value minus one] When in BT mode and.." newline hexmask.long.word 0x8 8.--19. 1. "HFP,Horizontal front porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted display [program to value minus one] When in BT mode and interlaced this field.." newline hexmask.long.byte 0x8 0.--7. 1. "HSW,Horizontal synchronization pulse width Encoded value [from 1 to 256] to specify the number of pixel clock periods to pulse the line clock at the end of each line display [program to value minus one] When in BT mode this field corresponds to the LSB.." line.long 0xC "VP1_TIMING_V,The register configures the timing logic for the VSYNC signal. Shadow register" hexmask.long.word 0xC 20.--31. 1. "VBP,Vertical back porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the beginning of a frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 2 for Odd Field When in BT and.." newline hexmask.long.word 0xC 8.--19. 1. "VFP,Vertical front porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the end of each frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 1 for Odd Field When in BT and in.." newline hexmask.long.byte 0xC 0.--7. 1. "VSW,Vertical synchronization pulse width Encoded value [from 1 to 256] to specify the number of line clock periods to pulse the frame clock [VSYNC] pin at the end of each frame after the end of frame wait [VFP] period elapses Frame clock uses as VSYNC.." line.long 0x10 "VP1_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "VP1_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.tbyte 0x14 11.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x18 "VP1_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x18 16.--18. "RESERVED1" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x18 0.--2. "RESERVED" "0,1,2,3,4,5,6,7" line.long 0x1C "VP1_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x1C 16.--18. "RESERVED1" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x1C 0.--2. "RESERVED" "0,1,2,3,4,5,6,7" line.long 0x20 "VP1_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x20 19.--31. 1. "POSTOFFSET3,Row-3 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x20 16.--18. "RESERVED1" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 3.--15. 1. "POSTOFFSET2,Row-2 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x20 0.--2. "RESERVED" "0,1,2,3,4,5,6,7" line.long 0x24 "VP1_SAFETY_ATTRIBUTES_0,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x24 13.--31. 1. "RESERVED" newline bitfld.long 0x24 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x24 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x24 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x24 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x24 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x28 "VP1_SAFETY_ATTRIBUTES_1,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x28 13.--31. 1. "RESERVED" newline bitfld.long 0x28 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x28 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x28 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x28 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x28 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x2C "VP1_SAFETY_ATTRIBUTES_2,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x2C 13.--31. 1. "RESERVED" newline bitfld.long 0x2C 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x2C 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x2C 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x2C 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x2C 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x30 "VP1_SAFETY_ATTRIBUTES_3,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x30 13.--31. 1. "RESERVED" newline bitfld.long 0x30 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x30 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x30 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x30 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x30 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" rgroup.long 0x90++0xF line.long 0x0 "VP1_SAFETY_CAPT_SIGNATURE_0,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x0 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x4 "VP1_SAFETY_CAPT_SIGNATURE_1,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x4 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x8 "VP1_SAFETY_CAPT_SIGNATURE_2,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x8 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0xC "VP1_SAFETY_CAPT_SIGNATURE_3,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0xC 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" group.long 0xB0++0xF line.long 0x0 "VP1_SAFETY_POSITION_0,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" newline hexmask.long.word 0x0 16.--27. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED1" newline hexmask.long.word 0x0 0.--11. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x4 "VP1_SAFETY_POSITION_1,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.byte 0x4 28.--31. 1. "RESERVED" newline hexmask.long.word 0x4 16.--27. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED1" newline hexmask.long.word 0x4 0.--11. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x8 "VP1_SAFETY_POSITION_2,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.byte 0x8 28.--31. 1. "RESERVED" newline hexmask.long.word 0x8 16.--27. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.byte 0x8 12.--15. 1. "RESERVED1" newline hexmask.long.word 0x8 0.--11. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0xC "VP1_SAFETY_POSITION_3,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.byte 0xC 28.--31. 1. "RESERVED" newline hexmask.long.word 0xC 16.--27. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.byte 0xC 12.--15. 1. "RESERVED1" newline hexmask.long.word 0xC 0.--11. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" group.long 0xD0++0xF line.long 0x0 "VP1_SAFETY_REF_SIGNATURE_0,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x0 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x4 "VP1_SAFETY_REF_SIGNATURE_1,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x4 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x8 "VP1_SAFETY_REF_SIGNATURE_2,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x8 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0xC "VP1_SAFETY_REF_SIGNATURE_3,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0xC 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" group.long 0xF0++0xF line.long 0x0 "VP1_SAFETY_SIZE_0,The register configures the size of the safety sub-region n Shadow register." hexmask.long.byte 0x0 28.--31. 1. "RESERVED" newline hexmask.long.word 0x0 16.--27. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED1" newline hexmask.long.word 0x0 0.--11. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x4 "VP1_SAFETY_SIZE_1,The register configures the size of the safety sub-region n Shadow register." hexmask.long.byte 0x4 28.--31. 1. "RESERVED" newline hexmask.long.word 0x4 16.--27. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED1" newline hexmask.long.word 0x4 0.--11. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x8 "VP1_SAFETY_SIZE_2,The register configures the size of the safety sub-region n Shadow register." hexmask.long.byte 0x8 28.--31. 1. "RESERVED" newline hexmask.long.word 0x8 16.--27. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.byte 0x8 12.--15. 1. "RESERVED1" newline hexmask.long.word 0x8 0.--11. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0xC "VP1_SAFETY_SIZE_3,The register configures the size of the safety sub-region n Shadow register." hexmask.long.byte 0xC 28.--31. 1. "RESERVED" newline hexmask.long.word 0xC 16.--27. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.byte 0xC 12.--15. 1. "RESERVED1" newline hexmask.long.word 0xC 0.--11. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen One pixel wide region has value of 0" group.long 0x110++0x3 line.long 0x0 "VP1_SAFETY_LFSR_SEED,The register configures the seed initial signature value of MISRs that are to be initialized with a user programmed initial value. Otherwise. the MISR is initialized with 0xFFFF_FFFF. Shadow register." hexmask.long 0x0 0.--31. 1. "SEED,The register configures the seed [initial signature value] of MISRs that are to be initialized with a user programmed initial value Otherwise the MISR is initialized with 0xFFFF_FFFF Shadow register" wgroup.long 0x120++0x3F line.long 0x0 "VP1_GAMMA_TABLE_0,The register configures the gamma table on VP output." hexmask.long.byte 0x0 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x0 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x0 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x0 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x4 "VP1_GAMMA_TABLE_1,The register configures the gamma table on VP output." hexmask.long.byte 0x4 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x4 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x4 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x4 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x8 "VP1_GAMMA_TABLE_2,The register configures the gamma table on VP output." hexmask.long.byte 0x8 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x8 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x8 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x8 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0xC "VP1_GAMMA_TABLE_3,The register configures the gamma table on VP output." hexmask.long.byte 0xC 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0xC 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0xC 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0xC 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x10 "VP1_GAMMA_TABLE_4,The register configures the gamma table on VP output." hexmask.long.byte 0x10 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x10 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x10 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x10 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x14 "VP1_GAMMA_TABLE_5,The register configures the gamma table on VP output." hexmask.long.byte 0x14 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x14 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x14 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x14 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x18 "VP1_GAMMA_TABLE_6,The register configures the gamma table on VP output." hexmask.long.byte 0x18 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x18 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x18 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x18 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x1C "VP1_GAMMA_TABLE_7,The register configures the gamma table on VP output." hexmask.long.byte 0x1C 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x1C 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x1C 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x1C 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x20 "VP1_GAMMA_TABLE_8,The register configures the gamma table on VP output." hexmask.long.byte 0x20 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x20 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x20 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x20 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x24 "VP1_GAMMA_TABLE_9,The register configures the gamma table on VP output." hexmask.long.byte 0x24 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x24 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x24 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x24 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x28 "VP1_GAMMA_TABLE_10,The register configures the gamma table on VP output." hexmask.long.byte 0x28 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x28 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x28 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x28 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x2C "VP1_GAMMA_TABLE_11,The register configures the gamma table on VP output." hexmask.long.byte 0x2C 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x2C 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x2C 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x2C 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x30 "VP1_GAMMA_TABLE_12,The register configures the gamma table on VP output." hexmask.long.byte 0x30 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x30 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x30 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x30 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x34 "VP1_GAMMA_TABLE_13,The register configures the gamma table on VP output." hexmask.long.byte 0x34 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x34 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x34 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x34 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x38 "VP1_GAMMA_TABLE_14,The register configures the gamma table on VP output." hexmask.long.byte 0x38 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x38 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x38 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x38 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x3C "VP1_GAMMA_TABLE_15,The register configures the gamma table on VP output." hexmask.long.byte 0x3C 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x3C 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x3C 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x3C 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" group.long 0x160++0x3 line.long 0x0 "VP1_DSS_OLDI_CFG,This register configures the OLDI[N:0] modules connected to the DSS" bitfld.long 0x0 13. "TPATCFG,Test pattern Config" "0,1" newline bitfld.long 0x0 12. "SOFTRST,SoftWare Reset. By default OLDI is kept under reset" "0,1" newline bitfld.long 0x0 11. "DUALMODESYNC,DualMode Sync" "0,1" newline bitfld.long 0x0 10. "LBDATA,LoopBack Data" "0,1" newline bitfld.long 0x0 9. "LBEN,LoopBack Enable" "0,1" newline bitfld.long 0x0 8. "MSB,DSS bit-depth [for 18b LVDS only]" "0,1" newline bitfld.long 0x0 7. "DEPOL,Polarity of the DE signal" "0,1" newline bitfld.long 0x0 6. "MASTERSLAVE,Master selection in Dual mode only [typically tied off in the SoC]" "0,1" newline bitfld.long 0x0 5. "MODE,Single mode or duplicate mode" "0,1" newline bitfld.long 0x0 4. "SRC,Source Channel" "0,1" newline bitfld.long 0x0 1.--3. "MAP,Configuration of OLDI mapping Also indicates dual mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ENABLE,OLDI Enable" "0,1" rgroup.long 0x164++0x7 line.long 0x0 "VP1_DSS_OLDI_STATUS,This register captures the PID from the OLDI[N:0] modules connected to the DSS. Reads 0x0 if no OLDI is connected" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID Field" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Revision" newline bitfld.long 0x0 8.--10. "REVMAJOR,Major Revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Revision" line.long 0x4 "VP1_DSS_OLDI_LB,This register captures the Loopback data from OLDI" hexmask.long.word 0x4 0.--9. 1. "LBRDATA,Returned Data from Loopback" tree.end tree "DSS0_VP2" base ad:0x3020B000 group.long 0x0++0x1F line.long 0x0 "VP2_CONFIG,The control register configures the Display Controller module for the VP output. Shadow register." hexmask.long.byte 0x0 27.--31. 1. "RESERVED3" newline bitfld.long 0x0 26. "COLORCONVPOS,Determines the position of the COLORCONV module" "0,1" newline bitfld.long 0x0 25. "FULLRANGE,Color Space Conversion full range setting" "0,1" newline bitfld.long 0x0 24. "COLORCONVENABLE,Enable the color space conversion. The coefficients and offsets used are all programmable and controlled by CPR_COEFF_* and CPR_OFFSET_* registers" "0,1" newline bitfld.long 0x0 23. "FIDFIRST,Selects the first field to output in case of interlace mode. In case of progressive mode the value is not used" "0,1" newline bitfld.long 0x0 22. "OUTPUTMODEENABLE,Selects between progressive and interlace mode for the VP output" "0,1" newline bitfld.long 0x0 21. "BT1120ENABLE,Selects BT-1120 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output" "0,1" newline bitfld.long 0x0 20. "BT656ENABLE,Selects BT-656 format on the VP output. It is not possible to enable BT656 and BT1120 at the same time one the same LCD output" "0,1" newline rbitfld.long 0x0 17.--19. "RESERVED2,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "BUFFERHANDSHAKE,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 15. "CPR,Deprecated. Always write 0" "0,1" newline hexmask.long.byte 0x0 9.--14. 1. "RESERVED1,Write 0's for future compatibility Reads return 0" newline bitfld.long 0x0 8. "EXTERNALSYNCEN,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 7. "VSYNCGATED,VSYNC Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 6. "HSYNCGATED,HSYNC Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 5. "PIXELCLOCKGATED,Pixel Clock Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 4. "PIXELDATAGATED,Pixel Data Gated Enabled [VP output]. Shadow bit-field" "0,1" newline bitfld.long 0x0 3. "HDMIMODE,Deprecated. Always write 0" "0,1" newline bitfld.long 0x0 2. "GAMMAENABLE,Enable the gamma Shadow bit-field" "0,1" newline bitfld.long 0x0 1. "DATAENABLEGATED,DE Gated Enable Shadow bit-field" "0,1" newline bitfld.long 0x0 0. "PIXELGATED,Pixel Gated Enable. Shadow bit-field" "0,1" line.long 0x4 "VP2_CONTROL,The control register configures the Display Controller module for the VP output" bitfld.long 0x4 30.--31. "SPATIALTEMPORALDITHERINGFRAMES,Spatial/Temporal dithering number of frames for the VP output Shadow bit-field" "0,1,2,3" newline rbitfld.long 0x4 27.--29. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 25.--26. "TDMUNUSEDBITS,State of unused bits [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 23.--24. "TDMCYCLEFORMAT,Cycle format [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 21.--22. "TDMPARALLELMODE,Output Interface width [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3" newline bitfld.long 0x4 20. "TDMENABLE,Enable the multiple cycle format for the VP output Shadow bit-field" "0,1" newline rbitfld.long 0x4 17.--19. "RESERVED1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 14.--16. "HT,Hold Time for output. Shadow bit-field. Encoded value [from 1 to 8] to specify the number of external digital clock periods to hold the data [programmed value = value minus one]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 13. "RESERVED3" "0,1" newline rbitfld.long 0x4 12. "RESERVED6" "0,1" newline bitfld.long 0x4 11. "STALLMODE,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 8.--10. "DATALINES,Width of the data bus on VP output Shadow bit-field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "STDITHERENABLE,Spatial Temporal dithering enable for the VP output Shadow bit-field" "0,1" newline bitfld.long 0x4 6. "DPIENABLE,Enable the DPI output. wr:immediate" "0,1" newline bitfld.long 0x4 5. "GOBIT,GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output wr:immediate" "0,1" newline bitfld.long 0x4 4. "M8B,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 3. "STN,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 2. "MONOCOLOR,Deprecated. Always write 0" "0,1" newline bitfld.long 0x4 1. "VPPROGLINENUMBERMODULO,Enable the modulo of the line number interrupt generation" "0,1" newline bitfld.long 0x4 0. "ENABLE,Enable the video port output. wr:immediate" "0,1" line.long 0x8 "VP2_CSC_COEF0,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x8 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x8 16.--26. 1. "C01,C01 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x8 0.--10. 1. "C00,C00 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0xC "VP2_CSC_COEF1,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0xC 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0xC 16.--26. 1. "C10,C10 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0xC 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0xC 0.--10. 1. "C02,C02 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x10 "VP2_CSC_COEF2,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x10 16.--26. 1. "C12,C12 Coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.word 0x10 0.--10. 1. "C11,C11 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "VP2_DATA_CYCLE_0,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x14 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x14 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x14 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x14 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" line.long 0x18 "VP2_DATA_CYCLE_1,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x18 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x18 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x18 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x18 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x18 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" line.long 0x1C "VP2_DATA_CYCLE_2,The control register configures the output data format over up to 3 cycles. Shadow register" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline hexmask.long.byte 0x1C 24.--27. 1. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" newline rbitfld.long 0x1C 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 16.--20. 1. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.byte 0x1C 8.--11. 1. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" newline rbitfld.long 0x1C 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 0.--4. 1. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]. The values from 17 to 31 are invalid" group.long 0x44++0x3 line.long 0x0 "VP2_LINE_NUMBER,The control register indicates the panel display line number for the interrupt and the DMA request. Shadow register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--11. 1. "LINENUMBER,LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs" group.long 0x4C++0x33 line.long 0x0 "VP2_POL_FREQ,The register configures the signal configuration. Shadow register" hexmask.long.word 0x0 19.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" newline bitfld.long 0x0 18. "ALIGN,Defines the alignment between HSYNC and VSYNC assertion" "0,1" newline bitfld.long 0x0 17. "ONOFF,HSYNC/VSYNC Pixel clock Control On/Off" "0,1" newline bitfld.long 0x0 16. "RF,Program HSYNC/VSYNC Rise or Fall" "0,1" newline bitfld.long 0x0 15. "IEO,Invert output enable" "0,1" newline bitfld.long 0x0 14. "IPC,Invert pixel clock" "0,1" newline bitfld.long 0x0 13. "IHS,Invert HSYNC" "0,1" newline bitfld.long 0x0 12. "IVS,Invert VSYNC" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "ACBI,AC Bias Pin transitions per interrupt Value [from 0 to 15] used to specify the number of AC Bias pin transitions" newline hexmask.long.byte 0x0 0.--7. 1. "ACB,AC Bias Pin Frequency Value [from 0 to 255] used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the.." line.long 0x4 "VP2_SIZE_SCREEN,The register configures the panel size horizontal and vertical. Shadow register. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." hexmask.long.byte 0x4 28.--31. 1. "RESERVED1" newline hexmask.long.word 0x4 16.--27. 1. "LPP,Lines per panel Encoded value [from 1 to 4096] to specify the number of lines per panel [program to value minus one]" newline bitfld.long 0x4 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field" "0,1,2,3" newline rbitfld.long 0x4 12.--13. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "PPL,Pixels per line Encoded value [from 1 to 4096] to specify the number of pixels contains within each line on the display [program to value minus one]. In STALL mode any value is valid In non-STALL mode only values multiple of 8 pixels are valid" line.long 0x8 "VP2_TIMING_H,The register configures the timing logic for the HSYNC signal. Shadow register" hexmask.long.word 0x8 20.--31. 1. "HBP,Horizontal Back Porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display [program to value minus one] When in BT mode and.." newline hexmask.long.word 0x8 8.--19. 1. "HFP,Horizontal front porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted display [program to value minus one] When in BT mode and interlaced this field.." newline hexmask.long.byte 0x8 0.--7. 1. "HSW,Horizontal synchronization pulse width Encoded value [from 1 to 256] to specify the number of pixel clock periods to pulse the line clock at the end of each line display [program to value minus one] When in BT mode this field corresponds to the LSB.." line.long 0xC "VP2_TIMING_V,The register configures the timing logic for the VSYNC signal. Shadow register" hexmask.long.word 0xC 20.--31. 1. "VBP,Vertical back porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the beginning of a frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 2 for Odd Field When in BT and.." newline hexmask.long.word 0xC 8.--19. 1. "VFP,Vertical front porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the end of each frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 1 for Odd Field When in BT and in.." newline hexmask.long.byte 0xC 0.--7. 1. "VSW,Vertical synchronization pulse width Encoded value [from 1 to 256] to specify the number of line clock periods to pulse the frame clock [VSYNC] pin at the end of each frame after the end of frame wait [VFP] period elapses Frame clock uses as VSYNC.." line.long 0x10 "VP2_CSC_COEF3,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.byte 0x10 27.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient. Encoded signed value [from -1024 to 1023]" newline hexmask.long.byte 0x10 11.--15. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x14 "VP2_CSC_COEF4,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.tbyte 0x14 11.--31. 1. "RESERVED,Write 0's for future compatibility. Reads return 0" newline hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient. Encoded signed value [from -1024 to 1023]" line.long 0x18 "VP2_CSC_COEF5,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x18 16.--18. "RESERVED1" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x18 0.--2. "RESERVED" "0,1,2,3,4,5,6,7" line.long 0x1C "VP2_CSC_COEF6,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x1C 16.--18. "RESERVED1" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x1C 0.--2. "RESERVED" "0,1,2,3,4,5,6,7" line.long 0x20 "VP2_CSC_COEF7,The register configures the color space conversion matrix coefficients. Shadow register" hexmask.long.word 0x20 19.--31. 1. "POSTOFFSET3,Row-3 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x20 16.--18. "RESERVED1" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 3.--15. 1. "POSTOFFSET2,Row-2 post-offset. Encoded signed value [from -4096 to 4095]" newline rbitfld.long 0x20 0.--2. "RESERVED" "0,1,2,3,4,5,6,7" line.long 0x24 "VP2_SAFETY_ATTRIBUTES_0,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x24 13.--31. 1. "RESERVED" newline bitfld.long 0x24 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x24 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x24 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x24 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x24 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x28 "VP2_SAFETY_ATTRIBUTES_1,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x28 13.--31. 1. "RESERVED" newline bitfld.long 0x28 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x28 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x28 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x28 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x28 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x2C "VP2_SAFETY_ATTRIBUTES_2,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x2C 13.--31. 1. "RESERVED" newline bitfld.long 0x2C 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x2C 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x2C 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x2C 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x2C 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" line.long 0x30 "VP2_SAFETY_ATTRIBUTES_3,The register configures the safety sub-region n. Shadow register" hexmask.long.tbyte 0x30 13.--31. 1. "RESERVED" newline bitfld.long 0x30 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]. 0x0: No frames are skipped 0x1: Even Frames are skipped starting from second frame after ENABLE 0x2: Odd Frames are skipped starting.." "0: No frames are skipped,1: Even Frames are skipped starting from second..,2: Odd Frames are skipped starting from first frame..,3: Reserved" newline hexmask.long.byte 0x30 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.." newline bitfld.long 0x30 2. "SEEDSELECT,Initial seed selection control" "0,1" newline bitfld.long 0x30 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1" newline bitfld.long 0x30 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1" rgroup.long 0x90++0xF line.long 0x0 "VP2_SAFETY_CAPT_SIGNATURE_0,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x0 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x4 "VP2_SAFETY_CAPT_SIGNATURE_1,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x4 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0x8 "VP2_SAFETY_CAPT_SIGNATURE_2,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0x8 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" line.long 0xC "VP2_SAFETY_CAPT_SIGNATURE_3,The register captures the signature from the MISR of the safety sub-region n. Shadow register" hexmask.long 0xC 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n Shadow register" group.long 0xB0++0xF line.long 0x0 "VP2_SAFETY_POSITION_0,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.byte 0x0 28.--31. 1. "RESERVED" newline hexmask.long.word 0x0 16.--27. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED1" newline hexmask.long.word 0x0 0.--11. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x4 "VP2_SAFETY_POSITION_1,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.byte 0x4 28.--31. 1. "RESERVED" newline hexmask.long.word 0x4 16.--27. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED1" newline hexmask.long.word 0x4 0.--11. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0x8 "VP2_SAFETY_POSITION_2,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.byte 0x8 28.--31. 1. "RESERVED" newline hexmask.long.word 0x8 16.--27. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.byte 0x8 12.--15. 1. "RESERVED1" newline hexmask.long.word 0x8 0.--11. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" line.long 0xC "VP2_SAFETY_POSITION_3,The register configures the position of the safety sub-region n. Shadow register" hexmask.long.byte 0xC 28.--31. 1. "RESERVED" newline hexmask.long.word 0xC 16.--27. 1. "POSY,Y position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the Y position of the sub-region on the screen The first line on the top of the screen has the Y-position 0" newline hexmask.long.byte 0xC 12.--15. 1. "RESERVED1" newline hexmask.long.word 0xC 0.--11. 1. "POSX,X position of the safety sub-region n. Encoded value [from 0 to 4095] to specify the X position of the sub-region on the screen The first pixel on the left of the screen has the X-position 0" group.long 0xD0++0xF line.long 0x0 "VP2_SAFETY_REF_SIGNATURE_0,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x0 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x4 "VP2_SAFETY_REF_SIGNATURE_1,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x4 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0x8 "VP2_SAFETY_REF_SIGNATURE_2,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0x8 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" line.long 0xC "VP2_SAFETY_REF_SIGNATURE_3,The register configures the reference signature of the safety sub-region n. Shadow register" hexmask.long 0xC 0.--31. 1. "SIGNATURE,The register configures the reference signature of the safety sub-region n. Shadow register" group.long 0xF0++0xF line.long 0x0 "VP2_SAFETY_SIZE_0,The register configures the size of the safety sub-region n Shadow register." hexmask.long.byte 0x0 28.--31. 1. "RESERVED" newline hexmask.long.word 0x0 16.--27. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED1" newline hexmask.long.word 0x0 0.--11. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x4 "VP2_SAFETY_SIZE_1,The register configures the size of the safety sub-region n Shadow register." hexmask.long.byte 0x4 28.--31. 1. "RESERVED" newline hexmask.long.word 0x4 16.--27. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED1" newline hexmask.long.word 0x4 0.--11. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0x8 "VP2_SAFETY_SIZE_2,The register configures the size of the safety sub-region n Shadow register." hexmask.long.byte 0x8 28.--31. 1. "RESERVED" newline hexmask.long.word 0x8 16.--27. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.byte 0x8 12.--15. 1. "RESERVED1" newline hexmask.long.word 0x8 0.--11. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen One pixel wide region has value of 0" line.long 0xC "VP2_SAFETY_SIZE_3,The register configures the size of the safety sub-region n Shadow register." hexmask.long.byte 0xC 28.--31. 1. "RESERVED" newline hexmask.long.word 0xC 16.--27. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen One line height region has value of 0" newline hexmask.long.byte 0xC 12.--15. 1. "RESERVED1" newline hexmask.long.word 0xC 0.--11. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen One pixel wide region has value of 0" group.long 0x110++0x3 line.long 0x0 "VP2_SAFETY_LFSR_SEED,The register configures the seed initial signature value of MISRs that are to be initialized with a user programmed initial value. Otherwise. the MISR is initialized with 0xFFFF_FFFF. Shadow register." hexmask.long 0x0 0.--31. 1. "SEED,The register configures the seed [initial signature value] of MISRs that are to be initialized with a user programmed initial value Otherwise the MISR is initialized with 0xFFFF_FFFF Shadow register" wgroup.long 0x120++0x3F line.long 0x0 "VP2_GAMMA_TABLE_0,The register configures the gamma table on VP output." hexmask.long.byte 0x0 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x0 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x0 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x0 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x4 "VP2_GAMMA_TABLE_1,The register configures the gamma table on VP output." hexmask.long.byte 0x4 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x4 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x4 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x4 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x8 "VP2_GAMMA_TABLE_2,The register configures the gamma table on VP output." hexmask.long.byte 0x8 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x8 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x8 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x8 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0xC "VP2_GAMMA_TABLE_3,The register configures the gamma table on VP output." hexmask.long.byte 0xC 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0xC 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0xC 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0xC 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x10 "VP2_GAMMA_TABLE_4,The register configures the gamma table on VP output." hexmask.long.byte 0x10 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x10 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x10 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x10 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x14 "VP2_GAMMA_TABLE_5,The register configures the gamma table on VP output." hexmask.long.byte 0x14 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x14 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x14 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x14 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x18 "VP2_GAMMA_TABLE_6,The register configures the gamma table on VP output." hexmask.long.byte 0x18 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x18 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x18 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x18 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x1C "VP2_GAMMA_TABLE_7,The register configures the gamma table on VP output." hexmask.long.byte 0x1C 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x1C 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x1C 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x1C 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x20 "VP2_GAMMA_TABLE_8,The register configures the gamma table on VP output." hexmask.long.byte 0x20 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x20 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x20 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x20 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x24 "VP2_GAMMA_TABLE_9,The register configures the gamma table on VP output." hexmask.long.byte 0x24 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x24 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x24 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x24 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x28 "VP2_GAMMA_TABLE_10,The register configures the gamma table on VP output." hexmask.long.byte 0x28 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x28 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x28 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x28 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x2C "VP2_GAMMA_TABLE_11,The register configures the gamma table on VP output." hexmask.long.byte 0x2C 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x2C 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x2C 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x2C 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x30 "VP2_GAMMA_TABLE_12,The register configures the gamma table on VP output." hexmask.long.byte 0x30 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x30 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x30 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x30 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x34 "VP2_GAMMA_TABLE_13,The register configures the gamma table on VP output." hexmask.long.byte 0x34 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x34 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x34 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x34 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x38 "VP2_GAMMA_TABLE_14,The register configures the gamma table on VP output." hexmask.long.byte 0x38 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x38 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x38 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x38 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" line.long 0x3C "VP2_GAMMA_TABLE_15,The register configures the gamma table on VP output." hexmask.long.byte 0x3C 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored" newline hexmask.long.byte 0x3C 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table" newline hexmask.long.byte 0x3C 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table" newline hexmask.long.byte 0x3C 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table" group.long 0x160++0x3 line.long 0x0 "VP2_DSS_OLDI_CFG,This register configures the OLDI[N:0] modules connected to the DSS" bitfld.long 0x0 13. "TPATCFG,Test pattern Config" "0,1" newline bitfld.long 0x0 12. "SOFTRST,SoftWare Reset. By default OLDI is kept under reset" "0,1" newline bitfld.long 0x0 11. "DUALMODESYNC,DualMode Sync" "0,1" newline bitfld.long 0x0 10. "LBDATA,LoopBack Data" "0,1" newline bitfld.long 0x0 9. "LBEN,LoopBack Enable" "0,1" newline bitfld.long 0x0 8. "MSB,DSS bit-depth [for 18b LVDS only]" "0,1" newline bitfld.long 0x0 7. "DEPOL,Polarity of the DE signal" "0,1" newline bitfld.long 0x0 6. "MASTERSLAVE,Master selection in Dual mode only [typically tied off in the SoC]" "0,1" newline bitfld.long 0x0 5. "MODE,Single mode or duplicate mode" "0,1" newline bitfld.long 0x0 4. "SRC,Source Channel" "0,1" newline bitfld.long 0x0 1.--3. "MAP,Configuration of OLDI mapping Also indicates dual mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ENABLE,OLDI Enable" "0,1" rgroup.long 0x164++0x7 line.long 0x0 "VP2_DSS_OLDI_STATUS,This register captures the PID from the OLDI[N:0] modules connected to the DSS. Reads 0x0 if no OLDI is connected" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID Field" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL Revision" newline bitfld.long 0x0 8.--10. "REVMAJOR,Major Revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Revision" line.long 0x4 "VP2_DSS_OLDI_LB,This register captures the Loopback data from OLDI" hexmask.long.word 0x4 0.--9. 1. "LBRDATA,Returned Data from Loopback" tree.end tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "ECAP" base ad:0x0 tree "ECAP0_CTL_STS" base ad:0x23100000 group.long 0x0++0x17 line.long 0x0 "CTL_STS_TSCNT" hexmask.long 0x0 0.--31. 1. "TSCNT,Active 32 bit Counter register which is used as the Capture time-base" line.long 0x4 "CTL_STS_CNTPHS" hexmask.long 0x4 0.--31. 1. "CNTPHS,Counter Phase value register that can be programmed for phase Lag/Lead. This register shadows TSCNT and is loaded into TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve Phase control sync with respect to other ECAP.." line.long 0x8 "CTL_STS_CAP1" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes / initialisation 3. APRD shadow register (i.e. CAP3) when used in APWM mode" line.long 0xC "CTL_STS_CAP2" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes 3. ACMP shadow register (i.e. CAP4) when used in APWM mode" line.long 0x10 "CTL_STS_CAP3" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register In APMW mode this is the Period Shadow (APER) register. User updates the PWM Period value via this register. In this mode CAP3 (APRD) shadows CAP1" line.long 0x14 "CTL_STS_CAP4" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register In APMW mode this is the Compare Shadow (ACMP) register. User updates the PWM Compare value via this register. In this mode CAP4 (ACMP) shadows CAP2" group.long 0x28++0xB line.long 0x0 "CTL_STS_ECCTL" hexmask.long.byte 0x0 27.--31. 1. "FILTER" bitfld.long 0x0 26. "APWMPOL,APWM output polarity select: 1'b0 Output is Active High (i.e. Compare value defines High time); 1'b1 Output is Active Low (i.e. Compare value defines Low time); Note: This is applicable only in APWM operating mode" "0,1" newline bitfld.long 0x0 25. "CAP_APWM,CAP/APWM operating mode select: 1'b0 ECAP module operates in Capture mode This mode forces the following configuration: 1- Inhibits TSCNT resets via PRD_eq event 2- Inhibits Shadow loads on CAP1 & 2 registers 3- Permits User to enable CAP1-4.." "0,1" bitfld.long 0x0 24. "SWSYNC,Software forced Counter (TSCNT) sync'ing: 1'b0 Writing a Zero has no effect Reading will always return a zero; 1'b1 Writing a One will force a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits.." "0,1" newline bitfld.long 0x0 22.--23. "SYNCO_SEL,Sync-Out select: 2'b00 Select Sync-In event to be the Sync-Out signal (pass through); 2'b01 Select PRD_eq event to be the Sync-Out signal; 2'b10 DISABLE Sync Out Signal; 2'b11 DISABLE Sync Out Signal; Note: Selection PRD_eq is meaningful only.." "0,1,2,3" bitfld.long 0x0 21. "SYNCI_EN,Counter (TSCNT) Sync-In select mode: 1'b0 Disable Sync-In option 1'b1 Enable Counter (TSCNT) to be loaded from CNTPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.long 0x0 20. "TSCNTSTP,Counter Stop (freeze) Control: 1'b0 Counter Stopped; 1'b1 Counter Free Running" "0,1" bitfld.long 0x0 19. "REARM_RESET,One-Shot Re-arming i.e. Wait for stop Trigger: Writing a One Arms the One-Shot sequence i.e.: 1. Resets the Mod4 counter to zero 2. Un-freezes the Mod4 counter 3. Enables Capture Register Loads; Writing a zero has no effect. Reading always.." "0,1" newline bitfld.long 0x0 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1-4) of Captures allowed to occur before the CAP(1-4) registers are frozen i.e.Capture sequence is stopped. 2'b00 Stop after Capture Event 1; 2'b01 Stop after Capture Event 2; 2'b10.." "0,1,2,3" bitfld.long 0x0 16. "CONT_ONESHT,Continuous or Oneshot mode control: (applicable only in Capture mode) 1'b0 Operate in Continuous mode 1'b1 Operate in One-Shot mode" "0,1" newline bitfld.long 0x0 14.--15. "FREE_SOFT,Emulation Control 2'b00 TSCNT Counter stops immediately on emulation suspend; 2'b01 TSCNT Counter runs until = 0; 2'b1X TSCNT Counter is unaffected by emulation suspend (Run Free)" "0,1,2,3" hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,Event Filter prescale select: 5'b00000 divide by 1 (i.e. no prescale by-pass the prescaler); 5'b00001 divide by 2; 5'b00010 divide by 4; 5'b00011 divide by 6; 5'b00100 divide by 8; 5'b00101 divide by 10; . . . . .; 5'b11110 divide by 60;.." newline bitfld.long 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a Capture Event: 1'b0 Disable CAP1-4 register loads at capture Event time; 1'b1 Enable CAP1-4 register loads at capture Event time" "0,1" bitfld.long 0x0 7. "CTRRST4,Counter Reset on Capture Event 4: 1'b0 Do Not reset Counter on Capture Event 4 (absolute time stamp); 1'b1 Reset Counter after Event 4 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 6. "CAP4POL,Capture Event 4 Polarity select: 1'b0 Capture event 4 triggered on a Rising Edge (FE); 1'b1 Capture event 4 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 5. "CTRRST3,Counter Reset on Capture Event 3: 1'b0 Do Not reset Counter on Capture Event 3 (absolute time stamp); 1'b1 Reset Counter after Event 3 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 4. "CAP3POL,Capture Event 3 Polarity select: 1'b0 Capture event 3 triggered on a Rising Edge (FE); 1'b1 Capture event 3 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 3. "CTRRST2,Counter Reset on Capture Event 2: 1'b0 Do Not reset Counter on Capture Event 2 (absolute time stamp); 1'b1 Reset Counter after Event 2 time-stamp has been captured (used in Difference mode operation)" "?,?" newline bitfld.long 0x0 2. "CAP2POL,Capture Event 2 Polarity select: 1'b0 Capture event 2 triggered on a Rising Edge (FE); 1'b1 Capture event 2 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 1. "CTRRST1,Counter Reset on Capture Event 1: 1'b0 Do Not reset Counter on Capture Event 1 (absolute time stamp); 1'b1 Reset Counter after Event 1 time-stamp has been captured (used in Difference mode operation)" "?,1: 1'b0 Do Not reset Counter on Capture Event 1" newline bitfld.long 0x0 0. "CAP1POL,Capture Event 1 Polarity select: 1'b0 Capture event 1 triggered on a Rising Edge (FE); 1'b1 Capture event 1 triggered on a Falling Edge (FE)" "0,1" line.long 0x4 "CTL_STS_ECINT_EN_FLG" rbitfld.long 0x4 23. "CMPEQ_FLG,Compare Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Compare register value (ACMP) Reading a 0 indicates no event occurred Note: This flag is only active in APWM mode." "0,1" rbitfld.long 0x4 22. "PRDEQ_FLG,Period Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Period register value (APER) and was reset. Reading a 0 indicates no event occurred Notes: This flag is only active in APWM mode." "0,1" newline rbitfld.long 0x4 21. "CNTOVF_FLG,Counter Overflow Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) has made the transition from 0xFFFFFFFF 0x00000000 Reading a 0 indicates no event occurred. Note: This flag is active in CAP & APWM mode." "0,1" rbitfld.long 0x4 20. "CEVT4_FLG,Capture Event 4 Status Flag: Reading a 1 on this bit indicates the fourth event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" newline rbitfld.long 0x4 19. "CEVT3_FLG,Capture Event 3 Status Flag: Reading a 1 on this bit indicates the third event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" rbitfld.long 0x4 18. "CEVT2_FLG,Capture Event 2 Status Flag: Reading a 1 on this bit indicates the second event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" newline rbitfld.long 0x4 17. "CEVT1_FLG,Capture Event 1 Status Flag: Reading a 1 on this bit indicates the first event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" rbitfld.long 0x4 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events. Reading a 0 indicates no interrupt generated." "0,1" newline bitfld.long 0x4 7. "CMPEQ_EN,Compare Equal Interrupt Enable: 1'b0 Disabled Compare Equal as an Interrupt source; 1'b1 Enable Compare Equal as an Interrupt source" "0,1" bitfld.long 0x4 6. "PRDEQ_EN,Period Equal Interrupt Enable: 1'b0 Disabled Period Equal as an Interrupt source; 1'b1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.long 0x4 5. "CNTOVF_EN,Counter Overflow Interrupt Enable: 1'b0 Disabled Counter Overflow as an Interrupt source; 1'b1 Enable Counter Overflow as an Interrupt source" "0,1" bitfld.long 0x4 4. "CEVT4_EN,Capture Event 4 Interrupt Enable: 1'b0 Disabled Capture Event 4 as an Interrupt source: 1'b1 Enable Capture Event 4 as an Interrupt source" "0,1" newline bitfld.long 0x4 3. "CEVT3_EN,Capture Event 3 Interrupt Enable: 1'b0 Disabled Capture Event 3 as an Interrupt source: 1'b1 Enable Capture Event 3 as an Interrupt source" "0,1" bitfld.long 0x4 2. "CEVT2_EN,Capture Event 2 Interrupt Enable: 1'b0 Disabled Capture Event 2 as an Interrupt source: 1'b1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.long 0x4 1. "CEVT1_EN,Capture Event 1 Interrupt Enable: 1'b0 Disabled Capture Event 1 as an Interrupt source: 1'b1 Enable Capture Event 1 as an Interrupt source" "0,1" line.long 0x8 "CTL_STS_ECINT_CLR_FRC" bitfld.long 0x8 23. "CMPEQ_FRC,Force Compare Equal: Writing a 1 to this bit will set the CMPEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 22. "PRDEQ_FRC,Force Period Equal: Writing a 1 to this bit will set the PRDEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" newline bitfld.long 0x8 21. "CNTOVF_FRC,Force Counter Overflow: Writing a 1 to this bit will set the CNTOVF flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 20. "CEVT4_FRC,Force Capture Event 4: Writing a 1 to this bit will set the CEVT4 flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" newline bitfld.long 0x8 19. "CEVT3_FRC,Force Capture Event 3: Writing a 1 to this bit will set the CEVT3 flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 18. "CEVT2_FRC,Force Capture Event 2: Writing a 1 to this bit will set the CEVT2 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,?" newline bitfld.long 0x8 17. "CEVT1_FRC,Force Capture Event 1: Writing a 1 to this bit will set the CEVT1 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,1: Writing a 1 to this bit will set the CEVT1 flag.." bitfld.long 0x8 7. "CMPEQ_CLR,Compare Equal Status Flag: Writing a 1 will clear the CMPEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 6. "PRDEQ_CLR,Period Equal Status Flag: Writing a 1 will clear the PRDEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 5. "CNTOVF_CLR,Counter Overflow Status Flag: Writing a 1 will clear the CNTOVF flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 4. "CEVT4_CLR,Capture Event 4 Status Flag: Writing a 1 will clear the CEVT4 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 3. "CEVT3_CLR,Capture Event 3 Status Flag: Writing a 1 will clear the CEVT3 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 2. "CEVT2_CLR,Capture Event 2 Status Flag: Writing a 1 will clear the CEVT2 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 1. "CEVT1_CLR,Capture Event 1 Status Flag: Writing a 1 will clear the CEVT1 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the INT flag and enable further interrupts to be generated if any of the event flags are set to 1. Writing a 0 will have no effect. Always reads back a 0." "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "CTL_STS_PID" bitfld.long 0x0 30.--31. "SCHEME" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION" hexmask.long.byte 0x0 11.--15. 1. "RTL" newline bitfld.long 0x0 8.--10. "MAJOR" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR" tree.end tree "ECAP1_CTL_STS" base ad:0x23110000 group.long 0x0++0x17 line.long 0x0 "CTL_STS_TSCNT" hexmask.long 0x0 0.--31. 1. "TSCNT,Active 32 bit Counter register which is used as the Capture time-base" line.long 0x4 "CTL_STS_CNTPHS" hexmask.long 0x4 0.--31. 1. "CNTPHS,Counter Phase value register that can be programmed for phase Lag/Lead. This register shadows TSCNT and is loaded into TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve Phase control sync with respect to other ECAP.." line.long 0x8 "CTL_STS_CAP1" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes / initialisation 3. APRD shadow register (i.e. CAP3) when used in APWM mode" line.long 0xC "CTL_STS_CAP2" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes 3. ACMP shadow register (i.e. CAP4) when used in APWM mode" line.long 0x10 "CTL_STS_CAP3" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register In APMW mode this is the Period Shadow (APER) register. User updates the PWM Period value via this register. In this mode CAP3 (APRD) shadows CAP1" line.long 0x14 "CTL_STS_CAP4" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register In APMW mode this is the Compare Shadow (ACMP) register. User updates the PWM Compare value via this register. In this mode CAP4 (ACMP) shadows CAP2" group.long 0x28++0xB line.long 0x0 "CTL_STS_ECCTL" hexmask.long.byte 0x0 27.--31. 1. "FILTER" bitfld.long 0x0 26. "APWMPOL,APWM output polarity select: 1'b0 Output is Active High (i.e. Compare value defines High time); 1'b1 Output is Active Low (i.e. Compare value defines Low time); Note: This is applicable only in APWM operating mode" "0,1" newline bitfld.long 0x0 25. "CAP_APWM,CAP/APWM operating mode select: 1'b0 ECAP module operates in Capture mode This mode forces the following configuration: 1- Inhibits TSCNT resets via PRD_eq event 2- Inhibits Shadow loads on CAP1 & 2 registers 3- Permits User to enable CAP1-4.." "0,1" bitfld.long 0x0 24. "SWSYNC,Software forced Counter (TSCNT) sync'ing: 1'b0 Writing a Zero has no effect Reading will always return a zero; 1'b1 Writing a One will force a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits.." "0,1" newline bitfld.long 0x0 22.--23. "SYNCO_SEL,Sync-Out select: 2'b00 Select Sync-In event to be the Sync-Out signal (pass through); 2'b01 Select PRD_eq event to be the Sync-Out signal; 2'b10 DISABLE Sync Out Signal; 2'b11 DISABLE Sync Out Signal; Note: Selection PRD_eq is meaningful only.." "0,1,2,3" bitfld.long 0x0 21. "SYNCI_EN,Counter (TSCNT) Sync-In select mode: 1'b0 Disable Sync-In option 1'b1 Enable Counter (TSCNT) to be loaded from CNTPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.long 0x0 20. "TSCNTSTP,Counter Stop (freeze) Control: 1'b0 Counter Stopped; 1'b1 Counter Free Running" "0,1" bitfld.long 0x0 19. "REARM_RESET,One-Shot Re-arming i.e. Wait for stop Trigger: Writing a One Arms the One-Shot sequence i.e.: 1. Resets the Mod4 counter to zero 2. Un-freezes the Mod4 counter 3. Enables Capture Register Loads; Writing a zero has no effect. Reading always.." "0,1" newline bitfld.long 0x0 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1-4) of Captures allowed to occur before the CAP(1-4) registers are frozen i.e.Capture sequence is stopped. 2'b00 Stop after Capture Event 1; 2'b01 Stop after Capture Event 2; 2'b10.." "0,1,2,3" bitfld.long 0x0 16. "CONT_ONESHT,Continuous or Oneshot mode control: (applicable only in Capture mode) 1'b0 Operate in Continuous mode 1'b1 Operate in One-Shot mode" "0,1" newline bitfld.long 0x0 14.--15. "FREE_SOFT,Emulation Control 2'b00 TSCNT Counter stops immediately on emulation suspend; 2'b01 TSCNT Counter runs until = 0; 2'b1X TSCNT Counter is unaffected by emulation suspend (Run Free)" "0,1,2,3" hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,Event Filter prescale select: 5'b00000 divide by 1 (i.e. no prescale by-pass the prescaler); 5'b00001 divide by 2; 5'b00010 divide by 4; 5'b00011 divide by 6; 5'b00100 divide by 8; 5'b00101 divide by 10; . . . . .; 5'b11110 divide by 60;.." newline bitfld.long 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a Capture Event: 1'b0 Disable CAP1-4 register loads at capture Event time; 1'b1 Enable CAP1-4 register loads at capture Event time" "0,1" bitfld.long 0x0 7. "CTRRST4,Counter Reset on Capture Event 4: 1'b0 Do Not reset Counter on Capture Event 4 (absolute time stamp); 1'b1 Reset Counter after Event 4 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 6. "CAP4POL,Capture Event 4 Polarity select: 1'b0 Capture event 4 triggered on a Rising Edge (FE); 1'b1 Capture event 4 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 5. "CTRRST3,Counter Reset on Capture Event 3: 1'b0 Do Not reset Counter on Capture Event 3 (absolute time stamp); 1'b1 Reset Counter after Event 3 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 4. "CAP3POL,Capture Event 3 Polarity select: 1'b0 Capture event 3 triggered on a Rising Edge (FE); 1'b1 Capture event 3 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 3. "CTRRST2,Counter Reset on Capture Event 2: 1'b0 Do Not reset Counter on Capture Event 2 (absolute time stamp); 1'b1 Reset Counter after Event 2 time-stamp has been captured (used in Difference mode operation)" "?,?" newline bitfld.long 0x0 2. "CAP2POL,Capture Event 2 Polarity select: 1'b0 Capture event 2 triggered on a Rising Edge (FE); 1'b1 Capture event 2 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 1. "CTRRST1,Counter Reset on Capture Event 1: 1'b0 Do Not reset Counter on Capture Event 1 (absolute time stamp); 1'b1 Reset Counter after Event 1 time-stamp has been captured (used in Difference mode operation)" "?,1: 1'b0 Do Not reset Counter on Capture Event 1" newline bitfld.long 0x0 0. "CAP1POL,Capture Event 1 Polarity select: 1'b0 Capture event 1 triggered on a Rising Edge (FE); 1'b1 Capture event 1 triggered on a Falling Edge (FE)" "0,1" line.long 0x4 "CTL_STS_ECINT_EN_FLG" rbitfld.long 0x4 23. "CMPEQ_FLG,Compare Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Compare register value (ACMP) Reading a 0 indicates no event occurred Note: This flag is only active in APWM mode." "0,1" rbitfld.long 0x4 22. "PRDEQ_FLG,Period Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Period register value (APER) and was reset. Reading a 0 indicates no event occurred Notes: This flag is only active in APWM mode." "0,1" newline rbitfld.long 0x4 21. "CNTOVF_FLG,Counter Overflow Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) has made the transition from 0xFFFFFFFF 0x00000000 Reading a 0 indicates no event occurred. Note: This flag is active in CAP & APWM mode." "0,1" rbitfld.long 0x4 20. "CEVT4_FLG,Capture Event 4 Status Flag: Reading a 1 on this bit indicates the fourth event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" newline rbitfld.long 0x4 19. "CEVT3_FLG,Capture Event 3 Status Flag: Reading a 1 on this bit indicates the third event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" rbitfld.long 0x4 18. "CEVT2_FLG,Capture Event 2 Status Flag: Reading a 1 on this bit indicates the second event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" newline rbitfld.long 0x4 17. "CEVT1_FLG,Capture Event 1 Status Flag: Reading a 1 on this bit indicates the first event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" rbitfld.long 0x4 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events. Reading a 0 indicates no interrupt generated." "0,1" newline bitfld.long 0x4 7. "CMPEQ_EN,Compare Equal Interrupt Enable: 1'b0 Disabled Compare Equal as an Interrupt source; 1'b1 Enable Compare Equal as an Interrupt source" "0,1" bitfld.long 0x4 6. "PRDEQ_EN,Period Equal Interrupt Enable: 1'b0 Disabled Period Equal as an Interrupt source; 1'b1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.long 0x4 5. "CNTOVF_EN,Counter Overflow Interrupt Enable: 1'b0 Disabled Counter Overflow as an Interrupt source; 1'b1 Enable Counter Overflow as an Interrupt source" "0,1" bitfld.long 0x4 4. "CEVT4_EN,Capture Event 4 Interrupt Enable: 1'b0 Disabled Capture Event 4 as an Interrupt source: 1'b1 Enable Capture Event 4 as an Interrupt source" "0,1" newline bitfld.long 0x4 3. "CEVT3_EN,Capture Event 3 Interrupt Enable: 1'b0 Disabled Capture Event 3 as an Interrupt source: 1'b1 Enable Capture Event 3 as an Interrupt source" "0,1" bitfld.long 0x4 2. "CEVT2_EN,Capture Event 2 Interrupt Enable: 1'b0 Disabled Capture Event 2 as an Interrupt source: 1'b1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.long 0x4 1. "CEVT1_EN,Capture Event 1 Interrupt Enable: 1'b0 Disabled Capture Event 1 as an Interrupt source: 1'b1 Enable Capture Event 1 as an Interrupt source" "0,1" line.long 0x8 "CTL_STS_ECINT_CLR_FRC" bitfld.long 0x8 23. "CMPEQ_FRC,Force Compare Equal: Writing a 1 to this bit will set the CMPEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 22. "PRDEQ_FRC,Force Period Equal: Writing a 1 to this bit will set the PRDEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" newline bitfld.long 0x8 21. "CNTOVF_FRC,Force Counter Overflow: Writing a 1 to this bit will set the CNTOVF flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 20. "CEVT4_FRC,Force Capture Event 4: Writing a 1 to this bit will set the CEVT4 flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" newline bitfld.long 0x8 19. "CEVT3_FRC,Force Capture Event 3: Writing a 1 to this bit will set the CEVT3 flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 18. "CEVT2_FRC,Force Capture Event 2: Writing a 1 to this bit will set the CEVT2 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,?" newline bitfld.long 0x8 17. "CEVT1_FRC,Force Capture Event 1: Writing a 1 to this bit will set the CEVT1 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,1: Writing a 1 to this bit will set the CEVT1 flag.." bitfld.long 0x8 7. "CMPEQ_CLR,Compare Equal Status Flag: Writing a 1 will clear the CMPEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 6. "PRDEQ_CLR,Period Equal Status Flag: Writing a 1 will clear the PRDEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 5. "CNTOVF_CLR,Counter Overflow Status Flag: Writing a 1 will clear the CNTOVF flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 4. "CEVT4_CLR,Capture Event 4 Status Flag: Writing a 1 will clear the CEVT4 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 3. "CEVT3_CLR,Capture Event 3 Status Flag: Writing a 1 will clear the CEVT3 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 2. "CEVT2_CLR,Capture Event 2 Status Flag: Writing a 1 will clear the CEVT2 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 1. "CEVT1_CLR,Capture Event 1 Status Flag: Writing a 1 will clear the CEVT1 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the INT flag and enable further interrupts to be generated if any of the event flags are set to 1. Writing a 0 will have no effect. Always reads back a 0." "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "CTL_STS_PID" bitfld.long 0x0 30.--31. "SCHEME" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION" hexmask.long.byte 0x0 11.--15. 1. "RTL" newline bitfld.long 0x0 8.--10. "MAJOR" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR" tree.end tree "ECAP2_CTL_STS" base ad:0x23120000 group.long 0x0++0x17 line.long 0x0 "CTL_STS_TSCNT" hexmask.long 0x0 0.--31. 1. "TSCNT,Active 32 bit Counter register which is used as the Capture time-base" line.long 0x4 "CTL_STS_CNTPHS" hexmask.long 0x4 0.--31. 1. "CNTPHS,Counter Phase value register that can be programmed for phase Lag/Lead. This register shadows TSCNT and is loaded into TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve Phase control sync with respect to other ECAP.." line.long 0x8 "CTL_STS_CAP1" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes / initialisation 3. APRD shadow register (i.e. CAP3) when used in APWM mode" line.long 0xC "CTL_STS_CAP2" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by : 1. Time-Stamp (i.e. counter value) during a Capture event 2. S/W - may be useful for test purposes 3. ACMP shadow register (i.e. CAP4) when used in APWM mode" line.long 0x10 "CTL_STS_CAP3" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register In APMW mode this is the Period Shadow (APER) register. User updates the PWM Period value via this register. In this mode CAP3 (APRD) shadows CAP1" line.long 0x14 "CTL_STS_CAP4" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register In APMW mode this is the Compare Shadow (ACMP) register. User updates the PWM Compare value via this register. In this mode CAP4 (ACMP) shadows CAP2" group.long 0x28++0xB line.long 0x0 "CTL_STS_ECCTL" hexmask.long.byte 0x0 27.--31. 1. "FILTER" bitfld.long 0x0 26. "APWMPOL,APWM output polarity select: 1'b0 Output is Active High (i.e. Compare value defines High time); 1'b1 Output is Active Low (i.e. Compare value defines Low time); Note: This is applicable only in APWM operating mode" "0,1" newline bitfld.long 0x0 25. "CAP_APWM,CAP/APWM operating mode select: 1'b0 ECAP module operates in Capture mode This mode forces the following configuration: 1- Inhibits TSCNT resets via PRD_eq event 2- Inhibits Shadow loads on CAP1 & 2 registers 3- Permits User to enable CAP1-4.." "0,1" bitfld.long 0x0 24. "SWSYNC,Software forced Counter (TSCNT) sync'ing: 1'b0 Writing a Zero has no effect Reading will always return a zero; 1'b1 Writing a One will force a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits.." "0,1" newline bitfld.long 0x0 22.--23. "SYNCO_SEL,Sync-Out select: 2'b00 Select Sync-In event to be the Sync-Out signal (pass through); 2'b01 Select PRD_eq event to be the Sync-Out signal; 2'b10 DISABLE Sync Out Signal; 2'b11 DISABLE Sync Out Signal; Note: Selection PRD_eq is meaningful only.." "0,1,2,3" bitfld.long 0x0 21. "SYNCI_EN,Counter (TSCNT) Sync-In select mode: 1'b0 Disable Sync-In option 1'b1 Enable Counter (TSCNT) to be loaded from CNTPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.long 0x0 20. "TSCNTSTP,Counter Stop (freeze) Control: 1'b0 Counter Stopped; 1'b1 Counter Free Running" "0,1" bitfld.long 0x0 19. "REARM_RESET,One-Shot Re-arming i.e. Wait for stop Trigger: Writing a One Arms the One-Shot sequence i.e.: 1. Resets the Mod4 counter to zero 2. Un-freezes the Mod4 counter 3. Enables Capture Register Loads; Writing a zero has no effect. Reading always.." "0,1" newline bitfld.long 0x0 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1-4) of Captures allowed to occur before the CAP(1-4) registers are frozen i.e.Capture sequence is stopped. 2'b00 Stop after Capture Event 1; 2'b01 Stop after Capture Event 2; 2'b10.." "0,1,2,3" bitfld.long 0x0 16. "CONT_ONESHT,Continuous or Oneshot mode control: (applicable only in Capture mode) 1'b0 Operate in Continuous mode 1'b1 Operate in One-Shot mode" "0,1" newline bitfld.long 0x0 14.--15. "FREE_SOFT,Emulation Control 2'b00 TSCNT Counter stops immediately on emulation suspend; 2'b01 TSCNT Counter runs until = 0; 2'b1X TSCNT Counter is unaffected by emulation suspend (Run Free)" "0,1,2,3" hexmask.long.byte 0x0 9.--13. 1. "EVTFLTPS,Event Filter prescale select: 5'b00000 divide by 1 (i.e. no prescale by-pass the prescaler); 5'b00001 divide by 2; 5'b00010 divide by 4; 5'b00011 divide by 6; 5'b00100 divide by 8; 5'b00101 divide by 10; . . . . .; 5'b11110 divide by 60;.." newline bitfld.long 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a Capture Event: 1'b0 Disable CAP1-4 register loads at capture Event time; 1'b1 Enable CAP1-4 register loads at capture Event time" "0,1" bitfld.long 0x0 7. "CTRRST4,Counter Reset on Capture Event 4: 1'b0 Do Not reset Counter on Capture Event 4 (absolute time stamp); 1'b1 Reset Counter after Event 4 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 6. "CAP4POL,Capture Event 4 Polarity select: 1'b0 Capture event 4 triggered on a Rising Edge (FE); 1'b1 Capture event 4 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 5. "CTRRST3,Counter Reset on Capture Event 3: 1'b0 Do Not reset Counter on Capture Event 3 (absolute time stamp); 1'b1 Reset Counter after Event 3 time-stamp has been captured (used in Difference mode operation)" "0,1" newline bitfld.long 0x0 4. "CAP3POL,Capture Event 3 Polarity select: 1'b0 Capture event 3 triggered on a Rising Edge (FE); 1'b1 Capture event 3 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 3. "CTRRST2,Counter Reset on Capture Event 2: 1'b0 Do Not reset Counter on Capture Event 2 (absolute time stamp); 1'b1 Reset Counter after Event 2 time-stamp has been captured (used in Difference mode operation)" "?,?" newline bitfld.long 0x0 2. "CAP2POL,Capture Event 2 Polarity select: 1'b0 Capture event 2 triggered on a Rising Edge (FE); 1'b1 Capture event 2 triggered on a Falling Edge (FE)" "0,1" bitfld.long 0x0 1. "CTRRST1,Counter Reset on Capture Event 1: 1'b0 Do Not reset Counter on Capture Event 1 (absolute time stamp); 1'b1 Reset Counter after Event 1 time-stamp has been captured (used in Difference mode operation)" "?,1: 1'b0 Do Not reset Counter on Capture Event 1" newline bitfld.long 0x0 0. "CAP1POL,Capture Event 1 Polarity select: 1'b0 Capture event 1 triggered on a Rising Edge (FE); 1'b1 Capture event 1 triggered on a Falling Edge (FE)" "0,1" line.long 0x4 "CTL_STS_ECINT_EN_FLG" rbitfld.long 0x4 23. "CMPEQ_FLG,Compare Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Compare register value (ACMP) Reading a 0 indicates no event occurred Note: This flag is only active in APWM mode." "0,1" rbitfld.long 0x4 22. "PRDEQ_FLG,Period Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Period register value (APER) and was reset. Reading a 0 indicates no event occurred Notes: This flag is only active in APWM mode." "0,1" newline rbitfld.long 0x4 21. "CNTOVF_FLG,Counter Overflow Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) has made the transition from 0xFFFFFFFF 0x00000000 Reading a 0 indicates no event occurred. Note: This flag is active in CAP & APWM mode." "0,1" rbitfld.long 0x4 20. "CEVT4_FLG,Capture Event 4 Status Flag: Reading a 1 on this bit indicates the fourth event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" newline rbitfld.long 0x4 19. "CEVT3_FLG,Capture Event 3 Status Flag: Reading a 1 on this bit indicates the third event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" rbitfld.long 0x4 18. "CEVT2_FLG,Capture Event 2 Status Flag: Reading a 1 on this bit indicates the second event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" newline rbitfld.long 0x4 17. "CEVT1_FLG,Capture Event 1 Status Flag: Reading a 1 on this bit indicates the first event occurred at ECAPx pin. Reading a 0 indicates no event occurred. Note: This flag is only active in CAP mode." "0,1" rbitfld.long 0x4 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events. Reading a 0 indicates no interrupt generated." "0,1" newline bitfld.long 0x4 7. "CMPEQ_EN,Compare Equal Interrupt Enable: 1'b0 Disabled Compare Equal as an Interrupt source; 1'b1 Enable Compare Equal as an Interrupt source" "0,1" bitfld.long 0x4 6. "PRDEQ_EN,Period Equal Interrupt Enable: 1'b0 Disabled Period Equal as an Interrupt source; 1'b1 Enable Period Equal as an Interrupt source" "0,1" newline bitfld.long 0x4 5. "CNTOVF_EN,Counter Overflow Interrupt Enable: 1'b0 Disabled Counter Overflow as an Interrupt source; 1'b1 Enable Counter Overflow as an Interrupt source" "0,1" bitfld.long 0x4 4. "CEVT4_EN,Capture Event 4 Interrupt Enable: 1'b0 Disabled Capture Event 4 as an Interrupt source: 1'b1 Enable Capture Event 4 as an Interrupt source" "0,1" newline bitfld.long 0x4 3. "CEVT3_EN,Capture Event 3 Interrupt Enable: 1'b0 Disabled Capture Event 3 as an Interrupt source: 1'b1 Enable Capture Event 3 as an Interrupt source" "0,1" bitfld.long 0x4 2. "CEVT2_EN,Capture Event 2 Interrupt Enable: 1'b0 Disabled Capture Event 2 as an Interrupt source: 1'b1 Enable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.long 0x4 1. "CEVT1_EN,Capture Event 1 Interrupt Enable: 1'b0 Disabled Capture Event 1 as an Interrupt source: 1'b1 Enable Capture Event 1 as an Interrupt source" "0,1" line.long 0x8 "CTL_STS_ECINT_CLR_FRC" bitfld.long 0x8 23. "CMPEQ_FRC,Force Compare Equal: Writing a 1 to this bit will set the CMPEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 22. "PRDEQ_FRC,Force Period Equal: Writing a 1 to this bit will set the PRDEQ flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" newline bitfld.long 0x8 21. "CNTOVF_FRC,Force Counter Overflow: Writing a 1 to this bit will set the CNTOVF flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 20. "CEVT4_FRC,Force Capture Event 4: Writing a 1 to this bit will set the CEVT4 flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" newline bitfld.long 0x8 19. "CEVT3_FRC,Force Capture Event 3: Writing a 1 to this bit will set the CEVT3 flag bit. Writing of 0 will be ignored. Always reads back a 0." "0,1" bitfld.long 0x8 18. "CEVT2_FRC,Force Capture Event 2: Writing a 1 to this bit will set the CEVT2 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,?" newline bitfld.long 0x8 17. "CEVT1_FRC,Force Capture Event 1: Writing a 1 to this bit will set the CEVT1 flag bit. Writing of 0 will be ignored. Always reads back a 0." "?,1: Writing a 1 to this bit will set the CEVT1 flag.." bitfld.long 0x8 7. "CMPEQ_CLR,Compare Equal Status Flag: Writing a 1 will clear the CMPEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 6. "PRDEQ_CLR,Period Equal Status Flag: Writing a 1 will clear the PRDEQ flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 5. "CNTOVF_CLR,Counter Overflow Status Flag: Writing a 1 will clear the CNTOVF flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 4. "CEVT4_CLR,Capture Event 4 Status Flag: Writing a 1 will clear the CEVT4 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 3. "CEVT3_CLR,Capture Event 3 Status Flag: Writing a 1 will clear the CEVT3 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 2. "CEVT2_CLR,Capture Event 2 Status Flag: Writing a 1 will clear the CEVT2 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" bitfld.long 0x8 1. "CEVT1_CLR,Capture Event 1 Status Flag: Writing a 1 will clear the CEVT1 flag condition. Writing a 0 will have no effect. Always reads back a 0." "0,1" newline bitfld.long 0x8 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the INT flag and enable further interrupts to be generated if any of the event flags are set to 1. Writing a 0 will have no effect. Always reads back a 0." "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "CTL_STS_PID" bitfld.long 0x0 30.--31. "SCHEME" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION" hexmask.long.byte 0x0 11.--15. 1. "RTL" newline bitfld.long 0x0 8.--10. "MAJOR" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR" tree.end tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "EFUSE0" base ad:0x300000 group.long 0x0++0xB line.long 0x0 "MEM_SYS_STATUS,efuse system_status" hexmask.long 0x0 0.--31. 1. "STATUS,efuse system status" line.long 0x4 "MEM_OCP_CTRL_LOWER,OCP control" hexmask.long 0x4 0.--31. 1. "OCP_CONTROL_LOWER,ocp_control_lower" line.long 0x8 "MEM_OCP_CTRL_UPPER,OCP control" hexmask.long 0x8 0.--31. 1. "OCP_CONTROL_UPPER,ocp_control_upper" group.long 0x10++0x3 line.long 0x0 "MEM_SYS_CONFIG,System config" hexmask.long 0x0 0.--31. 1. "SYS_CONFIG,efuse system config" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "ELM0" base ad:0x25010000 rgroup.long 0x0++0x3 line.long 0x0 "MEM_ELM_REVISION,This register contains the IP revision code." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_0,Read returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV_NUMBER,IP revision number [RTL] [7:4] Major revision [3:0] Minor revision" group.long 0x10++0x3 line.long 0x0 "MEM_ELM_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x0 8. "CLOCKACTIVITYOCP,OCP Clock activity when module is in IDLE mode [during wake up mode period]" "0,1" bitfld.long 0x0 3.--4. "SIDLEMODE,Slave interface power management [IDLE req/ack control]" "0,1,2,3" newline bitfld.long 0x0 1. "SOFTRESET,Module Software Reset The bit is automatically reset by the hardware [During reads it always returns 0] It has same effect as the OCP Hardware reset" "0,1" bitfld.long 0x0 0. "AUTOGATING,Internal OCP clock gating strategy [no module visible impact other than saving power]" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_ELM_SYSSTATUS,Internal Reset monitoring (OCP domain)" bitfld.long 0x0 0. "RESETDONE,Internal Reset monitoring [OCP domain] Undefined since: on HW perspective reset state is 0 on SW user perspective when module is accessible is 1" "0,1" group.long 0x18++0xB line.long 0x0 "MEM_ELM_IRQSTATUS,Interrupt status. This register doubles as a status register for the error location processes." bitfld.long 0x0 8. "PAGE_VALID,Error location status for a full page based on the mask definition Read 0x0: error locations invalid for all polynomials enabled in the ECC_INTERRUPT_MASK register Read 0x1: all error locations valid Write 0x0: no effect Write 0x1: clear.." "0: no effect Write,1: clear interrupt" bitfld.long 0x0 7. "LOC_VALID_7,Error location status for syndrome polynomial 7 Read 0x0: no syndrome processed or process in progress Read 0x1: error location process completed Write 0x0: no effect Write 0x1: clear interrupt" "0: no effect Write,1: clear interrupt" newline bitfld.long 0x0 6. "LOC_VALID_6,Error location status for syndrome polynomial 6" "0,1" bitfld.long 0x0 5. "LOC_VALID_5,Error location status for syndrome polynomial 5" "0,1" newline bitfld.long 0x0 4. "LOC_VALID_4,Error location status for syndrome polynomial 4" "0,1" bitfld.long 0x0 3. "LOC_VALID_3,Error location status for syndrome polynomial 3" "0,1" newline bitfld.long 0x0 2. "LOC_VALID_2,Error location status for syndrome polynomial 2" "0,1" bitfld.long 0x0 1. "LOC_VALID_1,Error location status for syndrome polynomial 1" "0,1" newline bitfld.long 0x0 0. "LOC_VALID_0,Error location status for syndrome polynomial 0" "0,1" line.long 0x4 "MEM_ELM_IRQENABLE,Interrupt enable" bitfld.long 0x4 8. "PAGE_MASK,Page interrupt mask bit 0: disable interrupt 1: enable interrupt" "0: disable interrupt,1: enable interrupt" bitfld.long 0x4 7. "LOCATION_MASK_7,Error location interrupt mask bit for syndrome polynomial 7" "0,1" newline bitfld.long 0x4 6. "LOCATION_MASK_6,Error location interrupt mask bit for syndrome polynomial 6" "0,1" bitfld.long 0x4 5. "LOCATION_MASK_5,Error location interrupt mask bit for syndrome polynomial 5" "0,1" newline bitfld.long 0x4 4. "LOCATION_MASK_4,Error location interrupt mask bit for syndrome polynomial 4" "0,1" bitfld.long 0x4 3. "LOCATION_MASK_3,Error location interrupt mask bit for syndrome polynomial 3" "0,1" newline bitfld.long 0x4 2. "LOCATION_MASK_2,Error location interrupt mask bit for syndrome polynomial 2" "0,1" bitfld.long 0x4 1. "LOCATION_MASK_1,Error location interrupt mask bit for syndrome polynomial 1" "0,1" newline bitfld.long 0x4 0. "LOCATION_MASK_0,Error location interrupt mask bit for syndrome polynomial 0 0: disable interrupt 1: enable interrupt" "0: disable interrupt,1: enable interrupt" line.long 0x8 "MEM_ELM_LOCATION_CONFIG,ECC algorithm parameters" hexmask.long.word 0x8 16.--26. 1. "ECC_SIZE,Maximum size of the buffers for which the error location engine is used in number of nibbles [4-bits entities]" bitfld.long 0x8 0.--1. "ECC_BCH_LEVEL,Error correction level 0x0: 4 bits 0x1: 8 bits 0x2: 16 bits 0x3: reserved" "0: 4 bits,1: 8 bits,2: 16 bits,3: reserved" group.long 0x80++0x3 line.long 0x0 "MEM_ELM_PAGE_CTRL,Page definition" bitfld.long 0x0 7. "SECTOR_7,Set to 1 if syndrome polynomial 7 is part of the page in page mode Must be 0 in continuous mode" "0,1" bitfld.long 0x0 6. "SECTOR_6,Set to 1 if syndrome polynomial 6 is part of the page in page mode Must be 0 in continuous mode" "0,1" newline bitfld.long 0x0 5. "SECTOR_5,Set to 1 if syndrome polynomial 5 is part of the page in page mode Must be 0 in continuous mode" "0,1" bitfld.long 0x0 4. "SECTOR_4,Set to 1 if syndrome polynomial 4 is part of the page in page mode Must be 0 in continuous mode" "0,1" newline bitfld.long 0x0 3. "SECTOR_3,Set to 1 if syndrome polynomial 3 is part of the page in page mode Must be 0 in continuous mode" "0,1" bitfld.long 0x0 2. "SECTOR_2,Set to 1 if syndrome polynomial 2 is part of the page in page mode Must be 0 in continuous mode" "0,1" newline bitfld.long 0x0 1. "SECTOR_1,Set to 1 if syndrome polynomial 1 is part of the page in page mode Must be 0 in continuous mode" "0,1" bitfld.long 0x0 0. "SECTOR_0,Set to 1 if syndrome polynomial 0 is part of the page in page mode Must be 0 in continuous mode" "0,1" group.long 0x400++0x1B line.long 0x0 "MEM_ELM_SYNDROME_FRAGMENT_0,Input syndrome polynomial bits 0 to 31." hexmask.long 0x0 0.--31. 1. "SYNDROME_0,Syndrome bits 0 to 31" line.long 0x4 "MEM_ELM_SYNDROME_FRAGMENT_1,Input syndrome polynomial bits 32 to 63." hexmask.long 0x4 0.--31. 1. "SYNDROME_1,Syndrome bits 32 to 63" line.long 0x8 "MEM_ELM_SYNDROME_FRAGMENT_2,Input syndrome polynomial bits 64 to 95." hexmask.long 0x8 0.--31. 1. "SYNDROME_2,Syndrome bits 64 to 95" line.long 0xC "MEM_ELM_SYNDROME_FRAGMENT_3,Input syndrome polynomial bits 96 to 127" hexmask.long 0xC 0.--31. 1. "SYNDROME_3,Syndrome bits 96 to 127" line.long 0x10 "MEM_ELM_SYNDROME_FRAGMENT_4,Input syndrome polynomial bits 128 to 159." hexmask.long 0x10 0.--31. 1. "SYNDROME_4,Syndrome bits 128 to 159" line.long 0x14 "MEM_ELM_SYNDROME_FRAGMENT_5,Input syndrome polynomial bits 160 to 191." hexmask.long 0x14 0.--31. 1. "SYNDROME_5,Syndrome bits 160 to 191" line.long 0x18 "MEM_ELM_SYNDROME_FRAGMENT_6,Input syndrome polynomial bits 192 to 207." bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit 0x0: this syndrome polynomial should not be processed 0x1: this syndrome polynomial must be processed" "0: this syndrome polynomial should not be processed,1: this syndrome polynomial must be processed" hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" rgroup.long 0x800++0x3 line.long 0x0 "MEM_ELM_LOCATION_STATUS,Exit status for the syndrome polynomial processing" bitfld.long 0x0 8. "ECC_CORRECTABLE,Error location process exit status 0x0: ECC error location process failed Number of errors and error locations are invalid 0x1: all errors were successfully located Number of errors and error locations are valid" "0: ECC error location process failed Number of..,1: all errors were successfully located Number of.." hexmask.long.byte 0x0 0.--4. 1. "ECC_NB_ERRORS,Number of errors detected and located" rgroup.long 0x880++0x3F line.long 0x0 "MEM_ELM_ERROR_LOCATION_0,Error location register" hexmask.long.word 0x0 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x4 "MEM_ELM_ERROR_LOCATION_1,Error location register" hexmask.long.word 0x4 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x8 "MEM_ELM_ERROR_LOCATION_2,Error location register" hexmask.long.word 0x8 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0xC "MEM_ELM_ERROR_LOCATION_3,Error location register" hexmask.long.word 0xC 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x10 "MEM_ELM_ERROR_LOCATION_4,Error location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x14 "MEM_ELM_ERROR_LOCATION_5,Error location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x18 "MEM_ELM_ERROR_LOCATION_6,Error location register" hexmask.long.word 0x18 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x1C "MEM_ELM_ERROR_LOCATION_7,Error location register" hexmask.long.word 0x1C 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x20 "MEM_ELM_ERROR_LOCATION_8,Error location register" hexmask.long.word 0x20 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x24 "MEM_ELM_ERROR_LOCATION_9,Error location register" hexmask.long.word 0x24 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x28 "MEM_ELM_ERROR_LOCATION_10,Error location register" hexmask.long.word 0x28 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x2C "MEM_ELM_ERROR_LOCATION_11,Error location register" hexmask.long.word 0x2C 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x30 "MEM_ELM_ERROR_LOCATION_12,Error location register" hexmask.long.word 0x30 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x34 "MEM_ELM_ERROR_LOCATION_13,Error location register" hexmask.long.word 0x34 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x38 "MEM_ELM_ERROR_LOCATION_14,Error location register" hexmask.long.word 0x38 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" line.long 0x3C "MEM_ELM_ERROR_LOCATION_15,Error location register" hexmask.long.word 0x3C 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address" tree.end tree "EPWM" base ad:0x0 tree "EPWM0_EPWM" base ad:0x23000000 group.word 0x0++0xB line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3" bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1" bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7" bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1" bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3" bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1" bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1" bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3" line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register" bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1" bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1" rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1" line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register" hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved." hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base counter is not loaded with.." line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register" hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.." line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register" hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0 then the shadow is enabled.." group.word 0xE++0x17 line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register" rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1" rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1" bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1" bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1" bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3" bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3" line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved." hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h" line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register" hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.." line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register" hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.." line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3" bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1" bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3" bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1" bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3" line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3" bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3" line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms the default is EPWMxA In is.." "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3" line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter" line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter" line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register" hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low a one-shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA and.." hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low a cycle-by-cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the.." group.word 0x28++0x3 line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register" bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1" bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1" bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1" bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1" group.word 0x2E++0x7 line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1" bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1" bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1" line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register" bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1" bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1" line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register" bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1" bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7" line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled ETSEL[INT] = 0 or the.." "0,1,2,3" bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3" rgroup.word 0x36++0x5 line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1" line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register" bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1" line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register" bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1" group.word 0x3C++0x1 line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7" bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width" bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R] maintained by IP design owner" bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]" tree.end tree "EPWM1_EPWM" base ad:0x23010000 group.word 0x0++0xB line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3" bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1" bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7" bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1" bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3" bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1" bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1" bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3" line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register" bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1" bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1" rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1" line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register" hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved." hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base counter is not loaded with.." line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register" hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.." line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register" hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0 then the shadow is enabled.." group.word 0xE++0x17 line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register" rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1" rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1" bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1" bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1" bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3" bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3" line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved." hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h" line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register" hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.." line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register" hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.." line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3" bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1" bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3" bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1" bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3" line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3" bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3" line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms the default is EPWMxA In is.." "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3" line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter" line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter" line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register" hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low a one-shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA and.." hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low a cycle-by-cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the.." group.word 0x28++0x3 line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register" bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1" bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1" bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1" bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1" group.word 0x2E++0x7 line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1" bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1" bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1" line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register" bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1" bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1" line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register" bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1" bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7" line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled ETSEL[INT] = 0 or the.." "0,1,2,3" bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3" rgroup.word 0x36++0x5 line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1" line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register" bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1" line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register" bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1" group.word 0x3C++0x1 line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7" bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width" bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R] maintained by IP design owner" bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]" tree.end tree "EPWM2_EPWM" base ad:0x23020000 group.word 0x0++0xB line.word 0x0 "EPWM_REGS_TBCTL,Time-Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events:" "0,1,2,3" bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value.." "0,1" bitfld.word 0x0 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7" bitfld.word 0x0 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1" bitfld.word 0x0 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3" bitfld.word 0x0 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1" bitfld.word 0x0 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1" bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3" line.word 0x2 "EPWM_REGS_TBSTS,Time-Base Status Register" bitfld.word 0x2 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1" bitfld.word 0x2 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1" rbitfld.word 0x2 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1" line.word 0x4 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register" hexmask.word.byte 0x4 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" line.word 0x6 "EPWM_REGS_TBPHS,Time Base Phase Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension. otherwise. this location is reserved." hexmask.word 0x6 0.--15. 1. "TBPHS,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal [a] If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base counter is not loaded with.." line.word 0x8 "EPWM_REGS_TBCNT,Time Base Counter Register" hexmask.word 0x8 0.--15. 1. "TBCNT,Reading these bits gives the current time-base counter value Writing to these bits sets the current time-base counter value The update happens as soon as the write occurs The write is NOT synchronized to the time-base clock [TBCLK] and the register.." line.word 0xA "EPWM_REGS_TBPRD,Time Base Period Register" hexmask.word 0xA 0.--15. 1. "TBPRD,These bits determine the period of the time-base counter This sets the PWM frequency Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit By default this register is shadowed [a] If TBCTL[PRDLD] = 0 then the shadow is enabled.." group.word 0xE++0x17 line.word 0x0 "EPWM_REGS_CMPCTL,Counter Compare Control Register" rbitfld.word 0x0 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1" rbitfld.word 0x0 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears.." "0,1" bitfld.word 0x0 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1" bitfld.word 0x0 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1" bitfld.word 0x0 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3" bitfld.word 0x0 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3" line.word 0x2 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register. This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise. this location is reserved." hexmask.word.byte 0x2 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h" line.word 0x4 "EPWM_REGS_CMPA,Counter Compare A Register" hexmask.word 0x4 0.--15. 1. "CMPA,The value in the active CMPA register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event This event is sent to the.." line.word 0x6 "EPWM_REGS_CMPB,Counter Compare B Register" hexmask.word 0x6 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event This event is sent to the.." line.word 0x8 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x8 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0x8 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0x8 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0x8 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xA "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0xA 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3" bitfld.word 0xA 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3" bitfld.word 0xA 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3" bitfld.word 0xA 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3" line.word 0xC "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0xC 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3" bitfld.word 0xC 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1" bitfld.word 0xC 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3" bitfld.word 0xC 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1" bitfld.word 0xC 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3" line.word 0xE "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0xE 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3" bitfld.word 0xE 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3" line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms the default is EPWMxA In is.." "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3" line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register" hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter" line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter" line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register" hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low a one-shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA and.." hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low a cycle-by-cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the.." group.word 0x28++0x3 line.word 0x0 "EPWM_REGS_TZCTL,Trip Zone Control Register" bitfld.word 0x0 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" bitfld.word 0x0 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3" line.word 0x2 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x2 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1" bitfld.word 0x2 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1" rgroup.word 0x2C++0x1 line.word 0x0 "EPWM_REGS_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1" bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1" bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag" "0,1" group.word 0x2E++0x7 line.word 0x0 "EPWM_REGS_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1" bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1" bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag" "0,1" line.word 0x2 "EPWM_REGS_TZFRC,Trip Zone Force Register" bitfld.word 0x2 2. "OST,Force a One-Shot Trip Event via Software" "0,1" bitfld.word 0x2 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1" line.word 0x4 "EPWM_REGS_ETSEL,Event Trigger Selection Register" bitfld.word 0x4 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1" bitfld.word 0x4 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7" line.word 0x6 "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x6 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled ETSEL[INT] = 0 or the.." "0,1,2,3" bitfld.word 0x6 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3" rgroup.word 0x36++0x5 line.word 0x0 "EPWM_REGS_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1" line.word 0x2 "EPWM_REGS_ETCLR,Event Trigger Clear Register" bitfld.word 0x2 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1" line.word 0x4 "EPWM_REGS_ETFRC,Event Trigger Force Register" bitfld.word 0x4 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1" group.word 0x3C++0x1 line.word 0x0 "EPWM_REGS_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7" bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width" bitfld.word 0x0 0. "CHPEN,PWM-chopping Enable" "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "EPWM_REGS_PID,EHRPWM Peripheral ID Register. The IP revision register is used by software to track features. bugs. and compatibility." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,FUNC" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version [R] maintained by IP design owner" bitfld.long 0x0 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,CUSTOM" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision [Y]" tree.end tree.end tree "EQEP" base ad:0x0 tree "EQEP0_REG" base ad:0x23200000 group.long 0x0++0xF line.long 0x0 "REG_QPOSCNT,Position Counter" hexmask.long 0x0 0.--31. 1. "QPOSCNT,Position Counter This 32-bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point. This.." line.long 0x4 "REG_QPOSINIT,Position Counter Init" hexmask.long 0x4 0.--31. 1. "QPOSINIT,Position Counter InitThis register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software. Writes to this register should.." line.long 0x8 "REG_QPOSMAX,Maximum Position Count" hexmask.long 0x8 0.--31. 1. "QPOSMAX,Maximum Position CountThis register contains the maximum position counter value. Writes to this register should always be full 32-bit writes." line.long 0xC "REG_QPOSCMP,Position Compare" hexmask.long 0xC 0.--31. 1. "QPOSCMP,Position Compare The position-compare value in this register is compared with the position counter [QPOSCNT] to generate sync output and/or interrupt on compare match." rgroup.long 0x10++0xB line.long 0x0 "REG_QPOSILAT,Index Position Latch" hexmask.long 0x0 0.--31. 1. "QPOSILAT,Index Position Latch The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits." line.long 0x4 "REG_QPOSSLAT,Strobe Position Latch" hexmask.long 0x4 0.--31. 1. "QPOSSLAT,Strobe Position Latch The position-counter value is latched into this register on a strobe event as defined by the QEPCTL[SEL] bits." line.long 0x8 "REG_QPOSLAT,Position Latch" hexmask.long 0x8 0.--31. 1. "QPOSLAT,Position Latch The position-counter value is latched into this register on a unit time out event." group.long 0x1C++0x7 line.long 0x0 "REG_QUTMR,QEP Unit Timer" hexmask.long 0x0 0.--31. 1. "QUTMR,QEP Unit TimerThis register acts as time base for unit time event generation. When this timer value matches the unit time period value a unit time event is generated." line.long 0x4 "REG_QUPRD,QEP Unit Period" hexmask.long 0x4 0.--31. 1. "QUPRD,QEP Unit PeriodThis register contains the period count for the unit timer to generate periodic unit time events. These events latch the eQEP position information at periodic intervals and optionally generate an interrupt. Writes to this register.." group.word 0x24++0xD line.word 0x0 "REG_QWDTMR,QEP Watchdog Timer" hexmask.word 0x0 0.--15. 1. "QWDTMR,QEP Watchdog Timer This register acts as time base for the watchdog to detect motor stalls. When this timer value matches with the watchdog's period value a watchdog timeout interrupt is generated. This register is reset upon edge transition in.." line.word 0x2 "REG_QWDPRD,QEP Watchdog Period" hexmask.word 0x2 0.--15. 1. "QWDPRD,QEP Watchdog Period This register contains the time-out count for the eQEP peripheral watch dog timer.When the watchdog timer value matches the watchdog period value a watchdog timeout interrupt is generated." line.word 0x4 "REG_QDECCTL_TYPE2,Quadrature Decoder Control" bitfld.word 0x4 14.--15. "QSRC,Position-counter source selection" "0,1,2,3" bitfld.word 0x4 13. "SOEN,Sync output-enable" "0,1" bitfld.word 0x4 12. "SPSEL,Sync output pin selection" "0,1" bitfld.word 0x4 11. "XCR,External Clock Rate" "0,1" bitfld.word 0x4 10. "SWAP,CLK/DIR Signal Source for Position Counter" "0,1" newline bitfld.word 0x4 9. "IGATE,Index pulse gating option" "0,1" bitfld.word 0x4 8. "QAP,QEPA input polarity" "0,1" bitfld.word 0x4 7. "QBP,QEPB input polarity" "0,1" bitfld.word 0x4 6. "QIP,QEPI input polarity" "0,1" bitfld.word 0x4 5. "QSP,QEPS input polarity" "0,1" newline bitfld.word 0x4 0. "QIDIRE,0 - Compatible mode Behavior same as existing devices1 - Enhancement for Direction change during Index will be enabled" "0,1" line.word 0x6 "REG_QEPCTL,QEP Control" bitfld.word 0x6 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3" bitfld.word 0x6 12.--13. "PCRM,Postion counter reset" "0,1,2,3" bitfld.word 0x6 10.--11. "SEI,Strobe event initialization of position counter" "0,1,2,3" bitfld.word 0x6 8.--9. "IEI,Index event init of position count" "0,1,2,3" bitfld.word 0x6 7. "SWI,Software init position counter" "0,1" newline bitfld.word 0x6 6. "SEL,Strobe event latch of position counter" "0,1" bitfld.word 0x6 4.--5. "IEL,Index event latch of position counter [software index marker]" "0,1,2,3" bitfld.word 0x6 3. "QPEN,Quadrature position counter enable/software reset" "0,1" bitfld.word 0x6 2. "QCLM,QEP capture latch mode" "0,1" bitfld.word 0x6 1. "UTE,QEP unit timer enable" "0,1" newline bitfld.word 0x6 0. "WDE,QEP watchdog enable" "0,1" line.word 0x8 "REG_QCAPCTL,Qaudrature Capture Control" bitfld.word 0x8 15. "CEN,Enable eQEP capture" "0,1" bitfld.word 0x8 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x8 0.--3. 1. "UPPS,Unit position event prescaler" line.word 0xA "REG_QPOSCTL,Position Compare Control" bitfld.word 0xA 15. "PCSHDW,Position compare of shadow enable" "0,1" bitfld.word 0xA 14. "PCLOAD,Position compare of shadow load" "0,1" bitfld.word 0xA 13. "PCPOL,Polarity of sync output" "0,1" bitfld.word 0xA 12. "PCE,Position compare enable/disable" "0,1" hexmask.word 0xA 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width" line.word 0xC "REG_QEINT_TYPE1,QEP Interrupt Control" bitfld.word 0xC 12. "QMAE,QMA Error Interrupt enable" "0,1" bitfld.word 0xC 11. "UTO,Unit time out interrupt enable" "0,1" bitfld.word 0xC 10. "IEL,Index event latch interrupt enable" "0,1" bitfld.word 0xC 9. "SEL,Strobe event latch interrupt enable" "0,1" bitfld.word 0xC 8. "PCM,Position-compare match interrupt enable" "0,1" newline bitfld.word 0xC 7. "PCR,Position-compare ready interrupt enable" "0,1" bitfld.word 0xC 6. "PCO,Position counter overflow interrupt enable" "0,1" bitfld.word 0xC 5. "PCU,Position counter underflow interrupt enable" "0,1" bitfld.word 0xC 4. "WTO,Watchdog time out interrupt enable" "0,1" bitfld.word 0xC 3. "QDC,Quadrature direction change interrupt enable" "0,1" newline bitfld.word 0xC 2. "QPE,Quadrature phase error interrupt enable" "0,1" bitfld.word 0xC 1. "PCE,Position counter error interrupt enable" "0,1" rgroup.word 0x32++0x1 line.word 0x0 "REG_QFLG_TYPE1,QEP Interrupt Flag" bitfld.word 0x0 12. "QMAE,QMA Error interrupt flag" "0,1" bitfld.word 0x0 11. "UTO,Unit time out interrupt flag" "0,1" bitfld.word 0x0 10. "IEL,Index event latch interrupt flag" "0,1" bitfld.word 0x0 9. "SEL,Strobe event latch interrupt flag" "0,1" bitfld.word 0x0 8. "PCM,eQEP compare match event interrupt flag" "0,1" newline bitfld.word 0x0 7. "PCR,Position-compare ready interrupt flag" "0,1" bitfld.word 0x0 6. "PCO,Position counter overflow interrupt flag" "0,1" bitfld.word 0x0 5. "PCU,Position counter underflow interrupt flag" "0,1" bitfld.word 0x0 4. "WTO,Watchdog timeout interrupt flag" "0,1" bitfld.word 0x0 3. "QDC,Quadrature direction change interrupt flag" "0,1" newline bitfld.word 0x0 2. "PHE,Quadrature phase error interrupt flag" "0,1" bitfld.word 0x0 1. "PCE,Position counter error interrupt flag" "0,1" bitfld.word 0x0 0. "INT,Global interrupt status flag" "0,1" group.word 0x34++0x9 line.word 0x0 "REG_QCLR_TYPE1,QEP Interrupt Clear" bitfld.word 0x0 12. "QMAE,Clear QMA Error interrupt flag" "0,1" bitfld.word 0x0 11. "UTO,Clear unit time out interrupt flag" "0,1" bitfld.word 0x0 10. "IEL,Clear index event latch interrupt flag" "0,1" bitfld.word 0x0 9. "SEL,Clear strobe event latch interrupt flag" "0,1" bitfld.word 0x0 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1" newline bitfld.word 0x0 7. "PCR,Clear position-compare ready interrupt flag" "0,1" bitfld.word 0x0 6. "PCO,Clear position counter overflow interrupt flag" "0,1" bitfld.word 0x0 5. "PCU,Clear position counter underflow interrupt flag" "0,1" bitfld.word 0x0 4. "WTO,Clear watchdog timeout interrupt flag" "0,1" bitfld.word 0x0 3. "QDC,Clear quadrature direction change interrupt flag" "0,1" newline bitfld.word 0x0 2. "PHE,Clear quadrature phase error interrupt flag" "0,1" bitfld.word 0x0 1. "PCE,Clear position counter error interrupt flag" "0,1" bitfld.word 0x0 0. "INT,Global interrupt clear flag" "0,1" line.word 0x2 "REG_QFRC_TYPE1,QEP Interrupt Force" bitfld.word 0x2 12. "QMAE,Force QMA error interrupt" "0,1" bitfld.word 0x2 11. "UTO,Force unit time out interrupt" "0,1" bitfld.word 0x2 10. "IEL,Force index event latch interrupt" "0,1" bitfld.word 0x2 9. "SEL,Force strobe event latch interrupt" "0,1" bitfld.word 0x2 8. "PCM,Force position-compare match interrupt" "0,1" newline bitfld.word 0x2 7. "PCR,Force position-compare ready interrupt" "0,1" bitfld.word 0x2 6. "PCO,Force position counter overflow interrupt" "0,1" bitfld.word 0x2 5. "PCU,Force position counter underflow interrupt" "0,1" bitfld.word 0x2 4. "WTO,Force watchdog time out interrupt" "0,1" bitfld.word 0x2 3. "QDC,Force quadrature direction change interrupt" "0,1" newline bitfld.word 0x2 2. "PHE,Force quadrature phase error interrupt" "0,1" bitfld.word 0x2 1. "PCE,Force position counter error interrupt" "0,1" line.word 0x4 "REG_QEPSTS_TYPE1,QEP Status" bitfld.word 0x4 7. "UPEVNT,Unit position event flag" "0,1" rbitfld.word 0x4 6. "FIDF,Direction on the first index markerStatus of the direction is latched on the first index event marker." "0,1" rbitfld.word 0x4 5. "QDF,Quadrature direction flag" "0,1" rbitfld.word 0x4 4. "QDLF,eQEP direction latch flag" "0,1" bitfld.word 0x4 3. "COEF,Capture overflow error flag" "0,1" newline bitfld.word 0x4 2. "CDEF,Capture direction error flag" "0,1" bitfld.word 0x4 1. "FIMF,First index marker flag" "0,1" rbitfld.word 0x4 0. "PCEF,Position counter error flag. This bit is not sticky and it is updated for every index event." "0,1" line.word 0x6 "REG_QCTMR,QEP Capture Timer" hexmask.word 0x6 0.--15. 1. "QCTMR,This register provides time base for edge capture unit." line.word 0x8 "REG_QCPRD,QEP Capture Period" hexmask.word 0x8 0.--15. 1. "QCPRD,This register holds the period count value between the last successive eQEP position events" rgroup.word 0x3E++0x3 line.word 0x0 "REG_QCTMRLAT,QEP Capture Latch" hexmask.word 0x0 0.--15. 1. "QCTMRLAT,The eQEP capture timer value can be latched into this register on two events viz. unit timeout event reading the eQEP position counter." line.word 0x2 "REG_QCPRDLAT,QEP Capture Period Latch" hexmask.word 0x2 0.--15. 1. "QCPRDLAT,eQEP capture period value can be latched into this register on two events viz. unit timeout event reading the eQEP position counter." group.word 0x42++0x1 line.word 0x0 "REG_Reserved_1" rgroup.long 0x60++0x3 line.long 0x0 "REG_REV_TYPE2,QEP Revision Number" bitfld.long 0x0 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" group.long 0x64++0xB line.long 0x0 "REG_QEPSTROBESEL,QEP Strobe select register" bitfld.long 0x0 0.--1. "STROBESEL,Strobe source select:" "0,1,2,3" line.long 0x4 "REG_QMACTRL,QMA Control register" bitfld.long 0x4 0.--2. "MODE,Select Mode for QMA mode:000 : QMA Module is bypassed. 001 : QMA Mode-1 operation selected010 : QMA Mode-2 operation selected011 : QMA Module is bypassed [reserved]1xx : QMA Module is bypassed [reserved]" "0: QMA Module is bypassed,1: QMA Mode-1 operation selected010 : QMA Mode-2..,?,?,?,?,?,?" line.long 0x8 "REG_QEPSRCSEL,QEP Source Select Register" hexmask.long.byte 0x8 12.--15. 1. "QEPSSEL,QEP Strobe source select:0000: From device Pins [Default].0001-1111: Device dependent." hexmask.long.byte 0x8 8.--11. 1. "QEPISEL,QEP Index source select:0000: From device Pins [Default].0001-1111: Device dependent." hexmask.long.byte 0x8 4.--7. 1. "QEPBSEL,QEPB source select:0000: From device Pins [Default].0001-1111: Device dependent." hexmask.long.byte 0x8 0.--3. 1. "QEPASEL,QEPA source select:0000: From device Pins [Default].0001-1111: Device dependent." group.word 0x70++0x1 line.word 0x0 "REG_Reserved_2" tree.end tree "EQEP1_REG" base ad:0x23210000 group.long 0x0++0xF line.long 0x0 "REG_QPOSCNT,Position Counter" hexmask.long 0x0 0.--31. 1. "QPOSCNT,Position Counter This 32-bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point. This.." line.long 0x4 "REG_QPOSINIT,Position Counter Init" hexmask.long 0x4 0.--31. 1. "QPOSINIT,Position Counter InitThis register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software. Writes to this register should.." line.long 0x8 "REG_QPOSMAX,Maximum Position Count" hexmask.long 0x8 0.--31. 1. "QPOSMAX,Maximum Position CountThis register contains the maximum position counter value. Writes to this register should always be full 32-bit writes." line.long 0xC "REG_QPOSCMP,Position Compare" hexmask.long 0xC 0.--31. 1. "QPOSCMP,Position Compare The position-compare value in this register is compared with the position counter [QPOSCNT] to generate sync output and/or interrupt on compare match." rgroup.long 0x10++0xB line.long 0x0 "REG_QPOSILAT,Index Position Latch" hexmask.long 0x0 0.--31. 1. "QPOSILAT,Index Position Latch The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits." line.long 0x4 "REG_QPOSSLAT,Strobe Position Latch" hexmask.long 0x4 0.--31. 1. "QPOSSLAT,Strobe Position Latch The position-counter value is latched into this register on a strobe event as defined by the QEPCTL[SEL] bits." line.long 0x8 "REG_QPOSLAT,Position Latch" hexmask.long 0x8 0.--31. 1. "QPOSLAT,Position Latch The position-counter value is latched into this register on a unit time out event." group.long 0x1C++0x7 line.long 0x0 "REG_QUTMR,QEP Unit Timer" hexmask.long 0x0 0.--31. 1. "QUTMR,QEP Unit TimerThis register acts as time base for unit time event generation. When this timer value matches the unit time period value a unit time event is generated." line.long 0x4 "REG_QUPRD,QEP Unit Period" hexmask.long 0x4 0.--31. 1. "QUPRD,QEP Unit PeriodThis register contains the period count for the unit timer to generate periodic unit time events. These events latch the eQEP position information at periodic intervals and optionally generate an interrupt. Writes to this register.." group.word 0x24++0xD line.word 0x0 "REG_QWDTMR,QEP Watchdog Timer" hexmask.word 0x0 0.--15. 1. "QWDTMR,QEP Watchdog Timer This register acts as time base for the watchdog to detect motor stalls. When this timer value matches with the watchdog's period value a watchdog timeout interrupt is generated. This register is reset upon edge transition in.." line.word 0x2 "REG_QWDPRD,QEP Watchdog Period" hexmask.word 0x2 0.--15. 1. "QWDPRD,QEP Watchdog Period This register contains the time-out count for the eQEP peripheral watch dog timer.When the watchdog timer value matches the watchdog period value a watchdog timeout interrupt is generated." line.word 0x4 "REG_QDECCTL_TYPE2,Quadrature Decoder Control" bitfld.word 0x4 14.--15. "QSRC,Position-counter source selection" "0,1,2,3" bitfld.word 0x4 13. "SOEN,Sync output-enable" "0,1" bitfld.word 0x4 12. "SPSEL,Sync output pin selection" "0,1" bitfld.word 0x4 11. "XCR,External Clock Rate" "0,1" bitfld.word 0x4 10. "SWAP,CLK/DIR Signal Source for Position Counter" "0,1" newline bitfld.word 0x4 9. "IGATE,Index pulse gating option" "0,1" bitfld.word 0x4 8. "QAP,QEPA input polarity" "0,1" bitfld.word 0x4 7. "QBP,QEPB input polarity" "0,1" bitfld.word 0x4 6. "QIP,QEPI input polarity" "0,1" bitfld.word 0x4 5. "QSP,QEPS input polarity" "0,1" newline bitfld.word 0x4 0. "QIDIRE,0 - Compatible mode Behavior same as existing devices1 - Enhancement for Direction change during Index will be enabled" "0,1" line.word 0x6 "REG_QEPCTL,QEP Control" bitfld.word 0x6 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3" bitfld.word 0x6 12.--13. "PCRM,Postion counter reset" "0,1,2,3" bitfld.word 0x6 10.--11. "SEI,Strobe event initialization of position counter" "0,1,2,3" bitfld.word 0x6 8.--9. "IEI,Index event init of position count" "0,1,2,3" bitfld.word 0x6 7. "SWI,Software init position counter" "0,1" newline bitfld.word 0x6 6. "SEL,Strobe event latch of position counter" "0,1" bitfld.word 0x6 4.--5. "IEL,Index event latch of position counter [software index marker]" "0,1,2,3" bitfld.word 0x6 3. "QPEN,Quadrature position counter enable/software reset" "0,1" bitfld.word 0x6 2. "QCLM,QEP capture latch mode" "0,1" bitfld.word 0x6 1. "UTE,QEP unit timer enable" "0,1" newline bitfld.word 0x6 0. "WDE,QEP watchdog enable" "0,1" line.word 0x8 "REG_QCAPCTL,Qaudrature Capture Control" bitfld.word 0x8 15. "CEN,Enable eQEP capture" "0,1" bitfld.word 0x8 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x8 0.--3. 1. "UPPS,Unit position event prescaler" line.word 0xA "REG_QPOSCTL,Position Compare Control" bitfld.word 0xA 15. "PCSHDW,Position compare of shadow enable" "0,1" bitfld.word 0xA 14. "PCLOAD,Position compare of shadow load" "0,1" bitfld.word 0xA 13. "PCPOL,Polarity of sync output" "0,1" bitfld.word 0xA 12. "PCE,Position compare enable/disable" "0,1" hexmask.word 0xA 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width" line.word 0xC "REG_QEINT_TYPE1,QEP Interrupt Control" bitfld.word 0xC 12. "QMAE,QMA Error Interrupt enable" "0,1" bitfld.word 0xC 11. "UTO,Unit time out interrupt enable" "0,1" bitfld.word 0xC 10. "IEL,Index event latch interrupt enable" "0,1" bitfld.word 0xC 9. "SEL,Strobe event latch interrupt enable" "0,1" bitfld.word 0xC 8. "PCM,Position-compare match interrupt enable" "0,1" newline bitfld.word 0xC 7. "PCR,Position-compare ready interrupt enable" "0,1" bitfld.word 0xC 6. "PCO,Position counter overflow interrupt enable" "0,1" bitfld.word 0xC 5. "PCU,Position counter underflow interrupt enable" "0,1" bitfld.word 0xC 4. "WTO,Watchdog time out interrupt enable" "0,1" bitfld.word 0xC 3. "QDC,Quadrature direction change interrupt enable" "0,1" newline bitfld.word 0xC 2. "QPE,Quadrature phase error interrupt enable" "0,1" bitfld.word 0xC 1. "PCE,Position counter error interrupt enable" "0,1" rgroup.word 0x32++0x1 line.word 0x0 "REG_QFLG_TYPE1,QEP Interrupt Flag" bitfld.word 0x0 12. "QMAE,QMA Error interrupt flag" "0,1" bitfld.word 0x0 11. "UTO,Unit time out interrupt flag" "0,1" bitfld.word 0x0 10. "IEL,Index event latch interrupt flag" "0,1" bitfld.word 0x0 9. "SEL,Strobe event latch interrupt flag" "0,1" bitfld.word 0x0 8. "PCM,eQEP compare match event interrupt flag" "0,1" newline bitfld.word 0x0 7. "PCR,Position-compare ready interrupt flag" "0,1" bitfld.word 0x0 6. "PCO,Position counter overflow interrupt flag" "0,1" bitfld.word 0x0 5. "PCU,Position counter underflow interrupt flag" "0,1" bitfld.word 0x0 4. "WTO,Watchdog timeout interrupt flag" "0,1" bitfld.word 0x0 3. "QDC,Quadrature direction change interrupt flag" "0,1" newline bitfld.word 0x0 2. "PHE,Quadrature phase error interrupt flag" "0,1" bitfld.word 0x0 1. "PCE,Position counter error interrupt flag" "0,1" bitfld.word 0x0 0. "INT,Global interrupt status flag" "0,1" group.word 0x34++0x9 line.word 0x0 "REG_QCLR_TYPE1,QEP Interrupt Clear" bitfld.word 0x0 12. "QMAE,Clear QMA Error interrupt flag" "0,1" bitfld.word 0x0 11. "UTO,Clear unit time out interrupt flag" "0,1" bitfld.word 0x0 10. "IEL,Clear index event latch interrupt flag" "0,1" bitfld.word 0x0 9. "SEL,Clear strobe event latch interrupt flag" "0,1" bitfld.word 0x0 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1" newline bitfld.word 0x0 7. "PCR,Clear position-compare ready interrupt flag" "0,1" bitfld.word 0x0 6. "PCO,Clear position counter overflow interrupt flag" "0,1" bitfld.word 0x0 5. "PCU,Clear position counter underflow interrupt flag" "0,1" bitfld.word 0x0 4. "WTO,Clear watchdog timeout interrupt flag" "0,1" bitfld.word 0x0 3. "QDC,Clear quadrature direction change interrupt flag" "0,1" newline bitfld.word 0x0 2. "PHE,Clear quadrature phase error interrupt flag" "0,1" bitfld.word 0x0 1. "PCE,Clear position counter error interrupt flag" "0,1" bitfld.word 0x0 0. "INT,Global interrupt clear flag" "0,1" line.word 0x2 "REG_QFRC_TYPE1,QEP Interrupt Force" bitfld.word 0x2 12. "QMAE,Force QMA error interrupt" "0,1" bitfld.word 0x2 11. "UTO,Force unit time out interrupt" "0,1" bitfld.word 0x2 10. "IEL,Force index event latch interrupt" "0,1" bitfld.word 0x2 9. "SEL,Force strobe event latch interrupt" "0,1" bitfld.word 0x2 8. "PCM,Force position-compare match interrupt" "0,1" newline bitfld.word 0x2 7. "PCR,Force position-compare ready interrupt" "0,1" bitfld.word 0x2 6. "PCO,Force position counter overflow interrupt" "0,1" bitfld.word 0x2 5. "PCU,Force position counter underflow interrupt" "0,1" bitfld.word 0x2 4. "WTO,Force watchdog time out interrupt" "0,1" bitfld.word 0x2 3. "QDC,Force quadrature direction change interrupt" "0,1" newline bitfld.word 0x2 2. "PHE,Force quadrature phase error interrupt" "0,1" bitfld.word 0x2 1. "PCE,Force position counter error interrupt" "0,1" line.word 0x4 "REG_QEPSTS_TYPE1,QEP Status" bitfld.word 0x4 7. "UPEVNT,Unit position event flag" "0,1" rbitfld.word 0x4 6. "FIDF,Direction on the first index markerStatus of the direction is latched on the first index event marker." "0,1" rbitfld.word 0x4 5. "QDF,Quadrature direction flag" "0,1" rbitfld.word 0x4 4. "QDLF,eQEP direction latch flag" "0,1" bitfld.word 0x4 3. "COEF,Capture overflow error flag" "0,1" newline bitfld.word 0x4 2. "CDEF,Capture direction error flag" "0,1" bitfld.word 0x4 1. "FIMF,First index marker flag" "0,1" rbitfld.word 0x4 0. "PCEF,Position counter error flag. This bit is not sticky and it is updated for every index event." "0,1" line.word 0x6 "REG_QCTMR,QEP Capture Timer" hexmask.word 0x6 0.--15. 1. "QCTMR,This register provides time base for edge capture unit." line.word 0x8 "REG_QCPRD,QEP Capture Period" hexmask.word 0x8 0.--15. 1. "QCPRD,This register holds the period count value between the last successive eQEP position events" rgroup.word 0x3E++0x3 line.word 0x0 "REG_QCTMRLAT,QEP Capture Latch" hexmask.word 0x0 0.--15. 1. "QCTMRLAT,The eQEP capture timer value can be latched into this register on two events viz. unit timeout event reading the eQEP position counter." line.word 0x2 "REG_QCPRDLAT,QEP Capture Period Latch" hexmask.word 0x2 0.--15. 1. "QCPRDLAT,eQEP capture period value can be latched into this register on two events viz. unit timeout event reading the eQEP position counter." group.word 0x42++0x1 line.word 0x0 "REG_Reserved_1" rgroup.long 0x60++0x3 line.long 0x0 "REG_REV_TYPE2,QEP Revision Number" bitfld.long 0x0 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" group.long 0x64++0xB line.long 0x0 "REG_QEPSTROBESEL,QEP Strobe select register" bitfld.long 0x0 0.--1. "STROBESEL,Strobe source select:" "0,1,2,3" line.long 0x4 "REG_QMACTRL,QMA Control register" bitfld.long 0x4 0.--2. "MODE,Select Mode for QMA mode:000 : QMA Module is bypassed. 001 : QMA Mode-1 operation selected010 : QMA Mode-2 operation selected011 : QMA Module is bypassed [reserved]1xx : QMA Module is bypassed [reserved]" "0: QMA Module is bypassed,1: QMA Mode-1 operation selected010 : QMA Mode-2..,?,?,?,?,?,?" line.long 0x8 "REG_QEPSRCSEL,QEP Source Select Register" hexmask.long.byte 0x8 12.--15. 1. "QEPSSEL,QEP Strobe source select:0000: From device Pins [Default].0001-1111: Device dependent." hexmask.long.byte 0x8 8.--11. 1. "QEPISEL,QEP Index source select:0000: From device Pins [Default].0001-1111: Device dependent." hexmask.long.byte 0x8 4.--7. 1. "QEPBSEL,QEPB source select:0000: From device Pins [Default].0001-1111: Device dependent." hexmask.long.byte 0x8 0.--3. 1. "QEPASEL,QEPA source select:0000: From device Pins [Default].0001-1111: Device dependent." group.word 0x70++0x1 line.word 0x0 "REG_Reserved_2" tree.end tree "EQEP2_REG" base ad:0x23220000 group.long 0x0++0xF line.long 0x0 "REG_QPOSCNT,Position Counter" hexmask.long 0x0 0.--31. 1. "QPOSCNT,Position Counter This 32-bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point. This.." line.long 0x4 "REG_QPOSINIT,Position Counter Init" hexmask.long 0x4 0.--31. 1. "QPOSINIT,Position Counter InitThis register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software. Writes to this register should.." line.long 0x8 "REG_QPOSMAX,Maximum Position Count" hexmask.long 0x8 0.--31. 1. "QPOSMAX,Maximum Position CountThis register contains the maximum position counter value. Writes to this register should always be full 32-bit writes." line.long 0xC "REG_QPOSCMP,Position Compare" hexmask.long 0xC 0.--31. 1. "QPOSCMP,Position Compare The position-compare value in this register is compared with the position counter [QPOSCNT] to generate sync output and/or interrupt on compare match." rgroup.long 0x10++0xB line.long 0x0 "REG_QPOSILAT,Index Position Latch" hexmask.long 0x0 0.--31. 1. "QPOSILAT,Index Position Latch The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits." line.long 0x4 "REG_QPOSSLAT,Strobe Position Latch" hexmask.long 0x4 0.--31. 1. "QPOSSLAT,Strobe Position Latch The position-counter value is latched into this register on a strobe event as defined by the QEPCTL[SEL] bits." line.long 0x8 "REG_QPOSLAT,Position Latch" hexmask.long 0x8 0.--31. 1. "QPOSLAT,Position Latch The position-counter value is latched into this register on a unit time out event." group.long 0x1C++0x7 line.long 0x0 "REG_QUTMR,QEP Unit Timer" hexmask.long 0x0 0.--31. 1. "QUTMR,QEP Unit TimerThis register acts as time base for unit time event generation. When this timer value matches the unit time period value a unit time event is generated." line.long 0x4 "REG_QUPRD,QEP Unit Period" hexmask.long 0x4 0.--31. 1. "QUPRD,QEP Unit PeriodThis register contains the period count for the unit timer to generate periodic unit time events. These events latch the eQEP position information at periodic intervals and optionally generate an interrupt. Writes to this register.." group.word 0x24++0xD line.word 0x0 "REG_QWDTMR,QEP Watchdog Timer" hexmask.word 0x0 0.--15. 1. "QWDTMR,QEP Watchdog Timer This register acts as time base for the watchdog to detect motor stalls. When this timer value matches with the watchdog's period value a watchdog timeout interrupt is generated. This register is reset upon edge transition in.." line.word 0x2 "REG_QWDPRD,QEP Watchdog Period" hexmask.word 0x2 0.--15. 1. "QWDPRD,QEP Watchdog Period This register contains the time-out count for the eQEP peripheral watch dog timer.When the watchdog timer value matches the watchdog period value a watchdog timeout interrupt is generated." line.word 0x4 "REG_QDECCTL_TYPE2,Quadrature Decoder Control" bitfld.word 0x4 14.--15. "QSRC,Position-counter source selection" "0,1,2,3" bitfld.word 0x4 13. "SOEN,Sync output-enable" "0,1" bitfld.word 0x4 12. "SPSEL,Sync output pin selection" "0,1" bitfld.word 0x4 11. "XCR,External Clock Rate" "0,1" bitfld.word 0x4 10. "SWAP,CLK/DIR Signal Source for Position Counter" "0,1" newline bitfld.word 0x4 9. "IGATE,Index pulse gating option" "0,1" bitfld.word 0x4 8. "QAP,QEPA input polarity" "0,1" bitfld.word 0x4 7. "QBP,QEPB input polarity" "0,1" bitfld.word 0x4 6. "QIP,QEPI input polarity" "0,1" bitfld.word 0x4 5. "QSP,QEPS input polarity" "0,1" newline bitfld.word 0x4 0. "QIDIRE,0 - Compatible mode Behavior same as existing devices1 - Enhancement for Direction change during Index will be enabled" "0,1" line.word 0x6 "REG_QEPCTL,QEP Control" bitfld.word 0x6 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3" bitfld.word 0x6 12.--13. "PCRM,Postion counter reset" "0,1,2,3" bitfld.word 0x6 10.--11. "SEI,Strobe event initialization of position counter" "0,1,2,3" bitfld.word 0x6 8.--9. "IEI,Index event init of position count" "0,1,2,3" bitfld.word 0x6 7. "SWI,Software init position counter" "0,1" newline bitfld.word 0x6 6. "SEL,Strobe event latch of position counter" "0,1" bitfld.word 0x6 4.--5. "IEL,Index event latch of position counter [software index marker]" "0,1,2,3" bitfld.word 0x6 3. "QPEN,Quadrature position counter enable/software reset" "0,1" bitfld.word 0x6 2. "QCLM,QEP capture latch mode" "0,1" bitfld.word 0x6 1. "UTE,QEP unit timer enable" "0,1" newline bitfld.word 0x6 0. "WDE,QEP watchdog enable" "0,1" line.word 0x8 "REG_QCAPCTL,Qaudrature Capture Control" bitfld.word 0x8 15. "CEN,Enable eQEP capture" "0,1" bitfld.word 0x8 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x8 0.--3. 1. "UPPS,Unit position event prescaler" line.word 0xA "REG_QPOSCTL,Position Compare Control" bitfld.word 0xA 15. "PCSHDW,Position compare of shadow enable" "0,1" bitfld.word 0xA 14. "PCLOAD,Position compare of shadow load" "0,1" bitfld.word 0xA 13. "PCPOL,Polarity of sync output" "0,1" bitfld.word 0xA 12. "PCE,Position compare enable/disable" "0,1" hexmask.word 0xA 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width" line.word 0xC "REG_QEINT_TYPE1,QEP Interrupt Control" bitfld.word 0xC 12. "QMAE,QMA Error Interrupt enable" "0,1" bitfld.word 0xC 11. "UTO,Unit time out interrupt enable" "0,1" bitfld.word 0xC 10. "IEL,Index event latch interrupt enable" "0,1" bitfld.word 0xC 9. "SEL,Strobe event latch interrupt enable" "0,1" bitfld.word 0xC 8. "PCM,Position-compare match interrupt enable" "0,1" newline bitfld.word 0xC 7. "PCR,Position-compare ready interrupt enable" "0,1" bitfld.word 0xC 6. "PCO,Position counter overflow interrupt enable" "0,1" bitfld.word 0xC 5. "PCU,Position counter underflow interrupt enable" "0,1" bitfld.word 0xC 4. "WTO,Watchdog time out interrupt enable" "0,1" bitfld.word 0xC 3. "QDC,Quadrature direction change interrupt enable" "0,1" newline bitfld.word 0xC 2. "QPE,Quadrature phase error interrupt enable" "0,1" bitfld.word 0xC 1. "PCE,Position counter error interrupt enable" "0,1" rgroup.word 0x32++0x1 line.word 0x0 "REG_QFLG_TYPE1,QEP Interrupt Flag" bitfld.word 0x0 12. "QMAE,QMA Error interrupt flag" "0,1" bitfld.word 0x0 11. "UTO,Unit time out interrupt flag" "0,1" bitfld.word 0x0 10. "IEL,Index event latch interrupt flag" "0,1" bitfld.word 0x0 9. "SEL,Strobe event latch interrupt flag" "0,1" bitfld.word 0x0 8. "PCM,eQEP compare match event interrupt flag" "0,1" newline bitfld.word 0x0 7. "PCR,Position-compare ready interrupt flag" "0,1" bitfld.word 0x0 6. "PCO,Position counter overflow interrupt flag" "0,1" bitfld.word 0x0 5. "PCU,Position counter underflow interrupt flag" "0,1" bitfld.word 0x0 4. "WTO,Watchdog timeout interrupt flag" "0,1" bitfld.word 0x0 3. "QDC,Quadrature direction change interrupt flag" "0,1" newline bitfld.word 0x0 2. "PHE,Quadrature phase error interrupt flag" "0,1" bitfld.word 0x0 1. "PCE,Position counter error interrupt flag" "0,1" bitfld.word 0x0 0. "INT,Global interrupt status flag" "0,1" group.word 0x34++0x9 line.word 0x0 "REG_QCLR_TYPE1,QEP Interrupt Clear" bitfld.word 0x0 12. "QMAE,Clear QMA Error interrupt flag" "0,1" bitfld.word 0x0 11. "UTO,Clear unit time out interrupt flag" "0,1" bitfld.word 0x0 10. "IEL,Clear index event latch interrupt flag" "0,1" bitfld.word 0x0 9. "SEL,Clear strobe event latch interrupt flag" "0,1" bitfld.word 0x0 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1" newline bitfld.word 0x0 7. "PCR,Clear position-compare ready interrupt flag" "0,1" bitfld.word 0x0 6. "PCO,Clear position counter overflow interrupt flag" "0,1" bitfld.word 0x0 5. "PCU,Clear position counter underflow interrupt flag" "0,1" bitfld.word 0x0 4. "WTO,Clear watchdog timeout interrupt flag" "0,1" bitfld.word 0x0 3. "QDC,Clear quadrature direction change interrupt flag" "0,1" newline bitfld.word 0x0 2. "PHE,Clear quadrature phase error interrupt flag" "0,1" bitfld.word 0x0 1. "PCE,Clear position counter error interrupt flag" "0,1" bitfld.word 0x0 0. "INT,Global interrupt clear flag" "0,1" line.word 0x2 "REG_QFRC_TYPE1,QEP Interrupt Force" bitfld.word 0x2 12. "QMAE,Force QMA error interrupt" "0,1" bitfld.word 0x2 11. "UTO,Force unit time out interrupt" "0,1" bitfld.word 0x2 10. "IEL,Force index event latch interrupt" "0,1" bitfld.word 0x2 9. "SEL,Force strobe event latch interrupt" "0,1" bitfld.word 0x2 8. "PCM,Force position-compare match interrupt" "0,1" newline bitfld.word 0x2 7. "PCR,Force position-compare ready interrupt" "0,1" bitfld.word 0x2 6. "PCO,Force position counter overflow interrupt" "0,1" bitfld.word 0x2 5. "PCU,Force position counter underflow interrupt" "0,1" bitfld.word 0x2 4. "WTO,Force watchdog time out interrupt" "0,1" bitfld.word 0x2 3. "QDC,Force quadrature direction change interrupt" "0,1" newline bitfld.word 0x2 2. "PHE,Force quadrature phase error interrupt" "0,1" bitfld.word 0x2 1. "PCE,Force position counter error interrupt" "0,1" line.word 0x4 "REG_QEPSTS_TYPE1,QEP Status" bitfld.word 0x4 7. "UPEVNT,Unit position event flag" "0,1" rbitfld.word 0x4 6. "FIDF,Direction on the first index markerStatus of the direction is latched on the first index event marker." "0,1" rbitfld.word 0x4 5. "QDF,Quadrature direction flag" "0,1" rbitfld.word 0x4 4. "QDLF,eQEP direction latch flag" "0,1" bitfld.word 0x4 3. "COEF,Capture overflow error flag" "0,1" newline bitfld.word 0x4 2. "CDEF,Capture direction error flag" "0,1" bitfld.word 0x4 1. "FIMF,First index marker flag" "0,1" rbitfld.word 0x4 0. "PCEF,Position counter error flag. This bit is not sticky and it is updated for every index event." "0,1" line.word 0x6 "REG_QCTMR,QEP Capture Timer" hexmask.word 0x6 0.--15. 1. "QCTMR,This register provides time base for edge capture unit." line.word 0x8 "REG_QCPRD,QEP Capture Period" hexmask.word 0x8 0.--15. 1. "QCPRD,This register holds the period count value between the last successive eQEP position events" rgroup.word 0x3E++0x3 line.word 0x0 "REG_QCTMRLAT,QEP Capture Latch" hexmask.word 0x0 0.--15. 1. "QCTMRLAT,The eQEP capture timer value can be latched into this register on two events viz. unit timeout event reading the eQEP position counter." line.word 0x2 "REG_QCPRDLAT,QEP Capture Period Latch" hexmask.word 0x2 0.--15. 1. "QCPRDLAT,eQEP capture period value can be latched into this register on two events viz. unit timeout event reading the eQEP position counter." group.word 0x42++0x1 line.word 0x0 "REG_Reserved_1" rgroup.long 0x60++0x3 line.long 0x0 "REG_REV_TYPE2,QEP Revision Number" bitfld.long 0x0 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" group.long 0x64++0xB line.long 0x0 "REG_QEPSTROBESEL,QEP Strobe select register" bitfld.long 0x0 0.--1. "STROBESEL,Strobe source select:" "0,1,2,3" line.long 0x4 "REG_QMACTRL,QMA Control register" bitfld.long 0x4 0.--2. "MODE,Select Mode for QMA mode:000 : QMA Module is bypassed. 001 : QMA Mode-1 operation selected010 : QMA Mode-2 operation selected011 : QMA Module is bypassed [reserved]1xx : QMA Module is bypassed [reserved]" "0: QMA Module is bypassed,1: QMA Mode-1 operation selected010 : QMA Mode-2..,?,?,?,?,?,?" line.long 0x8 "REG_QEPSRCSEL,QEP Source Select Register" hexmask.long.byte 0x8 12.--15. 1. "QEPSSEL,QEP Strobe source select:0000: From device Pins [Default].0001-1111: Device dependent." hexmask.long.byte 0x8 8.--11. 1. "QEPISEL,QEP Index source select:0000: From device Pins [Default].0001-1111: Device dependent." hexmask.long.byte 0x8 4.--7. 1. "QEPBSEL,QEPB source select:0000: From device Pins [Default].0001-1111: Device dependent." hexmask.long.byte 0x8 0.--3. 1. "QEPASEL,QEPA source select:0000: From device Pins [Default].0001-1111: Device dependent." group.word 0x70++0x1 line.word 0x0 "REG_Reserved_2" tree.end tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "ESM0_CFG" base ad:0x420000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_INFO,The Info Register gives the configuration Inforrmation of this ESM." bitfld.long 0x4 31. "LAST_RESET,Indicates the Source of the last Reset" "0,1" hexmask.long.byte 0x4 8.--15. 1. "PULSE_GROUPS,Number of Pulse Error Groups" hexmask.long.byte 0x4 0.--7. 1. "GROUPS,Total number of Error Groups" group.long 0x8++0x3 line.long 0x0 "CFG_EN,The Global Enable Register has the master interrupt mask" hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Enable" wgroup.long 0xC++0x3 line.long 0x0 "CFG_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables" hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Soft Reset" group.long 0x10++0xF line.long 0x0 "CFG_ERR_RAW,Raw Status/Set Register for Configuration Errors" hexmask.long.byte 0x0 0.--6. 1. "STS,This is the raw status for config errors" line.long 0x4 "CFG_ERR_STS,Config Error Enable and Clear Register" hexmask.long.byte 0x4 0.--6. 1. "MSK,This is the masked status/clear for config errors" line.long 0x8 "CFG_ERR_EN_SET,Config Error Enable Set Register" hexmask.long.byte 0x8 0.--6. 1. "MSK,This is the mask enable set for config errors" line.long 0xC "CFG_ERR_EN_CLR,Config Error Interrupt Enabled Clear register" hexmask.long.byte 0xC 0.--6. 1. "MSK,This is the mask enable clear for config errors" rgroup.long 0x20++0xF line.long 0x0 "CFG_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt" hexmask.long.word 0x0 16.--31. 1. "PLS,This is the highest priority outstanding low priority pulse interrupt" hexmask.long.word 0x0 0.--15. 1. "LVL,This is the highest priority outstanding low priority level interrupt" line.long 0x4 "CFG_HI_PRI,Shows which is the highest priority outstanding high priority interrupt" hexmask.long.word 0x4 16.--31. 1. "PLS,This is the highest priority outstanding high priority pulse interrupt" hexmask.long.word 0x4 0.--15. 1. "LVL,This is the highest priority outstanding high priority level interrupt" line.long 0x8 "CFG_LOW,Shows which groups have oustanding low priority interrupts" hexmask.long 0x8 0.--31. 1. "STS,This is the raw status for config errors" line.long 0xC "CFG_HI,Shows which groups have oustanding high priority interrupts" hexmask.long 0xC 0.--31. 1. "STS,This is the raw status for config errors" wgroup.long 0x30++0x3 line.long 0x0 "CFG_EOI,End of Interrupt Register" hexmask.long.word 0x0 0.--10. 1. "KEY,This is the interrupt being serviced" group.long 0x40++0x3 line.long 0x0 "CFG_PIN_CTRL,This register controls the error_pin_n output" hexmask.long.byte 0x0 4.--7. 1. "PWM_EN,PWM enable" hexmask.long.byte 0x0 0.--3. 1. "KEY,Pin Control Key" rgroup.long 0x44++0x7 line.long 0x0 "CFG_PIN_STS,This register reflects the status of the error_pin_n output" bitfld.long 0x0 0. "VAL,Value of the error_pin_n" "0,1" line.long 0x4 "CFG_PIN_CNTR,This register shows the current value of the error pin counter" hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Current Counter Value" group.long 0x4C++0x3 line.long 0x0 "CFG_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" rgroup.long 0x50++0x3 line.long 0x0 "CFG_PWMH_PIN_CNTR,This register shows the current value of the error pin PWM high counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value" group.long 0x54++0x3 line.long 0x0 "CFG_PWMH_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM High Counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" rgroup.long 0x58++0x3 line.long 0x0 "CFG_PWML_PIN_CNTR,This register shows the current value of the error pin PWM low counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value" group.long 0x5C++0x3 line.long 0x0 "CFG_PWML_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM Low Counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" group.long 0x400++0x1B line.long 0x0 "CFG_RAW,Raw Status/Set Register for Group A Errors" hexmask.long 0x0 0.--31. 1. "STS,This is the raw status/set for errors Group A" line.long 0x4 "CFG_STS,Error Enable and Clear Register" hexmask.long 0x4 0.--31. 1. "MSK,This is the masked status/clear for errors in Group A" line.long 0x8 "CFG_INTR_EN_SET,Level Error Enable Set Register" hexmask.long 0x8 0.--31. 1. "MSK,This is the mask enable set for errors in Group A" line.long 0xC "CFG_INTR_EN_CLR,Level Error Interrupt Enabled Clear register" hexmask.long 0xC 0.--31. 1. "MSK,This is the mask enable clear for errors in Group A" line.long 0x10 "CFG_INT_PRIO,Level Error Interrupt Enabled Clear register" hexmask.long 0x10 0.--31. 1. "MSK,This is interrupt priority for errors in Group A" line.long 0x14 "CFG_PIN_EN_SET,Level Error Interrupt Enabled Clear register" hexmask.long 0x14 0.--31. 1. "MSK,This is the error pin influence enable set for errors in Group A" line.long 0x18 "CFG_PIN_EN_CLR,Level Error Interrupt Enabled Clear register" hexmask.long 0x18 0.--31. 1. "MSK,This is the error pin influence enable clear for errors in Group A" tree.end tree "FSS0" base ad:0x0 tree "FSS0_CFG" base ad:0xFC00000 rgroup.long 0x0++0x3 line.long 0x0 "FSS_MMR__FSS_MMR_CFG__FSS_GENREGS_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" tree.end tree "FSS0_FSAS_0_DAT_REG0" base ad:0x400000000 group.long 0x0++0x3 line.long 0x0 "DAT_REG0_hpb_data_mem,FSAS data region0" hexmask.long 0x0 0.--31. 1. "HPB_DATA,FSAS data region0" tree.end tree "FSS0_FSAS_0_DAT_REG1" base ad:0x60000000 group.long 0x0++0x3 line.long 0x0 "DAT_REG1_hpb_data_mem,FSAS boot data region1" hexmask.long 0x0 0.--31. 1. "HPB_DATA,FSAS data region1" tree.end tree "FSS0_FSAS_0_DAT_REG3" base ad:0x500000000 group.long 0x0++0x3 line.long 0x0 "DAT_REG3_hpb_data_mem,FSAS bypass data region3" hexmask.long 0x0 0.--31. 1. "HPB_DATA,FSAS data region1" tree.end tree "FSS0_FSAS_0_FSAS_CFG" base ad:0xFC10000 rgroup.long 0x0++0x3 line.long 0x0 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" hexmask.long.word 0x0 16.--31. 1. "MODID,Module ID field" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision" group.long 0x4++0x1F line.long 0x0 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_SYSCONFIG,Controls various parameters of the cotroller state." bitfld.long 0x0 8. "OSPI_32B_DISABLE_MODE,0 OSPI 32bit mode enabled. 1 OSPI 32bit mode disabled" "0,1" bitfld.long 0x0 7. "DISXIP,0 XIP Prefetch Enabled. 1 XIP prefetch disabled" "0,1" bitfld.long 0x0 6. "OSPI_DDR_DISABLE_MODE,0 OSPI DDR mode enabled. 1 OSPI DDR mode disabled" "0,1" newline bitfld.long 0x0 3. "ECC_DISABLE_ADR,0 Block address within ECC calculation 1 Block address not within ECC calculation" "0,1" rbitfld.long 0x0 2. "FSS_AES_EN_IPCFG,1 select security 0 disable security" "0,1" bitfld.long 0x0 0. "ECC_EN,0 ECC disabled. 1 ECC enabled" "0,1" line.long 0x4 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_FRAG_ADR,This FRAG_ADR is the address of a request that frag_hi or frag_lo boundary occurs" hexmask.long 0x4 0.--31. 1. "FRAG_ADDR,This address is used to determine the boundary of frag_hi and flag_lo" line.long 0x8 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_FRAG_CTL,The FRAG_CTL determins which frag region is fragmented" bitfld.long 0x8 1. "FRAG_HI,When set any address greater than or equal to frag_addr will be fragmented to 16 bits" "0,1" bitfld.long 0x8 0. "FRAG_LO,When set any address less than frag_addr will be fragmented to 16 bits" "0,1" line.long 0xC "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_EOI,The End of Interrupt (EOI) MISC Register allows the CPU to acknowledge completion of an interrupt by writing to the EOI for MISC interrupt sources. An eoi_write signal will be generated and another interrupt will be.." bitfld.long 0xC 0. "EOI_VECTOR,Write with bit position of targeted interrupt. (E.g. Ext FSS ECC is bit 0). Upon write level interrupt will clear and if un-serviced will issue another pulse interrupt" "0,1" line.long 0x10 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_STATUS_RAW,The IRQ_STATUS_RAW register allows the interrupt sources to be manually set when writing a 1 to a specific bit. Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending" bitfld.long 0x10 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" bitfld.long 0x10 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1" bitfld.long 0x10 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1" line.long 0x14 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_STATUS,The IRQ_STATUS register allows the interrupt sources to be manually cleared when writing a 1 to a specific bit. Write 0: No action Write 1: Clear event Read 0: No event pending Read 1: Event pending" bitfld.long 0x14 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" bitfld.long 0x14 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1" bitfld.long 0x14 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1" line.long 0x18 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ENABLE_SET,The IRQ_ENABLE_SET register allows the interrupt sources to be manually enabled when writing a 1 to a specific bit. Write 0: No action Write 1: Enable event Read 0: Event is disabled Read 1: Event is enabled" bitfld.long 0x18 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" bitfld.long 0x18 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1" bitfld.long 0x18 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1" line.long 0x1C "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ENABLE_CLR,The IRQ_ENABLE_CLR register allows the interrupt sources to be manually disabled when writing a 1 to a specific bit. Write 0: No action Write 1: Disable event Read 0: Event is disabled Read 1: Event is enabled" bitfld.long 0x1C 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1" bitfld.long 0x1C 1. "ECC_ERROR_2BIT,ECC error on 2 bits. Not correctable" "0,1" bitfld.long 0x1C 0. "ECC_ERROR_1BIT,ECC error on 1 bits. correctable" "0,1" group.long 0x30++0x7 line.long 0x0 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_RGSTRT,This defines the start of the ECC region in 4KBytes steps." hexmask.long.tbyte 0x0 0.--19. 1. "R_START,This defines the start of the ECC region in 4KBytes steps. Address start = {start[19:0] 0x000} 0x0 means the start is 0x0000_0000 0x1 means the start is 0x0000_1000 0xA means the start is 0x0000_A000 Note the offset + size should be <=.." line.long 0x4 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_RGSIZ,This defines the size of the ECC region in 4KBytes steps." hexmask.long.tbyte 0x4 0.--19. 1. "R_SIZE,This defines the size of the ECC region in 4KBytes steps 0x0 means the size is zero and disabled 0x1 means the size is 4KBytes 0xA means the size is 40KBytes 0xF_FFFF means the size is 4GBytes Note the offset + size should be <= 4GBytes wrap.." rgroup.long 0x70++0x3 line.long 0x0 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_BLOCK_ADR,The ERR_ECC_BLOCK_ADR register holds the current top of stack ECC error block address. this is only valid when the ecc_err_valid is set" hexmask.long 0x0 5.--31. 1. "ECC_ERROR_BLOCK_ADDR,ECC 32 byte aligned block address" group.long 0x74++0x7 line.long 0x0 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_TYPE,The ERR_ECC_TYPE register holds the current top of stack ECC error info. this is only valid when the ecc_err_valid is set" bitfld.long 0x0 31. "ECC_ERR_VALID,When set indicates that there is valid ECC error information available Writing a one to this register will pop the top of the stack" "0,1" rbitfld.long 0x0 5. "ECC_ERR_ADR,When set indicates that there was a single error detected within the address field" "0,1" rbitfld.long 0x0 4. "ECC_ERR_MAC,When set indicates that there was a single error detected within the MAC field" "0,1" newline rbitfld.long 0x0 3. "ECC_ERR_DA1,When set indicates that there was a single error detected within the High Data word" "0,1" rbitfld.long 0x0 2. "ECC_ERR_DA0,When set indicates that there was a single error detected within the Low Data word" "0,1" rbitfld.long 0x0 1. "ECC_ERR_DED,When set indicates that there was a double error detected for the block" "0,1" newline rbitfld.long 0x0 0. "ECC_ERR_SEC,hen set indicates that there was a single error detected for the block" "0,1" line.long 0x4 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_WRT_TYPE,The ERR_WRT_TYPE register holds the current top of stack write error info. this is only valid when the wrt_err_valid is set" bitfld.long 0x4 31. "WRT_ERR_VALID,When set indicates that there is valid write error information available Writing a one to this register will pop the top of the stack" "0,1" rbitfld.long 0x4 13. "WRT_ERR_BEN,When set indicates that there was a write error due to a non-contiguous byte enables" "0,1" rbitfld.long 0x4 12. "WRT_ERR_ADR,When set indicates that there was a write error due to a non-aligned address" "0,1" newline hexmask.long.word 0x4 0.--11. 1. "WRT_ERR_ROUTEID,Indicates the Route ID for the Master that caused the write error" tree.end tree "FSS0_FSAS_0_OTFA_CFG" base ad:0xFC20000 rgroup.long 0x0++0x3 line.long 0x0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_revid" hexmask.long 0x0 0.--31. 1. "REVID,REVID" group.long 0x4++0x21B line.long 0x0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_scfg" bitfld.long 0x0 0.--1. "IDLE_MODE,IDLE MODE" "0,1,2,3" line.long 0x4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_isr" hexmask.long.byte 0x4 12.--15. 1. "MAC_ERR,MAC error" hexmask.long.byte 0x4 8.--11. 1. "WRT_ERR,Write error" hexmask.long.byte 0x4 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region" newline hexmask.long.byte 0x4 0.--3. 1. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule" line.long 0x8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_is" hexmask.long.byte 0x8 12.--15. 1. "MAC_ERR,MAC error" hexmask.long.byte 0x8 8.--11. 1. "WRT_ERR,Write error" hexmask.long.byte 0x8 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region" newline hexmask.long.byte 0x8 0.--3. 1. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule" line.long 0xC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_ies" hexmask.long.byte 0xC 12.--15. 1. "MAC_ERR,MAC error" hexmask.long.byte 0xC 8.--11. 1. "WRT_ERR,Write error" hexmask.long.byte 0xC 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region" newline hexmask.long.byte 0xC 0.--3. 1. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule" line.long 0x10 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_iec" hexmask.long.byte 0x10 12.--15. 1. "MAC_ERR,MAC error" hexmask.long.byte 0x10 8.--11. 1. "WRT_ERR,Write error" hexmask.long.byte 0x10 4.--7. 1. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region" newline hexmask.long.byte 0x10 0.--3. 1. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule" line.long 0x14 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_ccfg" bitfld.long 0x14 31. "MASTER_EN_RD,This register controls the enabling the functionality of this IP Disabled and Bypass mode active" "0,1" bitfld.long 0x14 9. "ERROR_RESP_EN,This register controls the enabling the the ocp error response for mac errors" "0,1" bitfld.long 0x14 8. "OTFA_WAIT,This register allows the ability to stop accepting any new transactions from getting accepted and allow the current transactions to complete" "0,1" newline bitfld.long 0x14 6. "CACHE_ENABLE,MAC cache enable" "0,1" bitfld.long 0x14 5. "CACHE_EVICT_MODE,cache evict mode" "0,1" bitfld.long 0x14 4. "KEY_SIZE,Key Size 0 128 Bit 1 256 Bit" "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "RD_WRT_OPT,This register defines the static allocation of the AES cores to read transactions. The remainder will be allocated to write transactions" line.long 0x18 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_cstatus" rbitfld.long 0x18 31. "BUSY,0 No transactions are active crypto or none crypto 1 One or more transactions are active crypto or none crypto" "0,1" rbitfld.long 0x18 30. "CRYPTO_BUSY,0 No transactions are active crypto or none crypto 1 One or more transactions are active crypto or none crypto" "0,1" hexmask.long.word 0x18 16.--29. 1. "RD_STALL_EVENT_CNT,rd stall event do to lack of eng" newline hexmask.long.word 0x18 0.--13. 1. "WRT_STALL_EVENT_CNT,wrt stall event do to lack of eng" line.long 0x1C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgcfg0" bitfld.long 0x1C 4. "WRT_PROTECT0,WRT protect" "0,1" bitfld.long 0x1C 2.--3. "MAC_MODE0,MAC mode" "0,1,2,3" bitfld.long 0x1C 0.--1. "AES_MODE0,AES mode" "0,1,2,3" line.long 0x20 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgmacst0" hexmask.long.tbyte 0x20 0.--19. 1. "M_START0,This defines the start of the mac buffer in 4KBytes steps" line.long 0x24 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgst0" hexmask.long.tbyte 0x24 0.--19. 1. "R_START0,This defines the start of the crypto region in 4KBytes steps" line.long 0x28 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgsi0" hexmask.long.tbyte 0x28 0.--19. 1. "R_SIZE0,This defines the size of the crypto region in 4KBytes steps" line.long 0x2C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye00" hexmask.long 0x2C 0.--31. 1. "R_KEY_E00,Key E" line.long 0x30 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye01" hexmask.long 0x30 0.--31. 1. "R_KEY_E01,Key E" line.long 0x34 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye02" hexmask.long 0x34 0.--31. 1. "R_KEY_E02,Key E" line.long 0x38 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye03" hexmask.long 0x38 0.--31. 1. "R_KEY_E03,Key E" line.long 0x3C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye04" hexmask.long 0x3C 0.--31. 1. "R_KEY_E04,Key E" line.long 0x40 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye05" hexmask.long 0x40 0.--31. 1. "R_KEY_E05,Key E" line.long 0x44 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye06" hexmask.long 0x44 0.--31. 1. "R_KEY_E06,Key E" line.long 0x48 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye07" hexmask.long 0x48 0.--31. 1. "R_KEY_E07,Key E" line.long 0x4C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep00" hexmask.long 0x4C 0.--31. 1. "R_KEY_EP00,Key EP" line.long 0x50 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep01" hexmask.long 0x50 0.--31. 1. "R_KEY_EP01,Key EP" line.long 0x54 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep02" hexmask.long 0x54 0.--31. 1. "R_KEY_EP02,Key EP" line.long 0x58 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep03" hexmask.long 0x58 0.--31. 1. "R_KEY_EP03,Key EP" line.long 0x5C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep04" hexmask.long 0x5C 0.--31. 1. "R_KEY_EP04,Key EP" line.long 0x60 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep05" hexmask.long 0x60 0.--31. 1. "R_KEY_EP05,Key EP" line.long 0x64 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep06" hexmask.long 0x64 0.--31. 1. "R_KEY_EP06,Key EP" line.long 0x68 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep07" hexmask.long 0x68 0.--31. 1. "R_KEY_EP07,Key EP" line.long 0x6C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya00" hexmask.long 0x6C 0.--31. 1. "R_KEY_A00,Key A" line.long 0x70 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya01" hexmask.long 0x70 0.--31. 1. "R_KEY_A01,Key A" line.long 0x74 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya02" hexmask.long 0x74 0.--31. 1. "R_KEY_A02,Key A" line.long 0x78 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya03" hexmask.long 0x78 0.--31. 1. "R_KEY_A03,Key A" line.long 0x7C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap00" hexmask.long 0x7C 0.--31. 1. "R_KEY_AP00,Key AP" line.long 0x80 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap01" hexmask.long 0x80 0.--31. 1. "R_KEY_AP01,Key AP" line.long 0x84 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap02" hexmask.long 0x84 0.--31. 1. "R_KEY_AP02,Key AP" line.long 0x88 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap03" hexmask.long 0x88 0.--31. 1. "R_KEY_AP03,Key AP" line.long 0x8C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv00" hexmask.long 0x8C 0.--31. 1. "R_IV00,IV" line.long 0x90 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv01" hexmask.long 0x90 0.--31. 1. "R_IV01,IV" line.long 0x94 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv02" hexmask.long 0x94 0.--31. 1. "R_IV02,IV" line.long 0x98 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv03" hexmask.long 0x98 0.--31. 1. "R_IV03,IV" line.long 0x9C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgcfg1" bitfld.long 0x9C 4. "WRT_PROTECT1,WRT protect" "0,1" bitfld.long 0x9C 2.--3. "MAC_MODE1,MAC mode" "0,1,2,3" bitfld.long 0x9C 0.--1. "AES_MODE1,AES mode" "0,1,2,3" line.long 0xA0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgmacst1" hexmask.long.tbyte 0xA0 0.--19. 1. "M_START1,This defines the start of the mac buffer in 4KBytes steps" line.long 0xA4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgst1" hexmask.long.tbyte 0xA4 0.--19. 1. "R_START1,This defines the start of the crypto region in 4KBytes steps" line.long 0xA8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgsi1" hexmask.long.tbyte 0xA8 0.--19. 1. "R_SIZE1,This defines the size of the crypto region in 4KBytes steps" line.long 0xAC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye10" hexmask.long 0xAC 0.--31. 1. "R_KEY_E10,Key E" line.long 0xB0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye11" hexmask.long 0xB0 0.--31. 1. "R_KEY_E11,Key E" line.long 0xB4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye12" hexmask.long 0xB4 0.--31. 1. "R_KEY_E12,Key E" line.long 0xB8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye13" hexmask.long 0xB8 0.--31. 1. "R_KEY_E13,Key E" line.long 0xBC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye14" hexmask.long 0xBC 0.--31. 1. "R_KEY_E14,Key E" line.long 0xC0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye15" hexmask.long 0xC0 0.--31. 1. "R_KEY_E15,Key E" line.long 0xC4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye16" hexmask.long 0xC4 0.--31. 1. "R_KEY_E16,Key E" line.long 0xC8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye17" hexmask.long 0xC8 0.--31. 1. "R_KEY_E17,Key E" line.long 0xCC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep10" hexmask.long 0xCC 0.--31. 1. "R_KEY_EP10,Key EP" line.long 0xD0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep11" hexmask.long 0xD0 0.--31. 1. "R_KEY_EP11,Key EP" line.long 0xD4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep12" hexmask.long 0xD4 0.--31. 1. "R_KEY_EP12,Key EP" line.long 0xD8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep13" hexmask.long 0xD8 0.--31. 1. "R_KEY_EP13,Key EP" line.long 0xDC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep14" hexmask.long 0xDC 0.--31. 1. "R_KEY_EP14,Key EP" line.long 0xE0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep15" hexmask.long 0xE0 0.--31. 1. "R_KEY_EP15,Key EP" line.long 0xE4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep16" hexmask.long 0xE4 0.--31. 1. "R_KEY_EP16,Key EP" line.long 0xE8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep17" hexmask.long 0xE8 0.--31. 1. "R_KEY_EP17,Key EP" line.long 0xEC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya10" hexmask.long 0xEC 0.--31. 1. "R_KEY_A10,Key A" line.long 0xF0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya11" hexmask.long 0xF0 0.--31. 1. "R_KEY_A11,Key A" line.long 0xF4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya12" hexmask.long 0xF4 0.--31. 1. "R_KEY_A12,Key A" line.long 0xF8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya13" hexmask.long 0xF8 0.--31. 1. "R_KEY_A13,Key A" line.long 0xFC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap10" hexmask.long 0xFC 0.--31. 1. "R_KEY_AP10,Key AP" line.long 0x100 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap11" hexmask.long 0x100 0.--31. 1. "R_KEY_AP11,Key AP" line.long 0x104 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap12" hexmask.long 0x104 0.--31. 1. "R_KEY_AP12,Key AP" line.long 0x108 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap13" hexmask.long 0x108 0.--31. 1. "R_KEY_AP13,Key AP" line.long 0x10C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv10" hexmask.long 0x10C 0.--31. 1. "R_IV10,IV" line.long 0x110 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv11" hexmask.long 0x110 0.--31. 1. "R_IV11,IV" line.long 0x114 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv12" hexmask.long 0x114 0.--31. 1. "R_IV12,IV" line.long 0x118 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv13" hexmask.long 0x118 0.--31. 1. "R_IV13,IV" line.long 0x11C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgcfg2" bitfld.long 0x11C 4. "WRT_PROTECT2,WRT protect" "0,1" bitfld.long 0x11C 2.--3. "MAC_MODE2,MAC mode" "0,1,2,3" bitfld.long 0x11C 0.--1. "AES_MODE2,AES mode" "0,1,2,3" line.long 0x120 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgmacst2" hexmask.long.tbyte 0x120 0.--19. 1. "M_START2,This defines the start of the mac buffer in 4KBytes steps" line.long 0x124 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgst2" hexmask.long.tbyte 0x124 0.--19. 1. "R_START2,This defines the start of the crypto region in 4KBytes steps" line.long 0x128 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgsi2" hexmask.long.tbyte 0x128 0.--19. 1. "R_SIZE2,This defines the size of the crypto region in 4KBytes steps" line.long 0x12C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye20" hexmask.long 0x12C 0.--31. 1. "R_KEY_E20,Key E" line.long 0x130 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye21" hexmask.long 0x130 0.--31. 1. "R_KEY_E21,Key E" line.long 0x134 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye22" hexmask.long 0x134 0.--31. 1. "R_KEY_E22,Key E" line.long 0x138 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye23" hexmask.long 0x138 0.--31. 1. "R_KEY_E23,Key E" line.long 0x13C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye24" hexmask.long 0x13C 0.--31. 1. "R_KEY_E24,Key E" line.long 0x140 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye25" hexmask.long 0x140 0.--31. 1. "R_KEY_E25,Key E" line.long 0x144 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye26" hexmask.long 0x144 0.--31. 1. "R_KEY_E26,Key E" line.long 0x148 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye27" hexmask.long 0x148 0.--31. 1. "R_KEY_E27,Key E" line.long 0x14C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep20" hexmask.long 0x14C 0.--31. 1. "R_KEY_EP20,Key EP" line.long 0x150 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep21" hexmask.long 0x150 0.--31. 1. "R_KEY_EP21,Key EP" line.long 0x154 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep22" hexmask.long 0x154 0.--31. 1. "R_KEY_EP22,Key EP" line.long 0x158 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep23" hexmask.long 0x158 0.--31. 1. "R_KEY_EP23,Key EP" line.long 0x15C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep24" hexmask.long 0x15C 0.--31. 1. "R_KEY_EP24,Key EP" line.long 0x160 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep25" hexmask.long 0x160 0.--31. 1. "R_KEY_EP25,Key EP" line.long 0x164 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep26" hexmask.long 0x164 0.--31. 1. "R_KEY_EP26,Key EP" line.long 0x168 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep27" hexmask.long 0x168 0.--31. 1. "R_KEY_EP27,Key EP" line.long 0x16C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya20" hexmask.long 0x16C 0.--31. 1. "R_KEY_A20,Key A" line.long 0x170 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya21" hexmask.long 0x170 0.--31. 1. "R_KEY_A21,Key A" line.long 0x174 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya22" hexmask.long 0x174 0.--31. 1. "R_KEY_A22,Key A" line.long 0x178 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya23" hexmask.long 0x178 0.--31. 1. "R_KEY_A23,Key A" line.long 0x17C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap20" hexmask.long 0x17C 0.--31. 1. "R_KEY_AP20,Key AP" line.long 0x180 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap21" hexmask.long 0x180 0.--31. 1. "R_KEY_AP21,Key AP" line.long 0x184 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap22" hexmask.long 0x184 0.--31. 1. "R_KEY_AP22,Key AP" line.long 0x188 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap23" hexmask.long 0x188 0.--31. 1. "R_KEY_AP23,Key AP" line.long 0x18C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv20" hexmask.long 0x18C 0.--31. 1. "R_IV20,IV" line.long 0x190 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv21" hexmask.long 0x190 0.--31. 1. "R_IV21,IV" line.long 0x194 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv22" hexmask.long 0x194 0.--31. 1. "R_IV22,IV" line.long 0x198 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv23" hexmask.long 0x198 0.--31. 1. "R_IV23,IV" line.long 0x19C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgcfg3" bitfld.long 0x19C 4. "WRT_PROTECT3,WRT protect" "0,1" bitfld.long 0x19C 2.--3. "MAC_MODE3,MAC mode" "0,1,2,3" bitfld.long 0x19C 0.--1. "AES_MODE3,AES mode" "0,1,2,3" line.long 0x1A0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgmacst3" hexmask.long.tbyte 0x1A0 0.--19. 1. "M_START3,This defines the start of the mac buffer in 4KBytes steps" line.long 0x1A4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgst3" hexmask.long.tbyte 0x1A4 0.--19. 1. "R_START3,This defines the start of the crypto region in 4KBytes steps" line.long 0x1A8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgsi3" hexmask.long.tbyte 0x1A8 0.--19. 1. "R_SIZE3,This defines the size of the crypto region in 4KBytes steps" line.long 0x1AC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye30" hexmask.long 0x1AC 0.--31. 1. "R_KEY_E30,Key E" line.long 0x1B0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye31" hexmask.long 0x1B0 0.--31. 1. "R_KEY_E31,Key E" line.long 0x1B4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye32" hexmask.long 0x1B4 0.--31. 1. "R_KEY_E32,Key E" line.long 0x1B8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye33" hexmask.long 0x1B8 0.--31. 1. "R_KEY_E33,Key E" line.long 0x1BC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye34" hexmask.long 0x1BC 0.--31. 1. "R_KEY_E34,Key E" line.long 0x1C0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye35" hexmask.long 0x1C0 0.--31. 1. "R_KEY_E35,Key E" line.long 0x1C4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye36" hexmask.long 0x1C4 0.--31. 1. "R_KEY_E36,Key E" line.long 0x1C8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye37" hexmask.long 0x1C8 0.--31. 1. "R_KEY_E37,Key E" line.long 0x1CC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep30" hexmask.long 0x1CC 0.--31. 1. "R_KEY_EP30,Key EP" line.long 0x1D0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep31" hexmask.long 0x1D0 0.--31. 1. "R_KEY_EP31,Key EP" line.long 0x1D4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep32" hexmask.long 0x1D4 0.--31. 1. "R_KEY_EP32,Key EP" line.long 0x1D8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep33" hexmask.long 0x1D8 0.--31. 1. "R_KEY_EP33,Key EP" line.long 0x1DC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep34" hexmask.long 0x1DC 0.--31. 1. "R_KEY_EP34,Key EP" line.long 0x1E0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep35" hexmask.long 0x1E0 0.--31. 1. "R_KEY_EP35,Key EP" line.long 0x1E4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep36" hexmask.long 0x1E4 0.--31. 1. "R_KEY_EP36,Key EP" line.long 0x1E8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep37" hexmask.long 0x1E8 0.--31. 1. "R_KEY_EP37,Key EP" line.long 0x1EC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya30" hexmask.long 0x1EC 0.--31. 1. "R_KEY_A30,Key A" line.long 0x1F0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya31" hexmask.long 0x1F0 0.--31. 1. "R_KEY_A31,Key A" line.long 0x1F4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya32" hexmask.long 0x1F4 0.--31. 1. "R_KEY_A32,Key A" line.long 0x1F8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya33" hexmask.long 0x1F8 0.--31. 1. "R_KEY_A33,Key A" line.long 0x1FC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap30" hexmask.long 0x1FC 0.--31. 1. "R_KEY_AP30,Key AP" line.long 0x200 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap31" hexmask.long 0x200 0.--31. 1. "R_KEY_AP31,Key AP" line.long 0x204 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap32" hexmask.long 0x204 0.--31. 1. "R_KEY_AP32,Key AP" line.long 0x208 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap33" hexmask.long 0x208 0.--31. 1. "R_KEY_AP33,Key AP" line.long 0x20C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv30" hexmask.long 0x20C 0.--31. 1. "R_IV30,IV" line.long 0x210 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv31" hexmask.long 0x210 0.--31. 1. "R_IV31,IV" line.long 0x214 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv32" hexmask.long 0x214 0.--31. 1. "R_IV32,IV" line.long 0x218 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv33" hexmask.long 0x218 0.--31. 1. "R_IV33,IV" rgroup.long 0x220++0xF line.long 0x0 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_irqaddinfo0" hexmask.long 0x0 0.--31. 1. "IRQ_MADDR,Master Address which caused the event" line.long 0x4 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_irqaddinfo1" hexmask.long.byte 0x4 14.--17. 1. "IRQ_MLEN,Master LENGTH which caused the event" bitfld.long 0x4 11.--13. "IRQ_MSEQ,Master SEQ which caused the event" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "IRQ_MCMD,Master CMD which caused the event" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--7. 1. "IRQ_MID,Master TAG ID which caused the event" line.long 0x8 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_maccacheinfo" hexmask.long.word 0x8 0.--15. 1. "CACHE_MISS_EVENT_CNT,MAC Cache Miss event cnt" line.long 0xC "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rmwrmcnt" hexmask.long.word 0xC 16.--31. 1. "RM_EVENT_CNT,RM event cnt" hexmask.long.word 0xC 0.--15. 1. "RMW_EVENT_CNT,RMW event cnt" tree.end tree "FSS0_OSPI_0_OSPI0_CTRL" base ad:0xFC40000 group.long 0x0++0x2B line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_config_reg,Octal-SPI Configuration Register" rbitfld.long 0x0 31. "IDLE_FLD,Serial interface and low level SPI pipeline is IDLE: This is a STATUS read-only bit. Note this is a retimed signal so there will be some inherent delay on the generation of this status signal." "0,1" newline bitfld.long 0x0 30. "DUAL_BYTE_OPCODE_EN_FLD,Dual-byte Opcode Mode enable bit This bit is to be set in case the target Flash Device supports dual byte opcode [i.e. Macronix MX25]. It is applicable for Octal I/O Mode or Protocol only so should be set back to low if the device.." "0,1" newline bitfld.long 0x0 29. "CRC_ENABLE_FLD,CRC enable bit This bit is to be set in case the target Flash Device supports CRC [Macronix MX25]. It is applicable for Octal DDR Protocol only so should be set back to low if the device is configured to work in another SPI Mode." "0,1" newline bitfld.long 0x0 25. "PIPELINE_PHY_FLD,Pipeline PHY Mode enable: This bit is relevant only for configuration with PHY Module. It should be asserted to 1 between consecutive PHY pipeline reads transfers and de-asserted to 0 otherwise." "0,1" newline bitfld.long 0x0 24. "ENABLE_DTR_PROTOCOL_FLD,Enable DTR Protocol: This bit should be set if device is configured to work in DTR protocol." "0,1" newline bitfld.long 0x0 23. "ENABLE_AHB_DECODER_FLD,Enable AHB Decoder: Value=0 : Active slave is selected based on Peripheral Chip Select Lines [bits [13:10]]. Value=1 Active slave is selected based on actual AHB address [the partition for each device is calculated with respect to.." "0: Active slave is selected based on Peripheral..,?" newline hexmask.long.byte 0x0 19.--22. 1. "MSTR_BAUD_DIV_FLD,Master Mode Baud Rate Divisor: SPI baud rate = [master reference clock] baud_rate_divisor" newline bitfld.long 0x0 18. "ENTER_XIP_MODE_IMM_FLD,Enter XIP Mode immediately: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : Operate the device in XIP mode immediately Use this register when the.." "0: If XIP is enabled,1: Operate the device in XIP mode immediately Use.." newline bitfld.long 0x0 17. "ENTER_XIP_MODE_FLD,Enter XIP Mode on next READ: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : If XIP is disabled then setting to ?1? will inform the controller that the.." "0: If XIP is enabled,1: If XIP is disabled" newline bitfld.long 0x0 16. "ENB_AHB_ADDR_REMAP_FLD,Enable AHB Address Re-mapping: [Direct Access Mode Only] When set to 1 the incoming AHB address will be adapted and sent to the FLASH device as [address + N] where N is the value stored in the remap address register." "0,1" newline bitfld.long 0x0 15. "ENB_DMA_IF_FLD,Enable DMA Peripheral Interface: Set to 1 to enable the DMA handshaking logic. When enabled the controller will trigger DMA transfer requests via the DMA peripheral interface. Set to 0 to disable" "0,1" newline bitfld.long 0x0 14. "WR_PROT_FLASH_FLD,Write Protect Flash Pin: Set to drive the Write Protect pin of the FLASH device. This is resynchronized to the generated memory clock as necessary." "0,1" newline hexmask.long.byte 0x0 10.--13. 1. "PERIPH_CS_LINES_FLD,Peripheral Chip Select Lines: Peripheral chip select lines If pdec = 0 ss[3:0] are output thus: ss[3:0] n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 [no peripheral selected] else ss[3:0] directly drives n_ss_out[3:0]" newline bitfld.long 0x0 9. "PERIPH_SEL_DEC_FLD,Peripheral select decode: 0 : only 1 of 4 selects n_ss_out[3:0] is active 1 : allow external 4-to-16 decode [n_ss_out = ss]" "0: only 1 of 4 selects n_ss_out[3:0] is active,1: allow external 4-to-16 decode [n_ss_out = ss]" newline bitfld.long 0x0 8. "ENB_LEGACY_IP_MODE_FLD,Legacy IP Mode Enable: 0 : Use Direct Access Controller/Indirect Access Controller 1 : legacy Mode is enabled. In this mode any write to the controller via the AHB interface is serialized and sent to the FLASH device. Any valid.." "0: Use Direct Access Controller/Indirect Access..,1: legacy Mode is enabled" newline bitfld.long 0x0 7. "ENB_DIR_ACC_CTLR_FLD,Enable Direct Access Controller: 0 : disable the Direct Access Controller once current transfer of the data word [FF_W] is complete. 1 : enable the Direct Access Controller When the Direct Access Controller and Indirect Access.." "0: disable the Direct Access Controller once..,1: enable the Direct Access Controller When the.." newline bitfld.long 0x0 6. "RESET_CFG_FLD,RESET pin configuration: 0 = RESET feature on DQ3 pin of the device 1 = RESET feature on dedicated pin of the device [controlling of 5th bit influences on reset_out output]" "0: RESET feature on DQ3 pin of the device,1: RESET feature on dedicated pin of the device.." newline bitfld.long 0x0 5. "RESET_PIN_FLD,Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature" "0,1" newline bitfld.long 0x0 4. "HOLD_PIN_FLD,Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature" "0,1" newline bitfld.long 0x0 3. "PHY_MODE_ENABLE_FLD,PHY mode enable: When enabled the controller is informed that PHY Module is to be used for handling SPI transfers. This bit is relevant only for configuration with PHY Module." "0,1" newline bitfld.long 0x0 2. "SEL_CLK_PHASE_FLD,Select Clock Phase: Selects whether the clock is in an active or inactive phase outside the SPI word. 0 : the SPI clock is active outside the word 1 : the SPI clock is inactive outside the word" "0: the SPI clock is active outside the word,1: the SPI clock is inactive outside the word" newline bitfld.long 0x0 1. "SEL_CLK_POL_FLD,Clock polarity outside SPI word: 0 : the SPI clock is quiescent low 1 : the SPI clock is quiescent high" "0: the SPI clock is quiescent low,1: the SPI clock is quiescent high" newline bitfld.long 0x0 0. "ENB_SPI_FLD,Octal-SPI Enable: 0 : disable the Octal-SPI once current transfer of the data word [FF_W] is complete. 1 : enable the Octal-SPI when spi_enable = 0 all output enables are inactive and all pins are set to input mode." "0: disable the Octal-SPI,1: enable the Octal-SPI" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_rd_config_reg,Device Read Instruction Configuration Register" hexmask.long.byte 0x4 24.--28. 1. "DUMMY_RD_CLK_CYCLES_FLD,Dummy Read Clock Cycles: Number of dummy clock cycles required by device for read instruction." newline bitfld.long 0x4 20. "MODE_BIT_ENABLE_FLD,Mode Bit Enable: Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline bitfld.long 0x4 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "0: SIO mode data is shifted to the device on DQ0..,1: Used for Dual Input/Output instructions,2: Used for Quad Input/Output instructions,3: Used for Quad Input/Output instructions" newline bitfld.long 0x4 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2.." "0: Addresses can be shifted to the device on DQ0 only,1: Addresses can be shifted to the device on DQ0..,2: Addresses can be shifted to the device on DQ0,3: Addresses can be shifted to the device on DQ[7:0]" newline bitfld.long 0x4 10. "DDR_EN_FLD,DDR Enable: This is to inform that opcode from rd_opcode_non_xip_fld is compliant with one of the DDR READ Commands" "0,1" newline bitfld.long 0x4 8.--9. "INSTR_TYPE_FLD,Instruction Type: 0 : Use Standard SPI mode [instruction always shifted into the device on DQ0 only] 1 : Use DIO-SPI mode [Instructions Address and Data always sent on DQ0 and DQ1] 2 : Use QIO-SPI mode [Instructions Address and Data.." "0: Use Standard SPI mode [instruction always..,1: Use DIO-SPI mode [Instructions,2: Use QIO-SPI mode [Instructions,3: Use Octal-IO-SPI mode [Instructions" newline hexmask.long.byte 0x4 0.--7. 1. "RD_OPCODE_NON_XIP_FLD,Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode" line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_wr_config_reg,Device Write Instruction Configuration Register" hexmask.long.byte 0x8 24.--28. 1. "DUMMY_WR_CLK_CYCLES_FLD,Dummy Write Clock Cycles: Number of dummy clock cycles required by device for write instruction." newline bitfld.long 0x8 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "0: SIO mode data is shifted to the device on DQ0..,1: Used for Dual Input/Output instructions,2: Used for Quad Input/Output instructions,3: Used for Quad Input/Output instructions" newline bitfld.long 0x8 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2.." "0: Addresses can be shifted to the device on DQ0 only,1: Addresses can be shifted to the device on DQ0..,2: Addresses can be shifted to the device on DQ0,3: Addresses can be shifted to the device on DQ[7:0]" newline bitfld.long 0x8 8. "WEL_DIS_FLD,WEL Disable: This is to turn off automatic issuing of WEL Command before write operation for DAC or INDAC" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "WR_OPCODE_FLD,Write Opcode" line.long 0xC "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_delay_reg,Octal-SPI Device Delay Register: This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles.." hexmask.long.byte 0xC 24.--31. 1. "D_NSS_FLD,Clock Delay for Chip Select Deassert: Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never.." newline hexmask.long.byte 0xC 16.--23. 1. "D_BTWN_FLD,Clock Delay for Chip Select Deactivation: Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different slaves and.." newline hexmask.long.byte 0xC 8.--15. 1. "D_AFTER_FLD,Clock Delay for Last Transaction Bit: Delay in master reference clocks between last bit of current transaction and deasserting the device chip select [n_ss_out]. By default the chip select will be deasserted on the cycle following the.." newline hexmask.long.byte 0xC 0.--7. 1. "D_INIT_FLD,Clock Delay with n_ss_out: Delay in master reference clocks between setting n_ss_out low and first bit transfer." line.long 0x10 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_rd_data_capture_reg,Read Data Capture Register" hexmask.long.byte 0x10 16.--19. 1. "DDR_READ_DELAY_FLD,DDR read delay: Delay the transmitted data by the programmed number of ref_clk cycles.This field is only relevant when DDR Read Command is executed. Otherwise can be ignored." newline bitfld.long 0x10 8. "DQS_ENABLE_FLD,DQS enable bit: If enabled signal from DQS input is driven into RX DLL and is used for data capturing in PHY Mode rather than internally generated gated ref_clk.." "0,1" newline bitfld.long 0x10 5. "SAMPLE_EDGE_SEL_FLD,Sample edge selection: Choose edge on which data outputs from flash memory will be sampled" "0,1" newline hexmask.long.byte 0x10 1.--4. 1. "DELAY_FLD,Read Delay: Delay the read data capturing logic by the programmed number of ref_clk cycles" newline bitfld.long 0x10 0. "BYPASS_FLD,Bypass the adapted loopback clock circuit" "0,1" line.long 0x14 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_size_config_reg,Device Size Configuration Register" bitfld.long 0x14 27.--28. "MEM_SIZE_ON_CS3_FLD,Size of Flash Device connected to CS[3] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?" newline bitfld.long 0x14 25.--26. "MEM_SIZE_ON_CS2_FLD,Size of Flash Device connected to CS[2] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?" newline bitfld.long 0x14 23.--24. "MEM_SIZE_ON_CS1_FLD,Size of Flash Device connected to CS[1] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?" newline bitfld.long 0x14 21.--22. "MEM_SIZE_ON_CS0_FLD,Size of Flash Device connected to CS[0] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "0: size of 512Mb,1: size of 1Gb,?,?" newline hexmask.long.byte 0x14 16.--20. 1. "BYTES_PER_SUBSECTOR_FLD,Number of bytes per Block. This is required by the controller for performing the write protection logic. The number of bytes per block must be a power of 2 number." newline hexmask.long.word 0x14 4.--15. 1. "BYTES_PER_DEVICE_PAGE_FLD,Number of bytes per device page. This is required by the controller for performing FLASH writes up to and across page boundaries." newline hexmask.long.byte 0x14 0.--3. 1. "NUM_ADDR_BYTES_FLD,Number of address bytes. A value of 0 indicates 1 byte." line.long 0x18 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_sram_partition_cfg_reg,SRAM Partition Configuration Register" hexmask.long.byte 0x18 0.--7. 1. "ADDR_FLD,Indirect Read Partition Size: Defines the size of the indirect read partition in the SRAM in units of SRAM locations. By default half of the SRAM is reserved for indirect read operation and half for indirect write. The size of this register.." line.long 0x1C "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_ind_AHB_addr_trigger_reg,Indirect AHB Address Trigger Register" hexmask.long 0x1C 0.--31. 1. "ADDR_FLD,This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15 then the AHB request will be completed by fetching.." line.long 0x20 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dma_periph_config_reg,DMA Peripheral Configuration Register" hexmask.long.byte 0x20 8.--11. 1. "NUM_BURST_REQ_BYTES_FLD,Number of Burst Bytes: Number of bytes in a burst type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual.." newline hexmask.long.byte 0x20 0.--3. 1. "NUM_SINGLE_REQ_BYTES_FLD,Number of Single Bytes: Number of bytes in a single type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The.." line.long 0x24 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_remap_addr_reg,Remap Address Register" hexmask.long 0x24 0.--31. 1. "VALUE_FLD,This register is used to remap an incoming AHB address to a different address used by the FLASH device." line.long 0x28 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_mode_bit_config_reg,Mode Bit Configuration Register" hexmask.long.byte 0x28 24.--31. 1. "RX_CRC_DATA_LOW_FLD,RX CRC data [lower] The first CRC byte returned after RX data chunk." newline hexmask.long.byte 0x28 16.--23. 1. "RX_CRC_DATA_UP_FLD,RX CRC data [upper] The second CRC byte returned after RX data chunk." newline bitfld.long 0x28 15. "CRC_OUT_ENABLE_FLD,CRC# output enable bit When enabled the controller expects the Flash Device to toggle CRC data on both SPI clock edges in CRC->CRC# sequence and calculates CRC compliance accordingly." "0,1" newline bitfld.long 0x28 8.--10. "CHUNK_SIZE_FLD,It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 0.--7. 1. "MODE_FLD,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled." rgroup.long 0x2C++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_sram_fill_reg,SRAM Fill Register" hexmask.long.word 0x0 16.--31. 1. "SRAM_FILL_INDAC_WRITE_FLD,SRAM Fill Level [Indirect Write Partition]: Identifies the current fill level of the SRAM Indirect Write partition" newline hexmask.long.word 0x0 0.--15. 1. "SRAM_FILL_INDAC_READ_FLD,SRAM Fill Level [Indirect Read Partition]: Identifies the current fill level of the SRAM Indirect Read partition" group.long 0x30++0x17 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_tx_thresh_reg,TX Threshold Register" hexmask.long.byte 0x0 0.--4. 1. "LEVEL_FLD,Defines the level at which the small TX FIFO not full interrupt is generated" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_rx_thresh_reg,RX Threshold Register" hexmask.long.byte 0x4 0.--4. 1. "LEVEL_FLD,Defines the level at which the small RX FIFO not empty interrupt is generated" line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_write_completion_ctrl_reg,Write Completion Control Register: This register defines how the controller will poll the device following a write transfer" hexmask.long.byte 0x8 24.--31. 1. "POLL_REP_DELAY_FLD,Defines additional delay for maintain Chip Select de-asserted during auto-polling phase" newline hexmask.long.byte 0x8 16.--23. 1. "POLL_COUNT_FLD,Defines the number of times the controller should expect to see a true result from the polling in successive reads of the device register." newline bitfld.long 0x8 15. "ENABLE_POLLING_EXP_FLD,Set to '1' for enabling auto-polling expiration." "0,1" newline bitfld.long 0x8 14. "DISABLE_POLLING_FLD,This switches off the automatic polling function" "0,1" newline bitfld.long 0x8 13. "POLLING_POLARITY_FLD,Defines the polling polarity. If '1' then the write transfer to the device will be complete if the polled bit is equal to '1'. If '0' then the write transfer to the device will be complete if the polled bit is equal to '0'." "0,1" newline bitfld.long 0x8 8.--10. "POLLING_BIT_INDEX_FLD,Defines the bit index that should be polled. A value of 010 means that bit 2 of the returned data will be polled for.A value of 111 means that bit 7 of the returned data will be polled for." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "OPCODE_FLD,Defines the opcode that should be issued by the controller when it is automatically polling for device program completion. This command is issued followed all device write operations. By default this will poll the standard device STATUS.." line.long 0xC "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_no_of_polls_bef_exp_reg,Polling Expiration Register" hexmask.long 0xC 0.--31. 1. "NO_OF_POLLS_BEF_EXP_FLD,Number of polls cycles before expiration" line.long 0x10 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_irq_status_reg,Interrupt Status Register: The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of.." bitfld.long 0x10 19. "ECC_FAIL_FLD,ECC failure This interrupt informs the system that Flash Device reported ECC error." "0,1" newline bitfld.long 0x10 18. "TX_CRC_CHUNK_BRK_FLD,TX CRC chunk was broken This interrupt informs the system that program page SPI transfer was discontinued somewhere inside the chunk." "0,1" newline bitfld.long 0x10 17. "RX_CRC_DATA_VAL_FLD,RX CRC data valid New RX CRC data was captured from Flash Device" "0,1" newline bitfld.long 0x10 16. "RX_CRC_DATA_ERR_FLD,RX CRC data error CRC data from Flash Device does not correspond to the one dynamically calculated by the controller." "0,1" newline bitfld.long 0x10 14. "STIG_REQ_INT_FLD,The controller is ready for getting another STIG request." "0,1" newline bitfld.long 0x10 13. "POLL_EXP_INT_FLD,The maximum number of programmed polls cycles is expired" "0,1" newline bitfld.long 0x10 12. "INDRD_SRAM_FULL_FLD,Indirect Read Partition overflow: Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation" "0,1" newline bitfld.long 0x10 11. "RX_FIFO_FULL_FLD,Small RX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "0: FIFO is not full,1: FIFO is full" newline bitfld.long 0x10 10. "RX_FIFO_NOT_EMPTY_FLD,Small RX FIFO not empty: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has less than RX THRESHOLD entries 1 : FIFO has >= THRESHOLD entries" "0: FIFO has less than RX THRESHOLD entries,1: FIFO has >= THRESHOLD entries" newline bitfld.long 0x10 9. "TX_FIFO_FULL_FLD,Small TX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "0: FIFO is not full,1: FIFO is full" newline bitfld.long 0x10 8. "TX_FIFO_NOT_FULL_FLD,Small TX FIFO not full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has >= THRESHOLD entries 1 : FIFO has less than THRESHOLD entries" "0: FIFO has >= THRESHOLD entries,1: FIFO has less than THRESHOLD entries" newline bitfld.long 0x10 7. "RECV_OVERFLOW_FLD,Receive Overflow: This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX.." "0: no overflow has been detected,1: an overflow has occurred" newline bitfld.long 0x10 6. "INDIRECT_XFER_LEVEL_BREACH_FLD,Indirect Transfer Watermark Level Breached" "0,1" newline bitfld.long 0x10 5. "ILLEGAL_ACCESS_DET_FLD,Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger." "0,1" newline bitfld.long 0x10 4. "PROT_WR_ATTEMPT_FLD,Write to protected area was attempted and rejected." "0,1" newline bitfld.long 0x10 3. "INDIRECT_READ_REJECT_FLD,Indirect operation was requested but could not be accepted. Two indirect operations already in storage." "0,1" newline bitfld.long 0x10 2. "INDIRECT_OP_DONE_FLD,Indirect Operation Complete: Controller has completed last triggered indirect operation" "0,1" newline bitfld.long 0x10 1. "UNDERFLOW_DET_FLD,Underflow Detected: 0 : no underflow has been detected 1 : underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with.." "0: no underflow has been detected,1: underflow is detected and an attempt to transfer.." newline bitfld.long 0x10 0. "MODE_M_FAIL_FLD,Mode M Failure: Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in master mode [multi-master contention]. These conditions will clear the spi_enable bit and disable the SPI." "0: no mode fault has been detected,1: a mode fault has occurred" line.long 0x14 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_irq_mask_reg,Interrupt Mask: 0 : the interrupt for the corresponding interrupt status register bit is disabled." bitfld.long 0x14 19. "ECC_FAIL_MASK_FLD,ECC failure Mask" "0,1" newline bitfld.long 0x14 18. "TX_CRC_CHUNK_BRK_MASK_FLD,TX CRC chunk was broken Mask" "0,1" newline bitfld.long 0x14 17. "RX_CRC_DATA_VAL_MASK_FLD,RX CRC data valid Mask" "0,1" newline bitfld.long 0x14 16. "RX_CRC_DATA_ERR_MASK_FLD,RX CRC data error Mask" "0,1" newline bitfld.long 0x14 14. "STIG_REQ_MASK_FLD,STIG request completion Mask" "0,1" newline bitfld.long 0x14 13. "POLL_EXP_INT_MASK_FLD,Polling expiration detected Mask" "0,1" newline bitfld.long 0x14 12. "INDRD_SRAM_FULL_MASK_FLD,Indirect Read Partition overflow mask" "0,1" newline bitfld.long 0x14 11. "RX_FIFO_FULL_MASK_FLD,Small RX FIFO full Mask" "0,1" newline bitfld.long 0x14 10. "RX_FIFO_NOT_EMPTY_MASK_FLD,Small RX FIFO not empty Mask" "0,1" newline bitfld.long 0x14 9. "TX_FIFO_FULL_MASK_FLD,Small TX FIFO full Mask" "0,1" newline bitfld.long 0x14 8. "TX_FIFO_NOT_FULL_MASK_FLD,Small TX FIFO not full Mask" "0,1" newline bitfld.long 0x14 7. "RECV_OVERFLOW_MASK_FLD,Receive Overflow Mask" "0,1" newline bitfld.long 0x14 6. "INDIRECT_XFER_LEVEL_BREACH_MASK_FLD,Transfer Watermark Breach Mask" "0,1" newline bitfld.long 0x14 5. "ILLEGAL_ACCESS_DET_MASK_FLD,Illegal Access Detected Mask" "0,1" newline bitfld.long 0x14 4. "PROT_WR_ATTEMPT_MASK_FLD,Protected Area Write Attempt Mask" "0,1" newline bitfld.long 0x14 3. "INDIRECT_READ_REJECT_MASK_FLD,Indirect Read Reject Mask" "0,1" newline bitfld.long 0x14 2. "INDIRECT_OP_DONE_MASK_FLD,Indirect Complete Mask" "0,1" newline bitfld.long 0x14 1. "UNDERFLOW_DET_MASK_FLD,Underflow Detected Mask" "0,1" newline bitfld.long 0x14 0. "MODE_M_FAIL_MASK_FLD,Mode M Failure Mask" "0,1" group.long 0x50++0xB line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_lower_wr_prot_reg,Lower Write Protection Register" hexmask.long 0x0 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the lower block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_upper_wr_prot_reg,Upper Write Protection Register" hexmask.long 0x4 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the upper block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_wr_prot_ctrl_reg,Write Protection Control Register" bitfld.long 0x8 1. "ENB_FLD,Write Protection Enable Bit: When set to 1 any AHB write access with an address within the protection region defined in the lower and upper write protection registers is rejected. An AHB error response is generated and an interrupt source.." "0,1" newline bitfld.long 0x8 0. "INV_FLD,Write Protection Inversion Bit: When set to 1 the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to. When set to 0 the protection region.." "0,1" group.long 0x60++0x23 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_ctrl_reg,Indirect Read Transfer Control Register" rbitfld.long 0x0 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field [bit 5]. It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x0 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x0 4. "RD_QUEUED_FLD,Two indirect read operations have been queued" "0,1" newline bitfld.long 0x0 3. "SRAM_FULL_FLD,SRAM Full: SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it.; indirect operation [status]" "0,1" newline rbitfld.long 0x0 2. "RD_STATUS_FLD,Indirect Read Status: Indirect read operation in progress [status]" "0,1" newline bitfld.long 0x0 1. "CANCEL_FLD,Cancel Indirect Read: Writing a 1 to this bit will cancel all ongoing indirect read operations." "0,1" newline bitfld.long 0x0 0. "START_FLD,Start Indirect Read: Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation." "0,1" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_watermark_reg,Indirect Read Transfer Watermark Register" hexmask.long 0x4 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the minimum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level passes the watermark an interrupt is also generated. This field can be disabled by writing a value of all.." line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_start_reg,Indirect Read Transfer Start Address Register" hexmask.long 0x8 0.--31. 1. "ADDR_FLD,This is the start address from which the indirect access will commence its READ operation." line.long 0xC "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_num_bytes_reg,Indirect Read Transfer Number Bytes Register" hexmask.long 0xC 0.--31. 1. "VALUE_FLD,This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x10 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_ctrl_reg,Indirect Write Transfer Control Register" rbitfld.long 0x10 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field [bit 5]. It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x10 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x10 4. "WR_QUEUED_FLD,Two indirect write operations have been queued" "0,1" newline rbitfld.long 0x10 2. "WR_STATUS_FLD,Indirect Write Status: Indirect write operation in progress [status]" "0,1" newline bitfld.long 0x10 1. "CANCEL_FLD,Cancel Indirect Write: Writing a 1 to this bit will cancel all ongoing indirect write operations." "0,1" newline bitfld.long 0x10 0. "START_FLD,Start Indirect Write: Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation." "0,1" line.long 0x14 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_watermark_reg,Indirect Write Transfer Watermark Register" hexmask.long 0x14 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the maximum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level falls below the watermark an interrupt is also generated. This field can be disabled by writing a value.." line.long 0x18 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_start_reg,Indirect Write Transfer Start Address Register" hexmask.long 0x18 0.--31. 1. "ADDR_FLD,Start of Indirect Access: This is the start address from which the indirect access will commence its READ operation." line.long 0x1C "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_num_bytes_reg,Indirect Write Transfer Number Bytes Register" hexmask.long 0x1C 0.--31. 1. "VALUE_FLD,Indirect Number of Bytes: This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x20 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_trigger_addr_range_reg,Indirect Trigger Address Range Register" hexmask.long.byte 0x20 0.--3. 1. "IND_RANGE_WIDTH_FLD,This is the address offset of Indirect Trigger Address Register." group.long 0x8C++0xB line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_command_ctrl_mem_reg,Flash Command Control Memory Register" hexmask.long.word 0x0 20.--28. 1. "MEM_BANK_ADDR_FLD,The address of the Memory Bank which data will be read from." newline bitfld.long 0x0 16.--18. "NB_OF_STIG_READ_BYTES_FLD,It defines the number of read bytes for the extended STIG." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "MEM_BANK_READ_DATA_FLD,Last requested data from the STIG Memory Bank." newline rbitfld.long 0x0 1. "MEM_BANK_REQ_IN_PROGRESS_FLD,Memory Bank data request in progress." "0,1" newline bitfld.long 0x0 0. "TRIGGER_MEM_BANK_REQ_FLD,Trigger the Memory Bank data request." "0,1" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_cmd_ctrl_reg,Flash Command Control Register" hexmask.long.byte 0x4 24.--31. 1. "CMD_OPCODE_FLD,Command Opcode: The command opcode field should be setup before triggering the command. For example 0x20 maps to SubSector Erase. Writing to the execute field [bit 0] of this register launches the command. NOTE : Using this approach to.." newline bitfld.long 0x4 23. "ENB_READ_DATA_FLD,Read Data Enable: Set to 1 if the command specified in the command opcode field [bits 31:24] requires read data bytes to be received from the device." "0,1" newline bitfld.long 0x4 20.--22. "NUM_RD_DATA_BYTES_FLD,Number of Read Data Bytes: Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "ENB_COMD_ADDR_FLD,Command Address Enable: Set to 1 if the command specified in bits 31:24 requires an address. This should be setup before triggering the command via writing a 1 to the execute field." "0,1" newline bitfld.long 0x4 18. "ENB_MODE_BIT_FLD,Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline bitfld.long 0x4 16.--17. "NUM_ADDR_BYTES_FLD,Number of Address Bytes: Set to the number of address bytes required [the address itself is programmed in the FLASH COMMAND ADDRESS REGISTERS]. This should be setup before triggering the command via bit 0 of this register. 2'b00 : 1.." "0: 1 address byte,1: 2 address bytes,2: 3 address bytes,3: 4 address bytes" newline bitfld.long 0x4 15. "ENB_WRITE_DATA_FLD,Write Data Enable: Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device." "0,1" newline bitfld.long 0x4 12.--14. "NUM_WR_DATA_BYTES_FLD,Number of Write Data Bytes: Up to 8 Data bytes may be written using this command Set to 0 for 1 byte 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 7.--11. 1. "NUM_DUMMY_CYCLES_FLD,Number of Dummy cycles: Set to the number of dummy cycles required. This should be setup before triggering the command via the execute field of this register." newline bitfld.long 0x4 2. "STIG_MEM_BANK_EN_FLD,STIG Memory Bank enable bit." "0,1" newline rbitfld.long 0x4 1. "CMD_EXEC_STATUS_FLD,Command execution in progress." "0,1" newline bitfld.long 0x4 0. "CMD_EXEC_FLD,Execute the command." "0,1" line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_cmd_addr_reg,Flash Command Address Register" hexmask.long 0x8 0.--31. 1. "ADDR_FLD,Command Address: This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the address used by the command specified in the opcode field [bits 31:24] of the Flash Command Control.." rgroup.long 0xA0++0x7 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_rd_data_lower_reg,Flash Command Read Data Register (Lower)" hexmask.long 0x0 0.--31. 1. "DATA_FLD,This is the data that is returned by the flash device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_rd_data_upper_reg,Flash Command Read Data Register (Upper)" hexmask.long 0x4 0.--31. 1. "DATA_FLD,This is the data that is returned by the FLASH device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." group.long 0xA8++0x13 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_wr_data_lower_reg,Flash Command Write Data Register (Lower)" hexmask.long 0x0 0.--31. 1. "DATA_FLD,Command Write Data Lower Byte: This is the command write data lower byte. This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_wr_data_upper_reg,Flash Command Write Data Register (Upper)" hexmask.long 0x4 0.--31. 1. "DATA_FLD,Command Write Data Upper Byte: This is the command write data upper byte. This should be setup before triggering the command with execute field [bit 0] of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_polling_flash_status_reg,Polling Flash Status Register" hexmask.long.byte 0x8 16.--19. 1. "DEVICE_STATUS_NB_DUMMY,Number of dummy cycles for auto-polling" newline rbitfld.long 0x8 8. "DEVICE_STATUS_VALID_FLD,Device Status Valid: This should be set when value in bits from 7 to 0 is valid." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "DEVICE_STATUS_FLD,Defines actual Status Register of Device" line.long 0xC "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_phy_configuration_reg,PHY Configuration Register" bitfld.long 0xC 31. "PHY_CONFIG_RESYNC_FLD,This bit is used for re-synchronisation delay lines to update them with values from TX DLL Delay and RX DLL Delay fields." "0,1" newline bitfld.long 0xC 30. "PHY_CONFIG_RESET_FLD,DLL Reset bit: This bit is used for reset of Delay Lines by software." "0,1" newline bitfld.long 0xC 29. "PHY_CONFIG_RX_DLL_BYPASS_FLD,RX DLL Bypass: This field determines id RX DLL is bypassed." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "PHY_CONFIG_TX_DLL_DELAY_FLD,TX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and spi_clk." newline hexmask.long.byte 0xC 0.--6. 1. "PHY_CONFIG_RX_DLL_DELAY_FLD,RX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and rx_dll_clk." line.long 0x10 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_phy_master_control_reg,PHY DLL Master Control Register" bitfld.long 0x10 24. "PHY_MASTER_LOCK_MODE_FLD,Determines if the master delay line locks on a full cycle or half cycle of delay." "0,1" newline bitfld.long 0x10 23. "PHY_MASTER_BYPASS_MODE_FLD,Controls the bypass mode of the master and slave DLLs." "0,1" newline bitfld.long 0x10 20.--22. "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD,Selects the number of delay elements to be inserted between the phase detect flip-flops." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 16.--18. "PHY_MASTER_NB_INDICATIONS_FLD,Holds the number of consecutive increment or decrement indications." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--6. 1. "PHY_MASTER_INITIAL_DELAY_FLD,This value is the initial delay value for the DLL." rgroup.long 0xBC++0x7 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dll_observable_lower_reg,DLL Observable Register Lower" hexmask.long.byte 0x0 24.--31. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD,Holds the state of the cumulative dll_lock_inc register." newline hexmask.long.byte 0x0 16.--23. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD,Holds the state of the cumulative dll_lock_dec register." newline bitfld.long 0x0 15. "DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD,This bit indicates that lock of loopback is done." "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD,Reports the DLL encoder value from the master DLL to the slave DLLs." newline hexmask.long.byte 0x0 3.--7. 1. "DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD,Reports the number of increments or decrements required for the master DLL to complete the locking process." newline bitfld.long 0x0 1.--2. "DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD,Defines the mode in which the DLL has achieved the lock." "0,1,2,3" newline bitfld.long 0x0 0. "DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD,Indicates status of DLL." "0,1" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dll_observable_upper_reg,DLL Observable Register Upper" hexmask.long.byte 0x4 16.--22. 1. "DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD,Holds the encoded value for the TX delay line for this slice." newline hexmask.long.byte 0x4 0.--6. 1. "DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD,Holds the encoded value for the RX delay line for this slice." group.long 0xE0++0x7 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_lower_reg,Opcode Extension Register (Lower)" hexmask.long.byte 0x0 24.--31. 1. "EXT_READ_OPCODE_FLD,Supplement byte of any Read Opcode" newline hexmask.long.byte 0x0 16.--23. 1. "EXT_WRITE_OPCODE_FLD,Supplement byte of any Write Opcode" newline hexmask.long.byte 0x0 8.--15. 1. "EXT_POLL_OPCODE_FLD,Supplement byte of any Polling Opcode" newline hexmask.long.byte 0x0 0.--7. 1. "EXT_STIG_OPCODE_FLD,Supplement byte of any STIG Opcode" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_upper_reg,Opcode Extension Register (Upper)" hexmask.long.byte 0x4 24.--31. 1. "WEL_OPCODE_FLD,First byte of any WEL Opcode" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_WEL_OPCODE_FLD,Supplement byte of any WEL Opcode" rgroup.long 0xFC++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_module_id_reg,Module ID Register" hexmask.long.byte 0x0 24.--31. 1. "FIX_PATCH_FLD,Fix/path number related to revision described by 3 LSBs of this register" newline hexmask.long.word 0x0 8.--23. 1. "MODULE_ID_FLD,Module/Revision ID number" newline bitfld.long 0x0 0.--1. "CONF_FLD,Configuration ID number: 0 : OCTAL + PHY Configuration 1 : OCTAL Configuration 2 : QUAD + PHY Configuration 3 : QUAD Configuration" "0: OCTAL + PHY Configuration,1: OCTAL Configuration,2: QUAD + PHY Configuration,3: QUAD Configuration" tree.end tree "FSS0_OSPI_0_OSPI0_ECC_AGGR" base ad:0x716000 rgroup.long 0x0++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" group.long 0x200++0xF line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "FSS0_OSPI_0_OSPI0_SS_CFG" base ad:0xFC44000 rgroup.long 0x0++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_CTRL,The Control Register contains general control bits for the ospi" bitfld.long 0x0 3. "PIPELINE_MODE_FLUSH,1 - Flush Cadence Flash Controller FIFO by forcin gAHB SEL low. 0 - AHB Sel to Cadence Controller is 1" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_STAT,The Status register provide general status bits for the ospi" bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0x20++0x3 line.long 0x0 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targetted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" tree.end tree.end tree "GICSS0" base ad:0x0 tree "GICSS0_GIC" base ad:0x1800000 group.long 0x0++0xB line.long 0x0 "GIC_REGS_Distributor__1_GICD_CTLR,GICD_CTLR" bitfld.long 0x0 31. "DISTRIBUTOR__1_GICD_CTLR__31_1,Register Write Pending" "0,1" newline bitfld.long 0x0 6. "DISTRIBUTOR__1_GICD_CTLR__6_1,S: DS" "0,1" newline bitfld.long 0x0 5. "DISTRIBUTOR__1_GICD_CTLR__5_1,S: ARE_NS" "0,1" newline bitfld.long 0x0 4. "DISTRIBUTOR__1_GICD_CTLR__4_1,NS: ARE_NS S: ARE_S" "0,1" newline bitfld.long 0x0 2. "DISTRIBUTOR__1_GICD_CTLR__2_1,S: EnableGrp1_S" "0,1" newline bitfld.long 0x0 1. "DISTRIBUTOR__1_GICD_CTLR__1_1,NS: EnableGrp1A S: EnableGrp1_NS" "0,1" newline bitfld.long 0x0 0. "DISTRIBUTOR__1_GICD_CTLR__0_1,NS: EnableGrp1 S: EnableGrp0" "0,1" line.long 0x4 "GIC_REGS_Distributor__3_GICD_TYPER,GICD_TYPER" bitfld.long 0x4 24. "DISTRIBUTOR__3_GICD_TYPER__24_1,A3V" "0,1" newline hexmask.long.byte 0x4 19.--23. 1. "DISTRIBUTOR__3_GICD_TYPER__19_5,IDbits" newline bitfld.long 0x4 18. "DISTRIBUTOR__3_GICD_TYPER__18_1,DVIS" "0,1" newline bitfld.long 0x4 17. "DISTRIBUTOR__3_GICD_TYPER__17_1,LPIS" "0,1" newline bitfld.long 0x4 16. "DISTRIBUTOR__3_GICD_TYPER__16_1,MBIS" "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "DISTRIBUTOR__3_GICD_TYPER__11_5,LSPI" newline bitfld.long 0x4 10. "DISTRIBUTOR__3_GICD_TYPER__10_1,SecurityExtn" "0,1" newline bitfld.long 0x4 5.--7. "DISTRIBUTOR__3_GICD_TYPER__5_3,CPUNumber" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--4. 1. "DISTRIBUTOR__3_GICD_TYPER__0_5,ITLinesNumber" line.long 0x8 "GIC_REGS_Distributor__4_GICD_IIDR,GICD_IIDR" hexmask.long.byte 0x8 24.--31. 1. "DISTRIBUTOR__4_GICD_IIDR__24_8,ProductID" newline hexmask.long.byte 0x8 16.--19. 1. "DISTRIBUTOR__4_GICD_IIDR__16_4,Variant" newline hexmask.long.byte 0x8 12.--15. 1. "DISTRIBUTOR__4_GICD_IIDR__12_4,Revision" newline hexmask.long.word 0x8 0.--11. 1. "DISTRIBUTOR__4_GICD_IIDR__0_12,Implementer" group.long 0x40++0x3 line.long 0x0 "GIC_REGS_Distributor__5_GICD_SETSPI_NSR,GICD_SETSPI_NSR" hexmask.long.word 0x0 0.--9. 1. "DISTRIBUTOR__5_GICD_SETSPI_NSR__0_10,SPI ID" group.long 0x48++0x3 line.long 0x0 "GIC_REGS_Distributor__6_GICD_CLRSPI_NSR,GICD_CLRSPI_NSR" hexmask.long.word 0x0 0.--9. 1. "DISTRIBUTOR__6_GICD_CLRSPI_NSR__0_10,SPI ID" group.long 0x50++0x3 line.long 0x0 "GIC_REGS_Distributor__7_GICD_SETSPI_SR,GICD_SETSPI_SR" hexmask.long.word 0x0 0.--9. 1. "DISTRIBUTOR__7_GICD_SETSPI_SR__0_10,SPI ID" group.long 0x58++0x3 line.long 0x0 "GIC_REGS_Distributor__8_GICD_CLRSPI_SR,GICD_CLRSPI_SR" hexmask.long.word 0x0 0.--9. 1. "DISTRIBUTOR__8_GICD_CLRSPI_SR__0_10,SPI ID" group.long 0x80++0x23 line.long 0x0 "GIC_REGS_Distributor__9_GICD_IGROUPR0,GICD_IGROUPR0" line.long 0x4 "GIC_REGS_Distributor__10_GICD_IGROUPR1,GICD_IGROUPR1" line.long 0x8 "GIC_REGS_Distributor__10_GICD_IGROUPR2,GICD_IGROUPR2" line.long 0xC "GIC_REGS_Distributor__10_GICD_IGROUPR3,GICD_IGROUPR3" line.long 0x10 "GIC_REGS_Distributor__10_GICD_IGROUPR4,GICD_IGROUPR4" line.long 0x14 "GIC_REGS_Distributor__10_GICD_IGROUPR5,GICD_IGROUPR5" line.long 0x18 "GIC_REGS_Distributor__10_GICD_IGROUPR6,GICD_IGROUPR6" line.long 0x1C "GIC_REGS_Distributor__10_GICD_IGROUPR7,GICD_IGROUPR7" line.long 0x20 "GIC_REGS_Distributor__10_GICD_IGROUPR8,GICD_IGROUPR8" group.long 0x104++0x1F line.long 0x0 "GIC_REGS_Distributor__12_GICD_ISENABLER1,GICD_ISENABLER1" line.long 0x4 "GIC_REGS_Distributor__12_GICD_ISENABLER2,GICD_ISENABLER2" line.long 0x8 "GIC_REGS_Distributor__12_GICD_ISENABLER3,GICD_ISENABLER3" line.long 0xC "GIC_REGS_Distributor__12_GICD_ISENABLER4,GICD_ISENABLER4" line.long 0x10 "GIC_REGS_Distributor__12_GICD_ISENABLER5,GICD_ISENABLER5" line.long 0x14 "GIC_REGS_Distributor__12_GICD_ISENABLER6,GICD_ISENABLER6" line.long 0x18 "GIC_REGS_Distributor__12_GICD_ISENABLER7,GICD_ISENABLER7" line.long 0x1C "GIC_REGS_Distributor__12_GICD_ISENABLER8,GICD_ISENABLER8" group.long 0x184++0x1F line.long 0x0 "GIC_REGS_Distributor__14_GICD_ICENABLER1,GICD_ICENABLER1" line.long 0x4 "GIC_REGS_Distributor__14_GICD_ICENABLER2,GICD_ICENABLER2" line.long 0x8 "GIC_REGS_Distributor__14_GICD_ICENABLER3,GICD_ICENABLER3" line.long 0xC "GIC_REGS_Distributor__14_GICD_ICENABLER4,GICD_ICENABLER4" line.long 0x10 "GIC_REGS_Distributor__14_GICD_ICENABLER5,GICD_ICENABLER5" line.long 0x14 "GIC_REGS_Distributor__14_GICD_ICENABLER6,GICD_ICENABLER6" line.long 0x18 "GIC_REGS_Distributor__14_GICD_ICENABLER7,GICD_ICENABLER7" line.long 0x1C "GIC_REGS_Distributor__14_GICD_ICENABLER8,GICD_ICENABLER8" group.long 0x204++0x1F line.long 0x0 "GIC_REGS_Distributor__16_GICD_ISPENDR1,GICD_ISPENDR1" line.long 0x4 "GIC_REGS_Distributor__16_GICD_ISPENDR2,GICD_ISPENDR2" line.long 0x8 "GIC_REGS_Distributor__16_GICD_ISPENDR3,GICD_ISPENDR3" line.long 0xC "GIC_REGS_Distributor__16_GICD_ISPENDR4,GICD_ISPENDR4" line.long 0x10 "GIC_REGS_Distributor__16_GICD_ISPENDR5,GICD_ISPENDR5" line.long 0x14 "GIC_REGS_Distributor__16_GICD_ISPENDR6,GICD_ISPENDR6" line.long 0x18 "GIC_REGS_Distributor__16_GICD_ISPENDR7,GICD_ISPENDR7" line.long 0x1C "GIC_REGS_Distributor__16_GICD_ISPENDR8,GICD_ISPENDR8" group.long 0x284++0x1F line.long 0x0 "GIC_REGS_Distributor__18_GICD_ICPENDR1,GICD_ICPENDR1" line.long 0x4 "GIC_REGS_Distributor__18_GICD_ICPENDR2,GICD_ICPENDR2" line.long 0x8 "GIC_REGS_Distributor__18_GICD_ICPENDR3,GICD_ICPENDR3" line.long 0xC "GIC_REGS_Distributor__18_GICD_ICPENDR4,GICD_ICPENDR4" line.long 0x10 "GIC_REGS_Distributor__18_GICD_ICPENDR5,GICD_ICPENDR5" line.long 0x14 "GIC_REGS_Distributor__18_GICD_ICPENDR6,GICD_ICPENDR6" line.long 0x18 "GIC_REGS_Distributor__18_GICD_ICPENDR7,GICD_ICPENDR7" line.long 0x1C "GIC_REGS_Distributor__18_GICD_ICPENDR8,GICD_ICPENDR8" group.long 0x304++0x1F line.long 0x0 "GIC_REGS_Distributor__20_GICD_ISACTIVER1,GICD_ISACTIVER1" line.long 0x4 "GIC_REGS_Distributor__20_GICD_ISACTIVER2,GICD_ISACTIVER2" line.long 0x8 "GIC_REGS_Distributor__20_GICD_ISACTIVER3,GICD_ISACTIVER3" line.long 0xC "GIC_REGS_Distributor__20_GICD_ISACTIVER4,GICD_ISACTIVER4" line.long 0x10 "GIC_REGS_Distributor__20_GICD_ISACTIVER5,GICD_ISACTIVER5" line.long 0x14 "GIC_REGS_Distributor__20_GICD_ISACTIVER6,GICD_ISACTIVER6" line.long 0x18 "GIC_REGS_Distributor__20_GICD_ISACTIVER7,GICD_ISACTIVER7" line.long 0x1C "GIC_REGS_Distributor__20_GICD_ISACTIVER8,GICD_ISACTIVER8" group.long 0x384++0x1F line.long 0x0 "GIC_REGS_Distributor__22_GICD_ICACTIVER1,GICD_ICACTIVER1" line.long 0x4 "GIC_REGS_Distributor__22_GICD_ICACTIVER2,GICD_ICACTIVER2" line.long 0x8 "GIC_REGS_Distributor__22_GICD_ICACTIVER3,GICD_ICACTIVER3" line.long 0xC "GIC_REGS_Distributor__22_GICD_ICACTIVER4,GICD_ICACTIVER4" line.long 0x10 "GIC_REGS_Distributor__22_GICD_ICACTIVER5,GICD_ICACTIVER5" line.long 0x14 "GIC_REGS_Distributor__22_GICD_ICACTIVER6,GICD_ICACTIVER6" line.long 0x18 "GIC_REGS_Distributor__22_GICD_ICACTIVER7,GICD_ICACTIVER7" line.long 0x1C "GIC_REGS_Distributor__22_GICD_ICACTIVER8,GICD_ICACTIVER8" group.long 0x420++0xFF line.long 0x0 "GIC_REGS_Distributor__24_GICD_IPRIORITYR8,GICD_IPRIORITYR8" line.long 0x4 "GIC_REGS_Distributor__24_GICD_IPRIORITYR9,GICD_IPRIORITYR9" line.long 0x8 "GIC_REGS_Distributor__24_GICD_IPRIORITYR10,GICD_IPRIORITYR10" line.long 0xC "GIC_REGS_Distributor__24_GICD_IPRIORITYR11,GICD_IPRIORITYR11" line.long 0x10 "GIC_REGS_Distributor__24_GICD_IPRIORITYR12,GICD_IPRIORITYR12" line.long 0x14 "GIC_REGS_Distributor__24_GICD_IPRIORITYR13,GICD_IPRIORITYR13" line.long 0x18 "GIC_REGS_Distributor__24_GICD_IPRIORITYR14,GICD_IPRIORITYR14" line.long 0x1C "GIC_REGS_Distributor__24_GICD_IPRIORITYR15,GICD_IPRIORITYR15" line.long 0x20 "GIC_REGS_Distributor__24_GICD_IPRIORITYR16,GICD_IPRIORITYR16" line.long 0x24 "GIC_REGS_Distributor__24_GICD_IPRIORITYR17,GICD_IPRIORITYR17" line.long 0x28 "GIC_REGS_Distributor__24_GICD_IPRIORITYR18,GICD_IPRIORITYR18" line.long 0x2C "GIC_REGS_Distributor__24_GICD_IPRIORITYR19,GICD_IPRIORITYR19" line.long 0x30 "GIC_REGS_Distributor__24_GICD_IPRIORITYR20,GICD_IPRIORITYR20" line.long 0x34 "GIC_REGS_Distributor__24_GICD_IPRIORITYR21,GICD_IPRIORITYR21" line.long 0x38 "GIC_REGS_Distributor__24_GICD_IPRIORITYR22,GICD_IPRIORITYR22" line.long 0x3C "GIC_REGS_Distributor__24_GICD_IPRIORITYR23,GICD_IPRIORITYR23" line.long 0x40 "GIC_REGS_Distributor__24_GICD_IPRIORITYR24,GICD_IPRIORITYR24" line.long 0x44 "GIC_REGS_Distributor__24_GICD_IPRIORITYR25,GICD_IPRIORITYR25" line.long 0x48 "GIC_REGS_Distributor__24_GICD_IPRIORITYR26,GICD_IPRIORITYR26" line.long 0x4C "GIC_REGS_Distributor__24_GICD_IPRIORITYR27,GICD_IPRIORITYR27" line.long 0x50 "GIC_REGS_Distributor__24_GICD_IPRIORITYR28,GICD_IPRIORITYR28" line.long 0x54 "GIC_REGS_Distributor__24_GICD_IPRIORITYR29,GICD_IPRIORITYR29" line.long 0x58 "GIC_REGS_Distributor__24_GICD_IPRIORITYR30,GICD_IPRIORITYR30" line.long 0x5C "GIC_REGS_Distributor__24_GICD_IPRIORITYR31,GICD_IPRIORITYR31" line.long 0x60 "GIC_REGS_Distributor__24_GICD_IPRIORITYR32,GICD_IPRIORITYR32" line.long 0x64 "GIC_REGS_Distributor__24_GICD_IPRIORITYR33,GICD_IPRIORITYR33" line.long 0x68 "GIC_REGS_Distributor__24_GICD_IPRIORITYR34,GICD_IPRIORITYR34" line.long 0x6C "GIC_REGS_Distributor__24_GICD_IPRIORITYR35,GICD_IPRIORITYR35" line.long 0x70 "GIC_REGS_Distributor__24_GICD_IPRIORITYR36,GICD_IPRIORITYR36" line.long 0x74 "GIC_REGS_Distributor__24_GICD_IPRIORITYR37,GICD_IPRIORITYR37" line.long 0x78 "GIC_REGS_Distributor__24_GICD_IPRIORITYR38,GICD_IPRIORITYR38" line.long 0x7C "GIC_REGS_Distributor__24_GICD_IPRIORITYR39,GICD_IPRIORITYR39" line.long 0x80 "GIC_REGS_Distributor__24_GICD_IPRIORITYR40,GICD_IPRIORITYR40" line.long 0x84 "GIC_REGS_Distributor__24_GICD_IPRIORITYR41,GICD_IPRIORITYR41" line.long 0x88 "GIC_REGS_Distributor__24_GICD_IPRIORITYR42,GICD_IPRIORITYR42" line.long 0x8C "GIC_REGS_Distributor__24_GICD_IPRIORITYR43,GICD_IPRIORITYR43" line.long 0x90 "GIC_REGS_Distributor__24_GICD_IPRIORITYR44,GICD_IPRIORITYR44" line.long 0x94 "GIC_REGS_Distributor__24_GICD_IPRIORITYR45,GICD_IPRIORITYR45" line.long 0x98 "GIC_REGS_Distributor__24_GICD_IPRIORITYR46,GICD_IPRIORITYR46" line.long 0x9C "GIC_REGS_Distributor__24_GICD_IPRIORITYR47,GICD_IPRIORITYR47" line.long 0xA0 "GIC_REGS_Distributor__24_GICD_IPRIORITYR48,GICD_IPRIORITYR48" line.long 0xA4 "GIC_REGS_Distributor__24_GICD_IPRIORITYR49,GICD_IPRIORITYR49" line.long 0xA8 "GIC_REGS_Distributor__24_GICD_IPRIORITYR50,GICD_IPRIORITYR50" line.long 0xAC "GIC_REGS_Distributor__24_GICD_IPRIORITYR51,GICD_IPRIORITYR51" line.long 0xB0 "GIC_REGS_Distributor__24_GICD_IPRIORITYR52,GICD_IPRIORITYR52" line.long 0xB4 "GIC_REGS_Distributor__24_GICD_IPRIORITYR53,GICD_IPRIORITYR53" line.long 0xB8 "GIC_REGS_Distributor__24_GICD_IPRIORITYR54,GICD_IPRIORITYR54" line.long 0xBC "GIC_REGS_Distributor__24_GICD_IPRIORITYR55,GICD_IPRIORITYR55" line.long 0xC0 "GIC_REGS_Distributor__24_GICD_IPRIORITYR56,GICD_IPRIORITYR56" line.long 0xC4 "GIC_REGS_Distributor__24_GICD_IPRIORITYR57,GICD_IPRIORITYR57" line.long 0xC8 "GIC_REGS_Distributor__24_GICD_IPRIORITYR58,GICD_IPRIORITYR58" line.long 0xCC "GIC_REGS_Distributor__24_GICD_IPRIORITYR59,GICD_IPRIORITYR59" line.long 0xD0 "GIC_REGS_Distributor__24_GICD_IPRIORITYR60,GICD_IPRIORITYR60" line.long 0xD4 "GIC_REGS_Distributor__24_GICD_IPRIORITYR61,GICD_IPRIORITYR61" line.long 0xD8 "GIC_REGS_Distributor__24_GICD_IPRIORITYR62,GICD_IPRIORITYR62" line.long 0xDC "GIC_REGS_Distributor__24_GICD_IPRIORITYR63,GICD_IPRIORITYR63" line.long 0xE0 "GIC_REGS_Distributor__24_GICD_IPRIORITYR64,GICD_IPRIORITYR64" line.long 0xE4 "GIC_REGS_Distributor__24_GICD_IPRIORITYR65,GICD_IPRIORITYR65" line.long 0xE8 "GIC_REGS_Distributor__24_GICD_IPRIORITYR66,GICD_IPRIORITYR66" line.long 0xEC "GIC_REGS_Distributor__24_GICD_IPRIORITYR67,GICD_IPRIORITYR67" line.long 0xF0 "GIC_REGS_Distributor__24_GICD_IPRIORITYR68,GICD_IPRIORITYR68" line.long 0xF4 "GIC_REGS_Distributor__24_GICD_IPRIORITYR69,GICD_IPRIORITYR69" line.long 0xF8 "GIC_REGS_Distributor__24_GICD_IPRIORITYR70,GICD_IPRIORITYR70" line.long 0xFC "GIC_REGS_Distributor__24_GICD_IPRIORITYR71,GICD_IPRIORITYR71" group.long 0x820++0xFF line.long 0x0 "GIC_REGS_Distributor__26_GICD_ITARGETSR8,GICD_ITARGETSR8" line.long 0x4 "GIC_REGS_Distributor__26_GICD_ITARGETSR9,GICD_ITARGETSR9" line.long 0x8 "GIC_REGS_Distributor__26_GICD_ITARGETSR10,GICD_ITARGETSR10" line.long 0xC "GIC_REGS_Distributor__26_GICD_ITARGETSR11,GICD_ITARGETSR11" line.long 0x10 "GIC_REGS_Distributor__26_GICD_ITARGETSR12,GICD_ITARGETSR12" line.long 0x14 "GIC_REGS_Distributor__26_GICD_ITARGETSR13,GICD_ITARGETSR13" line.long 0x18 "GIC_REGS_Distributor__26_GICD_ITARGETSR14,GICD_ITARGETSR14" line.long 0x1C "GIC_REGS_Distributor__26_GICD_ITARGETSR15,GICD_ITARGETSR15" line.long 0x20 "GIC_REGS_Distributor__26_GICD_ITARGETSR16,GICD_ITARGETSR16" line.long 0x24 "GIC_REGS_Distributor__26_GICD_ITARGETSR17,GICD_ITARGETSR17" line.long 0x28 "GIC_REGS_Distributor__26_GICD_ITARGETSR18,GICD_ITARGETSR18" line.long 0x2C "GIC_REGS_Distributor__26_GICD_ITARGETSR19,GICD_ITARGETSR19" line.long 0x30 "GIC_REGS_Distributor__26_GICD_ITARGETSR20,GICD_ITARGETSR20" line.long 0x34 "GIC_REGS_Distributor__26_GICD_ITARGETSR21,GICD_ITARGETSR21" line.long 0x38 "GIC_REGS_Distributor__26_GICD_ITARGETSR22,GICD_ITARGETSR22" line.long 0x3C "GIC_REGS_Distributor__26_GICD_ITARGETSR23,GICD_ITARGETSR23" line.long 0x40 "GIC_REGS_Distributor__26_GICD_ITARGETSR24,GICD_ITARGETSR24" line.long 0x44 "GIC_REGS_Distributor__26_GICD_ITARGETSR25,GICD_ITARGETSR25" line.long 0x48 "GIC_REGS_Distributor__26_GICD_ITARGETSR26,GICD_ITARGETSR26" line.long 0x4C "GIC_REGS_Distributor__26_GICD_ITARGETSR27,GICD_ITARGETSR27" line.long 0x50 "GIC_REGS_Distributor__26_GICD_ITARGETSR28,GICD_ITARGETSR28" line.long 0x54 "GIC_REGS_Distributor__26_GICD_ITARGETSR29,GICD_ITARGETSR29" line.long 0x58 "GIC_REGS_Distributor__26_GICD_ITARGETSR30,GICD_ITARGETSR30" line.long 0x5C "GIC_REGS_Distributor__26_GICD_ITARGETSR31,GICD_ITARGETSR31" line.long 0x60 "GIC_REGS_Distributor__26_GICD_ITARGETSR32,GICD_ITARGETSR32" line.long 0x64 "GIC_REGS_Distributor__26_GICD_ITARGETSR33,GICD_ITARGETSR33" line.long 0x68 "GIC_REGS_Distributor__26_GICD_ITARGETSR34,GICD_ITARGETSR34" line.long 0x6C "GIC_REGS_Distributor__26_GICD_ITARGETSR35,GICD_ITARGETSR35" line.long 0x70 "GIC_REGS_Distributor__26_GICD_ITARGETSR36,GICD_ITARGETSR36" line.long 0x74 "GIC_REGS_Distributor__26_GICD_ITARGETSR37,GICD_ITARGETSR37" line.long 0x78 "GIC_REGS_Distributor__26_GICD_ITARGETSR38,GICD_ITARGETSR38" line.long 0x7C "GIC_REGS_Distributor__26_GICD_ITARGETSR39,GICD_ITARGETSR39" line.long 0x80 "GIC_REGS_Distributor__26_GICD_ITARGETSR40,GICD_ITARGETSR40" line.long 0x84 "GIC_REGS_Distributor__26_GICD_ITARGETSR41,GICD_ITARGETSR41" line.long 0x88 "GIC_REGS_Distributor__26_GICD_ITARGETSR42,GICD_ITARGETSR42" line.long 0x8C "GIC_REGS_Distributor__26_GICD_ITARGETSR43,GICD_ITARGETSR43" line.long 0x90 "GIC_REGS_Distributor__26_GICD_ITARGETSR44,GICD_ITARGETSR44" line.long 0x94 "GIC_REGS_Distributor__26_GICD_ITARGETSR45,GICD_ITARGETSR45" line.long 0x98 "GIC_REGS_Distributor__26_GICD_ITARGETSR46,GICD_ITARGETSR46" line.long 0x9C "GIC_REGS_Distributor__26_GICD_ITARGETSR47,GICD_ITARGETSR47" line.long 0xA0 "GIC_REGS_Distributor__26_GICD_ITARGETSR48,GICD_ITARGETSR48" line.long 0xA4 "GIC_REGS_Distributor__26_GICD_ITARGETSR49,GICD_ITARGETSR49" line.long 0xA8 "GIC_REGS_Distributor__26_GICD_ITARGETSR50,GICD_ITARGETSR50" line.long 0xAC "GIC_REGS_Distributor__26_GICD_ITARGETSR51,GICD_ITARGETSR51" line.long 0xB0 "GIC_REGS_Distributor__26_GICD_ITARGETSR52,GICD_ITARGETSR52" line.long 0xB4 "GIC_REGS_Distributor__26_GICD_ITARGETSR53,GICD_ITARGETSR53" line.long 0xB8 "GIC_REGS_Distributor__26_GICD_ITARGETSR54,GICD_ITARGETSR54" line.long 0xBC "GIC_REGS_Distributor__26_GICD_ITARGETSR55,GICD_ITARGETSR55" line.long 0xC0 "GIC_REGS_Distributor__26_GICD_ITARGETSR56,GICD_ITARGETSR56" line.long 0xC4 "GIC_REGS_Distributor__26_GICD_ITARGETSR57,GICD_ITARGETSR57" line.long 0xC8 "GIC_REGS_Distributor__26_GICD_ITARGETSR58,GICD_ITARGETSR58" line.long 0xCC "GIC_REGS_Distributor__26_GICD_ITARGETSR59,GICD_ITARGETSR59" line.long 0xD0 "GIC_REGS_Distributor__26_GICD_ITARGETSR60,GICD_ITARGETSR60" line.long 0xD4 "GIC_REGS_Distributor__26_GICD_ITARGETSR61,GICD_ITARGETSR61" line.long 0xD8 "GIC_REGS_Distributor__26_GICD_ITARGETSR62,GICD_ITARGETSR62" line.long 0xDC "GIC_REGS_Distributor__26_GICD_ITARGETSR63,GICD_ITARGETSR63" line.long 0xE0 "GIC_REGS_Distributor__26_GICD_ITARGETSR64,GICD_ITARGETSR64" line.long 0xE4 "GIC_REGS_Distributor__26_GICD_ITARGETSR65,GICD_ITARGETSR65" line.long 0xE8 "GIC_REGS_Distributor__26_GICD_ITARGETSR66,GICD_ITARGETSR66" line.long 0xEC "GIC_REGS_Distributor__26_GICD_ITARGETSR67,GICD_ITARGETSR67" line.long 0xF0 "GIC_REGS_Distributor__26_GICD_ITARGETSR68,GICD_ITARGETSR68" line.long 0xF4 "GIC_REGS_Distributor__26_GICD_ITARGETSR69,GICD_ITARGETSR69" line.long 0xF8 "GIC_REGS_Distributor__26_GICD_ITARGETSR70,GICD_ITARGETSR70" line.long 0xFC "GIC_REGS_Distributor__26_GICD_ITARGETSR71,GICD_ITARGETSR71" group.long 0xC08++0x3F line.long 0x0 "GIC_REGS_Distributor__29_GICD_ICFGR2,GICD_ICFGR2" line.long 0x4 "GIC_REGS_Distributor__29_GICD_ICFGR3,GICD_ICFGR3" line.long 0x8 "GIC_REGS_Distributor__29_GICD_ICFGR4,GICD_ICFGR4" line.long 0xC "GIC_REGS_Distributor__29_GICD_ICFGR5,GICD_ICFGR5" line.long 0x10 "GIC_REGS_Distributor__29_GICD_ICFGR6,GICD_ICFGR6" line.long 0x14 "GIC_REGS_Distributor__29_GICD_ICFGR7,GICD_ICFGR7" line.long 0x18 "GIC_REGS_Distributor__29_GICD_ICFGR8,GICD_ICFGR8" line.long 0x1C "GIC_REGS_Distributor__29_GICD_ICFGR9,GICD_ICFGR9" line.long 0x20 "GIC_REGS_Distributor__29_GICD_ICFGR10,GICD_ICFGR10" line.long 0x24 "GIC_REGS_Distributor__29_GICD_ICFGR11,GICD_ICFGR11" line.long 0x28 "GIC_REGS_Distributor__29_GICD_ICFGR12,GICD_ICFGR12" line.long 0x2C "GIC_REGS_Distributor__29_GICD_ICFGR13,GICD_ICFGR13" line.long 0x30 "GIC_REGS_Distributor__29_GICD_ICFGR14,GICD_ICFGR14" line.long 0x34 "GIC_REGS_Distributor__29_GICD_ICFGR15,GICD_ICFGR15" line.long 0x38 "GIC_REGS_Distributor__29_GICD_ICFGR16,GICD_ICFGR16" line.long 0x3C "GIC_REGS_Distributor__29_GICD_ICFGR17,GICD_ICFGR17" group.long 0xD00++0x23 line.long 0x0 "GIC_REGS_Distributor__30_GICD_IGRPMODR0,GICD_IGRPMODR0" line.long 0x4 "GIC_REGS_Distributor__31_GICD_IGRPMODR1,GICD_IGRPMODR1" line.long 0x8 "GIC_REGS_Distributor__31_GICD_IGRPMODR2,GICD_IGRPMODR2" line.long 0xC "GIC_REGS_Distributor__31_GICD_IGRPMODR3,GICD_IGRPMODR3" line.long 0x10 "GIC_REGS_Distributor__31_GICD_IGRPMODR4,GICD_IGRPMODR4" line.long 0x14 "GIC_REGS_Distributor__31_GICD_IGRPMODR5,GICD_IGRPMODR5" line.long 0x18 "GIC_REGS_Distributor__31_GICD_IGRPMODR6,GICD_IGRPMODR6" line.long 0x1C "GIC_REGS_Distributor__31_GICD_IGRPMODR7,GICD_IGRPMODR7" line.long 0x20 "GIC_REGS_Distributor__31_GICD_IGRPMODR8,GICD_IGRPMODR8" group.long 0xE00++0x47 line.long 0x0 "GIC_REGS_Distributor__32_GICD_NSACR0,GICD_NSACR0" line.long 0x4 "GIC_REGS_Distributor__32_GICD_NSACR1,GICD_NSACR1" line.long 0x8 "GIC_REGS_Distributor__33_GICD_NSACR2,GICD_NSACR2" line.long 0xC "GIC_REGS_Distributor__33_GICD_NSACR3,GICD_NSACR3" line.long 0x10 "GIC_REGS_Distributor__33_GICD_NSACR4,GICD_NSACR4" line.long 0x14 "GIC_REGS_Distributor__33_GICD_NSACR5,GICD_NSACR5" line.long 0x18 "GIC_REGS_Distributor__33_GICD_NSACR6,GICD_NSACR6" line.long 0x1C "GIC_REGS_Distributor__33_GICD_NSACR7,GICD_NSACR7" line.long 0x20 "GIC_REGS_Distributor__33_GICD_NSACR8,GICD_NSACR8" line.long 0x24 "GIC_REGS_Distributor__33_GICD_NSACR9,GICD_NSACR9" line.long 0x28 "GIC_REGS_Distributor__33_GICD_NSACR10,GICD_NSACR10" line.long 0x2C "GIC_REGS_Distributor__33_GICD_NSACR11,GICD_NSACR11" line.long 0x30 "GIC_REGS_Distributor__33_GICD_NSACR12,GICD_NSACR12" line.long 0x34 "GIC_REGS_Distributor__33_GICD_NSACR13,GICD_NSACR13" line.long 0x38 "GIC_REGS_Distributor__33_GICD_NSACR14,GICD_NSACR14" line.long 0x3C "GIC_REGS_Distributor__33_GICD_NSACR15,GICD_NSACR15" line.long 0x40 "GIC_REGS_Distributor__33_GICD_NSACR16,GICD_NSACR16" line.long 0x44 "GIC_REGS_Distributor__33_GICD_NSACR17,GICD_NSACR17" group.long 0x6100++0x7FF line.long 0x0 "GIC_REGS_Distributor__37_GICD_IROUTER32_lower,GICD_IROUTER32_lower" bitfld.long 0x0 31. "DISTRIBUTOR__37_GICD_IROUTER32_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER32_LOWER__8_8,A1" newline hexmask.long.byte 0x0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER32_LOWER__0_8,A0" line.long 0x4 "GIC_REGS_Distributor__37_GICD_IROUTER32_upper,GICD_IROUTER32_upper" line.long 0x8 "GIC_REGS_Distributor__37_GICD_IROUTER33_lower,GICD_IROUTER33_lower" bitfld.long 0x8 31. "DISTRIBUTOR__37_GICD_IROUTER33_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER33_LOWER__8_8,A1" newline hexmask.long.byte 0x8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER33_LOWER__0_8,A0" line.long 0xC "GIC_REGS_Distributor__37_GICD_IROUTER33_upper,GICD_IROUTER33_upper" line.long 0x10 "GIC_REGS_Distributor__37_GICD_IROUTER34_lower,GICD_IROUTER34_lower" bitfld.long 0x10 31. "DISTRIBUTOR__37_GICD_IROUTER34_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x10 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER34_LOWER__8_8,A1" newline hexmask.long.byte 0x10 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER34_LOWER__0_8,A0" line.long 0x14 "GIC_REGS_Distributor__37_GICD_IROUTER34_upper,GICD_IROUTER34_upper" line.long 0x18 "GIC_REGS_Distributor__37_GICD_IROUTER35_lower,GICD_IROUTER35_lower" bitfld.long 0x18 31. "DISTRIBUTOR__37_GICD_IROUTER35_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x18 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER35_LOWER__8_8,A1" newline hexmask.long.byte 0x18 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER35_LOWER__0_8,A0" line.long 0x1C "GIC_REGS_Distributor__37_GICD_IROUTER35_upper,GICD_IROUTER35_upper" line.long 0x20 "GIC_REGS_Distributor__37_GICD_IROUTER36_lower,GICD_IROUTER36_lower" bitfld.long 0x20 31. "DISTRIBUTOR__37_GICD_IROUTER36_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x20 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER36_LOWER__8_8,A1" newline hexmask.long.byte 0x20 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER36_LOWER__0_8,A0" line.long 0x24 "GIC_REGS_Distributor__37_GICD_IROUTER36_upper,GICD_IROUTER36_upper" line.long 0x28 "GIC_REGS_Distributor__37_GICD_IROUTER37_lower,GICD_IROUTER37_lower" bitfld.long 0x28 31. "DISTRIBUTOR__37_GICD_IROUTER37_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x28 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER37_LOWER__8_8,A1" newline hexmask.long.byte 0x28 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER37_LOWER__0_8,A0" line.long 0x2C "GIC_REGS_Distributor__37_GICD_IROUTER37_upper,GICD_IROUTER37_upper" line.long 0x30 "GIC_REGS_Distributor__37_GICD_IROUTER38_lower,GICD_IROUTER38_lower" bitfld.long 0x30 31. "DISTRIBUTOR__37_GICD_IROUTER38_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x30 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER38_LOWER__8_8,A1" newline hexmask.long.byte 0x30 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER38_LOWER__0_8,A0" line.long 0x34 "GIC_REGS_Distributor__37_GICD_IROUTER38_upper,GICD_IROUTER38_upper" line.long 0x38 "GIC_REGS_Distributor__37_GICD_IROUTER39_lower,GICD_IROUTER39_lower" bitfld.long 0x38 31. "DISTRIBUTOR__37_GICD_IROUTER39_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x38 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER39_LOWER__8_8,A1" newline hexmask.long.byte 0x38 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER39_LOWER__0_8,A0" line.long 0x3C "GIC_REGS_Distributor__37_GICD_IROUTER39_upper,GICD_IROUTER39_upper" line.long 0x40 "GIC_REGS_Distributor__37_GICD_IROUTER40_lower,GICD_IROUTER40_lower" bitfld.long 0x40 31. "DISTRIBUTOR__37_GICD_IROUTER40_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x40 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER40_LOWER__8_8,A1" newline hexmask.long.byte 0x40 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER40_LOWER__0_8,A0" line.long 0x44 "GIC_REGS_Distributor__37_GICD_IROUTER40_upper,GICD_IROUTER40_upper" line.long 0x48 "GIC_REGS_Distributor__37_GICD_IROUTER41_lower,GICD_IROUTER41_lower" bitfld.long 0x48 31. "DISTRIBUTOR__37_GICD_IROUTER41_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x48 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER41_LOWER__8_8,A1" newline hexmask.long.byte 0x48 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER41_LOWER__0_8,A0" line.long 0x4C "GIC_REGS_Distributor__37_GICD_IROUTER41_upper,GICD_IROUTER41_upper" line.long 0x50 "GIC_REGS_Distributor__37_GICD_IROUTER42_lower,GICD_IROUTER42_lower" bitfld.long 0x50 31. "DISTRIBUTOR__37_GICD_IROUTER42_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x50 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER42_LOWER__8_8,A1" newline hexmask.long.byte 0x50 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER42_LOWER__0_8,A0" line.long 0x54 "GIC_REGS_Distributor__37_GICD_IROUTER42_upper,GICD_IROUTER42_upper" line.long 0x58 "GIC_REGS_Distributor__37_GICD_IROUTER43_lower,GICD_IROUTER43_lower" bitfld.long 0x58 31. "DISTRIBUTOR__37_GICD_IROUTER43_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x58 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER43_LOWER__8_8,A1" newline hexmask.long.byte 0x58 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER43_LOWER__0_8,A0" line.long 0x5C "GIC_REGS_Distributor__37_GICD_IROUTER43_upper,GICD_IROUTER43_upper" line.long 0x60 "GIC_REGS_Distributor__37_GICD_IROUTER44_lower,GICD_IROUTER44_lower" bitfld.long 0x60 31. "DISTRIBUTOR__37_GICD_IROUTER44_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x60 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER44_LOWER__8_8,A1" newline hexmask.long.byte 0x60 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER44_LOWER__0_8,A0" line.long 0x64 "GIC_REGS_Distributor__37_GICD_IROUTER44_upper,GICD_IROUTER44_upper" line.long 0x68 "GIC_REGS_Distributor__37_GICD_IROUTER45_lower,GICD_IROUTER45_lower" bitfld.long 0x68 31. "DISTRIBUTOR__37_GICD_IROUTER45_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x68 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER45_LOWER__8_8,A1" newline hexmask.long.byte 0x68 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER45_LOWER__0_8,A0" line.long 0x6C "GIC_REGS_Distributor__37_GICD_IROUTER45_upper,GICD_IROUTER45_upper" line.long 0x70 "GIC_REGS_Distributor__37_GICD_IROUTER46_lower,GICD_IROUTER46_lower" bitfld.long 0x70 31. "DISTRIBUTOR__37_GICD_IROUTER46_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x70 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER46_LOWER__8_8,A1" newline hexmask.long.byte 0x70 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER46_LOWER__0_8,A0" line.long 0x74 "GIC_REGS_Distributor__37_GICD_IROUTER46_upper,GICD_IROUTER46_upper" line.long 0x78 "GIC_REGS_Distributor__37_GICD_IROUTER47_lower,GICD_IROUTER47_lower" bitfld.long 0x78 31. "DISTRIBUTOR__37_GICD_IROUTER47_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x78 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER47_LOWER__8_8,A1" newline hexmask.long.byte 0x78 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER47_LOWER__0_8,A0" line.long 0x7C "GIC_REGS_Distributor__37_GICD_IROUTER47_upper,GICD_IROUTER47_upper" line.long 0x80 "GIC_REGS_Distributor__37_GICD_IROUTER48_lower,GICD_IROUTER48_lower" bitfld.long 0x80 31. "DISTRIBUTOR__37_GICD_IROUTER48_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x80 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER48_LOWER__8_8,A1" newline hexmask.long.byte 0x80 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER48_LOWER__0_8,A0" line.long 0x84 "GIC_REGS_Distributor__37_GICD_IROUTER48_upper,GICD_IROUTER48_upper" line.long 0x88 "GIC_REGS_Distributor__37_GICD_IROUTER49_lower,GICD_IROUTER49_lower" bitfld.long 0x88 31. "DISTRIBUTOR__37_GICD_IROUTER49_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x88 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER49_LOWER__8_8,A1" newline hexmask.long.byte 0x88 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER49_LOWER__0_8,A0" line.long 0x8C "GIC_REGS_Distributor__37_GICD_IROUTER49_upper,GICD_IROUTER49_upper" line.long 0x90 "GIC_REGS_Distributor__37_GICD_IROUTER50_lower,GICD_IROUTER50_lower" bitfld.long 0x90 31. "DISTRIBUTOR__37_GICD_IROUTER50_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x90 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER50_LOWER__8_8,A1" newline hexmask.long.byte 0x90 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER50_LOWER__0_8,A0" line.long 0x94 "GIC_REGS_Distributor__37_GICD_IROUTER50_upper,GICD_IROUTER50_upper" line.long 0x98 "GIC_REGS_Distributor__37_GICD_IROUTER51_lower,GICD_IROUTER51_lower" bitfld.long 0x98 31. "DISTRIBUTOR__37_GICD_IROUTER51_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x98 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER51_LOWER__8_8,A1" newline hexmask.long.byte 0x98 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER51_LOWER__0_8,A0" line.long 0x9C "GIC_REGS_Distributor__37_GICD_IROUTER51_upper,GICD_IROUTER51_upper" line.long 0xA0 "GIC_REGS_Distributor__37_GICD_IROUTER52_lower,GICD_IROUTER52_lower" bitfld.long 0xA0 31. "DISTRIBUTOR__37_GICD_IROUTER52_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0xA0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER52_LOWER__8_8,A1" newline hexmask.long.byte 0xA0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER52_LOWER__0_8,A0" line.long 0xA4 "GIC_REGS_Distributor__37_GICD_IROUTER52_upper,GICD_IROUTER52_upper" line.long 0xA8 "GIC_REGS_Distributor__37_GICD_IROUTER53_lower,GICD_IROUTER53_lower" bitfld.long 0xA8 31. "DISTRIBUTOR__37_GICD_IROUTER53_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0xA8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER53_LOWER__8_8,A1" newline hexmask.long.byte 0xA8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER53_LOWER__0_8,A0" line.long 0xAC "GIC_REGS_Distributor__37_GICD_IROUTER53_upper,GICD_IROUTER53_upper" line.long 0xB0 "GIC_REGS_Distributor__37_GICD_IROUTER54_lower,GICD_IROUTER54_lower" bitfld.long 0xB0 31. "DISTRIBUTOR__37_GICD_IROUTER54_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0xB0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER54_LOWER__8_8,A1" newline hexmask.long.byte 0xB0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER54_LOWER__0_8,A0" line.long 0xB4 "GIC_REGS_Distributor__37_GICD_IROUTER54_upper,GICD_IROUTER54_upper" line.long 0xB8 "GIC_REGS_Distributor__37_GICD_IROUTER55_lower,GICD_IROUTER55_lower" bitfld.long 0xB8 31. "DISTRIBUTOR__37_GICD_IROUTER55_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0xB8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER55_LOWER__8_8,A1" newline hexmask.long.byte 0xB8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER55_LOWER__0_8,A0" line.long 0xBC "GIC_REGS_Distributor__37_GICD_IROUTER55_upper,GICD_IROUTER55_upper" line.long 0xC0 "GIC_REGS_Distributor__37_GICD_IROUTER56_lower,GICD_IROUTER56_lower" bitfld.long 0xC0 31. "DISTRIBUTOR__37_GICD_IROUTER56_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0xC0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER56_LOWER__8_8,A1" newline hexmask.long.byte 0xC0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER56_LOWER__0_8,A0" line.long 0xC4 "GIC_REGS_Distributor__37_GICD_IROUTER56_upper,GICD_IROUTER56_upper" line.long 0xC8 "GIC_REGS_Distributor__37_GICD_IROUTER57_lower,GICD_IROUTER57_lower" bitfld.long 0xC8 31. "DISTRIBUTOR__37_GICD_IROUTER57_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0xC8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER57_LOWER__8_8,A1" newline hexmask.long.byte 0xC8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER57_LOWER__0_8,A0" line.long 0xCC "GIC_REGS_Distributor__37_GICD_IROUTER57_upper,GICD_IROUTER57_upper" line.long 0xD0 "GIC_REGS_Distributor__37_GICD_IROUTER58_lower,GICD_IROUTER58_lower" bitfld.long 0xD0 31. "DISTRIBUTOR__37_GICD_IROUTER58_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0xD0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER58_LOWER__8_8,A1" newline hexmask.long.byte 0xD0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER58_LOWER__0_8,A0" line.long 0xD4 "GIC_REGS_Distributor__37_GICD_IROUTER58_upper,GICD_IROUTER58_upper" line.long 0xD8 "GIC_REGS_Distributor__37_GICD_IROUTER59_lower,GICD_IROUTER59_lower" bitfld.long 0xD8 31. "DISTRIBUTOR__37_GICD_IROUTER59_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0xD8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER59_LOWER__8_8,A1" newline hexmask.long.byte 0xD8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER59_LOWER__0_8,A0" line.long 0xDC "GIC_REGS_Distributor__37_GICD_IROUTER59_upper,GICD_IROUTER59_upper" line.long 0xE0 "GIC_REGS_Distributor__37_GICD_IROUTER60_lower,GICD_IROUTER60_lower" bitfld.long 0xE0 31. "DISTRIBUTOR__37_GICD_IROUTER60_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0xE0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER60_LOWER__8_8,A1" newline hexmask.long.byte 0xE0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER60_LOWER__0_8,A0" line.long 0xE4 "GIC_REGS_Distributor__37_GICD_IROUTER60_upper,GICD_IROUTER60_upper" line.long 0xE8 "GIC_REGS_Distributor__37_GICD_IROUTER61_lower,GICD_IROUTER61_lower" bitfld.long 0xE8 31. "DISTRIBUTOR__37_GICD_IROUTER61_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0xE8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER61_LOWER__8_8,A1" newline hexmask.long.byte 0xE8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER61_LOWER__0_8,A0" line.long 0xEC "GIC_REGS_Distributor__37_GICD_IROUTER61_upper,GICD_IROUTER61_upper" line.long 0xF0 "GIC_REGS_Distributor__37_GICD_IROUTER62_lower,GICD_IROUTER62_lower" bitfld.long 0xF0 31. "DISTRIBUTOR__37_GICD_IROUTER62_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0xF0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER62_LOWER__8_8,A1" newline hexmask.long.byte 0xF0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER62_LOWER__0_8,A0" line.long 0xF4 "GIC_REGS_Distributor__37_GICD_IROUTER62_upper,GICD_IROUTER62_upper" line.long 0xF8 "GIC_REGS_Distributor__37_GICD_IROUTER63_lower,GICD_IROUTER63_lower" bitfld.long 0xF8 31. "DISTRIBUTOR__37_GICD_IROUTER63_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0xF8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER63_LOWER__8_8,A1" newline hexmask.long.byte 0xF8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER63_LOWER__0_8,A0" line.long 0xFC "GIC_REGS_Distributor__37_GICD_IROUTER63_upper,GICD_IROUTER63_upper" line.long 0x100 "GIC_REGS_Distributor__37_GICD_IROUTER64_lower,GICD_IROUTER64_lower" bitfld.long 0x100 31. "DISTRIBUTOR__37_GICD_IROUTER64_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x100 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER64_LOWER__8_8,A1" newline hexmask.long.byte 0x100 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER64_LOWER__0_8,A0" line.long 0x104 "GIC_REGS_Distributor__37_GICD_IROUTER64_upper,GICD_IROUTER64_upper" line.long 0x108 "GIC_REGS_Distributor__37_GICD_IROUTER65_lower,GICD_IROUTER65_lower" bitfld.long 0x108 31. "DISTRIBUTOR__37_GICD_IROUTER65_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x108 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER65_LOWER__8_8,A1" newline hexmask.long.byte 0x108 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER65_LOWER__0_8,A0" line.long 0x10C "GIC_REGS_Distributor__37_GICD_IROUTER65_upper,GICD_IROUTER65_upper" line.long 0x110 "GIC_REGS_Distributor__37_GICD_IROUTER66_lower,GICD_IROUTER66_lower" bitfld.long 0x110 31. "DISTRIBUTOR__37_GICD_IROUTER66_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x110 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER66_LOWER__8_8,A1" newline hexmask.long.byte 0x110 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER66_LOWER__0_8,A0" line.long 0x114 "GIC_REGS_Distributor__37_GICD_IROUTER66_upper,GICD_IROUTER66_upper" line.long 0x118 "GIC_REGS_Distributor__37_GICD_IROUTER67_lower,GICD_IROUTER67_lower" bitfld.long 0x118 31. "DISTRIBUTOR__37_GICD_IROUTER67_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x118 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER67_LOWER__8_8,A1" newline hexmask.long.byte 0x118 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER67_LOWER__0_8,A0" line.long 0x11C "GIC_REGS_Distributor__37_GICD_IROUTER67_upper,GICD_IROUTER67_upper" line.long 0x120 "GIC_REGS_Distributor__37_GICD_IROUTER68_lower,GICD_IROUTER68_lower" bitfld.long 0x120 31. "DISTRIBUTOR__37_GICD_IROUTER68_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x120 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER68_LOWER__8_8,A1" newline hexmask.long.byte 0x120 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER68_LOWER__0_8,A0" line.long 0x124 "GIC_REGS_Distributor__37_GICD_IROUTER68_upper,GICD_IROUTER68_upper" line.long 0x128 "GIC_REGS_Distributor__37_GICD_IROUTER69_lower,GICD_IROUTER69_lower" bitfld.long 0x128 31. "DISTRIBUTOR__37_GICD_IROUTER69_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x128 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER69_LOWER__8_8,A1" newline hexmask.long.byte 0x128 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER69_LOWER__0_8,A0" line.long 0x12C "GIC_REGS_Distributor__37_GICD_IROUTER69_upper,GICD_IROUTER69_upper" line.long 0x130 "GIC_REGS_Distributor__37_GICD_IROUTER70_lower,GICD_IROUTER70_lower" bitfld.long 0x130 31. "DISTRIBUTOR__37_GICD_IROUTER70_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x130 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER70_LOWER__8_8,A1" newline hexmask.long.byte 0x130 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER70_LOWER__0_8,A0" line.long 0x134 "GIC_REGS_Distributor__37_GICD_IROUTER70_upper,GICD_IROUTER70_upper" line.long 0x138 "GIC_REGS_Distributor__37_GICD_IROUTER71_lower,GICD_IROUTER71_lower" bitfld.long 0x138 31. "DISTRIBUTOR__37_GICD_IROUTER71_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x138 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER71_LOWER__8_8,A1" newline hexmask.long.byte 0x138 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER71_LOWER__0_8,A0" line.long 0x13C "GIC_REGS_Distributor__37_GICD_IROUTER71_upper,GICD_IROUTER71_upper" line.long 0x140 "GIC_REGS_Distributor__37_GICD_IROUTER72_lower,GICD_IROUTER72_lower" bitfld.long 0x140 31. "DISTRIBUTOR__37_GICD_IROUTER72_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x140 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER72_LOWER__8_8,A1" newline hexmask.long.byte 0x140 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER72_LOWER__0_8,A0" line.long 0x144 "GIC_REGS_Distributor__37_GICD_IROUTER72_upper,GICD_IROUTER72_upper" line.long 0x148 "GIC_REGS_Distributor__37_GICD_IROUTER73_lower,GICD_IROUTER73_lower" bitfld.long 0x148 31. "DISTRIBUTOR__37_GICD_IROUTER73_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x148 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER73_LOWER__8_8,A1" newline hexmask.long.byte 0x148 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER73_LOWER__0_8,A0" line.long 0x14C "GIC_REGS_Distributor__37_GICD_IROUTER73_upper,GICD_IROUTER73_upper" line.long 0x150 "GIC_REGS_Distributor__37_GICD_IROUTER74_lower,GICD_IROUTER74_lower" bitfld.long 0x150 31. "DISTRIBUTOR__37_GICD_IROUTER74_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x150 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER74_LOWER__8_8,A1" newline hexmask.long.byte 0x150 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER74_LOWER__0_8,A0" line.long 0x154 "GIC_REGS_Distributor__37_GICD_IROUTER74_upper,GICD_IROUTER74_upper" line.long 0x158 "GIC_REGS_Distributor__37_GICD_IROUTER75_lower,GICD_IROUTER75_lower" bitfld.long 0x158 31. "DISTRIBUTOR__37_GICD_IROUTER75_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x158 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER75_LOWER__8_8,A1" newline hexmask.long.byte 0x158 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER75_LOWER__0_8,A0" line.long 0x15C "GIC_REGS_Distributor__37_GICD_IROUTER75_upper,GICD_IROUTER75_upper" line.long 0x160 "GIC_REGS_Distributor__37_GICD_IROUTER76_lower,GICD_IROUTER76_lower" bitfld.long 0x160 31. "DISTRIBUTOR__37_GICD_IROUTER76_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x160 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER76_LOWER__8_8,A1" newline hexmask.long.byte 0x160 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER76_LOWER__0_8,A0" line.long 0x164 "GIC_REGS_Distributor__37_GICD_IROUTER76_upper,GICD_IROUTER76_upper" line.long 0x168 "GIC_REGS_Distributor__37_GICD_IROUTER77_lower,GICD_IROUTER77_lower" bitfld.long 0x168 31. "DISTRIBUTOR__37_GICD_IROUTER77_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x168 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER77_LOWER__8_8,A1" newline hexmask.long.byte 0x168 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER77_LOWER__0_8,A0" line.long 0x16C "GIC_REGS_Distributor__37_GICD_IROUTER77_upper,GICD_IROUTER77_upper" line.long 0x170 "GIC_REGS_Distributor__37_GICD_IROUTER78_lower,GICD_IROUTER78_lower" bitfld.long 0x170 31. "DISTRIBUTOR__37_GICD_IROUTER78_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x170 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER78_LOWER__8_8,A1" newline hexmask.long.byte 0x170 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER78_LOWER__0_8,A0" line.long 0x174 "GIC_REGS_Distributor__37_GICD_IROUTER78_upper,GICD_IROUTER78_upper" line.long 0x178 "GIC_REGS_Distributor__37_GICD_IROUTER79_lower,GICD_IROUTER79_lower" bitfld.long 0x178 31. "DISTRIBUTOR__37_GICD_IROUTER79_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x178 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER79_LOWER__8_8,A1" newline hexmask.long.byte 0x178 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER79_LOWER__0_8,A0" line.long 0x17C "GIC_REGS_Distributor__37_GICD_IROUTER79_upper,GICD_IROUTER79_upper" line.long 0x180 "GIC_REGS_Distributor__37_GICD_IROUTER80_lower,GICD_IROUTER80_lower" bitfld.long 0x180 31. "DISTRIBUTOR__37_GICD_IROUTER80_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x180 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER80_LOWER__8_8,A1" newline hexmask.long.byte 0x180 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER80_LOWER__0_8,A0" line.long 0x184 "GIC_REGS_Distributor__37_GICD_IROUTER80_upper,GICD_IROUTER80_upper" line.long 0x188 "GIC_REGS_Distributor__37_GICD_IROUTER81_lower,GICD_IROUTER81_lower" bitfld.long 0x188 31. "DISTRIBUTOR__37_GICD_IROUTER81_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x188 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER81_LOWER__8_8,A1" newline hexmask.long.byte 0x188 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER81_LOWER__0_8,A0" line.long 0x18C "GIC_REGS_Distributor__37_GICD_IROUTER81_upper,GICD_IROUTER81_upper" line.long 0x190 "GIC_REGS_Distributor__37_GICD_IROUTER82_lower,GICD_IROUTER82_lower" bitfld.long 0x190 31. "DISTRIBUTOR__37_GICD_IROUTER82_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x190 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER82_LOWER__8_8,A1" newline hexmask.long.byte 0x190 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER82_LOWER__0_8,A0" line.long 0x194 "GIC_REGS_Distributor__37_GICD_IROUTER82_upper,GICD_IROUTER82_upper" line.long 0x198 "GIC_REGS_Distributor__37_GICD_IROUTER83_lower,GICD_IROUTER83_lower" bitfld.long 0x198 31. "DISTRIBUTOR__37_GICD_IROUTER83_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x198 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER83_LOWER__8_8,A1" newline hexmask.long.byte 0x198 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER83_LOWER__0_8,A0" line.long 0x19C "GIC_REGS_Distributor__37_GICD_IROUTER83_upper,GICD_IROUTER83_upper" line.long 0x1A0 "GIC_REGS_Distributor__37_GICD_IROUTER84_lower,GICD_IROUTER84_lower" bitfld.long 0x1A0 31. "DISTRIBUTOR__37_GICD_IROUTER84_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x1A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER84_LOWER__8_8,A1" newline hexmask.long.byte 0x1A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER84_LOWER__0_8,A0" line.long 0x1A4 "GIC_REGS_Distributor__37_GICD_IROUTER84_upper,GICD_IROUTER84_upper" line.long 0x1A8 "GIC_REGS_Distributor__37_GICD_IROUTER85_lower,GICD_IROUTER85_lower" bitfld.long 0x1A8 31. "DISTRIBUTOR__37_GICD_IROUTER85_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x1A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER85_LOWER__8_8,A1" newline hexmask.long.byte 0x1A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER85_LOWER__0_8,A0" line.long 0x1AC "GIC_REGS_Distributor__37_GICD_IROUTER85_upper,GICD_IROUTER85_upper" line.long 0x1B0 "GIC_REGS_Distributor__37_GICD_IROUTER86_lower,GICD_IROUTER86_lower" bitfld.long 0x1B0 31. "DISTRIBUTOR__37_GICD_IROUTER86_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x1B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER86_LOWER__8_8,A1" newline hexmask.long.byte 0x1B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER86_LOWER__0_8,A0" line.long 0x1B4 "GIC_REGS_Distributor__37_GICD_IROUTER86_upper,GICD_IROUTER86_upper" line.long 0x1B8 "GIC_REGS_Distributor__37_GICD_IROUTER87_lower,GICD_IROUTER87_lower" bitfld.long 0x1B8 31. "DISTRIBUTOR__37_GICD_IROUTER87_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x1B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER87_LOWER__8_8,A1" newline hexmask.long.byte 0x1B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER87_LOWER__0_8,A0" line.long 0x1BC "GIC_REGS_Distributor__37_GICD_IROUTER87_upper,GICD_IROUTER87_upper" line.long 0x1C0 "GIC_REGS_Distributor__37_GICD_IROUTER88_lower,GICD_IROUTER88_lower" bitfld.long 0x1C0 31. "DISTRIBUTOR__37_GICD_IROUTER88_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x1C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER88_LOWER__8_8,A1" newline hexmask.long.byte 0x1C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER88_LOWER__0_8,A0" line.long 0x1C4 "GIC_REGS_Distributor__37_GICD_IROUTER88_upper,GICD_IROUTER88_upper" line.long 0x1C8 "GIC_REGS_Distributor__37_GICD_IROUTER89_lower,GICD_IROUTER89_lower" bitfld.long 0x1C8 31. "DISTRIBUTOR__37_GICD_IROUTER89_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x1C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER89_LOWER__8_8,A1" newline hexmask.long.byte 0x1C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER89_LOWER__0_8,A0" line.long 0x1CC "GIC_REGS_Distributor__37_GICD_IROUTER89_upper,GICD_IROUTER89_upper" line.long 0x1D0 "GIC_REGS_Distributor__37_GICD_IROUTER90_lower,GICD_IROUTER90_lower" bitfld.long 0x1D0 31. "DISTRIBUTOR__37_GICD_IROUTER90_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x1D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER90_LOWER__8_8,A1" newline hexmask.long.byte 0x1D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER90_LOWER__0_8,A0" line.long 0x1D4 "GIC_REGS_Distributor__37_GICD_IROUTER90_upper,GICD_IROUTER90_upper" line.long 0x1D8 "GIC_REGS_Distributor__37_GICD_IROUTER91_lower,GICD_IROUTER91_lower" bitfld.long 0x1D8 31. "DISTRIBUTOR__37_GICD_IROUTER91_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x1D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER91_LOWER__8_8,A1" newline hexmask.long.byte 0x1D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER91_LOWER__0_8,A0" line.long 0x1DC "GIC_REGS_Distributor__37_GICD_IROUTER91_upper,GICD_IROUTER91_upper" line.long 0x1E0 "GIC_REGS_Distributor__37_GICD_IROUTER92_lower,GICD_IROUTER92_lower" bitfld.long 0x1E0 31. "DISTRIBUTOR__37_GICD_IROUTER92_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x1E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER92_LOWER__8_8,A1" newline hexmask.long.byte 0x1E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER92_LOWER__0_8,A0" line.long 0x1E4 "GIC_REGS_Distributor__37_GICD_IROUTER92_upper,GICD_IROUTER92_upper" line.long 0x1E8 "GIC_REGS_Distributor__37_GICD_IROUTER93_lower,GICD_IROUTER93_lower" bitfld.long 0x1E8 31. "DISTRIBUTOR__37_GICD_IROUTER93_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x1E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER93_LOWER__8_8,A1" newline hexmask.long.byte 0x1E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER93_LOWER__0_8,A0" line.long 0x1EC "GIC_REGS_Distributor__37_GICD_IROUTER93_upper,GICD_IROUTER93_upper" line.long 0x1F0 "GIC_REGS_Distributor__37_GICD_IROUTER94_lower,GICD_IROUTER94_lower" bitfld.long 0x1F0 31. "DISTRIBUTOR__37_GICD_IROUTER94_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x1F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER94_LOWER__8_8,A1" newline hexmask.long.byte 0x1F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER94_LOWER__0_8,A0" line.long 0x1F4 "GIC_REGS_Distributor__37_GICD_IROUTER94_upper,GICD_IROUTER94_upper" line.long 0x1F8 "GIC_REGS_Distributor__37_GICD_IROUTER95_lower,GICD_IROUTER95_lower" bitfld.long 0x1F8 31. "DISTRIBUTOR__37_GICD_IROUTER95_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x1F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER95_LOWER__8_8,A1" newline hexmask.long.byte 0x1F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER95_LOWER__0_8,A0" line.long 0x1FC "GIC_REGS_Distributor__37_GICD_IROUTER95_upper,GICD_IROUTER95_upper" line.long 0x200 "GIC_REGS_Distributor__37_GICD_IROUTER96_lower,GICD_IROUTER96_lower" bitfld.long 0x200 31. "DISTRIBUTOR__37_GICD_IROUTER96_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x200 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER96_LOWER__8_8,A1" newline hexmask.long.byte 0x200 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER96_LOWER__0_8,A0" line.long 0x204 "GIC_REGS_Distributor__37_GICD_IROUTER96_upper,GICD_IROUTER96_upper" line.long 0x208 "GIC_REGS_Distributor__37_GICD_IROUTER97_lower,GICD_IROUTER97_lower" bitfld.long 0x208 31. "DISTRIBUTOR__37_GICD_IROUTER97_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x208 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER97_LOWER__8_8,A1" newline hexmask.long.byte 0x208 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER97_LOWER__0_8,A0" line.long 0x20C "GIC_REGS_Distributor__37_GICD_IROUTER97_upper,GICD_IROUTER97_upper" line.long 0x210 "GIC_REGS_Distributor__37_GICD_IROUTER98_lower,GICD_IROUTER98_lower" bitfld.long 0x210 31. "DISTRIBUTOR__37_GICD_IROUTER98_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x210 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER98_LOWER__8_8,A1" newline hexmask.long.byte 0x210 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER98_LOWER__0_8,A0" line.long 0x214 "GIC_REGS_Distributor__37_GICD_IROUTER98_upper,GICD_IROUTER98_upper" line.long 0x218 "GIC_REGS_Distributor__37_GICD_IROUTER99_lower,GICD_IROUTER99_lower" bitfld.long 0x218 31. "DISTRIBUTOR__37_GICD_IROUTER99_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x218 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER99_LOWER__8_8,A1" newline hexmask.long.byte 0x218 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER99_LOWER__0_8,A0" line.long 0x21C "GIC_REGS_Distributor__37_GICD_IROUTER99_upper,GICD_IROUTER99_upper" line.long 0x220 "GIC_REGS_Distributor__37_GICD_IROUTER100_lower,GICD_IROUTER100_lower" bitfld.long 0x220 31. "DISTRIBUTOR__37_GICD_IROUTER100_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x220 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER100_LOWER__8_8,A1" newline hexmask.long.byte 0x220 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER100_LOWER__0_8,A0" line.long 0x224 "GIC_REGS_Distributor__37_GICD_IROUTER100_upper,GICD_IROUTER100_upper" line.long 0x228 "GIC_REGS_Distributor__37_GICD_IROUTER101_lower,GICD_IROUTER101_lower" bitfld.long 0x228 31. "DISTRIBUTOR__37_GICD_IROUTER101_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x228 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER101_LOWER__8_8,A1" newline hexmask.long.byte 0x228 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER101_LOWER__0_8,A0" line.long 0x22C "GIC_REGS_Distributor__37_GICD_IROUTER101_upper,GICD_IROUTER101_upper" line.long 0x230 "GIC_REGS_Distributor__37_GICD_IROUTER102_lower,GICD_IROUTER102_lower" bitfld.long 0x230 31. "DISTRIBUTOR__37_GICD_IROUTER102_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x230 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER102_LOWER__8_8,A1" newline hexmask.long.byte 0x230 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER102_LOWER__0_8,A0" line.long 0x234 "GIC_REGS_Distributor__37_GICD_IROUTER102_upper,GICD_IROUTER102_upper" line.long 0x238 "GIC_REGS_Distributor__37_GICD_IROUTER103_lower,GICD_IROUTER103_lower" bitfld.long 0x238 31. "DISTRIBUTOR__37_GICD_IROUTER103_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x238 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER103_LOWER__8_8,A1" newline hexmask.long.byte 0x238 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER103_LOWER__0_8,A0" line.long 0x23C "GIC_REGS_Distributor__37_GICD_IROUTER103_upper,GICD_IROUTER103_upper" line.long 0x240 "GIC_REGS_Distributor__37_GICD_IROUTER104_lower,GICD_IROUTER104_lower" bitfld.long 0x240 31. "DISTRIBUTOR__37_GICD_IROUTER104_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x240 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER104_LOWER__8_8,A1" newline hexmask.long.byte 0x240 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER104_LOWER__0_8,A0" line.long 0x244 "GIC_REGS_Distributor__37_GICD_IROUTER104_upper,GICD_IROUTER104_upper" line.long 0x248 "GIC_REGS_Distributor__37_GICD_IROUTER105_lower,GICD_IROUTER105_lower" bitfld.long 0x248 31. "DISTRIBUTOR__37_GICD_IROUTER105_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x248 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER105_LOWER__8_8,A1" newline hexmask.long.byte 0x248 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER105_LOWER__0_8,A0" line.long 0x24C "GIC_REGS_Distributor__37_GICD_IROUTER105_upper,GICD_IROUTER105_upper" line.long 0x250 "GIC_REGS_Distributor__37_GICD_IROUTER106_lower,GICD_IROUTER106_lower" bitfld.long 0x250 31. "DISTRIBUTOR__37_GICD_IROUTER106_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x250 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER106_LOWER__8_8,A1" newline hexmask.long.byte 0x250 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER106_LOWER__0_8,A0" line.long 0x254 "GIC_REGS_Distributor__37_GICD_IROUTER106_upper,GICD_IROUTER106_upper" line.long 0x258 "GIC_REGS_Distributor__37_GICD_IROUTER107_lower,GICD_IROUTER107_lower" bitfld.long 0x258 31. "DISTRIBUTOR__37_GICD_IROUTER107_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x258 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER107_LOWER__8_8,A1" newline hexmask.long.byte 0x258 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER107_LOWER__0_8,A0" line.long 0x25C "GIC_REGS_Distributor__37_GICD_IROUTER107_upper,GICD_IROUTER107_upper" line.long 0x260 "GIC_REGS_Distributor__37_GICD_IROUTER108_lower,GICD_IROUTER108_lower" bitfld.long 0x260 31. "DISTRIBUTOR__37_GICD_IROUTER108_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x260 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER108_LOWER__8_8,A1" newline hexmask.long.byte 0x260 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER108_LOWER__0_8,A0" line.long 0x264 "GIC_REGS_Distributor__37_GICD_IROUTER108_upper,GICD_IROUTER108_upper" line.long 0x268 "GIC_REGS_Distributor__37_GICD_IROUTER109_lower,GICD_IROUTER109_lower" bitfld.long 0x268 31. "DISTRIBUTOR__37_GICD_IROUTER109_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x268 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER109_LOWER__8_8,A1" newline hexmask.long.byte 0x268 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER109_LOWER__0_8,A0" line.long 0x26C "GIC_REGS_Distributor__37_GICD_IROUTER109_upper,GICD_IROUTER109_upper" line.long 0x270 "GIC_REGS_Distributor__37_GICD_IROUTER110_lower,GICD_IROUTER110_lower" bitfld.long 0x270 31. "DISTRIBUTOR__37_GICD_IROUTER110_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x270 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER110_LOWER__8_8,A1" newline hexmask.long.byte 0x270 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER110_LOWER__0_8,A0" line.long 0x274 "GIC_REGS_Distributor__37_GICD_IROUTER110_upper,GICD_IROUTER110_upper" line.long 0x278 "GIC_REGS_Distributor__37_GICD_IROUTER111_lower,GICD_IROUTER111_lower" bitfld.long 0x278 31. "DISTRIBUTOR__37_GICD_IROUTER111_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x278 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER111_LOWER__8_8,A1" newline hexmask.long.byte 0x278 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER111_LOWER__0_8,A0" line.long 0x27C "GIC_REGS_Distributor__37_GICD_IROUTER111_upper,GICD_IROUTER111_upper" line.long 0x280 "GIC_REGS_Distributor__37_GICD_IROUTER112_lower,GICD_IROUTER112_lower" bitfld.long 0x280 31. "DISTRIBUTOR__37_GICD_IROUTER112_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x280 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER112_LOWER__8_8,A1" newline hexmask.long.byte 0x280 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER112_LOWER__0_8,A0" line.long 0x284 "GIC_REGS_Distributor__37_GICD_IROUTER112_upper,GICD_IROUTER112_upper" line.long 0x288 "GIC_REGS_Distributor__37_GICD_IROUTER113_lower,GICD_IROUTER113_lower" bitfld.long 0x288 31. "DISTRIBUTOR__37_GICD_IROUTER113_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x288 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER113_LOWER__8_8,A1" newline hexmask.long.byte 0x288 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER113_LOWER__0_8,A0" line.long 0x28C "GIC_REGS_Distributor__37_GICD_IROUTER113_upper,GICD_IROUTER113_upper" line.long 0x290 "GIC_REGS_Distributor__37_GICD_IROUTER114_lower,GICD_IROUTER114_lower" bitfld.long 0x290 31. "DISTRIBUTOR__37_GICD_IROUTER114_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x290 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER114_LOWER__8_8,A1" newline hexmask.long.byte 0x290 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER114_LOWER__0_8,A0" line.long 0x294 "GIC_REGS_Distributor__37_GICD_IROUTER114_upper,GICD_IROUTER114_upper" line.long 0x298 "GIC_REGS_Distributor__37_GICD_IROUTER115_lower,GICD_IROUTER115_lower" bitfld.long 0x298 31. "DISTRIBUTOR__37_GICD_IROUTER115_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x298 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER115_LOWER__8_8,A1" newline hexmask.long.byte 0x298 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER115_LOWER__0_8,A0" line.long 0x29C "GIC_REGS_Distributor__37_GICD_IROUTER115_upper,GICD_IROUTER115_upper" line.long 0x2A0 "GIC_REGS_Distributor__37_GICD_IROUTER116_lower,GICD_IROUTER116_lower" bitfld.long 0x2A0 31. "DISTRIBUTOR__37_GICD_IROUTER116_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x2A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER116_LOWER__8_8,A1" newline hexmask.long.byte 0x2A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER116_LOWER__0_8,A0" line.long 0x2A4 "GIC_REGS_Distributor__37_GICD_IROUTER116_upper,GICD_IROUTER116_upper" line.long 0x2A8 "GIC_REGS_Distributor__37_GICD_IROUTER117_lower,GICD_IROUTER117_lower" bitfld.long 0x2A8 31. "DISTRIBUTOR__37_GICD_IROUTER117_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x2A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER117_LOWER__8_8,A1" newline hexmask.long.byte 0x2A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER117_LOWER__0_8,A0" line.long 0x2AC "GIC_REGS_Distributor__37_GICD_IROUTER117_upper,GICD_IROUTER117_upper" line.long 0x2B0 "GIC_REGS_Distributor__37_GICD_IROUTER118_lower,GICD_IROUTER118_lower" bitfld.long 0x2B0 31. "DISTRIBUTOR__37_GICD_IROUTER118_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x2B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER118_LOWER__8_8,A1" newline hexmask.long.byte 0x2B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER118_LOWER__0_8,A0" line.long 0x2B4 "GIC_REGS_Distributor__37_GICD_IROUTER118_upper,GICD_IROUTER118_upper" line.long 0x2B8 "GIC_REGS_Distributor__37_GICD_IROUTER119_lower,GICD_IROUTER119_lower" bitfld.long 0x2B8 31. "DISTRIBUTOR__37_GICD_IROUTER119_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x2B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER119_LOWER__8_8,A1" newline hexmask.long.byte 0x2B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER119_LOWER__0_8,A0" line.long 0x2BC "GIC_REGS_Distributor__37_GICD_IROUTER119_upper,GICD_IROUTER119_upper" line.long 0x2C0 "GIC_REGS_Distributor__37_GICD_IROUTER120_lower,GICD_IROUTER120_lower" bitfld.long 0x2C0 31. "DISTRIBUTOR__37_GICD_IROUTER120_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x2C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER120_LOWER__8_8,A1" newline hexmask.long.byte 0x2C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER120_LOWER__0_8,A0" line.long 0x2C4 "GIC_REGS_Distributor__37_GICD_IROUTER120_upper,GICD_IROUTER120_upper" line.long 0x2C8 "GIC_REGS_Distributor__37_GICD_IROUTER121_lower,GICD_IROUTER121_lower" bitfld.long 0x2C8 31. "DISTRIBUTOR__37_GICD_IROUTER121_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x2C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER121_LOWER__8_8,A1" newline hexmask.long.byte 0x2C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER121_LOWER__0_8,A0" line.long 0x2CC "GIC_REGS_Distributor__37_GICD_IROUTER121_upper,GICD_IROUTER121_upper" line.long 0x2D0 "GIC_REGS_Distributor__37_GICD_IROUTER122_lower,GICD_IROUTER122_lower" bitfld.long 0x2D0 31. "DISTRIBUTOR__37_GICD_IROUTER122_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x2D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER122_LOWER__8_8,A1" newline hexmask.long.byte 0x2D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER122_LOWER__0_8,A0" line.long 0x2D4 "GIC_REGS_Distributor__37_GICD_IROUTER122_upper,GICD_IROUTER122_upper" line.long 0x2D8 "GIC_REGS_Distributor__37_GICD_IROUTER123_lower,GICD_IROUTER123_lower" bitfld.long 0x2D8 31. "DISTRIBUTOR__37_GICD_IROUTER123_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x2D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER123_LOWER__8_8,A1" newline hexmask.long.byte 0x2D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER123_LOWER__0_8,A0" line.long 0x2DC "GIC_REGS_Distributor__37_GICD_IROUTER123_upper,GICD_IROUTER123_upper" line.long 0x2E0 "GIC_REGS_Distributor__37_GICD_IROUTER124_lower,GICD_IROUTER124_lower" bitfld.long 0x2E0 31. "DISTRIBUTOR__37_GICD_IROUTER124_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x2E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER124_LOWER__8_8,A1" newline hexmask.long.byte 0x2E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER124_LOWER__0_8,A0" line.long 0x2E4 "GIC_REGS_Distributor__37_GICD_IROUTER124_upper,GICD_IROUTER124_upper" line.long 0x2E8 "GIC_REGS_Distributor__37_GICD_IROUTER125_lower,GICD_IROUTER125_lower" bitfld.long 0x2E8 31. "DISTRIBUTOR__37_GICD_IROUTER125_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x2E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER125_LOWER__8_8,A1" newline hexmask.long.byte 0x2E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER125_LOWER__0_8,A0" line.long 0x2EC "GIC_REGS_Distributor__37_GICD_IROUTER125_upper,GICD_IROUTER125_upper" line.long 0x2F0 "GIC_REGS_Distributor__37_GICD_IROUTER126_lower,GICD_IROUTER126_lower" bitfld.long 0x2F0 31. "DISTRIBUTOR__37_GICD_IROUTER126_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x2F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER126_LOWER__8_8,A1" newline hexmask.long.byte 0x2F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER126_LOWER__0_8,A0" line.long 0x2F4 "GIC_REGS_Distributor__37_GICD_IROUTER126_upper,GICD_IROUTER126_upper" line.long 0x2F8 "GIC_REGS_Distributor__37_GICD_IROUTER127_lower,GICD_IROUTER127_lower" bitfld.long 0x2F8 31. "DISTRIBUTOR__37_GICD_IROUTER127_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x2F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER127_LOWER__8_8,A1" newline hexmask.long.byte 0x2F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER127_LOWER__0_8,A0" line.long 0x2FC "GIC_REGS_Distributor__37_GICD_IROUTER127_upper,GICD_IROUTER127_upper" line.long 0x300 "GIC_REGS_Distributor__37_GICD_IROUTER128_lower,GICD_IROUTER128_lower" bitfld.long 0x300 31. "DISTRIBUTOR__37_GICD_IROUTER128_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x300 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER128_LOWER__8_8,A1" newline hexmask.long.byte 0x300 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER128_LOWER__0_8,A0" line.long 0x304 "GIC_REGS_Distributor__37_GICD_IROUTER128_upper,GICD_IROUTER128_upper" line.long 0x308 "GIC_REGS_Distributor__37_GICD_IROUTER129_lower,GICD_IROUTER129_lower" bitfld.long 0x308 31. "DISTRIBUTOR__37_GICD_IROUTER129_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x308 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER129_LOWER__8_8,A1" newline hexmask.long.byte 0x308 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER129_LOWER__0_8,A0" line.long 0x30C "GIC_REGS_Distributor__37_GICD_IROUTER129_upper,GICD_IROUTER129_upper" line.long 0x310 "GIC_REGS_Distributor__37_GICD_IROUTER130_lower,GICD_IROUTER130_lower" bitfld.long 0x310 31. "DISTRIBUTOR__37_GICD_IROUTER130_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x310 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER130_LOWER__8_8,A1" newline hexmask.long.byte 0x310 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER130_LOWER__0_8,A0" line.long 0x314 "GIC_REGS_Distributor__37_GICD_IROUTER130_upper,GICD_IROUTER130_upper" line.long 0x318 "GIC_REGS_Distributor__37_GICD_IROUTER131_lower,GICD_IROUTER131_lower" bitfld.long 0x318 31. "DISTRIBUTOR__37_GICD_IROUTER131_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x318 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER131_LOWER__8_8,A1" newline hexmask.long.byte 0x318 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER131_LOWER__0_8,A0" line.long 0x31C "GIC_REGS_Distributor__37_GICD_IROUTER131_upper,GICD_IROUTER131_upper" line.long 0x320 "GIC_REGS_Distributor__37_GICD_IROUTER132_lower,GICD_IROUTER132_lower" bitfld.long 0x320 31. "DISTRIBUTOR__37_GICD_IROUTER132_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x320 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER132_LOWER__8_8,A1" newline hexmask.long.byte 0x320 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER132_LOWER__0_8,A0" line.long 0x324 "GIC_REGS_Distributor__37_GICD_IROUTER132_upper,GICD_IROUTER132_upper" line.long 0x328 "GIC_REGS_Distributor__37_GICD_IROUTER133_lower,GICD_IROUTER133_lower" bitfld.long 0x328 31. "DISTRIBUTOR__37_GICD_IROUTER133_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x328 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER133_LOWER__8_8,A1" newline hexmask.long.byte 0x328 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER133_LOWER__0_8,A0" line.long 0x32C "GIC_REGS_Distributor__37_GICD_IROUTER133_upper,GICD_IROUTER133_upper" line.long 0x330 "GIC_REGS_Distributor__37_GICD_IROUTER134_lower,GICD_IROUTER134_lower" bitfld.long 0x330 31. "DISTRIBUTOR__37_GICD_IROUTER134_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x330 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER134_LOWER__8_8,A1" newline hexmask.long.byte 0x330 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER134_LOWER__0_8,A0" line.long 0x334 "GIC_REGS_Distributor__37_GICD_IROUTER134_upper,GICD_IROUTER134_upper" line.long 0x338 "GIC_REGS_Distributor__37_GICD_IROUTER135_lower,GICD_IROUTER135_lower" bitfld.long 0x338 31. "DISTRIBUTOR__37_GICD_IROUTER135_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x338 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER135_LOWER__8_8,A1" newline hexmask.long.byte 0x338 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER135_LOWER__0_8,A0" line.long 0x33C "GIC_REGS_Distributor__37_GICD_IROUTER135_upper,GICD_IROUTER135_upper" line.long 0x340 "GIC_REGS_Distributor__37_GICD_IROUTER136_lower,GICD_IROUTER136_lower" bitfld.long 0x340 31. "DISTRIBUTOR__37_GICD_IROUTER136_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x340 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER136_LOWER__8_8,A1" newline hexmask.long.byte 0x340 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER136_LOWER__0_8,A0" line.long 0x344 "GIC_REGS_Distributor__37_GICD_IROUTER136_upper,GICD_IROUTER136_upper" line.long 0x348 "GIC_REGS_Distributor__37_GICD_IROUTER137_lower,GICD_IROUTER137_lower" bitfld.long 0x348 31. "DISTRIBUTOR__37_GICD_IROUTER137_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x348 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER137_LOWER__8_8,A1" newline hexmask.long.byte 0x348 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER137_LOWER__0_8,A0" line.long 0x34C "GIC_REGS_Distributor__37_GICD_IROUTER137_upper,GICD_IROUTER137_upper" line.long 0x350 "GIC_REGS_Distributor__37_GICD_IROUTER138_lower,GICD_IROUTER138_lower" bitfld.long 0x350 31. "DISTRIBUTOR__37_GICD_IROUTER138_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x350 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER138_LOWER__8_8,A1" newline hexmask.long.byte 0x350 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER138_LOWER__0_8,A0" line.long 0x354 "GIC_REGS_Distributor__37_GICD_IROUTER138_upper,GICD_IROUTER138_upper" line.long 0x358 "GIC_REGS_Distributor__37_GICD_IROUTER139_lower,GICD_IROUTER139_lower" bitfld.long 0x358 31. "DISTRIBUTOR__37_GICD_IROUTER139_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x358 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER139_LOWER__8_8,A1" newline hexmask.long.byte 0x358 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER139_LOWER__0_8,A0" line.long 0x35C "GIC_REGS_Distributor__37_GICD_IROUTER139_upper,GICD_IROUTER139_upper" line.long 0x360 "GIC_REGS_Distributor__37_GICD_IROUTER140_lower,GICD_IROUTER140_lower" bitfld.long 0x360 31. "DISTRIBUTOR__37_GICD_IROUTER140_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x360 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER140_LOWER__8_8,A1" newline hexmask.long.byte 0x360 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER140_LOWER__0_8,A0" line.long 0x364 "GIC_REGS_Distributor__37_GICD_IROUTER140_upper,GICD_IROUTER140_upper" line.long 0x368 "GIC_REGS_Distributor__37_GICD_IROUTER141_lower,GICD_IROUTER141_lower" bitfld.long 0x368 31. "DISTRIBUTOR__37_GICD_IROUTER141_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x368 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER141_LOWER__8_8,A1" newline hexmask.long.byte 0x368 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER141_LOWER__0_8,A0" line.long 0x36C "GIC_REGS_Distributor__37_GICD_IROUTER141_upper,GICD_IROUTER141_upper" line.long 0x370 "GIC_REGS_Distributor__37_GICD_IROUTER142_lower,GICD_IROUTER142_lower" bitfld.long 0x370 31. "DISTRIBUTOR__37_GICD_IROUTER142_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x370 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER142_LOWER__8_8,A1" newline hexmask.long.byte 0x370 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER142_LOWER__0_8,A0" line.long 0x374 "GIC_REGS_Distributor__37_GICD_IROUTER142_upper,GICD_IROUTER142_upper" line.long 0x378 "GIC_REGS_Distributor__37_GICD_IROUTER143_lower,GICD_IROUTER143_lower" bitfld.long 0x378 31. "DISTRIBUTOR__37_GICD_IROUTER143_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x378 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER143_LOWER__8_8,A1" newline hexmask.long.byte 0x378 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER143_LOWER__0_8,A0" line.long 0x37C "GIC_REGS_Distributor__37_GICD_IROUTER143_upper,GICD_IROUTER143_upper" line.long 0x380 "GIC_REGS_Distributor__37_GICD_IROUTER144_lower,GICD_IROUTER144_lower" bitfld.long 0x380 31. "DISTRIBUTOR__37_GICD_IROUTER144_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x380 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER144_LOWER__8_8,A1" newline hexmask.long.byte 0x380 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER144_LOWER__0_8,A0" line.long 0x384 "GIC_REGS_Distributor__37_GICD_IROUTER144_upper,GICD_IROUTER144_upper" line.long 0x388 "GIC_REGS_Distributor__37_GICD_IROUTER145_lower,GICD_IROUTER145_lower" bitfld.long 0x388 31. "DISTRIBUTOR__37_GICD_IROUTER145_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x388 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER145_LOWER__8_8,A1" newline hexmask.long.byte 0x388 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER145_LOWER__0_8,A0" line.long 0x38C "GIC_REGS_Distributor__37_GICD_IROUTER145_upper,GICD_IROUTER145_upper" line.long 0x390 "GIC_REGS_Distributor__37_GICD_IROUTER146_lower,GICD_IROUTER146_lower" bitfld.long 0x390 31. "DISTRIBUTOR__37_GICD_IROUTER146_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x390 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER146_LOWER__8_8,A1" newline hexmask.long.byte 0x390 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER146_LOWER__0_8,A0" line.long 0x394 "GIC_REGS_Distributor__37_GICD_IROUTER146_upper,GICD_IROUTER146_upper" line.long 0x398 "GIC_REGS_Distributor__37_GICD_IROUTER147_lower,GICD_IROUTER147_lower" bitfld.long 0x398 31. "DISTRIBUTOR__37_GICD_IROUTER147_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x398 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER147_LOWER__8_8,A1" newline hexmask.long.byte 0x398 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER147_LOWER__0_8,A0" line.long 0x39C "GIC_REGS_Distributor__37_GICD_IROUTER147_upper,GICD_IROUTER147_upper" line.long 0x3A0 "GIC_REGS_Distributor__37_GICD_IROUTER148_lower,GICD_IROUTER148_lower" bitfld.long 0x3A0 31. "DISTRIBUTOR__37_GICD_IROUTER148_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x3A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER148_LOWER__8_8,A1" newline hexmask.long.byte 0x3A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER148_LOWER__0_8,A0" line.long 0x3A4 "GIC_REGS_Distributor__37_GICD_IROUTER148_upper,GICD_IROUTER148_upper" line.long 0x3A8 "GIC_REGS_Distributor__37_GICD_IROUTER149_lower,GICD_IROUTER149_lower" bitfld.long 0x3A8 31. "DISTRIBUTOR__37_GICD_IROUTER149_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x3A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER149_LOWER__8_8,A1" newline hexmask.long.byte 0x3A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER149_LOWER__0_8,A0" line.long 0x3AC "GIC_REGS_Distributor__37_GICD_IROUTER149_upper,GICD_IROUTER149_upper" line.long 0x3B0 "GIC_REGS_Distributor__37_GICD_IROUTER150_lower,GICD_IROUTER150_lower" bitfld.long 0x3B0 31. "DISTRIBUTOR__37_GICD_IROUTER150_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x3B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER150_LOWER__8_8,A1" newline hexmask.long.byte 0x3B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER150_LOWER__0_8,A0" line.long 0x3B4 "GIC_REGS_Distributor__37_GICD_IROUTER150_upper,GICD_IROUTER150_upper" line.long 0x3B8 "GIC_REGS_Distributor__37_GICD_IROUTER151_lower,GICD_IROUTER151_lower" bitfld.long 0x3B8 31. "DISTRIBUTOR__37_GICD_IROUTER151_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x3B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER151_LOWER__8_8,A1" newline hexmask.long.byte 0x3B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER151_LOWER__0_8,A0" line.long 0x3BC "GIC_REGS_Distributor__37_GICD_IROUTER151_upper,GICD_IROUTER151_upper" line.long 0x3C0 "GIC_REGS_Distributor__37_GICD_IROUTER152_lower,GICD_IROUTER152_lower" bitfld.long 0x3C0 31. "DISTRIBUTOR__37_GICD_IROUTER152_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x3C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER152_LOWER__8_8,A1" newline hexmask.long.byte 0x3C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER152_LOWER__0_8,A0" line.long 0x3C4 "GIC_REGS_Distributor__37_GICD_IROUTER152_upper,GICD_IROUTER152_upper" line.long 0x3C8 "GIC_REGS_Distributor__37_GICD_IROUTER153_lower,GICD_IROUTER153_lower" bitfld.long 0x3C8 31. "DISTRIBUTOR__37_GICD_IROUTER153_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x3C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER153_LOWER__8_8,A1" newline hexmask.long.byte 0x3C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER153_LOWER__0_8,A0" line.long 0x3CC "GIC_REGS_Distributor__37_GICD_IROUTER153_upper,GICD_IROUTER153_upper" line.long 0x3D0 "GIC_REGS_Distributor__37_GICD_IROUTER154_lower,GICD_IROUTER154_lower" bitfld.long 0x3D0 31. "DISTRIBUTOR__37_GICD_IROUTER154_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x3D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER154_LOWER__8_8,A1" newline hexmask.long.byte 0x3D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER154_LOWER__0_8,A0" line.long 0x3D4 "GIC_REGS_Distributor__37_GICD_IROUTER154_upper,GICD_IROUTER154_upper" line.long 0x3D8 "GIC_REGS_Distributor__37_GICD_IROUTER155_lower,GICD_IROUTER155_lower" bitfld.long 0x3D8 31. "DISTRIBUTOR__37_GICD_IROUTER155_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x3D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER155_LOWER__8_8,A1" newline hexmask.long.byte 0x3D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER155_LOWER__0_8,A0" line.long 0x3DC "GIC_REGS_Distributor__37_GICD_IROUTER155_upper,GICD_IROUTER155_upper" line.long 0x3E0 "GIC_REGS_Distributor__37_GICD_IROUTER156_lower,GICD_IROUTER156_lower" bitfld.long 0x3E0 31. "DISTRIBUTOR__37_GICD_IROUTER156_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x3E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER156_LOWER__8_8,A1" newline hexmask.long.byte 0x3E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER156_LOWER__0_8,A0" line.long 0x3E4 "GIC_REGS_Distributor__37_GICD_IROUTER156_upper,GICD_IROUTER156_upper" line.long 0x3E8 "GIC_REGS_Distributor__37_GICD_IROUTER157_lower,GICD_IROUTER157_lower" bitfld.long 0x3E8 31. "DISTRIBUTOR__37_GICD_IROUTER157_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x3E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER157_LOWER__8_8,A1" newline hexmask.long.byte 0x3E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER157_LOWER__0_8,A0" line.long 0x3EC "GIC_REGS_Distributor__37_GICD_IROUTER157_upper,GICD_IROUTER157_upper" line.long 0x3F0 "GIC_REGS_Distributor__37_GICD_IROUTER158_lower,GICD_IROUTER158_lower" bitfld.long 0x3F0 31. "DISTRIBUTOR__37_GICD_IROUTER158_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x3F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER158_LOWER__8_8,A1" newline hexmask.long.byte 0x3F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER158_LOWER__0_8,A0" line.long 0x3F4 "GIC_REGS_Distributor__37_GICD_IROUTER158_upper,GICD_IROUTER158_upper" line.long 0x3F8 "GIC_REGS_Distributor__37_GICD_IROUTER159_lower,GICD_IROUTER159_lower" bitfld.long 0x3F8 31. "DISTRIBUTOR__37_GICD_IROUTER159_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x3F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER159_LOWER__8_8,A1" newline hexmask.long.byte 0x3F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER159_LOWER__0_8,A0" line.long 0x3FC "GIC_REGS_Distributor__37_GICD_IROUTER159_upper,GICD_IROUTER159_upper" line.long 0x400 "GIC_REGS_Distributor__37_GICD_IROUTER160_lower,GICD_IROUTER160_lower" bitfld.long 0x400 31. "DISTRIBUTOR__37_GICD_IROUTER160_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x400 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER160_LOWER__8_8,A1" newline hexmask.long.byte 0x400 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER160_LOWER__0_8,A0" line.long 0x404 "GIC_REGS_Distributor__37_GICD_IROUTER160_upper,GICD_IROUTER160_upper" line.long 0x408 "GIC_REGS_Distributor__37_GICD_IROUTER161_lower,GICD_IROUTER161_lower" bitfld.long 0x408 31. "DISTRIBUTOR__37_GICD_IROUTER161_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x408 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER161_LOWER__8_8,A1" newline hexmask.long.byte 0x408 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER161_LOWER__0_8,A0" line.long 0x40C "GIC_REGS_Distributor__37_GICD_IROUTER161_upper,GICD_IROUTER161_upper" line.long 0x410 "GIC_REGS_Distributor__37_GICD_IROUTER162_lower,GICD_IROUTER162_lower" bitfld.long 0x410 31. "DISTRIBUTOR__37_GICD_IROUTER162_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x410 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER162_LOWER__8_8,A1" newline hexmask.long.byte 0x410 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER162_LOWER__0_8,A0" line.long 0x414 "GIC_REGS_Distributor__37_GICD_IROUTER162_upper,GICD_IROUTER162_upper" line.long 0x418 "GIC_REGS_Distributor__37_GICD_IROUTER163_lower,GICD_IROUTER163_lower" bitfld.long 0x418 31. "DISTRIBUTOR__37_GICD_IROUTER163_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x418 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER163_LOWER__8_8,A1" newline hexmask.long.byte 0x418 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER163_LOWER__0_8,A0" line.long 0x41C "GIC_REGS_Distributor__37_GICD_IROUTER163_upper,GICD_IROUTER163_upper" line.long 0x420 "GIC_REGS_Distributor__37_GICD_IROUTER164_lower,GICD_IROUTER164_lower" bitfld.long 0x420 31. "DISTRIBUTOR__37_GICD_IROUTER164_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x420 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER164_LOWER__8_8,A1" newline hexmask.long.byte 0x420 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER164_LOWER__0_8,A0" line.long 0x424 "GIC_REGS_Distributor__37_GICD_IROUTER164_upper,GICD_IROUTER164_upper" line.long 0x428 "GIC_REGS_Distributor__37_GICD_IROUTER165_lower,GICD_IROUTER165_lower" bitfld.long 0x428 31. "DISTRIBUTOR__37_GICD_IROUTER165_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x428 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER165_LOWER__8_8,A1" newline hexmask.long.byte 0x428 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER165_LOWER__0_8,A0" line.long 0x42C "GIC_REGS_Distributor__37_GICD_IROUTER165_upper,GICD_IROUTER165_upper" line.long 0x430 "GIC_REGS_Distributor__37_GICD_IROUTER166_lower,GICD_IROUTER166_lower" bitfld.long 0x430 31. "DISTRIBUTOR__37_GICD_IROUTER166_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x430 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER166_LOWER__8_8,A1" newline hexmask.long.byte 0x430 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER166_LOWER__0_8,A0" line.long 0x434 "GIC_REGS_Distributor__37_GICD_IROUTER166_upper,GICD_IROUTER166_upper" line.long 0x438 "GIC_REGS_Distributor__37_GICD_IROUTER167_lower,GICD_IROUTER167_lower" bitfld.long 0x438 31. "DISTRIBUTOR__37_GICD_IROUTER167_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x438 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER167_LOWER__8_8,A1" newline hexmask.long.byte 0x438 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER167_LOWER__0_8,A0" line.long 0x43C "GIC_REGS_Distributor__37_GICD_IROUTER167_upper,GICD_IROUTER167_upper" line.long 0x440 "GIC_REGS_Distributor__37_GICD_IROUTER168_lower,GICD_IROUTER168_lower" bitfld.long 0x440 31. "DISTRIBUTOR__37_GICD_IROUTER168_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x440 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER168_LOWER__8_8,A1" newline hexmask.long.byte 0x440 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER168_LOWER__0_8,A0" line.long 0x444 "GIC_REGS_Distributor__37_GICD_IROUTER168_upper,GICD_IROUTER168_upper" line.long 0x448 "GIC_REGS_Distributor__37_GICD_IROUTER169_lower,GICD_IROUTER169_lower" bitfld.long 0x448 31. "DISTRIBUTOR__37_GICD_IROUTER169_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x448 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER169_LOWER__8_8,A1" newline hexmask.long.byte 0x448 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER169_LOWER__0_8,A0" line.long 0x44C "GIC_REGS_Distributor__37_GICD_IROUTER169_upper,GICD_IROUTER169_upper" line.long 0x450 "GIC_REGS_Distributor__37_GICD_IROUTER170_lower,GICD_IROUTER170_lower" bitfld.long 0x450 31. "DISTRIBUTOR__37_GICD_IROUTER170_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x450 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER170_LOWER__8_8,A1" newline hexmask.long.byte 0x450 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER170_LOWER__0_8,A0" line.long 0x454 "GIC_REGS_Distributor__37_GICD_IROUTER170_upper,GICD_IROUTER170_upper" line.long 0x458 "GIC_REGS_Distributor__37_GICD_IROUTER171_lower,GICD_IROUTER171_lower" bitfld.long 0x458 31. "DISTRIBUTOR__37_GICD_IROUTER171_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x458 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER171_LOWER__8_8,A1" newline hexmask.long.byte 0x458 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER171_LOWER__0_8,A0" line.long 0x45C "GIC_REGS_Distributor__37_GICD_IROUTER171_upper,GICD_IROUTER171_upper" line.long 0x460 "GIC_REGS_Distributor__37_GICD_IROUTER172_lower,GICD_IROUTER172_lower" bitfld.long 0x460 31. "DISTRIBUTOR__37_GICD_IROUTER172_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x460 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER172_LOWER__8_8,A1" newline hexmask.long.byte 0x460 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER172_LOWER__0_8,A0" line.long 0x464 "GIC_REGS_Distributor__37_GICD_IROUTER172_upper,GICD_IROUTER172_upper" line.long 0x468 "GIC_REGS_Distributor__37_GICD_IROUTER173_lower,GICD_IROUTER173_lower" bitfld.long 0x468 31. "DISTRIBUTOR__37_GICD_IROUTER173_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x468 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER173_LOWER__8_8,A1" newline hexmask.long.byte 0x468 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER173_LOWER__0_8,A0" line.long 0x46C "GIC_REGS_Distributor__37_GICD_IROUTER173_upper,GICD_IROUTER173_upper" line.long 0x470 "GIC_REGS_Distributor__37_GICD_IROUTER174_lower,GICD_IROUTER174_lower" bitfld.long 0x470 31. "DISTRIBUTOR__37_GICD_IROUTER174_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x470 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER174_LOWER__8_8,A1" newline hexmask.long.byte 0x470 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER174_LOWER__0_8,A0" line.long 0x474 "GIC_REGS_Distributor__37_GICD_IROUTER174_upper,GICD_IROUTER174_upper" line.long 0x478 "GIC_REGS_Distributor__37_GICD_IROUTER175_lower,GICD_IROUTER175_lower" bitfld.long 0x478 31. "DISTRIBUTOR__37_GICD_IROUTER175_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x478 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER175_LOWER__8_8,A1" newline hexmask.long.byte 0x478 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER175_LOWER__0_8,A0" line.long 0x47C "GIC_REGS_Distributor__37_GICD_IROUTER175_upper,GICD_IROUTER175_upper" line.long 0x480 "GIC_REGS_Distributor__37_GICD_IROUTER176_lower,GICD_IROUTER176_lower" bitfld.long 0x480 31. "DISTRIBUTOR__37_GICD_IROUTER176_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x480 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER176_LOWER__8_8,A1" newline hexmask.long.byte 0x480 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER176_LOWER__0_8,A0" line.long 0x484 "GIC_REGS_Distributor__37_GICD_IROUTER176_upper,GICD_IROUTER176_upper" line.long 0x488 "GIC_REGS_Distributor__37_GICD_IROUTER177_lower,GICD_IROUTER177_lower" bitfld.long 0x488 31. "DISTRIBUTOR__37_GICD_IROUTER177_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x488 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER177_LOWER__8_8,A1" newline hexmask.long.byte 0x488 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER177_LOWER__0_8,A0" line.long 0x48C "GIC_REGS_Distributor__37_GICD_IROUTER177_upper,GICD_IROUTER177_upper" line.long 0x490 "GIC_REGS_Distributor__37_GICD_IROUTER178_lower,GICD_IROUTER178_lower" bitfld.long 0x490 31. "DISTRIBUTOR__37_GICD_IROUTER178_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x490 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER178_LOWER__8_8,A1" newline hexmask.long.byte 0x490 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER178_LOWER__0_8,A0" line.long 0x494 "GIC_REGS_Distributor__37_GICD_IROUTER178_upper,GICD_IROUTER178_upper" line.long 0x498 "GIC_REGS_Distributor__37_GICD_IROUTER179_lower,GICD_IROUTER179_lower" bitfld.long 0x498 31. "DISTRIBUTOR__37_GICD_IROUTER179_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x498 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER179_LOWER__8_8,A1" newline hexmask.long.byte 0x498 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER179_LOWER__0_8,A0" line.long 0x49C "GIC_REGS_Distributor__37_GICD_IROUTER179_upper,GICD_IROUTER179_upper" line.long 0x4A0 "GIC_REGS_Distributor__37_GICD_IROUTER180_lower,GICD_IROUTER180_lower" bitfld.long 0x4A0 31. "DISTRIBUTOR__37_GICD_IROUTER180_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x4A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER180_LOWER__8_8,A1" newline hexmask.long.byte 0x4A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER180_LOWER__0_8,A0" line.long 0x4A4 "GIC_REGS_Distributor__37_GICD_IROUTER180_upper,GICD_IROUTER180_upper" line.long 0x4A8 "GIC_REGS_Distributor__37_GICD_IROUTER181_lower,GICD_IROUTER181_lower" bitfld.long 0x4A8 31. "DISTRIBUTOR__37_GICD_IROUTER181_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x4A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER181_LOWER__8_8,A1" newline hexmask.long.byte 0x4A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER181_LOWER__0_8,A0" line.long 0x4AC "GIC_REGS_Distributor__37_GICD_IROUTER181_upper,GICD_IROUTER181_upper" line.long 0x4B0 "GIC_REGS_Distributor__37_GICD_IROUTER182_lower,GICD_IROUTER182_lower" bitfld.long 0x4B0 31. "DISTRIBUTOR__37_GICD_IROUTER182_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x4B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER182_LOWER__8_8,A1" newline hexmask.long.byte 0x4B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER182_LOWER__0_8,A0" line.long 0x4B4 "GIC_REGS_Distributor__37_GICD_IROUTER182_upper,GICD_IROUTER182_upper" line.long 0x4B8 "GIC_REGS_Distributor__37_GICD_IROUTER183_lower,GICD_IROUTER183_lower" bitfld.long 0x4B8 31. "DISTRIBUTOR__37_GICD_IROUTER183_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x4B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER183_LOWER__8_8,A1" newline hexmask.long.byte 0x4B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER183_LOWER__0_8,A0" line.long 0x4BC "GIC_REGS_Distributor__37_GICD_IROUTER183_upper,GICD_IROUTER183_upper" line.long 0x4C0 "GIC_REGS_Distributor__37_GICD_IROUTER184_lower,GICD_IROUTER184_lower" bitfld.long 0x4C0 31. "DISTRIBUTOR__37_GICD_IROUTER184_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x4C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER184_LOWER__8_8,A1" newline hexmask.long.byte 0x4C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER184_LOWER__0_8,A0" line.long 0x4C4 "GIC_REGS_Distributor__37_GICD_IROUTER184_upper,GICD_IROUTER184_upper" line.long 0x4C8 "GIC_REGS_Distributor__37_GICD_IROUTER185_lower,GICD_IROUTER185_lower" bitfld.long 0x4C8 31. "DISTRIBUTOR__37_GICD_IROUTER185_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x4C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER185_LOWER__8_8,A1" newline hexmask.long.byte 0x4C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER185_LOWER__0_8,A0" line.long 0x4CC "GIC_REGS_Distributor__37_GICD_IROUTER185_upper,GICD_IROUTER185_upper" line.long 0x4D0 "GIC_REGS_Distributor__37_GICD_IROUTER186_lower,GICD_IROUTER186_lower" bitfld.long 0x4D0 31. "DISTRIBUTOR__37_GICD_IROUTER186_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x4D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER186_LOWER__8_8,A1" newline hexmask.long.byte 0x4D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER186_LOWER__0_8,A0" line.long 0x4D4 "GIC_REGS_Distributor__37_GICD_IROUTER186_upper,GICD_IROUTER186_upper" line.long 0x4D8 "GIC_REGS_Distributor__37_GICD_IROUTER187_lower,GICD_IROUTER187_lower" bitfld.long 0x4D8 31. "DISTRIBUTOR__37_GICD_IROUTER187_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x4D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER187_LOWER__8_8,A1" newline hexmask.long.byte 0x4D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER187_LOWER__0_8,A0" line.long 0x4DC "GIC_REGS_Distributor__37_GICD_IROUTER187_upper,GICD_IROUTER187_upper" line.long 0x4E0 "GIC_REGS_Distributor__37_GICD_IROUTER188_lower,GICD_IROUTER188_lower" bitfld.long 0x4E0 31. "DISTRIBUTOR__37_GICD_IROUTER188_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x4E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER188_LOWER__8_8,A1" newline hexmask.long.byte 0x4E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER188_LOWER__0_8,A0" line.long 0x4E4 "GIC_REGS_Distributor__37_GICD_IROUTER188_upper,GICD_IROUTER188_upper" line.long 0x4E8 "GIC_REGS_Distributor__37_GICD_IROUTER189_lower,GICD_IROUTER189_lower" bitfld.long 0x4E8 31. "DISTRIBUTOR__37_GICD_IROUTER189_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x4E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER189_LOWER__8_8,A1" newline hexmask.long.byte 0x4E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER189_LOWER__0_8,A0" line.long 0x4EC "GIC_REGS_Distributor__37_GICD_IROUTER189_upper,GICD_IROUTER189_upper" line.long 0x4F0 "GIC_REGS_Distributor__37_GICD_IROUTER190_lower,GICD_IROUTER190_lower" bitfld.long 0x4F0 31. "DISTRIBUTOR__37_GICD_IROUTER190_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x4F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER190_LOWER__8_8,A1" newline hexmask.long.byte 0x4F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER190_LOWER__0_8,A0" line.long 0x4F4 "GIC_REGS_Distributor__37_GICD_IROUTER190_upper,GICD_IROUTER190_upper" line.long 0x4F8 "GIC_REGS_Distributor__37_GICD_IROUTER191_lower,GICD_IROUTER191_lower" bitfld.long 0x4F8 31. "DISTRIBUTOR__37_GICD_IROUTER191_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x4F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER191_LOWER__8_8,A1" newline hexmask.long.byte 0x4F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER191_LOWER__0_8,A0" line.long 0x4FC "GIC_REGS_Distributor__37_GICD_IROUTER191_upper,GICD_IROUTER191_upper" line.long 0x500 "GIC_REGS_Distributor__37_GICD_IROUTER192_lower,GICD_IROUTER192_lower" bitfld.long 0x500 31. "DISTRIBUTOR__37_GICD_IROUTER192_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x500 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER192_LOWER__8_8,A1" newline hexmask.long.byte 0x500 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER192_LOWER__0_8,A0" line.long 0x504 "GIC_REGS_Distributor__37_GICD_IROUTER192_upper,GICD_IROUTER192_upper" line.long 0x508 "GIC_REGS_Distributor__37_GICD_IROUTER193_lower,GICD_IROUTER193_lower" bitfld.long 0x508 31. "DISTRIBUTOR__37_GICD_IROUTER193_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x508 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER193_LOWER__8_8,A1" newline hexmask.long.byte 0x508 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER193_LOWER__0_8,A0" line.long 0x50C "GIC_REGS_Distributor__37_GICD_IROUTER193_upper,GICD_IROUTER193_upper" line.long 0x510 "GIC_REGS_Distributor__37_GICD_IROUTER194_lower,GICD_IROUTER194_lower" bitfld.long 0x510 31. "DISTRIBUTOR__37_GICD_IROUTER194_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x510 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER194_LOWER__8_8,A1" newline hexmask.long.byte 0x510 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER194_LOWER__0_8,A0" line.long 0x514 "GIC_REGS_Distributor__37_GICD_IROUTER194_upper,GICD_IROUTER194_upper" line.long 0x518 "GIC_REGS_Distributor__37_GICD_IROUTER195_lower,GICD_IROUTER195_lower" bitfld.long 0x518 31. "DISTRIBUTOR__37_GICD_IROUTER195_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x518 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER195_LOWER__8_8,A1" newline hexmask.long.byte 0x518 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER195_LOWER__0_8,A0" line.long 0x51C "GIC_REGS_Distributor__37_GICD_IROUTER195_upper,GICD_IROUTER195_upper" line.long 0x520 "GIC_REGS_Distributor__37_GICD_IROUTER196_lower,GICD_IROUTER196_lower" bitfld.long 0x520 31. "DISTRIBUTOR__37_GICD_IROUTER196_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x520 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER196_LOWER__8_8,A1" newline hexmask.long.byte 0x520 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER196_LOWER__0_8,A0" line.long 0x524 "GIC_REGS_Distributor__37_GICD_IROUTER196_upper,GICD_IROUTER196_upper" line.long 0x528 "GIC_REGS_Distributor__37_GICD_IROUTER197_lower,GICD_IROUTER197_lower" bitfld.long 0x528 31. "DISTRIBUTOR__37_GICD_IROUTER197_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x528 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER197_LOWER__8_8,A1" newline hexmask.long.byte 0x528 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER197_LOWER__0_8,A0" line.long 0x52C "GIC_REGS_Distributor__37_GICD_IROUTER197_upper,GICD_IROUTER197_upper" line.long 0x530 "GIC_REGS_Distributor__37_GICD_IROUTER198_lower,GICD_IROUTER198_lower" bitfld.long 0x530 31. "DISTRIBUTOR__37_GICD_IROUTER198_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x530 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER198_LOWER__8_8,A1" newline hexmask.long.byte 0x530 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER198_LOWER__0_8,A0" line.long 0x534 "GIC_REGS_Distributor__37_GICD_IROUTER198_upper,GICD_IROUTER198_upper" line.long 0x538 "GIC_REGS_Distributor__37_GICD_IROUTER199_lower,GICD_IROUTER199_lower" bitfld.long 0x538 31. "DISTRIBUTOR__37_GICD_IROUTER199_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x538 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER199_LOWER__8_8,A1" newline hexmask.long.byte 0x538 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER199_LOWER__0_8,A0" line.long 0x53C "GIC_REGS_Distributor__37_GICD_IROUTER199_upper,GICD_IROUTER199_upper" line.long 0x540 "GIC_REGS_Distributor__37_GICD_IROUTER200_lower,GICD_IROUTER200_lower" bitfld.long 0x540 31. "DISTRIBUTOR__37_GICD_IROUTER200_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x540 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER200_LOWER__8_8,A1" newline hexmask.long.byte 0x540 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER200_LOWER__0_8,A0" line.long 0x544 "GIC_REGS_Distributor__37_GICD_IROUTER200_upper,GICD_IROUTER200_upper" line.long 0x548 "GIC_REGS_Distributor__37_GICD_IROUTER201_lower,GICD_IROUTER201_lower" bitfld.long 0x548 31. "DISTRIBUTOR__37_GICD_IROUTER201_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x548 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER201_LOWER__8_8,A1" newline hexmask.long.byte 0x548 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER201_LOWER__0_8,A0" line.long 0x54C "GIC_REGS_Distributor__37_GICD_IROUTER201_upper,GICD_IROUTER201_upper" line.long 0x550 "GIC_REGS_Distributor__37_GICD_IROUTER202_lower,GICD_IROUTER202_lower" bitfld.long 0x550 31. "DISTRIBUTOR__37_GICD_IROUTER202_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x550 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER202_LOWER__8_8,A1" newline hexmask.long.byte 0x550 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER202_LOWER__0_8,A0" line.long 0x554 "GIC_REGS_Distributor__37_GICD_IROUTER202_upper,GICD_IROUTER202_upper" line.long 0x558 "GIC_REGS_Distributor__37_GICD_IROUTER203_lower,GICD_IROUTER203_lower" bitfld.long 0x558 31. "DISTRIBUTOR__37_GICD_IROUTER203_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x558 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER203_LOWER__8_8,A1" newline hexmask.long.byte 0x558 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER203_LOWER__0_8,A0" line.long 0x55C "GIC_REGS_Distributor__37_GICD_IROUTER203_upper,GICD_IROUTER203_upper" line.long 0x560 "GIC_REGS_Distributor__37_GICD_IROUTER204_lower,GICD_IROUTER204_lower" bitfld.long 0x560 31. "DISTRIBUTOR__37_GICD_IROUTER204_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x560 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER204_LOWER__8_8,A1" newline hexmask.long.byte 0x560 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER204_LOWER__0_8,A0" line.long 0x564 "GIC_REGS_Distributor__37_GICD_IROUTER204_upper,GICD_IROUTER204_upper" line.long 0x568 "GIC_REGS_Distributor__37_GICD_IROUTER205_lower,GICD_IROUTER205_lower" bitfld.long 0x568 31. "DISTRIBUTOR__37_GICD_IROUTER205_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x568 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER205_LOWER__8_8,A1" newline hexmask.long.byte 0x568 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER205_LOWER__0_8,A0" line.long 0x56C "GIC_REGS_Distributor__37_GICD_IROUTER205_upper,GICD_IROUTER205_upper" line.long 0x570 "GIC_REGS_Distributor__37_GICD_IROUTER206_lower,GICD_IROUTER206_lower" bitfld.long 0x570 31. "DISTRIBUTOR__37_GICD_IROUTER206_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x570 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER206_LOWER__8_8,A1" newline hexmask.long.byte 0x570 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER206_LOWER__0_8,A0" line.long 0x574 "GIC_REGS_Distributor__37_GICD_IROUTER206_upper,GICD_IROUTER206_upper" line.long 0x578 "GIC_REGS_Distributor__37_GICD_IROUTER207_lower,GICD_IROUTER207_lower" bitfld.long 0x578 31. "DISTRIBUTOR__37_GICD_IROUTER207_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x578 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER207_LOWER__8_8,A1" newline hexmask.long.byte 0x578 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER207_LOWER__0_8,A0" line.long 0x57C "GIC_REGS_Distributor__37_GICD_IROUTER207_upper,GICD_IROUTER207_upper" line.long 0x580 "GIC_REGS_Distributor__37_GICD_IROUTER208_lower,GICD_IROUTER208_lower" bitfld.long 0x580 31. "DISTRIBUTOR__37_GICD_IROUTER208_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x580 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER208_LOWER__8_8,A1" newline hexmask.long.byte 0x580 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER208_LOWER__0_8,A0" line.long 0x584 "GIC_REGS_Distributor__37_GICD_IROUTER208_upper,GICD_IROUTER208_upper" line.long 0x588 "GIC_REGS_Distributor__37_GICD_IROUTER209_lower,GICD_IROUTER209_lower" bitfld.long 0x588 31. "DISTRIBUTOR__37_GICD_IROUTER209_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x588 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER209_LOWER__8_8,A1" newline hexmask.long.byte 0x588 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER209_LOWER__0_8,A0" line.long 0x58C "GIC_REGS_Distributor__37_GICD_IROUTER209_upper,GICD_IROUTER209_upper" line.long 0x590 "GIC_REGS_Distributor__37_GICD_IROUTER210_lower,GICD_IROUTER210_lower" bitfld.long 0x590 31. "DISTRIBUTOR__37_GICD_IROUTER210_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x590 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER210_LOWER__8_8,A1" newline hexmask.long.byte 0x590 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER210_LOWER__0_8,A0" line.long 0x594 "GIC_REGS_Distributor__37_GICD_IROUTER210_upper,GICD_IROUTER210_upper" line.long 0x598 "GIC_REGS_Distributor__37_GICD_IROUTER211_lower,GICD_IROUTER211_lower" bitfld.long 0x598 31. "DISTRIBUTOR__37_GICD_IROUTER211_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x598 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER211_LOWER__8_8,A1" newline hexmask.long.byte 0x598 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER211_LOWER__0_8,A0" line.long 0x59C "GIC_REGS_Distributor__37_GICD_IROUTER211_upper,GICD_IROUTER211_upper" line.long 0x5A0 "GIC_REGS_Distributor__37_GICD_IROUTER212_lower,GICD_IROUTER212_lower" bitfld.long 0x5A0 31. "DISTRIBUTOR__37_GICD_IROUTER212_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x5A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER212_LOWER__8_8,A1" newline hexmask.long.byte 0x5A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER212_LOWER__0_8,A0" line.long 0x5A4 "GIC_REGS_Distributor__37_GICD_IROUTER212_upper,GICD_IROUTER212_upper" line.long 0x5A8 "GIC_REGS_Distributor__37_GICD_IROUTER213_lower,GICD_IROUTER213_lower" bitfld.long 0x5A8 31. "DISTRIBUTOR__37_GICD_IROUTER213_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x5A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER213_LOWER__8_8,A1" newline hexmask.long.byte 0x5A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER213_LOWER__0_8,A0" line.long 0x5AC "GIC_REGS_Distributor__37_GICD_IROUTER213_upper,GICD_IROUTER213_upper" line.long 0x5B0 "GIC_REGS_Distributor__37_GICD_IROUTER214_lower,GICD_IROUTER214_lower" bitfld.long 0x5B0 31. "DISTRIBUTOR__37_GICD_IROUTER214_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x5B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER214_LOWER__8_8,A1" newline hexmask.long.byte 0x5B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER214_LOWER__0_8,A0" line.long 0x5B4 "GIC_REGS_Distributor__37_GICD_IROUTER214_upper,GICD_IROUTER214_upper" line.long 0x5B8 "GIC_REGS_Distributor__37_GICD_IROUTER215_lower,GICD_IROUTER215_lower" bitfld.long 0x5B8 31. "DISTRIBUTOR__37_GICD_IROUTER215_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x5B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER215_LOWER__8_8,A1" newline hexmask.long.byte 0x5B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER215_LOWER__0_8,A0" line.long 0x5BC "GIC_REGS_Distributor__37_GICD_IROUTER215_upper,GICD_IROUTER215_upper" line.long 0x5C0 "GIC_REGS_Distributor__37_GICD_IROUTER216_lower,GICD_IROUTER216_lower" bitfld.long 0x5C0 31. "DISTRIBUTOR__37_GICD_IROUTER216_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x5C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER216_LOWER__8_8,A1" newline hexmask.long.byte 0x5C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER216_LOWER__0_8,A0" line.long 0x5C4 "GIC_REGS_Distributor__37_GICD_IROUTER216_upper,GICD_IROUTER216_upper" line.long 0x5C8 "GIC_REGS_Distributor__37_GICD_IROUTER217_lower,GICD_IROUTER217_lower" bitfld.long 0x5C8 31. "DISTRIBUTOR__37_GICD_IROUTER217_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x5C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER217_LOWER__8_8,A1" newline hexmask.long.byte 0x5C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER217_LOWER__0_8,A0" line.long 0x5CC "GIC_REGS_Distributor__37_GICD_IROUTER217_upper,GICD_IROUTER217_upper" line.long 0x5D0 "GIC_REGS_Distributor__37_GICD_IROUTER218_lower,GICD_IROUTER218_lower" bitfld.long 0x5D0 31. "DISTRIBUTOR__37_GICD_IROUTER218_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x5D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER218_LOWER__8_8,A1" newline hexmask.long.byte 0x5D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER218_LOWER__0_8,A0" line.long 0x5D4 "GIC_REGS_Distributor__37_GICD_IROUTER218_upper,GICD_IROUTER218_upper" line.long 0x5D8 "GIC_REGS_Distributor__37_GICD_IROUTER219_lower,GICD_IROUTER219_lower" bitfld.long 0x5D8 31. "DISTRIBUTOR__37_GICD_IROUTER219_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x5D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER219_LOWER__8_8,A1" newline hexmask.long.byte 0x5D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER219_LOWER__0_8,A0" line.long 0x5DC "GIC_REGS_Distributor__37_GICD_IROUTER219_upper,GICD_IROUTER219_upper" line.long 0x5E0 "GIC_REGS_Distributor__37_GICD_IROUTER220_lower,GICD_IROUTER220_lower" bitfld.long 0x5E0 31. "DISTRIBUTOR__37_GICD_IROUTER220_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x5E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER220_LOWER__8_8,A1" newline hexmask.long.byte 0x5E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER220_LOWER__0_8,A0" line.long 0x5E4 "GIC_REGS_Distributor__37_GICD_IROUTER220_upper,GICD_IROUTER220_upper" line.long 0x5E8 "GIC_REGS_Distributor__37_GICD_IROUTER221_lower,GICD_IROUTER221_lower" bitfld.long 0x5E8 31. "DISTRIBUTOR__37_GICD_IROUTER221_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x5E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER221_LOWER__8_8,A1" newline hexmask.long.byte 0x5E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER221_LOWER__0_8,A0" line.long 0x5EC "GIC_REGS_Distributor__37_GICD_IROUTER221_upper,GICD_IROUTER221_upper" line.long 0x5F0 "GIC_REGS_Distributor__37_GICD_IROUTER222_lower,GICD_IROUTER222_lower" bitfld.long 0x5F0 31. "DISTRIBUTOR__37_GICD_IROUTER222_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x5F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER222_LOWER__8_8,A1" newline hexmask.long.byte 0x5F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER222_LOWER__0_8,A0" line.long 0x5F4 "GIC_REGS_Distributor__37_GICD_IROUTER222_upper,GICD_IROUTER222_upper" line.long 0x5F8 "GIC_REGS_Distributor__37_GICD_IROUTER223_lower,GICD_IROUTER223_lower" bitfld.long 0x5F8 31. "DISTRIBUTOR__37_GICD_IROUTER223_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x5F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER223_LOWER__8_8,A1" newline hexmask.long.byte 0x5F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER223_LOWER__0_8,A0" line.long 0x5FC "GIC_REGS_Distributor__37_GICD_IROUTER223_upper,GICD_IROUTER223_upper" line.long 0x600 "GIC_REGS_Distributor__37_GICD_IROUTER224_lower,GICD_IROUTER224_lower" bitfld.long 0x600 31. "DISTRIBUTOR__37_GICD_IROUTER224_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x600 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER224_LOWER__8_8,A1" newline hexmask.long.byte 0x600 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER224_LOWER__0_8,A0" line.long 0x604 "GIC_REGS_Distributor__37_GICD_IROUTER224_upper,GICD_IROUTER224_upper" line.long 0x608 "GIC_REGS_Distributor__37_GICD_IROUTER225_lower,GICD_IROUTER225_lower" bitfld.long 0x608 31. "DISTRIBUTOR__37_GICD_IROUTER225_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x608 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER225_LOWER__8_8,A1" newline hexmask.long.byte 0x608 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER225_LOWER__0_8,A0" line.long 0x60C "GIC_REGS_Distributor__37_GICD_IROUTER225_upper,GICD_IROUTER225_upper" line.long 0x610 "GIC_REGS_Distributor__37_GICD_IROUTER226_lower,GICD_IROUTER226_lower" bitfld.long 0x610 31. "DISTRIBUTOR__37_GICD_IROUTER226_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x610 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER226_LOWER__8_8,A1" newline hexmask.long.byte 0x610 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER226_LOWER__0_8,A0" line.long 0x614 "GIC_REGS_Distributor__37_GICD_IROUTER226_upper,GICD_IROUTER226_upper" line.long 0x618 "GIC_REGS_Distributor__37_GICD_IROUTER227_lower,GICD_IROUTER227_lower" bitfld.long 0x618 31. "DISTRIBUTOR__37_GICD_IROUTER227_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x618 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER227_LOWER__8_8,A1" newline hexmask.long.byte 0x618 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER227_LOWER__0_8,A0" line.long 0x61C "GIC_REGS_Distributor__37_GICD_IROUTER227_upper,GICD_IROUTER227_upper" line.long 0x620 "GIC_REGS_Distributor__37_GICD_IROUTER228_lower,GICD_IROUTER228_lower" bitfld.long 0x620 31. "DISTRIBUTOR__37_GICD_IROUTER228_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x620 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER228_LOWER__8_8,A1" newline hexmask.long.byte 0x620 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER228_LOWER__0_8,A0" line.long 0x624 "GIC_REGS_Distributor__37_GICD_IROUTER228_upper,GICD_IROUTER228_upper" line.long 0x628 "GIC_REGS_Distributor__37_GICD_IROUTER229_lower,GICD_IROUTER229_lower" bitfld.long 0x628 31. "DISTRIBUTOR__37_GICD_IROUTER229_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x628 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER229_LOWER__8_8,A1" newline hexmask.long.byte 0x628 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER229_LOWER__0_8,A0" line.long 0x62C "GIC_REGS_Distributor__37_GICD_IROUTER229_upper,GICD_IROUTER229_upper" line.long 0x630 "GIC_REGS_Distributor__37_GICD_IROUTER230_lower,GICD_IROUTER230_lower" bitfld.long 0x630 31. "DISTRIBUTOR__37_GICD_IROUTER230_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x630 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER230_LOWER__8_8,A1" newline hexmask.long.byte 0x630 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER230_LOWER__0_8,A0" line.long 0x634 "GIC_REGS_Distributor__37_GICD_IROUTER230_upper,GICD_IROUTER230_upper" line.long 0x638 "GIC_REGS_Distributor__37_GICD_IROUTER231_lower,GICD_IROUTER231_lower" bitfld.long 0x638 31. "DISTRIBUTOR__37_GICD_IROUTER231_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x638 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER231_LOWER__8_8,A1" newline hexmask.long.byte 0x638 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER231_LOWER__0_8,A0" line.long 0x63C "GIC_REGS_Distributor__37_GICD_IROUTER231_upper,GICD_IROUTER231_upper" line.long 0x640 "GIC_REGS_Distributor__37_GICD_IROUTER232_lower,GICD_IROUTER232_lower" bitfld.long 0x640 31. "DISTRIBUTOR__37_GICD_IROUTER232_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x640 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER232_LOWER__8_8,A1" newline hexmask.long.byte 0x640 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER232_LOWER__0_8,A0" line.long 0x644 "GIC_REGS_Distributor__37_GICD_IROUTER232_upper,GICD_IROUTER232_upper" line.long 0x648 "GIC_REGS_Distributor__37_GICD_IROUTER233_lower,GICD_IROUTER233_lower" bitfld.long 0x648 31. "DISTRIBUTOR__37_GICD_IROUTER233_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x648 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER233_LOWER__8_8,A1" newline hexmask.long.byte 0x648 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER233_LOWER__0_8,A0" line.long 0x64C "GIC_REGS_Distributor__37_GICD_IROUTER233_upper,GICD_IROUTER233_upper" line.long 0x650 "GIC_REGS_Distributor__37_GICD_IROUTER234_lower,GICD_IROUTER234_lower" bitfld.long 0x650 31. "DISTRIBUTOR__37_GICD_IROUTER234_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x650 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER234_LOWER__8_8,A1" newline hexmask.long.byte 0x650 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER234_LOWER__0_8,A0" line.long 0x654 "GIC_REGS_Distributor__37_GICD_IROUTER234_upper,GICD_IROUTER234_upper" line.long 0x658 "GIC_REGS_Distributor__37_GICD_IROUTER235_lower,GICD_IROUTER235_lower" bitfld.long 0x658 31. "DISTRIBUTOR__37_GICD_IROUTER235_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x658 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER235_LOWER__8_8,A1" newline hexmask.long.byte 0x658 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER235_LOWER__0_8,A0" line.long 0x65C "GIC_REGS_Distributor__37_GICD_IROUTER235_upper,GICD_IROUTER235_upper" line.long 0x660 "GIC_REGS_Distributor__37_GICD_IROUTER236_lower,GICD_IROUTER236_lower" bitfld.long 0x660 31. "DISTRIBUTOR__37_GICD_IROUTER236_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x660 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER236_LOWER__8_8,A1" newline hexmask.long.byte 0x660 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER236_LOWER__0_8,A0" line.long 0x664 "GIC_REGS_Distributor__37_GICD_IROUTER236_upper,GICD_IROUTER236_upper" line.long 0x668 "GIC_REGS_Distributor__37_GICD_IROUTER237_lower,GICD_IROUTER237_lower" bitfld.long 0x668 31. "DISTRIBUTOR__37_GICD_IROUTER237_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x668 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER237_LOWER__8_8,A1" newline hexmask.long.byte 0x668 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER237_LOWER__0_8,A0" line.long 0x66C "GIC_REGS_Distributor__37_GICD_IROUTER237_upper,GICD_IROUTER237_upper" line.long 0x670 "GIC_REGS_Distributor__37_GICD_IROUTER238_lower,GICD_IROUTER238_lower" bitfld.long 0x670 31. "DISTRIBUTOR__37_GICD_IROUTER238_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x670 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER238_LOWER__8_8,A1" newline hexmask.long.byte 0x670 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER238_LOWER__0_8,A0" line.long 0x674 "GIC_REGS_Distributor__37_GICD_IROUTER238_upper,GICD_IROUTER238_upper" line.long 0x678 "GIC_REGS_Distributor__37_GICD_IROUTER239_lower,GICD_IROUTER239_lower" bitfld.long 0x678 31. "DISTRIBUTOR__37_GICD_IROUTER239_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x678 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER239_LOWER__8_8,A1" newline hexmask.long.byte 0x678 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER239_LOWER__0_8,A0" line.long 0x67C "GIC_REGS_Distributor__37_GICD_IROUTER239_upper,GICD_IROUTER239_upper" line.long 0x680 "GIC_REGS_Distributor__37_GICD_IROUTER240_lower,GICD_IROUTER240_lower" bitfld.long 0x680 31. "DISTRIBUTOR__37_GICD_IROUTER240_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x680 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER240_LOWER__8_8,A1" newline hexmask.long.byte 0x680 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER240_LOWER__0_8,A0" line.long 0x684 "GIC_REGS_Distributor__37_GICD_IROUTER240_upper,GICD_IROUTER240_upper" line.long 0x688 "GIC_REGS_Distributor__37_GICD_IROUTER241_lower,GICD_IROUTER241_lower" bitfld.long 0x688 31. "DISTRIBUTOR__37_GICD_IROUTER241_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x688 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER241_LOWER__8_8,A1" newline hexmask.long.byte 0x688 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER241_LOWER__0_8,A0" line.long 0x68C "GIC_REGS_Distributor__37_GICD_IROUTER241_upper,GICD_IROUTER241_upper" line.long 0x690 "GIC_REGS_Distributor__37_GICD_IROUTER242_lower,GICD_IROUTER242_lower" bitfld.long 0x690 31. "DISTRIBUTOR__37_GICD_IROUTER242_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x690 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER242_LOWER__8_8,A1" newline hexmask.long.byte 0x690 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER242_LOWER__0_8,A0" line.long 0x694 "GIC_REGS_Distributor__37_GICD_IROUTER242_upper,GICD_IROUTER242_upper" line.long 0x698 "GIC_REGS_Distributor__37_GICD_IROUTER243_lower,GICD_IROUTER243_lower" bitfld.long 0x698 31. "DISTRIBUTOR__37_GICD_IROUTER243_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x698 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER243_LOWER__8_8,A1" newline hexmask.long.byte 0x698 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER243_LOWER__0_8,A0" line.long 0x69C "GIC_REGS_Distributor__37_GICD_IROUTER243_upper,GICD_IROUTER243_upper" line.long 0x6A0 "GIC_REGS_Distributor__37_GICD_IROUTER244_lower,GICD_IROUTER244_lower" bitfld.long 0x6A0 31. "DISTRIBUTOR__37_GICD_IROUTER244_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x6A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER244_LOWER__8_8,A1" newline hexmask.long.byte 0x6A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER244_LOWER__0_8,A0" line.long 0x6A4 "GIC_REGS_Distributor__37_GICD_IROUTER244_upper,GICD_IROUTER244_upper" line.long 0x6A8 "GIC_REGS_Distributor__37_GICD_IROUTER245_lower,GICD_IROUTER245_lower" bitfld.long 0x6A8 31. "DISTRIBUTOR__37_GICD_IROUTER245_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x6A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER245_LOWER__8_8,A1" newline hexmask.long.byte 0x6A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER245_LOWER__0_8,A0" line.long 0x6AC "GIC_REGS_Distributor__37_GICD_IROUTER245_upper,GICD_IROUTER245_upper" line.long 0x6B0 "GIC_REGS_Distributor__37_GICD_IROUTER246_lower,GICD_IROUTER246_lower" bitfld.long 0x6B0 31. "DISTRIBUTOR__37_GICD_IROUTER246_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x6B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER246_LOWER__8_8,A1" newline hexmask.long.byte 0x6B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER246_LOWER__0_8,A0" line.long 0x6B4 "GIC_REGS_Distributor__37_GICD_IROUTER246_upper,GICD_IROUTER246_upper" line.long 0x6B8 "GIC_REGS_Distributor__37_GICD_IROUTER247_lower,GICD_IROUTER247_lower" bitfld.long 0x6B8 31. "DISTRIBUTOR__37_GICD_IROUTER247_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x6B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER247_LOWER__8_8,A1" newline hexmask.long.byte 0x6B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER247_LOWER__0_8,A0" line.long 0x6BC "GIC_REGS_Distributor__37_GICD_IROUTER247_upper,GICD_IROUTER247_upper" line.long 0x6C0 "GIC_REGS_Distributor__37_GICD_IROUTER248_lower,GICD_IROUTER248_lower" bitfld.long 0x6C0 31. "DISTRIBUTOR__37_GICD_IROUTER248_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x6C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER248_LOWER__8_8,A1" newline hexmask.long.byte 0x6C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER248_LOWER__0_8,A0" line.long 0x6C4 "GIC_REGS_Distributor__37_GICD_IROUTER248_upper,GICD_IROUTER248_upper" line.long 0x6C8 "GIC_REGS_Distributor__37_GICD_IROUTER249_lower,GICD_IROUTER249_lower" bitfld.long 0x6C8 31. "DISTRIBUTOR__37_GICD_IROUTER249_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x6C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER249_LOWER__8_8,A1" newline hexmask.long.byte 0x6C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER249_LOWER__0_8,A0" line.long 0x6CC "GIC_REGS_Distributor__37_GICD_IROUTER249_upper,GICD_IROUTER249_upper" line.long 0x6D0 "GIC_REGS_Distributor__37_GICD_IROUTER250_lower,GICD_IROUTER250_lower" bitfld.long 0x6D0 31. "DISTRIBUTOR__37_GICD_IROUTER250_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x6D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER250_LOWER__8_8,A1" newline hexmask.long.byte 0x6D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER250_LOWER__0_8,A0" line.long 0x6D4 "GIC_REGS_Distributor__37_GICD_IROUTER250_upper,GICD_IROUTER250_upper" line.long 0x6D8 "GIC_REGS_Distributor__37_GICD_IROUTER251_lower,GICD_IROUTER251_lower" bitfld.long 0x6D8 31. "DISTRIBUTOR__37_GICD_IROUTER251_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x6D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER251_LOWER__8_8,A1" newline hexmask.long.byte 0x6D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER251_LOWER__0_8,A0" line.long 0x6DC "GIC_REGS_Distributor__37_GICD_IROUTER251_upper,GICD_IROUTER251_upper" line.long 0x6E0 "GIC_REGS_Distributor__37_GICD_IROUTER252_lower,GICD_IROUTER252_lower" bitfld.long 0x6E0 31. "DISTRIBUTOR__37_GICD_IROUTER252_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x6E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER252_LOWER__8_8,A1" newline hexmask.long.byte 0x6E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER252_LOWER__0_8,A0" line.long 0x6E4 "GIC_REGS_Distributor__37_GICD_IROUTER252_upper,GICD_IROUTER252_upper" line.long 0x6E8 "GIC_REGS_Distributor__37_GICD_IROUTER253_lower,GICD_IROUTER253_lower" bitfld.long 0x6E8 31. "DISTRIBUTOR__37_GICD_IROUTER253_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x6E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER253_LOWER__8_8,A1" newline hexmask.long.byte 0x6E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER253_LOWER__0_8,A0" line.long 0x6EC "GIC_REGS_Distributor__37_GICD_IROUTER253_upper,GICD_IROUTER253_upper" line.long 0x6F0 "GIC_REGS_Distributor__37_GICD_IROUTER254_lower,GICD_IROUTER254_lower" bitfld.long 0x6F0 31. "DISTRIBUTOR__37_GICD_IROUTER254_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x6F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER254_LOWER__8_8,A1" newline hexmask.long.byte 0x6F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER254_LOWER__0_8,A0" line.long 0x6F4 "GIC_REGS_Distributor__37_GICD_IROUTER254_upper,GICD_IROUTER254_upper" line.long 0x6F8 "GIC_REGS_Distributor__37_GICD_IROUTER255_lower,GICD_IROUTER255_lower" bitfld.long 0x6F8 31. "DISTRIBUTOR__37_GICD_IROUTER255_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x6F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER255_LOWER__8_8,A1" newline hexmask.long.byte 0x6F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER255_LOWER__0_8,A0" line.long 0x6FC "GIC_REGS_Distributor__37_GICD_IROUTER255_upper,GICD_IROUTER255_upper" line.long 0x700 "GIC_REGS_Distributor__37_GICD_IROUTER256_lower,GICD_IROUTER256_lower" bitfld.long 0x700 31. "DISTRIBUTOR__37_GICD_IROUTER256_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x700 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER256_LOWER__8_8,A1" newline hexmask.long.byte 0x700 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER256_LOWER__0_8,A0" line.long 0x704 "GIC_REGS_Distributor__37_GICD_IROUTER256_upper,GICD_IROUTER256_upper" line.long 0x708 "GIC_REGS_Distributor__37_GICD_IROUTER257_lower,GICD_IROUTER257_lower" bitfld.long 0x708 31. "DISTRIBUTOR__37_GICD_IROUTER257_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x708 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER257_LOWER__8_8,A1" newline hexmask.long.byte 0x708 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER257_LOWER__0_8,A0" line.long 0x70C "GIC_REGS_Distributor__37_GICD_IROUTER257_upper,GICD_IROUTER257_upper" line.long 0x710 "GIC_REGS_Distributor__37_GICD_IROUTER258_lower,GICD_IROUTER258_lower" bitfld.long 0x710 31. "DISTRIBUTOR__37_GICD_IROUTER258_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x710 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER258_LOWER__8_8,A1" newline hexmask.long.byte 0x710 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER258_LOWER__0_8,A0" line.long 0x714 "GIC_REGS_Distributor__37_GICD_IROUTER258_upper,GICD_IROUTER258_upper" line.long 0x718 "GIC_REGS_Distributor__37_GICD_IROUTER259_lower,GICD_IROUTER259_lower" bitfld.long 0x718 31. "DISTRIBUTOR__37_GICD_IROUTER259_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x718 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER259_LOWER__8_8,A1" newline hexmask.long.byte 0x718 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER259_LOWER__0_8,A0" line.long 0x71C "GIC_REGS_Distributor__37_GICD_IROUTER259_upper,GICD_IROUTER259_upper" line.long 0x720 "GIC_REGS_Distributor__37_GICD_IROUTER260_lower,GICD_IROUTER260_lower" bitfld.long 0x720 31. "DISTRIBUTOR__37_GICD_IROUTER260_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x720 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER260_LOWER__8_8,A1" newline hexmask.long.byte 0x720 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER260_LOWER__0_8,A0" line.long 0x724 "GIC_REGS_Distributor__37_GICD_IROUTER260_upper,GICD_IROUTER260_upper" line.long 0x728 "GIC_REGS_Distributor__37_GICD_IROUTER261_lower,GICD_IROUTER261_lower" bitfld.long 0x728 31. "DISTRIBUTOR__37_GICD_IROUTER261_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x728 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER261_LOWER__8_8,A1" newline hexmask.long.byte 0x728 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER261_LOWER__0_8,A0" line.long 0x72C "GIC_REGS_Distributor__37_GICD_IROUTER261_upper,GICD_IROUTER261_upper" line.long 0x730 "GIC_REGS_Distributor__37_GICD_IROUTER262_lower,GICD_IROUTER262_lower" bitfld.long 0x730 31. "DISTRIBUTOR__37_GICD_IROUTER262_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x730 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER262_LOWER__8_8,A1" newline hexmask.long.byte 0x730 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER262_LOWER__0_8,A0" line.long 0x734 "GIC_REGS_Distributor__37_GICD_IROUTER262_upper,GICD_IROUTER262_upper" line.long 0x738 "GIC_REGS_Distributor__37_GICD_IROUTER263_lower,GICD_IROUTER263_lower" bitfld.long 0x738 31. "DISTRIBUTOR__37_GICD_IROUTER263_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x738 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER263_LOWER__8_8,A1" newline hexmask.long.byte 0x738 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER263_LOWER__0_8,A0" line.long 0x73C "GIC_REGS_Distributor__37_GICD_IROUTER263_upper,GICD_IROUTER263_upper" line.long 0x740 "GIC_REGS_Distributor__37_GICD_IROUTER264_lower,GICD_IROUTER264_lower" bitfld.long 0x740 31. "DISTRIBUTOR__37_GICD_IROUTER264_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x740 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER264_LOWER__8_8,A1" newline hexmask.long.byte 0x740 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER264_LOWER__0_8,A0" line.long 0x744 "GIC_REGS_Distributor__37_GICD_IROUTER264_upper,GICD_IROUTER264_upper" line.long 0x748 "GIC_REGS_Distributor__37_GICD_IROUTER265_lower,GICD_IROUTER265_lower" bitfld.long 0x748 31. "DISTRIBUTOR__37_GICD_IROUTER265_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x748 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER265_LOWER__8_8,A1" newline hexmask.long.byte 0x748 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER265_LOWER__0_8,A0" line.long 0x74C "GIC_REGS_Distributor__37_GICD_IROUTER265_upper,GICD_IROUTER265_upper" line.long 0x750 "GIC_REGS_Distributor__37_GICD_IROUTER266_lower,GICD_IROUTER266_lower" bitfld.long 0x750 31. "DISTRIBUTOR__37_GICD_IROUTER266_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x750 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER266_LOWER__8_8,A1" newline hexmask.long.byte 0x750 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER266_LOWER__0_8,A0" line.long 0x754 "GIC_REGS_Distributor__37_GICD_IROUTER266_upper,GICD_IROUTER266_upper" line.long 0x758 "GIC_REGS_Distributor__37_GICD_IROUTER267_lower,GICD_IROUTER267_lower" bitfld.long 0x758 31. "DISTRIBUTOR__37_GICD_IROUTER267_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x758 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER267_LOWER__8_8,A1" newline hexmask.long.byte 0x758 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER267_LOWER__0_8,A0" line.long 0x75C "GIC_REGS_Distributor__37_GICD_IROUTER267_upper,GICD_IROUTER267_upper" line.long 0x760 "GIC_REGS_Distributor__37_GICD_IROUTER268_lower,GICD_IROUTER268_lower" bitfld.long 0x760 31. "DISTRIBUTOR__37_GICD_IROUTER268_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x760 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER268_LOWER__8_8,A1" newline hexmask.long.byte 0x760 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER268_LOWER__0_8,A0" line.long 0x764 "GIC_REGS_Distributor__37_GICD_IROUTER268_upper,GICD_IROUTER268_upper" line.long 0x768 "GIC_REGS_Distributor__37_GICD_IROUTER269_lower,GICD_IROUTER269_lower" bitfld.long 0x768 31. "DISTRIBUTOR__37_GICD_IROUTER269_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x768 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER269_LOWER__8_8,A1" newline hexmask.long.byte 0x768 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER269_LOWER__0_8,A0" line.long 0x76C "GIC_REGS_Distributor__37_GICD_IROUTER269_upper,GICD_IROUTER269_upper" line.long 0x770 "GIC_REGS_Distributor__37_GICD_IROUTER270_lower,GICD_IROUTER270_lower" bitfld.long 0x770 31. "DISTRIBUTOR__37_GICD_IROUTER270_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x770 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER270_LOWER__8_8,A1" newline hexmask.long.byte 0x770 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER270_LOWER__0_8,A0" line.long 0x774 "GIC_REGS_Distributor__37_GICD_IROUTER270_upper,GICD_IROUTER270_upper" line.long 0x778 "GIC_REGS_Distributor__37_GICD_IROUTER271_lower,GICD_IROUTER271_lower" bitfld.long 0x778 31. "DISTRIBUTOR__37_GICD_IROUTER271_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x778 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER271_LOWER__8_8,A1" newline hexmask.long.byte 0x778 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER271_LOWER__0_8,A0" line.long 0x77C "GIC_REGS_Distributor__37_GICD_IROUTER271_upper,GICD_IROUTER271_upper" line.long 0x780 "GIC_REGS_Distributor__37_GICD_IROUTER272_lower,GICD_IROUTER272_lower" bitfld.long 0x780 31. "DISTRIBUTOR__37_GICD_IROUTER272_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x780 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER272_LOWER__8_8,A1" newline hexmask.long.byte 0x780 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER272_LOWER__0_8,A0" line.long 0x784 "GIC_REGS_Distributor__37_GICD_IROUTER272_upper,GICD_IROUTER272_upper" line.long 0x788 "GIC_REGS_Distributor__37_GICD_IROUTER273_lower,GICD_IROUTER273_lower" bitfld.long 0x788 31. "DISTRIBUTOR__37_GICD_IROUTER273_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x788 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER273_LOWER__8_8,A1" newline hexmask.long.byte 0x788 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER273_LOWER__0_8,A0" line.long 0x78C "GIC_REGS_Distributor__37_GICD_IROUTER273_upper,GICD_IROUTER273_upper" line.long 0x790 "GIC_REGS_Distributor__37_GICD_IROUTER274_lower,GICD_IROUTER274_lower" bitfld.long 0x790 31. "DISTRIBUTOR__37_GICD_IROUTER274_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x790 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER274_LOWER__8_8,A1" newline hexmask.long.byte 0x790 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER274_LOWER__0_8,A0" line.long 0x794 "GIC_REGS_Distributor__37_GICD_IROUTER274_upper,GICD_IROUTER274_upper" line.long 0x798 "GIC_REGS_Distributor__37_GICD_IROUTER275_lower,GICD_IROUTER275_lower" bitfld.long 0x798 31. "DISTRIBUTOR__37_GICD_IROUTER275_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x798 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER275_LOWER__8_8,A1" newline hexmask.long.byte 0x798 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER275_LOWER__0_8,A0" line.long 0x79C "GIC_REGS_Distributor__37_GICD_IROUTER275_upper,GICD_IROUTER275_upper" line.long 0x7A0 "GIC_REGS_Distributor__37_GICD_IROUTER276_lower,GICD_IROUTER276_lower" bitfld.long 0x7A0 31. "DISTRIBUTOR__37_GICD_IROUTER276_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x7A0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER276_LOWER__8_8,A1" newline hexmask.long.byte 0x7A0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER276_LOWER__0_8,A0" line.long 0x7A4 "GIC_REGS_Distributor__37_GICD_IROUTER276_upper,GICD_IROUTER276_upper" line.long 0x7A8 "GIC_REGS_Distributor__37_GICD_IROUTER277_lower,GICD_IROUTER277_lower" bitfld.long 0x7A8 31. "DISTRIBUTOR__37_GICD_IROUTER277_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x7A8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER277_LOWER__8_8,A1" newline hexmask.long.byte 0x7A8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER277_LOWER__0_8,A0" line.long 0x7AC "GIC_REGS_Distributor__37_GICD_IROUTER277_upper,GICD_IROUTER277_upper" line.long 0x7B0 "GIC_REGS_Distributor__37_GICD_IROUTER278_lower,GICD_IROUTER278_lower" bitfld.long 0x7B0 31. "DISTRIBUTOR__37_GICD_IROUTER278_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x7B0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER278_LOWER__8_8,A1" newline hexmask.long.byte 0x7B0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER278_LOWER__0_8,A0" line.long 0x7B4 "GIC_REGS_Distributor__37_GICD_IROUTER278_upper,GICD_IROUTER278_upper" line.long 0x7B8 "GIC_REGS_Distributor__37_GICD_IROUTER279_lower,GICD_IROUTER279_lower" bitfld.long 0x7B8 31. "DISTRIBUTOR__37_GICD_IROUTER279_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x7B8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER279_LOWER__8_8,A1" newline hexmask.long.byte 0x7B8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER279_LOWER__0_8,A0" line.long 0x7BC "GIC_REGS_Distributor__37_GICD_IROUTER279_upper,GICD_IROUTER279_upper" line.long 0x7C0 "GIC_REGS_Distributor__37_GICD_IROUTER280_lower,GICD_IROUTER280_lower" bitfld.long 0x7C0 31. "DISTRIBUTOR__37_GICD_IROUTER280_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x7C0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER280_LOWER__8_8,A1" newline hexmask.long.byte 0x7C0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER280_LOWER__0_8,A0" line.long 0x7C4 "GIC_REGS_Distributor__37_GICD_IROUTER280_upper,GICD_IROUTER280_upper" line.long 0x7C8 "GIC_REGS_Distributor__37_GICD_IROUTER281_lower,GICD_IROUTER281_lower" bitfld.long 0x7C8 31. "DISTRIBUTOR__37_GICD_IROUTER281_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x7C8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER281_LOWER__8_8,A1" newline hexmask.long.byte 0x7C8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER281_LOWER__0_8,A0" line.long 0x7CC "GIC_REGS_Distributor__37_GICD_IROUTER281_upper,GICD_IROUTER281_upper" line.long 0x7D0 "GIC_REGS_Distributor__37_GICD_IROUTER282_lower,GICD_IROUTER282_lower" bitfld.long 0x7D0 31. "DISTRIBUTOR__37_GICD_IROUTER282_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x7D0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER282_LOWER__8_8,A1" newline hexmask.long.byte 0x7D0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER282_LOWER__0_8,A0" line.long 0x7D4 "GIC_REGS_Distributor__37_GICD_IROUTER282_upper,GICD_IROUTER282_upper" line.long 0x7D8 "GIC_REGS_Distributor__37_GICD_IROUTER283_lower,GICD_IROUTER283_lower" bitfld.long 0x7D8 31. "DISTRIBUTOR__37_GICD_IROUTER283_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x7D8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER283_LOWER__8_8,A1" newline hexmask.long.byte 0x7D8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER283_LOWER__0_8,A0" line.long 0x7DC "GIC_REGS_Distributor__37_GICD_IROUTER283_upper,GICD_IROUTER283_upper" line.long 0x7E0 "GIC_REGS_Distributor__37_GICD_IROUTER284_lower,GICD_IROUTER284_lower" bitfld.long 0x7E0 31. "DISTRIBUTOR__37_GICD_IROUTER284_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x7E0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER284_LOWER__8_8,A1" newline hexmask.long.byte 0x7E0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER284_LOWER__0_8,A0" line.long 0x7E4 "GIC_REGS_Distributor__37_GICD_IROUTER284_upper,GICD_IROUTER284_upper" line.long 0x7E8 "GIC_REGS_Distributor__37_GICD_IROUTER285_lower,GICD_IROUTER285_lower" bitfld.long 0x7E8 31. "DISTRIBUTOR__37_GICD_IROUTER285_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x7E8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER285_LOWER__8_8,A1" newline hexmask.long.byte 0x7E8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER285_LOWER__0_8,A0" line.long 0x7EC "GIC_REGS_Distributor__37_GICD_IROUTER285_upper,GICD_IROUTER285_upper" line.long 0x7F0 "GIC_REGS_Distributor__37_GICD_IROUTER286_lower,GICD_IROUTER286_lower" bitfld.long 0x7F0 31. "DISTRIBUTOR__37_GICD_IROUTER286_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x7F0 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER286_LOWER__8_8,A1" newline hexmask.long.byte 0x7F0 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER286_LOWER__0_8,A0" line.long 0x7F4 "GIC_REGS_Distributor__37_GICD_IROUTER286_upper,GICD_IROUTER286_upper" line.long 0x7F8 "GIC_REGS_Distributor__37_GICD_IROUTER287_lower,GICD_IROUTER287_lower" bitfld.long 0x7F8 31. "DISTRIBUTOR__37_GICD_IROUTER287_LOWER__31_1,IRM" "0,1" newline hexmask.long.byte 0x7F8 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER287_LOWER__8_8,A1" newline hexmask.long.byte 0x7F8 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER287_LOWER__0_8,A0" line.long 0x7FC "GIC_REGS_Distributor__37_GICD_IROUTER287_upper,GICD_IROUTER287_upper" group.long 0xC000++0x7 line.long 0x0 "GIC_REGS_Distributor__38_GICD_ESTATUSR,GICD_ESTATUSR" bitfld.long 0x0 31. "DISTRIBUTOR__38_GICD_ESTATUSR__31_1,SWRP" "0,1" line.long 0x4 "GIC_REGS_Distributor__39_GICD_ERRTESTR,GICD_ERRTESTR" bitfld.long 0x4 1. "DISTRIBUTOR__39_GICD_ERRTESTR__1_1,AXIM_err" "0,1" newline bitfld.long 0x4 0. "DISTRIBUTOR__39_GICD_ERRTESTR__0_1,ECC_fatal" "0,1" group.long 0xC084++0x1F line.long 0x0 "GIC_REGS_Distributor__40_GICD_SPISR0,GICD_SPISR0" line.long 0x4 "GIC_REGS_Distributor__40_GICD_SPISR1,GICD_SPISR1" line.long 0x8 "GIC_REGS_Distributor__40_GICD_SPISR2,GICD_SPISR2" line.long 0xC "GIC_REGS_Distributor__40_GICD_SPISR3,GICD_SPISR3" line.long 0x10 "GIC_REGS_Distributor__40_GICD_SPISR4,GICD_SPISR4" line.long 0x14 "GIC_REGS_Distributor__40_GICD_SPISR5,GICD_SPISR5" line.long 0x18 "GIC_REGS_Distributor__40_GICD_SPISR6,GICD_SPISR6" line.long 0x1C "GIC_REGS_Distributor__40_GICD_SPISR7,GICD_SPISR7" group.long 0xFFD0++0x2F line.long 0x0 "GIC_REGS_Distributor__41_GICD_PIDR4,GICD_PIDR4" line.long 0x4 "GIC_REGS_Distributor__42_GICD_PIDR5,GICD_PIDR5" line.long 0x8 "GIC_REGS_Distributor__43_GICD_PIDR6,GICD_PIDR6" line.long 0xC "GIC_REGS_Distributor__44_GICD_PIDR7,GICD_PIDR7" line.long 0x10 "GIC_REGS_Distributor__45_GICD_PIDR0,GICD_PIDR0" line.long 0x14 "GIC_REGS_Distributor__46_GICD_PIDR1,GICD_PIDR1" line.long 0x18 "GIC_REGS_Distributor__47_GICD_PIDR2,GICD_PIDR2" line.long 0x1C "GIC_REGS_Distributor__48_GICD_PIDR3,GICD_PIDR3" line.long 0x20 "GIC_REGS_Distributor__49_GICD_CIDR0,GICD_CIDR0" line.long 0x24 "GIC_REGS_Distributor__50_GICD_CIDR1,GICD_CIDR1" line.long 0x28 "GIC_REGS_Distributor__51_GICD_CIDR2,GICD_CIDR2" line.long 0x2C "GIC_REGS_Distributor__52_GICD_CIDR3,GICD_CIDR3" group.long 0x10040++0x3 line.long 0x0 "GIC_REGS_Message_based_SPIs__1_GICD_SETSPI_NSR,GICD_SETSPI_NSR" hexmask.long.word 0x0 0.--9. 1. "MESSAGE_BASED_SPIS__1_GICD_SETSPI_NSR__0_10,SPI ID" group.long 0x10048++0x3 line.long 0x0 "GIC_REGS_Message_based_SPIs__2_GICD_CLRSPI_NSR,GICD_CLRSPI_NSR" hexmask.long.word 0x0 0.--9. 1. "MESSAGE_BASED_SPIS__2_GICD_CLRSPI_NSR__0_10,SPI ID" group.long 0x10050++0x3 line.long 0x0 "GIC_REGS_Message_based_SPIs__3_GICD_SETSPI_SR,GICD_SETSPI_SR" hexmask.long.word 0x0 0.--9. 1. "MESSAGE_BASED_SPIS__3_GICD_SETSPI_SR__0_10,SPI ID" group.long 0x10058++0x3 line.long 0x0 "GIC_REGS_Message_based_SPIs__4_GICD_CLRSPI_SR,GICD_CLRSPI_SR" hexmask.long.word 0x0 0.--9. 1. "MESSAGE_BASED_SPIS__4_GICD_CLRSPI_SR__0_10,SPI ID" group.long 0x20000++0xF line.long 0x0 "GIC_REGS_ITS__1_GITS_CTLR,GITS_CTLR" bitfld.long 0x0 31. "ITS__1_GITS_CTLR__31_1,Quiescent" "0,1" newline bitfld.long 0x0 0. "ITS__1_GITS_CTLR__0_1,Enabled" "0,1" line.long 0x4 "GIC_REGS_ITS__2_GITS_IIDR,GITS_IIDR" hexmask.long.byte 0x4 24.--31. 1. "ITS__2_GITS_IIDR__24_8,ProductID" newline hexmask.long.byte 0x4 16.--19. 1. "ITS__2_GITS_IIDR__16_4,Variant" newline hexmask.long.byte 0x4 12.--15. 1. "ITS__2_GITS_IIDR__12_4,Revision" newline hexmask.long.word 0x4 0.--11. 1. "ITS__2_GITS_IIDR__0_12,Implementer" line.long 0x8 "GIC_REGS_ITS__3_GITS_TYPER_lower,GITS_TYPER_lower" hexmask.long.byte 0x8 24.--31. 1. "ITS__3_GITS_TYPER_LOWER__24_8,HCC" newline bitfld.long 0x8 19. "ITS__3_GITS_TYPER_LOWER__19_1,PTA" "0,1" newline hexmask.long.byte 0x8 13.--17. 1. "ITS__3_GITS_TYPER_LOWER__13_5,Devbits" newline hexmask.long.byte 0x8 8.--12. 1. "ITS__3_GITS_TYPER_LOWER__8_5,IDbits" newline hexmask.long.byte 0x8 4.--7. 1. "ITS__3_GITS_TYPER_LOWER__4_4,ITT Entry Size" newline bitfld.long 0x8 3. "ITS__3_GITS_TYPER_LOWER__3_1,Distributed" "0,1" newline bitfld.long 0x8 1. "ITS__3_GITS_TYPER_LOWER__1_1,VLPIS" "0,1" newline bitfld.long 0x8 0. "ITS__3_GITS_TYPER_LOWER__0_1,PLPIS" "0,1" line.long 0xC "GIC_REGS_ITS__4_GITS_TYPER_upper,GITS_TYPER_upper" group.long 0x20080++0x17 line.long 0x0 "GIC_REGS_ITS__5_GITS_CBASER_lower,GITS_CBASER_lower" hexmask.long.tbyte 0x0 12.--31. 1. "ITS__5_GITS_CBASER_LOWER__12_20,Physical Address [31:12]" newline hexmask.long.byte 0x0 0.--7. 1. "ITS__5_GITS_CBASER_LOWER__0_8,Size" line.long 0x4 "GIC_REGS_ITS__6_GITS_CBASER_upper,GITS_CBASER_upper" bitfld.long 0x4 31. "ITS__6_GITS_CBASER_UPPER__31_1,Valid" "0,1" newline bitfld.long 0x4 27.--29. "ITS__6_GITS_CBASER_UPPER__27_3,Cacheability" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 0.--15. 1. "ITS__6_GITS_CBASER_UPPER__0_16,Physical Address [47:32]" line.long 0x8 "GIC_REGS_ITS__7_GITS_CWRITER_lower,GITS_CWRITER_lower" hexmask.long.word 0x8 5.--19. 1. "ITS__7_GITS_CWRITER_LOWER__5_15,Offset" line.long 0xC "GIC_REGS_ITS__8_GITS_CWRITER_upper,GITS_CWRITER_upper" line.long 0x10 "GIC_REGS_ITS__9_GITS_CREADR_lower,GITS_CREADR_lower" hexmask.long.word 0x10 5.--19. 1. "ITS__9_GITS_CREADR_LOWER__5_15,Offset" line.long 0x14 "GIC_REGS_ITS__10_GITS_CREADR_upper,GITS_CREADR_upper" group.long 0x20100++0x7 line.long 0x0 "GIC_REGS_ITS__11_GITS_BASER0_lower,GITS_BASER0_lower" hexmask.long.tbyte 0x0 12.--31. 1. "ITS__11_GITS_BASER0_LOWER__12_20,Physical Address [31:12]" newline bitfld.long 0x0 8.--9. "ITS__11_GITS_BASER0_LOWER__8_2,Page Size" "0,1,2,3" newline hexmask.long.byte 0x0 0.--7. 1. "ITS__11_GITS_BASER0_LOWER__0_8,Size" line.long 0x4 "GIC_REGS_ITS__12_GITS_BASER0_upper,GITS_BASER0_upper" bitfld.long 0x4 24.--26. "ITS__12_GITS_BASER0_UPPER__24_3,Type" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--23. 1. "ITS__12_GITS_BASER0_UPPER__16_8,Entry Size" newline hexmask.long.word 0x4 0.--15. 1. "ITS__12_GITS_BASER0_UPPER__0_16,Physical Address [47:32]" group.long 0x2C000++0x1F line.long 0x0 "GIC_REGS_ITS__13_GITS_TRKCTLR,GITS_TRKCTLR" bitfld.long 0x0 1. "ITS__13_GITS_TRKCTLR__1_1,ITS track" "0,1" newline bitfld.long 0x0 0. "ITS__13_GITS_TRKCTLR__0_1,Cache count reset" "0,1" line.long 0x4 "GIC_REGS_ITS__14_GITS_TRKR,GITS_TRKR" bitfld.long 0x4 5. "ITS__14_GITS_TRKR__5_1,Translated ID out of range" "0,1" newline bitfld.long 0x4 4. "ITS__14_GITS_TRKR__4_1,Target CPU out of range" "0,1" newline bitfld.long 0x4 3. "ITS__14_GITS_TRKR__3_1,DID/ID not mapped" "0,1" newline bitfld.long 0x4 2. "ITS__14_GITS_TRKR__2_1,Input ID out of range" "0,1" newline bitfld.long 0x4 1. "ITS__14_GITS_TRKR__1_1,DID unmapped" "0,1" newline bitfld.long 0x4 0. "ITS__14_GITS_TRKR__0_1,DID out of range" "0,1" line.long 0x8 "GIC_REGS_ITS__15_GITS_TRKDIDR,GITS_TRKDIDR" hexmask.long.tbyte 0x8 0.--19. 1. "ITS__15_GITS_TRKDIDR__0_20,DID" line.long 0xC "GIC_REGS_ITS__16_GITS_TRKPIDR,GITS_TRKPIDR" hexmask.long.word 0xC 0.--15. 1. "ITS__16_GITS_TRKPIDR__0_16,Translated ID" line.long 0x10 "GIC_REGS_ITS__17_GITS_TRKVIDR,GITS_TRKVIDR" hexmask.long.word 0x10 0.--15. 1. "ITS__17_GITS_TRKVIDR__0_16,Input ID" line.long 0x14 "GIC_REGS_ITS__18_GITS_TRKTGTR,GITS_TRKTGTR" hexmask.long.byte 0x14 0.--6. 1. "ITS__18_GITS_TRKTGTR__0_7,Target CPU" line.long 0x18 "GIC_REGS_ITS__19_GITS_TRKICR,GITS_TRKICR" hexmask.long.word 0x18 16.--31. 1. "ITS__19_GITS_TRKICR__16_16,ITE cache hits" newline hexmask.long.word 0x18 0.--15. 1. "ITS__19_GITS_TRKICR__0_16,ITE cache misses" line.long 0x1C "GIC_REGS_ITS__20_GITS_TRKLCR,GITS_TRKLCR" hexmask.long.word 0x1C 16.--31. 1. "ITS__20_GITS_TRKLCR__16_16,LPI cache hits" newline hexmask.long.word 0x1C 0.--15. 1. "ITS__20_GITS_TRKLCR__0_16,LPI cache misses" group.long 0x2FFD0++0x2F line.long 0x0 "GIC_REGS_ITS__21_GITS_PIDR4,GITS_PIDR4" line.long 0x4 "GIC_REGS_ITS__22_GITS_PIDR5,GITS_PIDR5" line.long 0x8 "GIC_REGS_ITS__23_GITS_PIDR6,GITS_PIDR6" line.long 0xC "GIC_REGS_ITS__24_GITS_PIDR7,GITS_PIDR7" line.long 0x10 "GIC_REGS_ITS__25_GITS_PIDR0,GITS_PIDR0" line.long 0x14 "GIC_REGS_ITS__26_GITS_PIDR1,GITS_PIDR1" line.long 0x18 "GIC_REGS_ITS__27_GITS_PIDR2,GITS_PIDR2" line.long 0x1C "GIC_REGS_ITS__28_GITS_PIDR3,GITS_PIDR3" line.long 0x20 "GIC_REGS_ITS__29_GITS_CIDR0,GITS_CIDR0" line.long 0x24 "GIC_REGS_ITS__30_GITS_CIDR1,GITS_CIDR1" line.long 0x28 "GIC_REGS_ITS__31_GITS_CIDR2,GITS_CIDR2" line.long 0x2C "GIC_REGS_ITS__32_GITS_CIDR3,GITS_CIDR3" group.long 0x40000++0xF line.long 0x0 "GIC_REGS_Redistributor_control_LPI_0__2_GICR_CTLR,GICR_CTLR" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_0__2_GICR_CTLR__31_1,Upstream Write Pending" "0,1" newline bitfld.long 0x0 3. "REDISTRIBUTOR_CONTROL_LPI_0__2_GICR_CTLR__3_1,Register Write Pending" "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_0__2_GICR_CTLR__0_1,Enable LPIs" "0,1" line.long 0x4 "GIC_REGS_Redistributor_control_LPI_0__3_GICR_IIDR,GICR_IIDR" hexmask.long.byte 0x4 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_0__3_GICR_IIDR__24_8,ProductID" newline hexmask.long.byte 0x4 16.--19. 1. "REDISTRIBUTOR_CONTROL_LPI_0__3_GICR_IIDR__16_4,Variant" newline hexmask.long.byte 0x4 12.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_0__3_GICR_IIDR__12_4,Revision" newline hexmask.long.word 0x4 0.--11. 1. "REDISTRIBUTOR_CONTROL_LPI_0__3_GICR_IIDR__0_12,Implementer" line.long 0x8 "GIC_REGS_Redistributor_control_LPI_0__4_GICR_TYPER_lower,GICR_TYPER_lower" hexmask.long.word 0x8 8.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_0__4_GICR_TYPER_LOWER__8_16,Processor Number" newline bitfld.long 0x8 4. "REDISTRIBUTOR_CONTROL_LPI_0__4_GICR_TYPER_LOWER__4_1,Last" "0,1" newline bitfld.long 0x8 3. "REDISTRIBUTOR_CONTROL_LPI_0__4_GICR_TYPER_LOWER__3_1,Distributed" "0,1" newline bitfld.long 0x8 1. "REDISTRIBUTOR_CONTROL_LPI_0__4_GICR_TYPER_LOWER__1_1,VLPIS" "0,1" newline bitfld.long 0x8 0. "REDISTRIBUTOR_CONTROL_LPI_0__4_GICR_TYPER_LOWER__0_1,PLPIS" "0,1" line.long 0xC "GIC_REGS_Redistributor_control_LPI_0__5_GICR_TYPER_upper,GICR_TYPER_upper" hexmask.long.byte 0xC 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_0__5_GICR_TYPER_UPPER__24_8,A3" newline hexmask.long.byte 0xC 16.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_0__5_GICR_TYPER_UPPER__16_8,A2" newline hexmask.long.byte 0xC 8.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_0__5_GICR_TYPER_UPPER__8_8,A1" newline hexmask.long.byte 0xC 0.--7. 1. "REDISTRIBUTOR_CONTROL_LPI_0__5_GICR_TYPER_UPPER__0_8,A0" group.long 0x40014++0x3 line.long 0x0 "GIC_REGS_Redistributor_control_LPI_0__6_GICR_WAKER,GICR_WAKER" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_0__6_GICR_WAKER__31_1,Quiescent" "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_CONTROL_LPI_0__6_GICR_WAKER__2_1,ChildrenAsleep" "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_CONTROL_LPI_0__6_GICR_WAKER__1_1,ProcessorSleep" "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_0__6_GICR_WAKER__0_1,Sleep" "0,1" group.long 0x40070++0xF line.long 0x0 "GIC_REGS_Redistributor_control_LPI_0__7_GICR_PROPBASER_lower,GICR_PROPBASER_lower" hexmask.long.tbyte 0x0 12.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_0__7_GICR_PROPBASER_LOWER__12_20,Physical Address [31:12]" newline bitfld.long 0x0 7.--9. "REDISTRIBUTOR_CONTROL_LPI_0__7_GICR_PROPBASER_LOWER__7_3,Cacheability" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "REDISTRIBUTOR_CONTROL_LPI_0__7_GICR_PROPBASER_LOWER__0_5,Idbits" line.long 0x4 "GIC_REGS_Redistributor_control_LPI_0__8_GICR_PROPBASER_upper,GICR_PROPBASER_upper" hexmask.long.word 0x4 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_0__8_GICR_PROPBASER_UPPER__0_16,Physical Address [47:32]" line.long 0x8 "GIC_REGS_Redistributor_control_LPI_0__9_GICR_PENDBASER_lower,GICR_PENDBASER_lower" hexmask.long.word 0x8 16.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_0__9_GICR_PENDBASER_LOWER__16_16,Physical Address [31:16]" newline bitfld.long 0x8 7.--9. "REDISTRIBUTOR_CONTROL_LPI_0__9_GICR_PENDBASER_LOWER__7_3,Cacheability" "0,1,2,3,4,5,6,7" line.long 0xC "GIC_REGS_Redistributor_control_LPI_0__10_GICR_PENDBASER_upper,GICR_PENDBASER_upper" bitfld.long 0xC 30. "REDISTRIBUTOR_CONTROL_LPI_0__10_GICR_PENDBASER_UPPER__30_1,Pending Table Zero" "0,1" newline hexmask.long.word 0xC 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_0__10_GICR_PENDBASER_UPPER__0_16,Physical Address [47:32]" group.long 0x4FFD0++0x2F line.long 0x0 "GIC_REGS_Redistributor_control_LPI_0__11_GICR_PIDR4,GICR_PIDR4" line.long 0x4 "GIC_REGS_Redistributor_control_LPI_0__12_GICR_PIDR5,GICR_PIDR5" line.long 0x8 "GIC_REGS_Redistributor_control_LPI_0__13_GICR_PIDR6,GICR_PIDR6" line.long 0xC "GIC_REGS_Redistributor_control_LPI_0__14_GICR_PIDR7,GICR_PIDR7" line.long 0x10 "GIC_REGS_Redistributor_control_LPI_0__15_GICR_PIDR0,GICR_PIDR0" line.long 0x14 "GIC_REGS_Redistributor_control_LPI_0__16_GICR_PIDR1,GICR_PIDR1" line.long 0x18 "GIC_REGS_Redistributor_control_LPI_0__17_GICR_PIDR2,GICR_PIDR2" line.long 0x1C "GIC_REGS_Redistributor_control_LPI_0__18_GICR_PIDR3,GICR_PIDR3" line.long 0x20 "GIC_REGS_Redistributor_control_LPI_0__19_GICR_CIDR0,GICR_CIDR0" line.long 0x24 "GIC_REGS_Redistributor_control_LPI_0__20_GICR_CIDR1,GICR_CIDR1" line.long 0x28 "GIC_REGS_Redistributor_control_LPI_0__21_GICR_CIDR2,GICR_CIDR2" line.long 0x2C "GIC_REGS_Redistributor_control_LPI_0__22_GICR_CIDR3,GICR_CIDR3" group.long 0x50080++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_0__1_GICR_IGROUPR0,GICR_IGROUPR0" group.long 0x50100++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_0__2_GICR_ISENABLER0,GICR_ISENABLER0" group.long 0x50180++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_0__3_GICR_ICENABLER0,GICR_ICENABLER0" group.long 0x50200++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_0__4_GICR_ISPENDR0,GICR_ISPENDR0" group.long 0x50280++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_0__5_GICR_ICPENDR0,GICR_ICPENDR0" group.long 0x50300++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_0__6_GICR_ISACTIVER0,GICR_ISACTIVER0" group.long 0x50380++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_0__7_GICR_ICACTIVER0,GICR_ICACTIVER0" group.long 0x50400++0x1F line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR0,GICR_IPRIORITYR0" line.long 0x4 "GIC_REGS_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR1,GICR_IPRIORITYR1" line.long 0x8 "GIC_REGS_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR2,GICR_IPRIORITYR2" line.long 0xC "GIC_REGS_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR3,GICR_IPRIORITYR3" line.long 0x10 "GIC_REGS_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR4,GICR_IPRIORITYR4" line.long 0x14 "GIC_REGS_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR5,GICR_IPRIORITYR5" line.long 0x18 "GIC_REGS_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR6,GICR_IPRIORITYR6" line.long 0x1C "GIC_REGS_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR7,GICR_IPRIORITYR7" group.long 0x50C00++0x7 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_0__9_GICR_ICFGR0,GICR_ICFGR0" line.long 0x4 "GIC_REGS_Redistributor_SGI_PPI_0__10_GICR_ICFGR1,GICR_ICFGR1" group.long 0x50D00++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_0__11_GICR_IGRPMODR0,GICR_IGRPMODR0" group.long 0x50E00++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_0__12_GICR_NSACR,GICR_NSACR" group.long 0x5C000++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_0__13_GICR_MISCSTATUSR,GICR_MISCSTATUSR" bitfld.long 0x0 31. "REDISTRIBUTOR_SGI_PPI_0__13_GICR_MISCSTATUSR__31_1,cpu_active" "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_SGI_PPI_0__13_GICR_MISCSTATUSR__2_1,EnableGrp1_S" "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_SGI_PPI_0__13_GICR_MISCSTATUSR__1_1,EnableGrp1_NS" "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_SGI_PPI_0__13_GICR_MISCSTATUSR__0_1,EnableGrp0" "0,1" group.long 0x5C080++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_0__14_GICR_PPISR,GICR_PPISR" hexmask.long.word 0x0 16.--31. 1. "REDISTRIBUTOR_SGI_PPI_0__14_GICR_PPISR__16_16,PPI status" group.long 0x60000++0xF line.long 0x0 "GIC_REGS_Redistributor_control_LPI_1__2_GICR_CTLR,GICR_CTLR" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_1__2_GICR_CTLR__31_1,Upstream Write Pending" "0,1" newline bitfld.long 0x0 3. "REDISTRIBUTOR_CONTROL_LPI_1__2_GICR_CTLR__3_1,Register Write Pending" "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_1__2_GICR_CTLR__0_1,Enable LPIs" "0,1" line.long 0x4 "GIC_REGS_Redistributor_control_LPI_1__3_GICR_IIDR,GICR_IIDR" hexmask.long.byte 0x4 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_1__3_GICR_IIDR__24_8,ProductID" newline hexmask.long.byte 0x4 16.--19. 1. "REDISTRIBUTOR_CONTROL_LPI_1__3_GICR_IIDR__16_4,Variant" newline hexmask.long.byte 0x4 12.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_1__3_GICR_IIDR__12_4,Revision" newline hexmask.long.word 0x4 0.--11. 1. "REDISTRIBUTOR_CONTROL_LPI_1__3_GICR_IIDR__0_12,Implementer" line.long 0x8 "GIC_REGS_Redistributor_control_LPI_1__4_GICR_TYPER_lower,GICR_TYPER_lower" hexmask.long.word 0x8 8.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_1__4_GICR_TYPER_LOWER__8_16,Processor Number" newline bitfld.long 0x8 4. "REDISTRIBUTOR_CONTROL_LPI_1__4_GICR_TYPER_LOWER__4_1,Last" "0,1" newline bitfld.long 0x8 3. "REDISTRIBUTOR_CONTROL_LPI_1__4_GICR_TYPER_LOWER__3_1,Distributed" "0,1" newline bitfld.long 0x8 1. "REDISTRIBUTOR_CONTROL_LPI_1__4_GICR_TYPER_LOWER__1_1,VLPIS" "0,1" newline bitfld.long 0x8 0. "REDISTRIBUTOR_CONTROL_LPI_1__4_GICR_TYPER_LOWER__0_1,PLPIS" "0,1" line.long 0xC "GIC_REGS_Redistributor_control_LPI_1__5_GICR_TYPER_upper,GICR_TYPER_upper" hexmask.long.byte 0xC 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_1__5_GICR_TYPER_UPPER__24_8,A3" newline hexmask.long.byte 0xC 16.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_1__5_GICR_TYPER_UPPER__16_8,A2" newline hexmask.long.byte 0xC 8.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_1__5_GICR_TYPER_UPPER__8_8,A1" newline hexmask.long.byte 0xC 0.--7. 1. "REDISTRIBUTOR_CONTROL_LPI_1__5_GICR_TYPER_UPPER__0_8,A0" group.long 0x60014++0x3 line.long 0x0 "GIC_REGS_Redistributor_control_LPI_1__6_GICR_WAKER,GICR_WAKER" bitfld.long 0x0 31. "REDISTRIBUTOR_CONTROL_LPI_1__6_GICR_WAKER__31_1,Quiescent" "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_CONTROL_LPI_1__6_GICR_WAKER__2_1,ChildrenAsleep" "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_CONTROL_LPI_1__6_GICR_WAKER__1_1,ProcessorSleep" "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_CONTROL_LPI_1__6_GICR_WAKER__0_1,Sleep" "0,1" group.long 0x60070++0xF line.long 0x0 "GIC_REGS_Redistributor_control_LPI_1__7_GICR_PROPBASER_lower,GICR_PROPBASER_lower" hexmask.long.tbyte 0x0 12.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_1__7_GICR_PROPBASER_LOWER__12_20,Physical Address [31:12]" newline bitfld.long 0x0 7.--9. "REDISTRIBUTOR_CONTROL_LPI_1__7_GICR_PROPBASER_LOWER__7_3,Cacheability" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "REDISTRIBUTOR_CONTROL_LPI_1__7_GICR_PROPBASER_LOWER__0_5,Idbits" line.long 0x4 "GIC_REGS_Redistributor_control_LPI_1__8_GICR_PROPBASER_upper,GICR_PROPBASER_upper" hexmask.long.word 0x4 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_1__8_GICR_PROPBASER_UPPER__0_16,Physical Address [47:32]" line.long 0x8 "GIC_REGS_Redistributor_control_LPI_1__9_GICR_PENDBASER_lower,GICR_PENDBASER_lower" hexmask.long.word 0x8 16.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_1__9_GICR_PENDBASER_LOWER__16_16,Physical Address [31:16]" newline bitfld.long 0x8 7.--9. "REDISTRIBUTOR_CONTROL_LPI_1__9_GICR_PENDBASER_LOWER__7_3,Cacheability" "0,1,2,3,4,5,6,7" line.long 0xC "GIC_REGS_Redistributor_control_LPI_1__10_GICR_PENDBASER_upper,GICR_PENDBASER_upper" bitfld.long 0xC 30. "REDISTRIBUTOR_CONTROL_LPI_1__10_GICR_PENDBASER_UPPER__30_1,Pending Table Zero" "0,1" newline hexmask.long.word 0xC 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_1__10_GICR_PENDBASER_UPPER__0_16,Physical Address [47:32]" group.long 0x6FFD0++0x2F line.long 0x0 "GIC_REGS_Redistributor_control_LPI_1__11_GICR_PIDR4,GICR_PIDR4" line.long 0x4 "GIC_REGS_Redistributor_control_LPI_1__12_GICR_PIDR5,GICR_PIDR5" line.long 0x8 "GIC_REGS_Redistributor_control_LPI_1__13_GICR_PIDR6,GICR_PIDR6" line.long 0xC "GIC_REGS_Redistributor_control_LPI_1__14_GICR_PIDR7,GICR_PIDR7" line.long 0x10 "GIC_REGS_Redistributor_control_LPI_1__15_GICR_PIDR0,GICR_PIDR0" line.long 0x14 "GIC_REGS_Redistributor_control_LPI_1__16_GICR_PIDR1,GICR_PIDR1" line.long 0x18 "GIC_REGS_Redistributor_control_LPI_1__17_GICR_PIDR2,GICR_PIDR2" line.long 0x1C "GIC_REGS_Redistributor_control_LPI_1__18_GICR_PIDR3,GICR_PIDR3" line.long 0x20 "GIC_REGS_Redistributor_control_LPI_1__19_GICR_CIDR0,GICR_CIDR0" line.long 0x24 "GIC_REGS_Redistributor_control_LPI_1__20_GICR_CIDR1,GICR_CIDR1" line.long 0x28 "GIC_REGS_Redistributor_control_LPI_1__21_GICR_CIDR2,GICR_CIDR2" line.long 0x2C "GIC_REGS_Redistributor_control_LPI_1__22_GICR_CIDR3,GICR_CIDR3" group.long 0x70080++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_1__1_GICR_IGROUPR0,GICR_IGROUPR0" group.long 0x70100++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_1__2_GICR_ISENABLER0,GICR_ISENABLER0" group.long 0x70180++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_1__3_GICR_ICENABLER0,GICR_ICENABLER0" group.long 0x70200++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_1__4_GICR_ISPENDR0,GICR_ISPENDR0" group.long 0x70280++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_1__5_GICR_ICPENDR0,GICR_ICPENDR0" group.long 0x70300++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_1__6_GICR_ISACTIVER0,GICR_ISACTIVER0" group.long 0x70380++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_1__7_GICR_ICACTIVER0,GICR_ICACTIVER0" group.long 0x70400++0x1F line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR0,GICR_IPRIORITYR0" line.long 0x4 "GIC_REGS_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR1,GICR_IPRIORITYR1" line.long 0x8 "GIC_REGS_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR2,GICR_IPRIORITYR2" line.long 0xC "GIC_REGS_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR3,GICR_IPRIORITYR3" line.long 0x10 "GIC_REGS_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR4,GICR_IPRIORITYR4" line.long 0x14 "GIC_REGS_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR5,GICR_IPRIORITYR5" line.long 0x18 "GIC_REGS_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR6,GICR_IPRIORITYR6" line.long 0x1C "GIC_REGS_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR7,GICR_IPRIORITYR7" group.long 0x70C00++0x7 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_1__9_GICR_ICFGR0,GICR_ICFGR0" line.long 0x4 "GIC_REGS_Redistributor_SGI_PPI_1__10_GICR_ICFGR1,GICR_ICFGR1" group.long 0x70D00++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_1__11_GICR_IGRPMODR0,GICR_IGRPMODR0" group.long 0x70E00++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_1__12_GICR_NSACR,GICR_NSACR" group.long 0x7C000++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_1__13_GICR_MISCSTATUSR,GICR_MISCSTATUSR" bitfld.long 0x0 31. "REDISTRIBUTOR_SGI_PPI_1__13_GICR_MISCSTATUSR__31_1,cpu_active" "0,1" newline bitfld.long 0x0 2. "REDISTRIBUTOR_SGI_PPI_1__13_GICR_MISCSTATUSR__2_1,EnableGrp1_S" "0,1" newline bitfld.long 0x0 1. "REDISTRIBUTOR_SGI_PPI_1__13_GICR_MISCSTATUSR__1_1,EnableGrp1_NS" "0,1" newline bitfld.long 0x0 0. "REDISTRIBUTOR_SGI_PPI_1__13_GICR_MISCSTATUSR__0_1,EnableGrp0" "0,1" group.long 0x7C080++0x3 line.long 0x0 "GIC_REGS_Redistributor_SGI_PPI_1__14_GICR_PPISR,GICR_PPISR" hexmask.long.word 0x0 16.--31. 1. "REDISTRIBUTOR_SGI_PPI_1__14_GICR_PPISR__16_16,PPI status" tree.end tree "GICSS0_GIC_TRANSLATER" base ad:0x1000000 group.long 0x30040++0x3 line.long 0x0 "GIC_TRANSLATER_REGS_TRANSLATER__1_GITS_TRANSLATER,GITS_TRANSLATER" hexmask.long 0x0 0.--31. 1. "TRANSLATER__1_GITS_TRANSLATER__0_32,Input ID" tree.end tree "GICSS0_REGS" base ad:0x3F004000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "LPI_RAMECC_PEND,Interrupt Pending Status for lpi_ramecc_pend" "0,1" bitfld.long 0x4 1. "ITE_RAMECC_PEND,Interrupt Pending Status for ite_ramecc_pend" "0,1" bitfld.long 0x4 0. "ICB_RAMECC_PEND,Interrupt Pending Status for icb_ramecc_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "LPI_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lpi_ramecc_pend" "0,1" bitfld.long 0x0 1. "ITE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for ite_ramecc_pend" "0,1" bitfld.long 0x0 0. "ICB_RAMECC_ENABLE_SET,Interrupt Enable Set Register for icb_ramecc_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "LPI_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lpi_ramecc_pend" "0,1" bitfld.long 0x0 1. "ITE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ite_ramecc_pend" "0,1" bitfld.long 0x0 0. "ICB_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for icb_ramecc_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "LPI_RAMECC_PEND,Interrupt Pending Status for lpi_ramecc_pend" "0,1" bitfld.long 0x4 1. "ITE_RAMECC_PEND,Interrupt Pending Status for ite_ramecc_pend" "0,1" bitfld.long 0x4 0. "ICB_RAMECC_PEND,Interrupt Pending Status for icb_ramecc_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "LPI_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lpi_ramecc_pend" "0,1" bitfld.long 0x0 1. "ITE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for ite_ramecc_pend" "0,1" bitfld.long 0x0 0. "ICB_RAMECC_ENABLE_SET,Interrupt Enable Set Register for icb_ramecc_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "LPI_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lpi_ramecc_pend" "0,1" bitfld.long 0x0 1. "ITE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ite_ramecc_pend" "0,1" bitfld.long 0x0 0. "ICB_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for icb_ramecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "GPIO" base ad:0x0 tree "GPIO0" base ad:0x600000 rgroup.long 0x0++0x7 line.long 0x0 "MEM_pid,GPIO Periperal ID Register" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "MEM_PCR,Peripheral Control Register" bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" group.long 0x8++0x3 line.long 0x0 "MEM_BINTEN,Bit Interrupt Enable Register" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." group.long 0x10++0xF line.long 0x0 "MEM_DIR01,Direction Register" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "MEM_OUT_DATA01,Output Drive State Register" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "MEM_SET_DATA01,Set Output Drive State Register" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "MEM_CLR_DATA01,Clear Output Drive State Register" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "MEM_IN_DATA01,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." group.long 0x24++0x23 line.long 0x0 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "MEM_INTSTAT01,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR23,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA23,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA23,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA23,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "MEM_IN_DATA23,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." group.long 0x4C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "MEM_INTSTAT23,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR45,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA45,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA45,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA45,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "MEM_IN_DATA45,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." group.long 0x74++0x23 line.long 0x0 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "MEM_INTSTAT45,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR67,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA67,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA67,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA67,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "MEM_IN_DATA67,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." group.long 0x9C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "MEM_INTSTAT67,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR8,Direction Register" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA8,Output Drive State Register" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA8,Set Output Drive State Register" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA8,Clear Output Drive State Register" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "MEM_IN_DATA8,Bank Status Register" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." group.long 0xC4++0x13 line.long 0x0 "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register" hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." line.long 0x4 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register" hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." line.long 0x8 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register" hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." line.long 0xC "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register" hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." line.long 0x10 "MEM_INTSTAT8,Bank Interrupt Status Register" hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree "GPIO1" base ad:0x601000 rgroup.long 0x0++0x7 line.long 0x0 "MEM_pid,GPIO Periperal ID Register" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "MEM_PCR,Peripheral Control Register" bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" group.long 0x8++0x3 line.long 0x0 "MEM_BINTEN,Bit Interrupt Enable Register" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." group.long 0x10++0xF line.long 0x0 "MEM_DIR01,Direction Register" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "MEM_OUT_DATA01,Output Drive State Register" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "MEM_SET_DATA01,Set Output Drive State Register" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "MEM_CLR_DATA01,Clear Output Drive State Register" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "MEM_IN_DATA01,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." group.long 0x24++0x23 line.long 0x0 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "MEM_INTSTAT01,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR23,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA23,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA23,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA23,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "MEM_IN_DATA23,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." group.long 0x4C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "MEM_INTSTAT23,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR45,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA45,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA45,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA45,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "MEM_IN_DATA45,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." group.long 0x74++0x23 line.long 0x0 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "MEM_INTSTAT45,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR67,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA67,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA67,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA67,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "MEM_IN_DATA67,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." group.long 0x9C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "MEM_INTSTAT67,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR8,Direction Register" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA8,Output Drive State Register" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA8,Set Output Drive State Register" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA8,Clear Output Drive State Register" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "MEM_IN_DATA8,Bank Status Register" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." group.long 0xC4++0x13 line.long 0x0 "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register" hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." line.long 0x4 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register" hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." line.long 0x8 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register" hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." line.long 0xC "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register" hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." line.long 0x10 "MEM_INTSTAT8,Bank Interrupt Status Register" hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree.end tree "GPMC0_CFG" base ad:0x3B000000 group.long 0x0++0x3 line.long 0x0 "CFG_GPMC_REVISION,This register contains the IP revision code" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" group.long 0x10++0xF line.long 0x0 "CFG_GPMC_SYSCONFIG,This register controls the various parameters of the OCP interface" hexmask.long 0x0 5.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0" bitfld.long 0x0 3.--4. "IDLEMODE" "0,1,2,3" newline bitfld.long 0x0 2. "RESERVED,Write 0 for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 1. "RESERVED,This bit must be kept 0 for normal functioning of the IP. Do not set this bit to 1" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" line.long 0x4 "CFG_GPMC_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reads returns 0" hexmask.long.byte 0x4 1.--7. 1. "RESERVED,Reads returns 0 [reserved for OCP-socket status information]" newline rbitfld.long 0x4 0. "RESETDONE,Internal reset monitoring" "0,1" line.long 0x8 "CFG_GPMC_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" bitfld.long 0x8 11. "WAIT3EDGEDETECTIONSTATUS,Status of the Wait3 Edge Detection interrupt" "0,1" newline bitfld.long 0x8 10. "WAIT2EDGEDETECTIONSTATUS,Status of the Wait2 Edge Detection interrupt" "0,1" bitfld.long 0x8 9. "WAIT1EDGEDETECTIONSTATUS,Status of the Wait1 Edge Detection interrupt" "0,1" newline bitfld.long 0x8 8. "WAIT0EDGEDETECTIONSTATUS,Status of the Wait0 Edge Detection interrupt" "0,1" hexmask.long.byte 0x8 2.--7. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline bitfld.long 0x8 1. "TERMINALCOUNTSTATUS,Status of the TerminalCountEvent interrupt" "0,1" bitfld.long 0x8 0. "FIFOEVENTSTATUS,Status of the FIFOEvent interrupt" "0,1" line.long 0xC "CFG_GPMC_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" bitfld.long 0xC 11. "WAIT3EDGEDETECTIONENABLE,Enables the Wait3 Edge Detection interrupt" "0,1" newline bitfld.long 0xC 10. "WAIT2EDGEDETECTIONENABLE,Enables the Wait2 Edge Detection interrupt" "0,1" bitfld.long 0xC 9. "WAIT1EDGEDETECTIONENABLE,Enables the Wait1 Edge Detection interrupt" "0,1" newline bitfld.long 0xC 8. "WAIT0EDGEDETECTIONENABLE,Enables the Wait0 Edge Detection interrupt" "0,1" hexmask.long.byte 0xC 2.--7. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline bitfld.long 0xC 1. "TERMINALCOUNTEVENTENABLE,Enables TerminalCountEvent interrupt issuing in pre-fetch or write posting mode" "0,1" bitfld.long 0xC 0. "FIFOEVENTENABLE,Enables the FIFOEvent interrupt" "0,1" group.long 0x40++0xB line.long 0x0 "CFG_GPMC_TIMEOUT_CONTROL,The GPMC_TIMEOUT_CONTROL register allows the user to set the start value of the timeout counter" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" hexmask.long.word 0x0 4.--12. 1. "TIMEOUTSTARTVALUE,Start value of the time-out counter [0x000 corresponds to 0 GPMC.FCLK cycle 0x001 corresponds to 1 GmpcClk cycle & 0x1FF corresponds to 511 GPMC.FCLK cyles.]" newline bitfld.long 0x0 1.--3. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "TIMEOUTENABLE,Enable bit of the TimeOut feature" "0,1" line.long 0x4 "CFG_GPMC_ERR_ADDRESS,The GPMC_ERR_ADDRESS register stores the address of the illegal access when an error occurs" bitfld.long 0x4 31. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" hexmask.long 0x4 0.--30. 1. "ILLEGALADD,Address of illegal access : A30[0 for memory region 1 for GPMC register region] and A29-A0[1 GBytes maximum]" line.long 0x8 "CFG_GPMC_ERR_TYPE,The GPMC_ERR_TYPE register stores the type of error when an error occurs" hexmask.long.tbyte 0x8 11.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" rbitfld.long 0x8 8.--10. "ILLEGALMCMD,System Command of the transaction that caused the error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 5.--7. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" rbitfld.long 0x8 4. "ERRORNOTSUPPADD,Not supported Address error" "0,1" newline rbitfld.long 0x8 3. "ERRORNOTSUPPMCMD,Not supported Command error" "0,1" rbitfld.long 0x8 2. "ERRORTIMEOUT,Time-out error" "0,1" newline bitfld.long 0x8 1. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" bitfld.long 0x8 0. "ERRORVALID,Error validity status - Must be explicitely cleared with a write 1 transaction" "0,1" group.long 0x50++0x7 line.long 0x0 "CFG_GPMC_CONFIG,The configuration register allows global configuration of the GPMC" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" bitfld.long 0x0 11. "WAIT3PINPOLARITY,Selects the polarity of input pin WAIT3" "0,1" newline bitfld.long 0x0 10. "WAIT2PINPOLARITY,Selects the polarity of input pin WAIT2" "0,1" bitfld.long 0x0 9. "WAIT1PINPOLARITY,Selects the polarity of input pin WAIT1" "0,1" newline bitfld.long 0x0 8. "WAIT0PINPOLARITY,Selects the polarity of input pin WAIT0" "0,1" bitfld.long 0x0 5.--7. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "WRITEPROTECT,Controls the WP output pin level" "0,1" bitfld.long 0x0 2.--3. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3" newline bitfld.long 0x0 1. "LIMITEDADDRESS,Limited Address device support" "0,1" bitfld.long 0x0 0. "NANDFORCEPOSTEDWRITE,Enables the Force Posted Write feature to NAND Cmd/Add/Data location" "0,1" line.long 0x4 "CFG_GPMC_STATUS,The status register provides global status bits of the GPMC" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" rbitfld.long 0x4 11. "WAIT3STATUS,Is a copy of input pin WAIT3. [Reset value is WAIT3 input pin sampled at IC reset]" "0,1" newline rbitfld.long 0x4 10. "WAIT2STATUS,Is a copy of input pin WAIT2. [Reset value is WAIT2 input pin sampled at IC reset]" "0,1" rbitfld.long 0x4 9. "WAIT1STATUS,Is a copy of input pin WAIT1. [Reset value is WAIT1 input pin sampled at IC reset]" "0,1" newline rbitfld.long 0x4 8. "WAIT0STATUS,Is a copy of input pin WAIT0. [Reset value is WAIT0 input pin sampled at IC reset]" "0,1" hexmask.long.byte 0x4 1.--7. 1. "RESERVED,Write 0's for future compatibility Reads returns 0" newline rbitfld.long 0x4 0. "EMPTYWRITEBUFFERSTATUS,Stores the empty status of the write buffer" "0,1" group.long 0x1E0++0x7 line.long 0x0 "CFG_GPMC_PREFETCH_CONFIG1,Prefetch engine configuration 1" bitfld.long 0x0 31. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" bitfld.long 0x0 28.--30. "CYCLEOPTIMIZATION,Define the number of GPMC.FCLK cycles to be substracted from RdCycleTime WrCycleTime AccessTime CSRdOffTime CSWrOffTime ADVRdOffTime ADVWrOffTime OEOffTime WEOffTime [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "ENABLEOPTIMIZEDACCESS,Enables access cycle optimization" "0,1" bitfld.long 0x0 24.--26. "ENGINECSSELECTOR,Selects the CS where Prefetch Postwrite engine is active [0x0 corresponds toCS0 0x1 corresponds to CS1 & 0x7 corresponds to CS7]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "PFPWENROUNDROBIN,Enables the PFPW RoundRobin arbitration" "0,1" bitfld.long 0x0 20.--22. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "PFPWWEIGHTEDPRIO,When an arbitration occurs between a direct memory access and a PFPW engine access the direct memory access is always serviced. If the PFPWEnRoundRobin is enabled 0x0 means : the next access is granted to the PFPW engine 0x1 means :.." bitfld.long 0x0 15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "FIFOTHRESHOLD,Selects the maximum number of bytes read from the FIFO or written to the FIFO by the host on a DMA or interrupt request [0x00 corresponds to 0 byte 0x01 corresponds to 1 byte & 0x40 corresponds to 64 bytes]" bitfld.long 0x0 7. "ENABLEENGINE,Enables the Prefetch Postwite engine" "0,1" newline bitfld.long 0x0 6. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" bitfld.long 0x0 4.--5. "WAITPINSELECTOR,Select which wait pin edge detector should start the engine in synchronized mode" "0,1,2,3" newline bitfld.long 0x0 3. "SYNCHROMODE,Selects when the engine starts the access to CS" "0,1" bitfld.long 0x0 2. "DMAMODE,Selects interrupt synchronization or DMA request synchronization" "0,1" newline bitfld.long 0x0 1. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" bitfld.long 0x0 0. "ACCESSMODE,Selects pre-fetch read or write posting accesses" "0,1" line.long 0x4 "CFG_GPMC_PREFETCH_CONFIG2,Prefetch engine configuration 2" hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" hexmask.long.word 0x4 0.--13. 1. "TRANSFERCOUNT,Selects the number of bytes to be read or written by the engine to the selected CS [0x0000 corresponds to 0 byte 0x0001 corresponds to 1 byte & 0x2000 corresponds to 8 Kbytes]" group.long 0x1EC++0x17 line.long 0x0 "CFG_GPMC_PREFETCH_CONTROL,Prefetch engine control" hexmask.long 0x0 1.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" bitfld.long 0x0 0. "STARTENGINE,Resets the FIFO pointer and starts the engine" "0,1" line.long 0x4 "CFG_GPMC_PREFETCH_STATUS,Prefetch engine status" bitfld.long 0x4 31. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" hexmask.long.byte 0x4 24.--30. 1. "FIFOPOINTER,Number of available bytes to be read or number of free empty byte places to be written [0x00 corresponds to 0 byte available to be read or 0 free empty place to be written & 0x40 corresponds to 64 bytes available to be read or 64 empty.." newline hexmask.long.byte 0x4 17.--23. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" rbitfld.long 0x4 16. "FIFOTHRESHOLDSTATUS,Set when FIFOPointer exceeds FIFOThreshold value" "0,1" newline bitfld.long 0x4 14.--15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3" hexmask.long.word 0x4 0.--13. 1. "COUNTVALUE,Number of remaining bytes to be read or to be written by the engine according to the TransferCount value [0x0000 corresponds to 0 byte remaining to be read or to be written 0x0001 corresponds to 1 byte remaining to be read or to be written .." line.long 0x8 "CFG_GPMC_ECC_CONFIG,ECC configuration" hexmask.long.word 0x8 17.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" bitfld.long 0x8 16. "ECCALGORITHM,ECC algorithm used 0x0: Hamming code 0x1: BCH code" "0: Hamming code,1: BCH code" newline bitfld.long 0x8 14.--15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3" bitfld.long 0x8 12.--13. "ECCBCHTSEL,Error correction capability used for BCH 0x0: up to 4 bits error correction [t = 4] 0x1: up to 8 bits error correction [t=8] 0x2: up to 16 bits error correction [t=16] 0x3: reserved" "0: up to 4 bits error correction [t = 4],1: up to 8 bits error correction [t=8],2: up to 16 bits error correction [t=16],3: reserved" newline hexmask.long.byte 0x8 8.--11. 1. "ECCWRAPMODE,Spare area organization definition for the BCH algorithm. See the BCH syndrome/parity calculator module functional specification for more details" bitfld.long 0x8 7. "ECC16B,Selects an ECC calculated on 16 columns" "0,1" newline bitfld.long 0x8 4.--6. "ECCTOPSECTOR,Number of sectors to process with the BCH algorithm 0x0: 1 sector [512kB page] 0x1: 2 sectors ... 0x3: 4 sectors [2kB page] ... 0x7: 8 sectors [4kB page]" "0: 1 sector [512kB page],1: 2 sectors,?,3: 4 sectors [2kB page],?,?,?,7: 8 sectors [4kB page]" bitfld.long 0x8 1.--3. "ECCCS,Selects the CS where ECC is computed" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "ECCENABLE,Enables the ECC feature" "0,1" line.long 0xC "CFG_GPMC_ECC_CONTROL,ECC control" hexmask.long.tbyte 0xC 9.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" bitfld.long 0xC 8. "ECCCLEAR,Clear all ECC result registers [Reads returns 0 - Writes 1 to this field clear all ECC result registers - Writes 0 are ignored]" "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" hexmask.long.byte 0xC 0.--3. 1. "ECCPOINTER,Selects ECC result register [Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored]; Other enums: writing other values disables the.." line.long 0x10 "CFG_GPMC_ECC_SIZE_CONFIG,ECC size" bitfld.long 0x10 30.--31. "RESERVED,Write 0's for future compatibility. Read returns 3" "0,1,2,3" hexmask.long.byte 0x10 22.--29. 1. "ECCSIZE1,Defines ECC size 1 [0x00 corresponds to 2 Bytes 0x01 corresponds to 4 Bytes 0x02 corresponds to 6 Bytes 0x03 corresponds to 8 Bytes & 0xFF corresponds to 512 Bytes]" newline bitfld.long 0x10 20.--21. "RESERVED,Write 0's for future compatibility. Read returns 3" "0,1,2,3" hexmask.long.byte 0x10 12.--19. 1. "ECCSIZE0,Defines ECC size 0 [0x00 corresponds to 2 Bytes 0x01 corresponds to 4 Bytes 0x02 corresponds to 6 Bytes 0x03 corresponds to 8 Bytes & 0xFF corresponds to 512 Bytes]" newline bitfld.long 0x10 9.--11. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8. "ECC9RESULTSIZE,Selects ECC size for ECC 9 result register" "0,1" newline bitfld.long 0x10 7. "ECC8RESULTSIZE,Selects ECC size for ECC 8 result register" "0,1" bitfld.long 0x10 6. "ECC7RESULTSIZE,Selects ECC size for ECC 7 result register" "0,1" newline bitfld.long 0x10 5. "ECC6RESULTSIZE,Selects ECC size for ECC 6 result register" "0,1" bitfld.long 0x10 4. "ECC5RESULTSIZE,Selects ECC size for ECC 5 result register" "0,1" newline bitfld.long 0x10 3. "ECC4RESULTSIZE,Selects ECC size for ECC 4 result register" "0,1" bitfld.long 0x10 2. "ECC3RESULTSIZE,Selects ECC size for ECC 3 result register" "0,1" newline bitfld.long 0x10 1. "ECC2RESULTSIZE,Selects ECC size for ECC 2 result register" "0,1" bitfld.long 0x10 0. "ECC1RESULTSIZE,Selects ECC size for ECC 1 result register" "0,1" line.long 0x14 "CFG_GPMC_ECC_RESULT,ECC result register" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" rbitfld.long 0x14 27. "P2048O,Odd Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1" newline rbitfld.long 0x14 26. "P1024O,Odd Row Parity bit 1024" "0,1" rbitfld.long 0x14 25. "P512O,Odd Row Parity bit 512" "0,1" newline rbitfld.long 0x14 24. "P256O,Odd Row Parity bit 256" "0,1" rbitfld.long 0x14 23. "P128O,Odd Row Parity bit 128" "0,1" newline rbitfld.long 0x14 22. "P64O,Odd Row Parity bit 64" "0,1" rbitfld.long 0x14 21. "P32O,Odd Row Parity bit 32" "0,1" newline rbitfld.long 0x14 20. "P16O,Odd Row Parity bit 16" "0,1" rbitfld.long 0x14 19. "P8O,Odd Row Parity bit 8" "0,1" newline rbitfld.long 0x14 18. "P4O,Odd Column Parity bit 4" "0,1" rbitfld.long 0x14 17. "P2O,Odd Column Parity bit 2" "0,1" newline rbitfld.long 0x14 16. "P1O,Odd Column Parity bit 1" "0,1" hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline rbitfld.long 0x14 11. "P2048E,Even Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1" rbitfld.long 0x14 10. "P1024E,Even Row Parity bit 1024" "0,1" newline rbitfld.long 0x14 9. "P512E,Even Row Parity bit 512" "0,1" rbitfld.long 0x14 8. "P256E,Even Row Parity bit 256" "0,1" newline rbitfld.long 0x14 7. "P128E,Even Row Parity bit 128" "0,1" rbitfld.long 0x14 6. "P64E,Even Row Parity bit 64" "0,1" newline rbitfld.long 0x14 5. "P32E,Even Row Parity bit 32" "0,1" rbitfld.long 0x14 4. "P16E,Even Row Parity bit 16" "0,1" newline rbitfld.long 0x14 3. "P8E,Even Row Parity bit 8" "0,1" rbitfld.long 0x14 2. "P4E,Even Column Parity bit 4" "0,1" newline rbitfld.long 0x14 1. "P2E,Even Column Parity bit 2" "0,1" rbitfld.long 0x14 0. "P1E,Even Column Parity bit 1" "0,1" wgroup.long 0x2D0++0x3 line.long 0x0 "CFG_GPMC_BCH_SWDATA,This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface." hexmask.long.word 0x0 0.--15. 1. "BCH_DATA,Data to be included in the BCH calculation. Only bits 0 to 7 are taken into account if the calculator is configured to use 8 bits data [ECC16B = 0]" group.long 0x60++0x1B line.long 0x0 "CFG_GPMC_CONFIG1,The configuration 1 register sets signal control parameters per chip select" bitfld.long 0x0 31. "WRAPBURST,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst" "0,1" bitfld.long 0x0 30. "READMULTIPLE,Selects the read single or multiple access" "0,1" newline bitfld.long 0x0 29. "READTYPE,Selects the read mode operation" "0,1" bitfld.long 0x0 28. "WRITEMULTIPLE,Selects the write single or multiple access" "0,1" newline bitfld.long 0x0 27. "WRITETYPE,Selects the write mode operation" "0,1" bitfld.long 0x0 25.--26. "CLKACTIVATIONTIME,Output GPMC.CLK activation time" "0,1,2,3" newline bitfld.long 0x0 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page [burst] length" "0,1,2,3" bitfld.long 0x0 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses [Reset value is BOOTWAITEN input pin sampled at IC reset]" "0,1" newline bitfld.long 0x0 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "0,1" bitfld.long 0x0 20. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" newline bitfld.long 0x0 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "0,1,2,3" bitfld.long 0x0 16.--17. "WAITPINSELECT,Selects the input WAIT pin for this chip select [Reset value is BOOTWAITSELECT input pin sampled at IC reset for CS0 and 0 for CS1-7]" "0,1,2,3" newline bitfld.long 0x0 14.--15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3" bitfld.long 0x0 12.--13. "DEVICESIZE,Selects the device size attached [Reset value is BOOTDEVICESIZE input pin sampled at IC reset for CS0 and 01 for CS1-7]" "0,1,2,3" newline bitfld.long 0x0 10.--11. "DEVICETYPE,Selects the attached device type" "0,1,2,3" bitfld.long 0x0 8.--9. "MUXADDDATA,Enables the Address and data multiplexed protocol [Reset value is CS0MUXDEVICE input pin sampled at IC reset for CS0 and 0 for CS1-7]" "0,1,2,3" newline bitfld.long 0x0 5.--7. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor [Rd/WRCycleTime AccessTime PageBurstAccessTime CSOnTime CSRd/WrOffTime ADVOnTime ADVRd/WrOffTime OEOnTime OEOffTime WEOnTime WEOffTime Cycle2CycleDelay BusTurnAround TimeOutStartValue]" "0,1" newline bitfld.long 0x0 2.--3. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3" bitfld.long 0x0 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC.FCLK clock" "0,1,2,3" line.long 0x4 "CFG_GPMC_CONFIG2,Chip-select signal timing parameter configuration" hexmask.long.word 0x4 21.--31. 1. "RESERVED,Write 0's for future compatibility Reads returns 0" hexmask.long.byte 0x4 16.--20. 1. "CSWROFFTIME,CS# de-assertion time from start cycle time for write accesses [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" newline bitfld.long 0x4 13.--15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "CSRDOFFTIME,CS# de-assertion time from start cycle time for read accesses [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" newline bitfld.long 0x4 7. "CSEXTRADELAY,CS# Add Extra Half GPMC.FCLK cycle" "0,1" bitfld.long 0x4 4.--6. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "CSONTIME,CS# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" line.long 0x8 "CFG_GPMC_CONFIG3,ADV# signal timing parameter configuration" rbitfld.long 0x8 31. "RESERVED_1,Write 0's for future compatibility. Read returns 0" "0,1" bitfld.long 0x8 28.--30. "ADVAADMUXWROFFTIME,ADV# de-assertion for first address phase when using the AAD-Mux protocol" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 27. "RESERVED_0,Write 0's for future compatibility. Read returns 0" "0,1" bitfld.long 0x8 24.--26. "ADVAADMUXRDOFFTIME,ADV# assertion for first address phase when using the AAD-Mux protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 21.--23. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 16.--20. 1. "ADVWROFFTIME,ADV# de-assertion time from start cycle time for write accesses [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" newline bitfld.long 0x8 13.--15. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--12. 1. "ADVRDOFFTIME,ADV# de-assertion time from start cycle time for read accesses[0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" newline bitfld.long 0x8 7. "ADVEXTRADELAY,ADV# Add Extra Half GPMC.FCLK cycle" "0,1" bitfld.long 0x8 4.--6. "ADVAADMUXONTIME,ADV# assertion for first address phase when using the AAD-Mux protocol" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--3. 1. "ADVONTIME,ADV# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" line.long 0xC "CFG_GPMC_CONFIG4,WE# and OE# signals timing parameter configuration" rbitfld.long 0xC 29.--31. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--28. 1. "WEOFFTIME,WE# de-assertion time from start cycle time [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" newline bitfld.long 0xC 23. "WEEXTRADELAY,WE# Add Extra Half GPMC.FCLK cycle" "0,1" bitfld.long 0xC 20.--22. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--19. 1. "WEONTIME,WE# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" bitfld.long 0xC 13.--15. "OEAADMUXOFFTIME,OE# de-assertion time for the first address phase in an AAD-Mux access" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--12. 1. "OEOFFTIME,OE# de-assertion time from start cycle time [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" bitfld.long 0xC 7. "OEEXTRADELAY,OE# Add Extra Half GPMC.FCLK cycle" "0,1" newline bitfld.long 0xC 4.--6. "OEAADMUXONTIME,OE# assertion time for the first address phase in an AAD-Mux access" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "OEONTIME,OE# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" line.long 0x10 "CFG_GPMC_CONFIG5,RdAccessTime and CycleTime timing parameters configuration" hexmask.long.byte 0x10 28.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" hexmask.long.byte 0x10 24.--27. 1. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" newline bitfld.long 0x10 21.--23. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 16.--20. 1. "RDACCESSTIME,Delay between start cycle time and first data valid [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" newline bitfld.long 0x10 13.--15. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 8.--12. 1. "WRCYCLETIME,Total write cycle time [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" newline bitfld.long 0x10 5.--7. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--4. 1. "RDCYCLETIME,Total read cycle time [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" line.long 0x14 "CFG_GPMC_CONFIG6,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x14 31. "RESERVED,TI Internal use - Do not modify" "0,1" bitfld.long 0x14 29.--30. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1,2,3" newline hexmask.long.byte 0x14 24.--28. 1. "WRACCESSTIME,Delay from StartAccessTime to the GPMC.FCLK rising edge corresponding the the GPMC.CLK rising edge used by the attached memory for the first data capture [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F.." hexmask.long.byte 0x14 20.--23. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline hexmask.long.byte 0x14 16.--19. 1. "WRDATAONADMUXBUS,Specifies on which GPMC.FCLK rising edge the first data of the synchronous burst write is driven in the add/data mux bus" hexmask.long.byte 0x14 12.--15. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" newline hexmask.long.byte 0x14 8.--11. 1. "CYCLE2CYCLEDELAY,Chip select high pulse delay between two successive accesses [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add Cycle2CycleDelay between two successive accesses to the same chip-select [any access type]" "0,1" newline bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add Cycle2CycleDelay between two successive accesses to a different chip-select [any access type]" "0,1" bitfld.long 0x14 4.--5. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3" newline hexmask.long.byte 0x14 0.--3. 1. "BUSTURNAROUND,Bus turn around latency between two successive accesses to the same chip-select [rd to wr] or to a different chip-select [read to read and read to write] [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF.." line.long 0x18 "CFG_GPMC_CONFIG7,Chip-select address mapping configuration" hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED,Write 0's for future compatibility. Read returns 0" hexmask.long.byte 0x18 8.--11. 1. "MASKADDRESS,Chip-select mask address" newline bitfld.long 0x18 7. "RESERVED,Write 0's for future compatibility. Read returns 0" "0,1" bitfld.long 0x18 6. "CSVALID,Chip-select enable [reset value is 1 for CS0 and 0 for CS1-7]" "0,1" newline hexmask.long.byte 0x18 0.--5. 1. "BASEADDRESS,Chip-select base address" wgroup.long 0x7C++0x7 line.long 0x0 "CFG_GPMC_NAND_COMMAND,This Register is not a true register. just a address location." hexmask.long 0x0 0.--31. 1. "GPMC_NAND_COMMAND_0" line.long 0x4 "CFG_GPMC_NAND_ADDRESS,This Register is not a true register. just a address location." hexmask.long 0x4 0.--31. 1. "GPMC_NAND_ADDRESS_0" group.long 0x84++0x3 line.long 0x0 "CFG_GPMC_NAND_DATA,This Register is not a true register. just a address location." hexmask.long 0x0 0.--31. 1. "GPMC_NAND_DATA_0" rgroup.long 0x240++0xF line.long 0x0 "CFG_GPMC_BCH_RESULT_0,BCH ECC result. bits 0 to 31" hexmask.long 0x0 0.--31. 1. "BCH_RESULT_0,BCH ECC result bits 0 to 31" line.long 0x4 "CFG_GPMC_BCH_RESULT_1,BCH ECC result. bits 32 to 63" hexmask.long 0x4 0.--31. 1. "BCH_RESULT_1,BCH ECC result bits 32 to 63" line.long 0x8 "CFG_GPMC_BCH_RESULT_2,BCH ECC result. bits 64 to 95" hexmask.long 0x8 0.--31. 1. "BCH_RESULT_2,BCH ECC result bits 64 to 95" line.long 0xC "CFG_GPMC_BCH_RESULT_3,BCH ECC result. bits 96 to 127" hexmask.long 0xC 0.--31. 1. "BCH_RESULT_3,BCH ECC result bits 96 to 127" rgroup.long 0x300++0xB line.long 0x0 "CFG_GPMC_BCH_RESULT_4,BCH ECC result. bits 128 to 159" hexmask.long 0x0 0.--31. 1. "BCH_RESULT_4,BCH ECC result bits 128 to 159" line.long 0x4 "CFG_GPMC_BCH_RESULT_5,BCH ECC result. bits 160 to 191" hexmask.long 0x4 0.--31. 1. "BCH_RESULT_5,BCH ECC result bits 160 to 191" line.long 0x8 "CFG_GPMC_BCH_RESULT_6,BCH ECC result. bits 192 to 207" hexmask.long.word 0x8 0.--15. 1. "BCH_RESULT_6,BCH ECC result bits 192 to 207" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "I2C" base ad:0x0 tree "I2C0_CFG" base ad:0x20000000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" group.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "I2C1_CFG" base ad:0x20010000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" group.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "I2C2_CFG" base ad:0x20020000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" group.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "I2C3_CFG" base ad:0x20030000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" group.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "JPGENC" base ad:0x0 tree "JPGENC0_CORE" base ad:0xFD20000 rgroup.long 0x0++0x7 line.long 0x0 "CORE_REGS_CR_JASPER_CORE_ID" hexmask.long.byte 0x0 24.--31. 1. "CR_GROUP_ID,This identifies the core as part of an IMG IP family group." newline hexmask.long.byte 0x0 16.--23. 1. "CR_CORE_ID,This identifies the member of the IP group." newline hexmask.long.word 0x0 3.--15. 1. "CR_UNIQUE_NUM,E5010 core unique identifier." newline bitfld.long 0x0 0.--2. "CR_PELS_PER_CYCLE,Number of pels processed simultaneously. Allowed values are '010' and '100'." "0,1,2,3,4,5,6,7" line.long 0x4 "CORE_REGS_CR_JASPER_CORE_REV" hexmask.long.byte 0x4 24.--31. 1. "CR_JASPER_DESIGNER,Company ID [Allocated by IMG]." newline hexmask.long.byte 0x4 16.--23. 1. "CR_JASPER_MAJOR_REV,Core major revision." newline hexmask.long.byte 0x4 8.--15. 1. "CR_JASPER_MINOR_REV,Core minor revision." newline hexmask.long.byte 0x4 0.--7. 1. "CR_JASPER_MAINT_REV,Core maintenance revision." group.long 0x8++0x3 line.long 0x0 "CORE_REGS_CR_JASPER_INTERRUPT_MASK" hexmask.long 0x0 2.--31. 1. "RESERVED_2" newline bitfld.long 0x0 1. "CR_OUTPUT_ADDRESS_ERROR_ENABLE,Enable generation of output address error interrupt." "0,1" newline bitfld.long 0x0 0. "CR_PICTURE_DONE_ENABLE,Enable generation of PICTURE_DONE interrupt." "0,1" rgroup.long 0xC++0x3 line.long 0x0 "CORE_REGS_CR_JASPER_INTERRUPT_STATUS" hexmask.long 0x0 2.--31. 1. "RESERVED_2" newline bitfld.long 0x0 1. "CR_OUTPUT_ADDRESS_ERROR_IRQ,Output bitstream size exceeded value stored in CR_JASPER_OUTPUT_MAX_SIZE register. [Pulse generated at event held by edge detection logic]." "0,1" newline bitfld.long 0x0 0. "CR_PICTURE_DONE_IRQ,Processing of picture is done. [Pulse generated at event held by edge detection logic]." "0,1" wgroup.long 0x10++0x3 line.long 0x0 "CORE_REGS_CR_JASPER_INTERRUPT_CLEAR" hexmask.long 0x0 2.--31. 1. "RESERVED_2" newline bitfld.long 0x0 1. "CR_OUTPUT_ERROR_CLEAR,Writing '1' to this field clears OUTPUT_ADDRESS_ERROR flag [JASPER_INTERRUPT_STATUS register]. This field is self-clear. When read it will always return zero." "0,1" newline bitfld.long 0x0 0. "CR_PICTURE_DONE_CLEAR,Writing '1' to this field clears PICTURE_DONE_IRQ flag [JASPER_INTERRUPT_STATUS register]. This field is self-clear. When read it will always return zero." "0,1" group.long 0x14++0x3 line.long 0x0 "CORE_REGS_CR_JASPER_CLK_CONTROL" hexmask.long 0x0 2.--31. 1. "RESERVED_2" newline bitfld.long 0x0 1. "CR_JASPER_AUTO_CLKG_ENABLE,0: disable auto clock gating 1: enable auto clock gating" "0: disable auto clock gating,1: enable auto clock gating" newline bitfld.long 0x0 0. "CR_JASPER_MAN_CLKG_ENABLE,Writing '1' to this field enables clocking of the E5010 core." "0,1" rgroup.long 0x18++0x3 line.long 0x0 "CORE_REGS_CR_JASPER_CLK_STATUS" hexmask.long 0x0 1.--31. 1. "RESERVED_1" newline bitfld.long 0x0 0. "CR_JASPER_CLKG_STATUS,Indicates the clock gate status 1: clock gating is off 0: clock gating is on" "0: clock gating is on,1: clock gating is off" wgroup.long 0x1C++0x3 line.long 0x0 "CORE_REGS_CR_JASPER_RESET" hexmask.long 0x0 2.--31. 1. "RESERVED_2" newline bitfld.long 0x0 1. "CR_SYS_RESET,When set forces a reset of the whole IP. It is self-cleared." "0,1" newline bitfld.long 0x0 0. "CR_CORE_RESET,When set forces a reset of the core modules except the core registers. It is self-cleared." "0,1" group.long 0x20++0x3 line.long 0x0 "CORE_REGS_CR_JASPER_CORE_CTRL" hexmask.long 0x0 1.--31. 1. "RESERVED_1" newline bitfld.long 0x0 0. "CR_JASPER_ENCODE_START,This bit can be written only when JASPER_BUSY flag is set to '0' [JASPER_CORE_STATUS register. Writing '1' forces E5010 to start encoding of an image and sets JASPER_BUSY flag to '1'. Writing '0' has no effect. This bit is.." "0,1" rgroup.long 0x24++0x3 line.long 0x0 "CORE_REGS_CR_JASPER_STATUS" hexmask.long 0x0 2.--31. 1. "RESERVED_2" newline bitfld.long 0x0 1. "CR_FLUSH_MODE,This field has value '1' when output address error occurred [output bitstream size exceeded value stored in CR_JASPER_OUTPUT_MAX_SIZE register]. It is self-cleared after recovering from the error state." "0,1" newline bitfld.long 0x0 0. "CR_JASPER_BUSY,When set up it indicates pending encoding process. It is automatically cleared after image encoding process finishes if image source is memory. In case of stream encoding this flag is cleared after a single frame has been encoded." "0,1" wgroup.long 0x28++0x3 line.long 0x0 "CORE_REGS_CR_JASPER_CRC_CLEAR,Active high resets for the CRCs. CRCs are cleared on writing the relevant bit of this register to '1'. The register bit will then self-clear. When read. this register will always return zero." hexmask.long 0x0 6.--31. 1. "RESERVED_6" newline bitfld.long 0x0 5. "CR_PACKING_BUFFER_CRC_CLEAR,0 : Has no effect 1 : Clear Packing buffer CRC" "0: Has no effect,1: Clear Packing buffer CRC" newline bitfld.long 0x0 4. "CR_ENTROPY_ENCODER_CRC_CLEAR,0 : Has no effect 1 : Clear Entropy encoder CRC" "0: Has no effect,1: Clear Entropy encoder CRC" newline bitfld.long 0x0 3. "CR_QUANT_CRC_CLEAR,0 : Has no effect 1 : Clear Quantization block CRC" "0: Has no effect,1: Clear Quantization block CRC" newline bitfld.long 0x0 2. "CR_ZZ_CRC_CLEAR,0 : Has no effect 1 : Clear Zig-zag CRC" "0: Has no effect,1: Clear Zig-zag CRC" newline bitfld.long 0x0 1. "CR_DCT_CRC_CLEAR,0 : Has no effect 1 : Clear DCT CRC" "0: Has no effect,1: Clear DCT CRC" newline bitfld.long 0x0 0. "CR_FRONT_END_CRC_CLEAR,0 : Has no effect 1 : Clear Front End CRC" "0: Has no effect,1: Clear Front End CRC" group.long 0x2C++0x1B line.long 0x0 "CORE_REGS_CR_JASPER_INPUT_CTRL0" hexmask.long.byte 0x0 25.--31. 1. "RESERVED_25" newline bitfld.long 0x0 24. "CR_INPUT_CHROMA_ORDER,Defines order of interleaved chroma pels in memory '0': chroma data in order Cb-Cr '1': chroma data in order Cr-Cb" "0: chroma data in order Cb-Cr,1: chroma data in order Cr-Cb" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED_18" newline bitfld.long 0x0 16.--17. "CR_INPUT_SUBSAMPLING,Chroma subsampling format. 0x00: Reserved 0x01: 4:2:0 0x02: 4:2:2 0x03: Reserved" "0: Reserved,?,2: 2,3: Reserved" newline hexmask.long.word 0x0 3.--15. 1. "RESERVED_3" newline bitfld.long 0x0 2. "CR_INPUT_SOURCE,Input data source. 0: direct 1: memory" "0: direct,1: memory" newline rbitfld.long 0x0 0.--1. "RESERVED_0" "0,1,2,3" line.long 0x4 "CORE_REGS_CR_JASPER_INPUT_CTRL1" rbitfld.long 0x4 29.--31. "RESERVED_29" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 22.--28. 1. "CR_INPUT_LUMA_STRIDE,Width of pixels' line of luma data in memory; multiples of 64 bytes. 0 denotes maximum value - 128x64 B" newline hexmask.long.word 0x4 13.--21. 1. "RESERVED_13" newline hexmask.long.byte 0x4 6.--12. 1. "CR_INPUT_CHROMA_STRIDE,Width of pixels' line of chroma data in memory; multiples of 64 bytes. 0 denotes maximum value - 128x64 B" newline hexmask.long.byte 0x4 0.--5. 1. "RESERVED_0" line.long 0x8 "CORE_REGS_CR_JASPER_MMU_CTRL,Setting this register is applicable only when processing image from system memory." hexmask.long 0x8 2.--31. 1. "RESERVED_2" newline bitfld.long 0x8 1. "CR_JASPER_TILING_SCHEME,Tiling scheme 0 = 256x16 1 = 512*8. This bit must be set to the same value as MMU_TILING_SCHEME in MMU_CONTROL0 register [see IMG_VIDEO_BUS4_MMU registers]." "0: 256x16,1: 512*8" newline bitfld.long 0x8 0. "CR_JASPER_TILING_ENABLE,Indicates that memory tiling in the MMU is enabled. Should be set to the same value as TILE_ENABLE bit in MMU_TILE_CFGn register [see IMG_VIDEO_BUS4_MMU registers]. NOTE: Memory tiling inside the E5010 core can be applied to input.." "0,1" line.long 0xC "CORE_REGS_CR_JASPER_IMAGE_SIZE" rbitfld.long 0xC 29.--31. "RESERVED_29" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC 16.--28. 1. "CR_IMAGE_VERTICAL_SIZE,Number of lines in an image - 1." newline rbitfld.long 0xC 13.--15. "RESERVED_13" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0xC 0.--12. 1. "CR_IMAGE_HORIZONTAL_SIZE,Number of pixels per line - 1." line.long 0x10 "CORE_REGS_CR_INPUT_LUMA_BASE" hexmask.long 0x10 6.--31. 1. "CR_INPUT_LUMA_BASE,Address of input luma data. Aligned to 64 bytes." newline hexmask.long.byte 0x10 0.--5. 1. "RESERVED_0" line.long 0x14 "CORE_REGS_CR_INPUT_CHROMA_BASE" hexmask.long 0x14 6.--31. 1. "CR_INPUT_CHROMA_BASE,Address of input chroma data. Aligned to 64 bytes." newline hexmask.long.byte 0x14 0.--5. 1. "RESERVED_0" line.long 0x18 "CORE_REGS_CR_JASPER_OUTPUT_BASE" hexmask.long 0x18 0.--31. 1. "CR_OUTPUT_BASE,Base address for output bitstream." rgroup.long 0x48++0x3 line.long 0x0 "CORE_REGS_CR_JASPER_OUTPUT_SIZE,Set when image processing is done (busy flag transits from 1 to 0). Cleared automatically after start of next frame compression." hexmask.long 0x0 0.--31. 1. "CR_OUTPUT_SIZE,Output bitstream size in bytes." group.long 0x4C++0x87 line.long 0x0 "CORE_REGS_CR_JASPER_OUTPUT_MAX_SIZE" hexmask.long 0x0 0.--31. 1. "CR_OUTPUT_MAX_SIZE,Maximum size of output bitstream. Should be set to the size of allocated memory. If set to 0 address checking is disabled." line.long 0x4 "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE0,Luma quantization table entries QL03..QL00" hexmask.long.byte 0x4 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_03,QL03" newline hexmask.long.byte 0x4 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_02,QL02" newline hexmask.long.byte 0x4 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_01,QL01" newline hexmask.long.byte 0x4 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_00,QL00" line.long 0x8 "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE1,QL07..QL04" hexmask.long.byte 0x8 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_07,QL07" newline hexmask.long.byte 0x8 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_06,QL06" newline hexmask.long.byte 0x8 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_05,QL05" newline hexmask.long.byte 0x8 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_04,QL04" line.long 0xC "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE2,QL13..QL10" hexmask.long.byte 0xC 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_13,QL13" newline hexmask.long.byte 0xC 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_12,QL12" newline hexmask.long.byte 0xC 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_11,QL11" newline hexmask.long.byte 0xC 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_10,QL10" line.long 0x10 "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE3,QL17..QL14" hexmask.long.byte 0x10 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_17,QL17" newline hexmask.long.byte 0x10 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_16,QL16" newline hexmask.long.byte 0x10 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_15,QL15" newline hexmask.long.byte 0x10 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_14,QL14" line.long 0x14 "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE4,QL23..QL20" hexmask.long.byte 0x14 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_23,QL23" newline hexmask.long.byte 0x14 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_22,QL22" newline hexmask.long.byte 0x14 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_21,QL21" newline hexmask.long.byte 0x14 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_20,QL20" line.long 0x18 "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE5,QL27..QL24" hexmask.long.byte 0x18 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_27,QL27" newline hexmask.long.byte 0x18 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_26,QL26" newline hexmask.long.byte 0x18 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_25,QL25" newline hexmask.long.byte 0x18 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_24,QL24" line.long 0x1C "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE6,QL33..QL30" hexmask.long.byte 0x1C 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_33,QL33" newline hexmask.long.byte 0x1C 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_32,QL32" newline hexmask.long.byte 0x1C 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_31,QL31" newline hexmask.long.byte 0x1C 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_30,QL30" line.long 0x20 "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE7,QL37..QL34" hexmask.long.byte 0x20 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_37,QL37" newline hexmask.long.byte 0x20 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_36,QL36" newline hexmask.long.byte 0x20 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_35,QL35" newline hexmask.long.byte 0x20 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_34,QL34" line.long 0x24 "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE8,QL43..QL40" hexmask.long.byte 0x24 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_43,QL43" newline hexmask.long.byte 0x24 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_42,QL42" newline hexmask.long.byte 0x24 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_41,QL41" newline hexmask.long.byte 0x24 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_40,QL40" line.long 0x28 "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE9,QL47..QL44" hexmask.long.byte 0x28 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_47,QL47" newline hexmask.long.byte 0x28 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_46,QL46" newline hexmask.long.byte 0x28 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_45,QL45" newline hexmask.long.byte 0x28 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_44,QL44" line.long 0x2C "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE10,QL53..QL50" hexmask.long.byte 0x2C 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_53,QL53" newline hexmask.long.byte 0x2C 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_52,QL52" newline hexmask.long.byte 0x2C 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_51,QL51" newline hexmask.long.byte 0x2C 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_50,QL50" line.long 0x30 "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE11,QL57..QL54" hexmask.long.byte 0x30 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_57,QL57" newline hexmask.long.byte 0x30 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_56,QL56" newline hexmask.long.byte 0x30 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_55,QL55" newline hexmask.long.byte 0x30 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_54,QL54" line.long 0x34 "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE12,QL63..QL60" hexmask.long.byte 0x34 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_63,QL63" newline hexmask.long.byte 0x34 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_62,QL62" newline hexmask.long.byte 0x34 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_61,QL61" newline hexmask.long.byte 0x34 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_60,QL60" line.long 0x38 "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE13,QL67..QL64" hexmask.long.byte 0x38 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_67,QL67" newline hexmask.long.byte 0x38 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_66,QL66" newline hexmask.long.byte 0x38 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_65,QL65" newline hexmask.long.byte 0x38 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_64,QL64" line.long 0x3C "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE14,QL73..QL70" hexmask.long.byte 0x3C 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_73,QL73" newline hexmask.long.byte 0x3C 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_72,QL72" newline hexmask.long.byte 0x3C 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_71,QL71" newline hexmask.long.byte 0x3C 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_70,QL70" line.long 0x40 "CORE_REGS_CR_JASPER_LUMA_QUANTIZATION_TABLE15,QL77..QL74" hexmask.long.byte 0x40 24.--31. 1. "CR_LUMA_QUANTIZATION_TABLE_77,QL77" newline hexmask.long.byte 0x40 16.--23. 1. "CR_LUMA_QUANTIZATION_TABLE_76,QL76" newline hexmask.long.byte 0x40 8.--15. 1. "CR_LUMA_QUANTIZATION_TABLE_75,QL75" newline hexmask.long.byte 0x40 0.--7. 1. "CR_LUMA_QUANTIZATION_TABLE_74,QL74" line.long 0x44 "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE0,Chroma quantization table entries QC03..QC00" hexmask.long.byte 0x44 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_03,QC03" newline hexmask.long.byte 0x44 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_02,QC02" newline hexmask.long.byte 0x44 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_01,QC01" newline hexmask.long.byte 0x44 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_00,QC00" line.long 0x48 "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE1,QC07..QC04" hexmask.long.byte 0x48 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_07,QC07" newline hexmask.long.byte 0x48 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_06,QC06" newline hexmask.long.byte 0x48 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_05,QC05" newline hexmask.long.byte 0x48 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_04,QC04" line.long 0x4C "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE2,QC13..QC10" hexmask.long.byte 0x4C 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_13,QC13" newline hexmask.long.byte 0x4C 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_12,QC12" newline hexmask.long.byte 0x4C 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_11,QC11" newline hexmask.long.byte 0x4C 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_10,QC10" line.long 0x50 "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE3,QC17..QC14" hexmask.long.byte 0x50 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_17,QC17" newline hexmask.long.byte 0x50 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_16,QC16" newline hexmask.long.byte 0x50 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_15,QC15" newline hexmask.long.byte 0x50 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_14,QC14" line.long 0x54 "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE4,QC23..QC20" hexmask.long.byte 0x54 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_23,QC23" newline hexmask.long.byte 0x54 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_22,QC22" newline hexmask.long.byte 0x54 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_21,QC21" newline hexmask.long.byte 0x54 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_20,QC20" line.long 0x58 "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE5,QC27..QC24" hexmask.long.byte 0x58 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_27,QC27" newline hexmask.long.byte 0x58 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_26,QC26" newline hexmask.long.byte 0x58 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_25,QC25" newline hexmask.long.byte 0x58 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_24,QC24" line.long 0x5C "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE6,QC33..QC30" hexmask.long.byte 0x5C 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_33,QC33" newline hexmask.long.byte 0x5C 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_32,QC32" newline hexmask.long.byte 0x5C 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_31,QC31" newline hexmask.long.byte 0x5C 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_30,QC30" line.long 0x60 "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE7,QC37..QC34" hexmask.long.byte 0x60 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_37,QC37" newline hexmask.long.byte 0x60 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_36,QC36" newline hexmask.long.byte 0x60 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_35,QC35" newline hexmask.long.byte 0x60 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_34,QC34" line.long 0x64 "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE8,QC43..QC40" hexmask.long.byte 0x64 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_43,QC43" newline hexmask.long.byte 0x64 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_42,QC42" newline hexmask.long.byte 0x64 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_41,QC41" newline hexmask.long.byte 0x64 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_40,QC40" line.long 0x68 "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE9,QC47..QC44" hexmask.long.byte 0x68 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_47,QC47" newline hexmask.long.byte 0x68 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_46,QC46" newline hexmask.long.byte 0x68 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_45,QC45" newline hexmask.long.byte 0x68 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_44,QC44" line.long 0x6C "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE10,QC53..QC50" hexmask.long.byte 0x6C 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_53,QC53" newline hexmask.long.byte 0x6C 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_52,QC52" newline hexmask.long.byte 0x6C 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_51,QC51" newline hexmask.long.byte 0x6C 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_50,QC50" line.long 0x70 "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE11,QC57..QC54" hexmask.long.byte 0x70 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_57,QC57" newline hexmask.long.byte 0x70 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_56,QC56" newline hexmask.long.byte 0x70 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_55,QC55" newline hexmask.long.byte 0x70 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_54,QC54" line.long 0x74 "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE12,QC63..QC60" hexmask.long.byte 0x74 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_63,QC63" newline hexmask.long.byte 0x74 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_62,QC62" newline hexmask.long.byte 0x74 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_61,QC61" newline hexmask.long.byte 0x74 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_60,QC60" line.long 0x78 "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE13,QC67..QC64" hexmask.long.byte 0x78 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_67,QC67" newline hexmask.long.byte 0x78 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_66,QC66" newline hexmask.long.byte 0x78 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_65,QC65" newline hexmask.long.byte 0x78 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_64,QC64" line.long 0x7C "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE14,QC73..QC70" hexmask.long.byte 0x7C 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_73,QC73" newline hexmask.long.byte 0x7C 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_72,QC72" newline hexmask.long.byte 0x7C 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_71,QC71" newline hexmask.long.byte 0x7C 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_70,QC70" line.long 0x80 "CORE_REGS_CR_JASPER_CHROMA_QUANTIZATION_TABLE15,QC77..QC74" hexmask.long.byte 0x80 24.--31. 1. "CR_CHROMA_QUANTIZATION_TABLE_77,QC77" newline hexmask.long.byte 0x80 16.--23. 1. "CR_CHROMA_QUANTIZATION_TABLE_76,QC76" newline hexmask.long.byte 0x80 8.--15. 1. "CR_CHROMA_QUANTIZATION_TABLE_75,QC75" newline hexmask.long.byte 0x80 0.--7. 1. "CR_CHROMA_QUANTIZATION_TABLE_74,QC74" line.long 0x84 "CORE_REGS_CR_JASPER_CRC_CTRL" hexmask.long 0x84 1.--31. 1. "RESERVED_1" newline bitfld.long 0x84 0. "JASPER_CRC_ENABLE,Writing '1' to this field enables CRC calculation." "0,1" rgroup.long 0xD4++0x1B line.long 0x0 "CORE_REGS_CR_JASPER_FRONT_END_CRC" hexmask.long 0x0 0.--31. 1. "CR_JASPER_FRONT_END_CRC_OUT,CRC value of the current data." line.long 0x4 "CORE_REGS_CR_JASPER_DCT_CRC" hexmask.long 0x4 0.--31. 1. "CR_JASPER_DCT_CRC_OUT,CRC value of the current data." line.long 0x8 "CORE_REGS_CR_JASPER_ZZ_CRC" hexmask.long 0x8 0.--31. 1. "CR_JASPER_ZZ_CRC_OUT,CRC value of the current data." line.long 0xC "CORE_REGS_CR_JASPER_QUANT_CRC" hexmask.long 0xC 0.--31. 1. "CR_JASPER_QUANT_CRC_OUT,CRC value of the current data. ang1045" line.long 0x10 "CORE_REGS_CR_JASPER_ENTROPY_ENCODER_CRC" hexmask.long 0x10 0.--31. 1. "CR_JASPER_ENTROPY_CRC_OUT,CRC value of the current data." line.long 0x14 "CORE_REGS_CR_JASPER_PACKING_BUFFER_DATA_CRC" hexmask.long 0x14 0.--31. 1. "CR_JASPER_PACKING_DATA_CRC_OUT,CRC value of the current data." line.long 0x18 "CORE_REGS_CR_JASPER_PACKING_BUFFER_ADDR_CRC" hexmask.long 0x18 0.--31. 1. "CR_JASPER_PACKING_ADDR_OUT_CRC,CRC value of the current data." tree.end tree "JPGENC0_CORE_MMU" base ad:0xFD20200 group.long 0x0++0x3 line.long 0x0 "CORE_MMU_REGS_MMU_CONTROL0" hexmask.long.word 0x0 17.--31. 1. "RESERVED_17" newline bitfld.long 0x0 16. "USE_TILE_STRIDE_PER_CONTEXT,1: Separate MMU_TILE_CFG fields apply per context 0: All contexts use MMU_TILE_CFG for context 0" "0: All contexts use MMU_TILE_CFG for context 0,1: Separate MMU_TILE_CFG fields apply per context" newline rbitfld.long 0x0 13.--15. "RESERVED_13" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "STALL_ON_PROTOCOL_FAULT,Debug only:Setting this bit to '1' causes any requestor with a protocol fault to stall" "0,1" newline rbitfld.long 0x0 10.--11. "RESERVED_10" "0,1,2,3" newline bitfld.long 0x0 9. "FORCE_CACHE_POLICY_BYPASS,Setting this bit to '1' causes all requests to external memory to have a cache policy of 0 [bypass] setting this bit to '0' passes internal cache policy to external interface" "0,1" newline bitfld.long 0x0 8. "MMU_CACHE_POLICY,1: MMU Directory/Page Table reads to be flagged as cacheable [external cache must have a way of flushing/tracking changes to Directory Table and Page Tables in host memory] 0: MMU reads to be flagged to bypass external cache" "0: MMU reads to be flagged to bypass external cache,1: MMU Directory/Page Table reads to be flagged as.." newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED_1" newline bitfld.long 0x0 0. "MMU_TILING_SCHEME,This bit controls the tiling scheme described in MMU Address Tiling section 0: Original tiling scheme [256-byte wide by 16 row tiles] 1: Alternative tiling scheme [512-byte wide by 8 row tiles]" "0: Original tiling scheme [256-byte wide by 16 row..,1: Alternative tiling scheme [512-byte wide by 8.." group.long 0x8++0x3 line.long 0x0 "CORE_MMU_REGS_MMU_CONTROL1" rbitfld.long 0x0 29.--31. "RESERVED_29" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "MMU_SOFT_RESET,Writing '1' to this bit causes all currently active or new memory requests to be discarded so a reset of all active requestors is likely to also be required. External memory transactions will attempt to complete [including writing 0 data.." "0,1" newline rbitfld.long 0x0 26.--27. "RESERVED_26" "0,1,2,3" newline bitfld.long 0x0 25. "MMU_PAUSE_CLEAR,Writing '1' to this bit clears the pause bit and allows new memory requests to resume. Writing '0' has no affect. Reading this field indicates if the pause bit is currently set. Setting both 'MMU_PAUSE_SET' and 'MMU_PAUSE_CLEAR' in the.." "0,1" newline bitfld.long 0x0 24. "MMU_PAUSE_SET,Writing '1' to this bit causes all new memory requests to pause [requests further down the pipeline will be allowed to complete]. Writing '0' has no affect. Reading this field indicates if the pause bit is currently set. Setting both.." "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED_21" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "PROTOCOL_FAULT_CLEAR,Writing '1' to this bit clears all bus protocol fault flags. Writing '0' has no affect" "0,1" newline rbitfld.long 0x0 17.--19. "RESERVED_17" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "MMU_FAULT_CLEAR,Writing '1' to this bit clears MMU fault [either page fault or read/write fault]. Writing '0' has no affect" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_12" newline bitfld.long 0x0 11. "MMU_INVALDC,For each 'dir_base_addr' used writing '1' triggers invalidation[/flushing] of both the directory cache and page table cache for that 'dir_base_addr' [cached results for different 'dir_base_addr' can be invalidated/flushed independently]." "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED_4" newline bitfld.long 0x0 3. "MMU_FLUSH,For each 'dir_base_addr' used writing '1' triggers a flush of the Page Table cache and registered results for that 'dir_base_addr' [cached results for different 'dir_base_addr' can be flushed independently]. Writing '0' has no affect" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "CORE_MMU_REGS_MMU_BANK_INDEX" hexmask.long 0x0 0.--31. 1. "RESERVED,Specify which directory base address to use for 'group override' input n [If GROUP_OVERRIDE_SIZE is 0 this register is not used otherwise there are '2 to the power GROUP_OVERRIDE_SIZE' entries supported in this register" group.long 0x14++0x3 line.long 0x0 "CORE_MMU_REGS_EXT_REQUEST_PRIORITY_ENABLE" rgroup.long 0x18++0x7 line.long 0x0 "CORE_MMU_REGS_REQUEST_PRIORITY_ENABLE" hexmask.long.word 0x0 17.--31. 1. "RESERVED_17" line.long 0x4 "CORE_MMU_REGS_REQUEST_LIMITED_THROUGHPUT,RESERVED" hexmask.long.byte 0x4 28.--31. 1. "RESERVED_28" newline hexmask.long.byte 0x4 10.--15. 1. "RESERVED_10" group.long 0x20++0x3 line.long 0x0 "CORE_MMU_REGS_MMU_DIR_BASE_ADDR_00" hexmask.long 0x0 4.--31. 1. "MMU_DIR_BASE_ADDR,Base address in physical memory for MMU Directory n Entries. When MMU_ENABLE_EXT_ADDRESSING is '1' the bits 31:0 are assigned to the address 31+EXT_ADDR_RANGE:0+EXT_ADDR_RANGE but then any address offset within a page is forced to 0." newline hexmask.long.byte 0x0 0.--3. 1. "MMU_DIR_BASE_ADDR_LSBS,Bits 3:0 of this register are read-only and hardcoded in RTL at 0x0" rgroup.long 0x24++0xB line.long 0x0 "CORE_MMU_REGS_MMU_DIR_BASE_ADDR_01" hexmask.long 0x0 0.--31. 1. "MMU_DIR_BASE_ADDR,GROUP_OVERRIDE_SIZE hardcoded at 0 in RTL. Hence this register is read only and returns 0x0" line.long 0x4 "CORE_MMU_REGS_MMU_DIR_BASE_ADDR_02" hexmask.long 0x4 0.--31. 1. "MMU_DIR_BASE_ADDR,GROUP_OVERRIDE_SIZE hardcoded at 0 in RTL. Hence this register is read only and returns 0x0" line.long 0x8 "CORE_MMU_REGS_MMU_DIR_BASE_ADDR_03" hexmask.long 0x8 0.--31. 1. "MMU_DIR_BASE_ADDR,GROUP_OVERRIDE_SIZE hardcoded at 0 in RTL. Hence this register is read only and returns 0x0" group.long 0x40++0x33 line.long 0x0 "CORE_MMU_REGS_MMU_TILE_CFG_00,If USE_TILE_STRIDE_PER_CONTEXT is low. only the bottom byte of the register is used. and each of the four registers applies to the four regions defined by the corresponding MIN and MAX tile address ranges." rbitfld.long 0x0 29.--31. "RESERVED_29" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "TILE_128INTERLEAVE_SPCR3,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0x0 27. "TILE_ENABLE_SPCR3,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0x0 24.--26. "TILE_STRIDE_SPCR3,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 21.--23. "RESERVED_21" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "TILE_128INTERLEAVE_SPCR2,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0x0 19. "TILE_ENABLE_SPCR2,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0x0 16.--18. "TILE_STRIDE_SPCR2,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 13.--15. "RESERVED_13" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "TILE_128INTERLEAVE_SPCR1,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0x0 11. "TILE_ENABLE_SPCR1,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0x0 8.--10. "TILE_STRIDE_SPCR1,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 5.--7. "RESERVED_5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "TILE_128INTERLEAVE,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0x0 3. "TILE_ENABLE,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0x0 0.--2. "TILE_STRIDE,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" line.long 0x4 "CORE_MMU_REGS_MMU_TILE_CFG_01,If USE_TILE_STRIDE_PER_CONTEXT is low. only the bottom byte of the register is used. and each of the four registers applies to the four regions defined by the corresponding MIN and MAX tile address ranges." rbitfld.long 0x4 29.--31. "RESERVED_29" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "TILE_128INTERLEAVE_SPCR3,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0x4 27. "TILE_ENABLE_SPCR3,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0x4 24.--26. "TILE_STRIDE_SPCR3,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 21.--23. "RESERVED_21" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "TILE_128INTERLEAVE_SPCR2,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0x4 19. "TILE_ENABLE_SPCR2,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0x4 16.--18. "TILE_STRIDE_SPCR2,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 13.--15. "RESERVED_13" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12. "TILE_128INTERLEAVE_SPCR1,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0x4 11. "TILE_ENABLE_SPCR1,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0x4 8.--10. "TILE_STRIDE_SPCR1,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 5.--7. "RESERVED_5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "TILE_128INTERLEAVE,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0x4 3. "TILE_ENABLE,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0x4 0.--2. "TILE_STRIDE,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" line.long 0x8 "CORE_MMU_REGS_MMU_TILE_CFG_02,If USE_TILE_STRIDE_PER_CONTEXT is low. only the bottom byte of the register is used. and each of the four registers applies to the four regions defined by the corresponding MIN and MAX tile address ranges." rbitfld.long 0x8 29.--31. "RESERVED_29" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "TILE_128INTERLEAVE_SPCR3,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0x8 27. "TILE_ENABLE_SPCR3,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0x8 24.--26. "TILE_STRIDE_SPCR3,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 21.--23. "RESERVED_21" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "TILE_128INTERLEAVE_SPCR2,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0x8 19. "TILE_ENABLE_SPCR2,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0x8 16.--18. "TILE_STRIDE_SPCR2,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 13.--15. "RESERVED_13" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12. "TILE_128INTERLEAVE_SPCR1,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0x8 11. "TILE_ENABLE_SPCR1,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0x8 8.--10. "TILE_STRIDE_SPCR1,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 5.--7. "RESERVED_5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "TILE_128INTERLEAVE,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0x8 3. "TILE_ENABLE,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0x8 0.--2. "TILE_STRIDE,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" line.long 0xC "CORE_MMU_REGS_MMU_TILE_CFG_03,If USE_TILE_STRIDE_PER_CONTEXT is low. only the bottom byte of the register is used. and each of the four registers applies to the four regions defined by the corresponding MIN and MAX tile address ranges." rbitfld.long 0xC 29.--31. "RESERVED_29" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 28. "TILE_128INTERLEAVE_SPCR3,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0xC 27. "TILE_ENABLE_SPCR3,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0xC 24.--26. "TILE_STRIDE_SPCR3,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 21.--23. "RESERVED_21" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20. "TILE_128INTERLEAVE_SPCR2,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0xC 19. "TILE_ENABLE_SPCR2,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0xC 16.--18. "TILE_STRIDE_SPCR2,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 13.--15. "RESERVED_13" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12. "TILE_128INTERLEAVE_SPCR1,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0xC 11. "TILE_ENABLE_SPCR1,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0xC 8.--10. "TILE_STRIDE_SPCR1,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 5.--7. "RESERVED_5" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "TILE_128INTERLEAVE,0 : Customizable address manipulation of tiled accesses is not enabled 1 : Customizable address manipulation of tiled accesses is enabled" "0: Customizable address manipulation of tiled..,1: Customizable address manipulation of tiled.." newline bitfld.long 0xC 3. "TILE_ENABLE,0 : Memory Tiling Disabled 1 : Memory Tiling Enabled" "0: Memory Tiling Disabled,1: Memory Tiling Enabled" newline bitfld.long 0xC 0.--2. "TILE_STRIDE,Defines the X Tile Stride for the memory address range [stride is 2 to the power of [9+tile_stride+tiling_scheme]]" "0,1,2,3,4,5,6,7" line.long 0x10 "CORE_MMU_REGS_MMU_TILE_MIN_ADDR_00" hexmask.long.tbyte 0x10 12.--31. 1. "TILE_MIN_ADDR,Defines the minimum address for tiling range in terms of the virtual address MSB's i.e. 31:TILE_ADDR_GRANULARITY" newline hexmask.long.word 0x10 0.--11. 1. "TILE_MIN_ADDR_LSBS,TILE_ADDR_GRANULARITY is hardcoded in RTL at 12 [decimal]. Hence bits 11:0 of this register are read-only and hardcoded in RTL at 0x000" line.long 0x14 "CORE_MMU_REGS_MMU_TILE_MIN_ADDR_01" hexmask.long.tbyte 0x14 12.--31. 1. "TILE_MIN_ADDR,Defines the minimum address for tiling range in terms of the virtual address MSB's i.e. 31:TILE_ADDR_GRANULARITY" newline hexmask.long.word 0x14 0.--11. 1. "TILE_MIN_ADDR_LSBS,TILE_ADDR_GRANULARITY is hardcoded in RTL at 12 [decimal]. Hence bits 11:0 of this register are read-only and hardcoded in RTL at 0x000" line.long 0x18 "CORE_MMU_REGS_MMU_TILE_MIN_ADDR_02" hexmask.long.tbyte 0x18 12.--31. 1. "TILE_MIN_ADDR,Defines the minimum address for tiling range in terms of the virtual address MSB's i.e. 31:TILE_ADDR_GRANULARITY" newline hexmask.long.word 0x18 0.--11. 1. "TILE_MIN_ADDR_LSBS,TILE_ADDR_GRANULARITY is hardcoded in RTL at 12 [decimal]. Hence bits 11:0 of this register are read-only and hardcoded in RTL at 0x000" line.long 0x1C "CORE_MMU_REGS_MMU_TILE_MIN_ADDR_03" hexmask.long.tbyte 0x1C 12.--31. 1. "TILE_MIN_ADDR,Defines the minimum address for tiling range in terms of the virtual address MSB's i.e. 31:TILE_ADDR_GRANULARITY" newline hexmask.long.word 0x1C 0.--11. 1. "TILE_MIN_ADDR_LSBS,TILE_ADDR_GRANULARITY is hardcoded in RTL at 12 [decimal]. Hence bits 11:0 of this register are read-only and hardcoded in RTL at 0x000" line.long 0x20 "CORE_MMU_REGS_MMU_TILE_MAX_ADDR_00" hexmask.long.tbyte 0x20 12.--31. 1. "TILE_MAX_ADDR,Defines the maximum address for tiling range in terms of the virtual address MSB's i.e. 31:TILE_ADDR_GRANULARITY" newline hexmask.long.word 0x20 0.--11. 1. "TILE_MAX_ADDR_LSBS,TILE_ADDR_GRANULARITY is hardcoded in RTL at 12 [decimal]. Hence bits 11:0 of this register are read-only and hardcoded in RTL at 0x000" line.long 0x24 "CORE_MMU_REGS_MMU_TILE_MAX_ADDR_01" hexmask.long.tbyte 0x24 12.--31. 1. "TILE_MAX_ADDR,Defines the maximum address for tiling range in terms of the virtual address MSB's i.e. 31:TILE_ADDR_GRANULARITY" newline hexmask.long.word 0x24 0.--11. 1. "TILE_MAX_ADDR_LSBS,TILE_ADDR_GRANULARITY is hardcoded in RTL at 12 [decimal]. Hence bits 11:0 of this register are read-only and hardcoded in RTL at 0x000" line.long 0x28 "CORE_MMU_REGS_MMU_TILE_MAX_ADDR_02" hexmask.long.tbyte 0x28 12.--31. 1. "TILE_MAX_ADDR,Defines the maximum address for tiling range in terms of the virtual address MSB's i.e. 31:TILE_ADDR_GRANULARITY" newline hexmask.long.word 0x28 0.--11. 1. "TILE_MAX_ADDR_LSBS,TILE_ADDR_GRANULARITY is hardcoded in RTL at 12 [decimal]. Hence bits 11:0 of this register are read-only and hardcoded in RTL at 0x000" line.long 0x2C "CORE_MMU_REGS_MMU_TILE_MAX_ADDR_03" hexmask.long.tbyte 0x2C 12.--31. 1. "TILE_MAX_ADDR,Defines the maximum address for tiling range in terms of the virtual address MSB's i.e. 31:TILE_ADDR_GRANULARITY" newline hexmask.long.word 0x2C 0.--11. 1. "TILE_MAX_ADDR_LSBS,TILE_ADDR_GRANULARITY is hardcoded in RTL at 12 [decimal]. Hence bits 11:0 of this register are read-only and hardcoded in RTL at 0x000" line.long 0x30 "CORE_MMU_REGS_MMU_ADDRESS_CONTROL" hexmask.long.byte 0x30 24.--31. 1. "RESERVED_24" newline hexmask.long.byte 0x30 16.--23. 1. "UPPER_ADDRESS_FIXED,If 'EXTENDED_ADDR_RANGE' is > 0 and MMU is used in bypass mode or MMU_ENABLE_EXT_ADDRESSING = '0' EXTENDED_ADDR_RANGE bits from this field will be used to define the state of the upper physical address bits [for all memory requests]" newline hexmask.long.byte 0x30 11.--15. 1. "RESERVED_11" newline bitfld.long 0x30 8.--10. "SOFT_PAGE_SIZE,This field selects MMU page size at run time [if this field is less than the minimum hardware configuration for PAGE_SIZE from MMU_CONFIG1 then the PAGE_SIZE will be used]" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 5.--7. "RESERVED_5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 4. "MMU_ENABLE_EXT_ADDRESSING,1: Directory/Page Table entries loaded into MSBits of physical address bus 0: Directory/Page Table entries loaded into bits 31 downwards of physical address bus" "0: Directory/Page Table entries loaded into bits 31..,1: Directory/Page Table entries loaded into MSBits.." newline rbitfld.long 0x30 1.--3. "RESERVED_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 0. "MMU_BYPASS,1: All memory requests bypass the 'Address Translation' part of the MMU but tiling can still be enabled 0: All memory requests use of the 'Address Translation' part of the MMU" "0: All memory requests use of the 'Address..,1: All memory requests bypass the 'Address.." rgroup.long 0x80++0x17 line.long 0x0 "CORE_MMU_REGS_MMU_CONFIG0" hexmask.long.word 0x0 22.--31. 1. "TAGS_SUPPORTED,Number of outstanding bursts supported" newline bitfld.long 0x0 21. "NO_READ_REORDER,If this field is set it indicates there is no read data re-ordering buffer [all requestors must accept read response out of order]" "0,1" newline hexmask.long.byte 0x0 16.--20. 1. "TILE_ADDR_GRANULARITY,This field indicates the granularity of the tile address range [where virtual address range is matched from [31:TILE_ADDR_GRANULARITY]]" newline bitfld.long 0x0 14.--15. "NUM_REQUESTORS_EXT,In MMU version 4.2 onwards NUM_REQUESTORS_EXT*16 + NUM_REQUESTORS indicates the number of requestors the core has been configured for [before version 4.2 this field was always 0]" "0,1,2,3" newline bitfld.long 0x0 13. "MMU_SUPPORTED,This field indicates if MMU page table mapping is supported [N.B. tiling can still be used even if the MMU is not supported]" "0,1" newline bitfld.long 0x0 12. "ADDR_COHERENCY_SUPPORTED,This field indicates if address coherency checking is supported [if it is not supported requestors need to use another mechanism to gurantee reads and writes to the same address don't occur out of order]" "0,1" newline bitfld.long 0x0 11. "RESERVED_11" "0,1" newline bitfld.long 0x0 8.--10. "GROUP_OVERRIDE_SIZE,If this field is 0 only 1 directory base address is supported [MMU_DIR_BASE_ADDR0]. If this field is 1 only the first two entries in MMU_BANK_INDEX are used to select one of 4 base addresses. If this field is 2 there are 4.." "?,?,?,3: 8 entries,4: 16 entries,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "EXTENDED_ADDR_RANGE,This field indicates the number of extended address bits [above 32] that the external memory interface uses" newline hexmask.long.byte 0x0 0.--3. 1. "NUM_REQUESTORS,Before MMU version 4.2 this field indicates the number of requestors the core has been configured for [between 1 and 15 or a value of 0 =16 requestors]. In MMU version 4.2 onwards this field + NUM_REQUESTORS_EXT*16 indicates the number.." line.long 0x4 "CORE_MMU_REGS_MMU_CONFIG1" bitfld.long 0x4 31. "RESERVED_31" "0,1" newline bitfld.long 0x4 30. "SUPPORT_EXCLUSIVE,Logic included to support exclusive transactions [for doing read-modify-write without another master modifying the value]" "0,1" newline bitfld.long 0x4 29. "SUPPORT_STRIDE_PER_CONTEXT,Logic included to support separate tile stride per context" "0,1" newline bitfld.long 0x4 28. "SUPPORT_READ_INTERLEAVE,Logic included to support interleaved read responses [violates Bus4 protocol but may occur when Bus4 to AXI bridge is used]" "0,1" newline bitfld.long 0x4 27. "RESERVED_27" "0,1" newline bitfld.long 0x4 26. "LATENCY_COUNT_SUPPORTED,Latency counts included" "0,1" newline bitfld.long 0x4 25. "STALL_COUNT_SUPPORTED,Stall counts included" "0,1" newline bitfld.long 0x4 24. "BANDWIDTH_COUNT_SUPPORTED,Bandwidth counts included" "0,1" newline bitfld.long 0x4 21.--23. "RESERVED_21" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--20. 1. "DIR_CACHE_ENTRIES,DIR_CACHE_ENTRIES * 128 defines the number of Directory Table entries which can be cached" newline hexmask.long.byte 0x4 8.--15. 1. "PAGE_CACHE_ENTRIES,PAGE_CACHE_ENTRIES * 128 defines the number of Page Table entries which can be cached" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED_4" newline hexmask.long.byte 0x4 0.--3. 1. "PAGE_SIZE,Log2 MMU page size minus 12 [4kbyte page = 0 16kbyte page = 2]" line.long 0x8 "CORE_MMU_REGS_MMU_STATUS0" hexmask.long.tbyte 0x8 12.--31. 1. "MMU_FAULT_ADDR,Page-aligned virtual address causing page fault" newline hexmask.long.word 0x8 1.--11. 1. "RESERVED_1" newline bitfld.long 0x8 0. "MMU_PF_N_RW,Indicates whether the current fault is a page fault [when high] or R/W protection fault [when low]" "0,1" line.long 0xC "CORE_MMU_REGS_MMU_STATUS1" bitfld.long 0xC 29.--31. "RESERVED_29" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 28. "MMU_FAULT_RNW,Indicates if a read or write operation caused the current fault" "0,1" newline bitfld.long 0xC 26.--27. "RESERVED_26" "0,1,2,3" newline bitfld.long 0xC 24.--25. "MMU_FAULT_INDEX,Indicates the directory cache index of the current fault" "0,1,2,3" newline bitfld.long 0xC 22.--23. "RESERVED_22" "0,1,2,3" newline hexmask.long.byte 0xC 16.--21. 1. "MMU_FAULT_REQ_ID,Indicates the requestor ID of the request causing the current page fault" newline hexmask.long.word 0xC 0.--15. 1. "MMU_FAULT_REQ_STAT,1-bit per requestor indicating if requestor triggered a page fault [in the event there are more than 16 requestors modulo 16 arithmetic is used to assign 1 of these bits [i.e. requestor 1 17 and 33 would all set bit 1]" line.long 0x10 "CORE_MMU_REGS_MMU_MEM_REQ" bitfld.long 0x10 31. "INT_PROTOCOL_FAULT,When set indicates the corresponding requestor had a bus protocol fault [excludes MMU requests]" "0,1" newline bitfld.long 0x10 15. "RESERVED_15" "0,1" newline bitfld.long 0x10 14. "EXT_READ_BURST_FAULT,When set indicates the external interface returned a read burst for a tag which didn't contain the expected number of words" "0,1" newline bitfld.long 0x10 13. "EXT_RDRESP_FAULT,When set indicates the external interface returned a read response for a tag which wasn't outstanding [may occur after reset]" "0,1" newline bitfld.long 0x10 12. "EXT_WRRESP_FAULT,When set indicates the external interface returned a write response for a tag which wasn't outstanding [may occur after reset]" "0,1" newline bitfld.long 0x10 10.--11. "RESERVED_10" "0,1,2,3" newline hexmask.long.word 0x10 0.--9. 1. "TAG_OUTSTANDING,Number of outstanding burst requests [TAGS which have been allocated but not yet freed includes reads which have been returned but are still in the read re-order buffer]" line.long 0x14 "CORE_MMU_REGS_MMU_MEM_EXT_OUTSTANDING" hexmask.long.word 0x14 16.--31. 1. "RESERVED_16" newline hexmask.long.word 0x14 0.--15. 1. "READ_WORDS_OUTSTANDING,Number of outstanding read words [in which read commands have been sent to the external interface but the corresponding words haven't been received yet counted in 'external data bus width' words]" group.long 0xA0++0x3 line.long 0x0 "CORE_MMU_REGS_MMU_FAULT_SELECT" hexmask.long 0x0 4.--31. 1. "RESERVED_4" newline hexmask.long.byte 0x0 0.--3. 1. "MMU_FAULT_SELECT,The core can be configured to include protocol checkers on the input requestors this field selects which interface is read from the PROTOCOL_FAULT register [0-15 = requestor 0-15]" rgroup.long 0xA8++0x3 line.long 0x0 "CORE_MMU_REGS_PROTOCOL_FAULT" hexmask.long 0x0 6.--31. 1. "RESERVED_6" newline bitfld.long 0x0 5. "FAULT_READ,For requestor interface indicates a read command on a requestor configured for write only" "0,1" newline bitfld.long 0x0 4. "FAULT_WRITE,For requestor interface indicates a write command on a requestor configured for read only" "0,1" newline bitfld.long 0x0 1.--3. "RESERVED_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "FAULT_PAGE_BREAK,The command crossed a page in the middle of a burst" "0,1" rgroup.long 0x100++0xF line.long 0x0 "CORE_MMU_REGS_TOTAL_READ_REQ,If MMU_CONFIG1.BANDWIDTH_COUNT_SUPPORTED is 0. this register will be fixed at 0." hexmask.long 0x0 0.--31. 1. "TOTAL_READ_REQ,Debug only: Total number of bytes read" line.long 0x4 "CORE_MMU_REGS_TOTAL_WRITE_REQ,If MMU_CONFIG1.BANDWIDTH_COUNT_SUPPORTED is 0. this register will be fixed at 0." hexmask.long 0x4 0.--31. 1. "TOTAL_WRITE_REQ,Debug only: Total number of bytes written" line.long 0x8 "CORE_MMU_REGS_READS_LESS_64_REQ,If MMU_CONFIG1.BANDWIDTH_COUNT_SUPPORTED is 0. this register will be fixed at 0." hexmask.long 0x8 0.--31. 1. "READS_LESS_64_REQ,Debug only: Total number of bytes read using a burst size less than 64 bytes" line.long 0xC "CORE_MMU_REGS_WRITES_LESS_64_REQ,If MMU_CONFIG1.BANDWIDTH_COUNT_SUPPORTED is 0. this register will be fixed at 0." hexmask.long 0xC 0.--31. 1. "WRITES_LESS_64_REQ,Debug only: Total number of bytes written using a burst size less than 64 bytes" rgroup.long 0x120++0x13 line.long 0x0 "CORE_MMU_REGS_EXT_CMD_STALL,If MMU_CONFIG1.STALL_COUNT_SUPPORTED is 0. this register will be fixed at 0." hexmask.long 0x0 0.--31. 1. "EXT_CMD_STALL,Debug only: Number of cycles in which command out of Page Table lookup stalled by external interface" line.long 0x4 "CORE_MMU_REGS_WRITE_REQ_STALL,If MMU_CONFIG1.STALL_COUNT_SUPPORTED is 0. this register will be fixed at 0." hexmask.long 0x4 0.--31. 1. "WRITE_REQ_STALL,Debug only: Number of cycles in which command out of Page Table lookup stalled by write request FIFO" line.long 0x8 "CORE_MMU_REGS_MMU_MISS_STALL,If MMU_CONFIG1.STALL_COUNT_SUPPORTED is 0. this register will be fixed at 0." hexmask.long 0x8 0.--31. 1. "MMU_MISS_STALL,Debug only: Number of cycles in which command is stalled because MMU cache miss buffer is full" line.long 0xC "CORE_MMU_REGS_ADDRESS_STALL,If MMU_CONFIG1.STALL_COUNT_SUPPORTED is 0. this register will be fixed at 0." hexmask.long 0xC 0.--31. 1. "ADDRESS_STALL,Debug only: Number of cycles in which command is stalled because Address coherency buffer is full" line.long 0x10 "CORE_MMU_REGS_TAG_STALL,If MMU_CONFIG1.STALL_COUNT_SUPPORTED is 0. this register will be fixed at 0." hexmask.long 0x10 0.--31. 1. "TAG_STALL,Debug only: Number of cycles in which command is stalled because no free TAGs to allocate" rgroup.long 0x140++0x7 line.long 0x0 "CORE_MMU_REGS_PEAK_READ_OUTSTANDING,If MMU_CONFIG1.LATENCY_COUNT_SUPPORTED is 0. this register will be fixed at 0." hexmask.long.word 0x0 16.--31. 1. "PEAK_READ_LATENCY,Debug only: Peak read latency detected [number of cycles a read tag remains outstanding]" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED_10" newline hexmask.long.word 0x0 0.--9. 1. "PEAK_TAG_OUTSTANDING,Debug only: Largest value on TAG_OUTSTANDING since last initialisation" line.long 0x4 "CORE_MMU_REGS_AVERAGE_READ_LATENCY,If MMU_CONFIG1.LATENCY_COUNT_SUPPORTED is 0. this register will be fixed at 0." hexmask.long 0x4 0.--31. 1. "AVERAGE_READ_LATENCY,Uses an IIR function on read latency where the 16 MSBits are the same resolution as PEAK_READ_LATENCY" group.long 0x160++0x3 line.long 0x0 "CORE_MMU_REGS_STATISTICS_CONTROL" hexmask.long 0x0 3.--31. 1. "RESERVED_3" newline bitfld.long 0x0 2. "LATENCY_STATS_INIT,Writing '1' resets the latency statistics [this bit automatically clears to '0']" "0,1" newline bitfld.long 0x0 1. "STALL_STATS_INIT,Writing '1' resets the stall count statistics [this bit automatically clears to '0']" "0,1" newline bitfld.long 0x0 0. "BANDWIDTH_STATS_INIT,Writing '1' resets the bandwidth statistics [this bit automatically clears to '0']" "0,1" rgroup.long 0x1D0++0x3 line.long 0x0 "CORE_MMU_REGS_MMU_VERSION" hexmask.long.byte 0x0 24.--31. 1. "RESERVED_24" newline hexmask.long.byte 0x0 16.--23. 1. "MMU_MAJOR_REV,MMU Major Revision" newline hexmask.long.byte 0x0 8.--15. 1. "MMU_MINOR_REV,MMU Minor Revision" newline hexmask.long.byte 0x0 0.--7. 1. "MMU_MAINT_REV,MMU Maintenance Revision" tree.end tree "JPGENC_RS_BW_LIMITER4_REGS" base ad:0x30404000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,PID function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" group.long 0x4++0x3 line.long 0x0 "REGS_CTRL,This register controls the overall behavior of the rate limiter module" bitfld.long 0x0 4. "REGION_FILTER_EN,Enable the region filter which will only apply the bandwith and transaction limits to the configured address regions" "0,1" bitfld.long 0x0 3. "WR_TXN_ENABLE,Enable limiting maximum outstanding write transactions" "0,1" bitfld.long 0x0 2. "RD_TXN_ENABLE,Enable limiting maximum outstanding read transactions" "0,1" bitfld.long 0x0 1. "WR_BW_ENABLE,Enable write bandwidth limiting" "0,1" bitfld.long 0x0 0. "RD_BW_ENABLE,Enable read bandwidth limiting" "0,1" group.long 0x100++0xB line.long 0x0 "REGS_RD_BW_CIR,Read Bandwidth Committed Information Rate" hexmask.long 0x0 0.--31. 1. "CIR,Committed Information Rate" line.long 0x4 "REGS_RD_BW_PIR,Read Bandwidth Peak Information Rate" hexmask.long 0x4 0.--31. 1. "PIR,Peak Information Rate" line.long 0x8 "REGS_RD_BW_BURST_OFFSET,Read Bandwidth Burst Offset" hexmask.long.word 0x8 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity. Peak Information Rate will still apply" rgroup.long 0x10C++0x3 line.long 0x0 "REGS_RD_BW_INFO,Read Bandwidth State machine information. Primarly for verification purposes" bitfld.long 0x0 0.--1. "COLOR,Read Bandwidth three-color marker output from rategen submodule" "0,1,2,3" group.long 0x120++0x7 line.long 0x0 "REGS_RD_BW_STATS,Read Bandwidth Statistics Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable read bandwidth statistics" "0,1" line.long 0x4 "REGS_RD_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR" hexmask.long 0x4 0.--31. 1. "THRESHOLD,Read bandwidth stats threshold in bytes. Note that this is total bytes unlike CIR and PIR. CIR and PIR are based on a rolling window and the statistics threshold is based on a fixed window. This will still take into account DDR bytes used so.." rgroup.long 0x128++0x13 line.long 0x0 "REGS_RD_BW_WINDOWS_CNT,Read Bandwidth Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Read bandwidth window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_RD_BW_CIR_CNT,Read Bandwidth Statistics - CIR Count" hexmask.long 0x4 0.--31. 1. "VAL,The total number of statistics windows in which Read Commit Information Rate occurred. Note that if PIR is set to a lower value than CIR or if the burst offset feature is used this will also count times that PIR is reached." line.long 0x8 "REGS_RD_BW_PIR_CNT,Read Bandwidth Statistics - PIR Count" hexmask.long 0x8 0.--31. 1. "VAL,The total number of statistics windows in which Read Peak Information Rate occurred" line.long 0xC "REGS_RD_BW_THRSHLD_CNT,Read Bandwidth Statistics - Threshold Count" hexmask.long 0xC 0.--31. 1. "VAL,The total number of statistics windows in which Read bytes transferred exceeded the statistics threshold" line.long 0x10 "REGS_RD_BYTES_MAX,The maximum number of bytes seen in a single statitsics window. This can be compared with the window size to calculate the maximum bandwidth seen" hexmask.long 0x10 0.--31. 1. "VAL,Max number of bytes in a single window. This number accounts for DDR bandwidth consumed not simply the accumulation of the packet bytecnt values across a window. The max bandwidth calculation is the total bytes value in this MMR divided by the.." group.long 0x300++0x3 line.long 0x0 "REGS_RD_TXN,The maximum number of outstanding read transactions the rate limiter will allow" hexmask.long.word 0x0 0.--15. 1. "LIMIT,The maximum number of outstanding read transactions allowed. NOTE: This cannot be programmed to a zero. If a zero is written it will default to the reset value of 16'd64 as a limit of zero outstanding transactions would hang the interface." rgroup.long 0x30C++0x3 line.long 0x0 "REGS_RD_TXN_INFO,Read Transaction State machine information. Primarly for verification purposes" hexmask.long.byte 0x0 0.--6. 1. "OCC,Read transaction scoreboard occupancy" group.long 0x320++0x7 line.long 0x0 "REGS_RD_TXN_STATS,Read Transaction Stats Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable read transaction statistics" "0,1" line.long 0x4 "REGS_RD_TXN_STATS_THRSHLD,A statistics threshold separate from the read transaction limit" hexmask.long.word 0x4 0.--15. 1. "THRESHOLD,Read transaction statistics threshold. The threshold can be set to any value though it will saturate at the outstanding transaction limit if it is set to a value greater than the programmed outstanding read transaction limit" rgroup.long 0x328++0x17 line.long 0x0 "REGS_RD_TXN_WINDOWS_CNT,Read Transaction Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Read transaction window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_RD_TXN_LMT_CNT,Read Transaction Statistics - number of windows in which the outstanding transaction limit was reached" hexmask.long 0x4 0.--31. 1. "VAL,The number of statistics windows in which the outstanding read transaction limit was reached" line.long 0x8 "REGS_RD_TXN_THRSHLD_CNT,Read Transaction Statistics - number of windows in which the statistics threshold was reached" hexmask.long 0x8 0.--31. 1. "VAL,The number of statistics windows in which the number of outstanding read transactions was greater than or equal to the threshold in RD_TXN_STATS_THRSHLD" line.long 0xC "REGS_RD_TXN_LIMIT_TOTAL,Read Transaction Statistics - Cycles at Outstanding Read Transactions Limit" hexmask.long 0xC 0.--31. 1. "VAL,The total number of cycles with the read transactions outstanding at the programmed limit since statistics collection began" line.long 0x10 "REGS_RD_TXN_THRSHLD_TOTAL,Read Transaction Statistics - Cycles at the Statistics Threshold" hexmask.long 0x10 0.--31. 1. "VAL,The total number of cycles with read transactions outstanding greater than or equal to the statistics threshold in RD_TXN_STATS_THRSHLD since statistics collection began" line.long 0x14 "REGS_RD_TXN_MAX,Read Transaction Statistics - Max Observed Outstanding Read Transactions" hexmask.long.word 0x14 0.--15. 1. "VAL,The maximum outstanding read transactions at any point in time regardless of the programmed limit" tree.end tree "JPGENC_WS_BW_LIMITER5_REGS" base ad:0x30405000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,PID function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" group.long 0x4++0x3 line.long 0x0 "REGS_CTRL,This register controls the overall behavior of the rate limiter module" bitfld.long 0x0 4. "REGION_FILTER_EN,Enable the region filter which will only apply the bandwith and transaction limits to the configured address regions" "0,1" bitfld.long 0x0 3. "WR_TXN_ENABLE,Enable limiting maximum outstanding write transactions" "0,1" bitfld.long 0x0 2. "RD_TXN_ENABLE,Enable limiting maximum outstanding read transactions" "0,1" bitfld.long 0x0 1. "WR_BW_ENABLE,Enable write bandwidth limiting" "0,1" bitfld.long 0x0 0. "RD_BW_ENABLE,Enable read bandwidth limiting" "0,1" group.long 0x200++0xB line.long 0x0 "REGS_WR_BW_CIR,Write Bandwidth Committed Information Rate" hexmask.long 0x0 0.--31. 1. "CIR,Committed Information Rate" line.long 0x4 "REGS_WR_BW_PIR,Write Bandwidth Peak Information Rate" hexmask.long 0x4 0.--31. 1. "PIR,Peak Information Rate" line.long 0x8 "REGS_WR_BW_BURST_OFFSET,Write Bandwidth Burst Offset" hexmask.long.word 0x8 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity. Peak Information Rate will still apply" rgroup.long 0x20C++0x3 line.long 0x0 "REGS_WR_BW_INFO,Write Bandwidth State machine information. Primarly for verification purposes" bitfld.long 0x0 0.--1. "COLOR,Write Bandwidth three-color marker output from rategen submodule" "0,1,2,3" group.long 0x220++0x7 line.long 0x0 "REGS_WR_BW_STATS,Write Bandwidth Statistics Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable write bandwidth statistics" "0,1" line.long 0x4 "REGS_WR_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR" hexmask.long 0x4 0.--31. 1. "THRESHOLD,Write bandwidth stats threshold in bytes. Note that this is total bytes unlike CIR and PIR. CIR and PIR are based on a rolling window and the statistics threshold is based on a fixed window. This will still take into account DDR bytes used .." rgroup.long 0x228++0x13 line.long 0x0 "REGS_WR_BW_WINDOWS_CNT,Write Bandwidth Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Write bandwidth window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_WR_BW_CIR_CNT,Write Bandwidth Statistics - CIR Count" hexmask.long 0x4 0.--31. 1. "VAL,The total number of statistics windows in which Write Commit Information Rate occurred. Note that if PIR is set to a lower value than CIR or if the burst offset feature is used this will also count times that PIR is reached." line.long 0x8 "REGS_WR_BW_PIR_CNT,Write Bandwidth Statistics - PIR Count" hexmask.long 0x8 0.--31. 1. "VAL,The total number of statistics windows in which Write Peak Information Rate occurred" line.long 0xC "REGS_WR_BW_THRSHLD_CNT,Write Bandwidth Statistics - Threshold Count" hexmask.long 0xC 0.--31. 1. "VAL,The total number of statistics windows in which Write bytes transferred exceeded the statistics threshold" line.long 0x10 "REGS_WR_BYTES_MAX,The maximum number of bytes seen in a single statitsics window. This can be compared with the window size to calculate the maximum bandwidth seen" hexmask.long 0x10 0.--31. 1. "VAL,Max number of bytes in a single window. This number accounts for DDR bandwidth consumed not simply the accumulation of the packet bytecnt values across a window. The max bandwidth calculation is the total bytes value in this MMR divided by the.." group.long 0x400++0x3 line.long 0x0 "REGS_WR_TXN,The maximum number of outstanding write transactions the rate limiter will allow" hexmask.long.word 0x0 0.--15. 1. "LIMIT,The maximum number of outstanding write transactions allowed. NOTE: This cannot be programmed to a zero. If a zero is written it will default to the reset value of 16'd64 as a limit of zero outstanding transactions would hang the interface." rgroup.long 0x40C++0x3 line.long 0x0 "REGS_WR_TXN_INFO,Write Transaction State machine information. Primarly for verification purposes" hexmask.long.byte 0x0 0.--6. 1. "OCC,Write transaction scoreboard occupancy" group.long 0x420++0x7 line.long 0x0 "REGS_WR_TXN_STATS,Write Transaction Stats Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable write transaction statistics" "0,1" line.long 0x4 "REGS_WR_TXN_STATS_THRSHLD,A statistics threshold separate from the write transaction limit" hexmask.long.word 0x4 0.--15. 1. "THRESHOLD,Write transaction statistics threshold. The threshold can be set to any value though it will saturate at the outstanding transaction limit if it is set to a value greater than the programmed outstanding write transaction limit" rgroup.long 0x428++0x17 line.long 0x0 "REGS_WR_TXN_WINDOWS_CNT,Write Transaction Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Write transaction window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_WR_TXN_LMT_CNT,Write Transaction Statistics - number of windows in which the outstanding transaction limit was reached" hexmask.long 0x4 0.--31. 1. "VAL,The number of statistics windows in which the outstanding write transaction limit was reached" line.long 0x8 "REGS_WR_TXN_THRSHLD_CNT,Write Transaction Statistics - number of windows in which the statistics threshold was reached" hexmask.long 0x8 0.--31. 1. "VAL,The number of statistics windows in which the number of outstanding write transactions was greater than or equal to the threshold in WR_TXN_STATS_THRSHLD" line.long 0xC "REGS_WR_TXN_LIMIT_TOTAL,Write Transaction Statistics - Cycles at Outstanding Write Transactions Limit" hexmask.long 0xC 0.--31. 1. "VAL,The total number of cycles with the write transactions outstanding at the programmed limit since statistics collection began" line.long 0x10 "REGS_WR_TXN_THRSHLD_TOTAL,Write Transaction Statistics - Cycles at the Statistics Threshold" hexmask.long 0x10 0.--31. 1. "VAL,The total number of cycles with write transactions outstanding greater than or equal to the statistics threshold in WR_TXN_STATS_THRSHLD since statistics collection began" line.long 0x14 "REGS_WR_TXN_MAX,Write Transaction Statistics - Max Observed Outstanding Write Transactions" hexmask.long.word 0x14 0.--15. 1. "VAL,The maximum outstanding write transactions at any point in time regardless of the programmed limit" tree.end tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "MAILBOX0_MAILBOX_CLUSTER" base ad:0x0 tree "MAILBOX0_MAILBOX_CLUSTER_0_REGS0" base ad:0x29000000 rgroup.long 0x0++0x3 line.long 0x0 "REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" wgroup.long 0x140++0x3 line.long 0x0 "REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" group.long 0x100++0xF line.long 0x0 "REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end tree "MAILBOX0_MAILBOX_CLUSTER_1_REGS1" base ad:0x29010000 rgroup.long 0x0++0x3 line.long 0x0 "REGS1_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "REGS1_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "REGS1_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "REGS1_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS1_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" wgroup.long 0x140++0x3 line.long 0x0 "REGS1_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" group.long 0x100++0xF line.long 0x0 "REGS1_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "REGS1_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "REGS1_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "REGS1_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end tree "MAILBOX0_MAILBOX_CLUSTER_2_REGS2" base ad:0x29020000 rgroup.long 0x0++0x3 line.long 0x0 "REGS2_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "REGS2_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "REGS2_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "REGS2_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS2_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" wgroup.long 0x140++0x3 line.long 0x0 "REGS2_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" group.long 0x100++0xF line.long 0x0 "REGS2_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "REGS2_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "REGS2_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "REGS2_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end tree "MAILBOX0_MAILBOX_CLUSTER_3_REGS3" base ad:0x29030000 rgroup.long 0x0++0x3 line.long 0x0 "REGS3_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "REGS3_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system. Provided for backwards compatibility with OMAP Mailbox. Only contains the soft reset." bitfld.long 0x0 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0. It has the same effect as the hardware reset. Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and empty all the.." "0,1" group.long 0x40++0x3 line.long 0x0 "REGS3_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox." hexmask.long 0x0 0.--31. 1. "MESSAGE_VALUE,Message in Mailbox [a]" rgroup.long 0x80++0x3 line.long 0x0 "REGS3_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO" bitfld.long 0x0 0. "FIFO_FULL,Full flag for Mailbox m" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "REGS3_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]" bitfld.long 0x0 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7" wgroup.long 0x140++0x3 line.long 0x0 "REGS3_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance." bitfld.long 0x0 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1" bitfld.long 0x0 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1" bitfld.long 0x0 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1" bitfld.long 0x0 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1" group.long 0x100++0xF line.long 0x0 "REGS3_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user ." bitfld.long 0x0 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1" bitfld.long 0x0 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1" bitfld.long 0x0 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1" bitfld.long 0x0 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1" newline bitfld.long 0x0 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1" bitfld.long 0x0 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1" bitfld.long 0x0 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1" bitfld.long 0x0 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1" newline bitfld.long 0x0 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1" bitfld.long 0x0 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1" bitfld.long 0x0 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1" bitfld.long 0x0 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1" newline bitfld.long 0x0 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1" bitfld.long 0x0 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1" bitfld.long 0x0 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1" bitfld.long 0x0 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1" newline bitfld.long 0x0 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1" bitfld.long 0x0 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1" bitfld.long 0x0 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1" bitfld.long 0x0 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1" newline bitfld.long 0x0 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1" bitfld.long 0x0 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1" bitfld.long 0x0 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1" bitfld.long 0x0 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1" newline bitfld.long 0x0 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1" bitfld.long 0x0 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1" bitfld.long 0x0 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1" bitfld.long 0x0 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1" newline bitfld.long 0x0 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1" bitfld.long 0x0 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1" bitfld.long 0x0 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1" bitfld.long 0x0 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1" line.long 0x4 "REGS3_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information." bitfld.long 0x4 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1" newline bitfld.long 0x4 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1" bitfld.long 0x4 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1" bitfld.long 0x4 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1" line.long 0x8 "REGS3_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0x8 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0x8 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0x8 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 enables the interrupt. Write 0 does nothing." "0,1" line.long 0xC "REGS3_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a]." bitfld.long 0xC 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" newline bitfld.long 0xC 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" bitfld.long 0xC 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt. Write 1 disables the interrupt. Write 0 does nothing." "0,1" tree.end tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "MAIN" base ad:0x0 tree "MAIN_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG" base ad:0xA00000 rgroup.long 0x0++0x3 line.long 0x0 "INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.byte 0x0 0.--7. 1. "MUX_CNTL,Mux control for interrupt N" tree.end tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "MCAN0" base ad:0x0 tree "MCAN0_CFG" base ad:0x20701000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" group.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" group.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" group.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCAN0_ECC_AGGR" base ad:0x24018000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" group.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCAN0_MSGMEM_RAM" base ad:0x20708000 group.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCAN0_SS" base ad:0x20700000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" group.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" group.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "MCASP" base ad:0x0 tree "MCASP0_CFG" base ad:0x2B00000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_PID,The revision identification register (PID) contains identification data for the peripheral." hexmask.long 0x0 0.--31. 1. "REV,Identifies revision of peripheral." group.long 0x4++0x3 line.long 0x0 "CFG_PWRIDLESYSCONFIG" hexmask.long 0x0 6.--31. 1. "RESERVED66" hexmask.long.byte 0x0 2.--5. 1. "OTHER,Reserved for future programming." bitfld.long 0x0 0.--1. "IDLEMODE,Power management Configuration of the local target state management mode. By definition target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" group.long 0x10++0x13 line.long 0x0 "CFG_PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin. CAUTION: Writing a value other than 0 to reserved bits in.." bitfld.long 0x0 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO." "0,1" newline bitfld.long 0x0 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO." "0,1" hexmask.long.tbyte 0x0 4.--24. 1. "RESERVED67" hexmask.long.byte 0x0 0.--3. 1. "AXR,Determines if AXRn pin functions as McASP or GPIO." line.long 0x4 "CFG_PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin. Regardless of the pin function register (PFUNC) setting. each PDIR bit must be set to 1 for.." bitfld.long 0x4 31. "AFSR,Determines if AFSR pin functions as an input or output." "0,1" bitfld.long 0x4 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output." "0,1" bitfld.long 0x4 29. "ACLKR,Determines if ACLKR pin functions as an input or output." "0,1" bitfld.long 0x4 28. "AFSX,Determines if AFSX pin functions as an input or output." "0,1" bitfld.long 0x4 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output." "0,1" bitfld.long 0x4 26. "ACLKX,Determines if ACLKX pin functions as an input or output." "0,1" newline bitfld.long 0x4 25. "AMUTE,Determines if AMUTE pin functions as an input or output." "0,1" hexmask.long.tbyte 0x4 4.--24. 1. "RESERVED68" hexmask.long.byte 0x4 0.--3. 1. "AXR,Determines if AXRn pin functions as an input or output." line.long 0x8 "CFG_PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times. The value held by PDOUT is not affected by writing to PDIR and PFUNC. However. the data value in PDOUT is driven out onto the McASP.." bitfld.long 0x8 31. "AFSR,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1." "0,1" bitfld.long 0x8 30. "AHCLKR,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1." "0,1" bitfld.long 0x8 29. "ACLKR,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1." "0,1" bitfld.long 0x8 28. "AFSX,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1." "0,1" bitfld.long 0x8 27. "AHCLKX,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1." "0,1" bitfld.long 0x8 26. "ACLKX,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1." "0,1" newline bitfld.long 0x8 25. "AMUTE,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1." "0,1" hexmask.long.tbyte 0x8 4.--24. 1. "RESERVED69" hexmask.long.byte 0x8 0.--3. 1. "AXR,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1." line.long 0xC "CFG_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read. regardless of the state of PFUNC and PDIR. The value after reset for registers 1 through 15 and 24 through.." bitfld.long 0xC 31. "AFSR,Logic level on AFSR pin." "0,1" bitfld.long 0xC 30. "AHCLKR,Logic level on AHCLKR pin." "0,1" bitfld.long 0xC 29. "ACLKR,Logic level on ACLKR pin." "0,1" bitfld.long 0xC 28. "AFSX,Logic level on AFSX pin." "0,1" bitfld.long 0xC 27. "AHCLKX,Logic level on AHCLKX pin." "0,1" bitfld.long 0xC 26. "ACLKX,Logic level on ACLKX pin." "0,1" newline bitfld.long 0xC 25. "AMUTE,Logic level on AMUTE pin." "0,1" hexmask.long.tbyte 0xC 4.--24. 1. "RESERVED70" hexmask.long.byte 0xC 0.--3. 1. "AXR,Logic level on AXR[n] pin." line.long 0x10 "CFG_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and. if PFUNC = 1 (GPIO function) and PDIR = 1 (output). drives a logic.." bitfld.long 0x10 31. "AFSR,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 30. "AHCLKR,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 29. "ACLKR,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 28. "AFSX,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 27. "AHCLKX,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 26. "ACLKX,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" newline bitfld.long 0x10 25. "AMUTE,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" hexmask.long.tbyte 0x10 4.--24. 1. "RESERVED71" hexmask.long.byte 0x10 0.--3. 1. "AXR,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." group.long 0x44++0xF line.long 0x0 "CFG_GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections. The bit fields in GBLCTL are synchronized and latched by the corresponding clocks (ACLKX for bits 12-8 and ACLKR for bits 4-0). Before GBLCTL is.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED73" bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. By clearing then setting this bit the transmit buffer is flushed to an empty state [XDATA = 1]. If XSMRST = 1 XSRCLR = 1 XDATA = 1 and XBUF is not loaded with new data before the start of the next active.." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED72" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. By clearing then setting this bit the receive buffer is flushed." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" line.long 0x4 "CFG_AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin. The value after reset for register 4 depends on how the pins are being driven." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED74" bitfld.long 0x4 12. "XDMAERR,If transmit DMA error [XDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 11. "RDMAERR,If receive DMA error [RDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 10. "XCKFAIL,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 9. "RCKFAIL,If receive clock failure [RCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 8. "XSYNCERR,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit." "0,1" newline bitfld.long 0x4 7. "RSYNCERR,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 6. "XUNDRN,If transmit underrun error [XUNDRN] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 5. "ROVRN,If receiver overrun error [ROVRN] drive AMUTE active enable bit." "0,1" rbitfld.long 0x4 4. "INSTAT,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1." "0,1" bitfld.long 0x4 3. "INEN,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]." "0,1" bitfld.long 0x4 2. "INPOL,Audio mute in [AMUTEIN] polarity select bit." "0,1" newline bitfld.long 0x4 0.--1. "MUTEN,AMUTE pin enable bit [unless overridden by GPIO registers]." "0,1,2,3" line.long 0x8 "CFG_DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode." hexmask.long 0x8 4.--31. 1. "RESERVED75" bitfld.long 0x8 2.--3. "MODE,Loopback generator mode bits. Applies only when loopback mode is enabled [DLBEN = 1]." "0,1,2,3" bitfld.long 0x8 1. "ORD,Loopback order bit when loopback mode is enabled [DLBEN = 1]." "0,1" bitfld.long 0x8 0. "DLBEN,Loopback mode enable bit." "0,1" line.long 0xC "CFG_DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP." hexmask.long 0xC 4.--31. 1. "RESERVED77" bitfld.long 0xC 3. "VB,Valid bit for odd time slots [DIT right subframe]." "0,1" bitfld.long 0xC 2. "VA,Valid bit for even time slots [DIT left subframe]." "0,1" rbitfld.long 0xC 1. "RESERVED76" "0,1" bitfld.long 0xC 0. "DITEN,DIT mode enable bit. DITEN should only be changed while the XSMRST bit in GBLCTL is in reset [and for startup XSRCLR also in reset]. However it is not necessary to reset the XCLKRST or XHCLKRST bits in GBLCTL to change DITEN." "0,1" group.long 0x60++0x23 line.long 0x0 "CFG_RGBLCTL,Alias of the global control register (GBLCTL). Writing to the receiver global control register (RGBLCTL) affects only the receive bits of GBLCTL (bits 4-0). Reads from RGBLCTL return the value of GBLCTL. RGBLCTL allows the receiver to be.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED79" rbitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A read of this bit returns the XFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A read of this bit returns the XSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A read of this bit returns the XSRCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A read of this bit returns the XHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A read of this bit returns the XCLKRST bit value of GBLCTL. Writes have no effect." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED78" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A write to this bit affects the RFRST bit of GBLCTL." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A write to this bit affects the RSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A write to this bit affects the RSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A write to this bit affects the RHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A write to this bit affects the RCLKRST bit of GBLCTL." "0,1" line.long 0x4 "CFG_RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA." hexmask.long 0x4 0.--31. 1. "RMASK,Receive data mask n enable bit." line.long 0x8 "CFG_RFMT,The receive bit stream format register (RFMT) configures the receive data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED80" bitfld.long 0x8 16.--17. "RDATDLY,Receive bit delay." "0,1,2,3" bitfld.long 0x8 15. "RRVRS,Receive serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "RPBIT,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits. This field only applies when RPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "RSSZ,Receive slot size." newline bitfld.long 0x8 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "RROT,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)." hexmask.long.word 0xC 16.--31. 1. "RESERVED83" hexmask.long.word 0xC 7.--15. 1. "RMOD,Receive frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED82" "0,1,2,3" bitfld.long 0xC 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED81" "0,1,2,3" bitfld.long 0xC 1. "FSRM,Receive frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSRP,Receive frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED86" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED85" newline bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit." "0,1" rbitfld.long 0x10 6. "RESERVED84" "0,1" bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." line.long 0x14 "CFG_AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED88" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKRM,Receive high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED87" "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR." line.long 0x18 "CFG_RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active." hexmask.long 0x18 0.--31. 1. "RTDMS,Receiver mode during TDM time slot n." line.long 0x1C "CFG_RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates RINT. See the RSTAT register for a.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED90" bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED89" "0,1" bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit." "0,1" line.long 0x20 "CFG_RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has priority.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED91" bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR. Allows a single bit to be checked to determine if a receiver error interrupt has occurred." "0,1" bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the data port in a given time slot than were programmed as receivers. Causes a receive interrupt [RINT] if this bit is set and RDMAERR in RINTCTL is set." "0,1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag. Causes a receive interrupt [RINT] if this bit is set and RSTAFRM in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 5. "RDATA,Receive data ready flag. Causes a receive interrupt [RINT] if this bit is set and RDATA in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 4. "RLAST,Receive last slot flag. RLAST is set along with RDATA if the current slot is the last slot in a frame. Causes a receive interrupt [RINT] if this bit is set and RLAST in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT. Allows a single read of RSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. Causes a receive interrupt [RINT] if this bit is set and RCKFAIL in RINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync [AFSR] occurs before it is expected. Causes a receive interrupt [RINT] if this bit is set and RSYNCERR in RINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF but the former data in RBUF has not yet been read by the CPU or DMA. Causes a receive interrupt [RINT] if this bit is set and ROVRN.." "0,1" rgroup.long 0x84++0x3 line.long 0x0 "CFG_RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED92" hexmask.long.word 0x0 0.--8. 1. "RSLOTCNT,0-17Fh = Current receive time slot count. Legal values: 0 to 383 [17Fh]. TDM function is not supported for > 32 time slots. However TDM time slot counter may count to 383 when used to receive a DIR block [transferred over TDM format]." group.long 0x88++0x7 line.long 0x0 "CFG_RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "RCNT,Receive clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 receive high-frequency master clock [AHCLKR] signals and stores the count in RCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "RMAX,Receive clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "RMIN,Receive clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If RCNT is less than RMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED93" hexmask.long.byte 0x0 0.--3. 1. "RPS,Receive clock check prescaler value." line.long 0x4 "CFG_PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event. Note for device-specific registers: Accessing PIDTCTL not implemented on a specific device may cause improper operation." hexmask.long 0x4 1.--31. 1. "RESERVED94" bitfld.long 0x4 0. "RDATDMA,Receive data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" group.long 0xA0++0x23 line.long 0x0 "CFG_XGBLCTL,Alias of the global control register (GBLCTL). Writing to the transmitter global control register (XGBLCTL) affects only the transmit bits of GBLCTL (bits 12-8). Reads from XGBLCTL return the value of GBLCTL. XGBLCTL allows the transmitter to.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED96" bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A write to this bit affects the XFRST bit of GBLCTL." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A write to this bit affects the XSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A write to this bit affects the XSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A write to this bit affects the XHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A write to this bit affects the XCLKRST bit of GBLCTL." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED95" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A read of this bit returns the RFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A read of this bit returns the RSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A read of this bit returns the RSRSCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A read of this bit returns the RHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of GBLCTL. Writes have no effect." "0,1" line.long 0x4 "CFG_XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP." hexmask.long 0x4 0.--31. 1. "XMASK,Transmit data mask n enable bit." line.long 0x8 "CFG_XFMT,The transmit bit stream format register (XFMT) configures the transmit data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED97" bitfld.long 0x8 16.--17. "XDATDLY,Transmit sync bit delay." "0,1,2,3" bitfld.long 0x8 15. "XRVRS,Transmit serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "XPBIT,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting. This field only applies when XPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "XSSZ,Transmit slot size." newline bitfld.long 0x8 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "XROT,Right-rotation value for transmit rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)." hexmask.long.word 0xC 16.--31. 1. "RESERVED100" hexmask.long.word 0xC 7.--15. 1. "XMOD,Transmit frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED99" "0,1,2,3" bitfld.long 0xC 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED98" "0,1,2,3" bitfld.long 0xC 1. "FSXM,Transmit frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSXP,Transmit frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED102" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED101" newline bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit." "0,1" bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit." "0,1" bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX." line.long 0x14 "CFG_AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED104" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED103" "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX." line.long 0x18 "CFG_XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active. TDM time slot counter range is extended to 384 slots (to support SPDIF blocks of 384 subframes). XTDM operates modulo 32. that is. XTDMS.." hexmask.long 0x18 0.--31. 1. "XTDMS,Transmitter mode during TDM time slot n." line.long 0x1C "CFG_XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates XINT. See the XSTAT register for.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED106" bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED105" "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit." "0,1" line.long 0x20 "CFG_XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED107" bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more serializers through the data port in a given time slot than were programmed as transmitters. Causes a transmit interrupt [XINT] if this bit is set and XDMAERR in XINTCTL is.." "0,1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag. Causes a transmit interrupt [XINT] if this bit is set and XSTAFRM in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 5. "XDATA,Transmit data ready flag. Causes a transmit interrupt [XINT] if this bit is set and XDATA in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag. XLAST is set along with XDATA if the current slot is the last slot in a frame. Causes a transmit interrupt [XINT] if this bit is set and XLAST in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt [XINT] if this bit is set and XCKFAIL in XINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag. XSYNCERR is set when a new transmit frame sync [AFSX] occurs before it is expected. Causes a transmit interrupt [XINT] if this bit is set and XSYNCERR in XINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF to XRSR but XBUF has not yet been serviced with new data since the last transfer. Causes a transmit interrupt [XINT] if this bit is.." "0,1" rgroup.long 0xC4++0x3 line.long 0x0 "CFG_XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED108" hexmask.long.word 0x0 0.--9. 1. "XSLOTCNT,Current transmit time slot count. Legal values: 0 to 383 [17Fh]. During reset this counter value is 383 so the next count value which is used to encode the first DIT group of data will be 0 and encodes the B preamble. TDM function is not.." group.long 0xC8++0x7 line.long 0x0 "CFG_XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "XCNT,Transmit clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 transmit high-frequency master clock [AHCLKX] signals and stores the count in XCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "XMAX,Transmit clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "XMIN,Transmit clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If XCNT is less than XMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED109" hexmask.long.byte 0x0 0.--3. 1. "XPS,Transmit clock check prescaler value. Fh = Reserved from 9h to Fh." line.long 0x4 "CFG_XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event. Note for device-specific registers: Accessing XEVTCTL not implemented on a specific device may cause improper device operation." hexmask.long 0x4 1.--31. 1. "RESERVED110" bitfld.long 0x4 0. "XDATDMA,Transmit data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" group.long 0x100++0x5F line.long 0x0 "CFG_DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x0 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x4 "CFG_DITCSRA1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x8 "CFG_DITCSRA2,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x8 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0xC "CFG_DITCSRA3,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0xC 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x10 "CFG_DITCSRA4,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x10 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x14 "CFG_DITCSRA5,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x14 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x18 "CFG_DITCSRB0,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x18 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x1C "CFG_DITCSRB1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x1C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x20 "CFG_DITCSRB2,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x20 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x24 "CFG_DITCSRB3,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x24 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x28 "CFG_DITCSRB4,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x28 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x2C "CFG_DITCSRB5,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x2C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x30 "CFG_DITUDRA0,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x30 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x34 "CFG_DITUDRA1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x34 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x38 "CFG_DITUDRA2,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x38 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x3C "CFG_DITUDRA3,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x3C 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x40 "CFG_DITUDRA4,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x40 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x44 "CFG_DITUDRA5,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x44 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x48 "CFG_DITUDRB0,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x48 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x4C "CFG_DITUDRB1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4C 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x50 "CFG_DITUDRB2,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x50 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x54 "CFG_DITUDRB3,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x54 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x58 "CFG_DITUDRB4,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x58 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x5C "CFG_DITUDRB5,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x5C 0.--31. 1. "DITUDRB,DIT right channel user data registers." group.long 0x180++0x3F line.long 0x0 "CFG_SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x0 6.--31. 1. "RESERVED111" rbitfld.long 0x0 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x0 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x0 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x0 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x4 "CFG_SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x4 6.--31. 1. "RESERVED112" rbitfld.long 0x4 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x4 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x4 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x4 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x8 "CFG_SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x8 6.--31. 1. "RESERVED113" rbitfld.long 0x8 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x8 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x8 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x8 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0xC "CFG_SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0xC 6.--31. 1. "RESERVED114" rbitfld.long 0xC 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0xC 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0xC 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0xC 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x10 "CFG_SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x10 6.--31. 1. "RESERVED115" rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x14 "CFG_SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x14 6.--31. 1. "RESERVED116" rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x18 "CFG_SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x18 6.--31. 1. "RESERVED117" rbitfld.long 0x18 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x18 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x18 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x18 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x1C "CFG_SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x1C 6.--31. 1. "RESERVED118" rbitfld.long 0x1C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x1C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x1C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x1C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x20 "CFG_SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x20 6.--31. 1. "RESERVED119" rbitfld.long 0x20 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x20 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x20 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x20 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x24 "CFG_SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x24 6.--31. 1. "RESERVED120" rbitfld.long 0x24 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x24 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x24 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x24 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x28 "CFG_SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x28 6.--31. 1. "RESERVED121" rbitfld.long 0x28 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x28 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x28 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x28 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x2C "CFG_SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x2C 6.--31. 1. "RESERVED122" rbitfld.long 0x2C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x2C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x2C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x2C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x30 "CFG_SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x30 6.--31. 1. "RESERVED123" rbitfld.long 0x30 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x30 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x30 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x30 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x34 "CFG_SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x34 6.--31. 1. "RESERVED124" rbitfld.long 0x34 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x34 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x34 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x34 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x38 "CFG_SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x38 6.--31. 1. "RESERVED125" rbitfld.long 0x38 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x38 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x38 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x38 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x3C "CFG_SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x3C 6.--31. 1. "RESERVED126" rbitfld.long 0x3C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x3C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x3C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x3C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" group.long 0x200++0x3F line.long 0x0 "CFG_XBUF0,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x0 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x4 "CFG_XBUF1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x4 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x8 "CFG_XBUF2,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x8 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0xC "CFG_XBUF3,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0xC 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x10 "CFG_XBUF4,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x10 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x14 "CFG_XBUF5,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x14 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x18 "CFG_XBUF6,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x18 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x1C "CFG_XBUF7,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x1C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x20 "CFG_XBUF8,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x20 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x24 "CFG_XBUF9,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x24 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x28 "CFG_XBUF10,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x28 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x2C "CFG_XBUF11,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x2C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x30 "CFG_XBUF12,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x30 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x34 "CFG_XBUF13,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x34 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x38 "CFG_XBUF14,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x38 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x3C "CFG_XBUF15,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x3C 0.--31. 1. "XBUF,Transmit buffers for serializers." group.long 0x280++0x3F line.long 0x0 "CFG_RBUF0,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x0 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x4 "CFG_RBUF1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x4 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x8 "CFG_RBUF2,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x8 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0xC "CFG_RBUF3,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0xC 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x10 "CFG_RBUF4,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x10 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x14 "CFG_RBUF5,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x14 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x18 "CFG_RBUF6,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x18 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x1C "CFG_RBUF7,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x1C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x20 "CFG_RBUF8,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x20 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x24 "CFG_RBUF9,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x24 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x28 "CFG_RBUF10,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x28 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x2C "CFG_RBUF11,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x2C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x30 "CFG_RBUF12,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x30 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x34 "CFG_RBUF13,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x34 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x38 "CFG_RBUF14,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x38 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x3C "CFG_RBUF15,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x3C 0.--31. 1. "RBUF,Receive buffers for serializers." group.long 0x1000++0x3 line.long 0x0 "CFG_WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED127" bitfld.long 0x0 16. "WENA,Write FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "WNUMEVT,Write word count per DMA event [32 bit]. When the Write FIFO has space for at least WNUMEVT words of data then an AXEVT [transmit DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the.." hexmask.long.byte 0x0 0.--7. 1. "WNUMDMA,Write word count per transfer [32 bit words]. Upon a transmit DMA event from the McASP WNUMDMA words are transferred from the Write FIFO to the McASP. This value must equal the number of McASP serializers used as transmitters. This value must be.." rgroup.long 0x1004++0x3 line.long 0x0 "CFG_WFIFOSTS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED128" hexmask.long.byte 0x0 0.--7. 1. "WLVL,Write level [read-only]. Number of 32 bit words currently in the Write FIFO. 40h = 3 to 64 words currently in Write FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." group.long 0x1008++0x3 line.long 0x0 "CFG_RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED129" bitfld.long 0x0 16. "RENA,Read FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "RNUMEVT,Read word count per DMA event [32 bit]. When the Read FIFO contains at least RNUMEVT words of data then an AREVT [receive DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the number.." hexmask.long.byte 0x0 0.--7. 1. "RNUMDMA,Read word count per transfer [32 bit words]. Upon a receive DMA event from the McASP the Read FIFO reads RNUMDMA words from the McASP. This value must equal the number of McASP serializers used as receivers. This value must be set prior to.." rgroup.long 0x100C++0x3 line.long 0x0 "CFG_RFIFOSTS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED130" hexmask.long.byte 0x0 0.--7. 1. "RLVL,Read level [read-only]. Number of 32 bit words currently in the Read FIFO. 40h = 3 to 64 words currently in Read FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." tree.end tree "MCASP1_CFG" base ad:0x2B10000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_PID,The revision identification register (PID) contains identification data for the peripheral." hexmask.long 0x0 0.--31. 1. "REV,Identifies revision of peripheral." group.long 0x4++0x3 line.long 0x0 "CFG_PWRIDLESYSCONFIG" hexmask.long 0x0 6.--31. 1. "RESERVED66" hexmask.long.byte 0x0 2.--5. 1. "OTHER,Reserved for future programming." bitfld.long 0x0 0.--1. "IDLEMODE,Power management Configuration of the local target state management mode. By definition target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" group.long 0x10++0x13 line.long 0x0 "CFG_PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin. CAUTION: Writing a value other than 0 to reserved bits in.." bitfld.long 0x0 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO." "0,1" newline bitfld.long 0x0 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO." "0,1" hexmask.long.tbyte 0x0 4.--24. 1. "RESERVED67" hexmask.long.byte 0x0 0.--3. 1. "AXR,Determines if AXRn pin functions as McASP or GPIO." line.long 0x4 "CFG_PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin. Regardless of the pin function register (PFUNC) setting. each PDIR bit must be set to 1 for.." bitfld.long 0x4 31. "AFSR,Determines if AFSR pin functions as an input or output." "0,1" bitfld.long 0x4 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output." "0,1" bitfld.long 0x4 29. "ACLKR,Determines if ACLKR pin functions as an input or output." "0,1" bitfld.long 0x4 28. "AFSX,Determines if AFSX pin functions as an input or output." "0,1" bitfld.long 0x4 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output." "0,1" bitfld.long 0x4 26. "ACLKX,Determines if ACLKX pin functions as an input or output." "0,1" newline bitfld.long 0x4 25. "AMUTE,Determines if AMUTE pin functions as an input or output." "0,1" hexmask.long.tbyte 0x4 4.--24. 1. "RESERVED68" hexmask.long.byte 0x4 0.--3. 1. "AXR,Determines if AXRn pin functions as an input or output." line.long 0x8 "CFG_PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times. The value held by PDOUT is not affected by writing to PDIR and PFUNC. However. the data value in PDOUT is driven out onto the McASP.." bitfld.long 0x8 31. "AFSR,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1." "0,1" bitfld.long 0x8 30. "AHCLKR,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1." "0,1" bitfld.long 0x8 29. "ACLKR,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1." "0,1" bitfld.long 0x8 28. "AFSX,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1." "0,1" bitfld.long 0x8 27. "AHCLKX,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1." "0,1" bitfld.long 0x8 26. "ACLKX,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1." "0,1" newline bitfld.long 0x8 25. "AMUTE,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1." "0,1" hexmask.long.tbyte 0x8 4.--24. 1. "RESERVED69" hexmask.long.byte 0x8 0.--3. 1. "AXR,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1." line.long 0xC "CFG_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read. regardless of the state of PFUNC and PDIR. The value after reset for registers 1 through 15 and 24 through.." bitfld.long 0xC 31. "AFSR,Logic level on AFSR pin." "0,1" bitfld.long 0xC 30. "AHCLKR,Logic level on AHCLKR pin." "0,1" bitfld.long 0xC 29. "ACLKR,Logic level on ACLKR pin." "0,1" bitfld.long 0xC 28. "AFSX,Logic level on AFSX pin." "0,1" bitfld.long 0xC 27. "AHCLKX,Logic level on AHCLKX pin." "0,1" bitfld.long 0xC 26. "ACLKX,Logic level on ACLKX pin." "0,1" newline bitfld.long 0xC 25. "AMUTE,Logic level on AMUTE pin." "0,1" hexmask.long.tbyte 0xC 4.--24. 1. "RESERVED70" hexmask.long.byte 0xC 0.--3. 1. "AXR,Logic level on AXR[n] pin." line.long 0x10 "CFG_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and. if PFUNC = 1 (GPIO function) and PDIR = 1 (output). drives a logic.." bitfld.long 0x10 31. "AFSR,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 30. "AHCLKR,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 29. "ACLKR,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 28. "AFSX,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 27. "AHCLKX,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 26. "ACLKX,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" newline bitfld.long 0x10 25. "AMUTE,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" hexmask.long.tbyte 0x10 4.--24. 1. "RESERVED71" hexmask.long.byte 0x10 0.--3. 1. "AXR,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." group.long 0x44++0xF line.long 0x0 "CFG_GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections. The bit fields in GBLCTL are synchronized and latched by the corresponding clocks (ACLKX for bits 12-8 and ACLKR for bits 4-0). Before GBLCTL is.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED73" bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. By clearing then setting this bit the transmit buffer is flushed to an empty state [XDATA = 1]. If XSMRST = 1 XSRCLR = 1 XDATA = 1 and XBUF is not loaded with new data before the start of the next active.." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED72" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. By clearing then setting this bit the receive buffer is flushed." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" line.long 0x4 "CFG_AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin. The value after reset for register 4 depends on how the pins are being driven." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED74" bitfld.long 0x4 12. "XDMAERR,If transmit DMA error [XDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 11. "RDMAERR,If receive DMA error [RDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 10. "XCKFAIL,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 9. "RCKFAIL,If receive clock failure [RCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 8. "XSYNCERR,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit." "0,1" newline bitfld.long 0x4 7. "RSYNCERR,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 6. "XUNDRN,If transmit underrun error [XUNDRN] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 5. "ROVRN,If receiver overrun error [ROVRN] drive AMUTE active enable bit." "0,1" rbitfld.long 0x4 4. "INSTAT,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1." "0,1" bitfld.long 0x4 3. "INEN,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]." "0,1" bitfld.long 0x4 2. "INPOL,Audio mute in [AMUTEIN] polarity select bit." "0,1" newline bitfld.long 0x4 0.--1. "MUTEN,AMUTE pin enable bit [unless overridden by GPIO registers]." "0,1,2,3" line.long 0x8 "CFG_DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode." hexmask.long 0x8 4.--31. 1. "RESERVED75" bitfld.long 0x8 2.--3. "MODE,Loopback generator mode bits. Applies only when loopback mode is enabled [DLBEN = 1]." "0,1,2,3" bitfld.long 0x8 1. "ORD,Loopback order bit when loopback mode is enabled [DLBEN = 1]." "0,1" bitfld.long 0x8 0. "DLBEN,Loopback mode enable bit." "0,1" line.long 0xC "CFG_DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP." hexmask.long 0xC 4.--31. 1. "RESERVED77" bitfld.long 0xC 3. "VB,Valid bit for odd time slots [DIT right subframe]." "0,1" bitfld.long 0xC 2. "VA,Valid bit for even time slots [DIT left subframe]." "0,1" rbitfld.long 0xC 1. "RESERVED76" "0,1" bitfld.long 0xC 0. "DITEN,DIT mode enable bit. DITEN should only be changed while the XSMRST bit in GBLCTL is in reset [and for startup XSRCLR also in reset]. However it is not necessary to reset the XCLKRST or XHCLKRST bits in GBLCTL to change DITEN." "0,1" group.long 0x60++0x23 line.long 0x0 "CFG_RGBLCTL,Alias of the global control register (GBLCTL). Writing to the receiver global control register (RGBLCTL) affects only the receive bits of GBLCTL (bits 4-0). Reads from RGBLCTL return the value of GBLCTL. RGBLCTL allows the receiver to be.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED79" rbitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A read of this bit returns the XFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A read of this bit returns the XSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A read of this bit returns the XSRCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A read of this bit returns the XHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A read of this bit returns the XCLKRST bit value of GBLCTL. Writes have no effect." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED78" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A write to this bit affects the RFRST bit of GBLCTL." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A write to this bit affects the RSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A write to this bit affects the RSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A write to this bit affects the RHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A write to this bit affects the RCLKRST bit of GBLCTL." "0,1" line.long 0x4 "CFG_RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA." hexmask.long 0x4 0.--31. 1. "RMASK,Receive data mask n enable bit." line.long 0x8 "CFG_RFMT,The receive bit stream format register (RFMT) configures the receive data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED80" bitfld.long 0x8 16.--17. "RDATDLY,Receive bit delay." "0,1,2,3" bitfld.long 0x8 15. "RRVRS,Receive serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "RPBIT,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits. This field only applies when RPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "RSSZ,Receive slot size." newline bitfld.long 0x8 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "RROT,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)." hexmask.long.word 0xC 16.--31. 1. "RESERVED83" hexmask.long.word 0xC 7.--15. 1. "RMOD,Receive frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED82" "0,1,2,3" bitfld.long 0xC 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED81" "0,1,2,3" bitfld.long 0xC 1. "FSRM,Receive frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSRP,Receive frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED86" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED85" newline bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit." "0,1" rbitfld.long 0x10 6. "RESERVED84" "0,1" bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." line.long 0x14 "CFG_AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED88" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKRM,Receive high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED87" "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR." line.long 0x18 "CFG_RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active." hexmask.long 0x18 0.--31. 1. "RTDMS,Receiver mode during TDM time slot n." line.long 0x1C "CFG_RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates RINT. See the RSTAT register for a.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED90" bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED89" "0,1" bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit." "0,1" line.long 0x20 "CFG_RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has priority.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED91" bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR. Allows a single bit to be checked to determine if a receiver error interrupt has occurred." "0,1" bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the data port in a given time slot than were programmed as receivers. Causes a receive interrupt [RINT] if this bit is set and RDMAERR in RINTCTL is set." "0,1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag. Causes a receive interrupt [RINT] if this bit is set and RSTAFRM in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 5. "RDATA,Receive data ready flag. Causes a receive interrupt [RINT] if this bit is set and RDATA in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 4. "RLAST,Receive last slot flag. RLAST is set along with RDATA if the current slot is the last slot in a frame. Causes a receive interrupt [RINT] if this bit is set and RLAST in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT. Allows a single read of RSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. Causes a receive interrupt [RINT] if this bit is set and RCKFAIL in RINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync [AFSR] occurs before it is expected. Causes a receive interrupt [RINT] if this bit is set and RSYNCERR in RINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF but the former data in RBUF has not yet been read by the CPU or DMA. Causes a receive interrupt [RINT] if this bit is set and ROVRN.." "0,1" rgroup.long 0x84++0x3 line.long 0x0 "CFG_RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED92" hexmask.long.word 0x0 0.--8. 1. "RSLOTCNT,0-17Fh = Current receive time slot count. Legal values: 0 to 383 [17Fh]. TDM function is not supported for > 32 time slots. However TDM time slot counter may count to 383 when used to receive a DIR block [transferred over TDM format]." group.long 0x88++0x7 line.long 0x0 "CFG_RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "RCNT,Receive clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 receive high-frequency master clock [AHCLKR] signals and stores the count in RCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "RMAX,Receive clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "RMIN,Receive clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If RCNT is less than RMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED93" hexmask.long.byte 0x0 0.--3. 1. "RPS,Receive clock check prescaler value." line.long 0x4 "CFG_PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event. Note for device-specific registers: Accessing PIDTCTL not implemented on a specific device may cause improper operation." hexmask.long 0x4 1.--31. 1. "RESERVED94" bitfld.long 0x4 0. "RDATDMA,Receive data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" group.long 0xA0++0x23 line.long 0x0 "CFG_XGBLCTL,Alias of the global control register (GBLCTL). Writing to the transmitter global control register (XGBLCTL) affects only the transmit bits of GBLCTL (bits 12-8). Reads from XGBLCTL return the value of GBLCTL. XGBLCTL allows the transmitter to.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED96" bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A write to this bit affects the XFRST bit of GBLCTL." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A write to this bit affects the XSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A write to this bit affects the XSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A write to this bit affects the XHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A write to this bit affects the XCLKRST bit of GBLCTL." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED95" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A read of this bit returns the RFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A read of this bit returns the RSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A read of this bit returns the RSRSCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A read of this bit returns the RHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of GBLCTL. Writes have no effect." "0,1" line.long 0x4 "CFG_XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP." hexmask.long 0x4 0.--31. 1. "XMASK,Transmit data mask n enable bit." line.long 0x8 "CFG_XFMT,The transmit bit stream format register (XFMT) configures the transmit data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED97" bitfld.long 0x8 16.--17. "XDATDLY,Transmit sync bit delay." "0,1,2,3" bitfld.long 0x8 15. "XRVRS,Transmit serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "XPBIT,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting. This field only applies when XPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "XSSZ,Transmit slot size." newline bitfld.long 0x8 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "XROT,Right-rotation value for transmit rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)." hexmask.long.word 0xC 16.--31. 1. "RESERVED100" hexmask.long.word 0xC 7.--15. 1. "XMOD,Transmit frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED99" "0,1,2,3" bitfld.long 0xC 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED98" "0,1,2,3" bitfld.long 0xC 1. "FSXM,Transmit frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSXP,Transmit frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED102" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED101" newline bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit." "0,1" bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit." "0,1" bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX." line.long 0x14 "CFG_AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED104" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED103" "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX." line.long 0x18 "CFG_XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active. TDM time slot counter range is extended to 384 slots (to support SPDIF blocks of 384 subframes). XTDM operates modulo 32. that is. XTDMS.." hexmask.long 0x18 0.--31. 1. "XTDMS,Transmitter mode during TDM time slot n." line.long 0x1C "CFG_XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates XINT. See the XSTAT register for.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED106" bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED105" "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit." "0,1" line.long 0x20 "CFG_XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED107" bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more serializers through the data port in a given time slot than were programmed as transmitters. Causes a transmit interrupt [XINT] if this bit is set and XDMAERR in XINTCTL is.." "0,1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag. Causes a transmit interrupt [XINT] if this bit is set and XSTAFRM in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 5. "XDATA,Transmit data ready flag. Causes a transmit interrupt [XINT] if this bit is set and XDATA in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag. XLAST is set along with XDATA if the current slot is the last slot in a frame. Causes a transmit interrupt [XINT] if this bit is set and XLAST in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt [XINT] if this bit is set and XCKFAIL in XINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag. XSYNCERR is set when a new transmit frame sync [AFSX] occurs before it is expected. Causes a transmit interrupt [XINT] if this bit is set and XSYNCERR in XINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF to XRSR but XBUF has not yet been serviced with new data since the last transfer. Causes a transmit interrupt [XINT] if this bit is.." "0,1" rgroup.long 0xC4++0x3 line.long 0x0 "CFG_XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED108" hexmask.long.word 0x0 0.--9. 1. "XSLOTCNT,Current transmit time slot count. Legal values: 0 to 383 [17Fh]. During reset this counter value is 383 so the next count value which is used to encode the first DIT group of data will be 0 and encodes the B preamble. TDM function is not.." group.long 0xC8++0x7 line.long 0x0 "CFG_XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "XCNT,Transmit clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 transmit high-frequency master clock [AHCLKX] signals and stores the count in XCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "XMAX,Transmit clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "XMIN,Transmit clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If XCNT is less than XMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED109" hexmask.long.byte 0x0 0.--3. 1. "XPS,Transmit clock check prescaler value. Fh = Reserved from 9h to Fh." line.long 0x4 "CFG_XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event. Note for device-specific registers: Accessing XEVTCTL not implemented on a specific device may cause improper device operation." hexmask.long 0x4 1.--31. 1. "RESERVED110" bitfld.long 0x4 0. "XDATDMA,Transmit data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" group.long 0x100++0x5F line.long 0x0 "CFG_DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x0 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x4 "CFG_DITCSRA1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x8 "CFG_DITCSRA2,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x8 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0xC "CFG_DITCSRA3,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0xC 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x10 "CFG_DITCSRA4,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x10 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x14 "CFG_DITCSRA5,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x14 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x18 "CFG_DITCSRB0,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x18 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x1C "CFG_DITCSRB1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x1C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x20 "CFG_DITCSRB2,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x20 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x24 "CFG_DITCSRB3,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x24 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x28 "CFG_DITCSRB4,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x28 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x2C "CFG_DITCSRB5,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x2C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x30 "CFG_DITUDRA0,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x30 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x34 "CFG_DITUDRA1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x34 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x38 "CFG_DITUDRA2,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x38 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x3C "CFG_DITUDRA3,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x3C 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x40 "CFG_DITUDRA4,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x40 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x44 "CFG_DITUDRA5,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x44 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x48 "CFG_DITUDRB0,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x48 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x4C "CFG_DITUDRB1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4C 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x50 "CFG_DITUDRB2,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x50 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x54 "CFG_DITUDRB3,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x54 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x58 "CFG_DITUDRB4,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x58 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x5C "CFG_DITUDRB5,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x5C 0.--31. 1. "DITUDRB,DIT right channel user data registers." group.long 0x180++0x3F line.long 0x0 "CFG_SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x0 6.--31. 1. "RESERVED111" rbitfld.long 0x0 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x0 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x0 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x0 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x4 "CFG_SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x4 6.--31. 1. "RESERVED112" rbitfld.long 0x4 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x4 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x4 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x4 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x8 "CFG_SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x8 6.--31. 1. "RESERVED113" rbitfld.long 0x8 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x8 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x8 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x8 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0xC "CFG_SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0xC 6.--31. 1. "RESERVED114" rbitfld.long 0xC 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0xC 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0xC 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0xC 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x10 "CFG_SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x10 6.--31. 1. "RESERVED115" rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x14 "CFG_SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x14 6.--31. 1. "RESERVED116" rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x18 "CFG_SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x18 6.--31. 1. "RESERVED117" rbitfld.long 0x18 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x18 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x18 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x18 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x1C "CFG_SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x1C 6.--31. 1. "RESERVED118" rbitfld.long 0x1C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x1C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x1C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x1C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x20 "CFG_SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x20 6.--31. 1. "RESERVED119" rbitfld.long 0x20 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x20 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x20 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x20 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x24 "CFG_SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x24 6.--31. 1. "RESERVED120" rbitfld.long 0x24 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x24 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x24 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x24 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x28 "CFG_SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x28 6.--31. 1. "RESERVED121" rbitfld.long 0x28 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x28 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x28 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x28 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x2C "CFG_SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x2C 6.--31. 1. "RESERVED122" rbitfld.long 0x2C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x2C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x2C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x2C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x30 "CFG_SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x30 6.--31. 1. "RESERVED123" rbitfld.long 0x30 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x30 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x30 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x30 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x34 "CFG_SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x34 6.--31. 1. "RESERVED124" rbitfld.long 0x34 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x34 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x34 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x34 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x38 "CFG_SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x38 6.--31. 1. "RESERVED125" rbitfld.long 0x38 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x38 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x38 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x38 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x3C "CFG_SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x3C 6.--31. 1. "RESERVED126" rbitfld.long 0x3C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x3C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x3C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x3C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" group.long 0x200++0x3F line.long 0x0 "CFG_XBUF0,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x0 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x4 "CFG_XBUF1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x4 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x8 "CFG_XBUF2,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x8 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0xC "CFG_XBUF3,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0xC 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x10 "CFG_XBUF4,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x10 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x14 "CFG_XBUF5,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x14 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x18 "CFG_XBUF6,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x18 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x1C "CFG_XBUF7,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x1C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x20 "CFG_XBUF8,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x20 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x24 "CFG_XBUF9,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x24 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x28 "CFG_XBUF10,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x28 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x2C "CFG_XBUF11,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x2C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x30 "CFG_XBUF12,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x30 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x34 "CFG_XBUF13,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x34 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x38 "CFG_XBUF14,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x38 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x3C "CFG_XBUF15,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x3C 0.--31. 1. "XBUF,Transmit buffers for serializers." group.long 0x280++0x3F line.long 0x0 "CFG_RBUF0,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x0 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x4 "CFG_RBUF1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x4 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x8 "CFG_RBUF2,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x8 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0xC "CFG_RBUF3,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0xC 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x10 "CFG_RBUF4,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x10 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x14 "CFG_RBUF5,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x14 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x18 "CFG_RBUF6,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x18 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x1C "CFG_RBUF7,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x1C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x20 "CFG_RBUF8,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x20 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x24 "CFG_RBUF9,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x24 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x28 "CFG_RBUF10,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x28 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x2C "CFG_RBUF11,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x2C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x30 "CFG_RBUF12,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x30 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x34 "CFG_RBUF13,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x34 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x38 "CFG_RBUF14,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x38 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x3C "CFG_RBUF15,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x3C 0.--31. 1. "RBUF,Receive buffers for serializers." group.long 0x1000++0x3 line.long 0x0 "CFG_WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED127" bitfld.long 0x0 16. "WENA,Write FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "WNUMEVT,Write word count per DMA event [32 bit]. When the Write FIFO has space for at least WNUMEVT words of data then an AXEVT [transmit DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the.." hexmask.long.byte 0x0 0.--7. 1. "WNUMDMA,Write word count per transfer [32 bit words]. Upon a transmit DMA event from the McASP WNUMDMA words are transferred from the Write FIFO to the McASP. This value must equal the number of McASP serializers used as transmitters. This value must be.." rgroup.long 0x1004++0x3 line.long 0x0 "CFG_WFIFOSTS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED128" hexmask.long.byte 0x0 0.--7. 1. "WLVL,Write level [read-only]. Number of 32 bit words currently in the Write FIFO. 40h = 3 to 64 words currently in Write FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." group.long 0x1008++0x3 line.long 0x0 "CFG_RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED129" bitfld.long 0x0 16. "RENA,Read FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "RNUMEVT,Read word count per DMA event [32 bit]. When the Read FIFO contains at least RNUMEVT words of data then an AREVT [receive DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the number.." hexmask.long.byte 0x0 0.--7. 1. "RNUMDMA,Read word count per transfer [32 bit words]. Upon a receive DMA event from the McASP the Read FIFO reads RNUMDMA words from the McASP. This value must equal the number of McASP serializers used as receivers. This value must be set prior to.." rgroup.long 0x100C++0x3 line.long 0x0 "CFG_RFIFOSTS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED130" hexmask.long.byte 0x0 0.--7. 1. "RLVL,Read level [read-only]. Number of 32 bit words currently in the Read FIFO. 40h = 3 to 64 words currently in Read FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." tree.end tree "MCASP2_CFG" base ad:0x2B20000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_PID,The revision identification register (PID) contains identification data for the peripheral." hexmask.long 0x0 0.--31. 1. "REV,Identifies revision of peripheral." group.long 0x4++0x3 line.long 0x0 "CFG_PWRIDLESYSCONFIG" hexmask.long 0x0 6.--31. 1. "RESERVED66" hexmask.long.byte 0x0 2.--5. 1. "OTHER,Reserved for future programming." bitfld.long 0x0 0.--1. "IDLEMODE,Power management Configuration of the local target state management mode. By definition target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" group.long 0x10++0x13 line.long 0x0 "CFG_PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin. CAUTION: Writing a value other than 0 to reserved bits in.." bitfld.long 0x0 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO." "0,1" newline bitfld.long 0x0 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO." "0,1" hexmask.long.tbyte 0x0 4.--24. 1. "RESERVED67" hexmask.long.byte 0x0 0.--3. 1. "AXR,Determines if AXRn pin functions as McASP or GPIO." line.long 0x4 "CFG_PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin. Regardless of the pin function register (PFUNC) setting. each PDIR bit must be set to 1 for.." bitfld.long 0x4 31. "AFSR,Determines if AFSR pin functions as an input or output." "0,1" bitfld.long 0x4 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output." "0,1" bitfld.long 0x4 29. "ACLKR,Determines if ACLKR pin functions as an input or output." "0,1" bitfld.long 0x4 28. "AFSX,Determines if AFSX pin functions as an input or output." "0,1" bitfld.long 0x4 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output." "0,1" bitfld.long 0x4 26. "ACLKX,Determines if ACLKX pin functions as an input or output." "0,1" newline bitfld.long 0x4 25. "AMUTE,Determines if AMUTE pin functions as an input or output." "0,1" hexmask.long.tbyte 0x4 4.--24. 1. "RESERVED68" hexmask.long.byte 0x4 0.--3. 1. "AXR,Determines if AXRn pin functions as an input or output." line.long 0x8 "CFG_PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times. The value held by PDOUT is not affected by writing to PDIR and PFUNC. However. the data value in PDOUT is driven out onto the McASP.." bitfld.long 0x8 31. "AFSR,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1." "0,1" bitfld.long 0x8 30. "AHCLKR,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1." "0,1" bitfld.long 0x8 29. "ACLKR,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1." "0,1" bitfld.long 0x8 28. "AFSX,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1." "0,1" bitfld.long 0x8 27. "AHCLKX,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1." "0,1" bitfld.long 0x8 26. "ACLKX,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1." "0,1" newline bitfld.long 0x8 25. "AMUTE,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1." "0,1" hexmask.long.tbyte 0x8 4.--24. 1. "RESERVED69" hexmask.long.byte 0x8 0.--3. 1. "AXR,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1." line.long 0xC "CFG_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read. regardless of the state of PFUNC and PDIR. The value after reset for registers 1 through 15 and 24 through.." bitfld.long 0xC 31. "AFSR,Logic level on AFSR pin." "0,1" bitfld.long 0xC 30. "AHCLKR,Logic level on AHCLKR pin." "0,1" bitfld.long 0xC 29. "ACLKR,Logic level on ACLKR pin." "0,1" bitfld.long 0xC 28. "AFSX,Logic level on AFSX pin." "0,1" bitfld.long 0xC 27. "AHCLKX,Logic level on AHCLKX pin." "0,1" bitfld.long 0xC 26. "ACLKX,Logic level on ACLKX pin." "0,1" newline bitfld.long 0xC 25. "AMUTE,Logic level on AMUTE pin." "0,1" hexmask.long.tbyte 0xC 4.--24. 1. "RESERVED70" hexmask.long.byte 0xC 0.--3. 1. "AXR,Logic level on AXR[n] pin." line.long 0x10 "CFG_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and. if PFUNC = 1 (GPIO function) and PDIR = 1 (output). drives a logic.." bitfld.long 0x10 31. "AFSR,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 30. "AHCLKR,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 29. "ACLKR,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 28. "AFSX,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 27. "AHCLKX,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x10 26. "ACLKX,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" newline bitfld.long 0x10 25. "AMUTE,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" hexmask.long.tbyte 0x10 4.--24. 1. "RESERVED71" hexmask.long.byte 0x10 0.--3. 1. "AXR,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." group.long 0x44++0xF line.long 0x0 "CFG_GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections. The bit fields in GBLCTL are synchronized and latched by the corresponding clocks (ACLKX for bits 12-8 and ACLKR for bits 4-0). Before GBLCTL is.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED73" bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. By clearing then setting this bit the transmit buffer is flushed to an empty state [XDATA = 1]. If XSMRST = 1 XSRCLR = 1 XDATA = 1 and XBUF is not loaded with new data before the start of the next active.." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED72" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. By clearing then setting this bit the receive buffer is flushed." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive high-frequency clock divider reset enable bit." "0,1" line.long 0x4 "CFG_AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin. The value after reset for register 4 depends on how the pins are being driven." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED74" bitfld.long 0x4 12. "XDMAERR,If transmit DMA error [XDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 11. "RDMAERR,If receive DMA error [RDMAERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 10. "XCKFAIL,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 9. "RCKFAIL,If receive clock failure [RCKFAIL] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 8. "XSYNCERR,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit." "0,1" newline bitfld.long 0x4 7. "RSYNCERR,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 6. "XUNDRN,If transmit underrun error [XUNDRN] drive AMUTE active enable bit." "0,1" bitfld.long 0x4 5. "ROVRN,If receiver overrun error [ROVRN] drive AMUTE active enable bit." "0,1" rbitfld.long 0x4 4. "INSTAT,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1." "0,1" bitfld.long 0x4 3. "INEN,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]." "0,1" bitfld.long 0x4 2. "INPOL,Audio mute in [AMUTEIN] polarity select bit." "0,1" newline bitfld.long 0x4 0.--1. "MUTEN,AMUTE pin enable bit [unless overridden by GPIO registers]." "0,1,2,3" line.long 0x8 "CFG_DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode." hexmask.long 0x8 4.--31. 1. "RESERVED75" bitfld.long 0x8 2.--3. "MODE,Loopback generator mode bits. Applies only when loopback mode is enabled [DLBEN = 1]." "0,1,2,3" bitfld.long 0x8 1. "ORD,Loopback order bit when loopback mode is enabled [DLBEN = 1]." "0,1" bitfld.long 0x8 0. "DLBEN,Loopback mode enable bit." "0,1" line.long 0xC "CFG_DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP." hexmask.long 0xC 4.--31. 1. "RESERVED77" bitfld.long 0xC 3. "VB,Valid bit for odd time slots [DIT right subframe]." "0,1" bitfld.long 0xC 2. "VA,Valid bit for even time slots [DIT left subframe]." "0,1" rbitfld.long 0xC 1. "RESERVED76" "0,1" bitfld.long 0xC 0. "DITEN,DIT mode enable bit. DITEN should only be changed while the XSMRST bit in GBLCTL is in reset [and for startup XSRCLR also in reset]. However it is not necessary to reset the XCLKRST or XHCLKRST bits in GBLCTL to change DITEN." "0,1" group.long 0x60++0x23 line.long 0x0 "CFG_RGBLCTL,Alias of the global control register (GBLCTL). Writing to the receiver global control register (RGBLCTL) affects only the receive bits of GBLCTL (bits 4-0). Reads from RGBLCTL return the value of GBLCTL. RGBLCTL allows the receiver to be.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED79" rbitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A read of this bit returns the XFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A read of this bit returns the XSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A read of this bit returns the XSRCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A read of this bit returns the XHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A read of this bit returns the XCLKRST bit value of GBLCTL. Writes have no effect." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED78" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A write to this bit affects the RFRST bit of GBLCTL." "0,1" bitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A write to this bit affects the RSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A write to this bit affects the RSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A write to this bit affects the RHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A write to this bit affects the RCLKRST bit of GBLCTL." "0,1" line.long 0x4 "CFG_RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA." hexmask.long 0x4 0.--31. 1. "RMASK,Receive data mask n enable bit." line.long 0x8 "CFG_RFMT,The receive bit stream format register (RFMT) configures the receive data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED80" bitfld.long 0x8 16.--17. "RDATDLY,Receive bit delay." "0,1,2,3" bitfld.long 0x8 15. "RRVRS,Receive serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "RPBIT,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits. This field only applies when RPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "RSSZ,Receive slot size." newline bitfld.long 0x8 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "RROT,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)." hexmask.long.word 0xC 16.--31. 1. "RESERVED83" hexmask.long.word 0xC 7.--15. 1. "RMOD,Receive frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED82" "0,1,2,3" bitfld.long 0xC 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED81" "0,1,2,3" bitfld.long 0xC 1. "FSRM,Receive frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSRP,Receive frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED86" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED85" newline bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit." "0,1" rbitfld.long 0x10 6. "RESERVED84" "0,1" bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bit does not have any effect if ACLKXCTL.ASYNC = 0." line.long 0x14 "CFG_AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED88" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKRM,Receive high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED87" "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR." line.long 0x18 "CFG_RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active." hexmask.long 0x18 0.--31. 1. "RTDMS,Receiver mode during TDM time slot n." line.long 0x1C "CFG_RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates RINT. See the RSTAT register for a.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED90" bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED89" "0,1" bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit." "0,1" line.long 0x20 "CFG_RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has priority.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED91" bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR. Allows a single bit to be checked to determine if a receiver error interrupt has occurred." "0,1" bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the data port in a given time slot than were programmed as receivers. Causes a receive interrupt [RINT] if this bit is set and RDMAERR in RINTCTL is set." "0,1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag. Causes a receive interrupt [RINT] if this bit is set and RSTAFRM in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 5. "RDATA,Receive data ready flag. Causes a receive interrupt [RINT] if this bit is set and RDATA in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x20 4. "RLAST,Receive last slot flag. RLAST is set along with RDATA if the current slot is the last slot in a frame. Causes a receive interrupt [RINT] if this bit is set and RLAST in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT. Allows a single read of RSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. Causes a receive interrupt [RINT] if this bit is set and RCKFAIL in RINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync [AFSR] occurs before it is expected. Causes a receive interrupt [RINT] if this bit is set and RSYNCERR in RINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF but the former data in RBUF has not yet been read by the CPU or DMA. Causes a receive interrupt [RINT] if this bit is set and ROVRN.." "0,1" rgroup.long 0x84++0x3 line.long 0x0 "CFG_RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED92" hexmask.long.word 0x0 0.--8. 1. "RSLOTCNT,0-17Fh = Current receive time slot count. Legal values: 0 to 383 [17Fh]. TDM function is not supported for > 32 time slots. However TDM time slot counter may count to 383 when used to receive a DIR block [transferred over TDM format]." group.long 0x88++0x7 line.long 0x0 "CFG_RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "RCNT,Receive clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 receive high-frequency master clock [AHCLKR] signals and stores the count in RCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "RMAX,Receive clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "RMIN,Receive clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock [AHCLKR] signals have been received. If RCNT is less than RMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED93" hexmask.long.byte 0x0 0.--3. 1. "RPS,Receive clock check prescaler value." line.long 0x4 "CFG_PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event. Note for device-specific registers: Accessing PIDTCTL not implemented on a specific device may cause improper operation." hexmask.long 0x4 1.--31. 1. "RESERVED94" bitfld.long 0x4 0. "RDATDMA,Receive data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" group.long 0xA0++0x23 line.long 0x0 "CFG_XGBLCTL,Alias of the global control register (GBLCTL). Writing to the transmitter global control register (XGBLCTL) affects only the transmit bits of GBLCTL (bits 12-8). Reads from XGBLCTL return the value of GBLCTL. XGBLCTL allows the transmitter to.." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED96" bitfld.long 0x0 12. "XFRST,Transmit frame sync generator reset enable bit. A write to this bit affects the XFRST bit of GBLCTL." "0,1" bitfld.long 0x0 11. "XSMRST,Transmit state machine reset enable bit. A write to this bit affects the XSMRST bit of GBLCTL." "0,1" bitfld.long 0x0 10. "XSRCLR,Transmit serializer clear enable bit. A write to this bit affects the XSRCLR bit of GBLCTL." "0,1" bitfld.long 0x0 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit. A write to this bit affects the XHCLKRST bit of GBLCTL." "0,1" bitfld.long 0x0 8. "XCLKRST,Transmit clock divider reset enable bit. A write to this bit affects the XCLKRST bit of GBLCTL." "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED95" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 4. "RFRST,Receive frame sync generator reset enable bit. A read of this bit returns the RFRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 3. "RSMRST,Receive state machine reset enable bit. A read of this bit returns the RSMRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 2. "RSRCLR,Receive serializer clear enable bit. A read of this bit returns the RSRSCLR bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit. A read of this bit returns the RHCLKRST bit value of GBLCTL. Writes have no effect." "0,1" rbitfld.long 0x0 0. "RCLKRST,Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of GBLCTL. Writes have no effect." "0,1" line.long 0x4 "CFG_XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP." hexmask.long 0x4 0.--31. 1. "XMASK,Transmit data mask n enable bit." line.long 0x8 "CFG_XFMT,The transmit bit stream format register (XFMT) configures the transmit data format." hexmask.long.word 0x8 18.--31. 1. "RESERVED97" bitfld.long 0x8 16.--17. "XDATDLY,Transmit sync bit delay." "0,1,2,3" bitfld.long 0x8 15. "XRVRS,Transmit serial bitstream order." "0,1" bitfld.long 0x8 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" hexmask.long.byte 0x8 8.--12. 1. "XPBIT,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting. This field only applies when XPAD = 2h." hexmask.long.byte 0x8 4.--7. 1. "XSSZ,Transmit slot size." newline bitfld.long 0x8 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port." "0,1" bitfld.long 0x8 0.--2. "XROT,Right-rotation value for transmit rotate right format unit." "0,1,2,3,4,5,6,7" line.long 0xC "CFG_AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)." hexmask.long.word 0xC 16.--31. 1. "RESERVED100" hexmask.long.word 0xC 7.--15. 1. "XMOD,Transmit frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh." rbitfld.long 0xC 5.--6. "RESERVED99" "0,1,2,3" bitfld.long 0xC 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period." "0,1" rbitfld.long 0xC 2.--3. "RESERVED98" "0,1,2,3" bitfld.long 0xC 1. "FSXM,Transmit frame sync generation select bit." "0,1" newline bitfld.long 0xC 0. "FSXP,Transmit frame sync polarity select bit." "0,1" line.long 0x10 "CFG_ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator." hexmask.long.word 0x10 21.--31. 1. "RESERVED102" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1" bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "0,1,2,3" hexmask.long.byte 0x10 8.--15. 1. "RESERVED101" newline bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit." "0,1" bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit." "0,1" bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit." "0,1" hexmask.long.byte 0x10 0.--4. 1. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX." line.long 0x14 "CFG_AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator." hexmask.long.word 0x14 21.--31. 1. "RESERVED104" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1" bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "0,1,2,3" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit." "0,1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit." "0,1" rbitfld.long 0x14 12.--13. "RESERVED103" "0,1,2,3" hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX." line.long 0x18 "CFG_XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active. TDM time slot counter range is extended to 384 slots (to support SPDIF blocks of 384 subframes). XTDM operates modulo 32. that is. XTDMS.." hexmask.long 0x18 0.--31. 1. "XTDMS,Transmitter mode during TDM time slot n." line.long 0x1C "CFG_XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT). When the register bit(s) is set to 1. the occurrence of the enabled McASP condition(s) generates XINT. See the XSTAT register for.." hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED106" bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit." "0,1" rbitfld.long 0x1C 6. "RESERVED105" "0,1" bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit." "0,1" bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit." "0,1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit." "0,1" newline bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit." "0,1" bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit." "0,1" bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit." "0,1" line.long 0x20 "CFG_XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has.." hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED107" bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more serializers through the data port in a given time slot than were programmed as transmitters. Causes a transmit interrupt [XINT] if this bit is set and XDMAERR in XINTCTL is.." "0,1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag. Causes a transmit interrupt [XINT] if this bit is set and XSTAFRM in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 5. "XDATA,Transmit data ready flag. Causes a transmit interrupt [XINT] if this bit is set and XDATA in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect." "0,1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag. XLAST is set along with XDATA if the current slot is the last slot in a frame. Causes a transmit interrupt [XINT] if this bit is set and XLAST in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0.." "0,1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt [XINT] if this bit is set and XCKFAIL in XINTCTL is set. This bit is cleared by writing a 1 to this bit." "0,1" bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag. XSYNCERR is set when a new transmit frame sync [AFSX] occurs before it is expected. Causes a transmit interrupt [XINT] if this bit is set and XSYNCERR in XINTCTL is set. This bit is cleared by writing a 1 to.." "0,1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF to XRSR but XBUF has not yet been serviced with new data since the last transfer. Causes a transmit interrupt [XINT] if this bit is.." "0,1" rgroup.long 0xC4++0x3 line.long 0x0 "CFG_XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED108" hexmask.long.word 0x0 0.--9. 1. "XSLOTCNT,Current transmit time slot count. Legal values: 0 to 383 [17Fh]. During reset this counter value is 383 so the next count value which is used to encode the first DIT group of data will be 0 and encodes the B preamble. TDM function is not.." group.long 0xC8++0x7 line.long 0x0 "CFG_XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit." hexmask.long.byte 0x0 24.--31. 1. "XCNT,Transmit clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 transmit high-frequency master clock [AHCLKX] signals and stores the count in XCNT until the next measurement is.." hexmask.long.byte 0x0 16.--23. 1. "XMAX,Transmit clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If the current counter value is greater than.." hexmask.long.byte 0x0 8.--15. 1. "XMIN,Transmit clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock [AHCLKX] signals have been received. If XCNT is less than XMIN after counting 32.." hexmask.long.byte 0x0 4.--7. 1. "RESERVED109" hexmask.long.byte 0x0 0.--3. 1. "XPS,Transmit clock check prescaler value. Fh = Reserved from 9h to Fh." line.long 0x4 "CFG_XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event. Note for device-specific registers: Accessing XEVTCTL not implemented on a specific device may cause improper device operation." hexmask.long 0x4 1.--31. 1. "RESERVED110" bitfld.long 0x4 0. "XDATDMA,Transmit data DMA request enable bit. If writing to this bit always write the default value of 0." "0,1" group.long 0x100++0x5F line.long 0x0 "CFG_DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x0 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x4 "CFG_DITCSRA1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x8 "CFG_DITCSRA2,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x8 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0xC "CFG_DITCSRA3,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0xC 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x10 "CFG_DITCSRA4,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x10 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x14 "CFG_DITCSRA5,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x14 0.--31. 1. "DITCSRA,DIT left channel status registers." line.long 0x18 "CFG_DITCSRB0,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x18 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x1C "CFG_DITCSRB1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x1C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x20 "CFG_DITCSRB2,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x20 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x24 "CFG_DITCSRB3,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x24 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x28 "CFG_DITCSRB4,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x28 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x2C "CFG_DITCSRB5,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of channel status data for a complete block of transmission. The DIT reuses.." hexmask.long 0x2C 0.--31. 1. "DITCSRB,DIT right channel status registers." line.long 0x30 "CFG_DITUDRA0,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x30 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x34 "CFG_DITUDRA1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x34 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x38 "CFG_DITUDRA2,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x38 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x3C "CFG_DITUDRA3,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x3C 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x40 "CFG_DITUDRA4,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x40 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x44 "CFG_DITUDRA5,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x44 0.--31. 1. "DITUDRA,DIT left channel user data registers." line.long 0x48 "CFG_DITUDRB0,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x48 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x4C "CFG_DITUDRB1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x4C 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x50 "CFG_DITUDRB2,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x50 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x54 "CFG_DITUDRB3,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x54 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x58 "CFG_DITUDRB4,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x58 0.--31. 1. "DITUDRB,DIT right channel user data registers." line.long 0x5C "CFG_DITUDRB5,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot). Each of the six 32-bit registers can store 192 bits of user data for a complete block of transmission. The DIT reuses the.." hexmask.long 0x5C 0.--31. 1. "DITUDRB,DIT right channel user data registers." group.long 0x180++0x3F line.long 0x0 "CFG_SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x0 6.--31. 1. "RESERVED111" rbitfld.long 0x0 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x0 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x0 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x0 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x4 "CFG_SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x4 6.--31. 1. "RESERVED112" rbitfld.long 0x4 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x4 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x4 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x4 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x8 "CFG_SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x8 6.--31. 1. "RESERVED113" rbitfld.long 0x8 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x8 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x8 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x8 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0xC "CFG_SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0xC 6.--31. 1. "RESERVED114" rbitfld.long 0xC 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0xC 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0xC 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0xC 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x10 "CFG_SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x10 6.--31. 1. "RESERVED115" rbitfld.long 0x10 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x10 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x10 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x10 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x14 "CFG_SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x14 6.--31. 1. "RESERVED116" rbitfld.long 0x14 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x14 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x14 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x14 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x18 "CFG_SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x18 6.--31. 1. "RESERVED117" rbitfld.long 0x18 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x18 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x18 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x18 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x1C "CFG_SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x1C 6.--31. 1. "RESERVED118" rbitfld.long 0x1C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x1C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x1C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x1C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x20 "CFG_SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x20 6.--31. 1. "RESERVED119" rbitfld.long 0x20 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x20 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x20 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x20 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x24 "CFG_SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x24 6.--31. 1. "RESERVED120" rbitfld.long 0x24 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x24 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x24 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x24 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x28 "CFG_SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x28 6.--31. 1. "RESERVED121" rbitfld.long 0x28 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x28 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x28 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x28 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x2C "CFG_SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x2C 6.--31. 1. "RESERVED122" rbitfld.long 0x2C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x2C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x2C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x2C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x30 "CFG_SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x30 6.--31. 1. "RESERVED123" rbitfld.long 0x30 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x30 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x30 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x30 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x34 "CFG_SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x34 6.--31. 1. "RESERVED124" rbitfld.long 0x34 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x34 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x34 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x34 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x38 "CFG_SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x38 6.--31. 1. "RESERVED125" rbitfld.long 0x38 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x38 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x38 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x38 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" line.long 0x3C "CFG_SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0). There are up to 16 serializers per McASP. Note for device-specific registers: Accessing SRCTL0n not implemented on a specific device may cause improper device operation." hexmask.long 0x3C 6.--31. 1. "RESERVED126" rbitfld.long 0x3C 5. "RRDY,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive [2h] RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF." "0,1" rbitfld.long 0x3C 4. "XRDY,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit [1h] XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1.." "0,1" bitfld.long 0x3C 2.--3. "DISMOD,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin [PFUNC = 0]." "0,1,2,3" bitfld.long 0x3C 0.--1. "SRMOD,Serializer mode bit." "0,1,2,3" group.long 0x200++0x3F line.long 0x0 "CFG_XBUF0,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x0 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x4 "CFG_XBUF1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x4 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x8 "CFG_XBUF2,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x8 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0xC "CFG_XBUF3,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0xC 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x10 "CFG_XBUF4,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x10 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x14 "CFG_XBUF5,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x14 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x18 "CFG_XBUF6,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x18 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x1C "CFG_XBUF7,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x1C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x20 "CFG_XBUF8,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x20 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x24 "CFG_XBUF9,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x24 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x28 "CFG_XBUF10,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x28 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x2C "CFG_XBUF11,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x2C 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x30 "CFG_XBUF12,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x30 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x34 "CFG_XBUF13,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x34 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x38 "CFG_XBUF14,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x38 0.--31. 1. "XBUF,Transmit buffers for serializers." line.long 0x3C "CFG_XBUF15,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit. For transmit operations. the XBUF0 is an alias of the XRBUF in the serializer. Accessing XBUF0 registers not implemented on a specific device may cause.." hexmask.long 0x3C 0.--31. 1. "XBUF,Transmit buffers for serializers." group.long 0x280++0x3F line.long 0x0 "CFG_RBUF0,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x0 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x4 "CFG_RBUF1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x4 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x8 "CFG_RBUF2,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x8 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0xC "CFG_RBUF3,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0xC 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x10 "CFG_RBUF4,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x10 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x14 "CFG_RBUF5,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x14 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x18 "CFG_RBUF6,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x18 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x1C "CFG_RBUF7,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x1C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x20 "CFG_RBUF8,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x20 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x24 "CFG_RBUF9,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x24 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x28 "CFG_RBUF10,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x28 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x2C "CFG_RBUF11,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x2C 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x30 "CFG_RBUF12,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x30 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x34 "CFG_RBUF13,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x34 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x38 "CFG_RBUF14,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x38 0.--31. 1. "RBUF,Receive buffers for serializers." line.long 0x3C "CFG_RBUF15,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit. For receive operations. the RBUF0 is an alias of the XRBUF0 in the serializer. Accessing XBUF registers not.." hexmask.long 0x3C 0.--31. 1. "RBUF,Receive buffers for serializers." group.long 0x1000++0x3 line.long 0x0 "CFG_WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED127" bitfld.long 0x0 16. "WENA,Write FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "WNUMEVT,Write word count per DMA event [32 bit]. When the Write FIFO has space for at least WNUMEVT words of data then an AXEVT [transmit DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the.." hexmask.long.byte 0x0 0.--7. 1. "WNUMDMA,Write word count per transfer [32 bit words]. Upon a transmit DMA event from the McASP WNUMDMA words are transferred from the Write FIFO to the McASP. This value must equal the number of McASP serializers used as transmitters. This value must be.." rgroup.long 0x1004++0x3 line.long 0x0 "CFG_WFIFOSTS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED128" hexmask.long.byte 0x0 0.--7. 1. "WLVL,Write level [read-only]. Number of 32 bit words currently in the Write FIFO. 40h = 3 to 64 words currently in Write FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." group.long 0x1008++0x3 line.long 0x0 "CFG_RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled. it must be enabled prior to taking the McASP out of reset" hexmask.long.word 0x0 17.--31. 1. "RESERVED129" bitfld.long 0x0 16. "RENA,Read FIFO enable bit." "0,1" hexmask.long.byte 0x0 8.--15. 1. "RNUMEVT,Read word count per DMA event [32 bit]. When the Read FIFO contains at least RNUMEVT words of data then an AREVT [receive DMA event] is generated to the host/DMA controller. This value should be set to a non-zero integer multiple of the number.." hexmask.long.byte 0x0 0.--7. 1. "RNUMDMA,Read word count per transfer [32 bit words]. Upon a receive DMA event from the McASP the Read FIFO reads RNUMDMA words from the McASP. This value must equal the number of McASP serializers used as receivers. This value must be set prior to.." rgroup.long 0x100C++0x3 line.long 0x0 "CFG_RFIFOSTS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED130" hexmask.long.byte 0x0 0.--7. 1. "RLVL,Read level [read-only]. Number of 32 bit words currently in the Read FIFO. 40h = 3 to 64 words currently in Read FIFO from 3h to 40h. FFh = Reserved from 41h to FFh." tree.end tree.end tree "MCRC64_0_REGS" base ad:0x30300000 group.long 0x0++0x3 line.long 0x0 "MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x0 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" newline bitfld.long 0x0 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not.." "0: PSA Signature Register not reset,1: PSA Signature Register reset" group.long 0x8++0x3 line.long 0x0 "MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode." "0: MCRC is not in power down mode,1: MCRC is in power down mode" group.long 0x10++0x3 line.long 0x0 "MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1. The seed value can be planted in PSA Signature Register during data capture mode by writing a seed value into PSA.." bitfld.long 0x0 24.--25. "CH4_MODE,Channel 4 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 16.--17. "CH3_MODE,Channel 3 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode. 00 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: Data Capture mode,1: AUTO mode,?,?" group.long 0x18++0x3 line.long 0x0 "MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read:.." "0: Has no effect,1: Compression Complete Interrupt enable" group.long 0x20++0x3 line.long 0x0 "MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register" bitfld.long 0x0 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" newline bitfld.long 0x0 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable" newline bitfld.long 0x0 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt enable" newline bitfld.long 0x0 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0.." "0: Has no effect,1: Compression Complete Interrupt disable" group.long 0x28++0x3 line.long 0x0 "MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register" bitfld.long 0x0 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." newline bitfld.long 0x0 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active" newline bitfld.long 0x0 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active" newline bitfld.long 0x0 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC.." "0: No CRC pattern compression complete interrupt is..,1: CRC pattern compression complete interrupt is.." rgroup.long 0x30++0x3 line.long 0x0 "MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset" hexmask.long.byte 0x0 0.--7. 1. "CRC,Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag." rgroup.long 0x38++0x3 line.long 0x0 "MCRC64_REGS_CRC_BUSY,CRC Busy Register" bitfld.long 0x0 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" newline bitfld.long 0x0 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1" group.long 0x40++0x7 line.long 0x0 "MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x48++0x3 line.long 0x0 "MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." group.long 0x4C++0x7 line.long 0x0 "MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated." group.long 0x60++0xF line.long 0x0 "MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG1,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register." line.long 0x4 "MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register." line.long 0x8 "MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC1,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register." line.long 0xC "MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC1_47_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register." rgroup.long 0x70++0xF line.long 0x0 "MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG1,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA1,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_47_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." group.long 0x80++0x7 line.long 0x0 "MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x88++0x3 line.long 0x0 "MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." group.long 0x8C++0x7 line.long 0x0 "MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." group.long 0xA0++0xF line.long 0x0 "MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG2,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register." line.long 0x4 "MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register." line.long 0x8 "MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC2,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register." line.long 0xC "MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register." rgroup.long 0xB0++0xF line.long 0x0 "MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG2,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA2,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." group.long 0xC0++0x7 line.long 0x0 "MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0xC8++0x3 line.long 0x0 "MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.." group.long 0xCC++0x7 line.long 0x0 "MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." group.long 0xE0++0xF line.long 0x0 "MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG3,Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register." line.long 0x4 "MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG3_63_32,Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register." line.long 0x8 "MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC3,Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register." line.long 0xC "MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC3_63_32,Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register." rgroup.long 0xF0++0xF line.long 0x0 "MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG3,Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register." line.long 0x4 "MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG3_63_32,Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register." line.long 0x8 "MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA3,Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA3_63_32,Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." group.long 0x100++0x7 line.long 0x0 "MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4" hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed." line.long 0x4 "MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4" hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory." rgroup.long 0x108++0x3 line.long 0x0 "MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4" hexmask.long.word 0x0 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number is logged into current sector ID.." group.long 0x10C++0x7 line.long 0x0 "MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register" hexmask.long.tbyte 0x0 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns." line.long 0x4 "MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x4 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated." group.long 0x120++0xF line.long 0x0 "MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register" hexmask.long 0x0 0.--31. 1. "PSASIG4,This register contains the value stored at PSASIG4[31:0] register." line.long 0x4 "MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register" hexmask.long 0x4 0.--31. 1. "PSASIG4_63_32,This register contains the value stored at PSASIG4[63:32] register." line.long 0x8 "MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register" hexmask.long 0x8 0.--31. 1. "CRC4,Channel 4 CRC Value Low Register." line.long 0xC "MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register" hexmask.long 0xC 0.--31. 1. "CRC4_63_32,Channel 4 CRC Value High Register." rgroup.long 0x130++0xF line.long 0x0 "MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register" hexmask.long 0x0 0.--31. 1. "PSASECSIG4,Channel 4 PSA Sector Signature Low Register." line.long 0x4 "MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register" hexmask.long 0x4 0.--31. 1. "PSASECSIG4_63_32,Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register." line.long 0x8 "MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register" hexmask.long 0x8 0.--31. 1. "RAW_DATA4,Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data." line.long 0xC "MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register" hexmask.long 0xC 0.--31. 1. "RAW_DATA4_63_32,Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data." group.long 0x140++0x3 line.long 0x0 "MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection" bitfld.long 0x0 2. "MEN,Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x0 1. "DTC_MEN,Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.." newline bitfld.long 0x0 0. "ITC_MEN,Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses." "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled Please.." wgroup.long 0x200++0x3 line.long 0x0 "MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG1_CPY0,This register is a 128 byte block copy of the PSASIG1 register for DMA destination it is write only the result can be found in the PSASIG1 register." wgroup.long 0x280++0x3 line.long 0x0 "MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG2_CPY0,This register is a 128 byte block copy of the PSASIG2 register for DMA destination it is write only the result can be found in the PSASIG2 register." wgroup.long 0x300++0x3 line.long 0x0 "MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG3_CPY0,This register is a 128 byte block copy of the PSASIG3 register for DMA destination it is write only the result can be found in the PSASIG3 register." wgroup.long 0x380++0x3 line.long 0x0 "MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems." hexmask.long 0x0 0.--31. 1. "I0_PSASIG4_CPY0,This register is a 128 byte block copy of the PSASIG4 register for DMA destination it is write only the result can be found in the PSASIG4 register." tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "MCSPI" base ad:0x0 tree "MCSPI0_CFG" base ad:0x20100000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" group.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" newline bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" newline bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" newline bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" newline bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree "MCSPI1_CFG" base ad:0x20110000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" group.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" newline bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" newline bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" newline bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" newline bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree "MCSPI2_CFG" base ad:0x20120000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" group.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" newline bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" newline bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" newline bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" newline bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-MCU")) tree "MCU" base ad:0x0 tree "MCU_CBASS0_ERR" base ad:0x4720000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,The interrupt raw status register indicates if there is null interrupt regardless of interrupt enable" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,The interrupt status register is gated by the interrupt enable" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Only when this register is set. null access will cause interrupt to be generated." bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Setting this register disables the null interrupt generation" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,Writing to EOI Register indicates that current interrupt has been serviced which then allows next interrupt to be generated" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,End Of Interrupt Register" tree.end tree "MCU_DCC0" base ad:0x4C00000 group.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." group.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." group.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" group.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "MCU_DCC1" base ad:0x4C10000 group.long 0x0++0x3 line.long 0x0 "CFG_DCCGCTRL,Starts / stops the counters. Clears the error signal." hexmask.long.byte 0x0 12.--15. 1. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register. User privilege and debug mode (read): 0101 = the done signal is disabled others = the done signal is enabled Privilege.." hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC. User privilege and debug mode (read): 1010 = stop counting when counter0 and valid0 both reach zero 1011 = stop counting when counter1 reaches zero others = continuously.." newline hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. User privilege and debug mode (read): 0101 = the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101 = disable error signal generation others =.." hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc. User privilege and debug mode (read): 0101 = counters are stopped others = counters are running Privilege and debug mode (write): 0101 = stop counters and error-checking others = load the.." rgroup.long 0x4++0x3 line.long 0x0 "CFG_DCCREV,Specifies the module version." bitfld.long 0x0 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01. Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Reflects software-compatability. If there is no level of software compatability a unique func number is assigned; for compatible modules the same number is maintained. User privilege and debug mode (read): 0x0 Privilege and debug mode (write):.." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Incremented for releases due to spec changes or post-release design changes. Reset to 0 when either MAJOR or MINOR is incremented. User privilege and debug mode (read): 0x1 Privilege and debug mode (write): Writes have no effect." bitfld.long 0x0 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. User privilege and debug mode (read): 0x2 Privilege and debug mode (write): Writes have no effect." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software. User privilege and debug mode (read): 0x0 Privilege and debug mode (write): Writes have no effect." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. User privilege and debug mode (read): 0x4 Privilege and debug mode (write): Writes have no effect." group.long 0x8++0xF line.long 0x0 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0). User privilege and debug mode (read): Returns the current seed value for counter 0. Privilege and debug mode (write): Sets the current seed value for.." line.long 0x4 "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0. User privilege and debug mode (read): Returns the current seed value for VALID0. Privilege and debug mode (write): Sets the current seed.." line.long 0x8 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1). User privilege and debug mode (read): Returns the current seed value for counter 1. Privilege and debug mode (write): Sets the current seed value for.." line.long 0xC "CFG_DCCSTAT,Specifies the status of the DCC Module." bitfld.long 0xC 1. "DONEFLG,Indicates when single-shot mode is complete without error. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = single-shot mode is not done 1 = single-shot mode is done Privilege and debug mode (write): 0 = no.." "0: no effect,1: clear the done flag" bitfld.long 0xC 0. "ERRFLG,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. User privilege and debug mode (read): 0 = an error has not occurred 1 = an error has occurred Privilege and debug mode (write): 0 = no effect 1 = clear the.." "0: no effect,1: clear the error flag" rgroup.long 0x18++0xB line.long 0x0 "CFG_DCCCNT0,Value of the counter attached to clock source 0." hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. User privilege and debug mode (read): Returns the current value for counter 0. Privilege and debug mode (write): Writes have no effect." line.long 0x4 "CFG_DCCVALID0,Value of the valid counter attached to clock source 0." hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. User privilege and debug mode (read): Returns the current value for valid counter 0. Privilege and debug mode (write): writes have no effect." line.long 0x8 "CFG_DCCCNT1,Value of the counter attached to clock source 1." hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. User privilege and debug mode (read): Returns the current value for counter 1. Privilege and debug mode (write): writes have no effect." group.long 0x24++0xB line.long 0x0 "CFG_DCCCLKSRC1,Selects the clock source for counter 1." hexmask.long.byte 0x0 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 1. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x0 0.--4. 1. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature. User privilege and debug mode (read): Returns the current value of CLKSRC. Privilege and debug mode (write): Sets the value of CLKSRC." line.long 0x4 "CFG_DCCCLKSRC0,Selects the clock source for counter 0." hexmask.long.byte 0x4 12.--15. 1. "KEY,This field enables or disables clock source selection for counter 0. User privilege and debug mode (read): Returns the current value of the key. Privilege and debug mode (write): Sets the key value. Key values: 1010: The CLKSRC field selects the.." hexmask.long.byte 0x4 0.--3. 1. "CLKSRC0,This field specifies the clock source for counter 0. User privilege and debug mode (read): Returns the current value of CLKSRC0. Privilege and debug mode (write): Sets the value of CLKSRC0." line.long 0x8 "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC." hexmask.long.byte 0x8 8.--11. 1. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." hexmask.long.byte 0x8 4.--7. 1. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Source values:.." newline hexmask.long.byte 0x8 0.--3. 1. "CONT_ON_ERR,Continues to next window of comparison despite the error condition. User privilege and debug mode (read): Returns the current field value. Privilege and debug mode (write): Sets the value of field value. Enable values: 0101: Comparison and.." rgroup.long 0x30++0x3 line.long 0x0 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs." bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full. Indicates whether Count1 FIFO is full. User privilege and debug mode (read): 0: Count1 FIFO is not full 1: Count1 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not full,1: Count1 FIFO is full" bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full. Indicates whether Valid0 FIFO is full. User privilege and debug mode (read): 0: Valid0 FIFO is not full 1: Valid0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not full,1: Valid0 FIFO is full" newline bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full. Indicates whether Count0 FIFO is full. User privilege and debug mode (read): 0: Count0 FIFO is not full 1: Count0 FIFO is full. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not full,1: Count0 FIFO is full" bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty. Indicates whether Count1 FIFO is empty. User privilege and debug mode (read): 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty" newline bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty. Indicates whether Valid0 FIFO is empty. User privilege and debug mode (read): 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty" bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty. Indicates whether Count0 FIFO is empty. User privilege and debug mode (read): 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. Privilege and debug mode (write): Writes have no effect." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty" group.long 0x34++0x3 line.long 0x0 "CFG_DCCERRCNT,Counts number of errors since last clear." hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it." tree.end tree "MCU_GPIO0" base ad:0x4201000 rgroup.long 0x0++0x7 line.long 0x0 "MEM_pid,GPIO Periperal ID Register" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" line.long 0x4 "MEM_PCR,Peripheral Control Register" bitfld.long 0x4 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.long 0x4 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" group.long 0x8++0x3 line.long 0x0 "MEM_BINTEN,Bit Interrupt Enable Register" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." group.long 0x10++0xF line.long 0x0 "MEM_DIR01,Direction Register" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "MEM_OUT_DATA01,Output Drive State Register" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "MEM_SET_DATA01,Set Output Drive State Register" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "MEM_CLR_DATA01,Clear Output Drive State Register" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "MEM_IN_DATA01,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." group.long 0x24++0x23 line.long 0x0 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "MEM_INTSTAT01,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR23,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA23,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA23,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA23,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "MEM_IN_DATA23,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." group.long 0x4C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "MEM_INTSTAT23,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR45,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA45,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA45,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA45,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "MEM_IN_DATA45,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." group.long 0x74++0x23 line.long 0x0 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "MEM_INTSTAT45,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR67,Direction Register" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA67,Output Drive State Register" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA67,Set Output Drive State Register" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA67,Clear Output Drive State Register" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "MEM_IN_DATA67,Bank Status Register" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." group.long 0x9C++0x23 line.long 0x0 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "MEM_INTSTAT67,Bank Interrupt Status Register" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "MEM_DIR8,Direction Register" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "MEM_OUT_DATA8,Output Drive State Register" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "MEM_SET_DATA8,Set Output Drive State Register" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "MEM_CLR_DATA8,Clear Output Drive State Register" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "MEM_IN_DATA8,Bank Status Register" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." group.long 0xC4++0x13 line.long 0x0 "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register" hexmask.long.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." line.long 0x4 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register" hexmask.long.word 0x4 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." line.long 0x8 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register" hexmask.long.word 0x8 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." line.long 0xC "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register" hexmask.long.word 0xC 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." line.long 0x10 "MEM_INTSTAT8,Bank Interrupt Status Register" hexmask.long.word 0x10 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree "MCU_I2C0_CFG" base ad:0x4900000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" group.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end tree "MCU_MCAN0_CFG" base ad:0x4E08000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" group.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" group.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" group.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCU_MCAN0_ECC_AGGR" base ad:0x4701000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" group.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_MCAN0_MSGMEM_RAM" base ad:0x4E00000 group.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCU_MCAN0_SS" base ad:0x4E09000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" group.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" group.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree "MCU_MCAN1_CFG" base ad:0x4E18000 rgroup.long 0x0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" group.long 0x8++0x37 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point" newline hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection" rbitfld.long 0x8 7. "RX,Receive Pin" "0,1" bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM" hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration" bitfld.long 0x10 15. "NISO,Non ISO Operation. 0= CAN FD frame format according to ISO 11898-1:2015. 1= CAN FD frame format according to Bosch CAN FD Specification 1.0" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.." bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1" bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x10 7. "TEST,Test Mode enable" "0,1" bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1" newline bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x10 2. "ASM,Restricted Operation Mode" "0,1" newline bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0x10 0. "INIT,Initialization" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing" hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector" hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter" hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter" hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved00,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved11,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved22,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved33,Reserved field" rgroup.long 0x40++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" group.long 0x48++0x4B line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved44,Reserved field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" newline bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable" bitfld.long 0xC 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)" bitfld.long 0x10 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved55,Reserved field" line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved66,Reserved field" line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved77,Reserved field" line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved88,Reserved field" line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved99,Reserved field" line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1010,Reserved field" line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1111,Reserved field" line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1212,Reserved field" line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x3C 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA,Filter List Standard Start Address" line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x40 16.--22. 1. "LSE,List Size Extended" hexmask.long.word 0x40 2.--15. 1. "FLESA,Filter List Extended Start Address" line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1313,Reserved field" line.long 0x48 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x98++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT1,NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x0 31. "ND31,New Data" "0,1" bitfld.long 0x0 30. "ND30,New Data" "0,1" bitfld.long 0x0 29. "ND29,New Data" "0,1" newline bitfld.long 0x0 28. "ND28,New Data" "0,1" bitfld.long 0x0 27. "ND27,New Data" "0,1" bitfld.long 0x0 26. "ND26,New Data" "0,1" newline bitfld.long 0x0 25. "ND25,New Data" "0,1" bitfld.long 0x0 24. "ND24,New Data" "0,1" bitfld.long 0x0 23. "ND23,New Data" "0,1" newline bitfld.long 0x0 22. "ND22,New Data" "0,1" bitfld.long 0x0 21. "ND21,New Data" "0,1" bitfld.long 0x0 20. "ND20,New Data" "0,1" newline bitfld.long 0x0 19. "ND19,New Data" "0,1" bitfld.long 0x0 18. "ND18,New Data" "0,1" bitfld.long 0x0 17. "ND17,New Data" "0,1" newline bitfld.long 0x0 16. "ND16,New Data" "0,1" bitfld.long 0x0 15. "ND15,New Data" "0,1" bitfld.long 0x0 14. "ND14,New Data" "0,1" newline bitfld.long 0x0 13. "ND13,New Data" "0,1" bitfld.long 0x0 12. "ND12,New Data" "0,1" bitfld.long 0x0 11. "ND11,New Data" "0,1" newline bitfld.long 0x0 10. "ND10,New Data" "0,1" bitfld.long 0x0 9. "ND9,New Data" "0,1" bitfld.long 0x0 8. "ND8,New Data" "0,1" newline bitfld.long 0x0 7. "ND7,New Data" "0,1" bitfld.long 0x0 6. "ND6,New Data" "0,1" bitfld.long 0x0 5. "ND5,New Data" "0,1" newline bitfld.long 0x0 4. "ND4,New Data" "0,1" bitfld.long 0x0 3. "ND3,New Data" "0,1" bitfld.long 0x0 2. "ND2,New Data" "0,1" newline bitfld.long 0x0 1. "ND1,New Data" "0,1" bitfld.long 0x0 0. "ND0,New Data" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT2,NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x4 31. "ND63,New Data" "0,1" bitfld.long 0x4 30. "ND62,New Data" "0,1" bitfld.long 0x4 29. "ND61,New Data" "0,1" newline bitfld.long 0x4 28. "ND60,New Data" "0,1" bitfld.long 0x4 27. "ND59,New Data" "0,1" bitfld.long 0x4 26. "ND58,New Data" "0,1" newline bitfld.long 0x4 25. "ND57,New Data" "0,1" bitfld.long 0x4 24. "ND56,New Data" "0,1" bitfld.long 0x4 23. "ND55,New Data" "0,1" newline bitfld.long 0x4 22. "ND54,New Data" "0,1" bitfld.long 0x4 21. "ND53,New Data" "0,1" bitfld.long 0x4 20. "ND52,New Data" "0,1" newline bitfld.long 0x4 19. "ND51,New Data" "0,1" bitfld.long 0x4 18. "ND50,New Data" "0,1" bitfld.long 0x4 17. "ND49,New Data" "0,1" newline bitfld.long 0x4 16. "ND48,New Data" "0,1" bitfld.long 0x4 15. "ND47,New Data" "0,1" bitfld.long 0x4 14. "ND46,New Data" "0,1" newline bitfld.long 0x4 13. "ND45,New Data" "0,1" bitfld.long 0x4 12. "ND44,New Data" "0,1" bitfld.long 0x4 11. "ND43,New Data" "0,1" newline bitfld.long 0x4 10. "ND42,New Data" "0,1" bitfld.long 0x4 9. "ND41,New Data" "0,1" bitfld.long 0x4 8. "ND40,New Data" "0,1" newline bitfld.long 0x4 7. "ND39,New Data" "0,1" bitfld.long 0x4 6. "ND38,New Data" "0,1" bitfld.long 0x4 5. "ND37,New Data" "0,1" newline bitfld.long 0x4 4. "ND36,New Data" "0,1" bitfld.long 0x4 3. "ND35,New Data" "0,1" bitfld.long 0x4 2. "ND34,New Data" "0,1" newline bitfld.long 0x4 1. "ND33,New Data" "0,1" bitfld.long 0x4 0. "ND32,New Data" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0xA8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x8 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request" bitfld.long 0x0 31. "TRP31,Transmission Request Pending" "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending" "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending" "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending" "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending" "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending" "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending" "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending" "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending" "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending" "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending" "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending" "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending" "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending" "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending" "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending" "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending" "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending" "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending" "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending" "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending" "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending" "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending" "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending" "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending" "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending" "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending" "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending" "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending" "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending" "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending" "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending" "0,1" group.long 0xD0++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests" bitfld.long 0x0 31. "AR31,Add request" "0,1" bitfld.long 0x0 30. "AR30,Add request" "0,1" bitfld.long 0x0 29. "AR29,Add request" "0,1" newline bitfld.long 0x0 28. "AR28,Add request" "0,1" bitfld.long 0x0 27. "AR27,Add request" "0,1" bitfld.long 0x0 26. "AR26,Add request" "0,1" newline bitfld.long 0x0 25. "AR25,Add request" "0,1" bitfld.long 0x0 24. "AR24,Add request" "0,1" bitfld.long 0x0 23. "AR23,Add request" "0,1" newline bitfld.long 0x0 22. "AR22,Add request" "0,1" bitfld.long 0x0 21. "AR21,Add request" "0,1" bitfld.long 0x0 20. "AR20,Add request" "0,1" newline bitfld.long 0x0 19. "AR19,Add request" "0,1" bitfld.long 0x0 18. "AR18,Add request" "0,1" bitfld.long 0x0 17. "AR17,Add request" "0,1" newline bitfld.long 0x0 16. "AR16,Add request" "0,1" bitfld.long 0x0 15. "AR15,Add request" "0,1" bitfld.long 0x0 14. "AR14,Add request" "0,1" newline bitfld.long 0x0 13. "AR13,Add request" "0,1" bitfld.long 0x0 12. "AR12,Add request" "0,1" bitfld.long 0x0 11. "AR11,Add request" "0,1" newline bitfld.long 0x0 10. "AR10,Add request" "0,1" bitfld.long 0x0 9. "AR9,Add request" "0,1" bitfld.long 0x0 8. "AR8,Add request" "0,1" newline bitfld.long 0x0 7. "AR7,Add request" "0,1" bitfld.long 0x0 6. "AR6,Add request" "0,1" bitfld.long 0x0 5. "AR5,Add request" "0,1" newline bitfld.long 0x0 4. "AR4,Add request" "0,1" bitfld.long 0x0 3. "AR3,Add request" "0,1" bitfld.long 0x0 2. "AR2,Add request" "0,1" newline bitfld.long 0x0 1. "AR1,Add request" "0,1" bitfld.long 0x0 0. "AR0,Add request" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions" bitfld.long 0x4 31. "CR31,Cancellation Request" "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request" "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request" "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request" "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request" "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request" "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request" "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request" "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request" "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request" "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request" "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request" "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request" "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request" "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request" "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request" "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request" "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request" "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request" "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request" "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request" "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request" "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request" "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request" "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request" "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request" "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request" "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request" "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request" "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request" "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request" "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request" "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared" bitfld.long 0x0 31. "TO31,Transmission Occurred" "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred" "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred" "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred" "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred" "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred" "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred" "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred" "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred" "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred" "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred" "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred" "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred" "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred" "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred" "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred" "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred" "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred" "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred" "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred" "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred" "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred" "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred" "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred" "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred" "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred" "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred" "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred" "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred" "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred" "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred" "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4 31. "CF31,Cancellation Finished" "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished" "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished" "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished" "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished" "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished" "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished" "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished" "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished" "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished" "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished" "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished" "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished" "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished" "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished" "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished" "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished" "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished" "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished" "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished" "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished" "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished" "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished" "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished" "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished" "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished" "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished" "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished" "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished" "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished" "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished" "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished" "0,1" group.long 0xE0++0x13 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable" "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable" "0,1" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1414,Reserved Field" line.long 0xC "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1515,Reserved Field" line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x3 line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level" group.long 0xF8++0xB line.long 0x0 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" line.long 0x4 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved1616,Reserved Field" line.long 0x8 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field" tree.end tree "MCU_MCAN1_ECC_AGGR" base ad:0x4702000 rgroup.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x4 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1" group.long 0x200++0xF line.long 0x0 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_MCAN1_MSGMEM_RAM" base ad:0x4E10000 group.long 0x0++0x3 line.long 0x0 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MCU_MCAN1_SS" base ad:0x4E19000 rgroup.long 0x0++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS" bitfld.long 0x0 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0xC++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits." "0,1" group.long 0x10++0xB line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status. Write '1' to set interrupt bits." bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status." "0,1" line.long 0x4 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits." "0,1" line.long 0x8 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt" group.long 0x24++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1" rgroup.long 0x28++0x3 line.long 0x0 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt" tree.end tree "MCU_MCSPI0_CFG" base ad:0x4B00000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" group.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" newline bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" newline bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" newline bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" newline bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree "MCU_MCSPI1_CFG" base ad:0x4B10000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_HL_REV,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e. typically the module's HDL generics (if any)." hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" group.long 0x10++0x3 line.long 0x0 "CFG_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "CFG_REVISION,This register contains the hard coded RTL revision number." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_13,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x2B line.long 0x0 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface." hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED_14,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" line.long 0x4 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" rbitfld.long 0x4 0. "RESETDONE,Internal Reset Monitoring" "0,1" line.long 0x8 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" hexmask.long.word 0x8 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x8 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" bitfld.long 0x8 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" newline bitfld.long 0x8 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x8 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" bitfld.long 0x8 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" bitfld.long 0x8 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" newline bitfld.long 0x8 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" bitfld.long 0x8 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x8 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x8 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x8 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x8 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x8 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x8 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" bitfld.long 0x8 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0xC "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis." hexmask.long.word 0xC 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0xC 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0xC 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" bitfld.long 0xC 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0xC 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" newline bitfld.long 0xC 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" bitfld.long 0xC 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" bitfld.long 0xC 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" newline bitfld.long 0xC 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" bitfld.long 0xC 7. "RESERVED,Reads return 0" "0,1" bitfld.long 0xC 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0xC 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0xC 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" bitfld.long 0xC 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis." hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0" bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x14 11. "SSB,Set status bit" "0,1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" newline bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface." hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1" newline bitfld.long 0x18 2. "MS,Master/ Slave" "0,1" bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x1C 18. "IS,Input Select" "0,1" bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x1C 7.--11. 1. "WL,SPI word length" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x1C 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1" line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x24 0. "EN,Channel Enable" "0,1" line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0x28 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0xF line.long 0x0 "CFG_CH1CONF,This register is dedicated to the configuration of the channel." bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0xF line.long 0x0 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0xF line.long 0x0 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" line.long 0x4 "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" hexmask.long 0x4 7.--31. 1. "RESERVED,Read returns 0" rbitfld.long 0x4 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1" rbitfld.long 0x4 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1" rbitfld.long 0x4 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1" rbitfld.long 0x4 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1" newline rbitfld.long 0x4 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" rbitfld.long 0x4 1. "TXS,Channel i Transmitter Register Status" "0,1" rbitfld.long 0x4 0. "RXS,Channel i Receiver Register Status" "0,1" line.long 0x8 "CFG_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x8 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x8 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x8 0. "EN,Channel Enable" "0,1" line.long 0xC "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is." hexmask.long 0xC 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is." hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." rgroup.long 0x1A0++0x3 line.long 0x0 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled." hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to 1 and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to.." tree.end tree "MCU_MSRAM_256K0_ECC_AGGR_REGS" base ad:0x4705000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_REGSREGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x4 1. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_REGSREGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x4 1. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_REGSREGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_REGSREGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_REGSREGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_MSRAM_256K1_ECC_AGGR_REGS" base ad:0x4706000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_REGSREGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x4 1. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_REGSREGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 2. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1" bitfld.long 0x4 1. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 2. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1" bitfld.long 0x0 1. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_REGSREGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_REGSREGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_REGSREGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MCU_PBIST0" base ad:0x4F00000 group.long 0x0++0x7F line.long 0x0 "MEM_RF0L" hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L" hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L" hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L" hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L" hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L" hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L" hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L" hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L" hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L" hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L" hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L" hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L" hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L" hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L" hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L" hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U" hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U" hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U" hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U" hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U" hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U" hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U" hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U" hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U" hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U" hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U" hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U" hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U" hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U" hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U" hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U" hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" group.long 0x100++0x27 line.long 0x0 "MEM_A0" hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1" hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2" hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3" hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0" hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1" hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2" hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3" hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D" hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E" hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" group.long 0x130++0x3F line.long 0x0 "MEM_CA0" hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1" hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2" hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3" hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0" hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1" hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2" hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3" hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0" hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1" hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2" hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3" hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT" hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR" hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS" hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR" bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" group.quad 0x170++0x7 line.quad 0x0 "MEM_SCR" hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" group.long 0x178++0x13 line.long 0x0 "MEM_CSR" hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY" hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT" bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID" hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER" bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF" bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC" hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA" hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0" hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1" hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE" bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ" bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS" bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" group.long 0x1C0++0x7 line.long 0x0 "MEM_ROM" bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO" hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" group.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO" hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree "MCU_RTI0_CFG" base ad:0x4880000 group.long 0x0++0x1B line.long 0x0 "CFG_GCTRL" hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL" bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL" bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL" bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0" hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0" hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." group.long 0x30++0xB line.long 0x0 "CFG_FRC1" hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1" hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." group.long 0x50++0x27 line.long 0x0 "CFG_COMP0" hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1" hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2" hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2" hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3" hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP" hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP" hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." group.long 0x80++0xB line.long 0x0 "CFG_SETINT" bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT" bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG" bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" group.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL" hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD" hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS" bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY" hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR" hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." group.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL" hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL" hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE" hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR" hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR" hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR" hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR" hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree "MCU_TIMEOUT0_CFG" base ad:0x4301000 rgroup.long 0x0++0xB line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket." hexmask.long.byte 0x4 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard" hexmask.long.byte 0x4 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard" line.long 0x8 "CFG_INFO,The Info Register contains information about the current state of the gasket." hexmask.long.word 0x8 16.--24. 1. "CUR_WRITES,Current number of occupied slots in the write scoreboard" hexmask.long.word 0x8 0.--8. 1. "CUR_READS,Current number of occupied slots in the read scoreboard" group.long 0xC++0xF line.long 0x0 "CFG_ENABLE,The Enable Register contains the gasket enable." hexmask.long.byte 0x0 0.--3. 1. "EN,Enable. 0 - Disabled All other values - Enabled." line.long 0x4 "CFG_FLUSH,The Flush Register contains software flush control." rbitfld.long 0x4 31. "EXT_FL,The value of external flush input" "0,1" hexmask.long.byte 0x4 0.--3. 1. "FL,SW control and indicator for whether the gasket is in flush mode. 4'b1111 - Flush mode All other values - Normal mode." line.long 0x8 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions." hexmask.long 0x8 0.--29. 1. "TO,The number of cycles in each eon. Each transaction can be outstanding for 2-3 eons before it times out." line.long 0xC "CFG_TIMER,The Timer Register contains the current value for free-running timer." rbitfld.long 0xC 30.--31. "EON,Current eon" "0,1,2,3" hexmask.long 0xC 0.--29. 1. "CNTR,Current value of the free-running timer. It increments once per clock cycle when the gasket is enabled." group.long 0x20++0x17 line.long 0x0 "CFG_ERR_RAW,This register contains the masked interrupt bits" bitfld.long 0x0 2. "CMD,Raw Command Error Interrupt" "0,1" bitfld.long 0x0 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1" bitfld.long 0x0 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1" line.long 0x4 "CFG_ERR,This register contains the masked interrupt bits" bitfld.long 0x4 2. "CMD,Masked Command Error Interrupt" "0,1" bitfld.long 0x4 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1" bitfld.long 0x4 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1" line.long 0x8 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits" bitfld.long 0x8 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1" bitfld.long 0x8 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1" bitfld.long 0x8 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1" line.long 0xC "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits" bitfld.long 0xC 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1" bitfld.long 0xC 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1" line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts" bitfld.long 0x10 0.--1. "CNT,This field contains information about how many transactions have timed out since the last one was serviced. Writing to this register decrements the contents by the value written. The value saturates at 3." "0,1,2,3" line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts" bitfld.long 0x14 0.--1. "CNT,This field contains information about how many unexpected responses have been received since the last one was serviced. Writing to this register decrements the contents by the value written. The value saturates at 3." "0,1,2,3" rgroup.long 0x38++0x13 line.long 0x0 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x0 16.--27. 1. "RID,Route ID Indicator" hexmask.long.byte 0x0 8.--11. 1. "OID,Order ID Indicator" bitfld.long 0x0 2. "DIR,Direction Indicator. 0-write. 1-read." "0,1" bitfld.long 0x0 1. "TYP,Error Type Indicator. 0-transaction timeout. 1-unexpected response." "0,1" bitfld.long 0x0 0. "VAL,Valid Indicator. If this field is a 1 then the contents of this and the below registers is considered valid: it contains the information about the transaction that was captured. If this field is 0 then this and the other listed registers are not.." "0,1" line.long 0x4 "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x4 16.--27. 1. "TAG,Command Tag Indicator consisting of replacement CID for timeout error or SID/RID for unexpected response error." hexmask.long.word 0x4 0.--11. 1. "CID,Command ID Indicator. This is the original command id and is only valid on timeout error." line.long 0x8 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt" hexmask.long.word 0x8 16.--25. 1. "CBYTECNT,Current Bytecnt. For timeout error this is the number of bytes that were not returned." hexmask.long.word 0x8 0.--9. 1. "OBYTECNT,Original Bytecnt. This field represents the transaction cbytecnt of the original command." line.long 0xC "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt" hexmask.long 0xC 0.--31. 1. "ADDR,Upper bits of the address for the captured transaction. This is field is only valid for timeout error." line.long 0x10 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt" hexmask.long 0x10 0.--31. 1. "ADDR,Lower bits of the address for the captured transaction. This is field is only valid for timeout error. If the address width is less than 32 then the bits above the address range will be read as 0." tree.end tree "MCU_TIMER0_CFG" base ad:0x4800000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" group.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" group.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" group.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" group.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "MCU_TIMER1_CFG" base ad:0x4810000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" group.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" group.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" group.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" group.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "MCU_TIMER2_CFG" base ad:0x4820000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" group.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" group.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" group.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" group.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "MCU_TIMER3_CFG" base ad:0x4830000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" group.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" group.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" group.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" group.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "MCU_UART0" base ad:0x4A00000 group.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "NOT_USED1" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" newline bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" group.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE" newline bitfld.long 0x0 0. "IT_PENDING" "0,1" group.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" newline bitfld.long 0x0 3. "PARITY_EN" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR" "0,1" newline bitfld.long 0x4 5. "XON_EN" "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN" "0,1" newline bitfld.long 0x4 3. "CD_STS_CH" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH" "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR" "0,1" group.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL" "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE" "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG" "0,1" newline bitfld.long 0x0 3. "ABORT" "0,1" newline bitfld.long 0x0 2. "CRC" "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "RX_FIFO_STS" "0,1" newline bitfld.long 0x0 6. "TX_SR_E" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E" "0,1" newline bitfld.long 0x0 4. "RX_BI" "0,1" newline bitfld.long 0x0 3. "RX_FE" "0,1" newline bitfld.long 0x0 2. "RX_PE" "0,1" newline bitfld.long 0x0 1. "RX_OE" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" group.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT" "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 5.--7. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR" "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR" "0,1" newline bitfld.long 0x0 0. "RESERVED0" "0,1" group.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." group.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "RX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 5. "DSR_IT" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE" "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL" "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST" "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL" "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY" "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL" line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL" group.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS" "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1" newline rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1" newline rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "MCU_CBASS0_ISC" base ad:0x45818000 group.long 0x0++0x3 line.long 0x0 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_uls_mcu_0.cpu0_rmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x10++0x13 line.long 0x0 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_uls_mcu_0.cpu0_rmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x30++0x13 line.long 0x0 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_uls_mcu_0.cpu0_rmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x50++0x13 line.long 0x0 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_uls_mcu_0.cpu0_rmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x70++0x13 line.long 0x0 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_rmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_uls_mcu_0.cpu0_rmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x400++0x3 line.long 0x0 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_uls_mcu_0.cpu0_wmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x410++0x13 line.long 0x0 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_uls_mcu_0.cpu0_wmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x430++0x13 line.long 0x0 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_uls_mcu_0.cpu0_wmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x450++0x13 line.long 0x0 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_uls_mcu_0.cpu0_wmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x470++0x13 line.long 0x0 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_wmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_uls_mcu_0.cpu0_wmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x800++0x3 line.long 0x0 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_uls_mcu_0.cpu0_pmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x810++0x13 line.long 0x0 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_uls_mcu_0.cpu0_pmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x830++0x13 line.long 0x0 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_uls_mcu_0.cpu0_pmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x850++0x13 line.long 0x0 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_uls_mcu_0.cpu0_pmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x870++0x13 line.long 0x0 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_uls_mcu_0.cpu0_pmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_uls_mcu_0.cpu0_pmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "MCU_CBASS0_GLB" base ad:0x45B02000 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "MCU_CBASS0_QOS" base ad:0x45D18000 group.long 0x100++0x3 line.long 0x0 "QOS_REGS_Ipulsar_uls_mcu_0_cpu0_rmst_map0,The Map Register defines the fields for the master Ipulsar_uls_mcu_0.cpu0_rmst per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x500++0x3 line.long 0x0 "QOS_REGS_Ipulsar_uls_mcu_0_cpu0_wmst_map0,The Map Register defines the fields for the master Ipulsar_uls_mcu_0.cpu0_wmst per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x900++0x3 line.long 0x0 "QOS_REGS_Ipulsar_uls_mcu_0_cpu0_pmst_map0,The Map Register defines the fields for the master Ipulsar_uls_mcu_0.cpu0_pmst per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "MCU_MSRAM_256K0_RAM" base ad:0x79100000 group.long 0x0++0x3 line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "MCU_MSRAM_256K1_RAM" base ad:0x79140000 group.long 0x0++0x3 line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end endif tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "MMCSD" base ad:0x0 tree "MMCSD0_CTL_CFG" base ad:0xFA10000 group.word 0x0++0xF line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_lo,This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." hexmask.word 0x0 0.--15. 1. "SDMA_ADDRESS,When Host Version 4 Enable is set to 0 in the Host Control 2 register DMA uses this register as system address in only 32-bit addressing mode. Auto CMD23 cannot be used with SDMA. When Host Version 4 Enable is set to 1 SDMA uses ADMA System.." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_hi,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." hexmask.word 0x2 0.--15. 1. "SDMA_ADDRESS,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_block_size,This register is used to configure the number of bytes in a data block" bitfld.word 0x4 12.--14. "SDMA_BUF_SIZE,To perform long DMA transfer System Address register shall be updated at every system boundary during DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at the every boundary.." "0,1,2,3,4,5,6,7" newline hexmask.word 0x4 0.--11. 1. "XFER_BLK_SIZE,This field specifies the block size for block data transfers for CMD17 CMD18 CMD24 CMD25 and CMD53. It can be accessed only if no transaction is executing [i.e after a transaction has stopped]. Read operations during transfer return an.." line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_block_count,This register is used to configure the number of data blocks" hexmask.word 0x6 0.--15. 1. "XFER_BLK_CNT,Host Controller Version 4.10 extends block count to 32-bit [Refer to Section 1.15].Selection of either 16-bit Block Count register or 32-bit Block Count register is defined as follows: [1] If Host Version 4 Enable in the Host Control 2.." line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_lo,This register contains Lower bits of SD Command Argument" hexmask.word 0x8 0.--15. 1. "CMD_ARG1,The SD Command Argument is specified as bit23-8 of Command-Format." line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_hi,This register contains higher bits of SD Command Argument" hexmask.word 0xA 0.--15. 1. "CMD_ARG1,The SD Command Argument is specified as bit39-24 of Command-Format." line.word 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_transfer_mode,This register is used to control the operations of data transfers" bitfld.word 0xC 8. "RESP_INTR_DIS,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0 and waits Command Complete.." "0,1" newline bitfld.word 0xC 7. "RESP_ERR_CHK_ENA,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked.If Host Driver checks response error this bit is set to 0 and Response Interrupt.." "0,1" newline bitfld.word 0xC 6. "RESP_TYPE,When response error check is enabled this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO." "0,1" newline bitfld.word 0xC 5. "MULTI_BLK_SEL,This bit enables multiple block data transfers." "0,1" newline bitfld.word 0xC 4. "DATA_XFER_DIR,This bit defines the direction of data transfers." "0,1" newline bitfld.word 0xC 2.--3. "AUTO_CMD_ENA,There are three methods to stop Multiple-block read and write operation. [1] Auto CMD12 Enable: Multiple-block read and write commands for memory require CMD12 to stop the operation. When this field is set to 01b the Host.." "0,1,2,3" newline bitfld.word 0xC 1. "BLK_CNT_ENA,This bit is used to enable the Block count register which is only relevant for multiple block transfers. When this bit is 0 the Block Count register is disabled which is useful in executing an infinite transfer." "0,1" newline bitfld.word 0xC 0. "DMA_ENA,DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1 a DMA operation shall begin when the HD writes to the upper byte of Command register [00Fh]." "0,1" line.word 0xE "SDHC_WRAP__CTL_CFG__CTLCFG_command,This register is used to program the Command for host controller" hexmask.word.byte 0xE 8.--13. 1. "CMD_INDEX,This bit shall be set to the command number [CMD0-63 ACMD0-63]." newline bitfld.word 0xE 6.--7. "CMD_TYPE,There are three types of special commands. Suspend Resume andAbort. These bits shall bet set to 00b for all other commands. Suspend Command: If the Suspend command succeeds the HC shall assume the SD Bus has been released and that it is.." "0,1,2,3" newline bitfld.word 0xE 5. "DATA_PRESENT,This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. If is set to 0 for the following: 1. Commands using only CMD line [ex. CMD52]. 2. Commands with no data transferbut using busy.." "0,1" newline bitfld.word 0xE 4. "CMD_INDEX_CHK_ENA,If this bit is set to 1 the HC shall check the index field in the response to see if it has the same value as the command index. If it is not it is reported as a Command Index Error. If this bit is set to 0 the Index field is not.." "0,1" newline bitfld.word 0xE 3. "CMD_CRC_CHK_ENA,If this bit is set to 1 the HC shall check the CRC field in the response. If an error is detected it is reported as a Command CRC Error. If this bit is set to 0 the CRC field is not checked." "0,1" newline bitfld.word 0xE 2. "SUB_CMD,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17]. When issuing a main com-mand this bit is set to 0 and when issuing a sub command this bit is set to 1. Setting of this bit is checked.." "0,1" newline bitfld.word 0xE 0.--1. "RESP_TYPE_SEL,Response Type Select." "0,1,2,3" rgroup.word 0x10++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_response,This register is used to store responses from SD Cards" hexmask.word 0x0 0.--15. 1. "CMD_RESP,R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." group.long 0x20++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_data_port,This register is used to access internal buffer" hexmask.long 0x0 0.--31. 1. "BUF_RD_DATA,The Host Controller Buffer can be accessed through this 32-bit Data Port Register." rgroup.long 0x24++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_presentstate,The Host Driver can get status of the Host Controller from this 32-bit read-only register" bitfld.long 0x0 31. "UHS2_IF_DETECTION,This status indicates whether a card supports UHS-II IF. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 regis-ter. UHS-II interface initialization is activated by setting SD Clock Enable in the.." "0,1" newline bitfld.long 0x0 30. "UHS2_IF_LANE_SYNC,This status indicates whether lane is synchronized in UHS-II mode. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On detecting UHS-II Interface [D31=1] Host Controller provides SYN.." "0,1" newline bitfld.long 0x0 29. "UHS2_DORMANT,This status indicates whether UHS-II Ianes enterDormant state. This function is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On issuing GO_DORMAT_STATE com-mand Go Dormant Command [111b]; is set to Command.." "0,1" newline bitfld.long 0x0 28. "SUB_COMMAND_STS,The Command register and Response register are commonly used for main command and sub command. This status is used to distinguish which response error statuses main command or sub command indicated in the Error Interrupt Status.." "0,1" newline bitfld.long 0x0 27. "CMD_NOT_ISS_BY_ERR,Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error. [Equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in the Auto CMD Error.." "0,1" newline bitfld.long 0x0 24. "SDIF_CMDIN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 23. "SDIF_DAT3IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[3]." "0,1" newline bitfld.long 0x0 22. "SDIF_DAT2IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[2]." "0,1" newline bitfld.long 0x0 21. "SDIF_DAT1IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[1]." "0,1" newline bitfld.long 0x0 20. "SDIF_DAT0IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[0]." "0,1" newline bitfld.long 0x0 19. "WRITE_PROTECT,The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin." "0,1" newline bitfld.long 0x0 18. "CARD_DETECT,This bit reflects the inverse value of the SDCD# pin. '0' No Card present [SDCD# = 1] '1' Card present [SDCD# = 0]" "0,1" newline bitfld.long 0x0 17. "CARD_STATE_STABLE,This bit is used for testing. If it is 0 the Card Detect Pin Level is not stable. If this bit is set to 1 it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this.." "0,1" newline bitfld.long 0x0 16. "CARD_INSERTED,This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt.." "0,1" newline bitfld.long 0x0 11. "BUF_RD_ENA,This status is used for non-DMA read transfers.This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1 readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the.." "0,1" newline bitfld.long 0x0 10. "BUF_WR_ENA,This status is used for non-DMA write transfers.This read only flag indicates if space is available for write data. If this bit is 1 data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written.." "0,1" newline bitfld.long 0x0 9. "RD_XFER_ACTIVE,This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: After the end bit of the read command. When writing a 1 to continue Request in the Block.." "0,1" newline bitfld.long 0x0 8. "WR_XFER_ACTIVE,This status indicates a write transfer is active. If this bit is 0 it means no valid write data exists in the HC. This bit is set in either of the following cases: After the end bit of the write command. When writing a.." "0,1" newline bitfld.long 0x0 7. "SDIF_DAT7IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 6. "SDIF_DAT6IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 5. "SDIF_DAT5IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 4. "SDIF_DAT4IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 3. "RETUNING_REQ,Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is.." "0,1" newline bitfld.long 0x0 2. "DATA_LINE_ACTIVE,This bit indicates whether one of the DAT line on SD bus is in use." "0,1" newline bitfld.long 0x0 1. "INHIBIT_DAT,This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0 it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit [DAT] [ex. R1b R5b.." "0,1" newline bitfld.long 0x0 0. "INHIBIT_CMD,SD Mode If this bit is 0 it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register [00Fh] is written. This bit is cleared when the command response is.." "0,1" group.byte 0x28++0x3 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control1,This register is used to program DMA modes. LED Control. Data Transfer Width. High Speed Enable. Card detect test level and signal selection" bitfld.byte 0x0 7. "CD_SIG_SEL,This bit selects source for card detection. '0' SDCD# is selected [for normal use] '1' The card detect test level is selected" "0,1" newline bitfld.byte 0x0 6. "CD_TEST_LEVEL,This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. Generates [card ins or card removal] interrupt when the normal int sts enable bit is set. '0' No Card '1' Card Inserted" "0,1" newline bitfld.byte 0x0 5. "EXT_DATA_WIDTH,This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register. If a device supports 8-bit bus mode this bit may be set to 1. If this bit.." "0,1" newline bitfld.byte 0x0 3.--4. "DMA_SELECT,This field is used to select DMA type. The Host Driver shall check support of DMA modes by referring the Capabilities register. Selected DMA is enabled by DMA Enable of the Transfer Mode register in SD mode and DMA Enable of UHS-II Transfer.." "0,1,2,3" newline bitfld.byte 0x0 2. "HIGH_SPEED_ENA,This bit is optional. Before setting this bit the HD shall check the High Speed Support in the capabilities register. If this bit is set to 0 [default] the HC outputs CMD line and DAT lines at the falling edge of the SD clock [up to.." "0,1" newline bitfld.byte 0x0 1. "DATA_WIDTH,This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. This bit is not effective in UHS-II mode." "0,1" newline bitfld.byte 0x0 0. "LED_CONTROL,This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands this bit can be set during all transactions. It is not necessary to change for each.." "0,1" line.byte 0x1 "SDHC_WRAP__CTL_CFG__CTLCFG_power_control,This register is used to program the SD Bus power and voltage level" bitfld.byte 0x1 5.--7. "UHS2_VOLTAGE,This field determines supply voltage range to VDD2. This field can be set to 101b if 1.8V VDD2 Support in the Capabilities register is set to 1. '000' VDD2 Not supported '001'- '011' Reserved '100' Reserved for 1.2V.." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x1 4. "UHS2_POWER,Setting this bit enables providing VDD2. '0' Power Off '1' Power On" "0,1" newline bitfld.byte 0x1 1.--3. "SD_BUS_VOLTAGE,By setting these bits the HD selects the voltage level for the SD card. Before setting this register the HD shall check the voltage support bits in the capabilities register. If an unsupported voltage is selected the Host System shall.." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x1 0. "SD_BUS_POWER,Before setting this bit the SD host driver shall set SD Bus Voltage Select. If the HC detects the No Card State this bit shall be cleared. If this bit is cleared the Host Control-ler should immediately stop driving CMD and DAT[3:0].." "0,1" line.byte 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_block_gap_control,This register is used to program the block gap request. read wait control and interrupt at block gap" bitfld.byte 0x2 7. "BOOT_ACK_ENA,To check for the boot acknowledge in boot operation." "0,1" newline bitfld.byte 0x2 6. "ALT_BOOT_MODE,To start boot code access in alternative mode." "0,1" newline bitfld.byte 0x2 5. "BOOT_ENABLE,To start boot code access." "0,1" newline bitfld.byte 0x2 4. "SPI_MODE,SPI mode enable bit." "0,1" newline bitfld.byte 0x2 3. "INTRPT_AT_BLK_GAP,This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt.." "0,1" newline bitfld.byte 0x2 2. "RDWAIT_CTRL,The read wait function is optional for SDIO cards. If the card supports read wait set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data which.." "0,1" newline bitfld.byte 0x2 1. "CONTINUE,This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap set Stop At block Gap Request to 0 and set this bit to restart the transfer. The Host Controller automatically.." "0,1" newline bitfld.byte 0x2 0. "STOP_AT_BLK_GAP,This bit is used to stop executing a transaction at the next block gap for non- DMA SDMA and ADMA transfers. Until the transfer complete is set to 1 indicating a transfer completion the HD shall leave this bit set to 1. Clearing both the.." "0,1" line.byte 0x3 "SDHC_WRAP__CTL_CFG__CTLCFG_wakeup_control,This register is used to program the wakeup functionality" bitfld.byte 0x3 2. "CARD_REMOVAL,This bit enables wakeup event via Card removal assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit." "0,1" newline bitfld.byte 0x3 1. "CARD_INSERTION,This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit." "0,1" newline bitfld.byte 0x3 0. "CARD_INTERRUPT,This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status register.This bit can be set to 1 if FN_WUS [Wake Up Support] in CIS is set to 1." "0,1" group.word 0x2C++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_clock_control,This register is used to program the Clock frequency select. generator select. Clock enable. Internal Clock state fields" hexmask.word.byte 0x0 8.--15. 1. "SDCLK_FRQSEL,This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register. Only the following.." newline bitfld.word 0x0 6.--7. "SDCLK_FRQSEL_UPBITS,Bit 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select." "0,1,2,3" newline bitfld.word 0x0 5. "CLKGEN_SEL,This bit is used to select the clock generator mode in SDCLK Frequency Select. If the Programmable Clock Mode is supported [non-zero value is set to Clock Multiplier in the Capabilities register] this bit attribute is RW and if not.." "0,1" newline bitfld.word 0x0 3. "PLL_ENA,This bit is added from Version 4.10 for Host Controller using PLL. This feature allows Host Controller to initialize clock generator in two steps: by Internal Clock Enable and PLL Enable and to minimize output latency [ex. SDCLK/RCLK D0lane].." "0,1" newline bitfld.word 0x0 2. "SD_CLK_ENA,The HC shall stop SDCLK when writing this bit to 0. SDCLK frequency Select can be changed when this bit is 0. Then the HC shall maintain the same clock frequency until SDCLK is stopped [Stop at SDCLK = 0]. If the HC detects the No Card state .." "0,1" newline rbitfld.word 0x0 1. "INT_CLK_STABLE,This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1. Note: This is useful when using PLL for a clock.." "0,1" newline bitfld.word 0x0 0. "INT_CLK_ENA,This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still registers shall be able to be read and written. Clock starts to oscillate when this.." "0,1" group.byte 0x2E++0x1 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_timeout_control,The register sets the Data Timeout counter value" hexmask.byte 0x0 0.--3. 1. "COUNTER_VALUE,This value determines the interval by which DAT line time-outs are detected. Refer to the Data Time-out Error in the Error Interrupt Status register for information on factors that dictate time-out generation. Time-out clock frequency will.." line.byte 0x1 "SDHC_WRAP__CTL_CFG__CTLCFG_software_reset,This register is used to program the software reset for data. command and for all" bitfld.byte 0x1 2. "SWRST_FOR_DAT,Only part of data circuit is reset. The following registers and bits are cleared by this bit: Buffer Data Port Register: Buffer is cleared and Initialized. Present State register: Buffer read Enable Buffer write.." "0,1" newline bitfld.byte 0x1 1. "SWRST_FOR_CMD,Software Reset For CMD Line Only part of command circuit is reset to be able to issue a command. From Version 4.10 this bit is also used to initialize UHS-II command circuit. This reset is effective only command issuing circuit [including.." "0,1" newline bitfld.byte 0x1 0. "SWRST_FOR_ALL,This reset affects the entire HC except for the card detection circuit. Register bits of type ROC RW RW1C RWAC are cleared to 0. During its initialization the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0.." "0,1" group.word 0x30++0xB line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts,This register gives the status of all the interrupts" rbitfld.word 0x0 15. "ERROR_INTR,If any of the bits in the Error Interrupt Status Register are set then this bit is set. Therefore the HD can test for an error by checking this bit first. In UHS-II mode is enabled if any of the bits in the UHS-II Error.." "0,1" newline bitfld.word 0x0 14. "BOOT_COMPLETE,This status is set if the boot operation gets terminated. '0' Boot operation is not terminated '1' Boot operation is terminated" "0,1" newline bitfld.word 0x0 13. "RCV_BOOT_ACK,This status is set if the boot acknowledge is received from device. '0' Boot ack not recieved '1' Boot ack is recieved" "0,1" newline rbitfld.word 0x0 12. "RETUNING_EVENT,This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer [not large block count] can be completed.." "0,1" newline rbitfld.word 0x0 11. "INTC,This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_C interrupt factor." "0,1" newline rbitfld.word 0x0 10. "INTB,This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_B interrupt factor." "0,1" newline rbitfld.word 0x0 9. "INTA,This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_A interrupt factor. NOTE : INT_A INT_B and INT_C are to be implemented based on the.." "0,1" newline rbitfld.word 0x0 8. "CARD_INTR,When this status has been set and the Host Driver needs to start this interrupt service Card Interrupt Status Enable in the Normal Interrupt Status Enable register may be set to 0 in order to clear the card interrupt status latched in the Host.." "0,1" newline bitfld.word 0x0 7. "CARD_REM,This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card.." "0,1" newline bitfld.word 0x0 6. "CARD_INS,This status is set if the Card Inserted in the Present State register changes from 0 to 1.When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card.." "0,1" newline bitfld.word 0x0 5. "BUF_RD_READY,This status is set if the Buffer Read Enable changes from 0 to 1. Buffer Read Ready is set to 1 for every CMD19 execution in tuning procedure.In UHS-II mode this bit is set at FC [Flow Control] unit basis. '0' Not ready to.." "0,1" newline bitfld.word 0x0 4. "BUF_WR_READY,This status is set if the Buffer Write Enable changes from 0 to 1.In UHS-II mode this bit is set at FC [Flow Control] unit basis. '0' Not ready to write to buffer '1' Ready to write to buffer" "0,1" newline bitfld.word 0x0 3. "DMA_INTERRUPT,This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size regiser. '0' No DMA Interrupt '1' DMA Interrupt is generated" "0,1" newline bitfld.word 0x0 2. "BLK_GAP_EVENT,If the Stop At Block Gap Request in the BlockGap Control Register is set this bit is set. Read Transaction: This bit is set at the falling edge of the DAT Line Active Status [When the transaction is stopped at SD Bus timing. The Read.." "0,1" newline bitfld.word 0x0 1. "XFER_COMPLETE,This bit is set when a read / write transaction is completed. SD Mode Read Transaction: This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated. The first is.." "0,1" newline bitfld.word 0x0 0. "CMD_COMPLETE,SD Mode This bit is set when we get the end bit of the command response [Except Auto CMD12 and Auto CMD23] Note: Command Time-out Error has higher priority than Command Complete. If both are set to 1 it can be considered that the.." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts,This register gives the status of the error interrupts" bitfld.word 0x2 12. "HOST,Occurs when detecting ERROR in m_hresp[dma transaction]" "0,1" newline bitfld.word 0x2 11. "RESP,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register Host Controller Checks R1 or.." "0,1" newline bitfld.word 0x2 10. "TUNING,This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure [Occurrence of an error during tuning procedure is indicated by Sampling Select]. By detecting Tuning Error Host Driver needs to abort a.." "0,1" newline bitfld.word 0x2 9. "ADMA,This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register." "0,1" newline bitfld.word 0x2 8. "AUTO_CMD,Auto CMD12 and Auto CMD23 use this error status.This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. D07 is effective in case of Auto CMD12. Auto CMD Error Status register is.." "0,1" newline bitfld.word 0x2 7. "CURR_LIMIT,By setting the SD Bus Power bit in the Power Control Register the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function it can be protected from an Illegal card by stopping power supply to the card in.." "0,1" newline bitfld.word 0x2 6. "DATA_ENDBIT,Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status." "0,1" newline bitfld.word 0x2 5. "DATA_CRC,Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 010." "0,1" newline bitfld.word 0x2 4. "DATA_TIMEOUT,Occurs when detecting one of following timeout conditions: 1. Busy Timeout for R1b R5b type. 2. Busy Timeout after Write CRC status 3. Write CRC status Timeout 4. Read Data Timeout." "0,1" newline bitfld.word 0x2 3. "CMD_INDEX,Occurs if a Command Index error occurs in the Command Response." "0,1" newline bitfld.word 0x2 2. "CMD_ENDBIT,Occurs when detecting that the end bit of a command response is 0." "0,1" newline bitfld.word 0x2 1. "CMD_CRC,Command CRC Error is generated in two cases. 1. If a response is returned and the Command Time-out Error is set to 0 this bit is set to 1 when detecting a CRT error in the command response 2. The HC detects a CMD line conflict by.." "0,1" newline bitfld.word 0x2 0. "CMD_TIMEOUT,Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK.." "0,1" line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts_ena,This register is used to enable the normal interrupt status register fields" rbitfld.word 0x4 15. "BIT15_FIXED0,The HC shall control error Interrupts using the Error Interrupt Status Enable register." "0,1" newline bitfld.word 0x4 14. "BOOT_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 13. "RCV_BOOT_ACK,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 12. "RETUNING_EVENT,0 - Masked 1 - Enabled" "0,1" newline bitfld.word 0x4 11. "INTC,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent.." "0,1" newline bitfld.word 0x4 10. "INTB,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent.." "0,1" newline bitfld.word 0x4 9. "INTA,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent.." "0,1" newline bitfld.word 0x4 8. "CARD_INTERRUPT,If this bit is set to 0 the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The HD may clear the Card Interrupt Status Enable before.." "0,1" newline bitfld.word 0x4 7. "CARD_REMOVAL,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 6. "CARD_INSERTION,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 5. "BUF_RD_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 4. "BUF_WR_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 3. "DMA_INTERRUPT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 2. "BLK_GAP_EVENT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 1. "XFER_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 0. "CMD_COMPLETE,'0' Masked '1' Enabled" "0,1" line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts_ena,This register is used to enable the Error Interrupt Status register fields" bitfld.word 0x6 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3" newline bitfld.word 0x6 12. "HOST,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 11. "RESP,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 10. "TUNING,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 9. "ADMA,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 8. "AUTO_CMD,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 7. "CURR_LIMIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 6. "DATA_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 5. "DATA_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 4. "DATA_TIMEOUT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 3. "CMD_INDEX,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 2. "CMD_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 1. "CMD_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 0. "CMD_TIMEOUT,'0' Masked '1' Enabled" "0,1" line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sig_ena,This register is used to enable the Normal Interrupt Signal register" rbitfld.word 0x8 15. "BIT15_FIXED0,The HD shall control error Interrupts using the Error Interrupt Signal Enable register." "0,1" newline bitfld.word 0x8 14. "BOOT_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 13. "RCV_BOOT_ACK,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 12. "RETUNING_EVENT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 11. "INTC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 10. "INTB,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 9. "INTA,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 8. "CARD_INTERRUPT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 7. "CARD_REMOVAL,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 6. "CARD_INSERTION,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 5. "BUF_RD_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 4. "BUF_WR_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 3. "DMA_INTERRUPT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 2. "BLK_GAP_EVENT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 1. "XFER_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 0. "CMD_COMPLETE,'0' Masked '1' Enabled" "0,1" line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sig_ena,This register is used to enable Error Interrupt Signal register" bitfld.word 0xA 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3" newline bitfld.word 0xA 12. "HOST,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 11. "RESP,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 10. "TUNING,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 9. "ADMA,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 8. "AUTO_CMD,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 7. "CURR_LIMIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 6. "DATA_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 5. "DATA_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 4. "DATA_TIMEOUT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 3. "CMD_INDEX,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 2. "CMD_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 1. "CMD_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 0. "CMD_TIMEOUT,'0' Masked '1' Enabled" "0,1" rgroup.word 0x3C++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_autocmd_err_sts,This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD 23" bitfld.word 0x0 7. "CMD_NOT_ISSUED,Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error [D04- D01] in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23." "0,1" newline bitfld.word 0x0 5. "RESP,This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or Auto CMD23. This status should be ignored if any bit of D00 to D04 is set to 1." "0,1" newline bitfld.word 0x0 4. "INDEX,Occurs if the Command Index error occurs in response to a command." "0,1" newline bitfld.word 0x0 3. "ENDBIT,Occurs when detecting that the end bit of command response is 0." "0,1" newline bitfld.word 0x0 2. "CRC,Occurs when detecting a CRC error in the command response." "0,1" newline bitfld.word 0x0 1. "TIMEOUT,Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command.If this bit is set to 1 the other error status bits [D04 - D02] are meaningless." "0,1" newline bitfld.word 0x0 0. "ACMD12_NOT_EXEC,If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot issue Auto CMD12 to stop memory multiple block.." "0,1" group.word 0x3E++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control2,This register is used to program UHS Select Mode.UHS Select Mode.Driver Strength Select.Execute Tuning.Sampling Clock Select.Asynchronous Interrupt Enable and Preset value enable" bitfld.word 0x0 15. "PRESET_VALUE_ENA,Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation it is difficult to determine these parameters in the Standard Host Driver. When Preset.." "0,1" newline bitfld.word 0x0 14. "ASYNCH_INTR_ENA,This bit can be set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode [and zero is.." "0,1" newline bitfld.word 0x0 13. "BIT64_ADDRESSING,This field is effective when Host Version 4.00 Enable is set to 1. Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory. Whether 32-bit or 64-bit is determined by OS installed in a host.." "0,1" newline bitfld.word 0x0 12. "HOST_VER40_ENA,This bit selects either Version 3.00 compatible mode or Ver4.mode. In Version 4.00 support of 64-bit System Addressing is modified. All DMAs support 64-bit System Addressing. UHS-II supported Host Driver shall enable this bit. In Version.." "0,1" newline bitfld.word 0x0 11. "CMD23_ENA,In memory card initialization Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]. If the card supports CMD23 [SCR[33]=1] this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3.." "0,1" newline bitfld.word 0x0 10. "ADMA2_LEN_MODE,This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit." "0,1" newline bitfld.word 0x0 9. "DRIVER_STRENGTH2,This is the programmed Drive STrength output and Bit[2] of the sdhccore_drivestrength value." "0,1" newline bitfld.word 0x0 8. "UHS2_INTF_ENABLE,This bit is used to enable UHS-II Interface. Before trying to start UHS-II initialization this bit shall be set to 1. Before trying to start SD mode initialization this bit shall be set to 0. This bit is used to enable UHS-II IF.." "0,1" newline bitfld.word 0x0 7. "SAMPLING_CLK_SELECT,This bit is set by tuning procedure when Execute Tuning is cleared. Writing 1 to this bit is meaningless and ignored. Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Host Controller.." "0,1" newline bitfld.word 0x0 6. "EXECUTE_TUNING,This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to Sampling Clock Select. Tuning procedure is aborted by writing 0 for more detail about tuning.." "0,1" newline bitfld.word 0x0 4.--5. "DRIVER_STRENGTH1,Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling this field is not effective. This field can be set depends on Driver Type A C and D support bits in the Capabilities register. This bit depends.." "0,1,2,3" newline bitfld.word 0x0 3. "V1P8_SIGNAL_ENA,This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within.." "?,1: SDR50" newline bitfld.word 0x0 0.--2. "UHS_MODE_SELECT,This field is used to select one of UHS-I modes or UHS-II mode.In case of UHS-I mode this field is effective when 1.8V Signal-ing Enable is set to 1. In case of UHS-II mode 1.8V Signaling Enable shall be set to 0. Setting of this field.." "0,1,2,3,4,5,6,7" rgroup.quad 0x40++0xF line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_capabilities,This register provides the HD with information specific to the HC implementation. The HC may implement these values as fixed or loaded from flash memory during power on initializa-tion." bitfld.quad 0x0 63. "HS400_SUPPORT,1 HS400 is Supported 0 HS400 is Not Supported" "0,1" newline bitfld.quad 0x0 60. "VDD2_1P8_SUPPORT,This field indicates that support of VDD2 on Host system." "0,1" newline bitfld.quad 0x0 59. "ADMA3_SUPPORT,This field indicates that support of ADMA3 on Host Controller." "0,1" newline bitfld.quad 0x0 57. "SPI_BLK_MODE,This field indicates whether SPI Block Mode is supported or not." "0,1" newline bitfld.quad 0x0 56. "SPI_SUPPORT,This field indicates whether SPI Mode is supported or not." "0,1" newline hexmask.quad.byte 0x0 48.--55. 1. "CLOCK_MULTIPLIER,This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. 'FF' Clock Multiplier M = 256.." newline bitfld.quad 0x0 46.--47. "RETUNING_MODES,This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver. '00' Mode 1 '01' Mode 2 '10' Mode 3 '11' Reserved. There are two.." "0,1,2,3" newline bitfld.quad 0x0 45. "TUNING_FOR_SDR50,If this bit is set to 1 this Host Controller requires tuning to operate SDR50. [Tuning is always required to operate SDR104]. '0' '1'" "0,1" newline hexmask.quad.byte 0x0 40.--43. 1. "RETUNING_TIMER_CNT,This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h - Get information via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds ------.." newline bitfld.quad 0x0 38. "DRIVERD_SUPPORT,This bit indicates support of Driver Type D for 1.8 Signaling. '0' Driver Type D is Not supported '1' Driver Type D is supported" "0,1" newline bitfld.quad 0x0 37. "DRIVERC_SUPPORT,This bit indicates support of Driver Type C for 1.8 Signaling. '0' Driver Type C is Not supported '1' Driver Type C is supported" "0,1" newline bitfld.quad 0x0 36. "DRIVERA_SUPPORT,This bit indicates support of Driver Type A for 1.8 Signaling. '0' Driver Type A is Not supported '1' Driver Type A is supported" "0,1" newline bitfld.quad 0x0 35. "UHS2_SUPPORT,This bit indicates whether Host controller supports UHS-II. If this bit is set to 1 1.8V VDD2 Support shall be set to 1 [Host Sys- tem shall support VDD2 power supply]. 1 UHS-II is Supported 0 UHS-II is Not Supported" "0,1" newline bitfld.quad 0x0 34. "DDR50_SUPPORT,This bit indicates whether DDR50 is supported or not." "0,1" newline bitfld.quad 0x0 33. "SDR104_SUPPORT,This bit indicates whether SDR104 is supported or not.SDR104 requires tuning." "0,1" newline bitfld.quad 0x0 32. "SDR50_SUPPORT,If SDR104 is supported this bit shall be set to 1. Bit 40 indicates whether SDR50 requires tuning or not." "0,1" newline bitfld.quad 0x0 30.--31. "SLOT_TYPE,This field indicates usage of a slot by a specific Host System. [A host controller register set is defined perslot.] Embedded slot for one device [01b] means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot.." "0,1,2,3" newline bitfld.quad 0x0 29. "ASYNCH_INTR_SUPPORT,Refer to SDIO Specification Version 3.00 about asynchronous interrupt." "0,1" newline bitfld.quad 0x0 28. "ADDR_64BIT_SUPPORT_V3,IMeaning of this bit is different depends on Versions [Refer to Table 2-35 for more details]. Host Controller Version 3.00 and Ver4.10 use this bit as 64-bit System Address support for V3 mode. Host Con- troller Version 4.00 uses.." "0,1" newline bitfld.quad 0x0 27. "ADDR_64BIT_SUPPORT_V4,This bit is added from Version 4.10. Set-ting 1 to this bit indicates that the Host Controller supports 64-bit System Addressing of Version 4 mode [Refer to Table 2-35 for the summary of 64-bit sys-tem address support].. When.." "0,1" newline bitfld.quad 0x0 26. "VOLT_1P8_SUPPORT,This bit indicates whether the HC supports 1.8V." "0,1" newline bitfld.quad 0x0 25. "VOLT_3P0_SUPPORT,This bit indicates whether the HC supports 3.0V." "0,1" newline bitfld.quad 0x0 24. "VOLT_3P3_SUPPORT,This bit indicates whether the HC supports 3.3V." "0,1" newline bitfld.quad 0x0 23. "SUSP_RES_SUPPORT,This bit indicates whether the HC supports Suspend / Resume functionality. If this bit is 0 the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend / Resume commands." "0,1" newline bitfld.quad 0x0 22. "SDMA_SUPPORT,This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly.Version 4.10 Host Controller shall support SDMA if ADMA2 is supported." "0,1" newline bitfld.quad 0x0 21. "HIGH_SPEED_SUPPORT,This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz [for SD]/ 20MHz to 52MHz [for MMC]." "0,1" newline bitfld.quad 0x0 19. "ADMA2_SUPPORT,'0' ADMA2 Not Supported '1' ADMA2 Supported" "0,1" newline bitfld.quad 0x0 18. "BUS_8BIT_SUPPORT,This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when Slot Type is set to 10b. In this case refer to Bus Width Preset in the Shared Bus resister." "0,1" newline bitfld.quad 0x0 16.--17. "MAX_BLK_LENGTH,This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below." "0,1,2,3" newline hexmask.quad.byte 0x0 8.--15. 1. "BASE_CLK_FREQ,[1]6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1MHz. The supported clock range is 10MHz to 63MHz. '11xx xxxxb' Not.." newline bitfld.quad 0x0 7. "TIMEOUT_CLK_UNIT,This bit shows the unit of base clock frequency used to detect Data Timeout Error." "0,1" newline hexmask.quad.byte 0x0 0.--5. 1. "TIMEOUT_CLK_FREQ,This bit shows the base clock frequency used to detect Data Timeout Error. '000000' Get Information via another method 'not 0' 1KHz to 63KHz/1MHz to 63MHz" line.quad 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_max_current_cap,This register indicates maximum current capability for each voltage" hexmask.quad.byte 0x8 32.--39. 1. "VDD2_1P8V,Maximum Current for 1.8V VDD2" newline hexmask.quad.byte 0x8 16.--23. 1. "VDD1_1P8V,Maximum Current for 1.8V VDD1" newline hexmask.quad.byte 0x8 8.--15. 1. "VDD1_3P0V,Maximum Current for 3.0V VDD1" newline hexmask.quad.byte 0x8 0.--7. 1. "VDD1_3P3V,Maximum Current for 3.3V VDD1" wgroup.word 0x50++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_ACMD_Err_Sts,This register is not physically implemented. rather it is an address where Auto CMD Error Status register can be written." bitfld.word 0x0 7. "CMD_NOT_ISS,Force Event for Command Not Issued by AUTO CMD12 Error." "0,1" newline bitfld.word 0x0 5. "RESP,Force Event for AUTO CMD Response Error.." "0,1" newline bitfld.word 0x0 4. "INDEX,Force Event for AUTO CMD Index Error.." "0,1" newline bitfld.word 0x0 3. "ENDBIT,Force Event for AUTO CMD End Bit Error." "0,1" newline bitfld.word 0x0 2. "CRC,Force Event for AUTO CMD Timeout Error." "0,1" newline bitfld.word 0x0 1. "TIMEOUT,Force Event for AUTO CMD Timeout Error." "0,1" newline bitfld.word 0x0 0. "ACMD_NOT_EXEC,Force Event for AUTO CMD12 Not Executed." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_Err_Int_Sts,This register is not physically implemented. rather it is an address where Error Interrupt Status register can be written." bitfld.word 0x2 12. "HOST,Force Event for Host Error" "0,1" newline bitfld.word 0x2 11. "RESP,Force Event for Response Error" "0,1" newline bitfld.word 0x2 10. "TUNING,Force Event for Tuning Error." "0,1" newline bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error." "0,1" newline bitfld.word 0x2 8. "AUTO_CMD,Force Event for Auto CMD Error." "0,1" newline bitfld.word 0x2 7. "CURR_LIM,Force Event for Current Limit Error." "0,1" newline bitfld.word 0x2 6. "DAT_ENDBIT,Force Event for Data End Bit Error." "0,1" newline bitfld.word 0x2 5. "DAT_CRC,Force Event for Data CRC Error." "0,1" newline bitfld.word 0x2 4. "DAT_TIMEOUT,Force Event for Data Timeout Error." "0,1" newline bitfld.word 0x2 3. "CMD_INDEX,Force Event for Command Index Error" "0,1" newline bitfld.word 0x2 2. "CMD_ENDBIT,Force Event for Command End Bit Error." "0,1" newline bitfld.word 0x2 1. "CMD_CRC,Force Event for Command CRC Error." "0,1" newline bitfld.word 0x2 0. "CMD_TIMEOUT,Force Event for CMD Timeout Error." "0,1" rgroup.byte 0x54++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_err_status,When the ADMA Error interrupt occur. this register holds the ADMA State in ADMA Error States field and ADMA System Address holds address around the error descriptor" bitfld.byte 0x0 2. "ADMA_LENGTH_ERR,This error occurs in the following 2 cases. While Block Count Enable being set the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. Total data length can not be.." "0,1" newline bitfld.byte 0x0 0.--1. "ADMA_ERR_STATE,This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates 10 because ADMA never stops in this state. D01 D00 : ADMA Error State when error occurred Contents of SYS_SDR.." "0,1,2,3" group.quad 0x58++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_sys_address,This register contains the physical address used for ADMA data transfer" hexmask.quad 0x0 0.--63. 1. "ADMA_ADDR,The 32-bit addressing Host Driver uses lower 32-bit of this register [upper 32-bit should be set to 0] and shall program Descriptor Table on 32-bit boundary andset 32-bit boundary address to this register. DMA2/3 ignores lower 2-bit of this.." rgroup.word 0x60++0xF line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value0,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x0 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value1,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x2 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value2,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x4 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x4 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x4 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value3,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x6 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x6 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x6 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value4,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x8 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x8 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x8 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value5,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0xA 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0xA 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0xA 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value6,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0xC 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0xC 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0xC 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0xE "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value7,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0xE 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0xE 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0xE 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." rgroup.word 0x72++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value8,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x0 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value10,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x2 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." group.quad 0x78++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma3_desc_address,The start address of Integrated DMA Descriptor is set to this register." hexmask.quad 0x0 0.--63. 1. "INTG_DESC_ADDR,The start address of Integrated DMA Descriptor is set to this register. Writing to a specific address starts ADMA3 depends on 32-bit/64-bit address-ing. The ADMA3 fetches one Descriptor Address and increments this field to indicate the.." group.word 0x80++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_size,This register is used to configure the number of bytes in a data block" bitfld.word 0x0 12.--14. "SDMA_BUF_BOUNDARY,When system memory is managed by paging SDMA data transfer is performed in unit of paging. A page size of sys-tem memory management is set to this field. Host Controller generates the DMA Interrupt at the page boundary and.." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--11. 1. "XFER_BLK_SIZE,This register specifies the block size of data packet. SD Memory Card uses a fixed block size of 512 bytes. Vari-able block size may be used for SDIO. The maximum value is 2048 Bytes because CRC16 covers up to 2048 bytes. This register is.." group.long 0x84++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_count,This register is used to configure the number of data blocks" hexmask.long 0x0 0.--31. 1. "XFER_BLK_COUNT,This register is effective when Data Present is set to 1 in UHS-II Command register and is enabled when Block Count Enable is set to 1 and Block / Byte Mode is set to 0 in the UHS-II Transfer Mode register. Data transfer stops when the.." group.byte 0x88++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command_pkt,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes. The command length varies depends on a Command Packet type. The length is specified by the UHS-II Command register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,UHS-II Command Packet image is set to this register.The command length varies depends on a Command Packet type." group.word 0x9C++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_xfer_mode,This register is used to control the operations of data transfers" bitfld.word 0x0 15. "DUPLEX_SELECT,Use of 2 lane half duplex mode is determined by Host Driver." "0,1" newline bitfld.word 0x0 14. "EBSY_WAIT,This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution. Busy is expected for CCMD with R1b/R5b type and DCMD with data transfer.If this bit is set to 1 Host Controller waits receiving of.." "0,1" newline bitfld.word 0x0 8. "RESP_INTR_DIS,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0 and waits Command.." "0,1" newline bitfld.word 0x0 7. "RESP_ERR_CHK_ENA,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver.Only R1 or R5 can be checked. If Host Driver checks response error this bit is set to 0 and Response.." "0,1" newline bitfld.word 0x0 6. "RESP_TYPE,When response error check is enabled this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO. Error Statuses Checked in R1 Bit31 OUT_OF_RANGE.." "0,1" newline bitfld.word 0x0 5. "BYTE_MODE,This bit specifies whether data transfer is in byte mode or block mode when Data Present is set to 1. This bit is effective to a command with data trans-fer." "0,1" newline bitfld.word 0x0 4. "DATA_XFER_DIR,This bit specifies direction of data trans-fer when Data Present is set to 1. This bit is effective to a command with data transfer. 0 - Read [Card to Host] 1 - Write [Host to Card]" "0,1" newline bitfld.word 0x0 1. "BLK_CNT_ENA,This bit specifies whether data transfer usesUHS-II Block Count register. If this bit is set to 1 data transfer is terminated by Block Count. Setting to UHS-II Block Count register shall be equivalent to TLEN in UHS-II Command Packet.." "0,1" newline bitfld.word 0x0 0. "DMA_ENA,This bit selects whether DMA is used or not and is effective to a command with data transfer. One of DMA types is selected by DMA Select in the Host Control 1 register." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command,This register is used to program the Command for host controller" hexmask.word.byte 0x2 8.--12. 1. "PKT_LENGTH,A command packet length which is set in the UHS-II Command Packet register is set to this register. 00011b - 00000b - 3-0 Bytes [Not used] 00100b - 4 Bytes .......... ...... 10100b - 20 Bytes.." newline bitfld.word 0x2 6.--7. "CMD_TYPE,This field is used to distinguish a spe-cific command like abort command. If this field is set to 00b the UHS-II RES Packet is stored in UHS-II Response register [0B3h-0A0h]. To avoid overwrit-ing the UHS-II Response register when this filed.." "0,1,2,3" newline bitfld.word 0x2 5. "DATA_PRESENT,This bit specifies whether the command is accompanied by data packet." "0,1" newline bitfld.word 0x2 2. "SUB_COMMAND,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17].When issuing a main command this bit is set to 0 and when issuing a sub com-mand this bit is set to 1. Setting of this bit is checked.." "0,1" rgroup.byte 0xA0++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_response,This register is used to store received UHS-II RES Packet image" hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xB4++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message_select,This register is used to access internal buffer" bitfld.byte 0x0 0.--1. "MSG_SEL,Host Controller holds 4 MSG packets in FIFO buffer.One of 4 MSGs can be read from the UHS-II MSG register [0BB-0B8h] by setting this register.[Assumed for debug usage.] '00' The latest MSG '01' One MSG before '10' Two MSGs.." "0,1,2,3" rgroup.long 0xB8++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message,This register is used to access internal buffer" hexmask.long.byte 0x0 24.--31. 1. "MSG_BYTE3,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." newline hexmask.long.byte 0x0 16.--23. 1. "MSG_BYTE2,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." newline hexmask.long.byte 0x0 8.--15. 1. "MSG_BYTE1,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_BYTE0,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." group.word 0xBC++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_intr_status,This register shows receipt of INT MSG from which device" hexmask.word 0x0 0.--15. 1. "DEV_INT_STS,This register shows receipt of INT MSG from which device and is effective when INT MSG Enable is set to 1 in the UHS- II Device Select register. On receiving INT MSG from a device Host Controller saves the INT MSG to UHS-II Device Interrupt.." group.byte 0xBE++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_select,UHS-II Device Select Register" bitfld.byte 0x0 7. "INT_MSG_ENA,This bit enables receipt of INT MSG. If this bit is set to 1 receipt of INT MSG is informed by Card Interrupt in the Nor-mal Interrupt Status register. If this bit is set to 0 Host Con-troller ignores receipt of INT MSG and may not set the.." "0,1" newline hexmask.byte 0x0 0.--3. 1. "DEV_SEL,Host Controller holds an INT MSG packet per device. One of INT MSGs [up to 15] can be selected by this field and read from the UHS-II Device Interrupt Code Register [0BFh]. This field is effective when INT MSG Enable is set to 1. The.." rgroup.byte 0xBF++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_int_code,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register." hexmask.byte 0x0 0.--7. 1. "DEV_INTR,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register. Host Controller holds an INT MSG packet per device. One of INT MSGs [Code length is 1 byte] up to 15 can be read from this register by.." group.word 0xC0++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_software_reset,UHS-II Software Reset Register" bitfld.word 0x0 1. "HOST_SDTRAN_RESET,Host Driver set this bit to 1 to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs. This bit is cleared automatically at completionof SD-TRAN reset. If CMD0 is issued SD-TRAN Initial- ization sequence from.." "0,1" newline bitfld.word 0x0 0. "HOST_FULL_RESET,On issuing FULL_RESET CCMD Host Driver set this bit to 1 to reset Host Controller. This bit is cleared auto-matically at completion of Host Controller reset. Initial- ization sequence from PHY Initialization is required to use UHS-II.." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_timer_control,UHS-II Timeout Control Register" hexmask.word.byte 0x2 4.--7. 1. "DEADLOCK_TIMEOUT_CTR,This value determines the deadlock period while host expecting to receive a packet [1 second]. Tim-eout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register prevent.." newline hexmask.word.byte 0x2 0.--3. 1. "CMDRESP_TIMEOUT_CTR,This value determines the interval between com-mand packet and response packet [5ms]. Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When set-ting this register prevent inadvertent.." group.long 0xC4++0xB line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts,This register gives the status of all UHS-II interrupts" hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECFIC_ERR,Vendor may use this field for vendor specific error status. '0' Interrupt is not generated '1' Vendor Specific Error" newline bitfld.long 0x0 17. "DEADLOCK_TIMEOUT,Setting of this bit means that deadlock timeout occurs. Host expects to receive a packet but not received in a specified timeout [1 second]. Timeout value is determined by the setting of Timeout Counter Value for Deadlock in UHS-II Timer.." "0,1" newline bitfld.long 0x0 16. "CMD_RESP_TIMEOUT,Setting of this bit means that RES Packet timeout occurs. Host expects to receive RES packet but not received in a specified timeout [5ms]. Timeout value is determined by the setting of Timeout Counter Value for CMD_RES in UHS-II Timer.." "0,1" newline bitfld.long 0x0 15. "ADMA2_ADMA3,Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode. ADMA2/3 Error Status is indicated to the ADMA Error Status [054h] which is defined in the Host spec 3.00." "0,1" newline bitfld.long 0x0 8. "EBSY,On receiving EBSY packet if the packet indicates an error this bit is set to 1. Setting of this bit also sets Error Interrupt and Transfer Completer together in the Normal Interrupt Status register. This error check is effective for a command with.." "0,1" newline bitfld.long 0x0 7. "UNRECOVERABLE,Setting of this bit means that Unrecoverable Error is set in a packet from a device." "0,1" newline bitfld.long 0x0 5. "TID,Setting of this bit means that TID Error occurs." "0,1" newline bitfld.long 0x0 4. "FRAMING,Setting of this bit means that Framing Error occurs during a packet receiving." "0,1" newline bitfld.long 0x0 3. "CRC,Setting of this bit means that CRC Error occurs during a packet receiving." "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Setting of this bit means that Retry Counter Expired Error occurs during data transfer.If this bit is set either Framing Error or CRC Error in this register shall be set." "0,1" newline bitfld.long 0x0 1. "RESP_PKT,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to1 in the UHS- II Transfer Mode register Host Controller.." "0,1" newline bitfld.long 0x0 0. "HEADER,Setting of this bit means that Header Error occurs in a received packet." "0,1" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts_ena,This register is used to enable the UHS-II Error Interrupt Status register fields" hexmask.long.byte 0x4 27.--31. 1. "VENDOR_SPECFIC,Setting this bit to 1 enables setting of Vendor Specific Error bit in the UHS-II Error Interrupt Status register. 0h - Status is Disabled 1h - Status is Enabled" newline bitfld.long 0x4 17. "DEADLOCK_TIMEOUT,Setting this bit to 1 enables setting of Timeout for Dead lock bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 16. "CMD_RESP_TIMEOUT,Setting this bit to 1 enables setting of Timeout for CMD_RES bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 15. "ADMA2_ADMA3,Setting this bit to 1 enables setting of ADMA2/3 Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 8. "EBSY,Setting this bit to 1 enables setting of EBSY Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 7. "UNRECOVERABLE,Setting this bit to 1 enables setting of Unrecoverable Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 5. "TID,Setting this bit to 1 enables setting of TID Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 4. "FRAMING,Setting this bit to 1 enables setting of Framing Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 3. "CRC,Setting this bit to 1 enables setting of CRC Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 2. "RETRY_EXPIRED,Setting this bit to 1 enables setting of Retry Expired bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 1. "RESP_PKT,Setting this bit to 1 enables setting of RES Packet Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 0. "HEADER,Setting this bit to 1 enables setting of Header Error bit in the UHS-II Error Interrupt Status Register." "0,1" line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sig_ena,This register is used to generate UHS-II Interrupt signals" hexmask.long.byte 0x8 27.--31. 1. "VENDOR_SPECFIC,Setting of a bit to 1 in this field enables generating interrupt signal when corre-spondent bit of Vendor Specific Error is set in the UHS-II Error Interrupt Status Register. 0h - Interrupt Signal is Disabled 1h -.." newline bitfld.long 0x8 17. "DEADLOCK_TIMEOUT,Setting this bit to 1 enables generating interrupt signal when Timeout for Dead lock bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 16. "CMD_RESP_TIMEOUT,Setting this bit to 1 enables generating interrupt signal when Timeout for CMD_RES bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 15. "ADMA2_ADMA3,Setting this bit to 1 enables generating interrupt signal when ADMA2/3 Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 8. "EBSY,Setting this bit to 1 enables generating interrupt signal when EBSY Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 7. "UNRECOVERABLE,Setting this bit to 1 enables generating interrupt signal when Unrecoverable Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 5. "TID,Setting this bit to 1 enables generating interrupt signal when TID Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 4. "FRAMING,Setting this bit to 1 enables generating interrupt signal when Framing Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 3. "CRC,Setting this bit to 1 enables generating interrupt signal when CRC Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 2. "RETRY_EXPIRED_SIG_ENA,Setting this bit to 1 enables generating interrupt signal when Retry Expired bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 1. "RESP_PKT,Setting this bit to 1 enables generating interrupt signal when RES Packet Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 0. "HEADER,Setting this bit to 1 enables generating interrupt signal when Header Error bit is set in the UHS-II Error Interrupt Status Register." "0,1" rgroup.word 0xE0++0x9 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_settings_ptr,This register is pointer for UHS-II settings." hexmask.word 0x0 0.--15. 1. "UHS2_SETTINGS_PTR,Pointer for UHS-II Settings Register" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_capabilities_ptr,This register is pointer for UHS-II Capabilities Register." hexmask.word 0x2 0.--15. 1. "UHS2_CAPABILITIES_PTR,Pointer for UHS-II Capabilities Register" line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_test_ptr,This register is pointer for UHS-II Test Register." hexmask.word 0x4 0.--15. 1. "UHS2_TEST_PTR,Pointer for UHS-II Test Register" line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_shared_bus_ctrl_ptr,This register is pointer for UHS-II Shared Bus Control Register." hexmask.word 0x6 0.--15. 1. "SHARED_BUS_CTRL_PTR,Pointer for Shared Bus Control Register" line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_specfic_ptr,This register is pointer for UHS-II Vendor Specific Pointer Register." hexmask.word 0x8 0.--15. 1. "VENDOR_SPECFIC_PTR,Pointer for Vendor Specific Area" group.long 0xF4++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_boot_timeout_control,This is used to program the boot timeout value counter" hexmask.long 0x0 0.--31. 1. "DATA_TIMEOUT_CNT,This value determines the interval by which DAT line time-outs are detected during boot operation for eMMC4.4 card.The value is in number of sd clock." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_register,Vendor register added for autogate sdclk. cmd11 power down timer. enhancedstrobe and eMMC hardware reset" bitfld.long 0x4 16. "AUTOGATE_SDCLK,If this bit is set SD CLK will be gated automatically when there is no transfer. This is applicable only for Embedded Device" "0,1" newline hexmask.long.word 0x4 2.--15. 1. "CMD11_PD_TIMER,cmd11 power-down timer value" newline bitfld.long 0x4 1. "EMMC_HW_RESET,Hardware reset signal is generared for eMMC card when this bit is set" "0,1" newline bitfld.long 0x4 0. "ENHANCED_STROBE,This bit enables the enhanced strobe logic of the Host Controller" "0,1" rgroup.word 0xFC++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_slot_int_sts,This register is used to read the interrupt signal for each slot." hexmask.word.byte 0x0 0.--7. 1. "INTR_SIG,These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_host_controller_ver,This register is used to read the vendor version number and specification version number" hexmask.word.byte 0x2 8.--15. 1. "VEN_VER_NUM,The Vendor Version Number is set to 0x10 [1.0]" newline hexmask.word.byte 0x2 0.--7. 1. "SPEC_VER_NUM,This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version. 00h - SD Host Controller Specification Version 1.00 01h - SD Host Controller Specification Version 2.00 Including the.." group.long 0x100++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_settings,Start Address of General settings is pointed by Pointer for UHS-II Setting Register." hexmask.long.byte 0x0 8.--13. 1. "NUMLANES,The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices. 2 Lanes FD mode is mandatory and the others modes are optional. 0000b - 2 Lanes FD or 2L-HD 0001b -.." newline bitfld.long 0x0 0. "POWER_MODE,This field determines either Fast mode or Low Power mode.Host and all devices connected to the host shall be set to the same mode." "0,1" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_settings,Start Address of PHY settings is pointed by Pointer for UHS-II Setting Register." hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field. 0h - 8 x16 LSS 1h - 8 x 1 LSS 2h - 8 x 2 LSS 3h - 8 x 3 LSS ...... ......" newline hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ......" newline bitfld.long 0x4 15. "HIBERNATE_ENA,After checking card capability of Hibernate mode if all devices support Hibernate mode this bit may be set. This bit determines whether Host remains in Dormant state or goes to Hibernate state. In Hibernate mode VDD1 Power may be off." "0,1" newline bitfld.long 0x4 6.--7. "SPEED_RANGE,PLL multiplier is selected by this field.Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State. '00' Range A [Default] '01' Range B '10' Reserved '11' Reserved" "0,1,2,3" group.quad 0x108++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_settings,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Setting Register." hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field. 00h - No Gap 01h - 1 LSS 02h - 2 LSS 03h - 3 LSS ...... ...... FFh - 255.." newline bitfld.quad 0x0 16.--17. "RETRY_COUNT,Data Burst retry count is set to this field. '00' Retry Disabled '01' 1 time '10' 2 times '11' 3 times" "0,1,2,3" newline hexmask.quad.byte 0x0 8.--15. 1. "HOST_NFCU,Host Driver sets the number of blocks in Data Burst [Flow Control] to this field.The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices. Setting 1 to 4 blocks is recommended.." rgroup.long 0x110++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_cap,Start Address of General Capabilities is pointed by Pointer for UHS-II Host Capabilities Register." bitfld.long 0x0 22.--23. "CORECFG_UHS2_BUS_TOPLOGY,This field indicates one of bus topologies configured by a Host system. '00' P2P Connection '01' Ring Connection '10' HUB Connection '11' HUB is connected in Ring" "0,1,2,3" newline hexmask.long.byte 0x0 18.--21. 1. "CORECFG_UHS2_MAX_DEVICES,This field indicates the maximum number of devices supported by the Host Controller. 0h - Not used 1h - 1 Devices 2h - 2 Devices ..... ....... Fh - 15 Devices" newline bitfld.long 0x0 16.--17. "DEVICE_TYPE,This field indicates device type configured by a Host system. '00' Removable Card[P2P] '01' Embedded Devices '10' Embedded Devices+Removable Card '11' Reserved" "0,1,2,3" newline bitfld.long 0x0 14. "CFG_64BIT_ADDRESSING,This field indicates support of 64-bit addressing by the Host Controller. '0' 32-bit Addressing is supported '1' 32-bit and 64-bit Addressing is supported" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "NUM_LANES,This field indicates support of lanes by the Host Controller.0 mean not supported and 1 means supported. D08 - 2L-HD D09 - 2D1U-FD D10 - 1D2U-FD D11 - 2D2U-FD D12 - Reserved D13 - Reserved" newline hexmask.long.byte 0x0 4.--7. 1. "GAP,This field indicates the maximum capability of host power supply for a group configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -Not used 1h - 360 mW 2h - 720 mW ....." newline hexmask.long.byte 0x0 0.--3. 1. "DAP,This field indicates the maximum capability of host power supply for a device configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -360 mW [Default] 1h - 360 mW 2h - 720 mW.." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_cap,Start Address of PHY Capabilities is pointed by Pointer for UHS-II Host Capabilities Register." hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,This field indicates the minimum N_LSS_DIR required by the Host Controller. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ...... Fh - 4 x 15 LSS" newline hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,This field indicates the minimum N_LSS_SYN required by the Host Controller. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ...... Fh - 4 x 15 LSS" newline bitfld.long 0x4 6.--7. "SPEED_RANGE,This field indicates supported Speed Range by the Host Controller '00' Range A [Default] '01' Range A and Range B '10' Reserved '11' Reserved" "0,1,2,3" rgroup.quad 0x118++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_cap,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Capabilities Register." hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,This field indicates the minimum number of data gap[DIDL] supported by the Host Controller. 00h - No Gap 01h - 1 LSS 02h - 2 LSS 03h - 3 LSS ...... ...... FFh - 255 LSS" newline hexmask.quad.word 0x0 20.--31. 1. "MAX_BLK_LENGTH,This field indicates maximum block length by the Host Controller. 000h - Not Used 001h - 1 byte 002h - 2 bytes ...... ...... 200h - 512 bytes ...... ......" newline hexmask.quad.byte 0x0 8.--15. 1. "N_FCU,This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller.This value is determined by supported buffer size. 00h - 256 Blocks 01h - 1 Block 02h - 2 Block 03h - 3 Block.." wgroup.long 0x120++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_force_UHSII_Err_Int_Sts,This register is not physically implemented. rather it is an address where UHS-II Error Interrupt Status register can be written." hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECIFIC,Force Event for Vendor Specific Error 0h - Not Affected 1h - Vendor Specific Error Status is set" newline bitfld.long 0x0 17. "TIMEOUT_DEADLOCK,Setting this bit forces the Host Controller to set Timeout for Deadlock in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 16. "TIMEOUT_CMD_RES,Setting this bit forces the Host Controller to set Timeout for CMD_RES in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 15. "ADMA,Setting this bit forces the Host Controller to set ADMA Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 8. "EBSY,Setting this bit forces the Host Controller to set EBSY Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 7. "UNRECOVERABLE,Setting this bit forces the Host Controller to set Unrecover-able Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 5. "TID,Setting this bit forces the Host Controller to set TID Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 4. "FRAMING,Setting this bit forces the Host Controller to set Framing Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 3. "CRC,Setting this bit forces the Host Controller to set CRC Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Setting this bit forces the Host Controller to set Retry Expired in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 1. "RES_PKT,Setting this bit forces the Host Controller to set RES Packet Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 0. "HEADER,Setting this bit forces the Host Controller to set Header Error in the UHS-II Error Interrupt Status register." "0,1" rgroup.long 0x200++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_version,This register provides information about the version of the eMMC CQ standard which is 285 implemented by the CQE. in BCD format. The current version is rev 5.1" hexmask.long.byte 0x0 8.--11. 1. "EMMC_MAJOR_VER_NUM,eMMC Major Version Number [digit left of decimal point] in BCD format" newline hexmask.long.byte 0x0 4.--7. 1. "EMMC_MINOR_VER_NUM,eMMC Minor Version Number [digit right of decimal point] in BCD format" newline hexmask.long.byte 0x0 0.--3. 1. "EMMC_VERSION_SUFFIX,eMMC Version Suffix [2nd digit right of decimal point] in BCD format" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_capabilities,This register is reserved for capability indication." hexmask.long.byte 0x4 12.--15. 1. "CF_MUL,Internal Timer Clock Frequency Multiplier [ITCFMUL] ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the SQS polling period. See ITCFVAL definition for details." newline hexmask.long.word 0x4 0.--9. 1. "CF_VAL,Internal Timer Clock Frequency Value [ITCFVAL] TCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the polling period when using periodic SEND_QUEUE_ STATUS [CMD13] polling." group.long 0x208++0x27 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_config,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time." bitfld.long 0x0 12. "DCMD_ENA,Direct Command [DCMD] Enable This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor or a Direct Command Task Descriptor. CQE uses this bit when a task is issued in slot.." "0: Task descriptor in slot #31 is a Data Transfer..,1: Task descriptor in slot #31 is a DCMD Task.." newline bitfld.long 0x0 8. "TASK_DESC_SIZE,Task Descriptor Size This bit indicates whether the task descriptor size is 128 bits or 64 bits as detailed in Data Structures section. This bit can only be configured when Command Queueing Enable bit is 0 [command queueing is.." "0: Task descriptor size is 64 bits,1: Task descriptor size is 128 bits" newline bitfld.long 0x0 0. "CQ_ENABLE,Command Queueing Enable Software shall write 1 this bit when in order to enable command queueing mode [i.e. enable CQE]. When this bit is 0 CQE is disabled and software controls the eMMC bus using the legacy eMMC host controller." "0,1" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_control,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time." bitfld.long 0x4 8. "CLEAR_ALL_TASKS,Clear All Tasks Software shall write 1 this bit when it wants to clear all the tasks sent to the device. This bit can only be written when CQE is in halt state [i.e.Halt bit is 1]. When software writes 1 the value of the.." "0,1" newline bitfld.long 0x4 0. "HALT_BIT,Halt Host software shall write 1 to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus. For example issuing a Discard Task command [CMDQ_TASK_MGMT] When software writes 1 .." "0,1" line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts,This register indicates pending interrupts that require service. Each bit in this registers is asserted 296 in response a specific event. only if the respective bit is set in CQ ISTE register." bitfld.long 0x8 4. "TASK_ERROR,Task Error Interrupt [TERR] This bit is asserted when task error is detected due to invalid task descriptor" "0,1" newline bitfld.long 0x8 3. "TASK_CLEARED,Task Cleared [TCL] This status bit is asserted [if CQISTE.TCL=1] when a task clear operation is completed by CQE. The com-pleted task clear operation is either an individual task clear [CQTCLR] or clearing of all tasks [CQCTL]." "0,1" newline bitfld.long 0x8 2. "RESP_ERR_DET,Response Error Detected Interrupt [RED] This status bit is asserted [if CQISTE.RED=1] when a response is received with an error bit set in the device status field. The contents of the device status field are listed in Section.." "0,1" newline bitfld.long 0x8 1. "TASK_COMPLETE,Task Complete Interrupt [TCC] This status bit is asserted [if CQISTE.TCC=1] when atleast one of the following two conditions are met: [1] A task is completed and the INT bit is set in its Task Descriptor [2] Interrupt caused by.." "0,1" newline bitfld.long 0x8 0. "HALT_COMPLETE,Halt Complete Interrupt [HAC] This status bit is asserted [if CQISTE.HAC=1] when halt bit in CQCTL register transitions from 0 to 1 indicating that host controller has completed its current ongoing task and has entered halt state." "0,1" line.long 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts_ena,This register enables and disables the reporting of the corresponding interrupt to host soft-ware in 299 CQIS register. When a bit is set ( 1 ) and the corresponding interrupt c -ondition is active. then.." bitfld.long 0xC 4. "TASK_ERROR,Task Error Interrupt Status Enable 1 = CQIS.TERR will be set when its interrupt condition is active 0 = CQIS.TERR is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 3. "TASK_CLEARED,Task Cleared Status Enable [TCL] 1 = CQIS.TCL will be set when its interrupt condition is active 0 = CQIS.TCL is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 2. "RESP_ERR_DET,Response Error Detected Status Enable [RED] 1 = CQIS.RED will be set when its interrupt condition is active 0 = CQIS.RED is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 1. "TASK_COMPLETE,Task Complete Status Enable [TCC] 1 = CQIS.TCC will be set when its interrupt condition is active 0 = CQIS.TCC is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 0. "HALT_COMPLETE,Halt Complete Status Enable [HAC] 1 = CQIS.HAC will be set when its interrupt condition is active 0 = CQIS.HAC is disabled" "0: CQIS,1: CQIS" line.long 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sig_ena,This register enables and disables the generation of interrupts to host software. When a bit is set 304 ( 1 ) and the corresponding bit in CQIS is set. then an interrupt is gene -rated. Interrupt sources.." bitfld.long 0x10 4. "TASK_ERROR,Task Error Interrupt Signal Enable [TERR] When set and CQIS.TERR is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 3. "TASK_CLEARED,Task Cleared Signal Enable [TCL] When set and CQIS.TCL is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 2. "RESP_ERR_DET,Response Error Detected Signal Enable [TCC] When set and CQIS.RED is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 1. "TASK_COMPLETE,Task Complete Signal Enable [TCC] When set and CQIS.TCC is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 0. "HALT_COMPLETE,Halt Complete Signal Enable [HAC] When set and CQIS.HAC is asserted the CQE shall generate an interrupt" "0,1" line.long 0x14 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_coalescing,This register controls the interrupt coalescing feature." bitfld.long 0x14 31. "CQINTCOALESC_ENABLE,When set to 0 by software command responses are neither counted nor timed. Interrupts are still triggered by completion of tasks with INT=1 in the Task Descriptor. When set to 1 the interrupt coalescing mechanism is enabled.." "0,1" newline rbitfld.long 0x14 20. "IC_STATUS,This bit indicates to software whether any tasks [with INT=0] have completed and counted towards interrupt coalescing [i.e. ICSB is set if and only if IC counter > 0]. Bit Value Description 1 = At least one task completion has been.." "0: No task completions have occurred since last..,1: At least one task completion has been counted.." newline hexmask.long.byte 0x14 8.--12. 1. "CTR_THRESHOLD,Interrupt Coalescing Counter Threshold [ICCTH]: Software uses this field to configure the number of task completions [only tasks with INT=0 in the Task Descriptor] which are required in order to generate an interrupt. Counter.." newline hexmask.long.byte 0x14 0.--6. 1. "TIMEOUT_VAL,Interrupt Coalescing Timeout Value [ICTOVAL]: Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. Timer Operation: The timer is reset by.." line.long 0x18 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory." hexmask.long 0x18 0.--31. 1. "CQTDLBA_LO,Task Descriptor List Base Address [TDLBA] This register stores the LSB bits [bits 31:0] of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * [Task Descrip-tor.." line.long 0x1C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr_upbits,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory." hexmask.long 0x1C 0.--31. 1. "CQTDLBA_HI,Task Descriptor List Base Address [TDLBA] This register stores the MSB bits [bits 63:32] of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * [Task Descrip-tor.." line.long 0x20 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_door_bell,Using this register. software triggers CQE to process a new task." hexmask.long 0x20 0.--31. 1. "CQTDB_VAL,Command Queueing Task Doorbell Software shall configure TDLBA and TDLBAU and enable CQE in CQCFG before using this register. Writing 1 to bit n of this register triggers CQE to start pro-cessing the task encoded in slot n of the TDL." line.long 0x24 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_comp_notif,This register is used by CQE to notify software about completed tasks." hexmask.long 0x24 0.--31. 1. "CQTCN_VAL,CQE shall set bit n of this register [at the same time it clears bit n of CQTDBR] when a task execution is com-pleted [with success or error]. When receiving interrupt for task completion software may read this register to know which tasks.." rgroup.long 0x230++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_queue_status,This register stores the most recent value of the device s queue status." hexmask.long 0x0 0.--31. 1. "CQDQ_STS,Every time the Host controller receives a queue status register [QSR] from the device it updates this register with the response of status command i.e. the devices queue status." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_pending_tasks,This register indicates to software which tasks are queued in the device. awaiting execution." hexmask.long 0x4 0.--31. 1. "CQDP_TSKS,Bit n of this register is set if and only if QUEUED_TASK_PARAMS [CMD44] and QUEUED_TASK_ADDRESS [CMD45] were sent for this specific task and if this task hasnt been executed yet.CQE shall set this bit after receiving a successful response for.." group.long 0x238++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_clear,This register is used for removing an outstanding task in the CQE. 327. The register should be used only when CQE is in Halt state." hexmask.long 0x0 0.--31. 1. "CQTCLR,Writing 1 to bit n of this register orders CQE to clear a task which software has previously issued.This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit.When software writes 1 to a bit in this.." group.long 0x240++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config1,The register controls the when SEND_QUEUE_STATUS commands are sent." hexmask.long.byte 0x0 16.--19. 1. "CMD_BLK_CNTR,This field indicates to CQE when to send SEND_QUEUE_STATUS [CMD13] command to inquire the status of the devices task queue.A value of n means CQE shall send status command on the CMD line during the transfer of data block BLOCK_CNT-n on.." newline hexmask.long.word 0x0 0.--15. 1. "CMD_IDLE_TIMER,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS [CMD13] polling.Periodic polling is used when tasks are pending in the device but no data transfer is in progress. When a SEND_QUEUE_STATUS.." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argu-ment." hexmask.long.word 0x4 0.--15. 1. "QUEUE_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_ STATUS [CMD13] com-mand. argument. CQE shall copy this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS [CMD13] command." rgroup.long 0x248++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dcmd_response,This register is used for passing the response of a DCMD task to software." hexmask.long 0x0 0.--31. 1. "LAST_RESP,This register contains the response of the command generated by the last direct-command [DCMD] task which was sent.CQE shall update this register when it receives the response for a DCMD task. This register is considered valid only after bit 31.." group.long 0x250++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_resp_err_mask,This register controls the generation of Response Error Detection (RED) interrupt." hexmask.long 0x0 0.--31. 1. "CQRMEM,This bit is used as in interrupt mask on the device status filed which is received in R1/R1b responses.Bit Value Description [for any bit i]:1 = When a R1/R1b response is received with bit i in the device status set a RED interrupt is generated.." rgroup.long 0x254++0xF line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_err_info,This register is updated by CQE when an error occurs on data or command related to a task activity." bitfld.long 0x0 31. "DATERR_VALID,Data Transfer Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller. If a data transfer is in progress when the error is detected/indicated the bit is set to 1. If a no.." "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "DATERR_TASK_ID,Data Transfer Error Task ID This field indicates the ID of the task which was executed on the data lines when an error occurred. The field is updated if a data transfer is in progress when an error is detected by CQE or.." newline hexmask.long.byte 0x0 16.--21. 1. "DATERR_CMD_INDEX,Data Transfer Error Command Index This field indicates the index of the command which was executed on the data lines when an error occurred. The index shall be set to EXECUTE_READ_TASK[CMD46] or EXECUTE_WRITE_TASK [CMD47].." newline bitfld.long 0x0 15. "RESP_MODE_VALID,Response Mode Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller. If a command transaction is in progress when the error is detected/indicated the bit is set to 1." "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "RESP_MODE_TASK_ID,Response Mode Error Task ID This field indicates the ID of the task which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by.." newline hexmask.long.byte 0x0 0.--5. 1. "RESP_MODE_CMD_INDEX,Response Mode Error Command Index This field indicates the index of the command which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is.." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_index,This register stores the index of the last received command response." hexmask.long.byte 0x4 0.--5. 1. "LAST_CRI,This field stores the index of the last received command response. CQE shall update the value every time a com-mand response is received." line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_arg,This register stores the index of the last received command response." hexmask.long 0x8 0.--31. 1. "LAST_CRA,This field stores the argument of the last received com-mand. CQE shall update the value every time a com-mand response is received." line.long 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_cq_error_task_id,CQ Error Task ID Register" hexmask.long.byte 0xC 0.--4. 1. "TERR_ID,Task Error ID" tree.end tree "MMCSD0_ECC_AGGR_RXMEM" base ad:0x706000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MMCSD0_ECC_AGGR_TXMEM" base ad:0x707000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MMCSD0_SS_CFG" base ad:0xFA18000 rgroup.long 0x0++0x3 line.long 0x0 "REGS__SS_CFG__SSCFG_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem" hexmask.long.word 0x0 16.--31. 1. "MOD_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version" newline bitfld.long 0x0 8.--10. "MAJ_REV,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MIN_REV,Minor revision" group.long 0x10++0x37 line.long 0x0 "REGS__SS_CFG__SSCFG_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.byte 0x0 24.--29. 1. "TUNINGCOUNT,Configures the Number of Taps (Phases) of the RX clock that is supported. The Tuning State machine uses this information to select one of the Taps (Phases) of the RX clock during the Tuning Procedure." bitfld.long 0x0 20. "ASYNCWKUPENA,Determines the Wakeup Signal Generation Mode. 0: Synchronous Wakeup Mode: The xin_clk has to be running for this mode. The Card Insertion/Removal/Interrupt events are detected synchronously on the xin_clk and the Wakeup Event is generated." "0: Synchronous Wakeup Mode: The xin_clk has to be..,1: Asyncrhonous Wakeup Mode: The xin_clk and the.." newline hexmask.long.byte 0x0 12.--15. 1. "CQFMUL,FMUL for the CQ Internal Timer Clock Frequency" hexmask.long.word 0x0 0.--9. 1. "CQFVAL,FVAL for the CQ Internal Timer Clock Frequency" line.long 0x4 "REGS__SS_CFG__SSCFG_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." bitfld.long 0x4 30.--31. "SLOTTYPE,Slot Type. Should be set based on the final product usage. 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved." "0,1,2,3" bitfld.long 0x4 29. "ASYNCHINTRSUPPORT,Asynchronous Interrupt Support. Suggested Value is 1'b1 (The Core supports monitoring of Asynchronous Interrupt)." "0,1" newline bitfld.long 0x4 26. "SUPPORT1P8VOLT,1.8V Support. Suggested Value is 1'b1 (The 1.8 Volt Switching is supported by Core). Optionally can be set to 1'b0 if the application doesn't want 1.8V switching (SD3.0)." "0,1" bitfld.long 0x4 25. "SUPPORT3P0VOLT,3.0V Support. Should be set based on whether 3.0V is supported on the SD Interface." "0,1" newline bitfld.long 0x4 24. "SUPPORT3P3VOLT,3.3V Support. Suggested Value is 1'b1 as the 3.3 V is the default voltage on the SD Interface." "0,1" bitfld.long 0x4 23. "SUSPRESSUPPORT,Suspend/Resume Support. Suggested Value is 1'b1 (The Suspend/Resume is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support Suspend/Resume Mode." "0,1" newline bitfld.long 0x4 22. "SDMASUPPORT,SDMA Support. Suggested Value is 1'b1 (The SDMA is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support SDMA Mode." "0,1" bitfld.long 0x4 21. "HIGHSPEEDSUPPORT,High Speed Support. Suggested Value is 1'b1 (The High Speed mode is supported by Core)." "0,1" newline bitfld.long 0x4 19. "ADMA2SUPPORT,ADMA2 Support. Suggested Value is 1'b1 (The ADMA2 is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support ADMA2 Mode." "0,1" bitfld.long 0x4 18. "SUPPORT8BIT,8-bit Support for Embedded Device. Suggested Value is 1'b1 (The Core supports 8-bit Interface). Optionally an be set to 1'b0 if the Application supports only 4-bit SD Interface." "0,1" newline bitfld.long 0x4 16.--17. "MAXBLKLENGTH,Max Block Length. Maximum Block Length supported by the Core/Device. 00: 512 (Bytes) 01: 1024 10: 2048 11: Reserved." "0: 512,1: 1024,?,?" hexmask.long.byte 0x4 8.--15. 1. "BASECLKFREQ,Base Clock Frequency for SD Clock. This is the frequency of the xin_clk." newline bitfld.long 0x4 7. "TIMEOUTCLKUNIT,Timeout Clock Unit. Suggested Value is 1'b0 (KHz)." "0,1" hexmask.long.byte 0x4 0.--5. 1. "TIMEOUTCLKFREQ,Timeout Clock Frequency. Suggested Value is 1 KHz. Internally the 1msec Timer is used for Timeout Detection. The 1msec Timer is generated from the xin_clk." line.long 0x8 "REGS__SS_CFG__SSCFG_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." bitfld.long 0x8 28. "SUPPORT1P8VDD2,1.8V VDD2 Support." "0,1" bitfld.long 0x8 27. "ADMA3SUPPORT,ADMA3 Support." "0,1" newline hexmask.long.byte 0x8 16.--23. 1. "CLOCKMULTIPLIER,Clock Multiplier. This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. FFh Clock Multiplier M =.." bitfld.long 0x8 14.--15. "RETUNINGMODES,Re-Tuning Modes. Should be set to 2'b00 as the Core supports only the Software Timer based Re-Tuning." "0,1,2,3" newline bitfld.long 0x8 13. "TUNINGFORSDR50,Use Tuning for SDR50. This bit should be set if the Application wants Tuning be used for SDR50 Modes. The Core operates with or with out tuning for SDR50 mode as long as the Clock can be manually tuned using tap delay." "0,1" hexmask.long.byte 0x8 8.--11. 1. "RETUNINGTIMERCNT,Timer Count for Re-Tuning. This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer." newline bitfld.long 0x8 7. "TYPE4SUPPORT,Driver Type 4 Support. This bit should be set based on whether Driver Type 4 for 1.8 Signalling is supported or not." "0,1" bitfld.long 0x8 6. "DDRIVERSUPPORT,Driver Type D Support. This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not." "0,1" newline bitfld.long 0x8 5. "CDRIVERSUPPORT,Driver Type C Support. This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not." "0,1" bitfld.long 0x8 4. "ADRIVERSUPPORT,Driver Type A Support. This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not." "0,1" newline bitfld.long 0x8 2. "DDR50SUPPORT,DDR50 Support. Suggested Value is 1'b1 (The Core supports DDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support DDR50." "0,1" bitfld.long 0x8 1. "SDR104SUPPORT,SDR104 Support. Suggested Value is 1'b1 (The Core supports SDR104 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR104." "0,1" newline bitfld.long 0x8 0. "SDR50SUPPORT,SDR50 Support. Suggested Value is 1'b1 (The Core supports SDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR50." "0,1" line.long 0xC "REGS__SS_CFG__SSCFG_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.byte 0xC 16.--23. 1. "MAXCURRENT1P8V,Maximum Current for 1.8V." hexmask.long.byte 0xC 8.--15. 1. "MAXCURRENT3P0V,Maximum Current for 3.0V." newline hexmask.long.byte 0xC 0.--7. 1. "MAXCURRENT3P3V,Maximum Current for 3.3V." line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.byte 0x10 0.--7. 1. "MAXCURRENTVDD2,Maximum Current for 1.8 V (VDD2)." line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x14 0.--12. 1. "INITPRESETVAL,Preset Value for Initialization." line.long 0x18 "REGS__SS_CFG__SSCFG_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x18 0.--12. 1. "DSPDPRESETVAL,Preset Value for Default Speed." line.long 0x1C "REGS__SS_CFG__SSCFG_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x1C 0.--12. 1. "HSPDPRESETVAL,Preset Value for High Speed." line.long 0x20 "REGS__SS_CFG__SSCFG_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x20 0.--12. 1. "SDR12PRESETVAL,Preset Value for SDR12." line.long 0x24 "REGS__SS_CFG__SSCFG_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x24 0.--12. 1. "SDR25PRESETVAL,Preset Value for SDR25." line.long 0x28 "REGS__SS_CFG__SSCFG_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x28 0.--12. 1. "SDR50PRESETVAL,Preset Value for SDR50." line.long 0x2C "REGS__SS_CFG__SSCFG_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x2C 0.--12. 1. "SDR104PRESETVAL,Preset Value for SDR104." line.long 0x30 "REGS__SS_CFG__SSCFG_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x30 0.--12. 1. "DDR50PRESETVAL,Preset Value for DDR50." line.long 0x34 "REGS__SS_CFG__SSCFG_CTL_CFG_14_REG,The Controller Config 14 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." rgroup.long 0x60++0x17 line.long 0x0 "REGS__SS_CFG__SSCFG_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." bitfld.long 0x0 31. "SDHC_CMDIDLE,Idle signal to enable S/W to gate off the clocks." "0,1" hexmask.long.byte 0x0 24.--28. 1. "RXCLKTAPSEL,Controller HW tunning RX clock tap selection value." newline hexmask.long.word 0x0 0.--15. 1. "DMADEBUGBUS,DMA_CTRL Debug Bus." line.long 0x4 "REGS__SS_CFG__SSCFG_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x4 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL Debug Bus." line.long 0x8 "REGS__SS_CFG__SSCFG_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x8 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL Debug Bus." line.long 0xC "REGS__SS_CFG__SSCFG_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0xC 0.--15. 1. "RXDDEBUGBUS0,RXD_CTRL Debug Bus (SD CLK)." line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x10 0.--15. 1. "RXDDEBUGBUS1,RXD_CTRL Debug Bus (RX CLK)." line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x14 0.--15. 1. "TUNDEBUGBUS,TUN_CTRL Debug Bus." group.long 0x100++0x17 line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0x0 31. "IOMUX_ENABLE,IO mux enable. Set 1 for GPIO. Set 0 for eMMC/SD" "0,1" line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_CTRL_2_REG,The PHY Control 2 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." line.long 0x8 "REGS__SS_CFG__SSCFG_PHY_CTRL_3_REG,The PHY Control 3 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." line.long 0xC "REGS__SS_CFG__SSCFG_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0xC 20. "OTAPDLYENA,Output Tap Delay Enable. Enables manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." "0,1" hexmask.long.byte 0xC 12.--15. 1. "OTAPDLYSEL,Output Tap Delay Select. Manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." newline bitfld.long 0xC 9. "ITAPCHGWIN,Input Tap Change Window. It gets asserted by the controller while changing the itapdlysel. Used to gate of the RX clock during switching the clock source while tap is changing to avoid clock glitches." "0,1" bitfld.long 0xC 8. "ITAPDLYENA,Input Tap Delay Enable. This is used for the manual control of the RX clock Tap Delay in non HS200/HS400 modes." "0,1" newline hexmask.long.byte 0xC 0.--4. 1. "ITAPDLYSEL,Input Tap Delay Select. Manual control of the RX clock Tap Delay in the non HS200/HS400 modes." line.long 0x10 "REGS__SS_CFG__SSCFG_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0x10 0.--2. "CLKBUFSEL,Clock Delay Buffer Select. Selects one of the eight taps in the CLK Delay Buffer based on PVT variation." "0,1,2,3,4,5,6,7" line.long 0x14 "REGS__SS_CFG__SSCFG_PHY_CTRL_6_REG,The PHY Control 6 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." group.long 0x130++0x7 line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_STAT_1_REG,The PHY Status 1 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports. For detailed functionality of the Arasan eMMC/SD PHY status ports please refer to its specification listed in.." line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_STAT_2_REG,The PHY Status 2 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports. For detailed functionality of the Arasan eMMC/SD PHY status ports please refer to its specification listed in.." tree.end tree "MMCSD1_CTL_CFG" base ad:0xFA00000 group.word 0x0++0xF line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_lo,This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." hexmask.word 0x0 0.--15. 1. "SDMA_ADDRESS,When Host Version 4 Enable is set to 0 in the Host Control 2 register DMA uses this register as system address in only 32-bit addressing mode. Auto CMD23 cannot be used with SDMA. When Host Version 4 Enable is set to 1 SDMA uses ADMA System.." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_hi,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." hexmask.word 0x2 0.--15. 1. "SDMA_ADDRESS,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_block_size,This register is used to configure the number of bytes in a data block" bitfld.word 0x4 12.--14. "SDMA_BUF_SIZE,To perform long DMA transfer System Address register shall be updated at every system boundary during DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at the every boundary.." "0,1,2,3,4,5,6,7" newline hexmask.word 0x4 0.--11. 1. "XFER_BLK_SIZE,This field specifies the block size for block data transfers for CMD17 CMD18 CMD24 CMD25 and CMD53. It can be accessed only if no transaction is executing [i.e after a transaction has stopped]. Read operations during transfer return an.." line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_block_count,This register is used to configure the number of data blocks" hexmask.word 0x6 0.--15. 1. "XFER_BLK_CNT,Host Controller Version 4.10 extends block count to 32-bit [Refer to Section 1.15].Selection of either 16-bit Block Count register or 32-bit Block Count register is defined as follows: [1] If Host Version 4 Enable in the Host Control 2.." line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_lo,This register contains Lower bits of SD Command Argument" hexmask.word 0x8 0.--15. 1. "CMD_ARG1,The SD Command Argument is specified as bit23-8 of Command-Format." line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_hi,This register contains higher bits of SD Command Argument" hexmask.word 0xA 0.--15. 1. "CMD_ARG1,The SD Command Argument is specified as bit39-24 of Command-Format." line.word 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_transfer_mode,This register is used to control the operations of data transfers" bitfld.word 0xC 8. "RESP_INTR_DIS,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0 and waits Command Complete.." "0,1" newline bitfld.word 0xC 7. "RESP_ERR_CHK_ENA,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked.If Host Driver checks response error this bit is set to 0 and Response Interrupt.." "0,1" newline bitfld.word 0xC 6. "RESP_TYPE,When response error check is enabled this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO." "0,1" newline bitfld.word 0xC 5. "MULTI_BLK_SEL,This bit enables multiple block data transfers." "0,1" newline bitfld.word 0xC 4. "DATA_XFER_DIR,This bit defines the direction of data transfers." "0,1" newline bitfld.word 0xC 2.--3. "AUTO_CMD_ENA,There are three methods to stop Multiple-block read and write operation. [1] Auto CMD12 Enable: Multiple-block read and write commands for memory require CMD12 to stop the operation. When this field is set to 01b the Host.." "0,1,2,3" newline bitfld.word 0xC 1. "BLK_CNT_ENA,This bit is used to enable the Block count register which is only relevant for multiple block transfers. When this bit is 0 the Block Count register is disabled which is useful in executing an infinite transfer." "0,1" newline bitfld.word 0xC 0. "DMA_ENA,DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1 a DMA operation shall begin when the HD writes to the upper byte of Command register [00Fh]." "0,1" line.word 0xE "SDHC_WRAP__CTL_CFG__CTLCFG_command,This register is used to program the Command for host controller" hexmask.word.byte 0xE 8.--13. 1. "CMD_INDEX,This bit shall be set to the command number [CMD0-63 ACMD0-63]." newline bitfld.word 0xE 6.--7. "CMD_TYPE,There are three types of special commands. Suspend Resume andAbort. These bits shall bet set to 00b for all other commands. Suspend Command: If the Suspend command succeeds the HC shall assume the SD Bus has been released and that it is.." "0,1,2,3" newline bitfld.word 0xE 5. "DATA_PRESENT,This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. If is set to 0 for the following: 1. Commands using only CMD line [ex. CMD52]. 2. Commands with no data transferbut using busy.." "0,1" newline bitfld.word 0xE 4. "CMD_INDEX_CHK_ENA,If this bit is set to 1 the HC shall check the index field in the response to see if it has the same value as the command index. If it is not it is reported as a Command Index Error. If this bit is set to 0 the Index field is not.." "0,1" newline bitfld.word 0xE 3. "CMD_CRC_CHK_ENA,If this bit is set to 1 the HC shall check the CRC field in the response. If an error is detected it is reported as a Command CRC Error. If this bit is set to 0 the CRC field is not checked." "0,1" newline bitfld.word 0xE 2. "SUB_CMD,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17]. When issuing a main com-mand this bit is set to 0 and when issuing a sub command this bit is set to 1. Setting of this bit is checked.." "0,1" newline bitfld.word 0xE 0.--1. "RESP_TYPE_SEL,Response Type Select." "0,1,2,3" rgroup.word 0x10++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_response,This register is used to store responses from SD Cards" hexmask.word 0x0 0.--15. 1. "CMD_RESP,R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." group.long 0x20++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_data_port,This register is used to access internal buffer" hexmask.long 0x0 0.--31. 1. "BUF_RD_DATA,The Host Controller Buffer can be accessed through this 32-bit Data Port Register." rgroup.long 0x24++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_presentstate,The Host Driver can get status of the Host Controller from this 32-bit read-only register" bitfld.long 0x0 31. "UHS2_IF_DETECTION,This status indicates whether a card supports UHS-II IF. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 regis-ter. UHS-II interface initialization is activated by setting SD Clock Enable in the.." "0,1" newline bitfld.long 0x0 30. "UHS2_IF_LANE_SYNC,This status indicates whether lane is synchronized in UHS-II mode. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On detecting UHS-II Interface [D31=1] Host Controller provides SYN.." "0,1" newline bitfld.long 0x0 29. "UHS2_DORMANT,This status indicates whether UHS-II Ianes enterDormant state. This function is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On issuing GO_DORMAT_STATE com-mand Go Dormant Command [111b]; is set to Command.." "0,1" newline bitfld.long 0x0 28. "SUB_COMMAND_STS,The Command register and Response register are commonly used for main command and sub command. This status is used to distinguish which response error statuses main command or sub command indicated in the Error Interrupt Status.." "0,1" newline bitfld.long 0x0 27. "CMD_NOT_ISS_BY_ERR,Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error. [Equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in the Auto CMD Error.." "0,1" newline bitfld.long 0x0 24. "SDIF_CMDIN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 23. "SDIF_DAT3IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[3]." "0,1" newline bitfld.long 0x0 22. "SDIF_DAT2IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[2]." "0,1" newline bitfld.long 0x0 21. "SDIF_DAT1IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[1]." "0,1" newline bitfld.long 0x0 20. "SDIF_DAT0IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[0]." "0,1" newline bitfld.long 0x0 19. "WRITE_PROTECT,The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin." "0,1" newline bitfld.long 0x0 18. "CARD_DETECT,This bit reflects the inverse value of the SDCD# pin. '0' No Card present [SDCD# = 1] '1' Card present [SDCD# = 0]" "0,1" newline bitfld.long 0x0 17. "CARD_STATE_STABLE,This bit is used for testing. If it is 0 the Card Detect Pin Level is not stable. If this bit is set to 1 it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this.." "0,1" newline bitfld.long 0x0 16. "CARD_INSERTED,This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt.." "0,1" newline bitfld.long 0x0 11. "BUF_RD_ENA,This status is used for non-DMA read transfers.This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1 readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the.." "0,1" newline bitfld.long 0x0 10. "BUF_WR_ENA,This status is used for non-DMA write transfers.This read only flag indicates if space is available for write data. If this bit is 1 data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written.." "0,1" newline bitfld.long 0x0 9. "RD_XFER_ACTIVE,This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: After the end bit of the read command. When writing a 1 to continue Request in the Block.." "0,1" newline bitfld.long 0x0 8. "WR_XFER_ACTIVE,This status indicates a write transfer is active. If this bit is 0 it means no valid write data exists in the HC. This bit is set in either of the following cases: After the end bit of the write command. When writing a.." "0,1" newline bitfld.long 0x0 7. "SDIF_DAT7IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 6. "SDIF_DAT6IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 5. "SDIF_DAT5IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 4. "SDIF_DAT4IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 3. "RETUNING_REQ,Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is.." "0,1" newline bitfld.long 0x0 2. "DATA_LINE_ACTIVE,This bit indicates whether one of the DAT line on SD bus is in use." "0,1" newline bitfld.long 0x0 1. "INHIBIT_DAT,This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0 it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit [DAT] [ex. R1b R5b.." "0,1" newline bitfld.long 0x0 0. "INHIBIT_CMD,SD Mode If this bit is 0 it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register [00Fh] is written. This bit is cleared when the command response is.." "0,1" group.byte 0x28++0x3 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control1,This register is used to program DMA modes. LED Control. Data Transfer Width. High Speed Enable. Card detect test level and signal selection" bitfld.byte 0x0 7. "CD_SIG_SEL,This bit selects source for card detection. '0' SDCD# is selected [for normal use] '1' The card detect test level is selected" "0,1" newline bitfld.byte 0x0 6. "CD_TEST_LEVEL,This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. Generates [card ins or card removal] interrupt when the normal int sts enable bit is set. '0' No Card '1' Card Inserted" "0,1" newline bitfld.byte 0x0 5. "EXT_DATA_WIDTH,This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register. If a device supports 8-bit bus mode this bit may be set to 1. If this bit.." "0,1" newline bitfld.byte 0x0 3.--4. "DMA_SELECT,This field is used to select DMA type. The Host Driver shall check support of DMA modes by referring the Capabilities register. Selected DMA is enabled by DMA Enable of the Transfer Mode register in SD mode and DMA Enable of UHS-II Transfer.." "0,1,2,3" newline bitfld.byte 0x0 2. "HIGH_SPEED_ENA,This bit is optional. Before setting this bit the HD shall check the High Speed Support in the capabilities register. If this bit is set to 0 [default] the HC outputs CMD line and DAT lines at the falling edge of the SD clock [up to.." "0,1" newline bitfld.byte 0x0 1. "DATA_WIDTH,This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. This bit is not effective in UHS-II mode." "0,1" newline bitfld.byte 0x0 0. "LED_CONTROL,This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands this bit can be set during all transactions. It is not necessary to change for each.." "0,1" line.byte 0x1 "SDHC_WRAP__CTL_CFG__CTLCFG_power_control,This register is used to program the SD Bus power and voltage level" bitfld.byte 0x1 5.--7. "UHS2_VOLTAGE,This field determines supply voltage range to VDD2. This field can be set to 101b if 1.8V VDD2 Support in the Capabilities register is set to 1. '000' VDD2 Not supported '001'- '011' Reserved '100' Reserved for 1.2V.." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x1 4. "UHS2_POWER,Setting this bit enables providing VDD2. '0' Power Off '1' Power On" "0,1" newline bitfld.byte 0x1 1.--3. "SD_BUS_VOLTAGE,By setting these bits the HD selects the voltage level for the SD card. Before setting this register the HD shall check the voltage support bits in the capabilities register. If an unsupported voltage is selected the Host System shall.." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x1 0. "SD_BUS_POWER,Before setting this bit the SD host driver shall set SD Bus Voltage Select. If the HC detects the No Card State this bit shall be cleared. If this bit is cleared the Host Control-ler should immediately stop driving CMD and DAT[3:0].." "0,1" line.byte 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_block_gap_control,This register is used to program the block gap request. read wait control and interrupt at block gap" bitfld.byte 0x2 7. "BOOT_ACK_ENA,To check for the boot acknowledge in boot operation." "0,1" newline bitfld.byte 0x2 6. "ALT_BOOT_MODE,To start boot code access in alternative mode." "0,1" newline bitfld.byte 0x2 5. "BOOT_ENABLE,To start boot code access." "0,1" newline bitfld.byte 0x2 4. "SPI_MODE,SPI mode enable bit." "0,1" newline bitfld.byte 0x2 3. "INTRPT_AT_BLK_GAP,This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt.." "0,1" newline bitfld.byte 0x2 2. "RDWAIT_CTRL,The read wait function is optional for SDIO cards. If the card supports read wait set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data which.." "0,1" newline bitfld.byte 0x2 1. "CONTINUE,This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap set Stop At block Gap Request to 0 and set this bit to restart the transfer. The Host Controller automatically.." "0,1" newline bitfld.byte 0x2 0. "STOP_AT_BLK_GAP,This bit is used to stop executing a transaction at the next block gap for non- DMA SDMA and ADMA transfers. Until the transfer complete is set to 1 indicating a transfer completion the HD shall leave this bit set to 1. Clearing both the.." "0,1" line.byte 0x3 "SDHC_WRAP__CTL_CFG__CTLCFG_wakeup_control,This register is used to program the wakeup functionality" bitfld.byte 0x3 2. "CARD_REMOVAL,This bit enables wakeup event via Card removal assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit." "0,1" newline bitfld.byte 0x3 1. "CARD_INSERTION,This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit." "0,1" newline bitfld.byte 0x3 0. "CARD_INTERRUPT,This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status register.This bit can be set to 1 if FN_WUS [Wake Up Support] in CIS is set to 1." "0,1" group.word 0x2C++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_clock_control,This register is used to program the Clock frequency select. generator select. Clock enable. Internal Clock state fields" hexmask.word.byte 0x0 8.--15. 1. "SDCLK_FRQSEL,This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register. Only the following.." newline bitfld.word 0x0 6.--7. "SDCLK_FRQSEL_UPBITS,Bit 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select." "0,1,2,3" newline bitfld.word 0x0 5. "CLKGEN_SEL,This bit is used to select the clock generator mode in SDCLK Frequency Select. If the Programmable Clock Mode is supported [non-zero value is set to Clock Multiplier in the Capabilities register] this bit attribute is RW and if not.." "0,1" newline bitfld.word 0x0 3. "PLL_ENA,This bit is added from Version 4.10 for Host Controller using PLL. This feature allows Host Controller to initialize clock generator in two steps: by Internal Clock Enable and PLL Enable and to minimize output latency [ex. SDCLK/RCLK D0lane].." "0,1" newline bitfld.word 0x0 2. "SD_CLK_ENA,The HC shall stop SDCLK when writing this bit to 0. SDCLK frequency Select can be changed when this bit is 0. Then the HC shall maintain the same clock frequency until SDCLK is stopped [Stop at SDCLK = 0]. If the HC detects the No Card state .." "0,1" newline rbitfld.word 0x0 1. "INT_CLK_STABLE,This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1. Note: This is useful when using PLL for a clock.." "0,1" newline bitfld.word 0x0 0. "INT_CLK_ENA,This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still registers shall be able to be read and written. Clock starts to oscillate when this.." "0,1" group.byte 0x2E++0x1 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_timeout_control,The register sets the Data Timeout counter value" hexmask.byte 0x0 0.--3. 1. "COUNTER_VALUE,This value determines the interval by which DAT line time-outs are detected. Refer to the Data Time-out Error in the Error Interrupt Status register for information on factors that dictate time-out generation. Time-out clock frequency will.." line.byte 0x1 "SDHC_WRAP__CTL_CFG__CTLCFG_software_reset,This register is used to program the software reset for data. command and for all" bitfld.byte 0x1 2. "SWRST_FOR_DAT,Only part of data circuit is reset. The following registers and bits are cleared by this bit: Buffer Data Port Register: Buffer is cleared and Initialized. Present State register: Buffer read Enable Buffer write.." "0,1" newline bitfld.byte 0x1 1. "SWRST_FOR_CMD,Software Reset For CMD Line Only part of command circuit is reset to be able to issue a command. From Version 4.10 this bit is also used to initialize UHS-II command circuit. This reset is effective only command issuing circuit [including.." "0,1" newline bitfld.byte 0x1 0. "SWRST_FOR_ALL,This reset affects the entire HC except for the card detection circuit. Register bits of type ROC RW RW1C RWAC are cleared to 0. During its initialization the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0.." "0,1" group.word 0x30++0xB line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts,This register gives the status of all the interrupts" rbitfld.word 0x0 15. "ERROR_INTR,If any of the bits in the Error Interrupt Status Register are set then this bit is set. Therefore the HD can test for an error by checking this bit first. In UHS-II mode is enabled if any of the bits in the UHS-II Error.." "0,1" newline bitfld.word 0x0 14. "BOOT_COMPLETE,This status is set if the boot operation gets terminated. '0' Boot operation is not terminated '1' Boot operation is terminated" "0,1" newline bitfld.word 0x0 13. "RCV_BOOT_ACK,This status is set if the boot acknowledge is received from device. '0' Boot ack not recieved '1' Boot ack is recieved" "0,1" newline rbitfld.word 0x0 12. "RETUNING_EVENT,This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer [not large block count] can be completed.." "0,1" newline rbitfld.word 0x0 11. "INTC,This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_C interrupt factor." "0,1" newline rbitfld.word 0x0 10. "INTB,This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_B interrupt factor." "0,1" newline rbitfld.word 0x0 9. "INTA,This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_A interrupt factor. NOTE : INT_A INT_B and INT_C are to be implemented based on the.." "0,1" newline rbitfld.word 0x0 8. "CARD_INTR,When this status has been set and the Host Driver needs to start this interrupt service Card Interrupt Status Enable in the Normal Interrupt Status Enable register may be set to 0 in order to clear the card interrupt status latched in the Host.." "0,1" newline bitfld.word 0x0 7. "CARD_REM,This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card.." "0,1" newline bitfld.word 0x0 6. "CARD_INS,This status is set if the Card Inserted in the Present State register changes from 0 to 1.When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card.." "0,1" newline bitfld.word 0x0 5. "BUF_RD_READY,This status is set if the Buffer Read Enable changes from 0 to 1. Buffer Read Ready is set to 1 for every CMD19 execution in tuning procedure.In UHS-II mode this bit is set at FC [Flow Control] unit basis. '0' Not ready to.." "0,1" newline bitfld.word 0x0 4. "BUF_WR_READY,This status is set if the Buffer Write Enable changes from 0 to 1.In UHS-II mode this bit is set at FC [Flow Control] unit basis. '0' Not ready to write to buffer '1' Ready to write to buffer" "0,1" newline bitfld.word 0x0 3. "DMA_INTERRUPT,This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size regiser. '0' No DMA Interrupt '1' DMA Interrupt is generated" "0,1" newline bitfld.word 0x0 2. "BLK_GAP_EVENT,If the Stop At Block Gap Request in the BlockGap Control Register is set this bit is set. Read Transaction: This bit is set at the falling edge of the DAT Line Active Status [When the transaction is stopped at SD Bus timing. The Read.." "0,1" newline bitfld.word 0x0 1. "XFER_COMPLETE,This bit is set when a read / write transaction is completed. SD Mode Read Transaction: This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated. The first is.." "0,1" newline bitfld.word 0x0 0. "CMD_COMPLETE,SD Mode This bit is set when we get the end bit of the command response [Except Auto CMD12 and Auto CMD23] Note: Command Time-out Error has higher priority than Command Complete. If both are set to 1 it can be considered that the.." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts,This register gives the status of the error interrupts" bitfld.word 0x2 12. "HOST,Occurs when detecting ERROR in m_hresp[dma transaction]" "0,1" newline bitfld.word 0x2 11. "RESP,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register Host Controller Checks R1 or.." "0,1" newline bitfld.word 0x2 10. "TUNING,This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure [Occurrence of an error during tuning procedure is indicated by Sampling Select]. By detecting Tuning Error Host Driver needs to abort a.." "0,1" newline bitfld.word 0x2 9. "ADMA,This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register." "0,1" newline bitfld.word 0x2 8. "AUTO_CMD,Auto CMD12 and Auto CMD23 use this error status.This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. D07 is effective in case of Auto CMD12. Auto CMD Error Status register is.." "0,1" newline bitfld.word 0x2 7. "CURR_LIMIT,By setting the SD Bus Power bit in the Power Control Register the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function it can be protected from an Illegal card by stopping power supply to the card in.." "0,1" newline bitfld.word 0x2 6. "DATA_ENDBIT,Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status." "0,1" newline bitfld.word 0x2 5. "DATA_CRC,Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 010." "0,1" newline bitfld.word 0x2 4. "DATA_TIMEOUT,Occurs when detecting one of following timeout conditions: 1. Busy Timeout for R1b R5b type. 2. Busy Timeout after Write CRC status 3. Write CRC status Timeout 4. Read Data Timeout." "0,1" newline bitfld.word 0x2 3. "CMD_INDEX,Occurs if a Command Index error occurs in the Command Response." "0,1" newline bitfld.word 0x2 2. "CMD_ENDBIT,Occurs when detecting that the end bit of a command response is 0." "0,1" newline bitfld.word 0x2 1. "CMD_CRC,Command CRC Error is generated in two cases. 1. If a response is returned and the Command Time-out Error is set to 0 this bit is set to 1 when detecting a CRT error in the command response 2. The HC detects a CMD line conflict by.." "0,1" newline bitfld.word 0x2 0. "CMD_TIMEOUT,Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK.." "0,1" line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts_ena,This register is used to enable the normal interrupt status register fields" rbitfld.word 0x4 15. "BIT15_FIXED0,The HC shall control error Interrupts using the Error Interrupt Status Enable register." "0,1" newline bitfld.word 0x4 14. "BOOT_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 13. "RCV_BOOT_ACK,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 12. "RETUNING_EVENT,0 - Masked 1 - Enabled" "0,1" newline bitfld.word 0x4 11. "INTC,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent.." "0,1" newline bitfld.word 0x4 10. "INTB,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent.." "0,1" newline bitfld.word 0x4 9. "INTA,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent.." "0,1" newline bitfld.word 0x4 8. "CARD_INTERRUPT,If this bit is set to 0 the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The HD may clear the Card Interrupt Status Enable before.." "0,1" newline bitfld.word 0x4 7. "CARD_REMOVAL,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 6. "CARD_INSERTION,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 5. "BUF_RD_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 4. "BUF_WR_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 3. "DMA_INTERRUPT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 2. "BLK_GAP_EVENT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 1. "XFER_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 0. "CMD_COMPLETE,'0' Masked '1' Enabled" "0,1" line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts_ena,This register is used to enable the Error Interrupt Status register fields" bitfld.word 0x6 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3" newline bitfld.word 0x6 12. "HOST,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 11. "RESP,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 10. "TUNING,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 9. "ADMA,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 8. "AUTO_CMD,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 7. "CURR_LIMIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 6. "DATA_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 5. "DATA_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 4. "DATA_TIMEOUT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 3. "CMD_INDEX,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 2. "CMD_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 1. "CMD_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 0. "CMD_TIMEOUT,'0' Masked '1' Enabled" "0,1" line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sig_ena,This register is used to enable the Normal Interrupt Signal register" rbitfld.word 0x8 15. "BIT15_FIXED0,The HD shall control error Interrupts using the Error Interrupt Signal Enable register." "0,1" newline bitfld.word 0x8 14. "BOOT_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 13. "RCV_BOOT_ACK,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 12. "RETUNING_EVENT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 11. "INTC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 10. "INTB,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 9. "INTA,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 8. "CARD_INTERRUPT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 7. "CARD_REMOVAL,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 6. "CARD_INSERTION,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 5. "BUF_RD_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 4. "BUF_WR_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 3. "DMA_INTERRUPT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 2. "BLK_GAP_EVENT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 1. "XFER_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 0. "CMD_COMPLETE,'0' Masked '1' Enabled" "0,1" line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sig_ena,This register is used to enable Error Interrupt Signal register" bitfld.word 0xA 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3" newline bitfld.word 0xA 12. "HOST,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 11. "RESP,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 10. "TUNING,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 9. "ADMA,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 8. "AUTO_CMD,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 7. "CURR_LIMIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 6. "DATA_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 5. "DATA_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 4. "DATA_TIMEOUT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 3. "CMD_INDEX,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 2. "CMD_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 1. "CMD_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 0. "CMD_TIMEOUT,'0' Masked '1' Enabled" "0,1" rgroup.word 0x3C++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_autocmd_err_sts,This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD 23" bitfld.word 0x0 7. "CMD_NOT_ISSUED,Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error [D04- D01] in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23." "0,1" newline bitfld.word 0x0 5. "RESP,This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or Auto CMD23. This status should be ignored if any bit of D00 to D04 is set to 1." "0,1" newline bitfld.word 0x0 4. "INDEX,Occurs if the Command Index error occurs in response to a command." "0,1" newline bitfld.word 0x0 3. "ENDBIT,Occurs when detecting that the end bit of command response is 0." "0,1" newline bitfld.word 0x0 2. "CRC,Occurs when detecting a CRC error in the command response." "0,1" newline bitfld.word 0x0 1. "TIMEOUT,Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command.If this bit is set to 1 the other error status bits [D04 - D02] are meaningless." "0,1" newline bitfld.word 0x0 0. "ACMD12_NOT_EXEC,If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot issue Auto CMD12 to stop memory multiple block.." "0,1" group.word 0x3E++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control2,This register is used to program UHS Select Mode.UHS Select Mode.Driver Strength Select.Execute Tuning.Sampling Clock Select.Asynchronous Interrupt Enable and Preset value enable" bitfld.word 0x0 15. "PRESET_VALUE_ENA,Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation it is difficult to determine these parameters in the Standard Host Driver. When Preset.." "0,1" newline bitfld.word 0x0 14. "ASYNCH_INTR_ENA,This bit can be set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode [and zero is.." "0,1" newline bitfld.word 0x0 13. "BIT64_ADDRESSING,This field is effective when Host Version 4.00 Enable is set to 1. Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory. Whether 32-bit or 64-bit is determined by OS installed in a host.." "0,1" newline bitfld.word 0x0 12. "HOST_VER40_ENA,This bit selects either Version 3.00 compatible mode or Ver4.mode. In Version 4.00 support of 64-bit System Addressing is modified. All DMAs support 64-bit System Addressing. UHS-II supported Host Driver shall enable this bit. In Version.." "0,1" newline bitfld.word 0x0 11. "CMD23_ENA,In memory card initialization Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]. If the card supports CMD23 [SCR[33]=1] this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3.." "0,1" newline bitfld.word 0x0 10. "ADMA2_LEN_MODE,This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit." "0,1" newline bitfld.word 0x0 9. "DRIVER_STRENGTH2,This is the programmed Drive STrength output and Bit[2] of the sdhccore_drivestrength value." "0,1" newline bitfld.word 0x0 8. "UHS2_INTF_ENABLE,This bit is used to enable UHS-II Interface. Before trying to start UHS-II initialization this bit shall be set to 1. Before trying to start SD mode initialization this bit shall be set to 0. This bit is used to enable UHS-II IF.." "0,1" newline bitfld.word 0x0 7. "SAMPLING_CLK_SELECT,This bit is set by tuning procedure when Execute Tuning is cleared. Writing 1 to this bit is meaningless and ignored. Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Host Controller.." "0,1" newline bitfld.word 0x0 6. "EXECUTE_TUNING,This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to Sampling Clock Select. Tuning procedure is aborted by writing 0 for more detail about tuning.." "0,1" newline bitfld.word 0x0 4.--5. "DRIVER_STRENGTH1,Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling this field is not effective. This field can be set depends on Driver Type A C and D support bits in the Capabilities register. This bit depends.." "0,1,2,3" newline bitfld.word 0x0 3. "V1P8_SIGNAL_ENA,This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within.." "?,1: SDR50" newline bitfld.word 0x0 0.--2. "UHS_MODE_SELECT,This field is used to select one of UHS-I modes or UHS-II mode.In case of UHS-I mode this field is effective when 1.8V Signal-ing Enable is set to 1. In case of UHS-II mode 1.8V Signaling Enable shall be set to 0. Setting of this field.." "0,1,2,3,4,5,6,7" rgroup.quad 0x40++0xF line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_capabilities,This register provides the HD with information specific to the HC implementation. The HC may implement these values as fixed or loaded from flash memory during power on initializa-tion." bitfld.quad 0x0 63. "HS400_SUPPORT,1 HS400 is Supported 0 HS400 is Not Supported" "0,1" newline bitfld.quad 0x0 60. "VDD2_1P8_SUPPORT,This field indicates that support of VDD2 on Host system." "0,1" newline bitfld.quad 0x0 59. "ADMA3_SUPPORT,This field indicates that support of ADMA3 on Host Controller." "0,1" newline bitfld.quad 0x0 57. "SPI_BLK_MODE,This field indicates whether SPI Block Mode is supported or not." "0,1" newline bitfld.quad 0x0 56. "SPI_SUPPORT,This field indicates whether SPI Mode is supported or not." "0,1" newline hexmask.quad.byte 0x0 48.--55. 1. "CLOCK_MULTIPLIER,This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. 'FF' Clock Multiplier M = 256.." newline bitfld.quad 0x0 46.--47. "RETUNING_MODES,This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver. '00' Mode 1 '01' Mode 2 '10' Mode 3 '11' Reserved. There are two.." "0,1,2,3" newline bitfld.quad 0x0 45. "TUNING_FOR_SDR50,If this bit is set to 1 this Host Controller requires tuning to operate SDR50. [Tuning is always required to operate SDR104]. '0' '1'" "0,1" newline hexmask.quad.byte 0x0 40.--43. 1. "RETUNING_TIMER_CNT,This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h - Get information via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds ------.." newline bitfld.quad 0x0 38. "DRIVERD_SUPPORT,This bit indicates support of Driver Type D for 1.8 Signaling. '0' Driver Type D is Not supported '1' Driver Type D is supported" "0,1" newline bitfld.quad 0x0 37. "DRIVERC_SUPPORT,This bit indicates support of Driver Type C for 1.8 Signaling. '0' Driver Type C is Not supported '1' Driver Type C is supported" "0,1" newline bitfld.quad 0x0 36. "DRIVERA_SUPPORT,This bit indicates support of Driver Type A for 1.8 Signaling. '0' Driver Type A is Not supported '1' Driver Type A is supported" "0,1" newline bitfld.quad 0x0 35. "UHS2_SUPPORT,This bit indicates whether Host controller supports UHS-II. If this bit is set to 1 1.8V VDD2 Support shall be set to 1 [Host Sys- tem shall support VDD2 power supply]. 1 UHS-II is Supported 0 UHS-II is Not Supported" "0,1" newline bitfld.quad 0x0 34. "DDR50_SUPPORT,This bit indicates whether DDR50 is supported or not." "0,1" newline bitfld.quad 0x0 33. "SDR104_SUPPORT,This bit indicates whether SDR104 is supported or not.SDR104 requires tuning." "0,1" newline bitfld.quad 0x0 32. "SDR50_SUPPORT,If SDR104 is supported this bit shall be set to 1. Bit 40 indicates whether SDR50 requires tuning or not." "0,1" newline bitfld.quad 0x0 30.--31. "SLOT_TYPE,This field indicates usage of a slot by a specific Host System. [A host controller register set is defined perslot.] Embedded slot for one device [01b] means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot.." "0,1,2,3" newline bitfld.quad 0x0 29. "ASYNCH_INTR_SUPPORT,Refer to SDIO Specification Version 3.00 about asynchronous interrupt." "0,1" newline bitfld.quad 0x0 28. "ADDR_64BIT_SUPPORT_V3,IMeaning of this bit is different depends on Versions [Refer to Table 2-35 for more details]. Host Controller Version 3.00 and Ver4.10 use this bit as 64-bit System Address support for V3 mode. Host Con- troller Version 4.00 uses.." "0,1" newline bitfld.quad 0x0 27. "ADDR_64BIT_SUPPORT_V4,This bit is added from Version 4.10. Set-ting 1 to this bit indicates that the Host Controller supports 64-bit System Addressing of Version 4 mode [Refer to Table 2-35 for the summary of 64-bit sys-tem address support].. When.." "0,1" newline bitfld.quad 0x0 26. "VOLT_1P8_SUPPORT,This bit indicates whether the HC supports 1.8V." "0,1" newline bitfld.quad 0x0 25. "VOLT_3P0_SUPPORT,This bit indicates whether the HC supports 3.0V." "0,1" newline bitfld.quad 0x0 24. "VOLT_3P3_SUPPORT,This bit indicates whether the HC supports 3.3V." "0,1" newline bitfld.quad 0x0 23. "SUSP_RES_SUPPORT,This bit indicates whether the HC supports Suspend / Resume functionality. If this bit is 0 the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend / Resume commands." "0,1" newline bitfld.quad 0x0 22. "SDMA_SUPPORT,This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly.Version 4.10 Host Controller shall support SDMA if ADMA2 is supported." "0,1" newline bitfld.quad 0x0 21. "HIGH_SPEED_SUPPORT,This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz [for SD]/ 20MHz to 52MHz [for MMC]." "0,1" newline bitfld.quad 0x0 19. "ADMA2_SUPPORT,'0' ADMA2 Not Supported '1' ADMA2 Supported" "0,1" newline bitfld.quad 0x0 18. "BUS_8BIT_SUPPORT,This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when Slot Type is set to 10b. In this case refer to Bus Width Preset in the Shared Bus resister." "0,1" newline bitfld.quad 0x0 16.--17. "MAX_BLK_LENGTH,This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below." "0,1,2,3" newline hexmask.quad.byte 0x0 8.--15. 1. "BASE_CLK_FREQ,[1]6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1MHz. The supported clock range is 10MHz to 63MHz. '11xx xxxxb' Not.." newline bitfld.quad 0x0 7. "TIMEOUT_CLK_UNIT,This bit shows the unit of base clock frequency used to detect Data Timeout Error." "0,1" newline hexmask.quad.byte 0x0 0.--5. 1. "TIMEOUT_CLK_FREQ,This bit shows the base clock frequency used to detect Data Timeout Error. '000000' Get Information via another method 'not 0' 1KHz to 63KHz/1MHz to 63MHz" line.quad 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_max_current_cap,This register indicates maximum current capability for each voltage" hexmask.quad.byte 0x8 32.--39. 1. "VDD2_1P8V,Maximum Current for 1.8V VDD2" newline hexmask.quad.byte 0x8 16.--23. 1. "VDD1_1P8V,Maximum Current for 1.8V VDD1" newline hexmask.quad.byte 0x8 8.--15. 1. "VDD1_3P0V,Maximum Current for 3.0V VDD1" newline hexmask.quad.byte 0x8 0.--7. 1. "VDD1_3P3V,Maximum Current for 3.3V VDD1" wgroup.word 0x50++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_ACMD_Err_Sts,This register is not physically implemented. rather it is an address where Auto CMD Error Status register can be written." bitfld.word 0x0 7. "CMD_NOT_ISS,Force Event for Command Not Issued by AUTO CMD12 Error." "0,1" newline bitfld.word 0x0 5. "RESP,Force Event for AUTO CMD Response Error.." "0,1" newline bitfld.word 0x0 4. "INDEX,Force Event for AUTO CMD Index Error.." "0,1" newline bitfld.word 0x0 3. "ENDBIT,Force Event for AUTO CMD End Bit Error." "0,1" newline bitfld.word 0x0 2. "CRC,Force Event for AUTO CMD Timeout Error." "0,1" newline bitfld.word 0x0 1. "TIMEOUT,Force Event for AUTO CMD Timeout Error." "0,1" newline bitfld.word 0x0 0. "ACMD_NOT_EXEC,Force Event for AUTO CMD12 Not Executed." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_Err_Int_Sts,This register is not physically implemented. rather it is an address where Error Interrupt Status register can be written." bitfld.word 0x2 12. "HOST,Force Event for Host Error" "0,1" newline bitfld.word 0x2 11. "RESP,Force Event for Response Error" "0,1" newline bitfld.word 0x2 10. "TUNING,Force Event for Tuning Error." "0,1" newline bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error." "0,1" newline bitfld.word 0x2 8. "AUTO_CMD,Force Event for Auto CMD Error." "0,1" newline bitfld.word 0x2 7. "CURR_LIM,Force Event for Current Limit Error." "0,1" newline bitfld.word 0x2 6. "DAT_ENDBIT,Force Event for Data End Bit Error." "0,1" newline bitfld.word 0x2 5. "DAT_CRC,Force Event for Data CRC Error." "0,1" newline bitfld.word 0x2 4. "DAT_TIMEOUT,Force Event for Data Timeout Error." "0,1" newline bitfld.word 0x2 3. "CMD_INDEX,Force Event for Command Index Error" "0,1" newline bitfld.word 0x2 2. "CMD_ENDBIT,Force Event for Command End Bit Error." "0,1" newline bitfld.word 0x2 1. "CMD_CRC,Force Event for Command CRC Error." "0,1" newline bitfld.word 0x2 0. "CMD_TIMEOUT,Force Event for CMD Timeout Error." "0,1" rgroup.byte 0x54++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_err_status,When the ADMA Error interrupt occur. this register holds the ADMA State in ADMA Error States field and ADMA System Address holds address around the error descriptor" bitfld.byte 0x0 2. "ADMA_LENGTH_ERR,This error occurs in the following 2 cases. While Block Count Enable being set the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. Total data length can not be.." "0,1" newline bitfld.byte 0x0 0.--1. "ADMA_ERR_STATE,This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates 10 because ADMA never stops in this state. D01 D00 : ADMA Error State when error occurred Contents of SYS_SDR.." "0,1,2,3" group.quad 0x58++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_sys_address,This register contains the physical address used for ADMA data transfer" hexmask.quad 0x0 0.--63. 1. "ADMA_ADDR,The 32-bit addressing Host Driver uses lower 32-bit of this register [upper 32-bit should be set to 0] and shall program Descriptor Table on 32-bit boundary andset 32-bit boundary address to this register. DMA2/3 ignores lower 2-bit of this.." rgroup.word 0x60++0xF line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value0,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x0 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value1,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x2 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value2,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x4 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x4 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x4 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value3,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x6 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x6 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x6 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value4,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x8 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x8 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x8 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value5,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0xA 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0xA 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0xA 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value6,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0xC 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0xC 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0xC 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0xE "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value7,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0xE 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0xE 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0xE 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." rgroup.word 0x72++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value8,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x0 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value10,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x2 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." group.quad 0x78++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma3_desc_address,The start address of Integrated DMA Descriptor is set to this register." hexmask.quad 0x0 0.--63. 1. "INTG_DESC_ADDR,The start address of Integrated DMA Descriptor is set to this register. Writing to a specific address starts ADMA3 depends on 32-bit/64-bit address-ing. The ADMA3 fetches one Descriptor Address and increments this field to indicate the.." group.word 0x80++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_size,This register is used to configure the number of bytes in a data block" bitfld.word 0x0 12.--14. "SDMA_BUF_BOUNDARY,When system memory is managed by paging SDMA data transfer is performed in unit of paging. A page size of sys-tem memory management is set to this field. Host Controller generates the DMA Interrupt at the page boundary and.." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--11. 1. "XFER_BLK_SIZE,This register specifies the block size of data packet. SD Memory Card uses a fixed block size of 512 bytes. Vari-able block size may be used for SDIO. The maximum value is 2048 Bytes because CRC16 covers up to 2048 bytes. This register is.." group.long 0x84++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_count,This register is used to configure the number of data blocks" hexmask.long 0x0 0.--31. 1. "XFER_BLK_COUNT,This register is effective when Data Present is set to 1 in UHS-II Command register and is enabled when Block Count Enable is set to 1 and Block / Byte Mode is set to 0 in the UHS-II Transfer Mode register. Data transfer stops when the.." group.byte 0x88++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command_pkt,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes. The command length varies depends on a Command Packet type. The length is specified by the UHS-II Command register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,UHS-II Command Packet image is set to this register.The command length varies depends on a Command Packet type." group.word 0x9C++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_xfer_mode,This register is used to control the operations of data transfers" bitfld.word 0x0 15. "DUPLEX_SELECT,Use of 2 lane half duplex mode is determined by Host Driver." "0,1" newline bitfld.word 0x0 14. "EBSY_WAIT,This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution. Busy is expected for CCMD with R1b/R5b type and DCMD with data transfer.If this bit is set to 1 Host Controller waits receiving of.." "0,1" newline bitfld.word 0x0 8. "RESP_INTR_DIS,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0 and waits Command.." "0,1" newline bitfld.word 0x0 7. "RESP_ERR_CHK_ENA,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver.Only R1 or R5 can be checked. If Host Driver checks response error this bit is set to 0 and Response.." "0,1" newline bitfld.word 0x0 6. "RESP_TYPE,When response error check is enabled this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO. Error Statuses Checked in R1 Bit31 OUT_OF_RANGE.." "0,1" newline bitfld.word 0x0 5. "BYTE_MODE,This bit specifies whether data transfer is in byte mode or block mode when Data Present is set to 1. This bit is effective to a command with data trans-fer." "0,1" newline bitfld.word 0x0 4. "DATA_XFER_DIR,This bit specifies direction of data trans-fer when Data Present is set to 1. This bit is effective to a command with data transfer. 0 - Read [Card to Host] 1 - Write [Host to Card]" "0,1" newline bitfld.word 0x0 1. "BLK_CNT_ENA,This bit specifies whether data transfer usesUHS-II Block Count register. If this bit is set to 1 data transfer is terminated by Block Count. Setting to UHS-II Block Count register shall be equivalent to TLEN in UHS-II Command Packet.." "0,1" newline bitfld.word 0x0 0. "DMA_ENA,This bit selects whether DMA is used or not and is effective to a command with data transfer. One of DMA types is selected by DMA Select in the Host Control 1 register." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command,This register is used to program the Command for host controller" hexmask.word.byte 0x2 8.--12. 1. "PKT_LENGTH,A command packet length which is set in the UHS-II Command Packet register is set to this register. 00011b - 00000b - 3-0 Bytes [Not used] 00100b - 4 Bytes .......... ...... 10100b - 20 Bytes.." newline bitfld.word 0x2 6.--7. "CMD_TYPE,This field is used to distinguish a spe-cific command like abort command. If this field is set to 00b the UHS-II RES Packet is stored in UHS-II Response register [0B3h-0A0h]. To avoid overwrit-ing the UHS-II Response register when this filed.." "0,1,2,3" newline bitfld.word 0x2 5. "DATA_PRESENT,This bit specifies whether the command is accompanied by data packet." "0,1" newline bitfld.word 0x2 2. "SUB_COMMAND,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17].When issuing a main command this bit is set to 0 and when issuing a sub com-mand this bit is set to 1. Setting of this bit is checked.." "0,1" rgroup.byte 0xA0++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_response,This register is used to store received UHS-II RES Packet image" hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xB4++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message_select,This register is used to access internal buffer" bitfld.byte 0x0 0.--1. "MSG_SEL,Host Controller holds 4 MSG packets in FIFO buffer.One of 4 MSGs can be read from the UHS-II MSG register [0BB-0B8h] by setting this register.[Assumed for debug usage.] '00' The latest MSG '01' One MSG before '10' Two MSGs.." "0,1,2,3" rgroup.long 0xB8++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message,This register is used to access internal buffer" hexmask.long.byte 0x0 24.--31. 1. "MSG_BYTE3,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." newline hexmask.long.byte 0x0 16.--23. 1. "MSG_BYTE2,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." newline hexmask.long.byte 0x0 8.--15. 1. "MSG_BYTE1,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_BYTE0,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." group.word 0xBC++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_intr_status,This register shows receipt of INT MSG from which device" hexmask.word 0x0 0.--15. 1. "DEV_INT_STS,This register shows receipt of INT MSG from which device and is effective when INT MSG Enable is set to 1 in the UHS- II Device Select register. On receiving INT MSG from a device Host Controller saves the INT MSG to UHS-II Device Interrupt.." group.byte 0xBE++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_select,UHS-II Device Select Register" bitfld.byte 0x0 7. "INT_MSG_ENA,This bit enables receipt of INT MSG. If this bit is set to 1 receipt of INT MSG is informed by Card Interrupt in the Nor-mal Interrupt Status register. If this bit is set to 0 Host Con-troller ignores receipt of INT MSG and may not set the.." "0,1" newline hexmask.byte 0x0 0.--3. 1. "DEV_SEL,Host Controller holds an INT MSG packet per device. One of INT MSGs [up to 15] can be selected by this field and read from the UHS-II Device Interrupt Code Register [0BFh]. This field is effective when INT MSG Enable is set to 1. The.." rgroup.byte 0xBF++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_int_code,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register." hexmask.byte 0x0 0.--7. 1. "DEV_INTR,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register. Host Controller holds an INT MSG packet per device. One of INT MSGs [Code length is 1 byte] up to 15 can be read from this register by.." group.word 0xC0++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_software_reset,UHS-II Software Reset Register" bitfld.word 0x0 1. "HOST_SDTRAN_RESET,Host Driver set this bit to 1 to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs. This bit is cleared automatically at completionof SD-TRAN reset. If CMD0 is issued SD-TRAN Initial- ization sequence from.." "0,1" newline bitfld.word 0x0 0. "HOST_FULL_RESET,On issuing FULL_RESET CCMD Host Driver set this bit to 1 to reset Host Controller. This bit is cleared auto-matically at completion of Host Controller reset. Initial- ization sequence from PHY Initialization is required to use UHS-II.." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_timer_control,UHS-II Timeout Control Register" hexmask.word.byte 0x2 4.--7. 1. "DEADLOCK_TIMEOUT_CTR,This value determines the deadlock period while host expecting to receive a packet [1 second]. Tim-eout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register prevent.." newline hexmask.word.byte 0x2 0.--3. 1. "CMDRESP_TIMEOUT_CTR,This value determines the interval between com-mand packet and response packet [5ms]. Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When set-ting this register prevent inadvertent.." group.long 0xC4++0xB line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts,This register gives the status of all UHS-II interrupts" hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECFIC_ERR,Vendor may use this field for vendor specific error status. '0' Interrupt is not generated '1' Vendor Specific Error" newline bitfld.long 0x0 17. "DEADLOCK_TIMEOUT,Setting of this bit means that deadlock timeout occurs. Host expects to receive a packet but not received in a specified timeout [1 second]. Timeout value is determined by the setting of Timeout Counter Value for Deadlock in UHS-II Timer.." "0,1" newline bitfld.long 0x0 16. "CMD_RESP_TIMEOUT,Setting of this bit means that RES Packet timeout occurs. Host expects to receive RES packet but not received in a specified timeout [5ms]. Timeout value is determined by the setting of Timeout Counter Value for CMD_RES in UHS-II Timer.." "0,1" newline bitfld.long 0x0 15. "ADMA2_ADMA3,Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode. ADMA2/3 Error Status is indicated to the ADMA Error Status [054h] which is defined in the Host spec 3.00." "0,1" newline bitfld.long 0x0 8. "EBSY,On receiving EBSY packet if the packet indicates an error this bit is set to 1. Setting of this bit also sets Error Interrupt and Transfer Completer together in the Normal Interrupt Status register. This error check is effective for a command with.." "0,1" newline bitfld.long 0x0 7. "UNRECOVERABLE,Setting of this bit means that Unrecoverable Error is set in a packet from a device." "0,1" newline bitfld.long 0x0 5. "TID,Setting of this bit means that TID Error occurs." "0,1" newline bitfld.long 0x0 4. "FRAMING,Setting of this bit means that Framing Error occurs during a packet receiving." "0,1" newline bitfld.long 0x0 3. "CRC,Setting of this bit means that CRC Error occurs during a packet receiving." "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Setting of this bit means that Retry Counter Expired Error occurs during data transfer.If this bit is set either Framing Error or CRC Error in this register shall be set." "0,1" newline bitfld.long 0x0 1. "RESP_PKT,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to1 in the UHS- II Transfer Mode register Host Controller.." "0,1" newline bitfld.long 0x0 0. "HEADER,Setting of this bit means that Header Error occurs in a received packet." "0,1" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts_ena,This register is used to enable the UHS-II Error Interrupt Status register fields" hexmask.long.byte 0x4 27.--31. 1. "VENDOR_SPECFIC,Setting this bit to 1 enables setting of Vendor Specific Error bit in the UHS-II Error Interrupt Status register. 0h - Status is Disabled 1h - Status is Enabled" newline bitfld.long 0x4 17. "DEADLOCK_TIMEOUT,Setting this bit to 1 enables setting of Timeout for Dead lock bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 16. "CMD_RESP_TIMEOUT,Setting this bit to 1 enables setting of Timeout for CMD_RES bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 15. "ADMA2_ADMA3,Setting this bit to 1 enables setting of ADMA2/3 Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 8. "EBSY,Setting this bit to 1 enables setting of EBSY Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 7. "UNRECOVERABLE,Setting this bit to 1 enables setting of Unrecoverable Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 5. "TID,Setting this bit to 1 enables setting of TID Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 4. "FRAMING,Setting this bit to 1 enables setting of Framing Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 3. "CRC,Setting this bit to 1 enables setting of CRC Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 2. "RETRY_EXPIRED,Setting this bit to 1 enables setting of Retry Expired bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 1. "RESP_PKT,Setting this bit to 1 enables setting of RES Packet Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 0. "HEADER,Setting this bit to 1 enables setting of Header Error bit in the UHS-II Error Interrupt Status Register." "0,1" line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sig_ena,This register is used to generate UHS-II Interrupt signals" hexmask.long.byte 0x8 27.--31. 1. "VENDOR_SPECFIC,Setting of a bit to 1 in this field enables generating interrupt signal when corre-spondent bit of Vendor Specific Error is set in the UHS-II Error Interrupt Status Register. 0h - Interrupt Signal is Disabled 1h -.." newline bitfld.long 0x8 17. "DEADLOCK_TIMEOUT,Setting this bit to 1 enables generating interrupt signal when Timeout for Dead lock bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 16. "CMD_RESP_TIMEOUT,Setting this bit to 1 enables generating interrupt signal when Timeout for CMD_RES bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 15. "ADMA2_ADMA3,Setting this bit to 1 enables generating interrupt signal when ADMA2/3 Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 8. "EBSY,Setting this bit to 1 enables generating interrupt signal when EBSY Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 7. "UNRECOVERABLE,Setting this bit to 1 enables generating interrupt signal when Unrecoverable Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 5. "TID,Setting this bit to 1 enables generating interrupt signal when TID Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 4. "FRAMING,Setting this bit to 1 enables generating interrupt signal when Framing Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 3. "CRC,Setting this bit to 1 enables generating interrupt signal when CRC Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 2. "RETRY_EXPIRED_SIG_ENA,Setting this bit to 1 enables generating interrupt signal when Retry Expired bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 1. "RESP_PKT,Setting this bit to 1 enables generating interrupt signal when RES Packet Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 0. "HEADER,Setting this bit to 1 enables generating interrupt signal when Header Error bit is set in the UHS-II Error Interrupt Status Register." "0,1" rgroup.word 0xE0++0x9 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_settings_ptr,This register is pointer for UHS-II settings." hexmask.word 0x0 0.--15. 1. "UHS2_SETTINGS_PTR,Pointer for UHS-II Settings Register" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_capabilities_ptr,This register is pointer for UHS-II Capabilities Register." hexmask.word 0x2 0.--15. 1. "UHS2_CAPABILITIES_PTR,Pointer for UHS-II Capabilities Register" line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_test_ptr,This register is pointer for UHS-II Test Register." hexmask.word 0x4 0.--15. 1. "UHS2_TEST_PTR,Pointer for UHS-II Test Register" line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_shared_bus_ctrl_ptr,This register is pointer for UHS-II Shared Bus Control Register." hexmask.word 0x6 0.--15. 1. "SHARED_BUS_CTRL_PTR,Pointer for Shared Bus Control Register" line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_specfic_ptr,This register is pointer for UHS-II Vendor Specific Pointer Register." hexmask.word 0x8 0.--15. 1. "VENDOR_SPECFIC_PTR,Pointer for Vendor Specific Area" group.long 0xF4++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_boot_timeout_control,This is used to program the boot timeout value counter" hexmask.long 0x0 0.--31. 1. "DATA_TIMEOUT_CNT,This value determines the interval by which DAT line time-outs are detected during boot operation for eMMC4.4 card.The value is in number of sd clock." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_register,Vendor register added for autogate sdclk. cmd11 power down timer. enhancedstrobe and eMMC hardware reset" bitfld.long 0x4 16. "AUTOGATE_SDCLK,If this bit is set SD CLK will be gated automatically when there is no transfer. This is applicable only for Embedded Device" "0,1" newline hexmask.long.word 0x4 2.--15. 1. "CMD11_PD_TIMER,cmd11 power-down timer value" newline bitfld.long 0x4 1. "EMMC_HW_RESET,Hardware reset signal is generared for eMMC card when this bit is set" "0,1" newline bitfld.long 0x4 0. "ENHANCED_STROBE,This bit enables the enhanced strobe logic of the Host Controller" "0,1" rgroup.word 0xFC++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_slot_int_sts,This register is used to read the interrupt signal for each slot." hexmask.word.byte 0x0 0.--7. 1. "INTR_SIG,These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_host_controller_ver,This register is used to read the vendor version number and specification version number" hexmask.word.byte 0x2 8.--15. 1. "VEN_VER_NUM,The Vendor Version Number is set to 0x10 [1.0]" newline hexmask.word.byte 0x2 0.--7. 1. "SPEC_VER_NUM,This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version. 00h - SD Host Controller Specification Version 1.00 01h - SD Host Controller Specification Version 2.00 Including the.." group.long 0x100++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_settings,Start Address of General settings is pointed by Pointer for UHS-II Setting Register." hexmask.long.byte 0x0 8.--13. 1. "NUMLANES,The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices. 2 Lanes FD mode is mandatory and the others modes are optional. 0000b - 2 Lanes FD or 2L-HD 0001b -.." newline bitfld.long 0x0 0. "POWER_MODE,This field determines either Fast mode or Low Power mode.Host and all devices connected to the host shall be set to the same mode." "0,1" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_settings,Start Address of PHY settings is pointed by Pointer for UHS-II Setting Register." hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field. 0h - 8 x16 LSS 1h - 8 x 1 LSS 2h - 8 x 2 LSS 3h - 8 x 3 LSS ...... ......" newline hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ......" newline bitfld.long 0x4 15. "HIBERNATE_ENA,After checking card capability of Hibernate mode if all devices support Hibernate mode this bit may be set. This bit determines whether Host remains in Dormant state or goes to Hibernate state. In Hibernate mode VDD1 Power may be off." "0,1" newline bitfld.long 0x4 6.--7. "SPEED_RANGE,PLL multiplier is selected by this field.Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State. '00' Range A [Default] '01' Range B '10' Reserved '11' Reserved" "0,1,2,3" group.quad 0x108++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_settings,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Setting Register." hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field. 00h - No Gap 01h - 1 LSS 02h - 2 LSS 03h - 3 LSS ...... ...... FFh - 255.." newline bitfld.quad 0x0 16.--17. "RETRY_COUNT,Data Burst retry count is set to this field. '00' Retry Disabled '01' 1 time '10' 2 times '11' 3 times" "0,1,2,3" newline hexmask.quad.byte 0x0 8.--15. 1. "HOST_NFCU,Host Driver sets the number of blocks in Data Burst [Flow Control] to this field.The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices. Setting 1 to 4 blocks is recommended.." rgroup.long 0x110++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_cap,Start Address of General Capabilities is pointed by Pointer for UHS-II Host Capabilities Register." bitfld.long 0x0 22.--23. "CORECFG_UHS2_BUS_TOPLOGY,This field indicates one of bus topologies configured by a Host system. '00' P2P Connection '01' Ring Connection '10' HUB Connection '11' HUB is connected in Ring" "0,1,2,3" newline hexmask.long.byte 0x0 18.--21. 1. "CORECFG_UHS2_MAX_DEVICES,This field indicates the maximum number of devices supported by the Host Controller. 0h - Not used 1h - 1 Devices 2h - 2 Devices ..... ....... Fh - 15 Devices" newline bitfld.long 0x0 16.--17. "DEVICE_TYPE,This field indicates device type configured by a Host system. '00' Removable Card[P2P] '01' Embedded Devices '10' Embedded Devices+Removable Card '11' Reserved" "0,1,2,3" newline bitfld.long 0x0 14. "CFG_64BIT_ADDRESSING,This field indicates support of 64-bit addressing by the Host Controller. '0' 32-bit Addressing is supported '1' 32-bit and 64-bit Addressing is supported" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "NUM_LANES,This field indicates support of lanes by the Host Controller.0 mean not supported and 1 means supported. D08 - 2L-HD D09 - 2D1U-FD D10 - 1D2U-FD D11 - 2D2U-FD D12 - Reserved D13 - Reserved" newline hexmask.long.byte 0x0 4.--7. 1. "GAP,This field indicates the maximum capability of host power supply for a group configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -Not used 1h - 360 mW 2h - 720 mW ....." newline hexmask.long.byte 0x0 0.--3. 1. "DAP,This field indicates the maximum capability of host power supply for a device configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -360 mW [Default] 1h - 360 mW 2h - 720 mW.." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_cap,Start Address of PHY Capabilities is pointed by Pointer for UHS-II Host Capabilities Register." hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,This field indicates the minimum N_LSS_DIR required by the Host Controller. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ...... Fh - 4 x 15 LSS" newline hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,This field indicates the minimum N_LSS_SYN required by the Host Controller. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ...... Fh - 4 x 15 LSS" newline bitfld.long 0x4 6.--7. "SPEED_RANGE,This field indicates supported Speed Range by the Host Controller '00' Range A [Default] '01' Range A and Range B '10' Reserved '11' Reserved" "0,1,2,3" rgroup.quad 0x118++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_cap,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Capabilities Register." hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,This field indicates the minimum number of data gap[DIDL] supported by the Host Controller. 00h - No Gap 01h - 1 LSS 02h - 2 LSS 03h - 3 LSS ...... ...... FFh - 255 LSS" newline hexmask.quad.word 0x0 20.--31. 1. "MAX_BLK_LENGTH,This field indicates maximum block length by the Host Controller. 000h - Not Used 001h - 1 byte 002h - 2 bytes ...... ...... 200h - 512 bytes ...... ......" newline hexmask.quad.byte 0x0 8.--15. 1. "N_FCU,This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller.This value is determined by supported buffer size. 00h - 256 Blocks 01h - 1 Block 02h - 2 Block 03h - 3 Block.." wgroup.long 0x120++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_force_UHSII_Err_Int_Sts,This register is not physically implemented. rather it is an address where UHS-II Error Interrupt Status register can be written." hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECIFIC,Force Event for Vendor Specific Error 0h - Not Affected 1h - Vendor Specific Error Status is set" newline bitfld.long 0x0 17. "TIMEOUT_DEADLOCK,Setting this bit forces the Host Controller to set Timeout for Deadlock in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 16. "TIMEOUT_CMD_RES,Setting this bit forces the Host Controller to set Timeout for CMD_RES in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 15. "ADMA,Setting this bit forces the Host Controller to set ADMA Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 8. "EBSY,Setting this bit forces the Host Controller to set EBSY Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 7. "UNRECOVERABLE,Setting this bit forces the Host Controller to set Unrecover-able Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 5. "TID,Setting this bit forces the Host Controller to set TID Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 4. "FRAMING,Setting this bit forces the Host Controller to set Framing Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 3. "CRC,Setting this bit forces the Host Controller to set CRC Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Setting this bit forces the Host Controller to set Retry Expired in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 1. "RES_PKT,Setting this bit forces the Host Controller to set RES Packet Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 0. "HEADER,Setting this bit forces the Host Controller to set Header Error in the UHS-II Error Interrupt Status register." "0,1" rgroup.long 0x200++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_version,This register provides information about the version of the eMMC CQ standard which is 285 implemented by the CQE. in BCD format. The current version is rev 5.1" hexmask.long.byte 0x0 8.--11. 1. "EMMC_MAJOR_VER_NUM,eMMC Major Version Number [digit left of decimal point] in BCD format" newline hexmask.long.byte 0x0 4.--7. 1. "EMMC_MINOR_VER_NUM,eMMC Minor Version Number [digit right of decimal point] in BCD format" newline hexmask.long.byte 0x0 0.--3. 1. "EMMC_VERSION_SUFFIX,eMMC Version Suffix [2nd digit right of decimal point] in BCD format" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_capabilities,This register is reserved for capability indication." hexmask.long.byte 0x4 12.--15. 1. "CF_MUL,Internal Timer Clock Frequency Multiplier [ITCFMUL] ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the SQS polling period. See ITCFVAL definition for details." newline hexmask.long.word 0x4 0.--9. 1. "CF_VAL,Internal Timer Clock Frequency Value [ITCFVAL] TCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the polling period when using periodic SEND_QUEUE_ STATUS [CMD13] polling." group.long 0x208++0x27 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_config,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time." bitfld.long 0x0 12. "DCMD_ENA,Direct Command [DCMD] Enable This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor or a Direct Command Task Descriptor. CQE uses this bit when a task is issued in slot.." "0: Task descriptor in slot #31 is a Data Transfer..,1: Task descriptor in slot #31 is a DCMD Task.." newline bitfld.long 0x0 8. "TASK_DESC_SIZE,Task Descriptor Size This bit indicates whether the task descriptor size is 128 bits or 64 bits as detailed in Data Structures section. This bit can only be configured when Command Queueing Enable bit is 0 [command queueing is.." "0: Task descriptor size is 64 bits,1: Task descriptor size is 128 bits" newline bitfld.long 0x0 0. "CQ_ENABLE,Command Queueing Enable Software shall write 1 this bit when in order to enable command queueing mode [i.e. enable CQE]. When this bit is 0 CQE is disabled and software controls the eMMC bus using the legacy eMMC host controller." "0,1" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_control,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time." bitfld.long 0x4 8. "CLEAR_ALL_TASKS,Clear All Tasks Software shall write 1 this bit when it wants to clear all the tasks sent to the device. This bit can only be written when CQE is in halt state [i.e.Halt bit is 1]. When software writes 1 the value of the.." "0,1" newline bitfld.long 0x4 0. "HALT_BIT,Halt Host software shall write 1 to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus. For example issuing a Discard Task command [CMDQ_TASK_MGMT] When software writes 1 .." "0,1" line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts,This register indicates pending interrupts that require service. Each bit in this registers is asserted 296 in response a specific event. only if the respective bit is set in CQ ISTE register." bitfld.long 0x8 4. "TASK_ERROR,Task Error Interrupt [TERR] This bit is asserted when task error is detected due to invalid task descriptor" "0,1" newline bitfld.long 0x8 3. "TASK_CLEARED,Task Cleared [TCL] This status bit is asserted [if CQISTE.TCL=1] when a task clear operation is completed by CQE. The com-pleted task clear operation is either an individual task clear [CQTCLR] or clearing of all tasks [CQCTL]." "0,1" newline bitfld.long 0x8 2. "RESP_ERR_DET,Response Error Detected Interrupt [RED] This status bit is asserted [if CQISTE.RED=1] when a response is received with an error bit set in the device status field. The contents of the device status field are listed in Section.." "0,1" newline bitfld.long 0x8 1. "TASK_COMPLETE,Task Complete Interrupt [TCC] This status bit is asserted [if CQISTE.TCC=1] when atleast one of the following two conditions are met: [1] A task is completed and the INT bit is set in its Task Descriptor [2] Interrupt caused by.." "0,1" newline bitfld.long 0x8 0. "HALT_COMPLETE,Halt Complete Interrupt [HAC] This status bit is asserted [if CQISTE.HAC=1] when halt bit in CQCTL register transitions from 0 to 1 indicating that host controller has completed its current ongoing task and has entered halt state." "0,1" line.long 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts_ena,This register enables and disables the reporting of the corresponding interrupt to host soft-ware in 299 CQIS register. When a bit is set ( 1 ) and the corresponding interrupt c -ondition is active. then.." bitfld.long 0xC 4. "TASK_ERROR,Task Error Interrupt Status Enable 1 = CQIS.TERR will be set when its interrupt condition is active 0 = CQIS.TERR is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 3. "TASK_CLEARED,Task Cleared Status Enable [TCL] 1 = CQIS.TCL will be set when its interrupt condition is active 0 = CQIS.TCL is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 2. "RESP_ERR_DET,Response Error Detected Status Enable [RED] 1 = CQIS.RED will be set when its interrupt condition is active 0 = CQIS.RED is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 1. "TASK_COMPLETE,Task Complete Status Enable [TCC] 1 = CQIS.TCC will be set when its interrupt condition is active 0 = CQIS.TCC is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 0. "HALT_COMPLETE,Halt Complete Status Enable [HAC] 1 = CQIS.HAC will be set when its interrupt condition is active 0 = CQIS.HAC is disabled" "0: CQIS,1: CQIS" line.long 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sig_ena,This register enables and disables the generation of interrupts to host software. When a bit is set 304 ( 1 ) and the corresponding bit in CQIS is set. then an interrupt is gene -rated. Interrupt sources.." bitfld.long 0x10 4. "TASK_ERROR,Task Error Interrupt Signal Enable [TERR] When set and CQIS.TERR is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 3. "TASK_CLEARED,Task Cleared Signal Enable [TCL] When set and CQIS.TCL is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 2. "RESP_ERR_DET,Response Error Detected Signal Enable [TCC] When set and CQIS.RED is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 1. "TASK_COMPLETE,Task Complete Signal Enable [TCC] When set and CQIS.TCC is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 0. "HALT_COMPLETE,Halt Complete Signal Enable [HAC] When set and CQIS.HAC is asserted the CQE shall generate an interrupt" "0,1" line.long 0x14 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_coalescing,This register controls the interrupt coalescing feature." bitfld.long 0x14 31. "CQINTCOALESC_ENABLE,When set to 0 by software command responses are neither counted nor timed. Interrupts are still triggered by completion of tasks with INT=1 in the Task Descriptor. When set to 1 the interrupt coalescing mechanism is enabled.." "0,1" newline rbitfld.long 0x14 20. "IC_STATUS,This bit indicates to software whether any tasks [with INT=0] have completed and counted towards interrupt coalescing [i.e. ICSB is set if and only if IC counter > 0]. Bit Value Description 1 = At least one task completion has been.." "0: No task completions have occurred since last..,1: At least one task completion has been counted.." newline hexmask.long.byte 0x14 8.--12. 1. "CTR_THRESHOLD,Interrupt Coalescing Counter Threshold [ICCTH]: Software uses this field to configure the number of task completions [only tasks with INT=0 in the Task Descriptor] which are required in order to generate an interrupt. Counter.." newline hexmask.long.byte 0x14 0.--6. 1. "TIMEOUT_VAL,Interrupt Coalescing Timeout Value [ICTOVAL]: Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. Timer Operation: The timer is reset by.." line.long 0x18 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory." hexmask.long 0x18 0.--31. 1. "CQTDLBA_LO,Task Descriptor List Base Address [TDLBA] This register stores the LSB bits [bits 31:0] of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * [Task Descrip-tor.." line.long 0x1C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr_upbits,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory." hexmask.long 0x1C 0.--31. 1. "CQTDLBA_HI,Task Descriptor List Base Address [TDLBA] This register stores the MSB bits [bits 63:32] of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * [Task Descrip-tor.." line.long 0x20 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_door_bell,Using this register. software triggers CQE to process a new task." hexmask.long 0x20 0.--31. 1. "CQTDB_VAL,Command Queueing Task Doorbell Software shall configure TDLBA and TDLBAU and enable CQE in CQCFG before using this register. Writing 1 to bit n of this register triggers CQE to start pro-cessing the task encoded in slot n of the TDL." line.long 0x24 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_comp_notif,This register is used by CQE to notify software about completed tasks." hexmask.long 0x24 0.--31. 1. "CQTCN_VAL,CQE shall set bit n of this register [at the same time it clears bit n of CQTDBR] when a task execution is com-pleted [with success or error]. When receiving interrupt for task completion software may read this register to know which tasks.." rgroup.long 0x230++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_queue_status,This register stores the most recent value of the device s queue status." hexmask.long 0x0 0.--31. 1. "CQDQ_STS,Every time the Host controller receives a queue status register [QSR] from the device it updates this register with the response of status command i.e. the devices queue status." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_pending_tasks,This register indicates to software which tasks are queued in the device. awaiting execution." hexmask.long 0x4 0.--31. 1. "CQDP_TSKS,Bit n of this register is set if and only if QUEUED_TASK_PARAMS [CMD44] and QUEUED_TASK_ADDRESS [CMD45] were sent for this specific task and if this task hasnt been executed yet.CQE shall set this bit after receiving a successful response for.." group.long 0x238++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_clear,This register is used for removing an outstanding task in the CQE. 327. The register should be used only when CQE is in Halt state." hexmask.long 0x0 0.--31. 1. "CQTCLR,Writing 1 to bit n of this register orders CQE to clear a task which software has previously issued.This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit.When software writes 1 to a bit in this.." group.long 0x240++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config1,The register controls the when SEND_QUEUE_STATUS commands are sent." hexmask.long.byte 0x0 16.--19. 1. "CMD_BLK_CNTR,This field indicates to CQE when to send SEND_QUEUE_STATUS [CMD13] command to inquire the status of the devices task queue.A value of n means CQE shall send status command on the CMD line during the transfer of data block BLOCK_CNT-n on.." newline hexmask.long.word 0x0 0.--15. 1. "CMD_IDLE_TIMER,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS [CMD13] polling.Periodic polling is used when tasks are pending in the device but no data transfer is in progress. When a SEND_QUEUE_STATUS.." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argu-ment." hexmask.long.word 0x4 0.--15. 1. "QUEUE_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_ STATUS [CMD13] com-mand. argument. CQE shall copy this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS [CMD13] command." rgroup.long 0x248++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dcmd_response,This register is used for passing the response of a DCMD task to software." hexmask.long 0x0 0.--31. 1. "LAST_RESP,This register contains the response of the command generated by the last direct-command [DCMD] task which was sent.CQE shall update this register when it receives the response for a DCMD task. This register is considered valid only after bit 31.." group.long 0x250++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_resp_err_mask,This register controls the generation of Response Error Detection (RED) interrupt." hexmask.long 0x0 0.--31. 1. "CQRMEM,This bit is used as in interrupt mask on the device status filed which is received in R1/R1b responses.Bit Value Description [for any bit i]:1 = When a R1/R1b response is received with bit i in the device status set a RED interrupt is generated.." rgroup.long 0x254++0xF line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_err_info,This register is updated by CQE when an error occurs on data or command related to a task activity." bitfld.long 0x0 31. "DATERR_VALID,Data Transfer Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller. If a data transfer is in progress when the error is detected/indicated the bit is set to 1. If a no.." "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "DATERR_TASK_ID,Data Transfer Error Task ID This field indicates the ID of the task which was executed on the data lines when an error occurred. The field is updated if a data transfer is in progress when an error is detected by CQE or.." newline hexmask.long.byte 0x0 16.--21. 1. "DATERR_CMD_INDEX,Data Transfer Error Command Index This field indicates the index of the command which was executed on the data lines when an error occurred. The index shall be set to EXECUTE_READ_TASK[CMD46] or EXECUTE_WRITE_TASK [CMD47].." newline bitfld.long 0x0 15. "RESP_MODE_VALID,Response Mode Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller. If a command transaction is in progress when the error is detected/indicated the bit is set to 1." "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "RESP_MODE_TASK_ID,Response Mode Error Task ID This field indicates the ID of the task which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by.." newline hexmask.long.byte 0x0 0.--5. 1. "RESP_MODE_CMD_INDEX,Response Mode Error Command Index This field indicates the index of the command which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is.." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_index,This register stores the index of the last received command response." hexmask.long.byte 0x4 0.--5. 1. "LAST_CRI,This field stores the index of the last received command response. CQE shall update the value every time a com-mand response is received." line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_arg,This register stores the index of the last received command response." hexmask.long 0x8 0.--31. 1. "LAST_CRA,This field stores the argument of the last received com-mand. CQE shall update the value every time a com-mand response is received." line.long 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_cq_error_task_id,CQ Error Task ID Register" hexmask.long.byte 0xC 0.--4. 1. "TERR_ID,Task Error ID" tree.end tree "MMCSD1_ECC_AGGR_RXMEM" base ad:0x708000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MMCSD1_ECC_AGGR_TXMEM" base ad:0x709000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MMCSD1_SS_CFG" base ad:0xFA08000 rgroup.long 0x0++0x3 line.long 0x0 "REGS__SS_CFG__SSCFG_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem" hexmask.long.word 0x0 16.--31. 1. "MOD_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version" newline bitfld.long 0x0 8.--10. "MAJ_REV,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MIN_REV,Minor revision" group.long 0x10++0x37 line.long 0x0 "REGS__SS_CFG__SSCFG_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.byte 0x0 24.--29. 1. "TUNINGCOUNT,Configures the Number of Taps (Phases) of the RX clock that is supported. The Tuning State machine uses this information to select one of the Taps (Phases) of the RX clock during the Tuning Procedure." bitfld.long 0x0 20. "ASYNCWKUPENA,Determines the Wakeup Signal Generation Mode. 0: Synchronous Wakeup Mode: The xin_clk has to be running for this mode. The Card Insertion/Removal/Interrupt events are detected synchronously on the xin_clk and the Wakeup Event is generated." "0: Synchronous Wakeup Mode: The xin_clk has to be..,1: Asyncrhonous Wakeup Mode: The xin_clk and the.." newline hexmask.long.byte 0x0 12.--15. 1. "CQFMUL,FMUL for the CQ Internal Timer Clock Frequency" hexmask.long.word 0x0 0.--9. 1. "CQFVAL,FVAL for the CQ Internal Timer Clock Frequency" line.long 0x4 "REGS__SS_CFG__SSCFG_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." bitfld.long 0x4 30.--31. "SLOTTYPE,Slot Type. Should be set based on the final product usage. 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved." "0,1,2,3" bitfld.long 0x4 29. "ASYNCHINTRSUPPORT,Asynchronous Interrupt Support. Suggested Value is 1'b1 (The Core supports monitoring of Asynchronous Interrupt)." "0,1" newline bitfld.long 0x4 26. "SUPPORT1P8VOLT,1.8V Support. Suggested Value is 1'b1 (The 1.8 Volt Switching is supported by Core). Optionally can be set to 1'b0 if the application doesn't want 1.8V switching (SD3.0)." "0,1" bitfld.long 0x4 25. "SUPPORT3P0VOLT,3.0V Support. Should be set based on whether 3.0V is supported on the SD Interface." "0,1" newline bitfld.long 0x4 24. "SUPPORT3P3VOLT,3.3V Support. Suggested Value is 1'b1 as the 3.3 V is the default voltage on the SD Interface." "0,1" bitfld.long 0x4 23. "SUSPRESSUPPORT,Suspend/Resume Support. Suggested Value is 1'b1 (The Suspend/Resume is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support Suspend/Resume Mode." "0,1" newline bitfld.long 0x4 22. "SDMASUPPORT,SDMA Support. Suggested Value is 1'b1 (The SDMA is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support SDMA Mode." "0,1" bitfld.long 0x4 21. "HIGHSPEEDSUPPORT,High Speed Support. Suggested Value is 1'b1 (The High Speed mode is supported by Core)." "0,1" newline bitfld.long 0x4 19. "ADMA2SUPPORT,ADMA2 Support. Suggested Value is 1'b1 (The ADMA2 is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support ADMA2 Mode." "0,1" bitfld.long 0x4 18. "SUPPORT8BIT,8-bit Support for Embedded Device. Suggested Value is 1'b1 (The Core supports 8-bit Interface). Optionally an be set to 1'b0 if the Application supports only 4-bit SD Interface." "0,1" newline bitfld.long 0x4 16.--17. "MAXBLKLENGTH,Max Block Length. Maximum Block Length supported by the Core/Device. 00: 512 (Bytes) 01: 1024 10: 2048 11: Reserved." "0: 512,1: 1024,?,?" hexmask.long.byte 0x4 8.--15. 1. "BASECLKFREQ,Base Clock Frequency for SD Clock. This is the frequency of the xin_clk." newline bitfld.long 0x4 7. "TIMEOUTCLKUNIT,Timeout Clock Unit. Suggested Value is 1'b0 (KHz)." "0,1" hexmask.long.byte 0x4 0.--5. 1. "TIMEOUTCLKFREQ,Timeout Clock Frequency. Suggested Value is 1 KHz. Internally the 1msec Timer is used for Timeout Detection. The 1msec Timer is generated from the xin_clk." line.long 0x8 "REGS__SS_CFG__SSCFG_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." bitfld.long 0x8 28. "SUPPORT1P8VDD2,1.8V VDD2 Support." "0,1" bitfld.long 0x8 27. "ADMA3SUPPORT,ADMA3 Support." "0,1" newline hexmask.long.byte 0x8 16.--23. 1. "CLOCKMULTIPLIER,Clock Multiplier. This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. FFh Clock Multiplier M =.." bitfld.long 0x8 14.--15. "RETUNINGMODES,Re-Tuning Modes. Should be set to 2'b00 as the Core supports only the Software Timer based Re-Tuning." "0,1,2,3" newline bitfld.long 0x8 13. "TUNINGFORSDR50,Use Tuning for SDR50. This bit should be set if the Application wants Tuning be used for SDR50 Modes. The Core operates with or with out tuning for SDR50 mode as long as the Clock can be manually tuned using tap delay." "0,1" hexmask.long.byte 0x8 8.--11. 1. "RETUNINGTIMERCNT,Timer Count for Re-Tuning. This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer." newline bitfld.long 0x8 7. "TYPE4SUPPORT,Driver Type 4 Support. This bit should be set based on whether Driver Type 4 for 1.8 Signalling is supported or not." "0,1" bitfld.long 0x8 6. "DDRIVERSUPPORT,Driver Type D Support. This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not." "0,1" newline bitfld.long 0x8 5. "CDRIVERSUPPORT,Driver Type C Support. This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not." "0,1" bitfld.long 0x8 4. "ADRIVERSUPPORT,Driver Type A Support. This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not." "0,1" newline bitfld.long 0x8 2. "DDR50SUPPORT,DDR50 Support. Suggested Value is 1'b1 (The Core supports DDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support DDR50." "0,1" bitfld.long 0x8 1. "SDR104SUPPORT,SDR104 Support. Suggested Value is 1'b1 (The Core supports SDR104 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR104." "0,1" newline bitfld.long 0x8 0. "SDR50SUPPORT,SDR50 Support. Suggested Value is 1'b1 (The Core supports SDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR50." "0,1" line.long 0xC "REGS__SS_CFG__SSCFG_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.byte 0xC 16.--23. 1. "MAXCURRENT1P8V,Maximum Current for 1.8V." hexmask.long.byte 0xC 8.--15. 1. "MAXCURRENT3P0V,Maximum Current for 3.0V." newline hexmask.long.byte 0xC 0.--7. 1. "MAXCURRENT3P3V,Maximum Current for 3.3V." line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.byte 0x10 0.--7. 1. "MAXCURRENTVDD2,Maximum Current for 1.8 V (VDD2)." line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x14 0.--12. 1. "INITPRESETVAL,Preset Value for Initialization." line.long 0x18 "REGS__SS_CFG__SSCFG_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x18 0.--12. 1. "DSPDPRESETVAL,Preset Value for Default Speed." line.long 0x1C "REGS__SS_CFG__SSCFG_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x1C 0.--12. 1. "HSPDPRESETVAL,Preset Value for High Speed." line.long 0x20 "REGS__SS_CFG__SSCFG_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x20 0.--12. 1. "SDR12PRESETVAL,Preset Value for SDR12." line.long 0x24 "REGS__SS_CFG__SSCFG_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x24 0.--12. 1. "SDR25PRESETVAL,Preset Value for SDR25." line.long 0x28 "REGS__SS_CFG__SSCFG_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x28 0.--12. 1. "SDR50PRESETVAL,Preset Value for SDR50." line.long 0x2C "REGS__SS_CFG__SSCFG_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x2C 0.--12. 1. "SDR104PRESETVAL,Preset Value for SDR104." line.long 0x30 "REGS__SS_CFG__SSCFG_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x30 0.--12. 1. "DDR50PRESETVAL,Preset Value for DDR50." line.long 0x34 "REGS__SS_CFG__SSCFG_CTL_CFG_14_REG,The Controller Config 14 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." rgroup.long 0x60++0x17 line.long 0x0 "REGS__SS_CFG__SSCFG_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." bitfld.long 0x0 31. "SDHC_CMDIDLE,Idle signal to enable S/W to gate off the clocks." "0,1" hexmask.long.word 0x0 0.--15. 1. "DMADEBUGBUS,DMA_CTRL Debug Bus." line.long 0x4 "REGS__SS_CFG__SSCFG_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x4 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL Debug Bus." line.long 0x8 "REGS__SS_CFG__SSCFG_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x8 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL Debug Bus." line.long 0xC "REGS__SS_CFG__SSCFG_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0xC 0.--15. 1. "RXDDEBUGBUS0,RXD_CTRL Debug Bus (SD CLK)." line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x10 0.--15. 1. "RXDDEBUGBUS1,RXD_CTRL Debug Bus (RX CLK)." line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x14 0.--15. 1. "TUNDEBUGBUS,TUN_CTRL Debug Bus." group.long 0x100++0x17 line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0x0 31. "IOMUX_ENABLE,IO mux enable. Set 1 for GPIO. Set 0 for eMMC/SD" "0,1" line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_CTRL_2_REG,The PHY Control 2 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." line.long 0x8 "REGS__SS_CFG__SSCFG_PHY_CTRL_3_REG,The PHY Control 3 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." line.long 0xC "REGS__SS_CFG__SSCFG_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0xC 20. "OTAPDLYENA,Output Tap Delay Enable. Enables manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." "0,1" hexmask.long.byte 0xC 12.--15. 1. "OTAPDLYSEL,Output Tap Delay Select. Manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." newline bitfld.long 0xC 9. "ITAPCHGWIN,Input Tap Change Window. It gets asserted by the controller while changing the itapdlysel. Used to gate of the RX clock during switching the clock source while tap is changing to avoid clock glitches." "0,1" bitfld.long 0xC 8. "ITAPDLYENA,Input Tap Delay Enable. This is used for the manual control of the RX clock Tap Delay in non HS200/HS400 modes." "0,1" newline hexmask.long.byte 0xC 0.--4. 1. "ITAPDLYSEL,Input Tap Delay Select. Manual control of the RX clock Tap Delay in the non HS200/HS400 modes." line.long 0x10 "REGS__SS_CFG__SSCFG_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0x10 0.--2. "CLKBUFSEL,Clock Delay Buffer Select. Selects one of the eight taps in the CLK Delay Buffer based on PVT variation." "0,1,2,3,4,5,6,7" line.long 0x14 "REGS__SS_CFG__SSCFG_PHY_CTRL_6_REG,The PHY Control 6 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." group.long 0x130++0x7 line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_STAT_1_REG,The PHY Status 1 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports. For detailed functionality of the Arasan eMMC/SD PHY status ports please refer to its specification listed in.." line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_STAT_2_REG,The PHY Status 2 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports. For detailed functionality of the Arasan eMMC/SD PHY status ports please refer to its specification listed in.." tree.end tree "MMCSD2_CTL_CFG" base ad:0xFA20000 group.word 0x0++0xF line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_lo,This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." hexmask.word 0x0 0.--15. 1. "SDMA_ADDRESS,When Host Version 4 Enable is set to 0 in the Host Control 2 register DMA uses this register as system address in only 32-bit addressing mode. Auto CMD23 cannot be used with SDMA. When Host Version 4 Enable is set to 1 SDMA uses ADMA System.." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_hi,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." hexmask.word 0x2 0.--15. 1. "SDMA_ADDRESS,This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10." line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_block_size,This register is used to configure the number of bytes in a data block" bitfld.word 0x4 12.--14. "SDMA_BUF_SIZE,To perform long DMA transfer System Address register shall be updated at every system boundary during DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at the every boundary.." "0,1,2,3,4,5,6,7" newline hexmask.word 0x4 0.--11. 1. "XFER_BLK_SIZE,This field specifies the block size for block data transfers for CMD17 CMD18 CMD24 CMD25 and CMD53. It can be accessed only if no transaction is executing [i.e after a transaction has stopped]. Read operations during transfer return an.." line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_block_count,This register is used to configure the number of data blocks" hexmask.word 0x6 0.--15. 1. "XFER_BLK_CNT,Host Controller Version 4.10 extends block count to 32-bit [Refer to Section 1.15].Selection of either 16-bit Block Count register or 32-bit Block Count register is defined as follows: [1] If Host Version 4 Enable in the Host Control 2.." line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_lo,This register contains Lower bits of SD Command Argument" hexmask.word 0x8 0.--15. 1. "CMD_ARG1,The SD Command Argument is specified as bit23-8 of Command-Format." line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_hi,This register contains higher bits of SD Command Argument" hexmask.word 0xA 0.--15. 1. "CMD_ARG1,The SD Command Argument is specified as bit39-24 of Command-Format." line.word 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_transfer_mode,This register is used to control the operations of data transfers" bitfld.word 0xC 8. "RESP_INTR_DIS,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0 and waits Command Complete.." "0,1" newline bitfld.word 0xC 7. "RESP_ERR_CHK_ENA,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked.If Host Driver checks response error this bit is set to 0 and Response Interrupt.." "0,1" newline bitfld.word 0xC 6. "RESP_TYPE,When response error check is enabled this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO." "0,1" newline bitfld.word 0xC 5. "MULTI_BLK_SEL,This bit enables multiple block data transfers." "0,1" newline bitfld.word 0xC 4. "DATA_XFER_DIR,This bit defines the direction of data transfers." "0,1" newline bitfld.word 0xC 2.--3. "AUTO_CMD_ENA,There are three methods to stop Multiple-block read and write operation. [1] Auto CMD12 Enable: Multiple-block read and write commands for memory require CMD12 to stop the operation. When this field is set to 01b the Host.." "0,1,2,3" newline bitfld.word 0xC 1. "BLK_CNT_ENA,This bit is used to enable the Block count register which is only relevant for multiple block transfers. When this bit is 0 the Block Count register is disabled which is useful in executing an infinite transfer." "0,1" newline bitfld.word 0xC 0. "DMA_ENA,DMA can be enabled only if DMA Support bit in the Capabilities register is set. If this bit is set to 1 a DMA operation shall begin when the HD writes to the upper byte of Command register [00Fh]." "0,1" line.word 0xE "SDHC_WRAP__CTL_CFG__CTLCFG_command,This register is used to program the Command for host controller" hexmask.word.byte 0xE 8.--13. 1. "CMD_INDEX,This bit shall be set to the command number [CMD0-63 ACMD0-63]." newline bitfld.word 0xE 6.--7. "CMD_TYPE,There are three types of special commands. Suspend Resume andAbort. These bits shall bet set to 00b for all other commands. Suspend Command: If the Suspend command succeeds the HC shall assume the SD Bus has been released and that it is.." "0,1,2,3" newline bitfld.word 0xE 5. "DATA_PRESENT,This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. If is set to 0 for the following: 1. Commands using only CMD line [ex. CMD52]. 2. Commands with no data transferbut using busy.." "0,1" newline bitfld.word 0xE 4. "CMD_INDEX_CHK_ENA,If this bit is set to 1 the HC shall check the index field in the response to see if it has the same value as the command index. If it is not it is reported as a Command Index Error. If this bit is set to 0 the Index field is not.." "0,1" newline bitfld.word 0xE 3. "CMD_CRC_CHK_ENA,If this bit is set to 1 the HC shall check the CRC field in the response. If an error is detected it is reported as a Command CRC Error. If this bit is set to 0 the CRC field is not checked." "0,1" newline bitfld.word 0xE 2. "SUB_CMD,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17]. When issuing a main com-mand this bit is set to 0 and when issuing a sub command this bit is set to 1. Setting of this bit is checked.." "0,1" newline bitfld.word 0xE 0.--1. "RESP_TYPE_SEL,Response Type Select." "0,1,2,3" rgroup.word 0x10++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_response,This register is used to store responses from SD Cards" hexmask.word 0x0 0.--15. 1. "CMD_RESP,R[] refers to a bit range within the response data as transmitted on the SD Bus REP[] refers to a bit range within the Response register." group.long 0x20++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_data_port,This register is used to access internal buffer" hexmask.long 0x0 0.--31. 1. "BUF_RD_DATA,The Host Controller Buffer can be accessed through this 32-bit Data Port Register." rgroup.long 0x24++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_presentstate,The Host Driver can get status of the Host Controller from this 32-bit read-only register" bitfld.long 0x0 31. "UHS2_IF_DETECTION,This status indicates whether a card supports UHS-II IF. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 regis-ter. UHS-II interface initialization is activated by setting SD Clock Enable in the.." "0,1" newline bitfld.long 0x0 30. "UHS2_IF_LANE_SYNC,This status indicates whether lane is synchronized in UHS-II mode. This status is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On detecting UHS-II Interface [D31=1] Host Controller provides SYN.." "0,1" newline bitfld.long 0x0 29. "UHS2_DORMANT,This status indicates whether UHS-II Ianes enterDormant state. This function is enabled by setting UHS-II Interface Enable to 1 in the Host Control 2 register. On issuing GO_DORMAT_STATE com-mand Go Dormant Command [111b]; is set to Command.." "0,1" newline bitfld.long 0x0 28. "SUB_COMMAND_STS,The Command register and Response register are commonly used for main command and sub command. This status is used to distinguish which response error statuses main command or sub command indicated in the Error Interrupt Status.." "0,1" newline bitfld.long 0x0 27. "CMD_NOT_ISS_BY_ERR,Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error. [Equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in the Auto CMD Error.." "0,1" newline bitfld.long 0x0 24. "SDIF_CMDIN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 23. "SDIF_DAT3IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[3]." "0,1" newline bitfld.long 0x0 22. "SDIF_DAT2IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[2]." "0,1" newline bitfld.long 0x0 21. "SDIF_DAT1IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[1]." "0,1" newline bitfld.long 0x0 20. "SDIF_DAT0IN,This status is used to check DAT line level to recover from errors and for debugging. This is especially useful in detecting the busy signal level from DAT[0]." "0,1" newline bitfld.long 0x0 19. "WRITE_PROTECT,The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin." "0,1" newline bitfld.long 0x0 18. "CARD_DETECT,This bit reflects the inverse value of the SDCD# pin. '0' No Card present [SDCD# = 1] '1' Card present [SDCD# = 0]" "0,1" newline bitfld.long 0x0 17. "CARD_STATE_STABLE,This bit is used for testing. If it is 0 the Card Detect Pin Level is not stable. If this bit is set to 1 it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this.." "0,1" newline bitfld.long 0x0 16. "CARD_INSERTED,This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt.." "0,1" newline bitfld.long 0x0 11. "BUF_RD_ENA,This status is used for non-DMA read transfers.This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1 readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the.." "0,1" newline bitfld.long 0x0 10. "BUF_WR_ENA,This status is used for non-DMA write transfers.This read only flag indicates if space is available for write data. If this bit is 1 data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written.." "0,1" newline bitfld.long 0x0 9. "RD_XFER_ACTIVE,This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: After the end bit of the read command. When writing a 1 to continue Request in the Block.." "0,1" newline bitfld.long 0x0 8. "WR_XFER_ACTIVE,This status indicates a write transfer is active. If this bit is 0 it means no valid write data exists in the HC. This bit is set in either of the following cases: After the end bit of the write command. When writing a.." "0,1" newline bitfld.long 0x0 7. "SDIF_DAT7IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 6. "SDIF_DAT6IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 5. "SDIF_DAT5IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 4. "SDIF_DAT4IN,This status is used to check DAT line level to recover from errors and for debugging." "0,1" newline bitfld.long 0x0 3. "RETUNING_REQ,Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is.." "0,1" newline bitfld.long 0x0 2. "DATA_LINE_ACTIVE,This bit indicates whether one of the DAT line on SD bus is in use." "0,1" newline bitfld.long 0x0 1. "INHIBIT_DAT,This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0 it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit [DAT] [ex. R1b R5b.." "0,1" newline bitfld.long 0x0 0. "INHIBIT_CMD,SD Mode If this bit is 0 it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register [00Fh] is written. This bit is cleared when the command response is.." "0,1" group.byte 0x28++0x3 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control1,This register is used to program DMA modes. LED Control. Data Transfer Width. High Speed Enable. Card detect test level and signal selection" bitfld.byte 0x0 7. "CD_SIG_SEL,This bit selects source for card detection. '0' SDCD# is selected [for normal use] '1' The card detect test level is selected" "0,1" newline bitfld.byte 0x0 6. "CD_TEST_LEVEL,This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. Generates [card ins or card removal] interrupt when the normal int sts enable bit is set. '0' No Card '1' Card Inserted" "0,1" newline bitfld.byte 0x0 5. "EXT_DATA_WIDTH,This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register. If a device supports 8-bit bus mode this bit may be set to 1. If this bit.." "0,1" newline bitfld.byte 0x0 3.--4. "DMA_SELECT,This field is used to select DMA type. The Host Driver shall check support of DMA modes by referring the Capabilities register. Selected DMA is enabled by DMA Enable of the Transfer Mode register in SD mode and DMA Enable of UHS-II Transfer.." "0,1,2,3" newline bitfld.byte 0x0 2. "HIGH_SPEED_ENA,This bit is optional. Before setting this bit the HD shall check the High Speed Support in the capabilities register. If this bit is set to 0 [default] the HC outputs CMD line and DAT lines at the falling edge of the SD clock [up to.." "0,1" newline bitfld.byte 0x0 1. "DATA_WIDTH,This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. This bit is not effective in UHS-II mode." "0,1" newline bitfld.byte 0x0 0. "LED_CONTROL,This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands this bit can be set during all transactions. It is not necessary to change for each.." "0,1" line.byte 0x1 "SDHC_WRAP__CTL_CFG__CTLCFG_power_control,This register is used to program the SD Bus power and voltage level" bitfld.byte 0x1 5.--7. "UHS2_VOLTAGE,This field determines supply voltage range to VDD2. This field can be set to 101b if 1.8V VDD2 Support in the Capabilities register is set to 1. '000' VDD2 Not supported '001'- '011' Reserved '100' Reserved for 1.2V.." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x1 4. "UHS2_POWER,Setting this bit enables providing VDD2. '0' Power Off '1' Power On" "0,1" newline bitfld.byte 0x1 1.--3. "SD_BUS_VOLTAGE,By setting these bits the HD selects the voltage level for the SD card. Before setting this register the HD shall check the voltage support bits in the capabilities register. If an unsupported voltage is selected the Host System shall.." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x1 0. "SD_BUS_POWER,Before setting this bit the SD host driver shall set SD Bus Voltage Select. If the HC detects the No Card State this bit shall be cleared. If this bit is cleared the Host Control-ler should immediately stop driving CMD and DAT[3:0].." "0,1" line.byte 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_block_gap_control,This register is used to program the block gap request. read wait control and interrupt at block gap" bitfld.byte 0x2 7. "BOOT_ACK_ENA,To check for the boot acknowledge in boot operation." "0,1" newline bitfld.byte 0x2 6. "ALT_BOOT_MODE,To start boot code access in alternative mode." "0,1" newline bitfld.byte 0x2 5. "BOOT_ENABLE,To start boot code access." "0,1" newline bitfld.byte 0x2 4. "SPI_MODE,SPI mode enable bit." "0,1" newline bitfld.byte 0x2 3. "INTRPT_AT_BLK_GAP,This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt.." "0,1" newline bitfld.byte 0x2 2. "RDWAIT_CTRL,The read wait function is optional for SDIO cards. If the card supports read wait set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data which.." "0,1" newline bitfld.byte 0x2 1. "CONTINUE,This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap set Stop At block Gap Request to 0 and set this bit to restart the transfer. The Host Controller automatically.." "0,1" newline bitfld.byte 0x2 0. "STOP_AT_BLK_GAP,This bit is used to stop executing a transaction at the next block gap for non- DMA SDMA and ADMA transfers. Until the transfer complete is set to 1 indicating a transfer completion the HD shall leave this bit set to 1. Clearing both the.." "0,1" line.byte 0x3 "SDHC_WRAP__CTL_CFG__CTLCFG_wakeup_control,This register is used to program the wakeup functionality" bitfld.byte 0x3 2. "CARD_REMOVAL,This bit enables wakeup event via Card removal assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit." "0,1" newline bitfld.byte 0x3 1. "CARD_INSERTION,This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit." "0,1" newline bitfld.byte 0x3 0. "CARD_INTERRUPT,This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status register.This bit can be set to 1 if FN_WUS [Wake Up Support] in CIS is set to 1." "0,1" group.word 0x2C++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_clock_control,This register is used to program the Clock frequency select. generator select. Clock enable. Internal Clock state fields" hexmask.word.byte 0x0 8.--15. 1. "SDCLK_FRQSEL,This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register. Only the following.." newline bitfld.word 0x0 6.--7. "SDCLK_FRQSEL_UPBITS,Bit 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select." "0,1,2,3" newline bitfld.word 0x0 5. "CLKGEN_SEL,This bit is used to select the clock generator mode in SDCLK Frequency Select. If the Programmable Clock Mode is supported [non-zero value is set to Clock Multiplier in the Capabilities register] this bit attribute is RW and if not.." "0,1" newline bitfld.word 0x0 3. "PLL_ENA,This bit is added from Version 4.10 for Host Controller using PLL. This feature allows Host Controller to initialize clock generator in two steps: by Internal Clock Enable and PLL Enable and to minimize output latency [ex. SDCLK/RCLK D0lane].." "0,1" newline bitfld.word 0x0 2. "SD_CLK_ENA,The HC shall stop SDCLK when writing this bit to 0. SDCLK frequency Select can be changed when this bit is 0. Then the HC shall maintain the same clock frequency until SDCLK is stopped [Stop at SDCLK = 0]. If the HC detects the No Card state .." "0,1" newline rbitfld.word 0x0 1. "INT_CLK_STABLE,This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1. Note: This is useful when using PLL for a clock.." "0,1" newline bitfld.word 0x0 0. "INT_CLK_ENA,This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still registers shall be able to be read and written. Clock starts to oscillate when this.." "0,1" group.byte 0x2E++0x1 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_timeout_control,The register sets the Data Timeout counter value" hexmask.byte 0x0 0.--3. 1. "COUNTER_VALUE,This value determines the interval by which DAT line time-outs are detected. Refer to the Data Time-out Error in the Error Interrupt Status register for information on factors that dictate time-out generation. Time-out clock frequency will.." line.byte 0x1 "SDHC_WRAP__CTL_CFG__CTLCFG_software_reset,This register is used to program the software reset for data. command and for all" bitfld.byte 0x1 2. "SWRST_FOR_DAT,Only part of data circuit is reset. The following registers and bits are cleared by this bit: Buffer Data Port Register: Buffer is cleared and Initialized. Present State register: Buffer read Enable Buffer write.." "0,1" newline bitfld.byte 0x1 1. "SWRST_FOR_CMD,Software Reset For CMD Line Only part of command circuit is reset to be able to issue a command. From Version 4.10 this bit is also used to initialize UHS-II command circuit. This reset is effective only command issuing circuit [including.." "0,1" newline bitfld.byte 0x1 0. "SWRST_FOR_ALL,This reset affects the entire HC except for the card detection circuit. Register bits of type ROC RW RW1C RWAC are cleared to 0. During its initialization the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0.." "0,1" group.word 0x30++0xB line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts,This register gives the status of all the interrupts" rbitfld.word 0x0 15. "ERROR_INTR,If any of the bits in the Error Interrupt Status Register are set then this bit is set. Therefore the HD can test for an error by checking this bit first. In UHS-II mode is enabled if any of the bits in the UHS-II Error.." "0,1" newline bitfld.word 0x0 14. "BOOT_COMPLETE,This status is set if the boot operation gets terminated. '0' Boot operation is not terminated '1' Boot operation is terminated" "0,1" newline bitfld.word 0x0 13. "RCV_BOOT_ACK,This status is set if the boot acknowledge is received from device. '0' Boot ack not recieved '1' Boot ack is recieved" "0,1" newline rbitfld.word 0x0 12. "RETUNING_EVENT,This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer [not large block count] can be completed.." "0,1" newline rbitfld.word 0x0 11. "INTC,This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_C interrupt factor." "0,1" newline rbitfld.word 0x0 10. "INTB,This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_B interrupt factor." "0,1" newline rbitfld.word 0x0 9. "INTA,This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_A interrupt factor. NOTE : INT_A INT_B and INT_C are to be implemented based on the.." "0,1" newline rbitfld.word 0x0 8. "CARD_INTR,When this status has been set and the Host Driver needs to start this interrupt service Card Interrupt Status Enable in the Normal Interrupt Status Enable register may be set to 0 in order to clear the card interrupt status latched in the Host.." "0,1" newline bitfld.word 0x0 7. "CARD_REM,This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card.." "0,1" newline bitfld.word 0x0 6. "CARD_INS,This status is set if the Card Inserted in the Present State register changes from 0 to 1.When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card.." "0,1" newline bitfld.word 0x0 5. "BUF_RD_READY,This status is set if the Buffer Read Enable changes from 0 to 1. Buffer Read Ready is set to 1 for every CMD19 execution in tuning procedure.In UHS-II mode this bit is set at FC [Flow Control] unit basis. '0' Not ready to.." "0,1" newline bitfld.word 0x0 4. "BUF_WR_READY,This status is set if the Buffer Write Enable changes from 0 to 1.In UHS-II mode this bit is set at FC [Flow Control] unit basis. '0' Not ready to write to buffer '1' Ready to write to buffer" "0,1" newline bitfld.word 0x0 3. "DMA_INTERRUPT,This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size regiser. '0' No DMA Interrupt '1' DMA Interrupt is generated" "0,1" newline bitfld.word 0x0 2. "BLK_GAP_EVENT,If the Stop At Block Gap Request in the BlockGap Control Register is set this bit is set. Read Transaction: This bit is set at the falling edge of the DAT Line Active Status [When the transaction is stopped at SD Bus timing. The Read.." "0,1" newline bitfld.word 0x0 1. "XFER_COMPLETE,This bit is set when a read / write transaction is completed. SD Mode Read Transaction: This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated. The first is.." "0,1" newline bitfld.word 0x0 0. "CMD_COMPLETE,SD Mode This bit is set when we get the end bit of the command response [Except Auto CMD12 and Auto CMD23] Note: Command Time-out Error has higher priority than Command Complete. If both are set to 1 it can be considered that the.." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts,This register gives the status of the error interrupts" bitfld.word 0x2 12. "HOST,Occurs when detecting ERROR in m_hresp[dma transaction]" "0,1" newline bitfld.word 0x2 11. "RESP,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register Host Controller Checks R1 or.." "0,1" newline bitfld.word 0x2 10. "TUNING,This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure [Occurrence of an error during tuning procedure is indicated by Sampling Select]. By detecting Tuning Error Host Driver needs to abort a.." "0,1" newline bitfld.word 0x2 9. "ADMA,This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register." "0,1" newline bitfld.word 0x2 8. "AUTO_CMD,Auto CMD12 and Auto CMD23 use this error status.This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. D07 is effective in case of Auto CMD12. Auto CMD Error Status register is.." "0,1" newline bitfld.word 0x2 7. "CURR_LIMIT,By setting the SD Bus Power bit in the Power Control Register the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function it can be protected from an Illegal card by stopping power supply to the card in.." "0,1" newline bitfld.word 0x2 6. "DATA_ENDBIT,Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status." "0,1" newline bitfld.word 0x2 5. "DATA_CRC,Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 010." "0,1" newline bitfld.word 0x2 4. "DATA_TIMEOUT,Occurs when detecting one of following timeout conditions: 1. Busy Timeout for R1b R5b type. 2. Busy Timeout after Write CRC status 3. Write CRC status Timeout 4. Read Data Timeout." "0,1" newline bitfld.word 0x2 3. "CMD_INDEX,Occurs if a Command Index error occurs in the Command Response." "0,1" newline bitfld.word 0x2 2. "CMD_ENDBIT,Occurs when detecting that the end bit of a command response is 0." "0,1" newline bitfld.word 0x2 1. "CMD_CRC,Command CRC Error is generated in two cases. 1. If a response is returned and the Command Time-out Error is set to 0 this bit is set to 1 when detecting a CRT error in the command response 2. The HC detects a CMD line conflict by.." "0,1" newline bitfld.word 0x2 0. "CMD_TIMEOUT,Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK.." "0,1" line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts_ena,This register is used to enable the normal interrupt status register fields" rbitfld.word 0x4 15. "BIT15_FIXED0,The HC shall control error Interrupts using the Error Interrupt Status Enable register." "0,1" newline bitfld.word 0x4 14. "BOOT_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 13. "RCV_BOOT_ACK,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 12. "RETUNING_EVENT,0 - Masked 1 - Enabled" "0,1" newline bitfld.word 0x4 11. "INTC,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent.." "0,1" newline bitfld.word 0x4 10. "INTB,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent.." "0,1" newline bitfld.word 0x4 9. "INTA,If this bit is set to 0 the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent.." "0,1" newline bitfld.word 0x4 8. "CARD_INTERRUPT,If this bit is set to 0 the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The HD may clear the Card Interrupt Status Enable before.." "0,1" newline bitfld.word 0x4 7. "CARD_REMOVAL,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 6. "CARD_INSERTION,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 5. "BUF_RD_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 4. "BUF_WR_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 3. "DMA_INTERRUPT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 2. "BLK_GAP_EVENT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 1. "XFER_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x4 0. "CMD_COMPLETE,'0' Masked '1' Enabled" "0,1" line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts_ena,This register is used to enable the Error Interrupt Status register fields" bitfld.word 0x6 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3" newline bitfld.word 0x6 12. "HOST,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 11. "RESP,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 10. "TUNING,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 9. "ADMA,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 8. "AUTO_CMD,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 7. "CURR_LIMIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 6. "DATA_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 5. "DATA_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 4. "DATA_TIMEOUT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 3. "CMD_INDEX,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 2. "CMD_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 1. "CMD_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x6 0. "CMD_TIMEOUT,'0' Masked '1' Enabled" "0,1" line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sig_ena,This register is used to enable the Normal Interrupt Signal register" rbitfld.word 0x8 15. "BIT15_FIXED0,The HD shall control error Interrupts using the Error Interrupt Signal Enable register." "0,1" newline bitfld.word 0x8 14. "BOOT_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 13. "RCV_BOOT_ACK,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 12. "RETUNING_EVENT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 11. "INTC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 10. "INTB,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 9. "INTA,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 8. "CARD_INTERRUPT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 7. "CARD_REMOVAL,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 6. "CARD_INSERTION,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 5. "BUF_RD_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 4. "BUF_WR_READY,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 3. "DMA_INTERRUPT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 2. "BLK_GAP_EVENT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 1. "XFER_COMPLETE,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0x8 0. "CMD_COMPLETE,'0' Masked '1' Enabled" "0,1" line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sig_ena,This register is used to enable Error Interrupt Signal register" bitfld.word 0xA 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3" newline bitfld.word 0xA 12. "HOST,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 11. "RESP,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 10. "TUNING,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 9. "ADMA,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 8. "AUTO_CMD,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 7. "CURR_LIMIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 6. "DATA_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 5. "DATA_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 4. "DATA_TIMEOUT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 3. "CMD_INDEX,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 2. "CMD_ENDBIT,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 1. "CMD_CRC,'0' Masked '1' Enabled" "0,1" newline bitfld.word 0xA 0. "CMD_TIMEOUT,'0' Masked '1' Enabled" "0,1" rgroup.word 0x3C++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_autocmd_err_sts,This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD 23" bitfld.word 0x0 7. "CMD_NOT_ISSUED,Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error [D04- D01] in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23." "0,1" newline bitfld.word 0x0 5. "RESP,This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or Auto CMD23. This status should be ignored if any bit of D00 to D04 is set to 1." "0,1" newline bitfld.word 0x0 4. "INDEX,Occurs if the Command Index error occurs in response to a command." "0,1" newline bitfld.word 0x0 3. "ENDBIT,Occurs when detecting that the end bit of command response is 0." "0,1" newline bitfld.word 0x0 2. "CRC,Occurs when detecting a CRC error in the command response." "0,1" newline bitfld.word 0x0 1. "TIMEOUT,Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command.If this bit is set to 1 the other error status bits [D04 - D02] are meaningless." "0,1" newline bitfld.word 0x0 0. "ACMD12_NOT_EXEC,If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot issue Auto CMD12 to stop memory multiple block.." "0,1" group.word 0x3E++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control2,This register is used to program UHS Select Mode.UHS Select Mode.Driver Strength Select.Execute Tuning.Sampling Clock Select.Asynchronous Interrupt Enable and Preset value enable" bitfld.word 0x0 15. "PRESET_VALUE_ENA,Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation it is difficult to determine these parameters in the Standard Host Driver. When Preset.." "0,1" newline bitfld.word 0x0 14. "ASYNCH_INTR_ENA,This bit can be set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode [and zero is.." "0,1" newline bitfld.word 0x0 13. "BIT64_ADDRESSING,This field is effective when Host Version 4.00 Enable is set to 1. Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory. Whether 32-bit or 64-bit is determined by OS installed in a host.." "0,1" newline bitfld.word 0x0 12. "HOST_VER40_ENA,This bit selects either Version 3.00 compatible mode or Ver4.mode. In Version 4.00 support of 64-bit System Addressing is modified. All DMAs support 64-bit System Addressing. UHS-II supported Host Driver shall enable this bit. In Version.." "0,1" newline bitfld.word 0x0 11. "CMD23_ENA,In memory card initialization Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]. If the card supports CMD23 [SCR[33]=1] this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3.." "0,1" newline bitfld.word 0x0 10. "ADMA2_LEN_MODE,This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit." "0,1" newline bitfld.word 0x0 9. "DRIVER_STRENGTH2,This is the programmed Drive STrength output and Bit[2] of the sdhccore_drivestrength value." "0,1" newline bitfld.word 0x0 8. "UHS2_INTF_ENABLE,This bit is used to enable UHS-II Interface. Before trying to start UHS-II initialization this bit shall be set to 1. Before trying to start SD mode initialization this bit shall be set to 0. This bit is used to enable UHS-II IF.." "0,1" newline bitfld.word 0x0 7. "SAMPLING_CLK_SELECT,This bit is set by tuning procedure when Execute Tuning is cleared. Writing 1 to this bit is meaningless and ignored. Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Host Controller.." "0,1" newline bitfld.word 0x0 6. "EXECUTE_TUNING,This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to Sampling Clock Select. Tuning procedure is aborted by writing 0 for more detail about tuning.." "0,1" newline bitfld.word 0x0 4.--5. "DRIVER_STRENGTH1,Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling this field is not effective. This field can be set depends on Driver Type A C and D support bits in the Capabilities register. This bit depends.." "0,1,2,3" newline bitfld.word 0x0 3. "V1P8_SIGNAL_ENA,This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within.." "?,1: SDR50" newline bitfld.word 0x0 0.--2. "UHS_MODE_SELECT,This field is used to select one of UHS-I modes or UHS-II mode.In case of UHS-I mode this field is effective when 1.8V Signal-ing Enable is set to 1. In case of UHS-II mode 1.8V Signaling Enable shall be set to 0. Setting of this field.." "0,1,2,3,4,5,6,7" rgroup.quad 0x40++0xF line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_capabilities,This register provides the HD with information specific to the HC implementation. The HC may implement these values as fixed or loaded from flash memory during power on initializa-tion." bitfld.quad 0x0 63. "HS400_SUPPORT,1 HS400 is Supported 0 HS400 is Not Supported" "0,1" newline bitfld.quad 0x0 60. "VDD2_1P8_SUPPORT,This field indicates that support of VDD2 on Host system." "0,1" newline bitfld.quad 0x0 59. "ADMA3_SUPPORT,This field indicates that support of ADMA3 on Host Controller." "0,1" newline bitfld.quad 0x0 57. "SPI_BLK_MODE,This field indicates whether SPI Block Mode is supported or not." "0,1" newline bitfld.quad 0x0 56. "SPI_SUPPORT,This field indicates whether SPI Mode is supported or not." "0,1" newline hexmask.quad.byte 0x0 48.--55. 1. "CLOCK_MULTIPLIER,This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. 'FF' Clock Multiplier M = 256.." newline bitfld.quad 0x0 46.--47. "RETUNING_MODES,This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver. '00' Mode 1 '01' Mode 2 '10' Mode 3 '11' Reserved. There are two.." "0,1,2,3" newline bitfld.quad 0x0 45. "TUNING_FOR_SDR50,If this bit is set to 1 this Host Controller requires tuning to operate SDR50. [Tuning is always required to operate SDR104]. '0' '1'" "0,1" newline hexmask.quad.byte 0x0 40.--43. 1. "RETUNING_TIMER_CNT,This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h - Get information via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds ------.." newline bitfld.quad 0x0 38. "DRIVERD_SUPPORT,This bit indicates support of Driver Type D for 1.8 Signaling. '0' Driver Type D is Not supported '1' Driver Type D is supported" "0,1" newline bitfld.quad 0x0 37. "DRIVERC_SUPPORT,This bit indicates support of Driver Type C for 1.8 Signaling. '0' Driver Type C is Not supported '1' Driver Type C is supported" "0,1" newline bitfld.quad 0x0 36. "DRIVERA_SUPPORT,This bit indicates support of Driver Type A for 1.8 Signaling. '0' Driver Type A is Not supported '1' Driver Type A is supported" "0,1" newline bitfld.quad 0x0 35. "UHS2_SUPPORT,This bit indicates whether Host controller supports UHS-II. If this bit is set to 1 1.8V VDD2 Support shall be set to 1 [Host Sys- tem shall support VDD2 power supply]. 1 UHS-II is Supported 0 UHS-II is Not Supported" "0,1" newline bitfld.quad 0x0 34. "DDR50_SUPPORT,This bit indicates whether DDR50 is supported or not." "0,1" newline bitfld.quad 0x0 33. "SDR104_SUPPORT,This bit indicates whether SDR104 is supported or not.SDR104 requires tuning." "0,1" newline bitfld.quad 0x0 32. "SDR50_SUPPORT,If SDR104 is supported this bit shall be set to 1. Bit 40 indicates whether SDR50 requires tuning or not." "0,1" newline bitfld.quad 0x0 30.--31. "SLOT_TYPE,This field indicates usage of a slot by a specific Host System. [A host controller register set is defined perslot.] Embedded slot for one device [01b] means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot.." "0,1,2,3" newline bitfld.quad 0x0 29. "ASYNCH_INTR_SUPPORT,Refer to SDIO Specification Version 3.00 about asynchronous interrupt." "0,1" newline bitfld.quad 0x0 28. "ADDR_64BIT_SUPPORT_V3,IMeaning of this bit is different depends on Versions [Refer to Table 2-35 for more details]. Host Controller Version 3.00 and Ver4.10 use this bit as 64-bit System Address support for V3 mode. Host Con- troller Version 4.00 uses.." "0,1" newline bitfld.quad 0x0 27. "ADDR_64BIT_SUPPORT_V4,This bit is added from Version 4.10. Set-ting 1 to this bit indicates that the Host Controller supports 64-bit System Addressing of Version 4 mode [Refer to Table 2-35 for the summary of 64-bit sys-tem address support].. When.." "0,1" newline bitfld.quad 0x0 26. "VOLT_1P8_SUPPORT,This bit indicates whether the HC supports 1.8V." "0,1" newline bitfld.quad 0x0 25. "VOLT_3P0_SUPPORT,This bit indicates whether the HC supports 3.0V." "0,1" newline bitfld.quad 0x0 24. "VOLT_3P3_SUPPORT,This bit indicates whether the HC supports 3.3V." "0,1" newline bitfld.quad 0x0 23. "SUSP_RES_SUPPORT,This bit indicates whether the HC supports Suspend / Resume functionality. If this bit is 0 the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend / Resume commands." "0,1" newline bitfld.quad 0x0 22. "SDMA_SUPPORT,This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly.Version 4.10 Host Controller shall support SDMA if ADMA2 is supported." "0,1" newline bitfld.quad 0x0 21. "HIGH_SPEED_SUPPORT,This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz [for SD]/ 20MHz to 52MHz [for MMC]." "0,1" newline bitfld.quad 0x0 19. "ADMA2_SUPPORT,'0' ADMA2 Not Supported '1' ADMA2 Supported" "0,1" newline bitfld.quad 0x0 18. "BUS_8BIT_SUPPORT,This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when Slot Type is set to 10b. In this case refer to Bus Width Preset in the Shared Bus resister." "0,1" newline bitfld.quad 0x0 16.--17. "MAX_BLK_LENGTH,This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below." "0,1,2,3" newline hexmask.quad.byte 0x0 8.--15. 1. "BASE_CLK_FREQ,[1]6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1MHz. The supported clock range is 10MHz to 63MHz. '11xx xxxxb' Not.." newline bitfld.quad 0x0 7. "TIMEOUT_CLK_UNIT,This bit shows the unit of base clock frequency used to detect Data Timeout Error." "0,1" newline hexmask.quad.byte 0x0 0.--5. 1. "TIMEOUT_CLK_FREQ,This bit shows the base clock frequency used to detect Data Timeout Error. '000000' Get Information via another method 'not 0' 1KHz to 63KHz/1MHz to 63MHz" line.quad 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_max_current_cap,This register indicates maximum current capability for each voltage" hexmask.quad.byte 0x8 32.--39. 1. "VDD2_1P8V,Maximum Current for 1.8V VDD2" newline hexmask.quad.byte 0x8 16.--23. 1. "VDD1_1P8V,Maximum Current for 1.8V VDD1" newline hexmask.quad.byte 0x8 8.--15. 1. "VDD1_3P0V,Maximum Current for 3.0V VDD1" newline hexmask.quad.byte 0x8 0.--7. 1. "VDD1_3P3V,Maximum Current for 3.3V VDD1" wgroup.word 0x50++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_ACMD_Err_Sts,This register is not physically implemented. rather it is an address where Auto CMD Error Status register can be written." bitfld.word 0x0 7. "CMD_NOT_ISS,Force Event for Command Not Issued by AUTO CMD12 Error." "0,1" newline bitfld.word 0x0 5. "RESP,Force Event for AUTO CMD Response Error.." "0,1" newline bitfld.word 0x0 4. "INDEX,Force Event for AUTO CMD Index Error.." "0,1" newline bitfld.word 0x0 3. "ENDBIT,Force Event for AUTO CMD End Bit Error." "0,1" newline bitfld.word 0x0 2. "CRC,Force Event for AUTO CMD Timeout Error." "0,1" newline bitfld.word 0x0 1. "TIMEOUT,Force Event for AUTO CMD Timeout Error." "0,1" newline bitfld.word 0x0 0. "ACMD_NOT_EXEC,Force Event for AUTO CMD12 Not Executed." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_Err_Int_Sts,This register is not physically implemented. rather it is an address where Error Interrupt Status register can be written." bitfld.word 0x2 12. "HOST,Force Event for Host Error" "0,1" newline bitfld.word 0x2 11. "RESP,Force Event for Response Error" "0,1" newline bitfld.word 0x2 10. "TUNING,Force Event for Tuning Error." "0,1" newline bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error." "0,1" newline bitfld.word 0x2 8. "AUTO_CMD,Force Event for Auto CMD Error." "0,1" newline bitfld.word 0x2 7. "CURR_LIM,Force Event for Current Limit Error." "0,1" newline bitfld.word 0x2 6. "DAT_ENDBIT,Force Event for Data End Bit Error." "0,1" newline bitfld.word 0x2 5. "DAT_CRC,Force Event for Data CRC Error." "0,1" newline bitfld.word 0x2 4. "DAT_TIMEOUT,Force Event for Data Timeout Error." "0,1" newline bitfld.word 0x2 3. "CMD_INDEX,Force Event for Command Index Error" "0,1" newline bitfld.word 0x2 2. "CMD_ENDBIT,Force Event for Command End Bit Error." "0,1" newline bitfld.word 0x2 1. "CMD_CRC,Force Event for Command CRC Error." "0,1" newline bitfld.word 0x2 0. "CMD_TIMEOUT,Force Event for CMD Timeout Error." "0,1" rgroup.byte 0x54++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_err_status,When the ADMA Error interrupt occur. this register holds the ADMA State in ADMA Error States field and ADMA System Address holds address around the error descriptor" bitfld.byte 0x0 2. "ADMA_LENGTH_ERR,This error occurs in the following 2 cases. While Block Count Enable being set the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. Total data length can not be.." "0,1" newline bitfld.byte 0x0 0.--1. "ADMA_ERR_STATE,This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates 10 because ADMA never stops in this state. D01 D00 : ADMA Error State when error occurred Contents of SYS_SDR.." "0,1,2,3" group.quad 0x58++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_sys_address,This register contains the physical address used for ADMA data transfer" hexmask.quad 0x0 0.--63. 1. "ADMA_ADDR,The 32-bit addressing Host Driver uses lower 32-bit of this register [upper 32-bit should be set to 0] and shall program Descriptor Table on 32-bit boundary andset 32-bit boundary address to this register. DMA2/3 ignores lower 2-bit of this.." rgroup.word 0x60++0xF line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value0,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x0 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value1,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x2 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value2,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x4 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x4 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x4 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value3,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x6 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x6 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x6 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value4,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x8 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x8 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x8 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0xA "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value5,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0xA 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0xA 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0xA 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value6,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0xC 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0xC 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0xC 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0xE "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value7,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0xE 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0xE 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0xE 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." rgroup.word 0x72++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value8,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x0 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x0 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x0 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value10,This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value" bitfld.word 0x2 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" newline bitfld.word 0x2 10. "CLOCK_GENSEL,This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator" "0,1" newline hexmask.word 0x2 0.--9. 1. "SDCLK_FRQSEL,10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system." group.quad 0x78++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_adma3_desc_address,The start address of Integrated DMA Descriptor is set to this register." hexmask.quad 0x0 0.--63. 1. "INTG_DESC_ADDR,The start address of Integrated DMA Descriptor is set to this register. Writing to a specific address starts ADMA3 depends on 32-bit/64-bit address-ing. The ADMA3 fetches one Descriptor Address and increments this field to indicate the.." group.word 0x80++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_size,This register is used to configure the number of bytes in a data block" bitfld.word 0x0 12.--14. "SDMA_BUF_BOUNDARY,When system memory is managed by paging SDMA data transfer is performed in unit of paging. A page size of sys-tem memory management is set to this field. Host Controller generates the DMA Interrupt at the page boundary and.." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--11. 1. "XFER_BLK_SIZE,This register specifies the block size of data packet. SD Memory Card uses a fixed block size of 512 bytes. Vari-able block size may be used for SDIO. The maximum value is 2048 Bytes because CRC16 covers up to 2048 bytes. This register is.." group.long 0x84++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_count,This register is used to configure the number of data blocks" hexmask.long 0x0 0.--31. 1. "XFER_BLK_COUNT,This register is effective when Data Present is set to 1 in UHS-II Command register and is enabled when Block Count Enable is set to 1 and Block / Byte Mode is set to 0 in the UHS-II Transfer Mode register. Data transfer stops when the.." group.byte 0x88++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command_pkt,UHS-II Command Packet image is set to this register. The maximum length is 20 bytes. The command length varies depends on a Command Packet type. The length is specified by the UHS-II Command register." hexmask.byte 0x0 0.--7. 1. "CMD_PKT_BYTE,UHS-II Command Packet image is set to this register.The command length varies depends on a Command Packet type." group.word 0x9C++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_xfer_mode,This register is used to control the operations of data transfers" bitfld.word 0x0 15. "DUPLEX_SELECT,Use of 2 lane half duplex mode is determined by Host Driver." "0,1" newline bitfld.word 0x0 14. "EBSY_WAIT,This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution. Busy is expected for CCMD with R1b/R5b type and DCMD with data transfer.If this bit is set to 1 Host Controller waits receiving of.." "0,1" newline bitfld.word 0x0 8. "RESP_INTR_DIS,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error sets this bit to 0 and waits Command.." "0,1" newline bitfld.word 0x0 7. "RESP_ERR_CHK_ENA,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver.Only R1 or R5 can be checked. If Host Driver checks response error this bit is set to 0 and Response.." "0,1" newline bitfld.word 0x0 6. "RESP_TYPE,When response error check is enabled this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO. Error Statuses Checked in R1 Bit31 OUT_OF_RANGE.." "0,1" newline bitfld.word 0x0 5. "BYTE_MODE,This bit specifies whether data transfer is in byte mode or block mode when Data Present is set to 1. This bit is effective to a command with data trans-fer." "0,1" newline bitfld.word 0x0 4. "DATA_XFER_DIR,This bit specifies direction of data trans-fer when Data Present is set to 1. This bit is effective to a command with data transfer. 0 - Read [Card to Host] 1 - Write [Host to Card]" "0,1" newline bitfld.word 0x0 1. "BLK_CNT_ENA,This bit specifies whether data transfer usesUHS-II Block Count register. If this bit is set to 1 data transfer is terminated by Block Count. Setting to UHS-II Block Count register shall be equivalent to TLEN in UHS-II Command Packet.." "0,1" newline bitfld.word 0x0 0. "DMA_ENA,This bit selects whether DMA is used or not and is effective to a command with data transfer. One of DMA types is selected by DMA Select in the Host Control 1 register." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command,This register is used to program the Command for host controller" hexmask.word.byte 0x2 8.--12. 1. "PKT_LENGTH,A command packet length which is set in the UHS-II Command Packet register is set to this register. 00011b - 00000b - 3-0 Bytes [Not used] 00100b - 4 Bytes .......... ...... 10100b - 20 Bytes.." newline bitfld.word 0x2 6.--7. "CMD_TYPE,This field is used to distinguish a spe-cific command like abort command. If this field is set to 00b the UHS-II RES Packet is stored in UHS-II Response register [0B3h-0A0h]. To avoid overwrit-ing the UHS-II Response register when this filed.." "0,1,2,3" newline bitfld.word 0x2 5. "DATA_PRESENT,This bit specifies whether the command is accompanied by data packet." "0,1" newline bitfld.word 0x2 2. "SUB_COMMAND,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17].When issuing a main command this bit is set to 0 and when issuing a sub com-mand this bit is set to 1. Setting of this bit is checked.." "0,1" rgroup.byte 0xA0++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_response,This register is used to store received UHS-II RES Packet image" hexmask.byte 0x0 0.--7. 1. "RESP_PKT_BYTE,Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command." group.byte 0xB4++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message_select,This register is used to access internal buffer" bitfld.byte 0x0 0.--1. "MSG_SEL,Host Controller holds 4 MSG packets in FIFO buffer.One of 4 MSGs can be read from the UHS-II MSG register [0BB-0B8h] by setting this register.[Assumed for debug usage.] '00' The latest MSG '01' One MSG before '10' Two MSGs.." "0,1,2,3" rgroup.long 0xB8++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message,This register is used to access internal buffer" hexmask.long.byte 0x0 24.--31. 1. "MSG_BYTE3,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." newline hexmask.long.byte 0x0 16.--23. 1. "MSG_BYTE2,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." newline hexmask.long.byte 0x0 8.--15. 1. "MSG_BYTE1,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_BYTE0,Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs [length is 4 bytes] can be read fromthis register by setting UHS-II MSG Select register. Usually 2 duplicate MSG packets are sent from/toUHS-II card. One of these 2 MSG packets.." group.word 0xBC++0x1 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_intr_status,This register shows receipt of INT MSG from which device" hexmask.word 0x0 0.--15. 1. "DEV_INT_STS,This register shows receipt of INT MSG from which device and is effective when INT MSG Enable is set to 1 in the UHS- II Device Select register. On receiving INT MSG from a device Host Controller saves the INT MSG to UHS-II Device Interrupt.." group.byte 0xBE++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_select,UHS-II Device Select Register" bitfld.byte 0x0 7. "INT_MSG_ENA,This bit enables receipt of INT MSG. If this bit is set to 1 receipt of INT MSG is informed by Card Interrupt in the Nor-mal Interrupt Status register. If this bit is set to 0 Host Con-troller ignores receipt of INT MSG and may not set the.." "0,1" newline hexmask.byte 0x0 0.--3. 1. "DEV_SEL,Host Controller holds an INT MSG packet per device. One of INT MSGs [up to 15] can be selected by this field and read from the UHS-II Device Interrupt Code Register [0BFh]. This field is effective when INT MSG Enable is set to 1. The.." rgroup.byte 0xBF++0x0 line.byte 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_int_code,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register." hexmask.byte 0x0 0.--7. 1. "DEV_INTR,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register. Host Controller holds an INT MSG packet per device. One of INT MSGs [Code length is 1 byte] up to 15 can be read from this register by.." group.word 0xC0++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_software_reset,UHS-II Software Reset Register" bitfld.word 0x0 1. "HOST_SDTRAN_RESET,Host Driver set this bit to 1 to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs. This bit is cleared automatically at completionof SD-TRAN reset. If CMD0 is issued SD-TRAN Initial- ization sequence from.." "0,1" newline bitfld.word 0x0 0. "HOST_FULL_RESET,On issuing FULL_RESET CCMD Host Driver set this bit to 1 to reset Host Controller. This bit is cleared auto-matically at completion of Host Controller reset. Initial- ization sequence from PHY Initialization is required to use UHS-II.." "0,1" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_timer_control,UHS-II Timeout Control Register" hexmask.word.byte 0x2 4.--7. 1. "DEADLOCK_TIMEOUT_CTR,This value determines the deadlock period while host expecting to receive a packet [1 second]. Tim-eout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register prevent.." newline hexmask.word.byte 0x2 0.--3. 1. "CMDRESP_TIMEOUT_CTR,This value determines the interval between com-mand packet and response packet [5ms]. Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When set-ting this register prevent inadvertent.." group.long 0xC4++0xB line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts,This register gives the status of all UHS-II interrupts" hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECFIC_ERR,Vendor may use this field for vendor specific error status. '0' Interrupt is not generated '1' Vendor Specific Error" newline bitfld.long 0x0 17. "DEADLOCK_TIMEOUT,Setting of this bit means that deadlock timeout occurs. Host expects to receive a packet but not received in a specified timeout [1 second]. Timeout value is determined by the setting of Timeout Counter Value for Deadlock in UHS-II Timer.." "0,1" newline bitfld.long 0x0 16. "CMD_RESP_TIMEOUT,Setting of this bit means that RES Packet timeout occurs. Host expects to receive RES packet but not received in a specified timeout [5ms]. Timeout value is determined by the setting of Timeout Counter Value for CMD_RES in UHS-II Timer.." "0,1" newline bitfld.long 0x0 15. "ADMA2_ADMA3,Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode. ADMA2/3 Error Status is indicated to the ADMA Error Status [054h] which is defined in the Host spec 3.00." "0,1" newline bitfld.long 0x0 8. "EBSY,On receiving EBSY packet if the packet indicates an error this bit is set to 1. Setting of this bit also sets Error Interrupt and Transfer Completer together in the Normal Interrupt Status register. This error check is effective for a command with.." "0,1" newline bitfld.long 0x0 7. "UNRECOVERABLE,Setting of this bit means that Unrecoverable Error is set in a packet from a device." "0,1" newline bitfld.long 0x0 5. "TID,Setting of this bit means that TID Error occurs." "0,1" newline bitfld.long 0x0 4. "FRAMING,Setting of this bit means that Framing Error occurs during a packet receiving." "0,1" newline bitfld.long 0x0 3. "CRC,Setting of this bit means that CRC Error occurs during a packet receiving." "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Setting of this bit means that Retry Counter Expired Error occurs during data transfer.If this bit is set either Framing Error or CRC Error in this register shall be set." "0,1" newline bitfld.long 0x0 1. "RESP_PKT,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to1 in the UHS- II Transfer Mode register Host Controller.." "0,1" newline bitfld.long 0x0 0. "HEADER,Setting of this bit means that Header Error occurs in a received packet." "0,1" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts_ena,This register is used to enable the UHS-II Error Interrupt Status register fields" hexmask.long.byte 0x4 27.--31. 1. "VENDOR_SPECFIC,Setting this bit to 1 enables setting of Vendor Specific Error bit in the UHS-II Error Interrupt Status register. 0h - Status is Disabled 1h - Status is Enabled" newline bitfld.long 0x4 17. "DEADLOCK_TIMEOUT,Setting this bit to 1 enables setting of Timeout for Dead lock bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 16. "CMD_RESP_TIMEOUT,Setting this bit to 1 enables setting of Timeout for CMD_RES bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 15. "ADMA2_ADMA3,Setting this bit to 1 enables setting of ADMA2/3 Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 8. "EBSY,Setting this bit to 1 enables setting of EBSY Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 7. "UNRECOVERABLE,Setting this bit to 1 enables setting of Unrecoverable Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 5. "TID,Setting this bit to 1 enables setting of TID Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 4. "FRAMING,Setting this bit to 1 enables setting of Framing Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 3. "CRC,Setting this bit to 1 enables setting of CRC Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 2. "RETRY_EXPIRED,Setting this bit to 1 enables setting of Retry Expired bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 1. "RESP_PKT,Setting this bit to 1 enables setting of RES Packet Error bit in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x4 0. "HEADER,Setting this bit to 1 enables setting of Header Error bit in the UHS-II Error Interrupt Status Register." "0,1" line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sig_ena,This register is used to generate UHS-II Interrupt signals" hexmask.long.byte 0x8 27.--31. 1. "VENDOR_SPECFIC,Setting of a bit to 1 in this field enables generating interrupt signal when corre-spondent bit of Vendor Specific Error is set in the UHS-II Error Interrupt Status Register. 0h - Interrupt Signal is Disabled 1h -.." newline bitfld.long 0x8 17. "DEADLOCK_TIMEOUT,Setting this bit to 1 enables generating interrupt signal when Timeout for Dead lock bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 16. "CMD_RESP_TIMEOUT,Setting this bit to 1 enables generating interrupt signal when Timeout for CMD_RES bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 15. "ADMA2_ADMA3,Setting this bit to 1 enables generating interrupt signal when ADMA2/3 Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 8. "EBSY,Setting this bit to 1 enables generating interrupt signal when EBSY Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 7. "UNRECOVERABLE,Setting this bit to 1 enables generating interrupt signal when Unrecoverable Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 5. "TID,Setting this bit to 1 enables generating interrupt signal when TID Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 4. "FRAMING,Setting this bit to 1 enables generating interrupt signal when Framing Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 3. "CRC,Setting this bit to 1 enables generating interrupt signal when CRC Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 2. "RETRY_EXPIRED_SIG_ENA,Setting this bit to 1 enables generating interrupt signal when Retry Expired bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 1. "RESP_PKT,Setting this bit to 1 enables generating interrupt signal when RES Packet Error bit is set in the UHS-II Error InterruptStatus Register." "0,1" newline bitfld.long 0x8 0. "HEADER,Setting this bit to 1 enables generating interrupt signal when Header Error bit is set in the UHS-II Error Interrupt Status Register." "0,1" rgroup.word 0xE0++0x9 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_settings_ptr,This register is pointer for UHS-II settings." hexmask.word 0x0 0.--15. 1. "UHS2_SETTINGS_PTR,Pointer for UHS-II Settings Register" line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_capabilities_ptr,This register is pointer for UHS-II Capabilities Register." hexmask.word 0x2 0.--15. 1. "UHS2_CAPABILITIES_PTR,Pointer for UHS-II Capabilities Register" line.word 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_test_ptr,This register is pointer for UHS-II Test Register." hexmask.word 0x4 0.--15. 1. "UHS2_TEST_PTR,Pointer for UHS-II Test Register" line.word 0x6 "SDHC_WRAP__CTL_CFG__CTLCFG_shared_bus_ctrl_ptr,This register is pointer for UHS-II Shared Bus Control Register." hexmask.word 0x6 0.--15. 1. "SHARED_BUS_CTRL_PTR,Pointer for Shared Bus Control Register" line.word 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_specfic_ptr,This register is pointer for UHS-II Vendor Specific Pointer Register." hexmask.word 0x8 0.--15. 1. "VENDOR_SPECFIC_PTR,Pointer for Vendor Specific Area" group.long 0xF4++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_boot_timeout_control,This is used to program the boot timeout value counter" hexmask.long 0x0 0.--31. 1. "DATA_TIMEOUT_CNT,This value determines the interval by which DAT line time-outs are detected during boot operation for eMMC4.4 card.The value is in number of sd clock." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_register,Vendor register added for autogate sdclk. cmd11 power down timer. enhancedstrobe and eMMC hardware reset" bitfld.long 0x4 16. "AUTOGATE_SDCLK,If this bit is set SD CLK will be gated automatically when there is no transfer. This is applicable only for Embedded Device" "0,1" newline hexmask.long.word 0x4 2.--15. 1. "CMD11_PD_TIMER,cmd11 power-down timer value" newline bitfld.long 0x4 1. "EMMC_HW_RESET,Hardware reset signal is generared for eMMC card when this bit is set" "0,1" newline bitfld.long 0x4 0. "ENHANCED_STROBE,This bit enables the enhanced strobe logic of the Host Controller" "0,1" rgroup.word 0xFC++0x3 line.word 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_slot_int_sts,This register is used to read the interrupt signal for each slot." hexmask.word.byte 0x0 0.--7. 1. "INTR_SIG,These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot." line.word 0x2 "SDHC_WRAP__CTL_CFG__CTLCFG_host_controller_ver,This register is used to read the vendor version number and specification version number" hexmask.word.byte 0x2 8.--15. 1. "VEN_VER_NUM,The Vendor Version Number is set to 0x10 [1.0]" newline hexmask.word.byte 0x2 0.--7. 1. "SPEC_VER_NUM,This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version. 00h - SD Host Controller Specification Version 1.00 01h - SD Host Controller Specification Version 2.00 Including the.." group.long 0x100++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_settings,Start Address of General settings is pointed by Pointer for UHS-II Setting Register." hexmask.long.byte 0x0 8.--13. 1. "NUMLANES,The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices. 2 Lanes FD mode is mandatory and the others modes are optional. 0000b - 2 Lanes FD or 2L-HD 0001b -.." newline bitfld.long 0x0 0. "POWER_MODE,This field determines either Fast mode or Low Power mode.Host and all devices connected to the host shall be set to the same mode." "0,1" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_settings,Start Address of PHY settings is pointed by Pointer for UHS-II Setting Register." hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field. 0h - 8 x16 LSS 1h - 8 x 1 LSS 2h - 8 x 2 LSS 3h - 8 x 3 LSS ...... ......" newline hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ......" newline bitfld.long 0x4 15. "HIBERNATE_ENA,After checking card capability of Hibernate mode if all devices support Hibernate mode this bit may be set. This bit determines whether Host remains in Dormant state or goes to Hibernate state. In Hibernate mode VDD1 Power may be off." "0,1" newline bitfld.long 0x4 6.--7. "SPEED_RANGE,PLL multiplier is selected by this field.Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State. '00' Range A [Default] '01' Range B '10' Reserved '11' Reserved" "0,1,2,3" group.quad 0x108++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_settings,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Setting Register." hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field. 00h - No Gap 01h - 1 LSS 02h - 2 LSS 03h - 3 LSS ...... ...... FFh - 255.." newline bitfld.quad 0x0 16.--17. "RETRY_COUNT,Data Burst retry count is set to this field. '00' Retry Disabled '01' 1 time '10' 2 times '11' 3 times" "0,1,2,3" newline hexmask.quad.byte 0x0 8.--15. 1. "HOST_NFCU,Host Driver sets the number of blocks in Data Burst [Flow Control] to this field.The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices. Setting 1 to 4 blocks is recommended.." rgroup.long 0x110++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_cap,Start Address of General Capabilities is pointed by Pointer for UHS-II Host Capabilities Register." bitfld.long 0x0 22.--23. "CORECFG_UHS2_BUS_TOPLOGY,This field indicates one of bus topologies configured by a Host system. '00' P2P Connection '01' Ring Connection '10' HUB Connection '11' HUB is connected in Ring" "0,1,2,3" newline hexmask.long.byte 0x0 18.--21. 1. "CORECFG_UHS2_MAX_DEVICES,This field indicates the maximum number of devices supported by the Host Controller. 0h - Not used 1h - 1 Devices 2h - 2 Devices ..... ....... Fh - 15 Devices" newline bitfld.long 0x0 16.--17. "DEVICE_TYPE,This field indicates device type configured by a Host system. '00' Removable Card[P2P] '01' Embedded Devices '10' Embedded Devices+Removable Card '11' Reserved" "0,1,2,3" newline bitfld.long 0x0 14. "CFG_64BIT_ADDRESSING,This field indicates support of 64-bit addressing by the Host Controller. '0' 32-bit Addressing is supported '1' 32-bit and 64-bit Addressing is supported" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "NUM_LANES,This field indicates support of lanes by the Host Controller.0 mean not supported and 1 means supported. D08 - 2L-HD D09 - 2D1U-FD D10 - 1D2U-FD D11 - 2D2U-FD D12 - Reserved D13 - Reserved" newline hexmask.long.byte 0x0 4.--7. 1. "GAP,This field indicates the maximum capability of host power supply for a group configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -Not used 1h - 360 mW 2h - 720 mW ....." newline hexmask.long.byte 0x0 0.--3. 1. "DAP,This field indicates the maximum capability of host power supply for a device configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -360 mW [Default] 1h - 360 mW 2h - 720 mW.." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_cap,Start Address of PHY Capabilities is pointed by Pointer for UHS-II Host Capabilities Register." hexmask.long.byte 0x4 20.--23. 1. "N_LSS_DIR,This field indicates the minimum N_LSS_DIR required by the Host Controller. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ...... Fh - 4 x 15 LSS" newline hexmask.long.byte 0x4 16.--19. 1. "N_LSS_SYN,This field indicates the minimum N_LSS_SYN required by the Host Controller. 0h - 4 x16 LSS 1h - 4 x 1 LSS 2h - 4 x 2 LSS 3h - 4 x 3 LSS ...... ...... Fh - 4 x 15 LSS" newline bitfld.long 0x4 6.--7. "SPEED_RANGE,This field indicates supported Speed Range by the Host Controller '00' Range A [Default] '01' Range A and Range B '10' Reserved '11' Reserved" "0,1,2,3" rgroup.quad 0x118++0x7 line.quad 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_cap,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Capabilities Register." hexmask.quad.byte 0x0 32.--39. 1. "N_DATA_GAP,This field indicates the minimum number of data gap[DIDL] supported by the Host Controller. 00h - No Gap 01h - 1 LSS 02h - 2 LSS 03h - 3 LSS ...... ...... FFh - 255 LSS" newline hexmask.quad.word 0x0 20.--31. 1. "MAX_BLK_LENGTH,This field indicates maximum block length by the Host Controller. 000h - Not Used 001h - 1 byte 002h - 2 bytes ...... ...... 200h - 512 bytes ...... ......" newline hexmask.quad.byte 0x0 8.--15. 1. "N_FCU,This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller.This value is determined by supported buffer size. 00h - 256 Blocks 01h - 1 Block 02h - 2 Block 03h - 3 Block.." wgroup.long 0x120++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_force_UHSII_Err_Int_Sts,This register is not physically implemented. rather it is an address where UHS-II Error Interrupt Status register can be written." hexmask.long.byte 0x0 27.--31. 1. "VENDOR_SPECIFIC,Force Event for Vendor Specific Error 0h - Not Affected 1h - Vendor Specific Error Status is set" newline bitfld.long 0x0 17. "TIMEOUT_DEADLOCK,Setting this bit forces the Host Controller to set Timeout for Deadlock in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 16. "TIMEOUT_CMD_RES,Setting this bit forces the Host Controller to set Timeout for CMD_RES in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 15. "ADMA,Setting this bit forces the Host Controller to set ADMA Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 8. "EBSY,Setting this bit forces the Host Controller to set EBSY Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 7. "UNRECOVERABLE,Setting this bit forces the Host Controller to set Unrecover-able Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 5. "TID,Setting this bit forces the Host Controller to set TID Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 4. "FRAMING,Setting this bit forces the Host Controller to set Framing Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 3. "CRC,Setting this bit forces the Host Controller to set CRC Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 2. "RETRY_EXPIRED,Setting this bit forces the Host Controller to set Retry Expired in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 1. "RES_PKT,Setting this bit forces the Host Controller to set RES Packet Error in the UHS-II Error Interrupt Status register." "0,1" newline bitfld.long 0x0 0. "HEADER,Setting this bit forces the Host Controller to set Header Error in the UHS-II Error Interrupt Status register." "0,1" rgroup.long 0x200++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_version,This register provides information about the version of the eMMC CQ standard which is 285 implemented by the CQE. in BCD format. The current version is rev 5.1" hexmask.long.byte 0x0 8.--11. 1. "EMMC_MAJOR_VER_NUM,eMMC Major Version Number [digit left of decimal point] in BCD format" newline hexmask.long.byte 0x0 4.--7. 1. "EMMC_MINOR_VER_NUM,eMMC Minor Version Number [digit right of decimal point] in BCD format" newline hexmask.long.byte 0x0 0.--3. 1. "EMMC_VERSION_SUFFIX,eMMC Version Suffix [2nd digit right of decimal point] in BCD format" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_capabilities,This register is reserved for capability indication." hexmask.long.byte 0x4 12.--15. 1. "CF_MUL,Internal Timer Clock Frequency Multiplier [ITCFMUL] ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the SQS polling period. See ITCFVAL definition for details." newline hexmask.long.word 0x4 0.--9. 1. "CF_VAL,Internal Timer Clock Frequency Value [ITCFVAL] TCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the polling period when using periodic SEND_QUEUE_ STATUS [CMD13] polling." group.long 0x208++0x27 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_config,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time." bitfld.long 0x0 12. "DCMD_ENA,Direct Command [DCMD] Enable This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor or a Direct Command Task Descriptor. CQE uses this bit when a task is issued in slot.." "0: Task descriptor in slot #31 is a Data Transfer..,1: Task descriptor in slot #31 is a DCMD Task.." newline bitfld.long 0x0 8. "TASK_DESC_SIZE,Task Descriptor Size This bit indicates whether the task descriptor size is 128 bits or 64 bits as detailed in Data Structures section. This bit can only be configured when Command Queueing Enable bit is 0 [command queueing is.." "0: Task descriptor size is 64 bits,1: Task descriptor size is 128 bits" newline bitfld.long 0x0 0. "CQ_ENABLE,Command Queueing Enable Software shall write 1 this bit when in order to enable command queueing mode [i.e. enable CQE]. When this bit is 0 CQE is disabled and software controls the eMMC bus using the legacy eMMC host controller." "0,1" line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_control,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time." bitfld.long 0x4 8. "CLEAR_ALL_TASKS,Clear All Tasks Software shall write 1 this bit when it wants to clear all the tasks sent to the device. This bit can only be written when CQE is in halt state [i.e.Halt bit is 1]. When software writes 1 the value of the.." "0,1" newline bitfld.long 0x4 0. "HALT_BIT,Halt Host software shall write 1 to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus. For example issuing a Discard Task command [CMDQ_TASK_MGMT] When software writes 1 .." "0,1" line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts,This register indicates pending interrupts that require service. Each bit in this registers is asserted 296 in response a specific event. only if the respective bit is set in CQ ISTE register." bitfld.long 0x8 4. "TASK_ERROR,Task Error Interrupt [TERR] This bit is asserted when task error is detected due to invalid task descriptor" "0,1" newline bitfld.long 0x8 3. "TASK_CLEARED,Task Cleared [TCL] This status bit is asserted [if CQISTE.TCL=1] when a task clear operation is completed by CQE. The com-pleted task clear operation is either an individual task clear [CQTCLR] or clearing of all tasks [CQCTL]." "0,1" newline bitfld.long 0x8 2. "RESP_ERR_DET,Response Error Detected Interrupt [RED] This status bit is asserted [if CQISTE.RED=1] when a response is received with an error bit set in the device status field. The contents of the device status field are listed in Section.." "0,1" newline bitfld.long 0x8 1. "TASK_COMPLETE,Task Complete Interrupt [TCC] This status bit is asserted [if CQISTE.TCC=1] when atleast one of the following two conditions are met: [1] A task is completed and the INT bit is set in its Task Descriptor [2] Interrupt caused by.." "0,1" newline bitfld.long 0x8 0. "HALT_COMPLETE,Halt Complete Interrupt [HAC] This status bit is asserted [if CQISTE.HAC=1] when halt bit in CQCTL register transitions from 0 to 1 indicating that host controller has completed its current ongoing task and has entered halt state." "0,1" line.long 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts_ena,This register enables and disables the reporting of the corresponding interrupt to host soft-ware in 299 CQIS register. When a bit is set ( 1 ) and the corresponding interrupt c -ondition is active. then.." bitfld.long 0xC 4. "TASK_ERROR,Task Error Interrupt Status Enable 1 = CQIS.TERR will be set when its interrupt condition is active 0 = CQIS.TERR is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 3. "TASK_CLEARED,Task Cleared Status Enable [TCL] 1 = CQIS.TCL will be set when its interrupt condition is active 0 = CQIS.TCL is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 2. "RESP_ERR_DET,Response Error Detected Status Enable [RED] 1 = CQIS.RED will be set when its interrupt condition is active 0 = CQIS.RED is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 1. "TASK_COMPLETE,Task Complete Status Enable [TCC] 1 = CQIS.TCC will be set when its interrupt condition is active 0 = CQIS.TCC is disabled" "0: CQIS,1: CQIS" newline bitfld.long 0xC 0. "HALT_COMPLETE,Halt Complete Status Enable [HAC] 1 = CQIS.HAC will be set when its interrupt condition is active 0 = CQIS.HAC is disabled" "0: CQIS,1: CQIS" line.long 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sig_ena,This register enables and disables the generation of interrupts to host software. When a bit is set 304 ( 1 ) and the corresponding bit in CQIS is set. then an interrupt is gene -rated. Interrupt sources.." bitfld.long 0x10 4. "TASK_ERROR,Task Error Interrupt Signal Enable [TERR] When set and CQIS.TERR is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 3. "TASK_CLEARED,Task Cleared Signal Enable [TCL] When set and CQIS.TCL is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 2. "RESP_ERR_DET,Response Error Detected Signal Enable [TCC] When set and CQIS.RED is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 1. "TASK_COMPLETE,Task Complete Signal Enable [TCC] When set and CQIS.TCC is asserted the CQE shall generate an interrupt" "0,1" newline bitfld.long 0x10 0. "HALT_COMPLETE,Halt Complete Signal Enable [HAC] When set and CQIS.HAC is asserted the CQE shall generate an interrupt" "0,1" line.long 0x14 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_coalescing,This register controls the interrupt coalescing feature." bitfld.long 0x14 31. "CQINTCOALESC_ENABLE,When set to 0 by software command responses are neither counted nor timed. Interrupts are still triggered by completion of tasks with INT=1 in the Task Descriptor. When set to 1 the interrupt coalescing mechanism is enabled.." "0,1" newline rbitfld.long 0x14 20. "IC_STATUS,This bit indicates to software whether any tasks [with INT=0] have completed and counted towards interrupt coalescing [i.e. ICSB is set if and only if IC counter > 0]. Bit Value Description 1 = At least one task completion has been.." "0: No task completions have occurred since last..,1: At least one task completion has been counted.." newline hexmask.long.byte 0x14 8.--12. 1. "CTR_THRESHOLD,Interrupt Coalescing Counter Threshold [ICCTH]: Software uses this field to configure the number of task completions [only tasks with INT=0 in the Task Descriptor] which are required in order to generate an interrupt. Counter.." newline hexmask.long.byte 0x14 0.--6. 1. "TIMEOUT_VAL,Interrupt Coalescing Timeout Value [ICTOVAL]: Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. Timer Operation: The timer is reset by.." line.long 0x18 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory." hexmask.long 0x18 0.--31. 1. "CQTDLBA_LO,Task Descriptor List Base Address [TDLBA] This register stores the LSB bits [bits 31:0] of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * [Task Descrip-tor.." line.long 0x1C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr_upbits,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory." hexmask.long 0x1C 0.--31. 1. "CQTDLBA_HI,Task Descriptor List Base Address [TDLBA] This register stores the MSB bits [bits 63:32] of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * [Task Descrip-tor.." line.long 0x20 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_door_bell,Using this register. software triggers CQE to process a new task." hexmask.long 0x20 0.--31. 1. "CQTDB_VAL,Command Queueing Task Doorbell Software shall configure TDLBA and TDLBAU and enable CQE in CQCFG before using this register. Writing 1 to bit n of this register triggers CQE to start pro-cessing the task encoded in slot n of the TDL." line.long 0x24 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_comp_notif,This register is used by CQE to notify software about completed tasks." hexmask.long 0x24 0.--31. 1. "CQTCN_VAL,CQE shall set bit n of this register [at the same time it clears bit n of CQTDBR] when a task execution is com-pleted [with success or error]. When receiving interrupt for task completion software may read this register to know which tasks.." rgroup.long 0x230++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_queue_status,This register stores the most recent value of the device s queue status." hexmask.long 0x0 0.--31. 1. "CQDQ_STS,Every time the Host controller receives a queue status register [QSR] from the device it updates this register with the response of status command i.e. the devices queue status." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_pending_tasks,This register indicates to software which tasks are queued in the device. awaiting execution." hexmask.long 0x4 0.--31. 1. "CQDP_TSKS,Bit n of this register is set if and only if QUEUED_TASK_PARAMS [CMD44] and QUEUED_TASK_ADDRESS [CMD45] were sent for this specific task and if this task hasnt been executed yet.CQE shall set this bit after receiving a successful response for.." group.long 0x238++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_clear,This register is used for removing an outstanding task in the CQE. 327. The register should be used only when CQE is in Halt state." hexmask.long 0x0 0.--31. 1. "CQTCLR,Writing 1 to bit n of this register orders CQE to clear a task which software has previously issued.This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit.When software writes 1 to a bit in this.." group.long 0x240++0x7 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config1,The register controls the when SEND_QUEUE_STATUS commands are sent." hexmask.long.byte 0x0 16.--19. 1. "CMD_BLK_CNTR,This field indicates to CQE when to send SEND_QUEUE_STATUS [CMD13] command to inquire the status of the devices task queue.A value of n means CQE shall send status command on the CMD line during the transfer of data block BLOCK_CNT-n on.." newline hexmask.long.word 0x0 0.--15. 1. "CMD_IDLE_TIMER,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS [CMD13] polling.Periodic polling is used when tasks are pending in the device but no data transfer is in progress. When a SEND_QUEUE_STATUS.." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argu-ment." hexmask.long.word 0x4 0.--15. 1. "QUEUE_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_ STATUS [CMD13] com-mand. argument. CQE shall copy this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS [CMD13] command." rgroup.long 0x248++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dcmd_response,This register is used for passing the response of a DCMD task to software." hexmask.long 0x0 0.--31. 1. "LAST_RESP,This register contains the response of the command generated by the last direct-command [DCMD] task which was sent.CQE shall update this register when it receives the response for a DCMD task. This register is considered valid only after bit 31.." group.long 0x250++0x3 line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_resp_err_mask,This register controls the generation of Response Error Detection (RED) interrupt." hexmask.long 0x0 0.--31. 1. "CQRMEM,This bit is used as in interrupt mask on the device status filed which is received in R1/R1b responses.Bit Value Description [for any bit i]:1 = When a R1/R1b response is received with bit i in the device status set a RED interrupt is generated.." rgroup.long 0x254++0xF line.long 0x0 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_err_info,This register is updated by CQE when an error occurs on data or command related to a task activity." bitfld.long 0x0 31. "DATERR_VALID,Data Transfer Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller. If a data transfer is in progress when the error is detected/indicated the bit is set to 1. If a no.." "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "DATERR_TASK_ID,Data Transfer Error Task ID This field indicates the ID of the task which was executed on the data lines when an error occurred. The field is updated if a data transfer is in progress when an error is detected by CQE or.." newline hexmask.long.byte 0x0 16.--21. 1. "DATERR_CMD_INDEX,Data Transfer Error Command Index This field indicates the index of the command which was executed on the data lines when an error occurred. The index shall be set to EXECUTE_READ_TASK[CMD46] or EXECUTE_WRITE_TASK [CMD47].." newline bitfld.long 0x0 15. "RESP_MODE_VALID,Response Mode Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller. If a command transaction is in progress when the error is detected/indicated the bit is set to 1." "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "RESP_MODE_TASK_ID,Response Mode Error Task ID This field indicates the ID of the task which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is detected by.." newline hexmask.long.byte 0x0 0.--5. 1. "RESP_MODE_CMD_INDEX,Response Mode Error Command Index This field indicates the index of the command which was executed on the command line when an error occurred. The field is updated if a command transaction is in progress when an error is.." line.long 0x4 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_index,This register stores the index of the last received command response." hexmask.long.byte 0x4 0.--5. 1. "LAST_CRI,This field stores the index of the last received command response. CQE shall update the value every time a com-mand response is received." line.long 0x8 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_arg,This register stores the index of the last received command response." hexmask.long 0x8 0.--31. 1. "LAST_CRA,This field stores the argument of the last received com-mand. CQE shall update the value every time a com-mand response is received." line.long 0xC "SDHC_WRAP__CTL_CFG__CTLCFG_cq_error_task_id,CQ Error Task ID Register" hexmask.long.byte 0xC 0.--4. 1. "TERR_ID,Task Error ID" tree.end tree "MMCSD2_ECC_AGGR_RXMEM" base ad:0x70B000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MMCSD2_ECC_AGGR_TXMEM" base ad:0x70A000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MMCSD2_SS_CFG" base ad:0xFA28000 rgroup.long 0x0++0x3 line.long 0x0 "REGS__SS_CFG__SSCFG_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem" hexmask.long.word 0x0 16.--31. 1. "MOD_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version" newline bitfld.long 0x0 8.--10. "MAJ_REV,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MIN_REV,Minor revision" group.long 0x10++0x37 line.long 0x0 "REGS__SS_CFG__SSCFG_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.byte 0x0 24.--29. 1. "TUNINGCOUNT,Configures the Number of Taps (Phases) of the RX clock that is supported. The Tuning State machine uses this information to select one of the Taps (Phases) of the RX clock during the Tuning Procedure." bitfld.long 0x0 20. "ASYNCWKUPENA,Determines the Wakeup Signal Generation Mode. 0: Synchronous Wakeup Mode: The xin_clk has to be running for this mode. The Card Insertion/Removal/Interrupt events are detected synchronously on the xin_clk and the Wakeup Event is generated." "0: Synchronous Wakeup Mode: The xin_clk has to be..,1: Asyncrhonous Wakeup Mode: The xin_clk and the.." newline hexmask.long.byte 0x0 12.--15. 1. "CQFMUL,FMUL for the CQ Internal Timer Clock Frequency" hexmask.long.word 0x0 0.--9. 1. "CQFVAL,FVAL for the CQ Internal Timer Clock Frequency" line.long 0x4 "REGS__SS_CFG__SSCFG_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." bitfld.long 0x4 30.--31. "SLOTTYPE,Slot Type. Should be set based on the final product usage. 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved." "0,1,2,3" bitfld.long 0x4 29. "ASYNCHINTRSUPPORT,Asynchronous Interrupt Support. Suggested Value is 1'b1 (The Core supports monitoring of Asynchronous Interrupt)." "0,1" newline bitfld.long 0x4 26. "SUPPORT1P8VOLT,1.8V Support. Suggested Value is 1'b1 (The 1.8 Volt Switching is supported by Core). Optionally can be set to 1'b0 if the application doesn't want 1.8V switching (SD3.0)." "0,1" bitfld.long 0x4 25. "SUPPORT3P0VOLT,3.0V Support. Should be set based on whether 3.0V is supported on the SD Interface." "0,1" newline bitfld.long 0x4 24. "SUPPORT3P3VOLT,3.3V Support. Suggested Value is 1'b1 as the 3.3 V is the default voltage on the SD Interface." "0,1" bitfld.long 0x4 23. "SUSPRESSUPPORT,Suspend/Resume Support. Suggested Value is 1'b1 (The Suspend/Resume is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support Suspend/Resume Mode." "0,1" newline bitfld.long 0x4 22. "SDMASUPPORT,SDMA Support. Suggested Value is 1'b1 (The SDMA is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support SDMA Mode." "0,1" bitfld.long 0x4 21. "HIGHSPEEDSUPPORT,High Speed Support. Suggested Value is 1'b1 (The High Speed mode is supported by Core)." "0,1" newline bitfld.long 0x4 19. "ADMA2SUPPORT,ADMA2 Support. Suggested Value is 1'b1 (The ADMA2 is supported by Core). Optionally can be set to 1'b0 if the application doesn't want to support ADMA2 Mode." "0,1" bitfld.long 0x4 18. "SUPPORT8BIT,8-bit Support for Embedded Device. Suggested Value is 1'b1 (The Core supports 8-bit Interface). Optionally an be set to 1'b0 if the Application supports only 4-bit SD Interface." "0,1" newline bitfld.long 0x4 16.--17. "MAXBLKLENGTH,Max Block Length. Maximum Block Length supported by the Core/Device. 00: 512 (Bytes) 01: 1024 10: 2048 11: Reserved." "0: 512,1: 1024,?,?" hexmask.long.byte 0x4 8.--15. 1. "BASECLKFREQ,Base Clock Frequency for SD Clock. This is the frequency of the xin_clk." newline bitfld.long 0x4 7. "TIMEOUTCLKUNIT,Timeout Clock Unit. Suggested Value is 1'b0 (KHz)." "0,1" hexmask.long.byte 0x4 0.--5. 1. "TIMEOUTCLKFREQ,Timeout Clock Frequency. Suggested Value is 1 KHz. Internally the 1msec Timer is used for Timeout Detection. The 1msec Timer is generated from the xin_clk." line.long 0x8 "REGS__SS_CFG__SSCFG_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." bitfld.long 0x8 28. "SUPPORT1P8VDD2,1.8V VDD2 Support." "0,1" bitfld.long 0x8 27. "ADMA3SUPPORT,ADMA3 Support." "0,1" newline hexmask.long.byte 0x8 16.--23. 1. "CLOCKMULTIPLIER,Clock Multiplier. This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h means that Host Controller does not support programmable clock generator. FFh Clock Multiplier M =.." bitfld.long 0x8 14.--15. "RETUNINGMODES,Re-Tuning Modes. Should be set to 2'b00 as the Core supports only the Software Timer based Re-Tuning." "0,1,2,3" newline bitfld.long 0x8 13. "TUNINGFORSDR50,Use Tuning for SDR50. This bit should be set if the Application wants Tuning be used for SDR50 Modes. The Core operates with or with out tuning for SDR50 mode as long as the Clock can be manually tuned using tap delay." "0,1" hexmask.long.byte 0x8 8.--11. 1. "RETUNINGTIMERCNT,Timer Count for Re-Tuning. This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer." newline bitfld.long 0x8 7. "TYPE4SUPPORT,Driver Type 4 Support. This bit should be set based on whether Driver Type 4 for 1.8 Signalling is supported or not." "0,1" bitfld.long 0x8 6. "DDRIVERSUPPORT,Driver Type D Support. This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not." "0,1" newline bitfld.long 0x8 5. "CDRIVERSUPPORT,Driver Type C Support. This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not." "0,1" bitfld.long 0x8 4. "ADRIVERSUPPORT,Driver Type A Support. This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not." "0,1" newline bitfld.long 0x8 2. "DDR50SUPPORT,DDR50 Support. Suggested Value is 1'b1 (The Core supports DDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support DDR50." "0,1" bitfld.long 0x8 1. "SDR104SUPPORT,SDR104 Support. Suggested Value is 1'b1 (The Core supports SDR104 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR104." "0,1" newline bitfld.long 0x8 0. "SDR50SUPPORT,SDR50 Support. Suggested Value is 1'b1 (The Core supports SDR50 mode of operation). Optionally can be set to 1'b0 if the application doesn't want to support SDR50." "0,1" line.long 0xC "REGS__SS_CFG__SSCFG_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.byte 0xC 16.--23. 1. "MAXCURRENT1P8V,Maximum Current for 1.8V." hexmask.long.byte 0xC 8.--15. 1. "MAXCURRENT3P0V,Maximum Current for 3.0V." newline hexmask.long.byte 0xC 0.--7. 1. "MAXCURRENT3P3V,Maximum Current for 3.3V." line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.byte 0x10 0.--7. 1. "MAXCURRENTVDD2,Maximum Current for 1.8 V (VDD2)." line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x14 0.--12. 1. "INITPRESETVAL,Preset Value for Initialization." line.long 0x18 "REGS__SS_CFG__SSCFG_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x18 0.--12. 1. "DSPDPRESETVAL,Preset Value for Default Speed." line.long 0x1C "REGS__SS_CFG__SSCFG_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x1C 0.--12. 1. "HSPDPRESETVAL,Preset Value for High Speed." line.long 0x20 "REGS__SS_CFG__SSCFG_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x20 0.--12. 1. "SDR12PRESETVAL,Preset Value for SDR12." line.long 0x24 "REGS__SS_CFG__SSCFG_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x24 0.--12. 1. "SDR25PRESETVAL,Preset Value for SDR25." line.long 0x28 "REGS__SS_CFG__SSCFG_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x28 0.--12. 1. "SDR50PRESETVAL,Preset Value for SDR50." line.long 0x2C "REGS__SS_CFG__SSCFG_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x2C 0.--12. 1. "SDR104PRESETVAL,Preset Value for SDR104." line.long 0x30 "REGS__SS_CFG__SSCFG_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." hexmask.long.word 0x30 0.--12. 1. "DDR50PRESETVAL,Preset Value for DDR50." line.long 0x34 "REGS__SS_CFG__SSCFG_CTL_CFG_14_REG,The Controller Config 14 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller configuration ports please refer.." rgroup.long 0x60++0x17 line.long 0x0 "REGS__SS_CFG__SSCFG_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." bitfld.long 0x0 31. "SDHC_CMDIDLE,Idle signal to enable S/W to gate off the clocks." "0,1" hexmask.long.word 0x0 0.--15. 1. "DMADEBUGBUS,DMA_CTRL Debug Bus." line.long 0x4 "REGS__SS_CFG__SSCFG_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x4 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL Debug Bus." line.long 0x8 "REGS__SS_CFG__SSCFG_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x8 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL Debug Bus." line.long 0xC "REGS__SS_CFG__SSCFG_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0xC 0.--15. 1. "RXDDEBUGBUS0,RXD_CTRL Debug Bus (SD CLK)." line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x10 0.--15. 1. "RXDDEBUGBUS1,RXD_CTRL Debug Bus (RX CLK)." line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller. For detailed functionality of the Arasan eMMC/SD Controller debug ports please refer to.." hexmask.long.word 0x14 0.--15. 1. "TUNDEBUGBUS,TUN_CTRL Debug Bus." group.long 0x100++0x17 line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0x0 31. "IOMUX_ENABLE,IO mux enable. Set 1 for GPIO. Set 0 for eMMC/SD" "0,1" line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_CTRL_2_REG,The PHY Control 2 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." line.long 0x8 "REGS__SS_CFG__SSCFG_PHY_CTRL_3_REG,The PHY Control 3 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." line.long 0xC "REGS__SS_CFG__SSCFG_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0xC 20. "OTAPDLYENA,Output Tap Delay Enable. Enables manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." "0,1" hexmask.long.byte 0xC 12.--15. 1. "OTAPDLYSEL,Output Tap Delay Select. Manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface." newline bitfld.long 0xC 9. "ITAPCHGWIN,Input Tap Change Window. It gets asserted by the controller while changing the itapdlysel. Used to gate of the RX clock during switching the clock source while tap is changing to avoid clock glitches." "0,1" bitfld.long 0xC 8. "ITAPDLYENA,Input Tap Delay Enable. This is used for the manual control of the RX clock Tap Delay in non HS200/HS400 modes." "0,1" newline hexmask.long.byte 0xC 0.--4. 1. "ITAPDLYSEL,Input Tap Delay Select. Manual control of the RX clock Tap Delay in the non HS200/HS400 modes." line.long 0x10 "REGS__SS_CFG__SSCFG_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." bitfld.long 0x10 0.--2. "CLKBUFSEL,Clock Delay Buffer Select. Selects one of the eight taps in the CLK Delay Buffer based on PVT variation." "0,1,2,3,4,5,6,7" line.long 0x14 "REGS__SS_CFG__SSCFG_PHY_CTRL_6_REG,The PHY Control 6 Register contains various fields to control the ports on the Arasan eMMC/SD PHY. For detailed functionality of the Arasan eMMC/SD PHY control ports please refer to its specification listed in Section.." group.long 0x130++0x7 line.long 0x0 "REGS__SS_CFG__SSCFG_PHY_STAT_1_REG,The PHY Status 1 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports. For detailed functionality of the Arasan eMMC/SD PHY status ports please refer to its specification listed in.." line.long 0x4 "REGS__SS_CFG__SSCFG_PHY_STAT_2_REG,The PHY Status 2 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports. For detailed functionality of the Arasan eMMC/SD PHY status ports please refer to its specification listed in.." tree.end tree.end tree "MSRAM_64K0" base ad:0x0 tree "MSRAM_64K0_ECC_AGGR_REGS" base ad:0x710000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "ECC_AGGR_REGSREGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGGR_REGSREGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGGR_REGSREGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1" group.long 0x200++0xF line.long 0x0 "ECC_AGGR_REGSREGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "ECC_AGGR_REGSREGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "ECC_AGGR_REGSREGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "ECC_AGGR_REGSREGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "MSRAM_64K0_RAM_0" base ad:0x43C40000 group.long 0x0++0x3 line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree "MSRAM_64K0_RAM_1" base ad:0x70000000 group.long 0x0++0x3 line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree.end tree "PADCFG_CTRL0_CFG0" base ad:0xF0000 rgroup.long 0x0++0xB line.long 0x0 "CFG0_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16" hexmask.long.byte 0x0 11.--15. 1. "PID_MISC" newline bitfld.long 0x0 8.--10. "PID_MAJOR" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "PID_CUSTOM" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR" line.long 0x4 "CFG0_MMR_CFG0" hexmask.long.word 0x4 16.--31. 1. "MMR_CFG0_CFG_REV,Major configuration release" hexmask.long.word 0x4 0.--15. 1. "MMR_CFG0_SPEC_REV,Minor spec-only revision. Doesn't change RTL release" line.long 0x8 "CFG0_MMR_CFG1" bitfld.long 0x8 31. "MMR_CFG1_PROXY_EN,Proxy addressing enabled" "0,1" hexmask.long.byte 0x8 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions" group.long 0x1008++0x1B line.long 0x0 "CFG0_LOCK0_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK0_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" line.long 0x8 "CFG0_intr_raw_status" bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "CFG0_intr_enabled_status_clear" bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "CFG0_intr_enable" bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "CFG0_intr_enable_clear" bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "CFG0_eoi" hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0xB line.long 0x0 "CFG0_fault_address" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." line.long 0x4 "CFG0_fault_type_status" bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.." line.long 0x8 "CFG0_fault_attr_status" hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID." hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID." wgroup.long 0x1030++0x3 line.long 0x0 "CFG0_fault_clear" bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" rgroup.long 0x1100++0x3 line.long 0x0 "CFG0_CLAIMREG_P0_R0_READONLY" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0_READONLY,Claim bits for Partition 0" rgroup.long 0x2000++0xB line.long 0x0 "CFG0_PID_PROXY" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16_PROXY" hexmask.long.byte 0x0 11.--15. 1. "PID_MISC_PROXY" newline bitfld.long 0x0 8.--10. "PID_MAJOR_PROXY" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "PID_CUSTOM_PROXY" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR_PROXY" line.long 0x4 "CFG0_MMR_CFG0_PROXY" hexmask.long.word 0x4 16.--31. 1. "MMR_CFG0_CFG_REV_PROXY,Major configuration release" hexmask.long.word 0x4 0.--15. 1. "MMR_CFG0_SPEC_REV_PROXY,Minor spec-only revision. Doesn't change RTL release" line.long 0x8 "CFG0_MMR_CFG1_PROXY" bitfld.long 0x8 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing enabled" "0,1" hexmask.long.byte 0x8 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions" group.long 0x3008++0x1B line.long 0x0 "CFG0_LOCK0_KICK0_PROXY" hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK0_KICK1_PROXY" hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1_PROXY,- KICK1 component" line.long 0x8 "CFG0_intr_raw_status_PROXY" bitfld.long 0x8 3. "PROXY_ERR_PROXY,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x8 2. "KICK_ERR_PROXY,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR_PROXY,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_PROXY,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "CFG0_intr_enabled_status_clear_PROXY" bitfld.long 0xC 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0xC 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "ENABLED_PROT_ERR_PROXY,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "CFG0_intr_enable_PROXY" bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "CFG0_intr_enable_clear_PROXY" bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "CFG0_eoi_PROXY" hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x3024++0xB line.long 0x0 "CFG0_fault_address_PROXY" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR_PROXY,Fault Address." line.long 0x4 "CFG0_fault_type_status_PROXY" bitfld.long 0x4 6. "FAULT_NS_PROXY,Non-secure access." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE_PROXY,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv =.." line.long 0x8 "CFG0_fault_attr_status_PROXY" hexmask.long.word 0x8 20.--31. 1. "FAULT_XID_PROXY,XID." hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID." wgroup.long 0x3030++0x3 line.long 0x0 "CFG0_fault_clear_PROXY" bitfld.long 0x0 0. "FAULT_CLR_PROXY,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" group.long 0x3100++0x3 line.long 0x0 "CFG0_CLAIMREG_P0_R0" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0,Claim bits for Partition 0" group.long 0x4000++0x25B line.long 0x0 "CFG0_PADCONFIG0" bitfld.long 0x0 31. "PADCONFIG0_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x0 30. "PADCONFIG0_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x0 29. "PADCONFIG0_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x0 28. "PADCONFIG0_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x0 27. "PADCONFIG0_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x0 26. "PADCONFIG0_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x0 25. "PADCONFIG0_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x0 24. "PADCONFIG0_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x0 23. "PADCONFIG0_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x0 22. "PADCONFIG0_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x0 21. "PADCONFIG0_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x0 19.--20. "PADCONFIG0_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "PADCONFIG0_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x0 17. "PADCONFIG0_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x0 16. "PADCONFIG0_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x0 15. "PADCONFIG0_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x0 14. "PADCONFIG0_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x0 11.--13. "PADCONFIG0_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "PADCONFIG0_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x0 7. "PADCONFIG0_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG0_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x4 "CFG0_PADCONFIG1" bitfld.long 0x4 31. "PADCONFIG1_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x4 30. "PADCONFIG1_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x4 29. "PADCONFIG1_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x4 28. "PADCONFIG1_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x4 27. "PADCONFIG1_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x4 26. "PADCONFIG1_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x4 25. "PADCONFIG1_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x4 24. "PADCONFIG1_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x4 23. "PADCONFIG1_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x4 22. "PADCONFIG1_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x4 21. "PADCONFIG1_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x4 19.--20. "PADCONFIG1_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "PADCONFIG1_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x4 17. "PADCONFIG1_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x4 16. "PADCONFIG1_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x4 15. "PADCONFIG1_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x4 14. "PADCONFIG1_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x4 11.--13. "PADCONFIG1_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "PADCONFIG1_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x4 7. "PADCONFIG1_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG1_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x8 "CFG0_PADCONFIG2" bitfld.long 0x8 31. "PADCONFIG2_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x8 30. "PADCONFIG2_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x8 29. "PADCONFIG2_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x8 28. "PADCONFIG2_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x8 27. "PADCONFIG2_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x8 26. "PADCONFIG2_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x8 25. "PADCONFIG2_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x8 24. "PADCONFIG2_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x8 23. "PADCONFIG2_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x8 22. "PADCONFIG2_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x8 21. "PADCONFIG2_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x8 19.--20. "PADCONFIG2_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "PADCONFIG2_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x8 17. "PADCONFIG2_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x8 16. "PADCONFIG2_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x8 15. "PADCONFIG2_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x8 14. "PADCONFIG2_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x8 11.--13. "PADCONFIG2_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "PADCONFIG2_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x8 7. "PADCONFIG2_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG2_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xC "CFG0_PADCONFIG3" bitfld.long 0xC 31. "PADCONFIG3_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xC 30. "PADCONFIG3_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xC 29. "PADCONFIG3_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xC 28. "PADCONFIG3_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xC 27. "PADCONFIG3_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xC 26. "PADCONFIG3_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xC 25. "PADCONFIG3_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xC 24. "PADCONFIG3_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xC 23. "PADCONFIG3_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xC 22. "PADCONFIG3_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xC 21. "PADCONFIG3_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xC 19.--20. "PADCONFIG3_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "PADCONFIG3_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xC 17. "PADCONFIG3_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xC 16. "PADCONFIG3_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xC 15. "PADCONFIG3_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xC 14. "PADCONFIG3_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xC 11.--13. "PADCONFIG3_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "PADCONFIG3_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xC 7. "PADCONFIG3_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG3_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x10 "CFG0_PADCONFIG4" bitfld.long 0x10 31. "PADCONFIG4_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x10 30. "PADCONFIG4_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x10 29. "PADCONFIG4_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x10 28. "PADCONFIG4_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x10 27. "PADCONFIG4_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x10 26. "PADCONFIG4_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x10 25. "PADCONFIG4_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x10 24. "PADCONFIG4_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x10 23. "PADCONFIG4_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x10 22. "PADCONFIG4_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x10 21. "PADCONFIG4_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x10 15. "PADCONFIG4_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x10 14. "PADCONFIG4_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "PADCONFIG4_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x10 7. "PADCONFIG4_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG4_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x14 "CFG0_PADCONFIG5" bitfld.long 0x14 31. "PADCONFIG5_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x14 30. "PADCONFIG5_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x14 29. "PADCONFIG5_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x14 28. "PADCONFIG5_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x14 27. "PADCONFIG5_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x14 26. "PADCONFIG5_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x14 25. "PADCONFIG5_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x14 24. "PADCONFIG5_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x14 23. "PADCONFIG5_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x14 22. "PADCONFIG5_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x14 21. "PADCONFIG5_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x14 15. "PADCONFIG5_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x14 14. "PADCONFIG5_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "PADCONFIG5_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x14 7. "PADCONFIG5_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG5_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x18 "CFG0_PADCONFIG6" bitfld.long 0x18 31. "PADCONFIG6_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x18 30. "PADCONFIG6_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x18 29. "PADCONFIG6_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x18 28. "PADCONFIG6_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x18 27. "PADCONFIG6_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x18 26. "PADCONFIG6_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x18 25. "PADCONFIG6_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x18 24. "PADCONFIG6_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x18 23. "PADCONFIG6_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x18 22. "PADCONFIG6_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x18 21. "PADCONFIG6_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x18 15. "PADCONFIG6_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x18 14. "PADCONFIG6_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "PADCONFIG6_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x18 7. "PADCONFIG6_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG6_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1C "CFG0_PADCONFIG7" bitfld.long 0x1C 31. "PADCONFIG7_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1C 30. "PADCONFIG7_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1C 29. "PADCONFIG7_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1C 28. "PADCONFIG7_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1C 27. "PADCONFIG7_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1C 26. "PADCONFIG7_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1C 25. "PADCONFIG7_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1C 24. "PADCONFIG7_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1C 23. "PADCONFIG7_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1C 22. "PADCONFIG7_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1C 15. "PADCONFIG7_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1C 14. "PADCONFIG7_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "PADCONFIG7_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1C 7. "PADCONFIG7_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG7_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x20 "CFG0_PADCONFIG8" bitfld.long 0x20 31. "PADCONFIG8_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x20 30. "PADCONFIG8_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x20 29. "PADCONFIG8_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x20 28. "PADCONFIG8_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x20 27. "PADCONFIG8_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x20 26. "PADCONFIG8_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x20 25. "PADCONFIG8_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x20 24. "PADCONFIG8_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x20 23. "PADCONFIG8_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x20 22. "PADCONFIG8_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x20 21. "PADCONFIG8_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x20 15. "PADCONFIG8_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x20 14. "PADCONFIG8_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 8. "PADCONFIG8_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x20 7. "PADCONFIG8_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG8_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x24 "CFG0_PADCONFIG9" bitfld.long 0x24 31. "PADCONFIG9_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x24 30. "PADCONFIG9_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x24 29. "PADCONFIG9_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x24 28. "PADCONFIG9_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x24 27. "PADCONFIG9_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x24 26. "PADCONFIG9_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x24 25. "PADCONFIG9_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x24 24. "PADCONFIG9_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x24 23. "PADCONFIG9_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x24 22. "PADCONFIG9_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x24 21. "PADCONFIG9_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x24 15. "PADCONFIG9_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x24 14. "PADCONFIG9_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "PADCONFIG9_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x24 7. "PADCONFIG9_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG9_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x28 "CFG0_PADCONFIG10" bitfld.long 0x28 31. "PADCONFIG10_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x28 30. "PADCONFIG10_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x28 29. "PADCONFIG10_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x28 28. "PADCONFIG10_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x28 27. "PADCONFIG10_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x28 26. "PADCONFIG10_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x28 25. "PADCONFIG10_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x28 24. "PADCONFIG10_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x28 23. "PADCONFIG10_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x28 22. "PADCONFIG10_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x28 21. "PADCONFIG10_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x28 15. "PADCONFIG10_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x28 14. "PADCONFIG10_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8. "PADCONFIG10_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x28 7. "PADCONFIG10_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG10_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x2C "CFG0_PADCONFIG11" bitfld.long 0x2C 31. "PADCONFIG11_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x2C 30. "PADCONFIG11_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x2C 29. "PADCONFIG11_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x2C 28. "PADCONFIG11_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x2C 27. "PADCONFIG11_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x2C 26. "PADCONFIG11_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x2C 25. "PADCONFIG11_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x2C 24. "PADCONFIG11_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x2C 23. "PADCONFIG11_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x2C 22. "PADCONFIG11_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x2C 15. "PADCONFIG11_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x2C 14. "PADCONFIG11_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 8. "PADCONFIG11_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x2C 7. "PADCONFIG11_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x2C 0.--3. 1. "PADCONFIG11_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x30 "CFG0_PADCONFIG12" bitfld.long 0x30 31. "PADCONFIG12_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x30 30. "PADCONFIG12_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x30 29. "PADCONFIG12_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x30 28. "PADCONFIG12_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x30 27. "PADCONFIG12_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x30 26. "PADCONFIG12_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x30 25. "PADCONFIG12_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x30 24. "PADCONFIG12_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x30 23. "PADCONFIG12_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x30 22. "PADCONFIG12_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x30 21. "PADCONFIG12_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x30 15. "PADCONFIG12_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x30 14. "PADCONFIG12_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 8. "PADCONFIG12_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x30 7. "PADCONFIG12_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PADCONFIG12_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x34 "CFG0_PADCONFIG13" bitfld.long 0x34 31. "PADCONFIG13_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x34 30. "PADCONFIG13_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x34 29. "PADCONFIG13_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x34 28. "PADCONFIG13_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x34 27. "PADCONFIG13_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x34 26. "PADCONFIG13_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x34 25. "PADCONFIG13_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x34 24. "PADCONFIG13_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x34 23. "PADCONFIG13_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x34 22. "PADCONFIG13_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x34 21. "PADCONFIG13_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x34 15. "PADCONFIG13_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x34 14. "PADCONFIG13_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 8. "PADCONFIG13_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x34 7. "PADCONFIG13_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x34 0.--3. 1. "PADCONFIG13_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x38 "CFG0_PADCONFIG14" bitfld.long 0x38 31. "PADCONFIG14_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x38 30. "PADCONFIG14_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x38 29. "PADCONFIG14_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x38 28. "PADCONFIG14_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x38 27. "PADCONFIG14_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x38 26. "PADCONFIG14_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x38 25. "PADCONFIG14_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x38 24. "PADCONFIG14_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x38 23. "PADCONFIG14_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x38 22. "PADCONFIG14_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x38 21. "PADCONFIG14_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x38 15. "PADCONFIG14_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x38 14. "PADCONFIG14_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 8. "PADCONFIG14_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x38 7. "PADCONFIG14_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x38 0.--3. 1. "PADCONFIG14_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x3C "CFG0_PADCONFIG15" bitfld.long 0x3C 31. "PADCONFIG15_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x3C 30. "PADCONFIG15_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x3C 29. "PADCONFIG15_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x3C 28. "PADCONFIG15_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x3C 27. "PADCONFIG15_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x3C 26. "PADCONFIG15_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x3C 25. "PADCONFIG15_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x3C 24. "PADCONFIG15_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x3C 23. "PADCONFIG15_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x3C 22. "PADCONFIG15_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x3C 15. "PADCONFIG15_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x3C 14. "PADCONFIG15_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x3C 8. "PADCONFIG15_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x3C 7. "PADCONFIG15_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x3C 0.--3. 1. "PADCONFIG15_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x40 "CFG0_PADCONFIG16" bitfld.long 0x40 31. "PADCONFIG16_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x40 30. "PADCONFIG16_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x40 29. "PADCONFIG16_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x40 28. "PADCONFIG16_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x40 27. "PADCONFIG16_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x40 26. "PADCONFIG16_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x40 25. "PADCONFIG16_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x40 24. "PADCONFIG16_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x40 23. "PADCONFIG16_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x40 22. "PADCONFIG16_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x40 21. "PADCONFIG16_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x40 15. "PADCONFIG16_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x40 14. "PADCONFIG16_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 8. "PADCONFIG16_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x40 7. "PADCONFIG16_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "PADCONFIG16_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x44 "CFG0_PADCONFIG17" bitfld.long 0x44 31. "PADCONFIG17_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x44 30. "PADCONFIG17_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x44 29. "PADCONFIG17_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x44 28. "PADCONFIG17_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x44 27. "PADCONFIG17_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x44 26. "PADCONFIG17_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x44 25. "PADCONFIG17_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x44 24. "PADCONFIG17_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x44 23. "PADCONFIG17_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x44 22. "PADCONFIG17_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x44 21. "PADCONFIG17_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x44 15. "PADCONFIG17_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x44 14. "PADCONFIG17_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x44 8. "PADCONFIG17_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x44 7. "PADCONFIG17_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x44 0.--3. 1. "PADCONFIG17_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x48 "CFG0_PADCONFIG18" bitfld.long 0x48 31. "PADCONFIG18_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x48 30. "PADCONFIG18_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x48 29. "PADCONFIG18_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x48 28. "PADCONFIG18_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x48 27. "PADCONFIG18_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x48 26. "PADCONFIG18_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x48 25. "PADCONFIG18_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x48 24. "PADCONFIG18_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x48 23. "PADCONFIG18_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x48 22. "PADCONFIG18_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x48 21. "PADCONFIG18_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x48 15. "PADCONFIG18_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x48 14. "PADCONFIG18_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 8. "PADCONFIG18_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x48 7. "PADCONFIG18_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x48 0.--3. 1. "PADCONFIG18_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x4C "CFG0_PADCONFIG19" bitfld.long 0x4C 31. "PADCONFIG19_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x4C 30. "PADCONFIG19_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x4C 29. "PADCONFIG19_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x4C 28. "PADCONFIG19_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x4C 27. "PADCONFIG19_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x4C 26. "PADCONFIG19_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x4C 25. "PADCONFIG19_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x4C 24. "PADCONFIG19_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x4C 23. "PADCONFIG19_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x4C 22. "PADCONFIG19_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x4C 15. "PADCONFIG19_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x4C 14. "PADCONFIG19_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4C 8. "PADCONFIG19_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x4C 7. "PADCONFIG19_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x4C 0.--3. 1. "PADCONFIG19_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x50 "CFG0_PADCONFIG20" bitfld.long 0x50 31. "PADCONFIG20_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x50 30. "PADCONFIG20_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x50 29. "PADCONFIG20_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x50 28. "PADCONFIG20_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x50 27. "PADCONFIG20_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x50 26. "PADCONFIG20_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x50 25. "PADCONFIG20_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x50 24. "PADCONFIG20_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x50 23. "PADCONFIG20_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x50 22. "PADCONFIG20_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x50 21. "PADCONFIG20_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x50 15. "PADCONFIG20_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x50 14. "PADCONFIG20_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 8. "PADCONFIG20_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x50 7. "PADCONFIG20_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x50 0.--3. 1. "PADCONFIG20_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x54 "CFG0_PADCONFIG21" bitfld.long 0x54 31. "PADCONFIG21_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x54 30. "PADCONFIG21_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x54 29. "PADCONFIG21_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x54 28. "PADCONFIG21_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x54 27. "PADCONFIG21_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x54 26. "PADCONFIG21_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x54 25. "PADCONFIG21_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x54 24. "PADCONFIG21_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x54 23. "PADCONFIG21_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x54 22. "PADCONFIG21_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x54 21. "PADCONFIG21_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x54 15. "PADCONFIG21_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x54 14. "PADCONFIG21_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x54 8. "PADCONFIG21_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x54 7. "PADCONFIG21_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x54 0.--3. 1. "PADCONFIG21_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x58 "CFG0_PADCONFIG22" bitfld.long 0x58 31. "PADCONFIG22_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x58 30. "PADCONFIG22_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x58 29. "PADCONFIG22_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x58 28. "PADCONFIG22_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x58 27. "PADCONFIG22_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x58 26. "PADCONFIG22_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x58 25. "PADCONFIG22_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x58 24. "PADCONFIG22_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x58 23. "PADCONFIG22_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x58 22. "PADCONFIG22_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x58 21. "PADCONFIG22_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x58 15. "PADCONFIG22_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x58 14. "PADCONFIG22_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 8. "PADCONFIG22_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x58 7. "PADCONFIG22_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x58 0.--3. 1. "PADCONFIG22_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x5C "CFG0_PADCONFIG23" bitfld.long 0x5C 31. "PADCONFIG23_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x5C 30. "PADCONFIG23_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x5C 29. "PADCONFIG23_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x5C 28. "PADCONFIG23_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x5C 27. "PADCONFIG23_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x5C 26. "PADCONFIG23_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x5C 25. "PADCONFIG23_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x5C 24. "PADCONFIG23_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x5C 23. "PADCONFIG23_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x5C 22. "PADCONFIG23_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x5C 15. "PADCONFIG23_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x5C 14. "PADCONFIG23_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x5C 8. "PADCONFIG23_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x5C 7. "PADCONFIG23_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x5C 0.--3. 1. "PADCONFIG23_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x60 "CFG0_PADCONFIG24" bitfld.long 0x60 31. "PADCONFIG24_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x60 30. "PADCONFIG24_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x60 29. "PADCONFIG24_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x60 28. "PADCONFIG24_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x60 27. "PADCONFIG24_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x60 26. "PADCONFIG24_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x60 25. "PADCONFIG24_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x60 24. "PADCONFIG24_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x60 23. "PADCONFIG24_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x60 22. "PADCONFIG24_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x60 21. "PADCONFIG24_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x60 15. "PADCONFIG24_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x60 14. "PADCONFIG24_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 8. "PADCONFIG24_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x60 7. "PADCONFIG24_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "PADCONFIG24_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x64 "CFG0_PADCONFIG25" bitfld.long 0x64 31. "PADCONFIG25_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x64 30. "PADCONFIG25_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x64 29. "PADCONFIG25_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x64 28. "PADCONFIG25_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x64 27. "PADCONFIG25_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x64 26. "PADCONFIG25_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x64 25. "PADCONFIG25_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x64 24. "PADCONFIG25_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x64 23. "PADCONFIG25_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x64 22. "PADCONFIG25_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x64 21. "PADCONFIG25_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x64 15. "PADCONFIG25_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x64 14. "PADCONFIG25_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x64 8. "PADCONFIG25_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x64 7. "PADCONFIG25_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x64 0.--3. 1. "PADCONFIG25_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x68 "CFG0_PADCONFIG26" bitfld.long 0x68 31. "PADCONFIG26_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x68 30. "PADCONFIG26_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x68 29. "PADCONFIG26_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x68 28. "PADCONFIG26_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x68 27. "PADCONFIG26_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x68 26. "PADCONFIG26_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x68 25. "PADCONFIG26_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x68 24. "PADCONFIG26_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x68 23. "PADCONFIG26_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x68 22. "PADCONFIG26_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x68 21. "PADCONFIG26_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x68 15. "PADCONFIG26_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x68 14. "PADCONFIG26_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 8. "PADCONFIG26_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x68 7. "PADCONFIG26_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x68 0.--3. 1. "PADCONFIG26_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x6C "CFG0_PADCONFIG27" bitfld.long 0x6C 31. "PADCONFIG27_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x6C 30. "PADCONFIG27_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x6C 29. "PADCONFIG27_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x6C 28. "PADCONFIG27_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x6C 27. "PADCONFIG27_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x6C 26. "PADCONFIG27_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x6C 25. "PADCONFIG27_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x6C 24. "PADCONFIG27_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x6C 23. "PADCONFIG27_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x6C 22. "PADCONFIG27_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x6C 15. "PADCONFIG27_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x6C 14. "PADCONFIG27_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x6C 8. "PADCONFIG27_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x6C 7. "PADCONFIG27_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x6C 0.--3. 1. "PADCONFIG27_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x70 "CFG0_PADCONFIG28" bitfld.long 0x70 31. "PADCONFIG28_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x70 30. "PADCONFIG28_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x70 29. "PADCONFIG28_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x70 28. "PADCONFIG28_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x70 27. "PADCONFIG28_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x70 26. "PADCONFIG28_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x70 25. "PADCONFIG28_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x70 24. "PADCONFIG28_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x70 23. "PADCONFIG28_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x70 22. "PADCONFIG28_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x70 21. "PADCONFIG28_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x70 15. "PADCONFIG28_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x70 14. "PADCONFIG28_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 8. "PADCONFIG28_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x70 7. "PADCONFIG28_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x70 0.--3. 1. "PADCONFIG28_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x74 "CFG0_PADCONFIG29" bitfld.long 0x74 31. "PADCONFIG29_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x74 30. "PADCONFIG29_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x74 29. "PADCONFIG29_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x74 28. "PADCONFIG29_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x74 27. "PADCONFIG29_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x74 26. "PADCONFIG29_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x74 25. "PADCONFIG29_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x74 24. "PADCONFIG29_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x74 23. "PADCONFIG29_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x74 22. "PADCONFIG29_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x74 21. "PADCONFIG29_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x74 15. "PADCONFIG29_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x74 14. "PADCONFIG29_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x74 8. "PADCONFIG29_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x74 7. "PADCONFIG29_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x74 0.--3. 1. "PADCONFIG29_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x78 "CFG0_PADCONFIG30" bitfld.long 0x78 31. "PADCONFIG30_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x78 30. "PADCONFIG30_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x78 29. "PADCONFIG30_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x78 28. "PADCONFIG30_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x78 27. "PADCONFIG30_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x78 26. "PADCONFIG30_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x78 25. "PADCONFIG30_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x78 24. "PADCONFIG30_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x78 23. "PADCONFIG30_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x78 22. "PADCONFIG30_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x78 21. "PADCONFIG30_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x78 15. "PADCONFIG30_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x78 14. "PADCONFIG30_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 8. "PADCONFIG30_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x78 7. "PADCONFIG30_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x78 0.--3. 1. "PADCONFIG30_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x7C "CFG0_PADCONFIG31" bitfld.long 0x7C 31. "PADCONFIG31_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x7C 30. "PADCONFIG31_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x7C 29. "PADCONFIG31_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x7C 28. "PADCONFIG31_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x7C 27. "PADCONFIG31_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x7C 26. "PADCONFIG31_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x7C 25. "PADCONFIG31_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x7C 24. "PADCONFIG31_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x7C 23. "PADCONFIG31_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x7C 22. "PADCONFIG31_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x7C 15. "PADCONFIG31_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x7C 14. "PADCONFIG31_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x7C 8. "PADCONFIG31_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x7C 7. "PADCONFIG31_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x7C 0.--3. 1. "PADCONFIG31_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x80 "CFG0_PADCONFIG32" bitfld.long 0x80 31. "PADCONFIG32_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x80 30. "PADCONFIG32_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x80 29. "PADCONFIG32_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x80 28. "PADCONFIG32_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x80 27. "PADCONFIG32_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x80 26. "PADCONFIG32_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x80 25. "PADCONFIG32_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x80 24. "PADCONFIG32_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x80 23. "PADCONFIG32_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x80 22. "PADCONFIG32_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x80 21. "PADCONFIG32_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x80 15. "PADCONFIG32_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x80 14. "PADCONFIG32_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 8. "PADCONFIG32_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x80 7. "PADCONFIG32_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "PADCONFIG32_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x84 "CFG0_PADCONFIG33" bitfld.long 0x84 31. "PADCONFIG33_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x84 30. "PADCONFIG33_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x84 29. "PADCONFIG33_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x84 28. "PADCONFIG33_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x84 27. "PADCONFIG33_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x84 26. "PADCONFIG33_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x84 25. "PADCONFIG33_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x84 24. "PADCONFIG33_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x84 23. "PADCONFIG33_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x84 22. "PADCONFIG33_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x84 21. "PADCONFIG33_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x84 19.--20. "PADCONFIG33_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x84 18. "PADCONFIG33_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x84 17. "PADCONFIG33_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x84 16. "PADCONFIG33_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x84 15. "PADCONFIG33_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x84 14. "PADCONFIG33_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x84 11.--13. "PADCONFIG33_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x84 8. "PADCONFIG33_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x84 7. "PADCONFIG33_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x84 0.--3. 1. "PADCONFIG33_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x88 "CFG0_PADCONFIG34" bitfld.long 0x88 31. "PADCONFIG34_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x88 30. "PADCONFIG34_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x88 29. "PADCONFIG34_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x88 28. "PADCONFIG34_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x88 27. "PADCONFIG34_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x88 26. "PADCONFIG34_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x88 25. "PADCONFIG34_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x88 24. "PADCONFIG34_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x88 23. "PADCONFIG34_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x88 22. "PADCONFIG34_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x88 21. "PADCONFIG34_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x88 19.--20. "PADCONFIG34_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x88 18. "PADCONFIG34_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x88 17. "PADCONFIG34_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x88 16. "PADCONFIG34_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x88 15. "PADCONFIG34_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x88 14. "PADCONFIG34_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x88 11.--13. "PADCONFIG34_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 8. "PADCONFIG34_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x88 7. "PADCONFIG34_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x88 0.--3. 1. "PADCONFIG34_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x8C "CFG0_PADCONFIG35" bitfld.long 0x8C 31. "PADCONFIG35_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x8C 30. "PADCONFIG35_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x8C 29. "PADCONFIG35_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x8C 28. "PADCONFIG35_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x8C 27. "PADCONFIG35_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x8C 26. "PADCONFIG35_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x8C 25. "PADCONFIG35_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x8C 24. "PADCONFIG35_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x8C 23. "PADCONFIG35_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x8C 22. "PADCONFIG35_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x8C 21. "PADCONFIG35_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x8C 19.--20. "PADCONFIG35_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8C 18. "PADCONFIG35_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x8C 17. "PADCONFIG35_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x8C 16. "PADCONFIG35_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x8C 15. "PADCONFIG35_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x8C 14. "PADCONFIG35_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x8C 11.--13. "PADCONFIG35_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8C 8. "PADCONFIG35_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x8C 7. "PADCONFIG35_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x8C 0.--3. 1. "PADCONFIG35_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x90 "CFG0_PADCONFIG36" bitfld.long 0x90 31. "PADCONFIG36_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x90 30. "PADCONFIG36_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x90 29. "PADCONFIG36_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x90 28. "PADCONFIG36_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x90 27. "PADCONFIG36_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x90 26. "PADCONFIG36_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x90 25. "PADCONFIG36_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x90 24. "PADCONFIG36_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x90 23. "PADCONFIG36_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x90 22. "PADCONFIG36_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x90 21. "PADCONFIG36_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x90 19.--20. "PADCONFIG36_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x90 18. "PADCONFIG36_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x90 17. "PADCONFIG36_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x90 16. "PADCONFIG36_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x90 15. "PADCONFIG36_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x90 14. "PADCONFIG36_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x90 11.--13. "PADCONFIG36_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 8. "PADCONFIG36_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x90 7. "PADCONFIG36_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x90 0.--3. 1. "PADCONFIG36_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x94 "CFG0_PADCONFIG37" bitfld.long 0x94 31. "PADCONFIG37_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x94 30. "PADCONFIG37_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x94 29. "PADCONFIG37_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x94 28. "PADCONFIG37_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x94 27. "PADCONFIG37_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x94 26. "PADCONFIG37_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x94 25. "PADCONFIG37_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x94 24. "PADCONFIG37_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x94 23. "PADCONFIG37_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x94 22. "PADCONFIG37_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x94 21. "PADCONFIG37_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x94 19.--20. "PADCONFIG37_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x94 18. "PADCONFIG37_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x94 17. "PADCONFIG37_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x94 16. "PADCONFIG37_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x94 15. "PADCONFIG37_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x94 14. "PADCONFIG37_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x94 11.--13. "PADCONFIG37_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x94 8. "PADCONFIG37_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x94 7. "PADCONFIG37_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x94 0.--3. 1. "PADCONFIG37_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x98 "CFG0_PADCONFIG38" bitfld.long 0x98 31. "PADCONFIG38_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x98 30. "PADCONFIG38_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x98 29. "PADCONFIG38_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x98 28. "PADCONFIG38_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x98 27. "PADCONFIG38_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x98 26. "PADCONFIG38_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x98 25. "PADCONFIG38_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x98 24. "PADCONFIG38_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x98 23. "PADCONFIG38_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x98 22. "PADCONFIG38_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x98 21. "PADCONFIG38_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x98 19.--20. "PADCONFIG38_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x98 18. "PADCONFIG38_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x98 17. "PADCONFIG38_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x98 16. "PADCONFIG38_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x98 15. "PADCONFIG38_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x98 14. "PADCONFIG38_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x98 11.--13. "PADCONFIG38_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 8. "PADCONFIG38_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x98 7. "PADCONFIG38_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x98 0.--3. 1. "PADCONFIG38_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x9C "CFG0_PADCONFIG39" bitfld.long 0x9C 31. "PADCONFIG39_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x9C 30. "PADCONFIG39_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x9C 29. "PADCONFIG39_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x9C 28. "PADCONFIG39_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x9C 27. "PADCONFIG39_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x9C 26. "PADCONFIG39_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x9C 25. "PADCONFIG39_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x9C 24. "PADCONFIG39_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x9C 23. "PADCONFIG39_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x9C 22. "PADCONFIG39_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x9C 21. "PADCONFIG39_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x9C 19.--20. "PADCONFIG39_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x9C 18. "PADCONFIG39_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x9C 17. "PADCONFIG39_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x9C 16. "PADCONFIG39_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x9C 15. "PADCONFIG39_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x9C 14. "PADCONFIG39_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x9C 11.--13. "PADCONFIG39_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x9C 8. "PADCONFIG39_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x9C 7. "PADCONFIG39_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x9C 0.--3. 1. "PADCONFIG39_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xA0 "CFG0_PADCONFIG40" bitfld.long 0xA0 31. "PADCONFIG40_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xA0 30. "PADCONFIG40_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xA0 29. "PADCONFIG40_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xA0 28. "PADCONFIG40_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xA0 27. "PADCONFIG40_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xA0 26. "PADCONFIG40_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xA0 25. "PADCONFIG40_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xA0 24. "PADCONFIG40_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xA0 23. "PADCONFIG40_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xA0 22. "PADCONFIG40_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xA0 21. "PADCONFIG40_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xA0 19.--20. "PADCONFIG40_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA0 18. "PADCONFIG40_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xA0 17. "PADCONFIG40_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xA0 16. "PADCONFIG40_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xA0 15. "PADCONFIG40_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xA0 14. "PADCONFIG40_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xA0 11.--13. "PADCONFIG40_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 8. "PADCONFIG40_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xA0 7. "PADCONFIG40_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "PADCONFIG40_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xA4 "CFG0_PADCONFIG41" bitfld.long 0xA4 31. "PADCONFIG41_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xA4 30. "PADCONFIG41_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xA4 29. "PADCONFIG41_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xA4 28. "PADCONFIG41_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xA4 27. "PADCONFIG41_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xA4 26. "PADCONFIG41_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xA4 25. "PADCONFIG41_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xA4 24. "PADCONFIG41_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xA4 23. "PADCONFIG41_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xA4 22. "PADCONFIG41_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xA4 21. "PADCONFIG41_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xA4 19.--20. "PADCONFIG41_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA4 18. "PADCONFIG41_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xA4 17. "PADCONFIG41_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xA4 16. "PADCONFIG41_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xA4 15. "PADCONFIG41_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xA4 14. "PADCONFIG41_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xA4 11.--13. "PADCONFIG41_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA4 8. "PADCONFIG41_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xA4 7. "PADCONFIG41_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xA4 0.--3. 1. "PADCONFIG41_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xA8 "CFG0_PADCONFIG42" bitfld.long 0xA8 31. "PADCONFIG42_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xA8 30. "PADCONFIG42_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xA8 29. "PADCONFIG42_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xA8 28. "PADCONFIG42_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xA8 27. "PADCONFIG42_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xA8 26. "PADCONFIG42_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xA8 25. "PADCONFIG42_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xA8 24. "PADCONFIG42_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xA8 23. "PADCONFIG42_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xA8 22. "PADCONFIG42_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xA8 21. "PADCONFIG42_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xA8 19.--20. "PADCONFIG42_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA8 18. "PADCONFIG42_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xA8 17. "PADCONFIG42_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xA8 16. "PADCONFIG42_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xA8 15. "PADCONFIG42_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xA8 14. "PADCONFIG42_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xA8 11.--13. "PADCONFIG42_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 8. "PADCONFIG42_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xA8 7. "PADCONFIG42_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xA8 0.--3. 1. "PADCONFIG42_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xAC "CFG0_PADCONFIG43" bitfld.long 0xAC 31. "PADCONFIG43_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xAC 30. "PADCONFIG43_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xAC 29. "PADCONFIG43_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xAC 28. "PADCONFIG43_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xAC 27. "PADCONFIG43_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xAC 26. "PADCONFIG43_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xAC 25. "PADCONFIG43_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xAC 24. "PADCONFIG43_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xAC 23. "PADCONFIG43_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xAC 22. "PADCONFIG43_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xAC 21. "PADCONFIG43_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xAC 19.--20. "PADCONFIG43_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xAC 18. "PADCONFIG43_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xAC 17. "PADCONFIG43_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xAC 16. "PADCONFIG43_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xAC 15. "PADCONFIG43_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xAC 14. "PADCONFIG43_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xAC 11.--13. "PADCONFIG43_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xAC 8. "PADCONFIG43_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xAC 7. "PADCONFIG43_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xAC 0.--3. 1. "PADCONFIG43_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xB0 "CFG0_PADCONFIG44" bitfld.long 0xB0 31. "PADCONFIG44_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xB0 30. "PADCONFIG44_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xB0 29. "PADCONFIG44_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xB0 28. "PADCONFIG44_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xB0 27. "PADCONFIG44_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xB0 26. "PADCONFIG44_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xB0 25. "PADCONFIG44_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xB0 24. "PADCONFIG44_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xB0 23. "PADCONFIG44_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xB0 22. "PADCONFIG44_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xB0 21. "PADCONFIG44_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xB0 19.--20. "PADCONFIG44_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB0 18. "PADCONFIG44_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xB0 17. "PADCONFIG44_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xB0 16. "PADCONFIG44_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xB0 15. "PADCONFIG44_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xB0 14. "PADCONFIG44_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xB0 11.--13. "PADCONFIG44_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 8. "PADCONFIG44_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xB0 7. "PADCONFIG44_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xB0 0.--3. 1. "PADCONFIG44_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xB4 "CFG0_PADCONFIG45" bitfld.long 0xB4 31. "PADCONFIG45_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xB4 30. "PADCONFIG45_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xB4 29. "PADCONFIG45_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xB4 28. "PADCONFIG45_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xB4 27. "PADCONFIG45_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xB4 26. "PADCONFIG45_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xB4 25. "PADCONFIG45_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xB4 24. "PADCONFIG45_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xB4 23. "PADCONFIG45_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xB4 22. "PADCONFIG45_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xB4 21. "PADCONFIG45_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xB4 19.--20. "PADCONFIG45_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB4 18. "PADCONFIG45_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xB4 17. "PADCONFIG45_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xB4 16. "PADCONFIG45_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xB4 15. "PADCONFIG45_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xB4 14. "PADCONFIG45_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xB4 11.--13. "PADCONFIG45_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB4 8. "PADCONFIG45_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xB4 7. "PADCONFIG45_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xB4 0.--3. 1. "PADCONFIG45_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xB8 "CFG0_PADCONFIG46" bitfld.long 0xB8 31. "PADCONFIG46_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xB8 30. "PADCONFIG46_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xB8 29. "PADCONFIG46_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xB8 28. "PADCONFIG46_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xB8 27. "PADCONFIG46_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xB8 26. "PADCONFIG46_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xB8 25. "PADCONFIG46_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xB8 24. "PADCONFIG46_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xB8 23. "PADCONFIG46_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xB8 22. "PADCONFIG46_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xB8 21. "PADCONFIG46_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xB8 19.--20. "PADCONFIG46_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB8 18. "PADCONFIG46_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xB8 17. "PADCONFIG46_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xB8 16. "PADCONFIG46_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xB8 15. "PADCONFIG46_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xB8 14. "PADCONFIG46_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xB8 11.--13. "PADCONFIG46_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 8. "PADCONFIG46_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xB8 7. "PADCONFIG46_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xB8 0.--3. 1. "PADCONFIG46_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xBC "CFG0_PADCONFIG47" bitfld.long 0xBC 31. "PADCONFIG47_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xBC 30. "PADCONFIG47_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xBC 29. "PADCONFIG47_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xBC 28. "PADCONFIG47_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xBC 27. "PADCONFIG47_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xBC 26. "PADCONFIG47_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xBC 25. "PADCONFIG47_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xBC 24. "PADCONFIG47_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xBC 23. "PADCONFIG47_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xBC 22. "PADCONFIG47_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xBC 21. "PADCONFIG47_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xBC 19.--20. "PADCONFIG47_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xBC 18. "PADCONFIG47_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xBC 17. "PADCONFIG47_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xBC 16. "PADCONFIG47_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xBC 15. "PADCONFIG47_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xBC 14. "PADCONFIG47_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xBC 11.--13. "PADCONFIG47_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xBC 8. "PADCONFIG47_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xBC 7. "PADCONFIG47_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xBC 0.--3. 1. "PADCONFIG47_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xC0 "CFG0_PADCONFIG48" bitfld.long 0xC0 31. "PADCONFIG48_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xC0 30. "PADCONFIG48_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xC0 29. "PADCONFIG48_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xC0 28. "PADCONFIG48_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xC0 27. "PADCONFIG48_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xC0 26. "PADCONFIG48_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xC0 25. "PADCONFIG48_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xC0 24. "PADCONFIG48_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xC0 23. "PADCONFIG48_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xC0 22. "PADCONFIG48_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xC0 21. "PADCONFIG48_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xC0 19.--20. "PADCONFIG48_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC0 18. "PADCONFIG48_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xC0 17. "PADCONFIG48_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xC0 16. "PADCONFIG48_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xC0 15. "PADCONFIG48_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xC0 14. "PADCONFIG48_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xC0 11.--13. "PADCONFIG48_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 8. "PADCONFIG48_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xC0 7. "PADCONFIG48_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "PADCONFIG48_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xC4 "CFG0_PADCONFIG49" bitfld.long 0xC4 31. "PADCONFIG49_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xC4 30. "PADCONFIG49_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xC4 29. "PADCONFIG49_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xC4 28. "PADCONFIG49_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xC4 27. "PADCONFIG49_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xC4 26. "PADCONFIG49_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xC4 25. "PADCONFIG49_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xC4 24. "PADCONFIG49_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xC4 23. "PADCONFIG49_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xC4 22. "PADCONFIG49_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xC4 21. "PADCONFIG49_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xC4 19.--20. "PADCONFIG49_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC4 18. "PADCONFIG49_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xC4 17. "PADCONFIG49_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xC4 16. "PADCONFIG49_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xC4 15. "PADCONFIG49_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xC4 14. "PADCONFIG49_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xC4 11.--13. "PADCONFIG49_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC4 8. "PADCONFIG49_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xC4 7. "PADCONFIG49_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xC4 0.--3. 1. "PADCONFIG49_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xC8 "CFG0_PADCONFIG50" bitfld.long 0xC8 31. "PADCONFIG50_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xC8 30. "PADCONFIG50_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xC8 29. "PADCONFIG50_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xC8 28. "PADCONFIG50_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xC8 27. "PADCONFIG50_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xC8 26. "PADCONFIG50_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xC8 25. "PADCONFIG50_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xC8 24. "PADCONFIG50_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xC8 23. "PADCONFIG50_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xC8 22. "PADCONFIG50_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xC8 21. "PADCONFIG50_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xC8 19.--20. "PADCONFIG50_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC8 18. "PADCONFIG50_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xC8 17. "PADCONFIG50_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xC8 16. "PADCONFIG50_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xC8 15. "PADCONFIG50_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xC8 14. "PADCONFIG50_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xC8 11.--13. "PADCONFIG50_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 8. "PADCONFIG50_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xC8 7. "PADCONFIG50_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xC8 0.--3. 1. "PADCONFIG50_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xCC "CFG0_PADCONFIG51" bitfld.long 0xCC 31. "PADCONFIG51_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xCC 30. "PADCONFIG51_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xCC 29. "PADCONFIG51_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xCC 28. "PADCONFIG51_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xCC 27. "PADCONFIG51_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xCC 26. "PADCONFIG51_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xCC 25. "PADCONFIG51_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xCC 24. "PADCONFIG51_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xCC 23. "PADCONFIG51_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xCC 22. "PADCONFIG51_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xCC 21. "PADCONFIG51_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xCC 19.--20. "PADCONFIG51_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xCC 18. "PADCONFIG51_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xCC 17. "PADCONFIG51_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xCC 16. "PADCONFIG51_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xCC 15. "PADCONFIG51_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xCC 14. "PADCONFIG51_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xCC 11.--13. "PADCONFIG51_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xCC 8. "PADCONFIG51_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xCC 7. "PADCONFIG51_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xCC 0.--3. 1. "PADCONFIG51_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xD0 "CFG0_PADCONFIG52" bitfld.long 0xD0 31. "PADCONFIG52_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xD0 30. "PADCONFIG52_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xD0 29. "PADCONFIG52_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xD0 28. "PADCONFIG52_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xD0 27. "PADCONFIG52_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xD0 26. "PADCONFIG52_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xD0 25. "PADCONFIG52_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xD0 24. "PADCONFIG52_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xD0 23. "PADCONFIG52_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xD0 22. "PADCONFIG52_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xD0 21. "PADCONFIG52_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xD0 19.--20. "PADCONFIG52_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xD0 18. "PADCONFIG52_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xD0 17. "PADCONFIG52_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xD0 16. "PADCONFIG52_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xD0 15. "PADCONFIG52_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xD0 14. "PADCONFIG52_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xD0 11.--13. "PADCONFIG52_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 8. "PADCONFIG52_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xD0 7. "PADCONFIG52_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xD0 0.--3. 1. "PADCONFIG52_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xD4 "CFG0_PADCONFIG53" bitfld.long 0xD4 31. "PADCONFIG53_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xD4 30. "PADCONFIG53_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xD4 29. "PADCONFIG53_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xD4 28. "PADCONFIG53_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xD4 27. "PADCONFIG53_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xD4 26. "PADCONFIG53_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xD4 25. "PADCONFIG53_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xD4 24. "PADCONFIG53_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xD4 23. "PADCONFIG53_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xD4 22. "PADCONFIG53_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xD4 21. "PADCONFIG53_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xD4 19.--20. "PADCONFIG53_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xD4 18. "PADCONFIG53_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xD4 17. "PADCONFIG53_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xD4 16. "PADCONFIG53_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xD4 15. "PADCONFIG53_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xD4 14. "PADCONFIG53_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xD4 11.--13. "PADCONFIG53_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD4 8. "PADCONFIG53_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xD4 7. "PADCONFIG53_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xD4 0.--3. 1. "PADCONFIG53_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xD8 "CFG0_PADCONFIG54" bitfld.long 0xD8 31. "PADCONFIG54_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xD8 30. "PADCONFIG54_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xD8 29. "PADCONFIG54_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xD8 28. "PADCONFIG54_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xD8 27. "PADCONFIG54_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xD8 26. "PADCONFIG54_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xD8 25. "PADCONFIG54_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xD8 24. "PADCONFIG54_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xD8 23. "PADCONFIG54_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xD8 22. "PADCONFIG54_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xD8 21. "PADCONFIG54_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xD8 19.--20. "PADCONFIG54_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xD8 18. "PADCONFIG54_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xD8 17. "PADCONFIG54_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xD8 16. "PADCONFIG54_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xD8 15. "PADCONFIG54_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xD8 14. "PADCONFIG54_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xD8 11.--13. "PADCONFIG54_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 8. "PADCONFIG54_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xD8 7. "PADCONFIG54_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xD8 0.--3. 1. "PADCONFIG54_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xDC "CFG0_PADCONFIG55" bitfld.long 0xDC 31. "PADCONFIG55_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xDC 30. "PADCONFIG55_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xDC 29. "PADCONFIG55_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xDC 28. "PADCONFIG55_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xDC 27. "PADCONFIG55_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xDC 26. "PADCONFIG55_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xDC 25. "PADCONFIG55_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xDC 24. "PADCONFIG55_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xDC 23. "PADCONFIG55_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xDC 22. "PADCONFIG55_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xDC 21. "PADCONFIG55_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xDC 19.--20. "PADCONFIG55_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xDC 18. "PADCONFIG55_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xDC 17. "PADCONFIG55_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xDC 16. "PADCONFIG55_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xDC 15. "PADCONFIG55_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xDC 14. "PADCONFIG55_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xDC 11.--13. "PADCONFIG55_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xDC 8. "PADCONFIG55_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xDC 7. "PADCONFIG55_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xDC 0.--3. 1. "PADCONFIG55_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xE0 "CFG0_PADCONFIG56" bitfld.long 0xE0 31. "PADCONFIG56_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xE0 30. "PADCONFIG56_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xE0 29. "PADCONFIG56_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xE0 28. "PADCONFIG56_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xE0 27. "PADCONFIG56_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xE0 26. "PADCONFIG56_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xE0 25. "PADCONFIG56_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xE0 24. "PADCONFIG56_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xE0 23. "PADCONFIG56_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xE0 22. "PADCONFIG56_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xE0 21. "PADCONFIG56_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xE0 19.--20. "PADCONFIG56_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xE0 18. "PADCONFIG56_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xE0 17. "PADCONFIG56_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xE0 16. "PADCONFIG56_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xE0 15. "PADCONFIG56_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xE0 14. "PADCONFIG56_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xE0 11.--13. "PADCONFIG56_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 8. "PADCONFIG56_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xE0 7. "PADCONFIG56_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "PADCONFIG56_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xE4 "CFG0_PADCONFIG57" bitfld.long 0xE4 31. "PADCONFIG57_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xE4 30. "PADCONFIG57_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xE4 29. "PADCONFIG57_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xE4 28. "PADCONFIG57_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xE4 27. "PADCONFIG57_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xE4 26. "PADCONFIG57_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xE4 25. "PADCONFIG57_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xE4 24. "PADCONFIG57_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xE4 23. "PADCONFIG57_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xE4 22. "PADCONFIG57_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xE4 21. "PADCONFIG57_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xE4 19.--20. "PADCONFIG57_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xE4 18. "PADCONFIG57_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xE4 17. "PADCONFIG57_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xE4 16. "PADCONFIG57_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xE4 15. "PADCONFIG57_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xE4 14. "PADCONFIG57_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xE4 11.--13. "PADCONFIG57_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE4 8. "PADCONFIG57_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xE4 7. "PADCONFIG57_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xE4 0.--3. 1. "PADCONFIG57_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xE8 "CFG0_PADCONFIG58" bitfld.long 0xE8 31. "PADCONFIG58_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xE8 30. "PADCONFIG58_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xE8 29. "PADCONFIG58_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xE8 28. "PADCONFIG58_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xE8 27. "PADCONFIG58_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xE8 26. "PADCONFIG58_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xE8 25. "PADCONFIG58_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xE8 24. "PADCONFIG58_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xE8 23. "PADCONFIG58_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xE8 22. "PADCONFIG58_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xE8 21. "PADCONFIG58_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xE8 19.--20. "PADCONFIG58_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xE8 18. "PADCONFIG58_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xE8 17. "PADCONFIG58_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xE8 16. "PADCONFIG58_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xE8 15. "PADCONFIG58_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xE8 14. "PADCONFIG58_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xE8 11.--13. "PADCONFIG58_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 8. "PADCONFIG58_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xE8 7. "PADCONFIG58_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xE8 0.--3. 1. "PADCONFIG58_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xEC "CFG0_PADCONFIG59" bitfld.long 0xEC 31. "PADCONFIG59_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xEC 30. "PADCONFIG59_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xEC 29. "PADCONFIG59_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xEC 28. "PADCONFIG59_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xEC 27. "PADCONFIG59_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xEC 26. "PADCONFIG59_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xEC 25. "PADCONFIG59_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xEC 24. "PADCONFIG59_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xEC 23. "PADCONFIG59_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xEC 22. "PADCONFIG59_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xEC 21. "PADCONFIG59_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xEC 19.--20. "PADCONFIG59_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xEC 18. "PADCONFIG59_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xEC 17. "PADCONFIG59_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xEC 16. "PADCONFIG59_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xEC 15. "PADCONFIG59_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xEC 14. "PADCONFIG59_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xEC 11.--13. "PADCONFIG59_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xEC 8. "PADCONFIG59_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xEC 7. "PADCONFIG59_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xEC 0.--3. 1. "PADCONFIG59_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xF0 "CFG0_PADCONFIG60" bitfld.long 0xF0 31. "PADCONFIG60_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xF0 30. "PADCONFIG60_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xF0 29. "PADCONFIG60_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xF0 28. "PADCONFIG60_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xF0 27. "PADCONFIG60_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xF0 26. "PADCONFIG60_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xF0 25. "PADCONFIG60_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xF0 24. "PADCONFIG60_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xF0 23. "PADCONFIG60_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xF0 22. "PADCONFIG60_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xF0 21. "PADCONFIG60_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xF0 19.--20. "PADCONFIG60_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xF0 18. "PADCONFIG60_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xF0 17. "PADCONFIG60_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xF0 16. "PADCONFIG60_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xF0 15. "PADCONFIG60_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xF0 14. "PADCONFIG60_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xF0 11.--13. "PADCONFIG60_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 8. "PADCONFIG60_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xF0 7. "PADCONFIG60_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xF0 0.--3. 1. "PADCONFIG60_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xF4 "CFG0_PADCONFIG61" bitfld.long 0xF4 31. "PADCONFIG61_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xF4 30. "PADCONFIG61_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xF4 29. "PADCONFIG61_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xF4 28. "PADCONFIG61_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xF4 27. "PADCONFIG61_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xF4 26. "PADCONFIG61_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xF4 25. "PADCONFIG61_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xF4 24. "PADCONFIG61_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xF4 23. "PADCONFIG61_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xF4 22. "PADCONFIG61_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xF4 21. "PADCONFIG61_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xF4 19.--20. "PADCONFIG61_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xF4 18. "PADCONFIG61_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xF4 17. "PADCONFIG61_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xF4 16. "PADCONFIG61_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xF4 15. "PADCONFIG61_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xF4 14. "PADCONFIG61_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xF4 11.--13. "PADCONFIG61_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF4 8. "PADCONFIG61_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xF4 7. "PADCONFIG61_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xF4 0.--3. 1. "PADCONFIG61_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xF8 "CFG0_PADCONFIG62" bitfld.long 0xF8 31. "PADCONFIG62_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xF8 30. "PADCONFIG62_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xF8 29. "PADCONFIG62_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xF8 28. "PADCONFIG62_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xF8 27. "PADCONFIG62_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xF8 26. "PADCONFIG62_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xF8 25. "PADCONFIG62_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xF8 24. "PADCONFIG62_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xF8 23. "PADCONFIG62_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xF8 22. "PADCONFIG62_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xF8 21. "PADCONFIG62_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xF8 19.--20. "PADCONFIG62_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xF8 18. "PADCONFIG62_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xF8 17. "PADCONFIG62_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xF8 16. "PADCONFIG62_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xF8 15. "PADCONFIG62_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xF8 14. "PADCONFIG62_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xF8 11.--13. "PADCONFIG62_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 8. "PADCONFIG62_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xF8 7. "PADCONFIG62_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xF8 0.--3. 1. "PADCONFIG62_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xFC "CFG0_PADCONFIG63" bitfld.long 0xFC 31. "PADCONFIG63_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xFC 30. "PADCONFIG63_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xFC 29. "PADCONFIG63_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xFC 28. "PADCONFIG63_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xFC 27. "PADCONFIG63_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xFC 26. "PADCONFIG63_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xFC 25. "PADCONFIG63_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xFC 24. "PADCONFIG63_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xFC 23. "PADCONFIG63_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xFC 22. "PADCONFIG63_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xFC 21. "PADCONFIG63_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xFC 19.--20. "PADCONFIG63_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xFC 18. "PADCONFIG63_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xFC 17. "PADCONFIG63_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xFC 16. "PADCONFIG63_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xFC 15. "PADCONFIG63_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xFC 14. "PADCONFIG63_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xFC 11.--13. "PADCONFIG63_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xFC 8. "PADCONFIG63_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xFC 7. "PADCONFIG63_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xFC 0.--3. 1. "PADCONFIG63_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x100 "CFG0_PADCONFIG64" bitfld.long 0x100 31. "PADCONFIG64_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x100 30. "PADCONFIG64_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x100 29. "PADCONFIG64_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x100 28. "PADCONFIG64_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x100 27. "PADCONFIG64_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x100 26. "PADCONFIG64_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x100 25. "PADCONFIG64_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x100 24. "PADCONFIG64_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x100 23. "PADCONFIG64_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x100 22. "PADCONFIG64_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x100 21. "PADCONFIG64_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x100 19.--20. "PADCONFIG64_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x100 18. "PADCONFIG64_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x100 17. "PADCONFIG64_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x100 16. "PADCONFIG64_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x100 15. "PADCONFIG64_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x100 14. "PADCONFIG64_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x100 11.--13. "PADCONFIG64_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x100 8. "PADCONFIG64_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x100 7. "PADCONFIG64_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x100 0.--3. 1. "PADCONFIG64_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x104 "CFG0_PADCONFIG65" bitfld.long 0x104 31. "PADCONFIG65_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x104 30. "PADCONFIG65_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x104 29. "PADCONFIG65_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x104 28. "PADCONFIG65_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x104 27. "PADCONFIG65_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x104 26. "PADCONFIG65_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x104 25. "PADCONFIG65_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x104 24. "PADCONFIG65_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x104 23. "PADCONFIG65_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x104 22. "PADCONFIG65_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x104 21. "PADCONFIG65_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x104 19.--20. "PADCONFIG65_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x104 18. "PADCONFIG65_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x104 17. "PADCONFIG65_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x104 16. "PADCONFIG65_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x104 15. "PADCONFIG65_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x104 14. "PADCONFIG65_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x104 11.--13. "PADCONFIG65_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x104 8. "PADCONFIG65_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x104 7. "PADCONFIG65_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x104 0.--3. 1. "PADCONFIG65_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x108 "CFG0_PADCONFIG66" bitfld.long 0x108 31. "PADCONFIG66_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x108 30. "PADCONFIG66_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x108 29. "PADCONFIG66_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x108 28. "PADCONFIG66_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x108 27. "PADCONFIG66_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x108 26. "PADCONFIG66_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x108 25. "PADCONFIG66_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x108 24. "PADCONFIG66_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x108 23. "PADCONFIG66_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x108 22. "PADCONFIG66_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x108 21. "PADCONFIG66_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x108 19.--20. "PADCONFIG66_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x108 18. "PADCONFIG66_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x108 17. "PADCONFIG66_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x108 16. "PADCONFIG66_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x108 15. "PADCONFIG66_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x108 14. "PADCONFIG66_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x108 11.--13. "PADCONFIG66_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x108 8. "PADCONFIG66_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x108 7. "PADCONFIG66_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x108 0.--3. 1. "PADCONFIG66_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x10C "CFG0_PADCONFIG67" bitfld.long 0x10C 31. "PADCONFIG67_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x10C 30. "PADCONFIG67_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x10C 29. "PADCONFIG67_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x10C 28. "PADCONFIG67_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x10C 27. "PADCONFIG67_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x10C 26. "PADCONFIG67_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x10C 25. "PADCONFIG67_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x10C 24. "PADCONFIG67_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x10C 23. "PADCONFIG67_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x10C 22. "PADCONFIG67_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x10C 21. "PADCONFIG67_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x10C 19.--20. "PADCONFIG67_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10C 18. "PADCONFIG67_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x10C 17. "PADCONFIG67_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x10C 16. "PADCONFIG67_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x10C 15. "PADCONFIG67_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x10C 14. "PADCONFIG67_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x10C 11.--13. "PADCONFIG67_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10C 8. "PADCONFIG67_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x10C 7. "PADCONFIG67_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x10C 0.--3. 1. "PADCONFIG67_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x110 "CFG0_PADCONFIG68" bitfld.long 0x110 31. "PADCONFIG68_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x110 30. "PADCONFIG68_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x110 29. "PADCONFIG68_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x110 28. "PADCONFIG68_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x110 27. "PADCONFIG68_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x110 26. "PADCONFIG68_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x110 25. "PADCONFIG68_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x110 24. "PADCONFIG68_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x110 23. "PADCONFIG68_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x110 22. "PADCONFIG68_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x110 21. "PADCONFIG68_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x110 19.--20. "PADCONFIG68_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x110 18. "PADCONFIG68_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x110 17. "PADCONFIG68_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x110 16. "PADCONFIG68_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x110 15. "PADCONFIG68_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x110 14. "PADCONFIG68_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x110 11.--13. "PADCONFIG68_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x110 8. "PADCONFIG68_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x110 7. "PADCONFIG68_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x110 0.--3. 1. "PADCONFIG68_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x114 "CFG0_PADCONFIG69" bitfld.long 0x114 31. "PADCONFIG69_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x114 30. "PADCONFIG69_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x114 29. "PADCONFIG69_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x114 28. "PADCONFIG69_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x114 27. "PADCONFIG69_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x114 26. "PADCONFIG69_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x114 25. "PADCONFIG69_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x114 24. "PADCONFIG69_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x114 23. "PADCONFIG69_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x114 22. "PADCONFIG69_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x114 21. "PADCONFIG69_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x114 19.--20. "PADCONFIG69_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x114 18. "PADCONFIG69_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x114 17. "PADCONFIG69_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x114 16. "PADCONFIG69_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x114 15. "PADCONFIG69_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x114 14. "PADCONFIG69_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x114 11.--13. "PADCONFIG69_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x114 8. "PADCONFIG69_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x114 7. "PADCONFIG69_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x114 0.--3. 1. "PADCONFIG69_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x118 "CFG0_PADCONFIG70" bitfld.long 0x118 31. "PADCONFIG70_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x118 30. "PADCONFIG70_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x118 29. "PADCONFIG70_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x118 28. "PADCONFIG70_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x118 27. "PADCONFIG70_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x118 26. "PADCONFIG70_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x118 25. "PADCONFIG70_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x118 24. "PADCONFIG70_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x118 23. "PADCONFIG70_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x118 22. "PADCONFIG70_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x118 21. "PADCONFIG70_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x118 19.--20. "PADCONFIG70_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x118 18. "PADCONFIG70_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x118 17. "PADCONFIG70_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x118 16. "PADCONFIG70_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x118 15. "PADCONFIG70_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x118 14. "PADCONFIG70_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x118 11.--13. "PADCONFIG70_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x118 8. "PADCONFIG70_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x118 7. "PADCONFIG70_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x118 0.--3. 1. "PADCONFIG70_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x11C "CFG0_PADCONFIG71" bitfld.long 0x11C 31. "PADCONFIG71_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x11C 30. "PADCONFIG71_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x11C 29. "PADCONFIG71_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x11C 28. "PADCONFIG71_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x11C 27. "PADCONFIG71_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x11C 26. "PADCONFIG71_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x11C 25. "PADCONFIG71_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x11C 24. "PADCONFIG71_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x11C 23. "PADCONFIG71_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x11C 22. "PADCONFIG71_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x11C 21. "PADCONFIG71_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x11C 19.--20. "PADCONFIG71_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x11C 18. "PADCONFIG71_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x11C 17. "PADCONFIG71_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x11C 16. "PADCONFIG71_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x11C 15. "PADCONFIG71_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x11C 14. "PADCONFIG71_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x11C 11.--13. "PADCONFIG71_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x11C 8. "PADCONFIG71_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x11C 7. "PADCONFIG71_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x11C 0.--3. 1. "PADCONFIG71_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x120 "CFG0_PADCONFIG72" bitfld.long 0x120 31. "PADCONFIG72_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x120 30. "PADCONFIG72_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x120 29. "PADCONFIG72_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x120 28. "PADCONFIG72_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x120 27. "PADCONFIG72_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x120 26. "PADCONFIG72_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x120 25. "PADCONFIG72_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x120 24. "PADCONFIG72_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x120 23. "PADCONFIG72_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x120 22. "PADCONFIG72_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x120 21. "PADCONFIG72_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x120 19.--20. "PADCONFIG72_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x120 18. "PADCONFIG72_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x120 17. "PADCONFIG72_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x120 16. "PADCONFIG72_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x120 15. "PADCONFIG72_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x120 14. "PADCONFIG72_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x120 11.--13. "PADCONFIG72_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x120 8. "PADCONFIG72_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x120 7. "PADCONFIG72_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x120 0.--3. 1. "PADCONFIG72_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x124 "CFG0_PADCONFIG73" bitfld.long 0x124 31. "PADCONFIG73_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x124 30. "PADCONFIG73_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x124 29. "PADCONFIG73_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x124 28. "PADCONFIG73_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x124 27. "PADCONFIG73_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x124 26. "PADCONFIG73_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x124 25. "PADCONFIG73_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x124 24. "PADCONFIG73_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x124 23. "PADCONFIG73_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x124 22. "PADCONFIG73_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x124 21. "PADCONFIG73_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x124 19.--20. "PADCONFIG73_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x124 18. "PADCONFIG73_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x124 17. "PADCONFIG73_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x124 16. "PADCONFIG73_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x124 15. "PADCONFIG73_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x124 14. "PADCONFIG73_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x124 11.--13. "PADCONFIG73_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x124 8. "PADCONFIG73_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x124 7. "PADCONFIG73_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x124 0.--3. 1. "PADCONFIG73_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x128 "CFG0_PADCONFIG74" bitfld.long 0x128 31. "PADCONFIG74_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x128 30. "PADCONFIG74_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x128 29. "PADCONFIG74_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x128 28. "PADCONFIG74_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x128 27. "PADCONFIG74_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x128 26. "PADCONFIG74_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x128 25. "PADCONFIG74_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x128 24. "PADCONFIG74_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x128 23. "PADCONFIG74_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x128 22. "PADCONFIG74_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x128 21. "PADCONFIG74_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x128 19.--20. "PADCONFIG74_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x128 18. "PADCONFIG74_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x128 17. "PADCONFIG74_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x128 16. "PADCONFIG74_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x128 15. "PADCONFIG74_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x128 14. "PADCONFIG74_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x128 11.--13. "PADCONFIG74_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x128 8. "PADCONFIG74_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x128 7. "PADCONFIG74_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x128 0.--3. 1. "PADCONFIG74_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x12C "CFG0_PADCONFIG75" bitfld.long 0x12C 31. "PADCONFIG75_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x12C 30. "PADCONFIG75_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x12C 29. "PADCONFIG75_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x12C 28. "PADCONFIG75_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x12C 27. "PADCONFIG75_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x12C 26. "PADCONFIG75_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x12C 25. "PADCONFIG75_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x12C 24. "PADCONFIG75_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x12C 23. "PADCONFIG75_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x12C 22. "PADCONFIG75_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x12C 21. "PADCONFIG75_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x12C 19.--20. "PADCONFIG75_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x12C 18. "PADCONFIG75_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x12C 17. "PADCONFIG75_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x12C 16. "PADCONFIG75_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x12C 15. "PADCONFIG75_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x12C 14. "PADCONFIG75_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x12C 11.--13. "PADCONFIG75_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x12C 8. "PADCONFIG75_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x12C 7. "PADCONFIG75_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x12C 0.--3. 1. "PADCONFIG75_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x130 "CFG0_PADCONFIG76" bitfld.long 0x130 31. "PADCONFIG76_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x130 30. "PADCONFIG76_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x130 29. "PADCONFIG76_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x130 28. "PADCONFIG76_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x130 27. "PADCONFIG76_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x130 26. "PADCONFIG76_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x130 25. "PADCONFIG76_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x130 24. "PADCONFIG76_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x130 23. "PADCONFIG76_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x130 22. "PADCONFIG76_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x130 21. "PADCONFIG76_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x130 19.--20. "PADCONFIG76_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x130 18. "PADCONFIG76_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x130 17. "PADCONFIG76_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x130 16. "PADCONFIG76_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x130 15. "PADCONFIG76_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x130 14. "PADCONFIG76_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x130 11.--13. "PADCONFIG76_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x130 8. "PADCONFIG76_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x130 7. "PADCONFIG76_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x130 0.--3. 1. "PADCONFIG76_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x134 "CFG0_PADCONFIG77" bitfld.long 0x134 31. "PADCONFIG77_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x134 30. "PADCONFIG77_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x134 29. "PADCONFIG77_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x134 28. "PADCONFIG77_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x134 27. "PADCONFIG77_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x134 26. "PADCONFIG77_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x134 25. "PADCONFIG77_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x134 24. "PADCONFIG77_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x134 23. "PADCONFIG77_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x134 22. "PADCONFIG77_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x134 21. "PADCONFIG77_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x134 19.--20. "PADCONFIG77_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x134 18. "PADCONFIG77_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x134 17. "PADCONFIG77_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x134 16. "PADCONFIG77_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x134 15. "PADCONFIG77_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x134 14. "PADCONFIG77_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x134 11.--13. "PADCONFIG77_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x134 8. "PADCONFIG77_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x134 7. "PADCONFIG77_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x134 0.--3. 1. "PADCONFIG77_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x138 "CFG0_PADCONFIG78" bitfld.long 0x138 31. "PADCONFIG78_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x138 30. "PADCONFIG78_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x138 29. "PADCONFIG78_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x138 28. "PADCONFIG78_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x138 27. "PADCONFIG78_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x138 26. "PADCONFIG78_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x138 25. "PADCONFIG78_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x138 24. "PADCONFIG78_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x138 23. "PADCONFIG78_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x138 22. "PADCONFIG78_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x138 21. "PADCONFIG78_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x138 19.--20. "PADCONFIG78_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x138 18. "PADCONFIG78_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x138 17. "PADCONFIG78_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x138 16. "PADCONFIG78_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x138 15. "PADCONFIG78_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x138 14. "PADCONFIG78_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x138 11.--13. "PADCONFIG78_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x138 8. "PADCONFIG78_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x138 7. "PADCONFIG78_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x138 0.--3. 1. "PADCONFIG78_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x13C "CFG0_PADCONFIG79" bitfld.long 0x13C 31. "PADCONFIG79_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x13C 30. "PADCONFIG79_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x13C 29. "PADCONFIG79_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x13C 28. "PADCONFIG79_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x13C 27. "PADCONFIG79_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x13C 26. "PADCONFIG79_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x13C 25. "PADCONFIG79_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x13C 24. "PADCONFIG79_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x13C 23. "PADCONFIG79_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x13C 22. "PADCONFIG79_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x13C 21. "PADCONFIG79_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x13C 19.--20. "PADCONFIG79_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x13C 18. "PADCONFIG79_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x13C 17. "PADCONFIG79_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x13C 16. "PADCONFIG79_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x13C 15. "PADCONFIG79_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x13C 14. "PADCONFIG79_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x13C 11.--13. "PADCONFIG79_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x13C 8. "PADCONFIG79_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x13C 7. "PADCONFIG79_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x13C 0.--3. 1. "PADCONFIG79_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x140 "CFG0_PADCONFIG80" bitfld.long 0x140 31. "PADCONFIG80_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x140 30. "PADCONFIG80_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x140 29. "PADCONFIG80_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x140 28. "PADCONFIG80_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x140 27. "PADCONFIG80_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x140 26. "PADCONFIG80_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x140 25. "PADCONFIG80_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x140 24. "PADCONFIG80_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x140 23. "PADCONFIG80_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x140 22. "PADCONFIG80_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x140 21. "PADCONFIG80_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x140 19.--20. "PADCONFIG80_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x140 18. "PADCONFIG80_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x140 17. "PADCONFIG80_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x140 16. "PADCONFIG80_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x140 15. "PADCONFIG80_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x140 14. "PADCONFIG80_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x140 11.--13. "PADCONFIG80_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x140 8. "PADCONFIG80_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x140 7. "PADCONFIG80_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x140 0.--3. 1. "PADCONFIG80_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x144 "CFG0_PADCONFIG81" bitfld.long 0x144 31. "PADCONFIG81_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x144 30. "PADCONFIG81_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x144 29. "PADCONFIG81_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x144 28. "PADCONFIG81_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x144 27. "PADCONFIG81_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x144 26. "PADCONFIG81_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x144 25. "PADCONFIG81_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x144 24. "PADCONFIG81_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x144 23. "PADCONFIG81_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x144 22. "PADCONFIG81_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x144 21. "PADCONFIG81_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x144 19.--20. "PADCONFIG81_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x144 18. "PADCONFIG81_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x144 17. "PADCONFIG81_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x144 16. "PADCONFIG81_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x144 15. "PADCONFIG81_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x144 14. "PADCONFIG81_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x144 11.--13. "PADCONFIG81_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x144 8. "PADCONFIG81_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x144 7. "PADCONFIG81_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x144 0.--3. 1. "PADCONFIG81_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x148 "CFG0_PADCONFIG82" bitfld.long 0x148 31. "PADCONFIG82_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x148 30. "PADCONFIG82_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x148 29. "PADCONFIG82_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x148 28. "PADCONFIG82_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x148 27. "PADCONFIG82_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x148 26. "PADCONFIG82_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x148 25. "PADCONFIG82_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x148 24. "PADCONFIG82_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x148 23. "PADCONFIG82_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x148 22. "PADCONFIG82_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x148 21. "PADCONFIG82_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x148 19.--20. "PADCONFIG82_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x148 18. "PADCONFIG82_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x148 17. "PADCONFIG82_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x148 16. "PADCONFIG82_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x148 15. "PADCONFIG82_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x148 14. "PADCONFIG82_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x148 11.--13. "PADCONFIG82_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x148 8. "PADCONFIG82_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x148 7. "PADCONFIG82_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x148 0.--3. 1. "PADCONFIG82_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x14C "CFG0_PADCONFIG83" bitfld.long 0x14C 31. "PADCONFIG83_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x14C 30. "PADCONFIG83_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x14C 29. "PADCONFIG83_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x14C 28. "PADCONFIG83_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x14C 27. "PADCONFIG83_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x14C 26. "PADCONFIG83_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x14C 25. "PADCONFIG83_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x14C 24. "PADCONFIG83_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x14C 23. "PADCONFIG83_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x14C 22. "PADCONFIG83_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x14C 21. "PADCONFIG83_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x14C 19.--20. "PADCONFIG83_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14C 18. "PADCONFIG83_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x14C 17. "PADCONFIG83_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x14C 16. "PADCONFIG83_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x14C 15. "PADCONFIG83_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x14C 14. "PADCONFIG83_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x14C 11.--13. "PADCONFIG83_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14C 8. "PADCONFIG83_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x14C 7. "PADCONFIG83_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x14C 0.--3. 1. "PADCONFIG83_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x150 "CFG0_PADCONFIG84" bitfld.long 0x150 31. "PADCONFIG84_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x150 30. "PADCONFIG84_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x150 29. "PADCONFIG84_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x150 28. "PADCONFIG84_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x150 27. "PADCONFIG84_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x150 26. "PADCONFIG84_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x150 25. "PADCONFIG84_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x150 24. "PADCONFIG84_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x150 23. "PADCONFIG84_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x150 22. "PADCONFIG84_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x150 21. "PADCONFIG84_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x150 19.--20. "PADCONFIG84_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x150 18. "PADCONFIG84_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x150 17. "PADCONFIG84_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x150 16. "PADCONFIG84_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x150 15. "PADCONFIG84_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x150 14. "PADCONFIG84_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x150 11.--13. "PADCONFIG84_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x150 8. "PADCONFIG84_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x150 7. "PADCONFIG84_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x150 0.--3. 1. "PADCONFIG84_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x154 "CFG0_PADCONFIG85" bitfld.long 0x154 31. "PADCONFIG85_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x154 30. "PADCONFIG85_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x154 29. "PADCONFIG85_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x154 28. "PADCONFIG85_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x154 27. "PADCONFIG85_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x154 26. "PADCONFIG85_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x154 25. "PADCONFIG85_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x154 24. "PADCONFIG85_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x154 23. "PADCONFIG85_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x154 22. "PADCONFIG85_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x154 21. "PADCONFIG85_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x154 19.--20. "PADCONFIG85_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x154 18. "PADCONFIG85_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x154 17. "PADCONFIG85_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x154 16. "PADCONFIG85_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x154 15. "PADCONFIG85_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x154 14. "PADCONFIG85_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x154 11.--13. "PADCONFIG85_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x154 8. "PADCONFIG85_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x154 7. "PADCONFIG85_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x154 0.--3. 1. "PADCONFIG85_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x158 "CFG0_PADCONFIG86" bitfld.long 0x158 31. "PADCONFIG86_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x158 30. "PADCONFIG86_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x158 29. "PADCONFIG86_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x158 28. "PADCONFIG86_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x158 27. "PADCONFIG86_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x158 26. "PADCONFIG86_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x158 25. "PADCONFIG86_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x158 24. "PADCONFIG86_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x158 23. "PADCONFIG86_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x158 22. "PADCONFIG86_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x158 21. "PADCONFIG86_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x158 19.--20. "PADCONFIG86_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x158 18. "PADCONFIG86_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x158 17. "PADCONFIG86_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x158 16. "PADCONFIG86_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x158 15. "PADCONFIG86_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x158 14. "PADCONFIG86_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x158 11.--13. "PADCONFIG86_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x158 8. "PADCONFIG86_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x158 7. "PADCONFIG86_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x158 0.--3. 1. "PADCONFIG86_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x15C "CFG0_PADCONFIG87" bitfld.long 0x15C 31. "PADCONFIG87_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x15C 30. "PADCONFIG87_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x15C 29. "PADCONFIG87_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x15C 28. "PADCONFIG87_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x15C 27. "PADCONFIG87_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x15C 26. "PADCONFIG87_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x15C 25. "PADCONFIG87_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x15C 24. "PADCONFIG87_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x15C 23. "PADCONFIG87_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x15C 22. "PADCONFIG87_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x15C 21. "PADCONFIG87_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x15C 19.--20. "PADCONFIG87_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x15C 18. "PADCONFIG87_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x15C 17. "PADCONFIG87_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x15C 16. "PADCONFIG87_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x15C 15. "PADCONFIG87_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x15C 14. "PADCONFIG87_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x15C 11.--13. "PADCONFIG87_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x15C 8. "PADCONFIG87_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x15C 7. "PADCONFIG87_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x15C 0.--3. 1. "PADCONFIG87_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x160 "CFG0_PADCONFIG88" bitfld.long 0x160 31. "PADCONFIG88_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x160 30. "PADCONFIG88_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x160 29. "PADCONFIG88_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x160 28. "PADCONFIG88_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x160 27. "PADCONFIG88_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x160 26. "PADCONFIG88_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x160 25. "PADCONFIG88_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x160 24. "PADCONFIG88_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x160 23. "PADCONFIG88_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x160 22. "PADCONFIG88_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x160 21. "PADCONFIG88_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x160 19.--20. "PADCONFIG88_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x160 18. "PADCONFIG88_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x160 17. "PADCONFIG88_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x160 16. "PADCONFIG88_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x160 15. "PADCONFIG88_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x160 14. "PADCONFIG88_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x160 11.--13. "PADCONFIG88_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x160 8. "PADCONFIG88_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x160 7. "PADCONFIG88_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x160 0.--3. 1. "PADCONFIG88_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x164 "CFG0_PADCONFIG89" bitfld.long 0x164 31. "PADCONFIG89_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x164 30. "PADCONFIG89_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x164 29. "PADCONFIG89_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x164 28. "PADCONFIG89_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x164 27. "PADCONFIG89_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x164 26. "PADCONFIG89_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x164 25. "PADCONFIG89_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x164 24. "PADCONFIG89_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x164 23. "PADCONFIG89_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x164 22. "PADCONFIG89_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x164 21. "PADCONFIG89_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x164 19.--20. "PADCONFIG89_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x164 18. "PADCONFIG89_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x164 17. "PADCONFIG89_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x164 16. "PADCONFIG89_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x164 15. "PADCONFIG89_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x164 14. "PADCONFIG89_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x164 11.--13. "PADCONFIG89_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x164 8. "PADCONFIG89_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x164 7. "PADCONFIG89_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x164 0.--3. 1. "PADCONFIG89_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x168 "CFG0_PADCONFIG90" bitfld.long 0x168 31. "PADCONFIG90_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x168 30. "PADCONFIG90_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x168 29. "PADCONFIG90_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x168 28. "PADCONFIG90_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x168 27. "PADCONFIG90_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x168 26. "PADCONFIG90_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x168 25. "PADCONFIG90_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x168 24. "PADCONFIG90_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x168 23. "PADCONFIG90_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x168 22. "PADCONFIG90_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x168 21. "PADCONFIG90_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x168 19.--20. "PADCONFIG90_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x168 18. "PADCONFIG90_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x168 17. "PADCONFIG90_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x168 16. "PADCONFIG90_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x168 15. "PADCONFIG90_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x168 14. "PADCONFIG90_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x168 11.--13. "PADCONFIG90_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x168 8. "PADCONFIG90_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x168 7. "PADCONFIG90_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x168 0.--3. 1. "PADCONFIG90_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x16C "CFG0_PADCONFIG91" bitfld.long 0x16C 31. "PADCONFIG91_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x16C 30. "PADCONFIG91_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x16C 29. "PADCONFIG91_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x16C 28. "PADCONFIG91_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x16C 27. "PADCONFIG91_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x16C 26. "PADCONFIG91_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x16C 25. "PADCONFIG91_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x16C 24. "PADCONFIG91_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x16C 23. "PADCONFIG91_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x16C 22. "PADCONFIG91_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x16C 21. "PADCONFIG91_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x16C 19.--20. "PADCONFIG91_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x16C 18. "PADCONFIG91_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x16C 17. "PADCONFIG91_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x16C 16. "PADCONFIG91_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x16C 15. "PADCONFIG91_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x16C 14. "PADCONFIG91_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x16C 11.--13. "PADCONFIG91_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x16C 8. "PADCONFIG91_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x16C 7. "PADCONFIG91_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x16C 0.--3. 1. "PADCONFIG91_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x170 "CFG0_PADCONFIG92" bitfld.long 0x170 31. "PADCONFIG92_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x170 30. "PADCONFIG92_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x170 29. "PADCONFIG92_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x170 28. "PADCONFIG92_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x170 27. "PADCONFIG92_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x170 26. "PADCONFIG92_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x170 25. "PADCONFIG92_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x170 24. "PADCONFIG92_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x170 23. "PADCONFIG92_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x170 22. "PADCONFIG92_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x170 21. "PADCONFIG92_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x170 19.--20. "PADCONFIG92_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x170 18. "PADCONFIG92_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x170 17. "PADCONFIG92_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x170 16. "PADCONFIG92_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x170 15. "PADCONFIG92_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x170 14. "PADCONFIG92_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x170 11.--13. "PADCONFIG92_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x170 8. "PADCONFIG92_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x170 7. "PADCONFIG92_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x170 0.--3. 1. "PADCONFIG92_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x174 "CFG0_PADCONFIG93" bitfld.long 0x174 31. "PADCONFIG93_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x174 30. "PADCONFIG93_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x174 29. "PADCONFIG93_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x174 28. "PADCONFIG93_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x174 27. "PADCONFIG93_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x174 26. "PADCONFIG93_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x174 25. "PADCONFIG93_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x174 24. "PADCONFIG93_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x174 23. "PADCONFIG93_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x174 22. "PADCONFIG93_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x174 21. "PADCONFIG93_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x174 19.--20. "PADCONFIG93_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x174 18. "PADCONFIG93_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x174 17. "PADCONFIG93_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x174 16. "PADCONFIG93_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x174 15. "PADCONFIG93_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x174 14. "PADCONFIG93_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x174 11.--13. "PADCONFIG93_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x174 8. "PADCONFIG93_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x174 7. "PADCONFIG93_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x174 0.--3. 1. "PADCONFIG93_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x178 "CFG0_PADCONFIG94" bitfld.long 0x178 31. "PADCONFIG94_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x178 30. "PADCONFIG94_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x178 29. "PADCONFIG94_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x178 28. "PADCONFIG94_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x178 27. "PADCONFIG94_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x178 26. "PADCONFIG94_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x178 25. "PADCONFIG94_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x178 24. "PADCONFIG94_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x178 23. "PADCONFIG94_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x178 22. "PADCONFIG94_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x178 21. "PADCONFIG94_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x178 19.--20. "PADCONFIG94_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x178 18. "PADCONFIG94_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x178 17. "PADCONFIG94_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x178 16. "PADCONFIG94_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x178 15. "PADCONFIG94_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x178 14. "PADCONFIG94_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x178 11.--13. "PADCONFIG94_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x178 8. "PADCONFIG94_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x178 7. "PADCONFIG94_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x178 0.--3. 1. "PADCONFIG94_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x17C "CFG0_PADCONFIG95" bitfld.long 0x17C 31. "PADCONFIG95_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x17C 30. "PADCONFIG95_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x17C 29. "PADCONFIG95_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x17C 28. "PADCONFIG95_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x17C 27. "PADCONFIG95_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x17C 26. "PADCONFIG95_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x17C 25. "PADCONFIG95_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x17C 24. "PADCONFIG95_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x17C 23. "PADCONFIG95_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x17C 22. "PADCONFIG95_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x17C 21. "PADCONFIG95_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x17C 19.--20. "PADCONFIG95_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x17C 18. "PADCONFIG95_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x17C 17. "PADCONFIG95_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x17C 16. "PADCONFIG95_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x17C 15. "PADCONFIG95_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x17C 14. "PADCONFIG95_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x17C 11.--13. "PADCONFIG95_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x17C 8. "PADCONFIG95_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x17C 7. "PADCONFIG95_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x17C 0.--3. 1. "PADCONFIG95_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x180 "CFG0_PADCONFIG96" bitfld.long 0x180 31. "PADCONFIG96_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x180 30. "PADCONFIG96_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x180 29. "PADCONFIG96_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x180 28. "PADCONFIG96_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x180 27. "PADCONFIG96_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x180 26. "PADCONFIG96_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x180 25. "PADCONFIG96_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x180 24. "PADCONFIG96_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x180 23. "PADCONFIG96_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x180 22. "PADCONFIG96_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x180 21. "PADCONFIG96_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x180 19.--20. "PADCONFIG96_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x180 18. "PADCONFIG96_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x180 17. "PADCONFIG96_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x180 16. "PADCONFIG96_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x180 15. "PADCONFIG96_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x180 14. "PADCONFIG96_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x180 11.--13. "PADCONFIG96_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x180 8. "PADCONFIG96_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x180 7. "PADCONFIG96_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x180 0.--3. 1. "PADCONFIG96_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x184 "CFG0_PADCONFIG97" bitfld.long 0x184 31. "PADCONFIG97_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x184 30. "PADCONFIG97_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x184 29. "PADCONFIG97_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x184 28. "PADCONFIG97_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x184 27. "PADCONFIG97_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x184 26. "PADCONFIG97_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x184 25. "PADCONFIG97_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x184 24. "PADCONFIG97_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x184 23. "PADCONFIG97_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x184 22. "PADCONFIG97_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x184 21. "PADCONFIG97_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x184 19.--20. "PADCONFIG97_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x184 18. "PADCONFIG97_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x184 17. "PADCONFIG97_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x184 16. "PADCONFIG97_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x184 15. "PADCONFIG97_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x184 14. "PADCONFIG97_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x184 11.--13. "PADCONFIG97_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x184 8. "PADCONFIG97_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x184 7. "PADCONFIG97_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x184 0.--3. 1. "PADCONFIG97_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x188 "CFG0_PADCONFIG98" bitfld.long 0x188 31. "PADCONFIG98_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x188 30. "PADCONFIG98_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x188 29. "PADCONFIG98_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x188 28. "PADCONFIG98_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x188 27. "PADCONFIG98_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x188 26. "PADCONFIG98_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x188 25. "PADCONFIG98_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x188 24. "PADCONFIG98_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x188 23. "PADCONFIG98_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x188 22. "PADCONFIG98_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x188 21. "PADCONFIG98_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x188 19.--20. "PADCONFIG98_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x188 18. "PADCONFIG98_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x188 17. "PADCONFIG98_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x188 16. "PADCONFIG98_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x188 15. "PADCONFIG98_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x188 14. "PADCONFIG98_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x188 11.--13. "PADCONFIG98_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x188 8. "PADCONFIG98_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x188 7. "PADCONFIG98_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x188 0.--3. 1. "PADCONFIG98_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x18C "CFG0_PADCONFIG99" bitfld.long 0x18C 31. "PADCONFIG99_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x18C 30. "PADCONFIG99_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x18C 29. "PADCONFIG99_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x18C 28. "PADCONFIG99_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x18C 27. "PADCONFIG99_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x18C 26. "PADCONFIG99_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x18C 25. "PADCONFIG99_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x18C 24. "PADCONFIG99_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x18C 23. "PADCONFIG99_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x18C 22. "PADCONFIG99_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x18C 21. "PADCONFIG99_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x18C 19.--20. "PADCONFIG99_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18C 18. "PADCONFIG99_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x18C 17. "PADCONFIG99_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x18C 16. "PADCONFIG99_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x18C 15. "PADCONFIG99_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x18C 14. "PADCONFIG99_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x18C 11.--13. "PADCONFIG99_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18C 8. "PADCONFIG99_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x18C 7. "PADCONFIG99_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x18C 0.--3. 1. "PADCONFIG99_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x190 "CFG0_PADCONFIG100" bitfld.long 0x190 31. "PADCONFIG100_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x190 30. "PADCONFIG100_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x190 29. "PADCONFIG100_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x190 28. "PADCONFIG100_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x190 27. "PADCONFIG100_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x190 26. "PADCONFIG100_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x190 25. "PADCONFIG100_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x190 24. "PADCONFIG100_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x190 23. "PADCONFIG100_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x190 22. "PADCONFIG100_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x190 21. "PADCONFIG100_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x190 19.--20. "PADCONFIG100_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x190 18. "PADCONFIG100_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x190 17. "PADCONFIG100_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x190 16. "PADCONFIG100_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x190 15. "PADCONFIG100_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x190 14. "PADCONFIG100_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x190 11.--13. "PADCONFIG100_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x190 8. "PADCONFIG100_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x190 7. "PADCONFIG100_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x190 0.--3. 1. "PADCONFIG100_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x194 "CFG0_PADCONFIG101" bitfld.long 0x194 31. "PADCONFIG101_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x194 30. "PADCONFIG101_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x194 29. "PADCONFIG101_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x194 28. "PADCONFIG101_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x194 27. "PADCONFIG101_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x194 26. "PADCONFIG101_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x194 25. "PADCONFIG101_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x194 24. "PADCONFIG101_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x194 23. "PADCONFIG101_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x194 22. "PADCONFIG101_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x194 21. "PADCONFIG101_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x194 19.--20. "PADCONFIG101_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x194 18. "PADCONFIG101_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x194 17. "PADCONFIG101_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x194 16. "PADCONFIG101_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x194 15. "PADCONFIG101_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x194 14. "PADCONFIG101_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x194 11.--13. "PADCONFIG101_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x194 8. "PADCONFIG101_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x194 7. "PADCONFIG101_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x194 0.--3. 1. "PADCONFIG101_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x198 "CFG0_PADCONFIG102" bitfld.long 0x198 31. "PADCONFIG102_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x198 30. "PADCONFIG102_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x198 29. "PADCONFIG102_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x198 28. "PADCONFIG102_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x198 27. "PADCONFIG102_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x198 26. "PADCONFIG102_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x198 25. "PADCONFIG102_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x198 24. "PADCONFIG102_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x198 23. "PADCONFIG102_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x198 22. "PADCONFIG102_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x198 21. "PADCONFIG102_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x198 19.--20. "PADCONFIG102_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x198 18. "PADCONFIG102_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x198 17. "PADCONFIG102_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x198 16. "PADCONFIG102_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x198 15. "PADCONFIG102_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x198 14. "PADCONFIG102_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x198 11.--13. "PADCONFIG102_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x198 8. "PADCONFIG102_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x198 7. "PADCONFIG102_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x198 0.--3. 1. "PADCONFIG102_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x19C "CFG0_PADCONFIG103" bitfld.long 0x19C 31. "PADCONFIG103_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x19C 30. "PADCONFIG103_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x19C 29. "PADCONFIG103_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x19C 28. "PADCONFIG103_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x19C 27. "PADCONFIG103_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x19C 26. "PADCONFIG103_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x19C 25. "PADCONFIG103_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x19C 24. "PADCONFIG103_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x19C 23. "PADCONFIG103_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x19C 22. "PADCONFIG103_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x19C 21. "PADCONFIG103_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x19C 19.--20. "PADCONFIG103_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x19C 18. "PADCONFIG103_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x19C 17. "PADCONFIG103_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x19C 16. "PADCONFIG103_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x19C 15. "PADCONFIG103_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x19C 14. "PADCONFIG103_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x19C 11.--13. "PADCONFIG103_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x19C 8. "PADCONFIG103_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x19C 7. "PADCONFIG103_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x19C 0.--3. 1. "PADCONFIG103_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1A0 "CFG0_PADCONFIG104" bitfld.long 0x1A0 31. "PADCONFIG104_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1A0 30. "PADCONFIG104_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1A0 29. "PADCONFIG104_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1A0 28. "PADCONFIG104_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1A0 27. "PADCONFIG104_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1A0 26. "PADCONFIG104_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1A0 25. "PADCONFIG104_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1A0 24. "PADCONFIG104_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1A0 23. "PADCONFIG104_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1A0 22. "PADCONFIG104_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1A0 21. "PADCONFIG104_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1A0 19.--20. "PADCONFIG104_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1A0 18. "PADCONFIG104_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1A0 17. "PADCONFIG104_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1A0 16. "PADCONFIG104_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1A0 15. "PADCONFIG104_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1A0 14. "PADCONFIG104_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1A0 11.--13. "PADCONFIG104_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1A0 8. "PADCONFIG104_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1A0 7. "PADCONFIG104_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1A0 0.--3. 1. "PADCONFIG104_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1A4 "CFG0_PADCONFIG105" bitfld.long 0x1A4 31. "PADCONFIG105_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1A4 30. "PADCONFIG105_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1A4 29. "PADCONFIG105_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1A4 28. "PADCONFIG105_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1A4 27. "PADCONFIG105_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1A4 26. "PADCONFIG105_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1A4 25. "PADCONFIG105_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1A4 24. "PADCONFIG105_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1A4 23. "PADCONFIG105_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1A4 22. "PADCONFIG105_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1A4 21. "PADCONFIG105_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1A4 19.--20. "PADCONFIG105_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1A4 18. "PADCONFIG105_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1A4 17. "PADCONFIG105_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1A4 16. "PADCONFIG105_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1A4 15. "PADCONFIG105_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1A4 14. "PADCONFIG105_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1A4 11.--13. "PADCONFIG105_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1A4 8. "PADCONFIG105_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1A4 7. "PADCONFIG105_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1A4 0.--3. 1. "PADCONFIG105_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1A8 "CFG0_PADCONFIG106" bitfld.long 0x1A8 31. "PADCONFIG106_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1A8 30. "PADCONFIG106_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1A8 29. "PADCONFIG106_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1A8 28. "PADCONFIG106_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1A8 27. "PADCONFIG106_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1A8 26. "PADCONFIG106_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1A8 25. "PADCONFIG106_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1A8 24. "PADCONFIG106_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1A8 23. "PADCONFIG106_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1A8 22. "PADCONFIG106_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1A8 21. "PADCONFIG106_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1A8 19.--20. "PADCONFIG106_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1A8 18. "PADCONFIG106_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1A8 17. "PADCONFIG106_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1A8 16. "PADCONFIG106_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1A8 15. "PADCONFIG106_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1A8 14. "PADCONFIG106_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1A8 11.--13. "PADCONFIG106_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1A8 8. "PADCONFIG106_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1A8 7. "PADCONFIG106_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1A8 0.--3. 1. "PADCONFIG106_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1AC "CFG0_PADCONFIG107" bitfld.long 0x1AC 31. "PADCONFIG107_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1AC 30. "PADCONFIG107_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1AC 29. "PADCONFIG107_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1AC 28. "PADCONFIG107_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1AC 27. "PADCONFIG107_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1AC 26. "PADCONFIG107_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1AC 25. "PADCONFIG107_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1AC 24. "PADCONFIG107_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1AC 23. "PADCONFIG107_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1AC 22. "PADCONFIG107_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1AC 21. "PADCONFIG107_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1AC 19.--20. "PADCONFIG107_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1AC 18. "PADCONFIG107_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1AC 17. "PADCONFIG107_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1AC 16. "PADCONFIG107_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1AC 15. "PADCONFIG107_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1AC 14. "PADCONFIG107_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1AC 11.--13. "PADCONFIG107_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1AC 8. "PADCONFIG107_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1AC 7. "PADCONFIG107_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1AC 0.--3. 1. "PADCONFIG107_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1B0 "CFG0_PADCONFIG108" bitfld.long 0x1B0 31. "PADCONFIG108_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1B0 30. "PADCONFIG108_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1B0 29. "PADCONFIG108_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1B0 28. "PADCONFIG108_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1B0 27. "PADCONFIG108_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1B0 26. "PADCONFIG108_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1B0 25. "PADCONFIG108_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1B0 24. "PADCONFIG108_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1B0 23. "PADCONFIG108_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1B0 22. "PADCONFIG108_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1B0 21. "PADCONFIG108_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1B0 19.--20. "PADCONFIG108_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1B0 18. "PADCONFIG108_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1B0 17. "PADCONFIG108_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1B0 16. "PADCONFIG108_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1B0 15. "PADCONFIG108_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1B0 14. "PADCONFIG108_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1B0 11.--13. "PADCONFIG108_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1B0 8. "PADCONFIG108_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1B0 7. "PADCONFIG108_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1B0 0.--3. 1. "PADCONFIG108_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1B4 "CFG0_PADCONFIG109" bitfld.long 0x1B4 31. "PADCONFIG109_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1B4 30. "PADCONFIG109_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1B4 29. "PADCONFIG109_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1B4 28. "PADCONFIG109_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1B4 27. "PADCONFIG109_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1B4 26. "PADCONFIG109_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1B4 25. "PADCONFIG109_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1B4 24. "PADCONFIG109_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1B4 23. "PADCONFIG109_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1B4 22. "PADCONFIG109_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1B4 21. "PADCONFIG109_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1B4 19.--20. "PADCONFIG109_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1B4 18. "PADCONFIG109_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1B4 17. "PADCONFIG109_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1B4 16. "PADCONFIG109_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1B4 15. "PADCONFIG109_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1B4 14. "PADCONFIG109_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1B4 11.--13. "PADCONFIG109_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1B4 8. "PADCONFIG109_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1B4 7. "PADCONFIG109_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1B4 0.--3. 1. "PADCONFIG109_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1B8 "CFG0_PADCONFIG110" bitfld.long 0x1B8 31. "PADCONFIG110_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1B8 30. "PADCONFIG110_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1B8 29. "PADCONFIG110_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1B8 28. "PADCONFIG110_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1B8 27. "PADCONFIG110_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1B8 26. "PADCONFIG110_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1B8 25. "PADCONFIG110_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1B8 24. "PADCONFIG110_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1B8 23. "PADCONFIG110_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1B8 22. "PADCONFIG110_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1B8 21. "PADCONFIG110_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1B8 19.--20. "PADCONFIG110_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1B8 18. "PADCONFIG110_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1B8 17. "PADCONFIG110_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1B8 16. "PADCONFIG110_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1B8 15. "PADCONFIG110_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1B8 14. "PADCONFIG110_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1B8 11.--13. "PADCONFIG110_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1B8 8. "PADCONFIG110_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1B8 7. "PADCONFIG110_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1B8 0.--3. 1. "PADCONFIG110_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1BC "CFG0_PADCONFIG111" bitfld.long 0x1BC 31. "PADCONFIG111_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1BC 30. "PADCONFIG111_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1BC 29. "PADCONFIG111_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1BC 28. "PADCONFIG111_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1BC 27. "PADCONFIG111_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1BC 26. "PADCONFIG111_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1BC 25. "PADCONFIG111_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1BC 24. "PADCONFIG111_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1BC 23. "PADCONFIG111_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1BC 22. "PADCONFIG111_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1BC 21. "PADCONFIG111_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1BC 19.--20. "PADCONFIG111_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1BC 18. "PADCONFIG111_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1BC 17. "PADCONFIG111_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1BC 16. "PADCONFIG111_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1BC 15. "PADCONFIG111_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1BC 14. "PADCONFIG111_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1BC 11.--13. "PADCONFIG111_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1BC 8. "PADCONFIG111_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1BC 7. "PADCONFIG111_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1BC 0.--3. 1. "PADCONFIG111_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1C0 "CFG0_PADCONFIG112" bitfld.long 0x1C0 31. "PADCONFIG112_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1C0 30. "PADCONFIG112_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1C0 29. "PADCONFIG112_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1C0 28. "PADCONFIG112_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1C0 27. "PADCONFIG112_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1C0 26. "PADCONFIG112_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1C0 25. "PADCONFIG112_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1C0 24. "PADCONFIG112_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1C0 23. "PADCONFIG112_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1C0 22. "PADCONFIG112_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1C0 21. "PADCONFIG112_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1C0 19.--20. "PADCONFIG112_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C0 18. "PADCONFIG112_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1C0 17. "PADCONFIG112_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1C0 16. "PADCONFIG112_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1C0 15. "PADCONFIG112_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1C0 14. "PADCONFIG112_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1C0 11.--13. "PADCONFIG112_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C0 8. "PADCONFIG112_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1C0 7. "PADCONFIG112_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1C0 0.--3. 1. "PADCONFIG112_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1C4 "CFG0_PADCONFIG113" bitfld.long 0x1C4 31. "PADCONFIG113_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1C4 30. "PADCONFIG113_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1C4 29. "PADCONFIG113_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1C4 28. "PADCONFIG113_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1C4 27. "PADCONFIG113_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1C4 26. "PADCONFIG113_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1C4 25. "PADCONFIG113_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1C4 24. "PADCONFIG113_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1C4 23. "PADCONFIG113_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1C4 22. "PADCONFIG113_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1C4 21. "PADCONFIG113_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1C4 19.--20. "PADCONFIG113_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C4 18. "PADCONFIG113_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1C4 17. "PADCONFIG113_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1C4 16. "PADCONFIG113_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1C4 15. "PADCONFIG113_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1C4 14. "PADCONFIG113_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1C4 11.--13. "PADCONFIG113_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C4 8. "PADCONFIG113_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1C4 7. "PADCONFIG113_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1C4 0.--3. 1. "PADCONFIG113_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1C8 "CFG0_PADCONFIG114" bitfld.long 0x1C8 31. "PADCONFIG114_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1C8 30. "PADCONFIG114_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1C8 29. "PADCONFIG114_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1C8 28. "PADCONFIG114_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1C8 27. "PADCONFIG114_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1C8 26. "PADCONFIG114_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1C8 25. "PADCONFIG114_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1C8 24. "PADCONFIG114_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1C8 23. "PADCONFIG114_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1C8 22. "PADCONFIG114_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1C8 21. "PADCONFIG114_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1C8 19.--20. "PADCONFIG114_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C8 18. "PADCONFIG114_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1C8 17. "PADCONFIG114_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1C8 16. "PADCONFIG114_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1C8 15. "PADCONFIG114_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1C8 14. "PADCONFIG114_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1C8 11.--13. "PADCONFIG114_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C8 8. "PADCONFIG114_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1C8 7. "PADCONFIG114_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1C8 0.--3. 1. "PADCONFIG114_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1CC "CFG0_PADCONFIG115" bitfld.long 0x1CC 31. "PADCONFIG115_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1CC 30. "PADCONFIG115_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1CC 29. "PADCONFIG115_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1CC 28. "PADCONFIG115_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1CC 27. "PADCONFIG115_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1CC 26. "PADCONFIG115_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1CC 25. "PADCONFIG115_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1CC 24. "PADCONFIG115_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1CC 23. "PADCONFIG115_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1CC 22. "PADCONFIG115_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1CC 21. "PADCONFIG115_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1CC 19.--20. "PADCONFIG115_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1CC 18. "PADCONFIG115_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1CC 17. "PADCONFIG115_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1CC 16. "PADCONFIG115_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1CC 15. "PADCONFIG115_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1CC 14. "PADCONFIG115_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1CC 11.--13. "PADCONFIG115_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1CC 8. "PADCONFIG115_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1CC 7. "PADCONFIG115_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1CC 0.--3. 1. "PADCONFIG115_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1D0 "CFG0_PADCONFIG116" bitfld.long 0x1D0 31. "PADCONFIG116_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1D0 30. "PADCONFIG116_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1D0 29. "PADCONFIG116_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1D0 28. "PADCONFIG116_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1D0 27. "PADCONFIG116_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1D0 26. "PADCONFIG116_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1D0 25. "PADCONFIG116_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1D0 24. "PADCONFIG116_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1D0 23. "PADCONFIG116_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1D0 22. "PADCONFIG116_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1D0 21. "PADCONFIG116_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1D0 19.--20. "PADCONFIG116_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1D0 18. "PADCONFIG116_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1D0 17. "PADCONFIG116_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1D0 16. "PADCONFIG116_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1D0 15. "PADCONFIG116_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1D0 14. "PADCONFIG116_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1D0 11.--13. "PADCONFIG116_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1D0 8. "PADCONFIG116_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1D0 7. "PADCONFIG116_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1D0 0.--3. 1. "PADCONFIG116_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1D4 "CFG0_PADCONFIG117" bitfld.long 0x1D4 31. "PADCONFIG117_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1D4 30. "PADCONFIG117_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1D4 29. "PADCONFIG117_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1D4 28. "PADCONFIG117_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1D4 27. "PADCONFIG117_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1D4 26. "PADCONFIG117_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1D4 25. "PADCONFIG117_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1D4 24. "PADCONFIG117_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1D4 23. "PADCONFIG117_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1D4 22. "PADCONFIG117_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1D4 21. "PADCONFIG117_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1D4 19.--20. "PADCONFIG117_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1D4 18. "PADCONFIG117_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1D4 17. "PADCONFIG117_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1D4 16. "PADCONFIG117_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1D4 15. "PADCONFIG117_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1D4 14. "PADCONFIG117_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1D4 11.--13. "PADCONFIG117_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1D4 8. "PADCONFIG117_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1D4 7. "PADCONFIG117_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1D4 0.--3. 1. "PADCONFIG117_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1D8 "CFG0_PADCONFIG118" bitfld.long 0x1D8 31. "PADCONFIG118_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1D8 30. "PADCONFIG118_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1D8 29. "PADCONFIG118_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1D8 28. "PADCONFIG118_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1D8 27. "PADCONFIG118_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1D8 26. "PADCONFIG118_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1D8 25. "PADCONFIG118_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1D8 24. "PADCONFIG118_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1D8 23. "PADCONFIG118_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1D8 22. "PADCONFIG118_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1D8 21. "PADCONFIG118_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1D8 19.--20. "PADCONFIG118_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1D8 18. "PADCONFIG118_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1D8 17. "PADCONFIG118_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1D8 16. "PADCONFIG118_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1D8 15. "PADCONFIG118_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1D8 14. "PADCONFIG118_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1D8 11.--13. "PADCONFIG118_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1D8 8. "PADCONFIG118_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1D8 7. "PADCONFIG118_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1D8 0.--3. 1. "PADCONFIG118_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1DC "CFG0_PADCONFIG119" bitfld.long 0x1DC 31. "PADCONFIG119_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1DC 30. "PADCONFIG119_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1DC 29. "PADCONFIG119_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1DC 28. "PADCONFIG119_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1DC 27. "PADCONFIG119_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1DC 26. "PADCONFIG119_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1DC 25. "PADCONFIG119_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1DC 24. "PADCONFIG119_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1DC 23. "PADCONFIG119_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1DC 22. "PADCONFIG119_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1DC 21. "PADCONFIG119_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1DC 19.--20. "PADCONFIG119_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1DC 18. "PADCONFIG119_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1DC 17. "PADCONFIG119_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1DC 16. "PADCONFIG119_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1DC 15. "PADCONFIG119_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1DC 14. "PADCONFIG119_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1DC 11.--13. "PADCONFIG119_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1DC 8. "PADCONFIG119_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1DC 7. "PADCONFIG119_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1DC 0.--3. 1. "PADCONFIG119_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1E0 "CFG0_PADCONFIG120" bitfld.long 0x1E0 31. "PADCONFIG120_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1E0 30. "PADCONFIG120_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1E0 29. "PADCONFIG120_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1E0 28. "PADCONFIG120_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1E0 27. "PADCONFIG120_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1E0 26. "PADCONFIG120_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1E0 25. "PADCONFIG120_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1E0 24. "PADCONFIG120_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1E0 23. "PADCONFIG120_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1E0 22. "PADCONFIG120_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1E0 21. "PADCONFIG120_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1E0 19.--20. "PADCONFIG120_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1E0 18. "PADCONFIG120_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1E0 17. "PADCONFIG120_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1E0 16. "PADCONFIG120_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1E0 15. "PADCONFIG120_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1E0 14. "PADCONFIG120_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1E0 11.--13. "PADCONFIG120_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1E0 8. "PADCONFIG120_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1E0 7. "PADCONFIG120_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1E0 0.--3. 1. "PADCONFIG120_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1E4 "CFG0_PADCONFIG121" bitfld.long 0x1E4 31. "PADCONFIG121_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1E4 30. "PADCONFIG121_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1E4 29. "PADCONFIG121_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1E4 28. "PADCONFIG121_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1E4 27. "PADCONFIG121_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1E4 26. "PADCONFIG121_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1E4 25. "PADCONFIG121_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1E4 24. "PADCONFIG121_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1E4 23. "PADCONFIG121_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1E4 22. "PADCONFIG121_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1E4 21. "PADCONFIG121_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1E4 19.--20. "PADCONFIG121_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1E4 18. "PADCONFIG121_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1E4 17. "PADCONFIG121_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1E4 16. "PADCONFIG121_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1E4 15. "PADCONFIG121_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1E4 14. "PADCONFIG121_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1E4 11.--13. "PADCONFIG121_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1E4 8. "PADCONFIG121_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1E4 7. "PADCONFIG121_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1E4 0.--3. 1. "PADCONFIG121_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1E8 "CFG0_PADCONFIG122" bitfld.long 0x1E8 31. "PADCONFIG122_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1E8 30. "PADCONFIG122_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1E8 29. "PADCONFIG122_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1E8 28. "PADCONFIG122_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1E8 27. "PADCONFIG122_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1E8 26. "PADCONFIG122_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1E8 25. "PADCONFIG122_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1E8 24. "PADCONFIG122_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1E8 23. "PADCONFIG122_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1E8 22. "PADCONFIG122_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1E8 21. "PADCONFIG122_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1E8 19.--20. "PADCONFIG122_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1E8 18. "PADCONFIG122_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1E8 17. "PADCONFIG122_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1E8 16. "PADCONFIG122_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1E8 15. "PADCONFIG122_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1E8 14. "PADCONFIG122_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1E8 11.--13. "PADCONFIG122_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1E8 8. "PADCONFIG122_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1E8 7. "PADCONFIG122_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1E8 0.--3. 1. "PADCONFIG122_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1EC "CFG0_PADCONFIG123" bitfld.long 0x1EC 31. "PADCONFIG123_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1EC 30. "PADCONFIG123_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1EC 29. "PADCONFIG123_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1EC 28. "PADCONFIG123_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1EC 27. "PADCONFIG123_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1EC 26. "PADCONFIG123_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1EC 25. "PADCONFIG123_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1EC 24. "PADCONFIG123_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1EC 23. "PADCONFIG123_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1EC 22. "PADCONFIG123_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1EC 21. "PADCONFIG123_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1EC 19.--20. "PADCONFIG123_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1EC 18. "PADCONFIG123_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1EC 17. "PADCONFIG123_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1EC 16. "PADCONFIG123_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1EC 15. "PADCONFIG123_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1EC 14. "PADCONFIG123_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1EC 11.--13. "PADCONFIG123_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1EC 8. "PADCONFIG123_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1EC 7. "PADCONFIG123_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1EC 0.--3. 1. "PADCONFIG123_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1F0 "CFG0_PADCONFIG124" bitfld.long 0x1F0 31. "PADCONFIG124_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1F0 30. "PADCONFIG124_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1F0 29. "PADCONFIG124_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1F0 28. "PADCONFIG124_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1F0 27. "PADCONFIG124_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1F0 26. "PADCONFIG124_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1F0 25. "PADCONFIG124_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1F0 24. "PADCONFIG124_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1F0 23. "PADCONFIG124_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1F0 22. "PADCONFIG124_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1F0 21. "PADCONFIG124_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1F0 19.--20. "PADCONFIG124_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1F0 18. "PADCONFIG124_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1F0 17. "PADCONFIG124_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1F0 16. "PADCONFIG124_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1F0 15. "PADCONFIG124_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1F0 14. "PADCONFIG124_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1F0 11.--13. "PADCONFIG124_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1F0 8. "PADCONFIG124_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1F0 7. "PADCONFIG124_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1F0 0.--3. 1. "PADCONFIG124_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1F4 "CFG0_PADCONFIG125" bitfld.long 0x1F4 31. "PADCONFIG125_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1F4 30. "PADCONFIG125_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1F4 29. "PADCONFIG125_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1F4 28. "PADCONFIG125_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1F4 27. "PADCONFIG125_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1F4 26. "PADCONFIG125_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1F4 25. "PADCONFIG125_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1F4 24. "PADCONFIG125_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1F4 23. "PADCONFIG125_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1F4 22. "PADCONFIG125_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1F4 21. "PADCONFIG125_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1F4 19.--20. "PADCONFIG125_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1F4 18. "PADCONFIG125_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1F4 17. "PADCONFIG125_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1F4 16. "PADCONFIG125_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1F4 15. "PADCONFIG125_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1F4 14. "PADCONFIG125_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1F4 11.--13. "PADCONFIG125_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1F4 8. "PADCONFIG125_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1F4 7. "PADCONFIG125_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1F4 0.--3. 1. "PADCONFIG125_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1F8 "CFG0_PADCONFIG126" bitfld.long 0x1F8 31. "PADCONFIG126_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1F8 30. "PADCONFIG126_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1F8 29. "PADCONFIG126_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1F8 28. "PADCONFIG126_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1F8 27. "PADCONFIG126_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1F8 26. "PADCONFIG126_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1F8 25. "PADCONFIG126_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1F8 24. "PADCONFIG126_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1F8 23. "PADCONFIG126_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1F8 22. "PADCONFIG126_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1F8 21. "PADCONFIG126_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1F8 19.--20. "PADCONFIG126_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1F8 18. "PADCONFIG126_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1F8 17. "PADCONFIG126_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1F8 16. "PADCONFIG126_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1F8 15. "PADCONFIG126_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1F8 14. "PADCONFIG126_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1F8 11.--13. "PADCONFIG126_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1F8 8. "PADCONFIG126_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1F8 7. "PADCONFIG126_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1F8 0.--3. 1. "PADCONFIG126_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1FC "CFG0_PADCONFIG127" bitfld.long 0x1FC 31. "PADCONFIG127_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1FC 30. "PADCONFIG127_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1FC 29. "PADCONFIG127_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1FC 28. "PADCONFIG127_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1FC 27. "PADCONFIG127_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1FC 26. "PADCONFIG127_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1FC 25. "PADCONFIG127_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1FC 24. "PADCONFIG127_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1FC 23. "PADCONFIG127_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1FC 22. "PADCONFIG127_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1FC 21. "PADCONFIG127_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1FC 19.--20. "PADCONFIG127_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1FC 18. "PADCONFIG127_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1FC 17. "PADCONFIG127_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1FC 16. "PADCONFIG127_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1FC 15. "PADCONFIG127_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1FC 14. "PADCONFIG127_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1FC 11.--13. "PADCONFIG127_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1FC 8. "PADCONFIG127_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1FC 7. "PADCONFIG127_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1FC 0.--3. 1. "PADCONFIG127_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x200 "CFG0_PADCONFIG128" bitfld.long 0x200 31. "PADCONFIG128_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x200 30. "PADCONFIG128_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x200 29. "PADCONFIG128_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x200 28. "PADCONFIG128_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x200 27. "PADCONFIG128_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x200 26. "PADCONFIG128_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x200 25. "PADCONFIG128_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x200 24. "PADCONFIG128_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x200 23. "PADCONFIG128_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x200 22. "PADCONFIG128_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x200 21. "PADCONFIG128_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x200 19.--20. "PADCONFIG128_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x200 18. "PADCONFIG128_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x200 17. "PADCONFIG128_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x200 16. "PADCONFIG128_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x200 15. "PADCONFIG128_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x200 14. "PADCONFIG128_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x200 11.--13. "PADCONFIG128_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x200 8. "PADCONFIG128_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x200 7. "PADCONFIG128_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x200 0.--3. 1. "PADCONFIG128_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x204 "CFG0_PADCONFIG129" bitfld.long 0x204 31. "PADCONFIG129_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x204 30. "PADCONFIG129_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x204 29. "PADCONFIG129_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x204 28. "PADCONFIG129_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x204 27. "PADCONFIG129_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x204 26. "PADCONFIG129_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x204 25. "PADCONFIG129_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x204 24. "PADCONFIG129_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x204 23. "PADCONFIG129_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x204 22. "PADCONFIG129_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x204 21. "PADCONFIG129_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x204 19.--20. "PADCONFIG129_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x204 18. "PADCONFIG129_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x204 17. "PADCONFIG129_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x204 16. "PADCONFIG129_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x204 15. "PADCONFIG129_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x204 14. "PADCONFIG129_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x204 11.--13. "PADCONFIG129_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x204 8. "PADCONFIG129_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x204 7. "PADCONFIG129_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x204 0.--3. 1. "PADCONFIG129_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x208 "CFG0_PADCONFIG130" bitfld.long 0x208 31. "PADCONFIG130_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x208 30. "PADCONFIG130_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x208 29. "PADCONFIG130_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x208 28. "PADCONFIG130_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x208 27. "PADCONFIG130_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x208 26. "PADCONFIG130_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x208 25. "PADCONFIG130_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x208 24. "PADCONFIG130_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x208 23. "PADCONFIG130_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x208 22. "PADCONFIG130_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x208 21. "PADCONFIG130_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x208 19.--20. "PADCONFIG130_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x208 18. "PADCONFIG130_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x208 17. "PADCONFIG130_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x208 16. "PADCONFIG130_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x208 15. "PADCONFIG130_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x208 14. "PADCONFIG130_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x208 11.--13. "PADCONFIG130_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x208 8. "PADCONFIG130_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x208 7. "PADCONFIG130_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x208 0.--3. 1. "PADCONFIG130_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x20C "CFG0_PADCONFIG131" bitfld.long 0x20C 31. "PADCONFIG131_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x20C 30. "PADCONFIG131_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x20C 29. "PADCONFIG131_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x20C 28. "PADCONFIG131_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x20C 27. "PADCONFIG131_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x20C 26. "PADCONFIG131_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x20C 25. "PADCONFIG131_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x20C 24. "PADCONFIG131_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x20C 23. "PADCONFIG131_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x20C 22. "PADCONFIG131_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x20C 21. "PADCONFIG131_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x20C 19.--20. "PADCONFIG131_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20C 18. "PADCONFIG131_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x20C 17. "PADCONFIG131_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x20C 16. "PADCONFIG131_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x20C 15. "PADCONFIG131_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x20C 14. "PADCONFIG131_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x20C 11.--13. "PADCONFIG131_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20C 8. "PADCONFIG131_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x20C 7. "PADCONFIG131_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x20C 0.--3. 1. "PADCONFIG131_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x210 "CFG0_PADCONFIG132" bitfld.long 0x210 31. "PADCONFIG132_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x210 30. "PADCONFIG132_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x210 29. "PADCONFIG132_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x210 28. "PADCONFIG132_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x210 27. "PADCONFIG132_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x210 26. "PADCONFIG132_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x210 25. "PADCONFIG132_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x210 24. "PADCONFIG132_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x210 23. "PADCONFIG132_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x210 22. "PADCONFIG132_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x210 21. "PADCONFIG132_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x210 19.--20. "PADCONFIG132_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x210 18. "PADCONFIG132_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x210 17. "PADCONFIG132_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x210 16. "PADCONFIG132_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x210 15. "PADCONFIG132_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x210 14. "PADCONFIG132_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x210 11.--13. "PADCONFIG132_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x210 8. "PADCONFIG132_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x210 7. "PADCONFIG132_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x210 0.--3. 1. "PADCONFIG132_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x214 "CFG0_PADCONFIG133" bitfld.long 0x214 31. "PADCONFIG133_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x214 30. "PADCONFIG133_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x214 29. "PADCONFIG133_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x214 28. "PADCONFIG133_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x214 27. "PADCONFIG133_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x214 26. "PADCONFIG133_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x214 25. "PADCONFIG133_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x214 24. "PADCONFIG133_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x214 23. "PADCONFIG133_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x214 22. "PADCONFIG133_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x214 21. "PADCONFIG133_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x214 19.--20. "PADCONFIG133_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x214 18. "PADCONFIG133_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x214 17. "PADCONFIG133_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x214 16. "PADCONFIG133_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x214 15. "PADCONFIG133_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x214 14. "PADCONFIG133_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x214 11.--13. "PADCONFIG133_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x214 8. "PADCONFIG133_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x214 7. "PADCONFIG133_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x214 0.--3. 1. "PADCONFIG133_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x218 "CFG0_PADCONFIG134" bitfld.long 0x218 31. "PADCONFIG134_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x218 30. "PADCONFIG134_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x218 29. "PADCONFIG134_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x218 28. "PADCONFIG134_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x218 27. "PADCONFIG134_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x218 26. "PADCONFIG134_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x218 25. "PADCONFIG134_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x218 24. "PADCONFIG134_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x218 23. "PADCONFIG134_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x218 22. "PADCONFIG134_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x218 21. "PADCONFIG134_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x218 19.--20. "PADCONFIG134_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x218 18. "PADCONFIG134_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x218 17. "PADCONFIG134_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x218 16. "PADCONFIG134_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x218 15. "PADCONFIG134_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x218 14. "PADCONFIG134_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x218 11.--13. "PADCONFIG134_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x218 8. "PADCONFIG134_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x218 7. "PADCONFIG134_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x218 0.--3. 1. "PADCONFIG134_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x21C "CFG0_PADCONFIG135" bitfld.long 0x21C 31. "PADCONFIG135_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x21C 30. "PADCONFIG135_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x21C 29. "PADCONFIG135_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x21C 28. "PADCONFIG135_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x21C 27. "PADCONFIG135_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x21C 26. "PADCONFIG135_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x21C 25. "PADCONFIG135_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x21C 24. "PADCONFIG135_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x21C 23. "PADCONFIG135_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x21C 22. "PADCONFIG135_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x21C 21. "PADCONFIG135_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x21C 19.--20. "PADCONFIG135_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x21C 18. "PADCONFIG135_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x21C 17. "PADCONFIG135_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x21C 16. "PADCONFIG135_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x21C 15. "PADCONFIG135_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x21C 14. "PADCONFIG135_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x21C 11.--13. "PADCONFIG135_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x21C 8. "PADCONFIG135_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x21C 7. "PADCONFIG135_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x21C 0.--3. 1. "PADCONFIG135_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x220 "CFG0_PADCONFIG136" bitfld.long 0x220 31. "PADCONFIG136_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x220 30. "PADCONFIG136_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x220 29. "PADCONFIG136_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x220 28. "PADCONFIG136_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x220 27. "PADCONFIG136_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x220 26. "PADCONFIG136_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x220 25. "PADCONFIG136_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x220 24. "PADCONFIG136_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x220 23. "PADCONFIG136_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x220 22. "PADCONFIG136_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x220 21. "PADCONFIG136_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x220 19.--20. "PADCONFIG136_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x220 18. "PADCONFIG136_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x220 17. "PADCONFIG136_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x220 16. "PADCONFIG136_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x220 15. "PADCONFIG136_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x220 14. "PADCONFIG136_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x220 11.--13. "PADCONFIG136_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x220 8. "PADCONFIG136_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x220 7. "PADCONFIG136_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x220 0.--3. 1. "PADCONFIG136_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x224 "CFG0_PADCONFIG137" bitfld.long 0x224 31. "PADCONFIG137_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x224 30. "PADCONFIG137_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x224 29. "PADCONFIG137_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x224 28. "PADCONFIG137_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x224 27. "PADCONFIG137_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x224 26. "PADCONFIG137_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x224 25. "PADCONFIG137_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x224 24. "PADCONFIG137_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x224 23. "PADCONFIG137_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x224 22. "PADCONFIG137_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x224 21. "PADCONFIG137_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x224 19.--20. "PADCONFIG137_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x224 18. "PADCONFIG137_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x224 17. "PADCONFIG137_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x224 16. "PADCONFIG137_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x224 15. "PADCONFIG137_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x224 14. "PADCONFIG137_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x224 11.--13. "PADCONFIG137_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x224 8. "PADCONFIG137_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x224 7. "PADCONFIG137_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x224 0.--3. 1. "PADCONFIG137_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x228 "CFG0_PADCONFIG138" bitfld.long 0x228 31. "PADCONFIG138_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x228 30. "PADCONFIG138_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x228 29. "PADCONFIG138_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x228 28. "PADCONFIG138_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x228 27. "PADCONFIG138_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x228 26. "PADCONFIG138_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x228 25. "PADCONFIG138_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x228 24. "PADCONFIG138_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x228 23. "PADCONFIG138_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x228 22. "PADCONFIG138_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x228 21. "PADCONFIG138_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x228 19.--20. "PADCONFIG138_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x228 18. "PADCONFIG138_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x228 17. "PADCONFIG138_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x228 16. "PADCONFIG138_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x228 15. "PADCONFIG138_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x228 14. "PADCONFIG138_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x228 11.--13. "PADCONFIG138_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x228 8. "PADCONFIG138_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x228 7. "PADCONFIG138_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x228 0.--3. 1. "PADCONFIG138_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x22C "CFG0_PADCONFIG139" bitfld.long 0x22C 31. "PADCONFIG139_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x22C 30. "PADCONFIG139_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x22C 29. "PADCONFIG139_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x22C 28. "PADCONFIG139_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x22C 27. "PADCONFIG139_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x22C 26. "PADCONFIG139_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x22C 25. "PADCONFIG139_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x22C 24. "PADCONFIG139_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x22C 23. "PADCONFIG139_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x22C 22. "PADCONFIG139_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x22C 21. "PADCONFIG139_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x22C 19.--20. "PADCONFIG139_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x22C 18. "PADCONFIG139_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x22C 17. "PADCONFIG139_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x22C 16. "PADCONFIG139_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x22C 15. "PADCONFIG139_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x22C 14. "PADCONFIG139_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x22C 11.--13. "PADCONFIG139_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x22C 8. "PADCONFIG139_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x22C 7. "PADCONFIG139_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x22C 0.--3. 1. "PADCONFIG139_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x230 "CFG0_PADCONFIG140" bitfld.long 0x230 31. "PADCONFIG140_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x230 30. "PADCONFIG140_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x230 29. "PADCONFIG140_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x230 28. "PADCONFIG140_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x230 27. "PADCONFIG140_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x230 26. "PADCONFIG140_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x230 25. "PADCONFIG140_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x230 24. "PADCONFIG140_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x230 23. "PADCONFIG140_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x230 22. "PADCONFIG140_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x230 21. "PADCONFIG140_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x230 19.--20. "PADCONFIG140_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x230 18. "PADCONFIG140_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x230 17. "PADCONFIG140_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x230 16. "PADCONFIG140_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x230 15. "PADCONFIG140_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x230 14. "PADCONFIG140_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x230 11.--13. "PADCONFIG140_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x230 8. "PADCONFIG140_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x230 7. "PADCONFIG140_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x230 0.--3. 1. "PADCONFIG140_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x234 "CFG0_PADCONFIG141" bitfld.long 0x234 31. "PADCONFIG141_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x234 30. "PADCONFIG141_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x234 29. "PADCONFIG141_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x234 28. "PADCONFIG141_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x234 27. "PADCONFIG141_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x234 26. "PADCONFIG141_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x234 25. "PADCONFIG141_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x234 24. "PADCONFIG141_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x234 23. "PADCONFIG141_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x234 22. "PADCONFIG141_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x234 21. "PADCONFIG141_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x234 19.--20. "PADCONFIG141_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x234 18. "PADCONFIG141_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x234 17. "PADCONFIG141_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x234 16. "PADCONFIG141_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x234 15. "PADCONFIG141_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x234 14. "PADCONFIG141_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x234 11.--13. "PADCONFIG141_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x234 8. "PADCONFIG141_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x234 7. "PADCONFIG141_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x234 0.--3. 1. "PADCONFIG141_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x238 "CFG0_PADCONFIG142" bitfld.long 0x238 31. "PADCONFIG142_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x238 30. "PADCONFIG142_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x238 29. "PADCONFIG142_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x238 28. "PADCONFIG142_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x238 27. "PADCONFIG142_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x238 26. "PADCONFIG142_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x238 25. "PADCONFIG142_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x238 24. "PADCONFIG142_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x238 23. "PADCONFIG142_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x238 22. "PADCONFIG142_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x238 21. "PADCONFIG142_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x238 19.--20. "PADCONFIG142_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x238 18. "PADCONFIG142_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x238 17. "PADCONFIG142_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x238 16. "PADCONFIG142_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x238 15. "PADCONFIG142_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x238 14. "PADCONFIG142_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x238 11.--13. "PADCONFIG142_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x238 8. "PADCONFIG142_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x238 7. "PADCONFIG142_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x238 0.--3. 1. "PADCONFIG142_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x23C "CFG0_PADCONFIG143" bitfld.long 0x23C 31. "PADCONFIG143_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x23C 30. "PADCONFIG143_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x23C 29. "PADCONFIG143_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x23C 28. "PADCONFIG143_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x23C 27. "PADCONFIG143_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x23C 26. "PADCONFIG143_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x23C 25. "PADCONFIG143_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x23C 24. "PADCONFIG143_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x23C 23. "PADCONFIG143_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x23C 22. "PADCONFIG143_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x23C 21. "PADCONFIG143_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x23C 19.--20. "PADCONFIG143_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x23C 18. "PADCONFIG143_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x23C 17. "PADCONFIG143_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x23C 16. "PADCONFIG143_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x23C 15. "PADCONFIG143_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x23C 14. "PADCONFIG143_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x23C 11.--13. "PADCONFIG143_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x23C 8. "PADCONFIG143_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x23C 7. "PADCONFIG143_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x23C 0.--3. 1. "PADCONFIG143_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x240 "CFG0_PADCONFIG144" bitfld.long 0x240 31. "PADCONFIG144_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x240 30. "PADCONFIG144_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x240 29. "PADCONFIG144_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x240 28. "PADCONFIG144_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x240 27. "PADCONFIG144_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x240 26. "PADCONFIG144_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x240 25. "PADCONFIG144_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x240 24. "PADCONFIG144_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x240 23. "PADCONFIG144_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x240 22. "PADCONFIG144_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x240 21. "PADCONFIG144_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x240 19.--20. "PADCONFIG144_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x240 18. "PADCONFIG144_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x240 17. "PADCONFIG144_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x240 16. "PADCONFIG144_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x240 15. "PADCONFIG144_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x240 14. "PADCONFIG144_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x240 11.--13. "PADCONFIG144_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x240 8. "PADCONFIG144_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x240 7. "PADCONFIG144_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x240 0.--3. 1. "PADCONFIG144_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x244 "CFG0_PADCONFIG145" bitfld.long 0x244 31. "PADCONFIG145_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x244 30. "PADCONFIG145_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x244 29. "PADCONFIG145_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x244 28. "PADCONFIG145_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x244 27. "PADCONFIG145_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x244 26. "PADCONFIG145_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x244 25. "PADCONFIG145_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x244 24. "PADCONFIG145_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x244 23. "PADCONFIG145_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x244 22. "PADCONFIG145_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x244 21. "PADCONFIG145_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x244 19.--20. "PADCONFIG145_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x244 18. "PADCONFIG145_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x244 17. "PADCONFIG145_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x244 16. "PADCONFIG145_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x244 15. "PADCONFIG145_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x244 14. "PADCONFIG145_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x244 11.--13. "PADCONFIG145_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x244 8. "PADCONFIG145_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x244 7. "PADCONFIG145_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x244 0.--3. 1. "PADCONFIG145_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x248 "CFG0_PADCONFIG146" bitfld.long 0x248 31. "PADCONFIG146_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x248 30. "PADCONFIG146_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x248 29. "PADCONFIG146_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x248 28. "PADCONFIG146_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x248 27. "PADCONFIG146_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x248 26. "PADCONFIG146_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x248 25. "PADCONFIG146_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x248 24. "PADCONFIG146_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x248 23. "PADCONFIG146_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x248 22. "PADCONFIG146_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x248 21. "PADCONFIG146_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x248 19.--20. "PADCONFIG146_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x248 18. "PADCONFIG146_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x248 17. "PADCONFIG146_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x248 16. "PADCONFIG146_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x248 15. "PADCONFIG146_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x248 14. "PADCONFIG146_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x248 11.--13. "PADCONFIG146_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x248 8. "PADCONFIG146_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x248 7. "PADCONFIG146_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x248 0.--3. 1. "PADCONFIG146_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x24C "CFG0_PADCONFIG147" bitfld.long 0x24C 31. "PADCONFIG147_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x24C 30. "PADCONFIG147_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x24C 29. "PADCONFIG147_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x24C 28. "PADCONFIG147_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x24C 27. "PADCONFIG147_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x24C 26. "PADCONFIG147_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x24C 25. "PADCONFIG147_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x24C 24. "PADCONFIG147_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x24C 23. "PADCONFIG147_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x24C 22. "PADCONFIG147_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x24C 21. "PADCONFIG147_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x24C 19.--20. "PADCONFIG147_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24C 18. "PADCONFIG147_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x24C 17. "PADCONFIG147_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x24C 16. "PADCONFIG147_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x24C 15. "PADCONFIG147_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x24C 14. "PADCONFIG147_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x24C 11.--13. "PADCONFIG147_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24C 8. "PADCONFIG147_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x24C 7. "PADCONFIG147_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x24C 0.--3. 1. "PADCONFIG147_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x250 "CFG0_PADCONFIG148" bitfld.long 0x250 31. "PADCONFIG148_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x250 30. "PADCONFIG148_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x250 29. "PADCONFIG148_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x250 28. "PADCONFIG148_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x250 27. "PADCONFIG148_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x250 26. "PADCONFIG148_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x250 25. "PADCONFIG148_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x250 24. "PADCONFIG148_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x250 23. "PADCONFIG148_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x250 22. "PADCONFIG148_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x250 21. "PADCONFIG148_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x250 19.--20. "PADCONFIG148_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x250 18. "PADCONFIG148_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x250 17. "PADCONFIG148_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x250 16. "PADCONFIG148_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x250 15. "PADCONFIG148_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x250 14. "PADCONFIG148_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x250 11.--13. "PADCONFIG148_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x250 8. "PADCONFIG148_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x250 7. "PADCONFIG148_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x250 0.--3. 1. "PADCONFIG148_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x254 "CFG0_PADCONFIG149" bitfld.long 0x254 31. "PADCONFIG149_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x254 30. "PADCONFIG149_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x254 29. "PADCONFIG149_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x254 28. "PADCONFIG149_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x254 27. "PADCONFIG149_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x254 26. "PADCONFIG149_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x254 25. "PADCONFIG149_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x254 24. "PADCONFIG149_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x254 23. "PADCONFIG149_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x254 22. "PADCONFIG149_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x254 21. "PADCONFIG149_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x254 19.--20. "PADCONFIG149_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x254 18. "PADCONFIG149_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x254 17. "PADCONFIG149_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x254 16. "PADCONFIG149_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x254 15. "PADCONFIG149_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x254 14. "PADCONFIG149_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x254 11.--13. "PADCONFIG149_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x254 8. "PADCONFIG149_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x254 7. "PADCONFIG149_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x254 0.--3. 1. "PADCONFIG149_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x258 "CFG0_PADCONFIG150" bitfld.long 0x258 31. "PADCONFIG150_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x258 30. "PADCONFIG150_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x258 29. "PADCONFIG150_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x258 28. "PADCONFIG150_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x258 27. "PADCONFIG150_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x258 26. "PADCONFIG150_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x258 25. "PADCONFIG150_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x258 24. "PADCONFIG150_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x258 23. "PADCONFIG150_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x258 22. "PADCONFIG150_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x258 21. "PADCONFIG150_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x258 19.--20. "PADCONFIG150_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x258 18. "PADCONFIG150_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x258 17. "PADCONFIG150_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x258 16. "PADCONFIG150_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x258 15. "PADCONFIG150_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x258 14. "PADCONFIG150_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x258 11.--13. "PADCONFIG150_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x258 8. "PADCONFIG150_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x258 7. "PADCONFIG150_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x258 0.--3. 1. "PADCONFIG150_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." group.long 0x5008++0x7 line.long 0x0 "CFG0_LOCK1_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK1_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1,- KICK1 component" rgroup.long 0x5100++0x13 line.long 0x0 "CFG0_CLAIMREG_P1_R0_READONLY" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0_READONLY,Claim bits for Partition 1" line.long 0x4 "CFG0_CLAIMREG_P1_R1_READONLY" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1_READONLY,Claim bits for Partition 1" line.long 0x8 "CFG0_CLAIMREG_P1_R2_READONLY" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2_READONLY,Claim bits for Partition 1" line.long 0xC "CFG0_CLAIMREG_P1_R3_READONLY" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P1_R3_READONLY,Claim bits for Partition 1" line.long 0x10 "CFG0_CLAIMREG_P1_R4_READONLY" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P1_R4_READONLY,Claim bits for Partition 1" group.long 0x6000++0x25B line.long 0x0 "CFG0_PADCONFIG0_PROXY" bitfld.long 0x0 31. "PADCONFIG0_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x0 30. "PADCONFIG0_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x0 29. "PADCONFIG0_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x0 28. "PADCONFIG0_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x0 27. "PADCONFIG0_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x0 26. "PADCONFIG0_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x0 25. "PADCONFIG0_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x0 24. "PADCONFIG0_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x0 23. "PADCONFIG0_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x0 22. "PADCONFIG0_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x0 21. "PADCONFIG0_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x0 19.--20. "PADCONFIG0_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "PADCONFIG0_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x0 17. "PADCONFIG0_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x0 16. "PADCONFIG0_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x0 15. "PADCONFIG0_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x0 14. "PADCONFIG0_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x0 11.--13. "PADCONFIG0_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "PADCONFIG0_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x0 7. "PADCONFIG0_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG0_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x4 "CFG0_PADCONFIG1_PROXY" bitfld.long 0x4 31. "PADCONFIG1_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x4 30. "PADCONFIG1_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x4 29. "PADCONFIG1_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x4 28. "PADCONFIG1_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x4 27. "PADCONFIG1_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x4 26. "PADCONFIG1_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x4 25. "PADCONFIG1_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x4 24. "PADCONFIG1_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x4 23. "PADCONFIG1_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x4 22. "PADCONFIG1_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x4 21. "PADCONFIG1_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x4 19.--20. "PADCONFIG1_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "PADCONFIG1_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x4 17. "PADCONFIG1_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x4 16. "PADCONFIG1_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x4 15. "PADCONFIG1_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x4 14. "PADCONFIG1_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x4 11.--13. "PADCONFIG1_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "PADCONFIG1_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x4 7. "PADCONFIG1_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG1_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x8 "CFG0_PADCONFIG2_PROXY" bitfld.long 0x8 31. "PADCONFIG2_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x8 30. "PADCONFIG2_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x8 29. "PADCONFIG2_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x8 28. "PADCONFIG2_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x8 27. "PADCONFIG2_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x8 26. "PADCONFIG2_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x8 25. "PADCONFIG2_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x8 24. "PADCONFIG2_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x8 23. "PADCONFIG2_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x8 22. "PADCONFIG2_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x8 21. "PADCONFIG2_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x8 19.--20. "PADCONFIG2_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "PADCONFIG2_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x8 17. "PADCONFIG2_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x8 16. "PADCONFIG2_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x8 15. "PADCONFIG2_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x8 14. "PADCONFIG2_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x8 11.--13. "PADCONFIG2_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "PADCONFIG2_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x8 7. "PADCONFIG2_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG2_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xC "CFG0_PADCONFIG3_PROXY" bitfld.long 0xC 31. "PADCONFIG3_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xC 30. "PADCONFIG3_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xC 29. "PADCONFIG3_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xC 28. "PADCONFIG3_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xC 27. "PADCONFIG3_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xC 26. "PADCONFIG3_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xC 25. "PADCONFIG3_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xC 24. "PADCONFIG3_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xC 23. "PADCONFIG3_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xC 22. "PADCONFIG3_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xC 21. "PADCONFIG3_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xC 19.--20. "PADCONFIG3_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "PADCONFIG3_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xC 17. "PADCONFIG3_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xC 16. "PADCONFIG3_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xC 15. "PADCONFIG3_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xC 14. "PADCONFIG3_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xC 11.--13. "PADCONFIG3_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "PADCONFIG3_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xC 7. "PADCONFIG3_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG3_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x10 "CFG0_PADCONFIG4_PROXY" bitfld.long 0x10 31. "PADCONFIG4_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x10 30. "PADCONFIG4_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x10 29. "PADCONFIG4_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x10 28. "PADCONFIG4_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x10 27. "PADCONFIG4_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x10 26. "PADCONFIG4_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x10 25. "PADCONFIG4_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x10 24. "PADCONFIG4_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x10 23. "PADCONFIG4_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x10 22. "PADCONFIG4_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x10 21. "PADCONFIG4_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x10 15. "PADCONFIG4_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x10 14. "PADCONFIG4_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "PADCONFIG4_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x10 7. "PADCONFIG4_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG4_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x14 "CFG0_PADCONFIG5_PROXY" bitfld.long 0x14 31. "PADCONFIG5_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x14 30. "PADCONFIG5_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x14 29. "PADCONFIG5_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x14 28. "PADCONFIG5_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x14 27. "PADCONFIG5_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x14 26. "PADCONFIG5_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x14 25. "PADCONFIG5_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x14 24. "PADCONFIG5_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x14 23. "PADCONFIG5_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x14 22. "PADCONFIG5_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x14 21. "PADCONFIG5_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x14 15. "PADCONFIG5_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x14 14. "PADCONFIG5_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "PADCONFIG5_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x14 7. "PADCONFIG5_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG5_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x18 "CFG0_PADCONFIG6_PROXY" bitfld.long 0x18 31. "PADCONFIG6_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x18 30. "PADCONFIG6_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x18 29. "PADCONFIG6_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x18 28. "PADCONFIG6_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x18 27. "PADCONFIG6_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x18 26. "PADCONFIG6_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x18 25. "PADCONFIG6_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x18 24. "PADCONFIG6_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x18 23. "PADCONFIG6_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x18 22. "PADCONFIG6_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x18 21. "PADCONFIG6_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x18 15. "PADCONFIG6_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x18 14. "PADCONFIG6_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "PADCONFIG6_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x18 7. "PADCONFIG6_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG6_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x1C "CFG0_PADCONFIG7_PROXY" bitfld.long 0x1C 31. "PADCONFIG7_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1C 30. "PADCONFIG7_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1C 29. "PADCONFIG7_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1C 28. "PADCONFIG7_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1C 27. "PADCONFIG7_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1C 26. "PADCONFIG7_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1C 25. "PADCONFIG7_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1C 24. "PADCONFIG7_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1C 23. "PADCONFIG7_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1C 22. "PADCONFIG7_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1C 15. "PADCONFIG7_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1C 14. "PADCONFIG7_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "PADCONFIG7_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1C 7. "PADCONFIG7_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG7_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x20 "CFG0_PADCONFIG8_PROXY" bitfld.long 0x20 31. "PADCONFIG8_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x20 30. "PADCONFIG8_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x20 29. "PADCONFIG8_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x20 28. "PADCONFIG8_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x20 27. "PADCONFIG8_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x20 26. "PADCONFIG8_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x20 25. "PADCONFIG8_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x20 24. "PADCONFIG8_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x20 23. "PADCONFIG8_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x20 22. "PADCONFIG8_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x20 21. "PADCONFIG8_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x20 15. "PADCONFIG8_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x20 14. "PADCONFIG8_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 8. "PADCONFIG8_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x20 7. "PADCONFIG8_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG8_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x24 "CFG0_PADCONFIG9_PROXY" bitfld.long 0x24 31. "PADCONFIG9_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x24 30. "PADCONFIG9_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x24 29. "PADCONFIG9_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x24 28. "PADCONFIG9_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x24 27. "PADCONFIG9_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x24 26. "PADCONFIG9_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x24 25. "PADCONFIG9_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x24 24. "PADCONFIG9_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x24 23. "PADCONFIG9_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x24 22. "PADCONFIG9_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x24 21. "PADCONFIG9_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x24 15. "PADCONFIG9_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x24 14. "PADCONFIG9_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "PADCONFIG9_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x24 7. "PADCONFIG9_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG9_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x28 "CFG0_PADCONFIG10_PROXY" bitfld.long 0x28 31. "PADCONFIG10_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x28 30. "PADCONFIG10_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x28 29. "PADCONFIG10_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x28 28. "PADCONFIG10_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x28 27. "PADCONFIG10_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x28 26. "PADCONFIG10_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x28 25. "PADCONFIG10_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x28 24. "PADCONFIG10_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x28 23. "PADCONFIG10_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x28 22. "PADCONFIG10_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x28 21. "PADCONFIG10_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x28 15. "PADCONFIG10_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x28 14. "PADCONFIG10_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8. "PADCONFIG10_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x28 7. "PADCONFIG10_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG10_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x2C "CFG0_PADCONFIG11_PROXY" bitfld.long 0x2C 31. "PADCONFIG11_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x2C 30. "PADCONFIG11_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x2C 29. "PADCONFIG11_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x2C 28. "PADCONFIG11_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x2C 27. "PADCONFIG11_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x2C 26. "PADCONFIG11_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x2C 25. "PADCONFIG11_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x2C 24. "PADCONFIG11_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x2C 23. "PADCONFIG11_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x2C 22. "PADCONFIG11_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x2C 15. "PADCONFIG11_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x2C 14. "PADCONFIG11_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 8. "PADCONFIG11_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x2C 7. "PADCONFIG11_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x2C 0.--3. 1. "PADCONFIG11_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x30 "CFG0_PADCONFIG12_PROXY" bitfld.long 0x30 31. "PADCONFIG12_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x30 30. "PADCONFIG12_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x30 29. "PADCONFIG12_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x30 28. "PADCONFIG12_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x30 27. "PADCONFIG12_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x30 26. "PADCONFIG12_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x30 25. "PADCONFIG12_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x30 24. "PADCONFIG12_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x30 23. "PADCONFIG12_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x30 22. "PADCONFIG12_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x30 21. "PADCONFIG12_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x30 15. "PADCONFIG12_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x30 14. "PADCONFIG12_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 8. "PADCONFIG12_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x30 7. "PADCONFIG12_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PADCONFIG12_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x34 "CFG0_PADCONFIG13_PROXY" bitfld.long 0x34 31. "PADCONFIG13_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x34 30. "PADCONFIG13_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x34 29. "PADCONFIG13_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x34 28. "PADCONFIG13_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x34 27. "PADCONFIG13_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x34 26. "PADCONFIG13_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x34 25. "PADCONFIG13_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x34 24. "PADCONFIG13_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x34 23. "PADCONFIG13_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x34 22. "PADCONFIG13_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x34 21. "PADCONFIG13_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x34 15. "PADCONFIG13_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x34 14. "PADCONFIG13_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 8. "PADCONFIG13_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x34 7. "PADCONFIG13_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x34 0.--3. 1. "PADCONFIG13_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x38 "CFG0_PADCONFIG14_PROXY" bitfld.long 0x38 31. "PADCONFIG14_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x38 30. "PADCONFIG14_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x38 29. "PADCONFIG14_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x38 28. "PADCONFIG14_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x38 27. "PADCONFIG14_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x38 26. "PADCONFIG14_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x38 25. "PADCONFIG14_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x38 24. "PADCONFIG14_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x38 23. "PADCONFIG14_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x38 22. "PADCONFIG14_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x38 21. "PADCONFIG14_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x38 15. "PADCONFIG14_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x38 14. "PADCONFIG14_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 8. "PADCONFIG14_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x38 7. "PADCONFIG14_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x38 0.--3. 1. "PADCONFIG14_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x3C "CFG0_PADCONFIG15_PROXY" bitfld.long 0x3C 31. "PADCONFIG15_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x3C 30. "PADCONFIG15_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x3C 29. "PADCONFIG15_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x3C 28. "PADCONFIG15_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x3C 27. "PADCONFIG15_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x3C 26. "PADCONFIG15_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x3C 25. "PADCONFIG15_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x3C 24. "PADCONFIG15_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x3C 23. "PADCONFIG15_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x3C 22. "PADCONFIG15_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x3C 15. "PADCONFIG15_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x3C 14. "PADCONFIG15_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x3C 8. "PADCONFIG15_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x3C 7. "PADCONFIG15_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x3C 0.--3. 1. "PADCONFIG15_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x40 "CFG0_PADCONFIG16_PROXY" bitfld.long 0x40 31. "PADCONFIG16_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x40 30. "PADCONFIG16_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x40 29. "PADCONFIG16_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x40 28. "PADCONFIG16_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x40 27. "PADCONFIG16_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x40 26. "PADCONFIG16_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x40 25. "PADCONFIG16_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x40 24. "PADCONFIG16_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x40 23. "PADCONFIG16_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x40 22. "PADCONFIG16_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x40 21. "PADCONFIG16_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x40 15. "PADCONFIG16_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x40 14. "PADCONFIG16_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 8. "PADCONFIG16_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x40 7. "PADCONFIG16_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "PADCONFIG16_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x44 "CFG0_PADCONFIG17_PROXY" bitfld.long 0x44 31. "PADCONFIG17_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x44 30. "PADCONFIG17_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x44 29. "PADCONFIG17_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x44 28. "PADCONFIG17_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x44 27. "PADCONFIG17_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x44 26. "PADCONFIG17_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x44 25. "PADCONFIG17_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x44 24. "PADCONFIG17_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x44 23. "PADCONFIG17_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x44 22. "PADCONFIG17_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x44 21. "PADCONFIG17_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x44 15. "PADCONFIG17_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x44 14. "PADCONFIG17_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x44 8. "PADCONFIG17_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x44 7. "PADCONFIG17_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x44 0.--3. 1. "PADCONFIG17_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x48 "CFG0_PADCONFIG18_PROXY" bitfld.long 0x48 31. "PADCONFIG18_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x48 30. "PADCONFIG18_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x48 29. "PADCONFIG18_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x48 28. "PADCONFIG18_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x48 27. "PADCONFIG18_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x48 26. "PADCONFIG18_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x48 25. "PADCONFIG18_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x48 24. "PADCONFIG18_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x48 23. "PADCONFIG18_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x48 22. "PADCONFIG18_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x48 21. "PADCONFIG18_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x48 15. "PADCONFIG18_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x48 14. "PADCONFIG18_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 8. "PADCONFIG18_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x48 7. "PADCONFIG18_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x48 0.--3. 1. "PADCONFIG18_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x4C "CFG0_PADCONFIG19_PROXY" bitfld.long 0x4C 31. "PADCONFIG19_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x4C 30. "PADCONFIG19_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x4C 29. "PADCONFIG19_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x4C 28. "PADCONFIG19_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x4C 27. "PADCONFIG19_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x4C 26. "PADCONFIG19_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x4C 25. "PADCONFIG19_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x4C 24. "PADCONFIG19_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x4C 23. "PADCONFIG19_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x4C 22. "PADCONFIG19_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x4C 15. "PADCONFIG19_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x4C 14. "PADCONFIG19_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4C 8. "PADCONFIG19_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x4C 7. "PADCONFIG19_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x4C 0.--3. 1. "PADCONFIG19_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x50 "CFG0_PADCONFIG20_PROXY" bitfld.long 0x50 31. "PADCONFIG20_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x50 30. "PADCONFIG20_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x50 29. "PADCONFIG20_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x50 28. "PADCONFIG20_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x50 27. "PADCONFIG20_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x50 26. "PADCONFIG20_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x50 25. "PADCONFIG20_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x50 24. "PADCONFIG20_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x50 23. "PADCONFIG20_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x50 22. "PADCONFIG20_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x50 21. "PADCONFIG20_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x50 15. "PADCONFIG20_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x50 14. "PADCONFIG20_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 8. "PADCONFIG20_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x50 7. "PADCONFIG20_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x50 0.--3. 1. "PADCONFIG20_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x54 "CFG0_PADCONFIG21_PROXY" bitfld.long 0x54 31. "PADCONFIG21_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x54 30. "PADCONFIG21_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x54 29. "PADCONFIG21_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x54 28. "PADCONFIG21_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x54 27. "PADCONFIG21_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x54 26. "PADCONFIG21_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x54 25. "PADCONFIG21_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x54 24. "PADCONFIG21_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x54 23. "PADCONFIG21_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x54 22. "PADCONFIG21_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x54 21. "PADCONFIG21_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x54 15. "PADCONFIG21_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x54 14. "PADCONFIG21_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x54 8. "PADCONFIG21_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x54 7. "PADCONFIG21_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x54 0.--3. 1. "PADCONFIG21_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x58 "CFG0_PADCONFIG22_PROXY" bitfld.long 0x58 31. "PADCONFIG22_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x58 30. "PADCONFIG22_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x58 29. "PADCONFIG22_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x58 28. "PADCONFIG22_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x58 27. "PADCONFIG22_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x58 26. "PADCONFIG22_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x58 25. "PADCONFIG22_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x58 24. "PADCONFIG22_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x58 23. "PADCONFIG22_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x58 22. "PADCONFIG22_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x58 21. "PADCONFIG22_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x58 15. "PADCONFIG22_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x58 14. "PADCONFIG22_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 8. "PADCONFIG22_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x58 7. "PADCONFIG22_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x58 0.--3. 1. "PADCONFIG22_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x5C "CFG0_PADCONFIG23_PROXY" bitfld.long 0x5C 31. "PADCONFIG23_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x5C 30. "PADCONFIG23_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x5C 29. "PADCONFIG23_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x5C 28. "PADCONFIG23_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x5C 27. "PADCONFIG23_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x5C 26. "PADCONFIG23_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x5C 25. "PADCONFIG23_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x5C 24. "PADCONFIG23_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x5C 23. "PADCONFIG23_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x5C 22. "PADCONFIG23_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x5C 15. "PADCONFIG23_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x5C 14. "PADCONFIG23_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x5C 8. "PADCONFIG23_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x5C 7. "PADCONFIG23_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x5C 0.--3. 1. "PADCONFIG23_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x60 "CFG0_PADCONFIG24_PROXY" bitfld.long 0x60 31. "PADCONFIG24_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x60 30. "PADCONFIG24_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x60 29. "PADCONFIG24_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x60 28. "PADCONFIG24_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x60 27. "PADCONFIG24_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x60 26. "PADCONFIG24_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x60 25. "PADCONFIG24_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x60 24. "PADCONFIG24_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x60 23. "PADCONFIG24_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x60 22. "PADCONFIG24_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x60 21. "PADCONFIG24_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x60 15. "PADCONFIG24_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x60 14. "PADCONFIG24_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 8. "PADCONFIG24_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x60 7. "PADCONFIG24_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "PADCONFIG24_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x64 "CFG0_PADCONFIG25_PROXY" bitfld.long 0x64 31. "PADCONFIG25_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x64 30. "PADCONFIG25_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x64 29. "PADCONFIG25_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x64 28. "PADCONFIG25_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x64 27. "PADCONFIG25_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x64 26. "PADCONFIG25_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x64 25. "PADCONFIG25_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x64 24. "PADCONFIG25_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x64 23. "PADCONFIG25_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x64 22. "PADCONFIG25_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x64 21. "PADCONFIG25_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x64 15. "PADCONFIG25_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x64 14. "PADCONFIG25_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x64 8. "PADCONFIG25_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x64 7. "PADCONFIG25_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x64 0.--3. 1. "PADCONFIG25_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x68 "CFG0_PADCONFIG26_PROXY" bitfld.long 0x68 31. "PADCONFIG26_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x68 30. "PADCONFIG26_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x68 29. "PADCONFIG26_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x68 28. "PADCONFIG26_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x68 27. "PADCONFIG26_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x68 26. "PADCONFIG26_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x68 25. "PADCONFIG26_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x68 24. "PADCONFIG26_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x68 23. "PADCONFIG26_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x68 22. "PADCONFIG26_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x68 21. "PADCONFIG26_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x68 15. "PADCONFIG26_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x68 14. "PADCONFIG26_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 8. "PADCONFIG26_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x68 7. "PADCONFIG26_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x68 0.--3. 1. "PADCONFIG26_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x6C "CFG0_PADCONFIG27_PROXY" bitfld.long 0x6C 31. "PADCONFIG27_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x6C 30. "PADCONFIG27_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x6C 29. "PADCONFIG27_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x6C 28. "PADCONFIG27_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x6C 27. "PADCONFIG27_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x6C 26. "PADCONFIG27_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x6C 25. "PADCONFIG27_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x6C 24. "PADCONFIG27_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x6C 23. "PADCONFIG27_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x6C 22. "PADCONFIG27_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x6C 15. "PADCONFIG27_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x6C 14. "PADCONFIG27_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x6C 8. "PADCONFIG27_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x6C 7. "PADCONFIG27_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x6C 0.--3. 1. "PADCONFIG27_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x70 "CFG0_PADCONFIG28_PROXY" bitfld.long 0x70 31. "PADCONFIG28_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x70 30. "PADCONFIG28_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x70 29. "PADCONFIG28_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x70 28. "PADCONFIG28_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x70 27. "PADCONFIG28_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x70 26. "PADCONFIG28_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x70 25. "PADCONFIG28_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x70 24. "PADCONFIG28_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x70 23. "PADCONFIG28_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x70 22. "PADCONFIG28_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x70 21. "PADCONFIG28_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x70 15. "PADCONFIG28_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x70 14. "PADCONFIG28_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 8. "PADCONFIG28_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x70 7. "PADCONFIG28_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x70 0.--3. 1. "PADCONFIG28_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x74 "CFG0_PADCONFIG29_PROXY" bitfld.long 0x74 31. "PADCONFIG29_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x74 30. "PADCONFIG29_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x74 29. "PADCONFIG29_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x74 28. "PADCONFIG29_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x74 27. "PADCONFIG29_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x74 26. "PADCONFIG29_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x74 25. "PADCONFIG29_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x74 24. "PADCONFIG29_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x74 23. "PADCONFIG29_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x74 22. "PADCONFIG29_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x74 21. "PADCONFIG29_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x74 15. "PADCONFIG29_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x74 14. "PADCONFIG29_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x74 8. "PADCONFIG29_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x74 7. "PADCONFIG29_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x74 0.--3. 1. "PADCONFIG29_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x78 "CFG0_PADCONFIG30_PROXY" bitfld.long 0x78 31. "PADCONFIG30_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x78 30. "PADCONFIG30_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x78 29. "PADCONFIG30_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x78 28. "PADCONFIG30_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x78 27. "PADCONFIG30_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x78 26. "PADCONFIG30_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x78 25. "PADCONFIG30_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x78 24. "PADCONFIG30_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x78 23. "PADCONFIG30_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x78 22. "PADCONFIG30_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x78 21. "PADCONFIG30_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x78 15. "PADCONFIG30_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x78 14. "PADCONFIG30_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 8. "PADCONFIG30_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x78 7. "PADCONFIG30_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x78 0.--3. 1. "PADCONFIG30_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x7C "CFG0_PADCONFIG31_PROXY" bitfld.long 0x7C 31. "PADCONFIG31_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x7C 30. "PADCONFIG31_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x7C 29. "PADCONFIG31_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x7C 28. "PADCONFIG31_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x7C 27. "PADCONFIG31_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x7C 26. "PADCONFIG31_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x7C 25. "PADCONFIG31_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x7C 24. "PADCONFIG31_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x7C 23. "PADCONFIG31_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x7C 22. "PADCONFIG31_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x7C 15. "PADCONFIG31_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x7C 14. "PADCONFIG31_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x7C 8. "PADCONFIG31_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x7C 7. "PADCONFIG31_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x7C 0.--3. 1. "PADCONFIG31_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x80 "CFG0_PADCONFIG32_PROXY" bitfld.long 0x80 31. "PADCONFIG32_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x80 30. "PADCONFIG32_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x80 29. "PADCONFIG32_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x80 28. "PADCONFIG32_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x80 27. "PADCONFIG32_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x80 26. "PADCONFIG32_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x80 25. "PADCONFIG32_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x80 24. "PADCONFIG32_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x80 23. "PADCONFIG32_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x80 22. "PADCONFIG32_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x80 21. "PADCONFIG32_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x80 15. "PADCONFIG32_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x80 14. "PADCONFIG32_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 8. "PADCONFIG32_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x80 7. "PADCONFIG32_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "PADCONFIG32_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x84 "CFG0_PADCONFIG33_PROXY" bitfld.long 0x84 31. "PADCONFIG33_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x84 30. "PADCONFIG33_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x84 29. "PADCONFIG33_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x84 28. "PADCONFIG33_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x84 27. "PADCONFIG33_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x84 26. "PADCONFIG33_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x84 25. "PADCONFIG33_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x84 24. "PADCONFIG33_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x84 23. "PADCONFIG33_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x84 22. "PADCONFIG33_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x84 21. "PADCONFIG33_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x84 19.--20. "PADCONFIG33_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x84 18. "PADCONFIG33_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x84 17. "PADCONFIG33_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x84 16. "PADCONFIG33_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x84 15. "PADCONFIG33_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x84 14. "PADCONFIG33_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x84 11.--13. "PADCONFIG33_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x84 8. "PADCONFIG33_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x84 7. "PADCONFIG33_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x84 0.--3. 1. "PADCONFIG33_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x88 "CFG0_PADCONFIG34_PROXY" bitfld.long 0x88 31. "PADCONFIG34_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x88 30. "PADCONFIG34_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x88 29. "PADCONFIG34_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x88 28. "PADCONFIG34_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x88 27. "PADCONFIG34_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x88 26. "PADCONFIG34_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x88 25. "PADCONFIG34_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x88 24. "PADCONFIG34_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x88 23. "PADCONFIG34_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x88 22. "PADCONFIG34_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x88 21. "PADCONFIG34_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x88 19.--20. "PADCONFIG34_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x88 18. "PADCONFIG34_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x88 17. "PADCONFIG34_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x88 16. "PADCONFIG34_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x88 15. "PADCONFIG34_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x88 14. "PADCONFIG34_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x88 11.--13. "PADCONFIG34_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 8. "PADCONFIG34_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x88 7. "PADCONFIG34_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x88 0.--3. 1. "PADCONFIG34_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x8C "CFG0_PADCONFIG35_PROXY" bitfld.long 0x8C 31. "PADCONFIG35_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x8C 30. "PADCONFIG35_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x8C 29. "PADCONFIG35_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x8C 28. "PADCONFIG35_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x8C 27. "PADCONFIG35_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x8C 26. "PADCONFIG35_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x8C 25. "PADCONFIG35_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x8C 24. "PADCONFIG35_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x8C 23. "PADCONFIG35_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x8C 22. "PADCONFIG35_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x8C 21. "PADCONFIG35_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x8C 19.--20. "PADCONFIG35_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8C 18. "PADCONFIG35_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x8C 17. "PADCONFIG35_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x8C 16. "PADCONFIG35_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x8C 15. "PADCONFIG35_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x8C 14. "PADCONFIG35_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x8C 11.--13. "PADCONFIG35_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8C 8. "PADCONFIG35_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x8C 7. "PADCONFIG35_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x8C 0.--3. 1. "PADCONFIG35_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x90 "CFG0_PADCONFIG36_PROXY" bitfld.long 0x90 31. "PADCONFIG36_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x90 30. "PADCONFIG36_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x90 29. "PADCONFIG36_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x90 28. "PADCONFIG36_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x90 27. "PADCONFIG36_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x90 26. "PADCONFIG36_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x90 25. "PADCONFIG36_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x90 24. "PADCONFIG36_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x90 23. "PADCONFIG36_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x90 22. "PADCONFIG36_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x90 21. "PADCONFIG36_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x90 19.--20. "PADCONFIG36_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x90 18. "PADCONFIG36_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x90 17. "PADCONFIG36_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x90 16. "PADCONFIG36_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x90 15. "PADCONFIG36_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x90 14. "PADCONFIG36_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x90 11.--13. "PADCONFIG36_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x90 8. "PADCONFIG36_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x90 7. "PADCONFIG36_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x90 0.--3. 1. "PADCONFIG36_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x94 "CFG0_PADCONFIG37_PROXY" bitfld.long 0x94 31. "PADCONFIG37_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x94 30. "PADCONFIG37_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x94 29. "PADCONFIG37_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x94 28. "PADCONFIG37_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x94 27. "PADCONFIG37_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x94 26. "PADCONFIG37_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x94 25. "PADCONFIG37_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x94 24. "PADCONFIG37_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x94 23. "PADCONFIG37_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x94 22. "PADCONFIG37_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x94 21. "PADCONFIG37_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x94 19.--20. "PADCONFIG37_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x94 18. "PADCONFIG37_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x94 17. "PADCONFIG37_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x94 16. "PADCONFIG37_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x94 15. "PADCONFIG37_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x94 14. "PADCONFIG37_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x94 11.--13. "PADCONFIG37_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x94 8. "PADCONFIG37_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x94 7. "PADCONFIG37_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x94 0.--3. 1. "PADCONFIG37_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x98 "CFG0_PADCONFIG38_PROXY" bitfld.long 0x98 31. "PADCONFIG38_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x98 30. "PADCONFIG38_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x98 29. "PADCONFIG38_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x98 28. "PADCONFIG38_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x98 27. "PADCONFIG38_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x98 26. "PADCONFIG38_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x98 25. "PADCONFIG38_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x98 24. "PADCONFIG38_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x98 23. "PADCONFIG38_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x98 22. "PADCONFIG38_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x98 21. "PADCONFIG38_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x98 19.--20. "PADCONFIG38_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x98 18. "PADCONFIG38_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x98 17. "PADCONFIG38_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x98 16. "PADCONFIG38_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x98 15. "PADCONFIG38_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x98 14. "PADCONFIG38_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x98 11.--13. "PADCONFIG38_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x98 8. "PADCONFIG38_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x98 7. "PADCONFIG38_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x98 0.--3. 1. "PADCONFIG38_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x9C "CFG0_PADCONFIG39_PROXY" bitfld.long 0x9C 31. "PADCONFIG39_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x9C 30. "PADCONFIG39_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x9C 29. "PADCONFIG39_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x9C 28. "PADCONFIG39_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x9C 27. "PADCONFIG39_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x9C 26. "PADCONFIG39_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x9C 25. "PADCONFIG39_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x9C 24. "PADCONFIG39_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x9C 23. "PADCONFIG39_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x9C 22. "PADCONFIG39_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x9C 21. "PADCONFIG39_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x9C 19.--20. "PADCONFIG39_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x9C 18. "PADCONFIG39_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x9C 17. "PADCONFIG39_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x9C 16. "PADCONFIG39_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x9C 15. "PADCONFIG39_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x9C 14. "PADCONFIG39_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x9C 11.--13. "PADCONFIG39_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x9C 8. "PADCONFIG39_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x9C 7. "PADCONFIG39_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x9C 0.--3. 1. "PADCONFIG39_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xA0 "CFG0_PADCONFIG40_PROXY" bitfld.long 0xA0 31. "PADCONFIG40_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xA0 30. "PADCONFIG40_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xA0 29. "PADCONFIG40_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xA0 28. "PADCONFIG40_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xA0 27. "PADCONFIG40_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xA0 26. "PADCONFIG40_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xA0 25. "PADCONFIG40_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xA0 24. "PADCONFIG40_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xA0 23. "PADCONFIG40_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xA0 22. "PADCONFIG40_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xA0 21. "PADCONFIG40_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xA0 19.--20. "PADCONFIG40_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA0 18. "PADCONFIG40_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xA0 17. "PADCONFIG40_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xA0 16. "PADCONFIG40_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xA0 15. "PADCONFIG40_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xA0 14. "PADCONFIG40_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xA0 11.--13. "PADCONFIG40_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA0 8. "PADCONFIG40_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xA0 7. "PADCONFIG40_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "PADCONFIG40_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xA4 "CFG0_PADCONFIG41_PROXY" bitfld.long 0xA4 31. "PADCONFIG41_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xA4 30. "PADCONFIG41_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xA4 29. "PADCONFIG41_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xA4 28. "PADCONFIG41_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xA4 27. "PADCONFIG41_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xA4 26. "PADCONFIG41_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xA4 25. "PADCONFIG41_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xA4 24. "PADCONFIG41_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xA4 23. "PADCONFIG41_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xA4 22. "PADCONFIG41_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xA4 21. "PADCONFIG41_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xA4 19.--20. "PADCONFIG41_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA4 18. "PADCONFIG41_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xA4 17. "PADCONFIG41_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xA4 16. "PADCONFIG41_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xA4 15. "PADCONFIG41_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xA4 14. "PADCONFIG41_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xA4 11.--13. "PADCONFIG41_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA4 8. "PADCONFIG41_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xA4 7. "PADCONFIG41_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xA4 0.--3. 1. "PADCONFIG41_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xA8 "CFG0_PADCONFIG42_PROXY" bitfld.long 0xA8 31. "PADCONFIG42_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xA8 30. "PADCONFIG42_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xA8 29. "PADCONFIG42_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xA8 28. "PADCONFIG42_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xA8 27. "PADCONFIG42_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xA8 26. "PADCONFIG42_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xA8 25. "PADCONFIG42_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xA8 24. "PADCONFIG42_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xA8 23. "PADCONFIG42_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xA8 22. "PADCONFIG42_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xA8 21. "PADCONFIG42_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xA8 19.--20. "PADCONFIG42_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xA8 18. "PADCONFIG42_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xA8 17. "PADCONFIG42_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xA8 16. "PADCONFIG42_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xA8 15. "PADCONFIG42_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xA8 14. "PADCONFIG42_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xA8 11.--13. "PADCONFIG42_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xA8 8. "PADCONFIG42_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xA8 7. "PADCONFIG42_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xA8 0.--3. 1. "PADCONFIG42_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xAC "CFG0_PADCONFIG43_PROXY" bitfld.long 0xAC 31. "PADCONFIG43_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xAC 30. "PADCONFIG43_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xAC 29. "PADCONFIG43_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xAC 28. "PADCONFIG43_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xAC 27. "PADCONFIG43_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xAC 26. "PADCONFIG43_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xAC 25. "PADCONFIG43_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xAC 24. "PADCONFIG43_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xAC 23. "PADCONFIG43_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xAC 22. "PADCONFIG43_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xAC 21. "PADCONFIG43_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xAC 19.--20. "PADCONFIG43_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xAC 18. "PADCONFIG43_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xAC 17. "PADCONFIG43_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xAC 16. "PADCONFIG43_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xAC 15. "PADCONFIG43_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xAC 14. "PADCONFIG43_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xAC 11.--13. "PADCONFIG43_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xAC 8. "PADCONFIG43_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xAC 7. "PADCONFIG43_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xAC 0.--3. 1. "PADCONFIG43_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xB0 "CFG0_PADCONFIG44_PROXY" bitfld.long 0xB0 31. "PADCONFIG44_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xB0 30. "PADCONFIG44_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xB0 29. "PADCONFIG44_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xB0 28. "PADCONFIG44_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xB0 27. "PADCONFIG44_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xB0 26. "PADCONFIG44_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xB0 25. "PADCONFIG44_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xB0 24. "PADCONFIG44_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xB0 23. "PADCONFIG44_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xB0 22. "PADCONFIG44_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xB0 21. "PADCONFIG44_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xB0 19.--20. "PADCONFIG44_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB0 18. "PADCONFIG44_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xB0 17. "PADCONFIG44_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xB0 16. "PADCONFIG44_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xB0 15. "PADCONFIG44_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xB0 14. "PADCONFIG44_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xB0 11.--13. "PADCONFIG44_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB0 8. "PADCONFIG44_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xB0 7. "PADCONFIG44_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xB0 0.--3. 1. "PADCONFIG44_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xB4 "CFG0_PADCONFIG45_PROXY" bitfld.long 0xB4 31. "PADCONFIG45_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xB4 30. "PADCONFIG45_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xB4 29. "PADCONFIG45_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xB4 28. "PADCONFIG45_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xB4 27. "PADCONFIG45_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xB4 26. "PADCONFIG45_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xB4 25. "PADCONFIG45_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xB4 24. "PADCONFIG45_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xB4 23. "PADCONFIG45_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xB4 22. "PADCONFIG45_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xB4 21. "PADCONFIG45_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xB4 19.--20. "PADCONFIG45_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB4 18. "PADCONFIG45_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xB4 17. "PADCONFIG45_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xB4 16. "PADCONFIG45_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xB4 15. "PADCONFIG45_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xB4 14. "PADCONFIG45_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xB4 11.--13. "PADCONFIG45_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB4 8. "PADCONFIG45_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xB4 7. "PADCONFIG45_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xB4 0.--3. 1. "PADCONFIG45_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xB8 "CFG0_PADCONFIG46_PROXY" bitfld.long 0xB8 31. "PADCONFIG46_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xB8 30. "PADCONFIG46_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xB8 29. "PADCONFIG46_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xB8 28. "PADCONFIG46_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xB8 27. "PADCONFIG46_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xB8 26. "PADCONFIG46_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xB8 25. "PADCONFIG46_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xB8 24. "PADCONFIG46_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xB8 23. "PADCONFIG46_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xB8 22. "PADCONFIG46_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xB8 21. "PADCONFIG46_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xB8 19.--20. "PADCONFIG46_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xB8 18. "PADCONFIG46_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xB8 17. "PADCONFIG46_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xB8 16. "PADCONFIG46_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xB8 15. "PADCONFIG46_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xB8 14. "PADCONFIG46_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xB8 11.--13. "PADCONFIG46_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xB8 8. "PADCONFIG46_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xB8 7. "PADCONFIG46_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xB8 0.--3. 1. "PADCONFIG46_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xBC "CFG0_PADCONFIG47_PROXY" bitfld.long 0xBC 31. "PADCONFIG47_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xBC 30. "PADCONFIG47_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xBC 29. "PADCONFIG47_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xBC 28. "PADCONFIG47_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xBC 27. "PADCONFIG47_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xBC 26. "PADCONFIG47_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xBC 25. "PADCONFIG47_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xBC 24. "PADCONFIG47_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xBC 23. "PADCONFIG47_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xBC 22. "PADCONFIG47_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xBC 21. "PADCONFIG47_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xBC 19.--20. "PADCONFIG47_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xBC 18. "PADCONFIG47_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xBC 17. "PADCONFIG47_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xBC 16. "PADCONFIG47_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xBC 15. "PADCONFIG47_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xBC 14. "PADCONFIG47_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xBC 11.--13. "PADCONFIG47_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xBC 8. "PADCONFIG47_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xBC 7. "PADCONFIG47_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xBC 0.--3. 1. "PADCONFIG47_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xC0 "CFG0_PADCONFIG48_PROXY" bitfld.long 0xC0 31. "PADCONFIG48_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xC0 30. "PADCONFIG48_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xC0 29. "PADCONFIG48_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xC0 28. "PADCONFIG48_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xC0 27. "PADCONFIG48_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xC0 26. "PADCONFIG48_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xC0 25. "PADCONFIG48_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xC0 24. "PADCONFIG48_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xC0 23. "PADCONFIG48_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xC0 22. "PADCONFIG48_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xC0 21. "PADCONFIG48_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xC0 19.--20. "PADCONFIG48_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC0 18. "PADCONFIG48_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xC0 17. "PADCONFIG48_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xC0 16. "PADCONFIG48_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xC0 15. "PADCONFIG48_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xC0 14. "PADCONFIG48_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xC0 11.--13. "PADCONFIG48_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC0 8. "PADCONFIG48_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xC0 7. "PADCONFIG48_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "PADCONFIG48_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xC4 "CFG0_PADCONFIG49_PROXY" bitfld.long 0xC4 31. "PADCONFIG49_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xC4 30. "PADCONFIG49_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xC4 29. "PADCONFIG49_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xC4 28. "PADCONFIG49_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xC4 27. "PADCONFIG49_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xC4 26. "PADCONFIG49_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xC4 25. "PADCONFIG49_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xC4 24. "PADCONFIG49_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xC4 23. "PADCONFIG49_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xC4 22. "PADCONFIG49_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xC4 21. "PADCONFIG49_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xC4 19.--20. "PADCONFIG49_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC4 18. "PADCONFIG49_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xC4 17. "PADCONFIG49_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xC4 16. "PADCONFIG49_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xC4 15. "PADCONFIG49_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xC4 14. "PADCONFIG49_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xC4 11.--13. "PADCONFIG49_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC4 8. "PADCONFIG49_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xC4 7. "PADCONFIG49_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xC4 0.--3. 1. "PADCONFIG49_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xC8 "CFG0_PADCONFIG50_PROXY" bitfld.long 0xC8 31. "PADCONFIG50_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xC8 30. "PADCONFIG50_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xC8 29. "PADCONFIG50_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xC8 28. "PADCONFIG50_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xC8 27. "PADCONFIG50_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xC8 26. "PADCONFIG50_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xC8 25. "PADCONFIG50_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xC8 24. "PADCONFIG50_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xC8 23. "PADCONFIG50_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xC8 22. "PADCONFIG50_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xC8 21. "PADCONFIG50_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xC8 19.--20. "PADCONFIG50_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC8 18. "PADCONFIG50_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xC8 17. "PADCONFIG50_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xC8 16. "PADCONFIG50_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xC8 15. "PADCONFIG50_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xC8 14. "PADCONFIG50_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xC8 11.--13. "PADCONFIG50_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC8 8. "PADCONFIG50_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xC8 7. "PADCONFIG50_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xC8 0.--3. 1. "PADCONFIG50_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xCC "CFG0_PADCONFIG51_PROXY" bitfld.long 0xCC 31. "PADCONFIG51_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xCC 30. "PADCONFIG51_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xCC 29. "PADCONFIG51_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xCC 28. "PADCONFIG51_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xCC 27. "PADCONFIG51_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xCC 26. "PADCONFIG51_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xCC 25. "PADCONFIG51_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xCC 24. "PADCONFIG51_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xCC 23. "PADCONFIG51_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xCC 22. "PADCONFIG51_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xCC 21. "PADCONFIG51_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xCC 19.--20. "PADCONFIG51_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xCC 18. "PADCONFIG51_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xCC 17. "PADCONFIG51_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xCC 16. "PADCONFIG51_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xCC 15. "PADCONFIG51_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xCC 14. "PADCONFIG51_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xCC 11.--13. "PADCONFIG51_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xCC 8. "PADCONFIG51_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xCC 7. "PADCONFIG51_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xCC 0.--3. 1. "PADCONFIG51_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xD0 "CFG0_PADCONFIG52_PROXY" bitfld.long 0xD0 31. "PADCONFIG52_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xD0 30. "PADCONFIG52_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xD0 29. "PADCONFIG52_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xD0 28. "PADCONFIG52_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xD0 27. "PADCONFIG52_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xD0 26. "PADCONFIG52_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xD0 25. "PADCONFIG52_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xD0 24. "PADCONFIG52_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xD0 23. "PADCONFIG52_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xD0 22. "PADCONFIG52_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xD0 21. "PADCONFIG52_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xD0 19.--20. "PADCONFIG52_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xD0 18. "PADCONFIG52_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xD0 17. "PADCONFIG52_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xD0 16. "PADCONFIG52_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xD0 15. "PADCONFIG52_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xD0 14. "PADCONFIG52_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xD0 11.--13. "PADCONFIG52_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD0 8. "PADCONFIG52_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xD0 7. "PADCONFIG52_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xD0 0.--3. 1. "PADCONFIG52_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xD4 "CFG0_PADCONFIG53_PROXY" bitfld.long 0xD4 31. "PADCONFIG53_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xD4 30. "PADCONFIG53_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xD4 29. "PADCONFIG53_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xD4 28. "PADCONFIG53_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xD4 27. "PADCONFIG53_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xD4 26. "PADCONFIG53_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xD4 25. "PADCONFIG53_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xD4 24. "PADCONFIG53_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xD4 23. "PADCONFIG53_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xD4 22. "PADCONFIG53_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xD4 21. "PADCONFIG53_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xD4 19.--20. "PADCONFIG53_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xD4 18. "PADCONFIG53_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xD4 17. "PADCONFIG53_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xD4 16. "PADCONFIG53_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xD4 15. "PADCONFIG53_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xD4 14. "PADCONFIG53_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xD4 11.--13. "PADCONFIG53_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD4 8. "PADCONFIG53_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xD4 7. "PADCONFIG53_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xD4 0.--3. 1. "PADCONFIG53_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xD8 "CFG0_PADCONFIG54_PROXY" bitfld.long 0xD8 31. "PADCONFIG54_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xD8 30. "PADCONFIG54_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xD8 29. "PADCONFIG54_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xD8 28. "PADCONFIG54_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xD8 27. "PADCONFIG54_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xD8 26. "PADCONFIG54_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xD8 25. "PADCONFIG54_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xD8 24. "PADCONFIG54_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xD8 23. "PADCONFIG54_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xD8 22. "PADCONFIG54_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xD8 21. "PADCONFIG54_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xD8 19.--20. "PADCONFIG54_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xD8 18. "PADCONFIG54_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xD8 17. "PADCONFIG54_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xD8 16. "PADCONFIG54_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xD8 15. "PADCONFIG54_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xD8 14. "PADCONFIG54_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xD8 11.--13. "PADCONFIG54_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xD8 8. "PADCONFIG54_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xD8 7. "PADCONFIG54_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xD8 0.--3. 1. "PADCONFIG54_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xDC "CFG0_PADCONFIG55_PROXY" bitfld.long 0xDC 31. "PADCONFIG55_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xDC 30. "PADCONFIG55_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xDC 29. "PADCONFIG55_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xDC 28. "PADCONFIG55_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xDC 27. "PADCONFIG55_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xDC 26. "PADCONFIG55_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xDC 25. "PADCONFIG55_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xDC 24. "PADCONFIG55_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xDC 23. "PADCONFIG55_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xDC 22. "PADCONFIG55_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xDC 21. "PADCONFIG55_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xDC 19.--20. "PADCONFIG55_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xDC 18. "PADCONFIG55_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xDC 17. "PADCONFIG55_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xDC 16. "PADCONFIG55_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xDC 15. "PADCONFIG55_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xDC 14. "PADCONFIG55_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xDC 11.--13. "PADCONFIG55_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xDC 8. "PADCONFIG55_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xDC 7. "PADCONFIG55_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xDC 0.--3. 1. "PADCONFIG55_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xE0 "CFG0_PADCONFIG56_PROXY" bitfld.long 0xE0 31. "PADCONFIG56_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xE0 30. "PADCONFIG56_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xE0 29. "PADCONFIG56_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xE0 28. "PADCONFIG56_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xE0 27. "PADCONFIG56_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xE0 26. "PADCONFIG56_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xE0 25. "PADCONFIG56_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xE0 24. "PADCONFIG56_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xE0 23. "PADCONFIG56_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xE0 22. "PADCONFIG56_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xE0 21. "PADCONFIG56_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xE0 19.--20. "PADCONFIG56_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xE0 18. "PADCONFIG56_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xE0 17. "PADCONFIG56_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xE0 16. "PADCONFIG56_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xE0 15. "PADCONFIG56_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xE0 14. "PADCONFIG56_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xE0 11.--13. "PADCONFIG56_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE0 8. "PADCONFIG56_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xE0 7. "PADCONFIG56_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "PADCONFIG56_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xE4 "CFG0_PADCONFIG57_PROXY" bitfld.long 0xE4 31. "PADCONFIG57_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xE4 30. "PADCONFIG57_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xE4 29. "PADCONFIG57_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xE4 28. "PADCONFIG57_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xE4 27. "PADCONFIG57_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xE4 26. "PADCONFIG57_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xE4 25. "PADCONFIG57_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xE4 24. "PADCONFIG57_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xE4 23. "PADCONFIG57_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xE4 22. "PADCONFIG57_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xE4 21. "PADCONFIG57_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xE4 19.--20. "PADCONFIG57_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xE4 18. "PADCONFIG57_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xE4 17. "PADCONFIG57_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xE4 16. "PADCONFIG57_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xE4 15. "PADCONFIG57_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xE4 14. "PADCONFIG57_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xE4 11.--13. "PADCONFIG57_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE4 8. "PADCONFIG57_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xE4 7. "PADCONFIG57_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xE4 0.--3. 1. "PADCONFIG57_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xE8 "CFG0_PADCONFIG58_PROXY" bitfld.long 0xE8 31. "PADCONFIG58_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xE8 30. "PADCONFIG58_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xE8 29. "PADCONFIG58_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xE8 28. "PADCONFIG58_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xE8 27. "PADCONFIG58_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xE8 26. "PADCONFIG58_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xE8 25. "PADCONFIG58_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xE8 24. "PADCONFIG58_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xE8 23. "PADCONFIG58_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xE8 22. "PADCONFIG58_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xE8 21. "PADCONFIG58_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xE8 19.--20. "PADCONFIG58_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xE8 18. "PADCONFIG58_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xE8 17. "PADCONFIG58_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xE8 16. "PADCONFIG58_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xE8 15. "PADCONFIG58_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xE8 14. "PADCONFIG58_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xE8 11.--13. "PADCONFIG58_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xE8 8. "PADCONFIG58_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xE8 7. "PADCONFIG58_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xE8 0.--3. 1. "PADCONFIG58_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xEC "CFG0_PADCONFIG59_PROXY" bitfld.long 0xEC 31. "PADCONFIG59_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xEC 30. "PADCONFIG59_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xEC 29. "PADCONFIG59_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xEC 28. "PADCONFIG59_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xEC 27. "PADCONFIG59_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xEC 26. "PADCONFIG59_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xEC 25. "PADCONFIG59_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xEC 24. "PADCONFIG59_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xEC 23. "PADCONFIG59_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xEC 22. "PADCONFIG59_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xEC 21. "PADCONFIG59_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xEC 19.--20. "PADCONFIG59_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xEC 18. "PADCONFIG59_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xEC 17. "PADCONFIG59_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xEC 16. "PADCONFIG59_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xEC 15. "PADCONFIG59_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xEC 14. "PADCONFIG59_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xEC 11.--13. "PADCONFIG59_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xEC 8. "PADCONFIG59_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xEC 7. "PADCONFIG59_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xEC 0.--3. 1. "PADCONFIG59_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xF0 "CFG0_PADCONFIG60_PROXY" bitfld.long 0xF0 31. "PADCONFIG60_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xF0 30. "PADCONFIG60_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xF0 29. "PADCONFIG60_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xF0 28. "PADCONFIG60_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xF0 27. "PADCONFIG60_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xF0 26. "PADCONFIG60_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xF0 25. "PADCONFIG60_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xF0 24. "PADCONFIG60_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xF0 23. "PADCONFIG60_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xF0 22. "PADCONFIG60_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xF0 21. "PADCONFIG60_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xF0 19.--20. "PADCONFIG60_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xF0 18. "PADCONFIG60_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xF0 17. "PADCONFIG60_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xF0 16. "PADCONFIG60_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xF0 15. "PADCONFIG60_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xF0 14. "PADCONFIG60_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xF0 11.--13. "PADCONFIG60_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF0 8. "PADCONFIG60_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xF0 7. "PADCONFIG60_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xF0 0.--3. 1. "PADCONFIG60_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xF4 "CFG0_PADCONFIG61_PROXY" bitfld.long 0xF4 31. "PADCONFIG61_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xF4 30. "PADCONFIG61_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xF4 29. "PADCONFIG61_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xF4 28. "PADCONFIG61_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xF4 27. "PADCONFIG61_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xF4 26. "PADCONFIG61_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xF4 25. "PADCONFIG61_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xF4 24. "PADCONFIG61_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xF4 23. "PADCONFIG61_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xF4 22. "PADCONFIG61_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xF4 21. "PADCONFIG61_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xF4 19.--20. "PADCONFIG61_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xF4 18. "PADCONFIG61_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xF4 17. "PADCONFIG61_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xF4 16. "PADCONFIG61_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xF4 15. "PADCONFIG61_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xF4 14. "PADCONFIG61_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xF4 11.--13. "PADCONFIG61_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF4 8. "PADCONFIG61_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xF4 7. "PADCONFIG61_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xF4 0.--3. 1. "PADCONFIG61_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xF8 "CFG0_PADCONFIG62_PROXY" bitfld.long 0xF8 31. "PADCONFIG62_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xF8 30. "PADCONFIG62_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xF8 29. "PADCONFIG62_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xF8 28. "PADCONFIG62_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xF8 27. "PADCONFIG62_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xF8 26. "PADCONFIG62_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xF8 25. "PADCONFIG62_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xF8 24. "PADCONFIG62_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xF8 23. "PADCONFIG62_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xF8 22. "PADCONFIG62_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xF8 21. "PADCONFIG62_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xF8 19.--20. "PADCONFIG62_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xF8 18. "PADCONFIG62_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xF8 17. "PADCONFIG62_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xF8 16. "PADCONFIG62_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xF8 15. "PADCONFIG62_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xF8 14. "PADCONFIG62_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xF8 11.--13. "PADCONFIG62_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xF8 8. "PADCONFIG62_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xF8 7. "PADCONFIG62_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xF8 0.--3. 1. "PADCONFIG62_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xFC "CFG0_PADCONFIG63_PROXY" bitfld.long 0xFC 31. "PADCONFIG63_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xFC 30. "PADCONFIG63_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xFC 29. "PADCONFIG63_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xFC 28. "PADCONFIG63_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xFC 27. "PADCONFIG63_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xFC 26. "PADCONFIG63_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xFC 25. "PADCONFIG63_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xFC 24. "PADCONFIG63_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xFC 23. "PADCONFIG63_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xFC 22. "PADCONFIG63_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xFC 21. "PADCONFIG63_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xFC 19.--20. "PADCONFIG63_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xFC 18. "PADCONFIG63_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xFC 17. "PADCONFIG63_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xFC 16. "PADCONFIG63_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xFC 15. "PADCONFIG63_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xFC 14. "PADCONFIG63_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xFC 11.--13. "PADCONFIG63_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xFC 8. "PADCONFIG63_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xFC 7. "PADCONFIG63_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xFC 0.--3. 1. "PADCONFIG63_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x100 "CFG0_PADCONFIG64_PROXY" bitfld.long 0x100 31. "PADCONFIG64_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x100 30. "PADCONFIG64_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x100 29. "PADCONFIG64_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x100 28. "PADCONFIG64_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x100 27. "PADCONFIG64_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x100 26. "PADCONFIG64_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x100 25. "PADCONFIG64_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x100 24. "PADCONFIG64_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x100 23. "PADCONFIG64_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x100 22. "PADCONFIG64_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x100 21. "PADCONFIG64_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x100 19.--20. "PADCONFIG64_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x100 18. "PADCONFIG64_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x100 17. "PADCONFIG64_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x100 16. "PADCONFIG64_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x100 15. "PADCONFIG64_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x100 14. "PADCONFIG64_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x100 11.--13. "PADCONFIG64_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x100 8. "PADCONFIG64_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x100 7. "PADCONFIG64_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x100 0.--3. 1. "PADCONFIG64_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x104 "CFG0_PADCONFIG65_PROXY" bitfld.long 0x104 31. "PADCONFIG65_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x104 30. "PADCONFIG65_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x104 29. "PADCONFIG65_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x104 28. "PADCONFIG65_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x104 27. "PADCONFIG65_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x104 26. "PADCONFIG65_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x104 25. "PADCONFIG65_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x104 24. "PADCONFIG65_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x104 23. "PADCONFIG65_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x104 22. "PADCONFIG65_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x104 21. "PADCONFIG65_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x104 19.--20. "PADCONFIG65_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x104 18. "PADCONFIG65_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x104 17. "PADCONFIG65_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x104 16. "PADCONFIG65_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x104 15. "PADCONFIG65_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x104 14. "PADCONFIG65_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x104 11.--13. "PADCONFIG65_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x104 8. "PADCONFIG65_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x104 7. "PADCONFIG65_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x104 0.--3. 1. "PADCONFIG65_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x108 "CFG0_PADCONFIG66_PROXY" bitfld.long 0x108 31. "PADCONFIG66_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x108 30. "PADCONFIG66_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x108 29. "PADCONFIG66_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x108 28. "PADCONFIG66_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x108 27. "PADCONFIG66_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x108 26. "PADCONFIG66_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x108 25. "PADCONFIG66_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x108 24. "PADCONFIG66_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x108 23. "PADCONFIG66_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x108 22. "PADCONFIG66_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x108 21. "PADCONFIG66_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x108 19.--20. "PADCONFIG66_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x108 18. "PADCONFIG66_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x108 17. "PADCONFIG66_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x108 16. "PADCONFIG66_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x108 15. "PADCONFIG66_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x108 14. "PADCONFIG66_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x108 11.--13. "PADCONFIG66_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x108 8. "PADCONFIG66_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x108 7. "PADCONFIG66_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x108 0.--3. 1. "PADCONFIG66_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x10C "CFG0_PADCONFIG67_PROXY" bitfld.long 0x10C 31. "PADCONFIG67_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x10C 30. "PADCONFIG67_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x10C 29. "PADCONFIG67_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x10C 28. "PADCONFIG67_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x10C 27. "PADCONFIG67_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x10C 26. "PADCONFIG67_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x10C 25. "PADCONFIG67_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x10C 24. "PADCONFIG67_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x10C 23. "PADCONFIG67_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x10C 22. "PADCONFIG67_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x10C 21. "PADCONFIG67_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x10C 19.--20. "PADCONFIG67_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10C 18. "PADCONFIG67_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x10C 17. "PADCONFIG67_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x10C 16. "PADCONFIG67_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x10C 15. "PADCONFIG67_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x10C 14. "PADCONFIG67_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x10C 11.--13. "PADCONFIG67_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10C 8. "PADCONFIG67_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x10C 7. "PADCONFIG67_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x10C 0.--3. 1. "PADCONFIG67_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x110 "CFG0_PADCONFIG68_PROXY" bitfld.long 0x110 31. "PADCONFIG68_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x110 30. "PADCONFIG68_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x110 29. "PADCONFIG68_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x110 28. "PADCONFIG68_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x110 27. "PADCONFIG68_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x110 26. "PADCONFIG68_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x110 25. "PADCONFIG68_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x110 24. "PADCONFIG68_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x110 23. "PADCONFIG68_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x110 22. "PADCONFIG68_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x110 21. "PADCONFIG68_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x110 19.--20. "PADCONFIG68_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x110 18. "PADCONFIG68_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x110 17. "PADCONFIG68_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x110 16. "PADCONFIG68_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x110 15. "PADCONFIG68_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x110 14. "PADCONFIG68_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x110 11.--13. "PADCONFIG68_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x110 8. "PADCONFIG68_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x110 7. "PADCONFIG68_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x110 0.--3. 1. "PADCONFIG68_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x114 "CFG0_PADCONFIG69_PROXY" bitfld.long 0x114 31. "PADCONFIG69_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x114 30. "PADCONFIG69_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x114 29. "PADCONFIG69_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x114 28. "PADCONFIG69_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x114 27. "PADCONFIG69_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x114 26. "PADCONFIG69_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x114 25. "PADCONFIG69_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x114 24. "PADCONFIG69_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x114 23. "PADCONFIG69_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x114 22. "PADCONFIG69_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x114 21. "PADCONFIG69_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x114 19.--20. "PADCONFIG69_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x114 18. "PADCONFIG69_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x114 17. "PADCONFIG69_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x114 16. "PADCONFIG69_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x114 15. "PADCONFIG69_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x114 14. "PADCONFIG69_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x114 11.--13. "PADCONFIG69_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x114 8. "PADCONFIG69_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x114 7. "PADCONFIG69_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x114 0.--3. 1. "PADCONFIG69_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x118 "CFG0_PADCONFIG70_PROXY" bitfld.long 0x118 31. "PADCONFIG70_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x118 30. "PADCONFIG70_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x118 29. "PADCONFIG70_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x118 28. "PADCONFIG70_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x118 27. "PADCONFIG70_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x118 26. "PADCONFIG70_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x118 25. "PADCONFIG70_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x118 24. "PADCONFIG70_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x118 23. "PADCONFIG70_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x118 22. "PADCONFIG70_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x118 21. "PADCONFIG70_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x118 19.--20. "PADCONFIG70_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x118 18. "PADCONFIG70_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x118 17. "PADCONFIG70_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x118 16. "PADCONFIG70_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x118 15. "PADCONFIG70_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x118 14. "PADCONFIG70_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x118 11.--13. "PADCONFIG70_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x118 8. "PADCONFIG70_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x118 7. "PADCONFIG70_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x118 0.--3. 1. "PADCONFIG70_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x11C "CFG0_PADCONFIG71_PROXY" bitfld.long 0x11C 31. "PADCONFIG71_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x11C 30. "PADCONFIG71_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x11C 29. "PADCONFIG71_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x11C 28. "PADCONFIG71_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x11C 27. "PADCONFIG71_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x11C 26. "PADCONFIG71_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x11C 25. "PADCONFIG71_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x11C 24. "PADCONFIG71_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x11C 23. "PADCONFIG71_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x11C 22. "PADCONFIG71_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x11C 21. "PADCONFIG71_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x11C 19.--20. "PADCONFIG71_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x11C 18. "PADCONFIG71_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x11C 17. "PADCONFIG71_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x11C 16. "PADCONFIG71_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x11C 15. "PADCONFIG71_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x11C 14. "PADCONFIG71_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x11C 11.--13. "PADCONFIG71_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x11C 8. "PADCONFIG71_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x11C 7. "PADCONFIG71_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x11C 0.--3. 1. "PADCONFIG71_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x120 "CFG0_PADCONFIG72_PROXY" bitfld.long 0x120 31. "PADCONFIG72_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x120 30. "PADCONFIG72_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x120 29. "PADCONFIG72_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x120 28. "PADCONFIG72_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x120 27. "PADCONFIG72_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x120 26. "PADCONFIG72_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x120 25. "PADCONFIG72_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x120 24. "PADCONFIG72_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x120 23. "PADCONFIG72_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x120 22. "PADCONFIG72_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x120 21. "PADCONFIG72_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x120 19.--20. "PADCONFIG72_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x120 18. "PADCONFIG72_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x120 17. "PADCONFIG72_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x120 16. "PADCONFIG72_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x120 15. "PADCONFIG72_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x120 14. "PADCONFIG72_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x120 11.--13. "PADCONFIG72_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x120 8. "PADCONFIG72_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x120 7. "PADCONFIG72_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x120 0.--3. 1. "PADCONFIG72_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x124 "CFG0_PADCONFIG73_PROXY" bitfld.long 0x124 31. "PADCONFIG73_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x124 30. "PADCONFIG73_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x124 29. "PADCONFIG73_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x124 28. "PADCONFIG73_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x124 27. "PADCONFIG73_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x124 26. "PADCONFIG73_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x124 25. "PADCONFIG73_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x124 24. "PADCONFIG73_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x124 23. "PADCONFIG73_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x124 22. "PADCONFIG73_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x124 21. "PADCONFIG73_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x124 19.--20. "PADCONFIG73_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x124 18. "PADCONFIG73_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x124 17. "PADCONFIG73_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x124 16. "PADCONFIG73_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x124 15. "PADCONFIG73_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x124 14. "PADCONFIG73_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x124 11.--13. "PADCONFIG73_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x124 8. "PADCONFIG73_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x124 7. "PADCONFIG73_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x124 0.--3. 1. "PADCONFIG73_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x128 "CFG0_PADCONFIG74_PROXY" bitfld.long 0x128 31. "PADCONFIG74_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x128 30. "PADCONFIG74_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x128 29. "PADCONFIG74_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x128 28. "PADCONFIG74_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x128 27. "PADCONFIG74_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x128 26. "PADCONFIG74_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x128 25. "PADCONFIG74_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x128 24. "PADCONFIG74_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x128 23. "PADCONFIG74_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x128 22. "PADCONFIG74_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x128 21. "PADCONFIG74_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x128 19.--20. "PADCONFIG74_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x128 18. "PADCONFIG74_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x128 17. "PADCONFIG74_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x128 16. "PADCONFIG74_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x128 15. "PADCONFIG74_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x128 14. "PADCONFIG74_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x128 11.--13. "PADCONFIG74_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x128 8. "PADCONFIG74_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x128 7. "PADCONFIG74_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x128 0.--3. 1. "PADCONFIG74_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x12C "CFG0_PADCONFIG75_PROXY" bitfld.long 0x12C 31. "PADCONFIG75_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x12C 30. "PADCONFIG75_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x12C 29. "PADCONFIG75_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x12C 28. "PADCONFIG75_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x12C 27. "PADCONFIG75_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x12C 26. "PADCONFIG75_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x12C 25. "PADCONFIG75_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x12C 24. "PADCONFIG75_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x12C 23. "PADCONFIG75_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x12C 22. "PADCONFIG75_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x12C 21. "PADCONFIG75_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x12C 19.--20. "PADCONFIG75_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x12C 18. "PADCONFIG75_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x12C 17. "PADCONFIG75_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x12C 16. "PADCONFIG75_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x12C 15. "PADCONFIG75_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x12C 14. "PADCONFIG75_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x12C 11.--13. "PADCONFIG75_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x12C 8. "PADCONFIG75_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x12C 7. "PADCONFIG75_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x12C 0.--3. 1. "PADCONFIG75_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x130 "CFG0_PADCONFIG76_PROXY" bitfld.long 0x130 31. "PADCONFIG76_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x130 30. "PADCONFIG76_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x130 29. "PADCONFIG76_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x130 28. "PADCONFIG76_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x130 27. "PADCONFIG76_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x130 26. "PADCONFIG76_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x130 25. "PADCONFIG76_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x130 24. "PADCONFIG76_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x130 23. "PADCONFIG76_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x130 22. "PADCONFIG76_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x130 21. "PADCONFIG76_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x130 19.--20. "PADCONFIG76_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x130 18. "PADCONFIG76_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x130 17. "PADCONFIG76_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x130 16. "PADCONFIG76_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x130 15. "PADCONFIG76_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x130 14. "PADCONFIG76_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x130 11.--13. "PADCONFIG76_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x130 8. "PADCONFIG76_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x130 7. "PADCONFIG76_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x130 0.--3. 1. "PADCONFIG76_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x134 "CFG0_PADCONFIG77_PROXY" bitfld.long 0x134 31. "PADCONFIG77_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x134 30. "PADCONFIG77_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x134 29. "PADCONFIG77_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x134 28. "PADCONFIG77_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x134 27. "PADCONFIG77_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x134 26. "PADCONFIG77_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x134 25. "PADCONFIG77_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x134 24. "PADCONFIG77_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x134 23. "PADCONFIG77_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x134 22. "PADCONFIG77_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x134 21. "PADCONFIG77_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x134 19.--20. "PADCONFIG77_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x134 18. "PADCONFIG77_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x134 17. "PADCONFIG77_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x134 16. "PADCONFIG77_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x134 15. "PADCONFIG77_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x134 14. "PADCONFIG77_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x134 11.--13. "PADCONFIG77_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x134 8. "PADCONFIG77_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x134 7. "PADCONFIG77_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x134 0.--3. 1. "PADCONFIG77_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x138 "CFG0_PADCONFIG78_PROXY" bitfld.long 0x138 31. "PADCONFIG78_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x138 30. "PADCONFIG78_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x138 29. "PADCONFIG78_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x138 28. "PADCONFIG78_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x138 27. "PADCONFIG78_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x138 26. "PADCONFIG78_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x138 25. "PADCONFIG78_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x138 24. "PADCONFIG78_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x138 23. "PADCONFIG78_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x138 22. "PADCONFIG78_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x138 21. "PADCONFIG78_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x138 19.--20. "PADCONFIG78_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x138 18. "PADCONFIG78_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x138 17. "PADCONFIG78_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x138 16. "PADCONFIG78_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x138 15. "PADCONFIG78_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x138 14. "PADCONFIG78_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x138 11.--13. "PADCONFIG78_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x138 8. "PADCONFIG78_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x138 7. "PADCONFIG78_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x138 0.--3. 1. "PADCONFIG78_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x13C "CFG0_PADCONFIG79_PROXY" bitfld.long 0x13C 31. "PADCONFIG79_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x13C 30. "PADCONFIG79_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x13C 29. "PADCONFIG79_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x13C 28. "PADCONFIG79_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x13C 27. "PADCONFIG79_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x13C 26. "PADCONFIG79_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x13C 25. "PADCONFIG79_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x13C 24. "PADCONFIG79_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x13C 23. "PADCONFIG79_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x13C 22. "PADCONFIG79_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x13C 21. "PADCONFIG79_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x13C 19.--20. "PADCONFIG79_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x13C 18. "PADCONFIG79_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x13C 17. "PADCONFIG79_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x13C 16. "PADCONFIG79_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x13C 15. "PADCONFIG79_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x13C 14. "PADCONFIG79_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x13C 11.--13. "PADCONFIG79_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x13C 8. "PADCONFIG79_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x13C 7. "PADCONFIG79_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x13C 0.--3. 1. "PADCONFIG79_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x140 "CFG0_PADCONFIG80_PROXY" bitfld.long 0x140 31. "PADCONFIG80_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x140 30. "PADCONFIG80_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x140 29. "PADCONFIG80_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x140 28. "PADCONFIG80_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x140 27. "PADCONFIG80_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x140 26. "PADCONFIG80_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x140 25. "PADCONFIG80_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x140 24. "PADCONFIG80_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x140 23. "PADCONFIG80_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x140 22. "PADCONFIG80_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x140 21. "PADCONFIG80_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x140 19.--20. "PADCONFIG80_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x140 18. "PADCONFIG80_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x140 17. "PADCONFIG80_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x140 16. "PADCONFIG80_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x140 15. "PADCONFIG80_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x140 14. "PADCONFIG80_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x140 11.--13. "PADCONFIG80_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x140 8. "PADCONFIG80_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x140 7. "PADCONFIG80_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x140 0.--3. 1. "PADCONFIG80_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x144 "CFG0_PADCONFIG81_PROXY" bitfld.long 0x144 31. "PADCONFIG81_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x144 30. "PADCONFIG81_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x144 29. "PADCONFIG81_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x144 28. "PADCONFIG81_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x144 27. "PADCONFIG81_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x144 26. "PADCONFIG81_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x144 25. "PADCONFIG81_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x144 24. "PADCONFIG81_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x144 23. "PADCONFIG81_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x144 22. "PADCONFIG81_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x144 21. "PADCONFIG81_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x144 19.--20. "PADCONFIG81_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x144 18. "PADCONFIG81_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x144 17. "PADCONFIG81_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x144 16. "PADCONFIG81_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x144 15. "PADCONFIG81_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x144 14. "PADCONFIG81_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x144 11.--13. "PADCONFIG81_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x144 8. "PADCONFIG81_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x144 7. "PADCONFIG81_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x144 0.--3. 1. "PADCONFIG81_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x148 "CFG0_PADCONFIG82_PROXY" bitfld.long 0x148 31. "PADCONFIG82_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x148 30. "PADCONFIG82_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x148 29. "PADCONFIG82_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x148 28. "PADCONFIG82_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x148 27. "PADCONFIG82_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x148 26. "PADCONFIG82_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x148 25. "PADCONFIG82_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x148 24. "PADCONFIG82_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x148 23. "PADCONFIG82_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x148 22. "PADCONFIG82_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x148 21. "PADCONFIG82_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x148 19.--20. "PADCONFIG82_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x148 18. "PADCONFIG82_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x148 17. "PADCONFIG82_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x148 16. "PADCONFIG82_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x148 15. "PADCONFIG82_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x148 14. "PADCONFIG82_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x148 11.--13. "PADCONFIG82_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x148 8. "PADCONFIG82_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x148 7. "PADCONFIG82_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x148 0.--3. 1. "PADCONFIG82_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x14C "CFG0_PADCONFIG83_PROXY" bitfld.long 0x14C 31. "PADCONFIG83_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x14C 30. "PADCONFIG83_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x14C 29. "PADCONFIG83_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x14C 28. "PADCONFIG83_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x14C 27. "PADCONFIG83_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x14C 26. "PADCONFIG83_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x14C 25. "PADCONFIG83_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x14C 24. "PADCONFIG83_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x14C 23. "PADCONFIG83_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x14C 22. "PADCONFIG83_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x14C 21. "PADCONFIG83_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x14C 19.--20. "PADCONFIG83_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14C 18. "PADCONFIG83_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x14C 17. "PADCONFIG83_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x14C 16. "PADCONFIG83_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x14C 15. "PADCONFIG83_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x14C 14. "PADCONFIG83_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x14C 11.--13. "PADCONFIG83_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14C 8. "PADCONFIG83_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x14C 7. "PADCONFIG83_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x14C 0.--3. 1. "PADCONFIG83_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x150 "CFG0_PADCONFIG84_PROXY" bitfld.long 0x150 31. "PADCONFIG84_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x150 30. "PADCONFIG84_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x150 29. "PADCONFIG84_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x150 28. "PADCONFIG84_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x150 27. "PADCONFIG84_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x150 26. "PADCONFIG84_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x150 25. "PADCONFIG84_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x150 24. "PADCONFIG84_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x150 23. "PADCONFIG84_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x150 22. "PADCONFIG84_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x150 21. "PADCONFIG84_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x150 19.--20. "PADCONFIG84_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x150 18. "PADCONFIG84_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x150 17. "PADCONFIG84_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x150 16. "PADCONFIG84_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x150 15. "PADCONFIG84_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x150 14. "PADCONFIG84_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x150 11.--13. "PADCONFIG84_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x150 8. "PADCONFIG84_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x150 7. "PADCONFIG84_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x150 0.--3. 1. "PADCONFIG84_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x154 "CFG0_PADCONFIG85_PROXY" bitfld.long 0x154 31. "PADCONFIG85_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x154 30. "PADCONFIG85_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x154 29. "PADCONFIG85_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x154 28. "PADCONFIG85_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x154 27. "PADCONFIG85_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x154 26. "PADCONFIG85_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x154 25. "PADCONFIG85_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x154 24. "PADCONFIG85_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x154 23. "PADCONFIG85_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x154 22. "PADCONFIG85_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x154 21. "PADCONFIG85_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x154 19.--20. "PADCONFIG85_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x154 18. "PADCONFIG85_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x154 17. "PADCONFIG85_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x154 16. "PADCONFIG85_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x154 15. "PADCONFIG85_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x154 14. "PADCONFIG85_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x154 11.--13. "PADCONFIG85_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x154 8. "PADCONFIG85_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x154 7. "PADCONFIG85_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x154 0.--3. 1. "PADCONFIG85_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x158 "CFG0_PADCONFIG86_PROXY" bitfld.long 0x158 31. "PADCONFIG86_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x158 30. "PADCONFIG86_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x158 29. "PADCONFIG86_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x158 28. "PADCONFIG86_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x158 27. "PADCONFIG86_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x158 26. "PADCONFIG86_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x158 25. "PADCONFIG86_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x158 24. "PADCONFIG86_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x158 23. "PADCONFIG86_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x158 22. "PADCONFIG86_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x158 21. "PADCONFIG86_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x158 19.--20. "PADCONFIG86_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x158 18. "PADCONFIG86_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x158 17. "PADCONFIG86_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x158 16. "PADCONFIG86_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x158 15. "PADCONFIG86_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x158 14. "PADCONFIG86_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x158 11.--13. "PADCONFIG86_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x158 8. "PADCONFIG86_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x158 7. "PADCONFIG86_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x158 0.--3. 1. "PADCONFIG86_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x15C "CFG0_PADCONFIG87_PROXY" bitfld.long 0x15C 31. "PADCONFIG87_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x15C 30. "PADCONFIG87_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x15C 29. "PADCONFIG87_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x15C 28. "PADCONFIG87_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x15C 27. "PADCONFIG87_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x15C 26. "PADCONFIG87_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x15C 25. "PADCONFIG87_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x15C 24. "PADCONFIG87_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x15C 23. "PADCONFIG87_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x15C 22. "PADCONFIG87_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x15C 21. "PADCONFIG87_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x15C 19.--20. "PADCONFIG87_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x15C 18. "PADCONFIG87_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x15C 17. "PADCONFIG87_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x15C 16. "PADCONFIG87_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x15C 15. "PADCONFIG87_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x15C 14. "PADCONFIG87_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x15C 11.--13. "PADCONFIG87_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x15C 8. "PADCONFIG87_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x15C 7. "PADCONFIG87_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x15C 0.--3. 1. "PADCONFIG87_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x160 "CFG0_PADCONFIG88_PROXY" bitfld.long 0x160 31. "PADCONFIG88_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x160 30. "PADCONFIG88_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x160 29. "PADCONFIG88_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x160 28. "PADCONFIG88_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x160 27. "PADCONFIG88_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x160 26. "PADCONFIG88_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x160 25. "PADCONFIG88_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x160 24. "PADCONFIG88_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x160 23. "PADCONFIG88_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x160 22. "PADCONFIG88_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x160 21. "PADCONFIG88_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x160 19.--20. "PADCONFIG88_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x160 18. "PADCONFIG88_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x160 17. "PADCONFIG88_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x160 16. "PADCONFIG88_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x160 15. "PADCONFIG88_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x160 14. "PADCONFIG88_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x160 11.--13. "PADCONFIG88_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x160 8. "PADCONFIG88_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x160 7. "PADCONFIG88_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x160 0.--3. 1. "PADCONFIG88_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x164 "CFG0_PADCONFIG89_PROXY" bitfld.long 0x164 31. "PADCONFIG89_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x164 30. "PADCONFIG89_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x164 29. "PADCONFIG89_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x164 28. "PADCONFIG89_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x164 27. "PADCONFIG89_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x164 26. "PADCONFIG89_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x164 25. "PADCONFIG89_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x164 24. "PADCONFIG89_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x164 23. "PADCONFIG89_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x164 22. "PADCONFIG89_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x164 21. "PADCONFIG89_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x164 19.--20. "PADCONFIG89_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x164 18. "PADCONFIG89_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x164 17. "PADCONFIG89_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x164 16. "PADCONFIG89_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x164 15. "PADCONFIG89_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x164 14. "PADCONFIG89_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x164 11.--13. "PADCONFIG89_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x164 8. "PADCONFIG89_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x164 7. "PADCONFIG89_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x164 0.--3. 1. "PADCONFIG89_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x168 "CFG0_PADCONFIG90_PROXY" bitfld.long 0x168 31. "PADCONFIG90_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x168 30. "PADCONFIG90_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x168 29. "PADCONFIG90_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x168 28. "PADCONFIG90_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x168 27. "PADCONFIG90_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x168 26. "PADCONFIG90_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x168 25. "PADCONFIG90_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x168 24. "PADCONFIG90_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x168 23. "PADCONFIG90_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x168 22. "PADCONFIG90_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x168 21. "PADCONFIG90_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x168 19.--20. "PADCONFIG90_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x168 18. "PADCONFIG90_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x168 17. "PADCONFIG90_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x168 16. "PADCONFIG90_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x168 15. "PADCONFIG90_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x168 14. "PADCONFIG90_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x168 11.--13. "PADCONFIG90_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x168 8. "PADCONFIG90_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x168 7. "PADCONFIG90_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x168 0.--3. 1. "PADCONFIG90_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x16C "CFG0_PADCONFIG91_PROXY" bitfld.long 0x16C 31. "PADCONFIG91_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x16C 30. "PADCONFIG91_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x16C 29. "PADCONFIG91_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x16C 28. "PADCONFIG91_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x16C 27. "PADCONFIG91_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x16C 26. "PADCONFIG91_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x16C 25. "PADCONFIG91_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x16C 24. "PADCONFIG91_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x16C 23. "PADCONFIG91_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x16C 22. "PADCONFIG91_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x16C 21. "PADCONFIG91_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x16C 19.--20. "PADCONFIG91_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x16C 18. "PADCONFIG91_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x16C 17. "PADCONFIG91_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x16C 16. "PADCONFIG91_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x16C 15. "PADCONFIG91_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x16C 14. "PADCONFIG91_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x16C 11.--13. "PADCONFIG91_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x16C 8. "PADCONFIG91_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x16C 7. "PADCONFIG91_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x16C 0.--3. 1. "PADCONFIG91_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x170 "CFG0_PADCONFIG92_PROXY" bitfld.long 0x170 31. "PADCONFIG92_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x170 30. "PADCONFIG92_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x170 29. "PADCONFIG92_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x170 28. "PADCONFIG92_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x170 27. "PADCONFIG92_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x170 26. "PADCONFIG92_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x170 25. "PADCONFIG92_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x170 24. "PADCONFIG92_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x170 23. "PADCONFIG92_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x170 22. "PADCONFIG92_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x170 21. "PADCONFIG92_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x170 19.--20. "PADCONFIG92_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x170 18. "PADCONFIG92_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x170 17. "PADCONFIG92_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x170 16. "PADCONFIG92_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x170 15. "PADCONFIG92_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x170 14. "PADCONFIG92_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x170 11.--13. "PADCONFIG92_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x170 8. "PADCONFIG92_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x170 7. "PADCONFIG92_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x170 0.--3. 1. "PADCONFIG92_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x174 "CFG0_PADCONFIG93_PROXY" bitfld.long 0x174 31. "PADCONFIG93_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x174 30. "PADCONFIG93_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x174 29. "PADCONFIG93_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x174 28. "PADCONFIG93_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x174 27. "PADCONFIG93_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x174 26. "PADCONFIG93_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x174 25. "PADCONFIG93_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x174 24. "PADCONFIG93_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x174 23. "PADCONFIG93_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x174 22. "PADCONFIG93_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x174 21. "PADCONFIG93_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x174 19.--20. "PADCONFIG93_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x174 18. "PADCONFIG93_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x174 17. "PADCONFIG93_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x174 16. "PADCONFIG93_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x174 15. "PADCONFIG93_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x174 14. "PADCONFIG93_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x174 11.--13. "PADCONFIG93_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x174 8. "PADCONFIG93_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x174 7. "PADCONFIG93_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x174 0.--3. 1. "PADCONFIG93_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x178 "CFG0_PADCONFIG94_PROXY" bitfld.long 0x178 31. "PADCONFIG94_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x178 30. "PADCONFIG94_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x178 29. "PADCONFIG94_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x178 28. "PADCONFIG94_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x178 27. "PADCONFIG94_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x178 26. "PADCONFIG94_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x178 25. "PADCONFIG94_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x178 24. "PADCONFIG94_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x178 23. "PADCONFIG94_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x178 22. "PADCONFIG94_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x178 21. "PADCONFIG94_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x178 19.--20. "PADCONFIG94_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x178 18. "PADCONFIG94_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x178 17. "PADCONFIG94_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x178 16. "PADCONFIG94_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x178 15. "PADCONFIG94_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x178 14. "PADCONFIG94_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x178 11.--13. "PADCONFIG94_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x178 8. "PADCONFIG94_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x178 7. "PADCONFIG94_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x178 0.--3. 1. "PADCONFIG94_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x17C "CFG0_PADCONFIG95_PROXY" bitfld.long 0x17C 31. "PADCONFIG95_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x17C 30. "PADCONFIG95_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x17C 29. "PADCONFIG95_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x17C 28. "PADCONFIG95_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x17C 27. "PADCONFIG95_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x17C 26. "PADCONFIG95_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x17C 25. "PADCONFIG95_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x17C 24. "PADCONFIG95_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x17C 23. "PADCONFIG95_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x17C 22. "PADCONFIG95_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x17C 21. "PADCONFIG95_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x17C 19.--20. "PADCONFIG95_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x17C 18. "PADCONFIG95_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x17C 17. "PADCONFIG95_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x17C 16. "PADCONFIG95_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x17C 15. "PADCONFIG95_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x17C 14. "PADCONFIG95_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x17C 11.--13. "PADCONFIG95_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x17C 8. "PADCONFIG95_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x17C 7. "PADCONFIG95_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x17C 0.--3. 1. "PADCONFIG95_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x180 "CFG0_PADCONFIG96_PROXY" bitfld.long 0x180 31. "PADCONFIG96_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x180 30. "PADCONFIG96_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x180 29. "PADCONFIG96_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x180 28. "PADCONFIG96_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x180 27. "PADCONFIG96_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x180 26. "PADCONFIG96_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x180 25. "PADCONFIG96_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x180 24. "PADCONFIG96_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x180 23. "PADCONFIG96_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x180 22. "PADCONFIG96_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x180 21. "PADCONFIG96_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x180 19.--20. "PADCONFIG96_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x180 18. "PADCONFIG96_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x180 17. "PADCONFIG96_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x180 16. "PADCONFIG96_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x180 15. "PADCONFIG96_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x180 14. "PADCONFIG96_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x180 11.--13. "PADCONFIG96_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x180 8. "PADCONFIG96_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x180 7. "PADCONFIG96_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x180 0.--3. 1. "PADCONFIG96_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x184 "CFG0_PADCONFIG97_PROXY" bitfld.long 0x184 31. "PADCONFIG97_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x184 30. "PADCONFIG97_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x184 29. "PADCONFIG97_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x184 28. "PADCONFIG97_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x184 27. "PADCONFIG97_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x184 26. "PADCONFIG97_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x184 25. "PADCONFIG97_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x184 24. "PADCONFIG97_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x184 23. "PADCONFIG97_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x184 22. "PADCONFIG97_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x184 21. "PADCONFIG97_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x184 19.--20. "PADCONFIG97_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x184 18. "PADCONFIG97_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x184 17. "PADCONFIG97_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x184 16. "PADCONFIG97_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x184 15. "PADCONFIG97_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x184 14. "PADCONFIG97_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x184 11.--13. "PADCONFIG97_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x184 8. "PADCONFIG97_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x184 7. "PADCONFIG97_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x184 0.--3. 1. "PADCONFIG97_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x188 "CFG0_PADCONFIG98_PROXY" bitfld.long 0x188 31. "PADCONFIG98_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x188 30. "PADCONFIG98_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x188 29. "PADCONFIG98_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x188 28. "PADCONFIG98_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x188 27. "PADCONFIG98_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x188 26. "PADCONFIG98_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x188 25. "PADCONFIG98_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x188 24. "PADCONFIG98_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x188 23. "PADCONFIG98_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x188 22. "PADCONFIG98_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x188 21. "PADCONFIG98_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x188 19.--20. "PADCONFIG98_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x188 18. "PADCONFIG98_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x188 17. "PADCONFIG98_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x188 16. "PADCONFIG98_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x188 15. "PADCONFIG98_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x188 14. "PADCONFIG98_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x188 11.--13. "PADCONFIG98_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x188 8. "PADCONFIG98_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x188 7. "PADCONFIG98_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x188 0.--3. 1. "PADCONFIG98_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x18C "CFG0_PADCONFIG99_PROXY" bitfld.long 0x18C 31. "PADCONFIG99_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x18C 30. "PADCONFIG99_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x18C 29. "PADCONFIG99_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x18C 28. "PADCONFIG99_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x18C 27. "PADCONFIG99_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x18C 26. "PADCONFIG99_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x18C 25. "PADCONFIG99_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x18C 24. "PADCONFIG99_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x18C 23. "PADCONFIG99_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x18C 22. "PADCONFIG99_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x18C 21. "PADCONFIG99_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x18C 19.--20. "PADCONFIG99_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18C 18. "PADCONFIG99_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x18C 17. "PADCONFIG99_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x18C 16. "PADCONFIG99_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x18C 15. "PADCONFIG99_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x18C 14. "PADCONFIG99_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x18C 11.--13. "PADCONFIG99_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18C 8. "PADCONFIG99_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x18C 7. "PADCONFIG99_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x18C 0.--3. 1. "PADCONFIG99_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x190 "CFG0_PADCONFIG100_PROXY" bitfld.long 0x190 31. "PADCONFIG100_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x190 30. "PADCONFIG100_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x190 29. "PADCONFIG100_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x190 28. "PADCONFIG100_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x190 27. "PADCONFIG100_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x190 26. "PADCONFIG100_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x190 25. "PADCONFIG100_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x190 24. "PADCONFIG100_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x190 23. "PADCONFIG100_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x190 22. "PADCONFIG100_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x190 21. "PADCONFIG100_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x190 19.--20. "PADCONFIG100_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x190 18. "PADCONFIG100_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x190 17. "PADCONFIG100_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x190 16. "PADCONFIG100_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x190 15. "PADCONFIG100_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x190 14. "PADCONFIG100_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x190 11.--13. "PADCONFIG100_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x190 8. "PADCONFIG100_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x190 7. "PADCONFIG100_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x190 0.--3. 1. "PADCONFIG100_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x194 "CFG0_PADCONFIG101_PROXY" bitfld.long 0x194 31. "PADCONFIG101_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x194 30. "PADCONFIG101_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x194 29. "PADCONFIG101_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x194 28. "PADCONFIG101_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x194 27. "PADCONFIG101_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x194 26. "PADCONFIG101_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x194 25. "PADCONFIG101_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x194 24. "PADCONFIG101_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x194 23. "PADCONFIG101_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x194 22. "PADCONFIG101_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x194 21. "PADCONFIG101_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x194 19.--20. "PADCONFIG101_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x194 18. "PADCONFIG101_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x194 17. "PADCONFIG101_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x194 16. "PADCONFIG101_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x194 15. "PADCONFIG101_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x194 14. "PADCONFIG101_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x194 11.--13. "PADCONFIG101_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x194 8. "PADCONFIG101_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x194 7. "PADCONFIG101_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x194 0.--3. 1. "PADCONFIG101_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x198 "CFG0_PADCONFIG102_PROXY" bitfld.long 0x198 31. "PADCONFIG102_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x198 30. "PADCONFIG102_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x198 29. "PADCONFIG102_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x198 28. "PADCONFIG102_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x198 27. "PADCONFIG102_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x198 26. "PADCONFIG102_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x198 25. "PADCONFIG102_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x198 24. "PADCONFIG102_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x198 23. "PADCONFIG102_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x198 22. "PADCONFIG102_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x198 21. "PADCONFIG102_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x198 19.--20. "PADCONFIG102_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x198 18. "PADCONFIG102_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x198 17. "PADCONFIG102_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x198 16. "PADCONFIG102_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x198 15. "PADCONFIG102_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x198 14. "PADCONFIG102_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x198 11.--13. "PADCONFIG102_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x198 8. "PADCONFIG102_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x198 7. "PADCONFIG102_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x198 0.--3. 1. "PADCONFIG102_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x19C "CFG0_PADCONFIG103_PROXY" bitfld.long 0x19C 31. "PADCONFIG103_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x19C 30. "PADCONFIG103_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x19C 29. "PADCONFIG103_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x19C 28. "PADCONFIG103_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x19C 27. "PADCONFIG103_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x19C 26. "PADCONFIG103_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x19C 25. "PADCONFIG103_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x19C 24. "PADCONFIG103_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x19C 23. "PADCONFIG103_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x19C 22. "PADCONFIG103_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x19C 21. "PADCONFIG103_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x19C 19.--20. "PADCONFIG103_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x19C 18. "PADCONFIG103_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x19C 17. "PADCONFIG103_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x19C 16. "PADCONFIG103_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x19C 15. "PADCONFIG103_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x19C 14. "PADCONFIG103_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x19C 11.--13. "PADCONFIG103_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x19C 8. "PADCONFIG103_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x19C 7. "PADCONFIG103_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x19C 0.--3. 1. "PADCONFIG103_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1A0 "CFG0_PADCONFIG104_PROXY" bitfld.long 0x1A0 31. "PADCONFIG104_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1A0 30. "PADCONFIG104_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1A0 29. "PADCONFIG104_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1A0 28. "PADCONFIG104_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1A0 27. "PADCONFIG104_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1A0 26. "PADCONFIG104_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1A0 25. "PADCONFIG104_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1A0 24. "PADCONFIG104_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1A0 23. "PADCONFIG104_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1A0 22. "PADCONFIG104_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1A0 21. "PADCONFIG104_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1A0 19.--20. "PADCONFIG104_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1A0 18. "PADCONFIG104_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1A0 17. "PADCONFIG104_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1A0 16. "PADCONFIG104_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1A0 15. "PADCONFIG104_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1A0 14. "PADCONFIG104_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1A0 11.--13. "PADCONFIG104_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1A0 8. "PADCONFIG104_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1A0 7. "PADCONFIG104_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1A0 0.--3. 1. "PADCONFIG104_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1A4 "CFG0_PADCONFIG105_PROXY" bitfld.long 0x1A4 31. "PADCONFIG105_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1A4 30. "PADCONFIG105_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1A4 29. "PADCONFIG105_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1A4 28. "PADCONFIG105_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1A4 27. "PADCONFIG105_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1A4 26. "PADCONFIG105_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1A4 25. "PADCONFIG105_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1A4 24. "PADCONFIG105_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1A4 23. "PADCONFIG105_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1A4 22. "PADCONFIG105_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1A4 21. "PADCONFIG105_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1A4 19.--20. "PADCONFIG105_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1A4 18. "PADCONFIG105_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1A4 17. "PADCONFIG105_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1A4 16. "PADCONFIG105_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1A4 15. "PADCONFIG105_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1A4 14. "PADCONFIG105_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1A4 11.--13. "PADCONFIG105_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1A4 8. "PADCONFIG105_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1A4 7. "PADCONFIG105_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1A4 0.--3. 1. "PADCONFIG105_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1A8 "CFG0_PADCONFIG106_PROXY" bitfld.long 0x1A8 31. "PADCONFIG106_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1A8 30. "PADCONFIG106_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1A8 29. "PADCONFIG106_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1A8 28. "PADCONFIG106_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1A8 27. "PADCONFIG106_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1A8 26. "PADCONFIG106_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1A8 25. "PADCONFIG106_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1A8 24. "PADCONFIG106_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1A8 23. "PADCONFIG106_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1A8 22. "PADCONFIG106_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1A8 21. "PADCONFIG106_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1A8 19.--20. "PADCONFIG106_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1A8 18. "PADCONFIG106_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1A8 17. "PADCONFIG106_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1A8 16. "PADCONFIG106_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1A8 15. "PADCONFIG106_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1A8 14. "PADCONFIG106_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1A8 11.--13. "PADCONFIG106_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1A8 8. "PADCONFIG106_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1A8 7. "PADCONFIG106_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1A8 0.--3. 1. "PADCONFIG106_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1AC "CFG0_PADCONFIG107_PROXY" bitfld.long 0x1AC 31. "PADCONFIG107_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1AC 30. "PADCONFIG107_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1AC 29. "PADCONFIG107_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1AC 28. "PADCONFIG107_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1AC 27. "PADCONFIG107_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1AC 26. "PADCONFIG107_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1AC 25. "PADCONFIG107_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1AC 24. "PADCONFIG107_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1AC 23. "PADCONFIG107_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1AC 22. "PADCONFIG107_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1AC 21. "PADCONFIG107_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1AC 19.--20. "PADCONFIG107_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1AC 18. "PADCONFIG107_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1AC 17. "PADCONFIG107_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1AC 16. "PADCONFIG107_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1AC 15. "PADCONFIG107_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1AC 14. "PADCONFIG107_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1AC 11.--13. "PADCONFIG107_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1AC 8. "PADCONFIG107_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1AC 7. "PADCONFIG107_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1AC 0.--3. 1. "PADCONFIG107_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1B0 "CFG0_PADCONFIG108_PROXY" bitfld.long 0x1B0 31. "PADCONFIG108_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1B0 30. "PADCONFIG108_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1B0 29. "PADCONFIG108_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1B0 28. "PADCONFIG108_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1B0 27. "PADCONFIG108_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1B0 26. "PADCONFIG108_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1B0 25. "PADCONFIG108_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1B0 24. "PADCONFIG108_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1B0 23. "PADCONFIG108_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1B0 22. "PADCONFIG108_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1B0 21. "PADCONFIG108_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1B0 19.--20. "PADCONFIG108_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1B0 18. "PADCONFIG108_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1B0 17. "PADCONFIG108_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1B0 16. "PADCONFIG108_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1B0 15. "PADCONFIG108_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1B0 14. "PADCONFIG108_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1B0 11.--13. "PADCONFIG108_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1B0 8. "PADCONFIG108_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1B0 7. "PADCONFIG108_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1B0 0.--3. 1. "PADCONFIG108_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1B4 "CFG0_PADCONFIG109_PROXY" bitfld.long 0x1B4 31. "PADCONFIG109_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1B4 30. "PADCONFIG109_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1B4 29. "PADCONFIG109_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1B4 28. "PADCONFIG109_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1B4 27. "PADCONFIG109_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1B4 26. "PADCONFIG109_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1B4 25. "PADCONFIG109_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1B4 24. "PADCONFIG109_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1B4 23. "PADCONFIG109_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1B4 22. "PADCONFIG109_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1B4 21. "PADCONFIG109_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1B4 19.--20. "PADCONFIG109_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1B4 18. "PADCONFIG109_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1B4 17. "PADCONFIG109_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1B4 16. "PADCONFIG109_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1B4 15. "PADCONFIG109_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1B4 14. "PADCONFIG109_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1B4 11.--13. "PADCONFIG109_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1B4 8. "PADCONFIG109_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1B4 7. "PADCONFIG109_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1B4 0.--3. 1. "PADCONFIG109_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1B8 "CFG0_PADCONFIG110_PROXY" bitfld.long 0x1B8 31. "PADCONFIG110_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1B8 30. "PADCONFIG110_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1B8 29. "PADCONFIG110_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1B8 28. "PADCONFIG110_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1B8 27. "PADCONFIG110_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1B8 26. "PADCONFIG110_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1B8 25. "PADCONFIG110_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1B8 24. "PADCONFIG110_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1B8 23. "PADCONFIG110_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1B8 22. "PADCONFIG110_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1B8 21. "PADCONFIG110_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1B8 19.--20. "PADCONFIG110_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1B8 18. "PADCONFIG110_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1B8 17. "PADCONFIG110_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1B8 16. "PADCONFIG110_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1B8 15. "PADCONFIG110_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1B8 14. "PADCONFIG110_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1B8 11.--13. "PADCONFIG110_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1B8 8. "PADCONFIG110_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1B8 7. "PADCONFIG110_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1B8 0.--3. 1. "PADCONFIG110_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1BC "CFG0_PADCONFIG111_PROXY" bitfld.long 0x1BC 31. "PADCONFIG111_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1BC 30. "PADCONFIG111_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1BC 29. "PADCONFIG111_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1BC 28. "PADCONFIG111_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1BC 27. "PADCONFIG111_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1BC 26. "PADCONFIG111_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1BC 25. "PADCONFIG111_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1BC 24. "PADCONFIG111_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1BC 23. "PADCONFIG111_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1BC 22. "PADCONFIG111_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1BC 21. "PADCONFIG111_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1BC 19.--20. "PADCONFIG111_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1BC 18. "PADCONFIG111_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1BC 17. "PADCONFIG111_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1BC 16. "PADCONFIG111_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1BC 15. "PADCONFIG111_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1BC 14. "PADCONFIG111_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1BC 11.--13. "PADCONFIG111_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1BC 8. "PADCONFIG111_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1BC 7. "PADCONFIG111_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1BC 0.--3. 1. "PADCONFIG111_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1C0 "CFG0_PADCONFIG112_PROXY" bitfld.long 0x1C0 31. "PADCONFIG112_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1C0 30. "PADCONFIG112_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1C0 29. "PADCONFIG112_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1C0 28. "PADCONFIG112_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1C0 27. "PADCONFIG112_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1C0 26. "PADCONFIG112_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1C0 25. "PADCONFIG112_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1C0 24. "PADCONFIG112_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1C0 23. "PADCONFIG112_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1C0 22. "PADCONFIG112_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1C0 21. "PADCONFIG112_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1C0 19.--20. "PADCONFIG112_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C0 18. "PADCONFIG112_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1C0 17. "PADCONFIG112_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1C0 16. "PADCONFIG112_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1C0 15. "PADCONFIG112_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1C0 14. "PADCONFIG112_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1C0 11.--13. "PADCONFIG112_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C0 8. "PADCONFIG112_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1C0 7. "PADCONFIG112_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1C0 0.--3. 1. "PADCONFIG112_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1C4 "CFG0_PADCONFIG113_PROXY" bitfld.long 0x1C4 31. "PADCONFIG113_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1C4 30. "PADCONFIG113_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1C4 29. "PADCONFIG113_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1C4 28. "PADCONFIG113_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1C4 27. "PADCONFIG113_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1C4 26. "PADCONFIG113_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1C4 25. "PADCONFIG113_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1C4 24. "PADCONFIG113_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1C4 23. "PADCONFIG113_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1C4 22. "PADCONFIG113_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1C4 21. "PADCONFIG113_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1C4 19.--20. "PADCONFIG113_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C4 18. "PADCONFIG113_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1C4 17. "PADCONFIG113_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1C4 16. "PADCONFIG113_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1C4 15. "PADCONFIG113_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1C4 14. "PADCONFIG113_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1C4 11.--13. "PADCONFIG113_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C4 8. "PADCONFIG113_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1C4 7. "PADCONFIG113_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1C4 0.--3. 1. "PADCONFIG113_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1C8 "CFG0_PADCONFIG114_PROXY" bitfld.long 0x1C8 31. "PADCONFIG114_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1C8 30. "PADCONFIG114_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1C8 29. "PADCONFIG114_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1C8 28. "PADCONFIG114_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1C8 27. "PADCONFIG114_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1C8 26. "PADCONFIG114_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1C8 25. "PADCONFIG114_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1C8 24. "PADCONFIG114_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1C8 23. "PADCONFIG114_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1C8 22. "PADCONFIG114_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1C8 21. "PADCONFIG114_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1C8 19.--20. "PADCONFIG114_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C8 18. "PADCONFIG114_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1C8 17. "PADCONFIG114_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1C8 16. "PADCONFIG114_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1C8 15. "PADCONFIG114_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1C8 14. "PADCONFIG114_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1C8 11.--13. "PADCONFIG114_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C8 8. "PADCONFIG114_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1C8 7. "PADCONFIG114_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1C8 0.--3. 1. "PADCONFIG114_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1CC "CFG0_PADCONFIG115_PROXY" bitfld.long 0x1CC 31. "PADCONFIG115_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1CC 30. "PADCONFIG115_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1CC 29. "PADCONFIG115_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1CC 28. "PADCONFIG115_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1CC 27. "PADCONFIG115_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1CC 26. "PADCONFIG115_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1CC 25. "PADCONFIG115_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1CC 24. "PADCONFIG115_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1CC 23. "PADCONFIG115_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1CC 22. "PADCONFIG115_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1CC 21. "PADCONFIG115_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1CC 19.--20. "PADCONFIG115_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1CC 18. "PADCONFIG115_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1CC 17. "PADCONFIG115_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1CC 16. "PADCONFIG115_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1CC 15. "PADCONFIG115_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1CC 14. "PADCONFIG115_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1CC 11.--13. "PADCONFIG115_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1CC 8. "PADCONFIG115_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1CC 7. "PADCONFIG115_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1CC 0.--3. 1. "PADCONFIG115_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1D0 "CFG0_PADCONFIG116_PROXY" bitfld.long 0x1D0 31. "PADCONFIG116_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1D0 30. "PADCONFIG116_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1D0 29. "PADCONFIG116_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1D0 28. "PADCONFIG116_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1D0 27. "PADCONFIG116_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1D0 26. "PADCONFIG116_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1D0 25. "PADCONFIG116_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1D0 24. "PADCONFIG116_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1D0 23. "PADCONFIG116_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1D0 22. "PADCONFIG116_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1D0 21. "PADCONFIG116_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1D0 19.--20. "PADCONFIG116_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1D0 18. "PADCONFIG116_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1D0 17. "PADCONFIG116_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1D0 16. "PADCONFIG116_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1D0 15. "PADCONFIG116_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1D0 14. "PADCONFIG116_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1D0 11.--13. "PADCONFIG116_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1D0 8. "PADCONFIG116_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1D0 7. "PADCONFIG116_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1D0 0.--3. 1. "PADCONFIG116_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1D4 "CFG0_PADCONFIG117_PROXY" bitfld.long 0x1D4 31. "PADCONFIG117_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1D4 30. "PADCONFIG117_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1D4 29. "PADCONFIG117_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1D4 28. "PADCONFIG117_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1D4 27. "PADCONFIG117_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1D4 26. "PADCONFIG117_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1D4 25. "PADCONFIG117_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1D4 24. "PADCONFIG117_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1D4 23. "PADCONFIG117_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1D4 22. "PADCONFIG117_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1D4 21. "PADCONFIG117_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1D4 19.--20. "PADCONFIG117_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1D4 18. "PADCONFIG117_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1D4 17. "PADCONFIG117_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1D4 16. "PADCONFIG117_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1D4 15. "PADCONFIG117_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1D4 14. "PADCONFIG117_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1D4 11.--13. "PADCONFIG117_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1D4 8. "PADCONFIG117_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1D4 7. "PADCONFIG117_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1D4 0.--3. 1. "PADCONFIG117_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1D8 "CFG0_PADCONFIG118_PROXY" bitfld.long 0x1D8 31. "PADCONFIG118_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1D8 30. "PADCONFIG118_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1D8 29. "PADCONFIG118_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1D8 28. "PADCONFIG118_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1D8 27. "PADCONFIG118_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1D8 26. "PADCONFIG118_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1D8 25. "PADCONFIG118_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1D8 24. "PADCONFIG118_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1D8 23. "PADCONFIG118_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1D8 22. "PADCONFIG118_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1D8 21. "PADCONFIG118_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1D8 19.--20. "PADCONFIG118_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1D8 18. "PADCONFIG118_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1D8 17. "PADCONFIG118_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1D8 16. "PADCONFIG118_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1D8 15. "PADCONFIG118_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1D8 14. "PADCONFIG118_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1D8 11.--13. "PADCONFIG118_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1D8 8. "PADCONFIG118_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1D8 7. "PADCONFIG118_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1D8 0.--3. 1. "PADCONFIG118_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1DC "CFG0_PADCONFIG119_PROXY" bitfld.long 0x1DC 31. "PADCONFIG119_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1DC 30. "PADCONFIG119_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1DC 29. "PADCONFIG119_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1DC 28. "PADCONFIG119_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1DC 27. "PADCONFIG119_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1DC 26. "PADCONFIG119_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1DC 25. "PADCONFIG119_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1DC 24. "PADCONFIG119_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1DC 23. "PADCONFIG119_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1DC 22. "PADCONFIG119_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1DC 21. "PADCONFIG119_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1DC 19.--20. "PADCONFIG119_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1DC 18. "PADCONFIG119_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1DC 17. "PADCONFIG119_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1DC 16. "PADCONFIG119_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1DC 15. "PADCONFIG119_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1DC 14. "PADCONFIG119_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1DC 11.--13. "PADCONFIG119_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1DC 8. "PADCONFIG119_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1DC 7. "PADCONFIG119_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1DC 0.--3. 1. "PADCONFIG119_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1E0 "CFG0_PADCONFIG120_PROXY" bitfld.long 0x1E0 31. "PADCONFIG120_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1E0 30. "PADCONFIG120_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1E0 29. "PADCONFIG120_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1E0 28. "PADCONFIG120_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1E0 27. "PADCONFIG120_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1E0 26. "PADCONFIG120_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1E0 25. "PADCONFIG120_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1E0 24. "PADCONFIG120_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1E0 23. "PADCONFIG120_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1E0 22. "PADCONFIG120_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1E0 21. "PADCONFIG120_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1E0 19.--20. "PADCONFIG120_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1E0 18. "PADCONFIG120_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1E0 17. "PADCONFIG120_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1E0 16. "PADCONFIG120_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1E0 15. "PADCONFIG120_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1E0 14. "PADCONFIG120_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1E0 11.--13. "PADCONFIG120_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1E0 8. "PADCONFIG120_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1E0 7. "PADCONFIG120_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1E0 0.--3. 1. "PADCONFIG120_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1E4 "CFG0_PADCONFIG121_PROXY" bitfld.long 0x1E4 31. "PADCONFIG121_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1E4 30. "PADCONFIG121_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1E4 29. "PADCONFIG121_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1E4 28. "PADCONFIG121_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1E4 27. "PADCONFIG121_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1E4 26. "PADCONFIG121_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1E4 25. "PADCONFIG121_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1E4 24. "PADCONFIG121_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1E4 23. "PADCONFIG121_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1E4 22. "PADCONFIG121_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1E4 21. "PADCONFIG121_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1E4 19.--20. "PADCONFIG121_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1E4 18. "PADCONFIG121_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1E4 17. "PADCONFIG121_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1E4 16. "PADCONFIG121_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1E4 15. "PADCONFIG121_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1E4 14. "PADCONFIG121_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1E4 11.--13. "PADCONFIG121_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1E4 8. "PADCONFIG121_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1E4 7. "PADCONFIG121_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1E4 0.--3. 1. "PADCONFIG121_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1E8 "CFG0_PADCONFIG122_PROXY" bitfld.long 0x1E8 31. "PADCONFIG122_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1E8 30. "PADCONFIG122_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1E8 29. "PADCONFIG122_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1E8 28. "PADCONFIG122_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1E8 27. "PADCONFIG122_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1E8 26. "PADCONFIG122_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1E8 25. "PADCONFIG122_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1E8 24. "PADCONFIG122_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1E8 23. "PADCONFIG122_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1E8 22. "PADCONFIG122_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1E8 21. "PADCONFIG122_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1E8 19.--20. "PADCONFIG122_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1E8 18. "PADCONFIG122_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1E8 17. "PADCONFIG122_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1E8 16. "PADCONFIG122_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1E8 15. "PADCONFIG122_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1E8 14. "PADCONFIG122_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1E8 11.--13. "PADCONFIG122_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1E8 8. "PADCONFIG122_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1E8 7. "PADCONFIG122_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1E8 0.--3. 1. "PADCONFIG122_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1EC "CFG0_PADCONFIG123_PROXY" bitfld.long 0x1EC 31. "PADCONFIG123_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1EC 30. "PADCONFIG123_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1EC 29. "PADCONFIG123_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1EC 28. "PADCONFIG123_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1EC 27. "PADCONFIG123_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1EC 26. "PADCONFIG123_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1EC 25. "PADCONFIG123_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1EC 24. "PADCONFIG123_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1EC 23. "PADCONFIG123_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1EC 22. "PADCONFIG123_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1EC 21. "PADCONFIG123_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1EC 19.--20. "PADCONFIG123_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1EC 18. "PADCONFIG123_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1EC 17. "PADCONFIG123_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1EC 16. "PADCONFIG123_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1EC 15. "PADCONFIG123_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1EC 14. "PADCONFIG123_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1EC 11.--13. "PADCONFIG123_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1EC 8. "PADCONFIG123_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1EC 7. "PADCONFIG123_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1EC 0.--3. 1. "PADCONFIG123_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1F0 "CFG0_PADCONFIG124_PROXY" bitfld.long 0x1F0 31. "PADCONFIG124_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1F0 30. "PADCONFIG124_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1F0 29. "PADCONFIG124_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1F0 28. "PADCONFIG124_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1F0 27. "PADCONFIG124_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1F0 26. "PADCONFIG124_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1F0 25. "PADCONFIG124_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1F0 24. "PADCONFIG124_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1F0 23. "PADCONFIG124_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1F0 22. "PADCONFIG124_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1F0 21. "PADCONFIG124_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1F0 19.--20. "PADCONFIG124_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1F0 18. "PADCONFIG124_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1F0 17. "PADCONFIG124_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1F0 16. "PADCONFIG124_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1F0 15. "PADCONFIG124_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1F0 14. "PADCONFIG124_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1F0 11.--13. "PADCONFIG124_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1F0 8. "PADCONFIG124_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1F0 7. "PADCONFIG124_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1F0 0.--3. 1. "PADCONFIG124_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1F4 "CFG0_PADCONFIG125_PROXY" bitfld.long 0x1F4 31. "PADCONFIG125_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1F4 30. "PADCONFIG125_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1F4 29. "PADCONFIG125_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1F4 28. "PADCONFIG125_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1F4 27. "PADCONFIG125_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1F4 26. "PADCONFIG125_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1F4 25. "PADCONFIG125_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1F4 24. "PADCONFIG125_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1F4 23. "PADCONFIG125_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1F4 22. "PADCONFIG125_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1F4 21. "PADCONFIG125_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1F4 19.--20. "PADCONFIG125_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1F4 18. "PADCONFIG125_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1F4 17. "PADCONFIG125_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1F4 16. "PADCONFIG125_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1F4 15. "PADCONFIG125_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1F4 14. "PADCONFIG125_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1F4 11.--13. "PADCONFIG125_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1F4 8. "PADCONFIG125_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1F4 7. "PADCONFIG125_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1F4 0.--3. 1. "PADCONFIG125_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1F8 "CFG0_PADCONFIG126_PROXY" bitfld.long 0x1F8 31. "PADCONFIG126_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1F8 30. "PADCONFIG126_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1F8 29. "PADCONFIG126_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1F8 28. "PADCONFIG126_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1F8 27. "PADCONFIG126_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1F8 26. "PADCONFIG126_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1F8 25. "PADCONFIG126_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1F8 24. "PADCONFIG126_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1F8 23. "PADCONFIG126_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1F8 22. "PADCONFIG126_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1F8 21. "PADCONFIG126_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1F8 19.--20. "PADCONFIG126_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1F8 18. "PADCONFIG126_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1F8 17. "PADCONFIG126_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1F8 16. "PADCONFIG126_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1F8 15. "PADCONFIG126_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1F8 14. "PADCONFIG126_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1F8 11.--13. "PADCONFIG126_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1F8 8. "PADCONFIG126_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1F8 7. "PADCONFIG126_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1F8 0.--3. 1. "PADCONFIG126_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x1FC "CFG0_PADCONFIG127_PROXY" bitfld.long 0x1FC 31. "PADCONFIG127_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1FC 30. "PADCONFIG127_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1FC 29. "PADCONFIG127_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1FC 28. "PADCONFIG127_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1FC 27. "PADCONFIG127_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1FC 26. "PADCONFIG127_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1FC 25. "PADCONFIG127_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1FC 24. "PADCONFIG127_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1FC 23. "PADCONFIG127_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1FC 22. "PADCONFIG127_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1FC 21. "PADCONFIG127_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1FC 19.--20. "PADCONFIG127_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1FC 18. "PADCONFIG127_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1FC 17. "PADCONFIG127_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1FC 16. "PADCONFIG127_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1FC 15. "PADCONFIG127_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1FC 14. "PADCONFIG127_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1FC 11.--13. "PADCONFIG127_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1FC 8. "PADCONFIG127_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1FC 7. "PADCONFIG127_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1FC 0.--3. 1. "PADCONFIG127_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x200 "CFG0_PADCONFIG128_PROXY" bitfld.long 0x200 31. "PADCONFIG128_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x200 30. "PADCONFIG128_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x200 29. "PADCONFIG128_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x200 28. "PADCONFIG128_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x200 27. "PADCONFIG128_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x200 26. "PADCONFIG128_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x200 25. "PADCONFIG128_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x200 24. "PADCONFIG128_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x200 23. "PADCONFIG128_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x200 22. "PADCONFIG128_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x200 21. "PADCONFIG128_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x200 19.--20. "PADCONFIG128_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x200 18. "PADCONFIG128_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x200 17. "PADCONFIG128_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x200 16. "PADCONFIG128_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x200 15. "PADCONFIG128_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x200 14. "PADCONFIG128_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x200 11.--13. "PADCONFIG128_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x200 8. "PADCONFIG128_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x200 7. "PADCONFIG128_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x200 0.--3. 1. "PADCONFIG128_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x204 "CFG0_PADCONFIG129_PROXY" bitfld.long 0x204 31. "PADCONFIG129_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x204 30. "PADCONFIG129_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x204 29. "PADCONFIG129_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x204 28. "PADCONFIG129_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x204 27. "PADCONFIG129_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x204 26. "PADCONFIG129_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x204 25. "PADCONFIG129_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x204 24. "PADCONFIG129_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x204 23. "PADCONFIG129_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x204 22. "PADCONFIG129_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x204 21. "PADCONFIG129_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x204 19.--20. "PADCONFIG129_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x204 18. "PADCONFIG129_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x204 17. "PADCONFIG129_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x204 16. "PADCONFIG129_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x204 15. "PADCONFIG129_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x204 14. "PADCONFIG129_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x204 11.--13. "PADCONFIG129_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x204 8. "PADCONFIG129_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x204 7. "PADCONFIG129_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x204 0.--3. 1. "PADCONFIG129_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x208 "CFG0_PADCONFIG130_PROXY" bitfld.long 0x208 31. "PADCONFIG130_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x208 30. "PADCONFIG130_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x208 29. "PADCONFIG130_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x208 28. "PADCONFIG130_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x208 27. "PADCONFIG130_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x208 26. "PADCONFIG130_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x208 25. "PADCONFIG130_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x208 24. "PADCONFIG130_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x208 23. "PADCONFIG130_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x208 22. "PADCONFIG130_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x208 21. "PADCONFIG130_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x208 19.--20. "PADCONFIG130_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x208 18. "PADCONFIG130_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x208 17. "PADCONFIG130_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x208 16. "PADCONFIG130_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x208 15. "PADCONFIG130_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x208 14. "PADCONFIG130_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x208 11.--13. "PADCONFIG130_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x208 8. "PADCONFIG130_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x208 7. "PADCONFIG130_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x208 0.--3. 1. "PADCONFIG130_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x20C "CFG0_PADCONFIG131_PROXY" bitfld.long 0x20C 31. "PADCONFIG131_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x20C 30. "PADCONFIG131_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x20C 29. "PADCONFIG131_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x20C 28. "PADCONFIG131_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x20C 27. "PADCONFIG131_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x20C 26. "PADCONFIG131_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x20C 25. "PADCONFIG131_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x20C 24. "PADCONFIG131_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x20C 23. "PADCONFIG131_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x20C 22. "PADCONFIG131_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x20C 21. "PADCONFIG131_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x20C 19.--20. "PADCONFIG131_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20C 18. "PADCONFIG131_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x20C 17. "PADCONFIG131_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x20C 16. "PADCONFIG131_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x20C 15. "PADCONFIG131_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x20C 14. "PADCONFIG131_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x20C 11.--13. "PADCONFIG131_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20C 8. "PADCONFIG131_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x20C 7. "PADCONFIG131_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x20C 0.--3. 1. "PADCONFIG131_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x210 "CFG0_PADCONFIG132_PROXY" bitfld.long 0x210 31. "PADCONFIG132_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x210 30. "PADCONFIG132_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x210 29. "PADCONFIG132_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x210 28. "PADCONFIG132_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x210 27. "PADCONFIG132_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x210 26. "PADCONFIG132_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x210 25. "PADCONFIG132_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x210 24. "PADCONFIG132_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x210 23. "PADCONFIG132_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x210 22. "PADCONFIG132_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x210 21. "PADCONFIG132_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x210 19.--20. "PADCONFIG132_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x210 18. "PADCONFIG132_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x210 17. "PADCONFIG132_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x210 16. "PADCONFIG132_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x210 15. "PADCONFIG132_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x210 14. "PADCONFIG132_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x210 11.--13. "PADCONFIG132_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x210 8. "PADCONFIG132_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x210 7. "PADCONFIG132_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x210 0.--3. 1. "PADCONFIG132_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x214 "CFG0_PADCONFIG133_PROXY" bitfld.long 0x214 31. "PADCONFIG133_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x214 30. "PADCONFIG133_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x214 29. "PADCONFIG133_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x214 28. "PADCONFIG133_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x214 27. "PADCONFIG133_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x214 26. "PADCONFIG133_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x214 25. "PADCONFIG133_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x214 24. "PADCONFIG133_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x214 23. "PADCONFIG133_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x214 22. "PADCONFIG133_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x214 21. "PADCONFIG133_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x214 19.--20. "PADCONFIG133_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x214 18. "PADCONFIG133_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x214 17. "PADCONFIG133_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x214 16. "PADCONFIG133_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x214 15. "PADCONFIG133_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x214 14. "PADCONFIG133_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x214 11.--13. "PADCONFIG133_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x214 8. "PADCONFIG133_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x214 7. "PADCONFIG133_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x214 0.--3. 1. "PADCONFIG133_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x218 "CFG0_PADCONFIG134_PROXY" bitfld.long 0x218 31. "PADCONFIG134_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x218 30. "PADCONFIG134_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x218 29. "PADCONFIG134_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x218 28. "PADCONFIG134_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x218 27. "PADCONFIG134_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x218 26. "PADCONFIG134_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x218 25. "PADCONFIG134_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x218 24. "PADCONFIG134_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x218 23. "PADCONFIG134_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x218 22. "PADCONFIG134_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x218 21. "PADCONFIG134_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x218 19.--20. "PADCONFIG134_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x218 18. "PADCONFIG134_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x218 17. "PADCONFIG134_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x218 16. "PADCONFIG134_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x218 15. "PADCONFIG134_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x218 14. "PADCONFIG134_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x218 11.--13. "PADCONFIG134_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x218 8. "PADCONFIG134_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x218 7. "PADCONFIG134_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x218 0.--3. 1. "PADCONFIG134_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x21C "CFG0_PADCONFIG135_PROXY" bitfld.long 0x21C 31. "PADCONFIG135_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x21C 30. "PADCONFIG135_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x21C 29. "PADCONFIG135_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x21C 28. "PADCONFIG135_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x21C 27. "PADCONFIG135_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x21C 26. "PADCONFIG135_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x21C 25. "PADCONFIG135_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x21C 24. "PADCONFIG135_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x21C 23. "PADCONFIG135_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x21C 22. "PADCONFIG135_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x21C 21. "PADCONFIG135_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x21C 19.--20. "PADCONFIG135_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x21C 18. "PADCONFIG135_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x21C 17. "PADCONFIG135_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x21C 16. "PADCONFIG135_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x21C 15. "PADCONFIG135_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x21C 14. "PADCONFIG135_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x21C 11.--13. "PADCONFIG135_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x21C 8. "PADCONFIG135_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x21C 7. "PADCONFIG135_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x21C 0.--3. 1. "PADCONFIG135_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x220 "CFG0_PADCONFIG136_PROXY" bitfld.long 0x220 31. "PADCONFIG136_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x220 30. "PADCONFIG136_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x220 29. "PADCONFIG136_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x220 28. "PADCONFIG136_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x220 27. "PADCONFIG136_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x220 26. "PADCONFIG136_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x220 25. "PADCONFIG136_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x220 24. "PADCONFIG136_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x220 23. "PADCONFIG136_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x220 22. "PADCONFIG136_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x220 21. "PADCONFIG136_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x220 19.--20. "PADCONFIG136_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x220 18. "PADCONFIG136_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x220 17. "PADCONFIG136_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x220 16. "PADCONFIG136_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x220 15. "PADCONFIG136_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x220 14. "PADCONFIG136_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x220 11.--13. "PADCONFIG136_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x220 8. "PADCONFIG136_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x220 7. "PADCONFIG136_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x220 0.--3. 1. "PADCONFIG136_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x224 "CFG0_PADCONFIG137_PROXY" bitfld.long 0x224 31. "PADCONFIG137_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x224 30. "PADCONFIG137_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x224 29. "PADCONFIG137_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x224 28. "PADCONFIG137_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x224 27. "PADCONFIG137_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x224 26. "PADCONFIG137_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x224 25. "PADCONFIG137_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x224 24. "PADCONFIG137_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x224 23. "PADCONFIG137_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x224 22. "PADCONFIG137_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x224 21. "PADCONFIG137_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x224 19.--20. "PADCONFIG137_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x224 18. "PADCONFIG137_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x224 17. "PADCONFIG137_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x224 16. "PADCONFIG137_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x224 15. "PADCONFIG137_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x224 14. "PADCONFIG137_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x224 11.--13. "PADCONFIG137_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x224 8. "PADCONFIG137_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x224 7. "PADCONFIG137_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x224 0.--3. 1. "PADCONFIG137_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x228 "CFG0_PADCONFIG138_PROXY" bitfld.long 0x228 31. "PADCONFIG138_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x228 30. "PADCONFIG138_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x228 29. "PADCONFIG138_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x228 28. "PADCONFIG138_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x228 27. "PADCONFIG138_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x228 26. "PADCONFIG138_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x228 25. "PADCONFIG138_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x228 24. "PADCONFIG138_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x228 23. "PADCONFIG138_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x228 22. "PADCONFIG138_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x228 21. "PADCONFIG138_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x228 19.--20. "PADCONFIG138_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x228 18. "PADCONFIG138_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x228 17. "PADCONFIG138_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x228 16. "PADCONFIG138_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x228 15. "PADCONFIG138_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x228 14. "PADCONFIG138_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x228 11.--13. "PADCONFIG138_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x228 8. "PADCONFIG138_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x228 7. "PADCONFIG138_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x228 0.--3. 1. "PADCONFIG138_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x22C "CFG0_PADCONFIG139_PROXY" bitfld.long 0x22C 31. "PADCONFIG139_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x22C 30. "PADCONFIG139_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x22C 29. "PADCONFIG139_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x22C 28. "PADCONFIG139_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x22C 27. "PADCONFIG139_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x22C 26. "PADCONFIG139_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x22C 25. "PADCONFIG139_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x22C 24. "PADCONFIG139_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x22C 23. "PADCONFIG139_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x22C 22. "PADCONFIG139_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x22C 21. "PADCONFIG139_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x22C 19.--20. "PADCONFIG139_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x22C 18. "PADCONFIG139_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x22C 17. "PADCONFIG139_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x22C 16. "PADCONFIG139_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x22C 15. "PADCONFIG139_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x22C 14. "PADCONFIG139_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x22C 11.--13. "PADCONFIG139_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x22C 8. "PADCONFIG139_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x22C 7. "PADCONFIG139_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x22C 0.--3. 1. "PADCONFIG139_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x230 "CFG0_PADCONFIG140_PROXY" bitfld.long 0x230 31. "PADCONFIG140_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x230 30. "PADCONFIG140_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x230 29. "PADCONFIG140_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x230 28. "PADCONFIG140_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x230 27. "PADCONFIG140_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x230 26. "PADCONFIG140_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x230 25. "PADCONFIG140_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x230 24. "PADCONFIG140_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x230 23. "PADCONFIG140_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x230 22. "PADCONFIG140_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x230 21. "PADCONFIG140_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x230 19.--20. "PADCONFIG140_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x230 18. "PADCONFIG140_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x230 17. "PADCONFIG140_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x230 16. "PADCONFIG140_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x230 15. "PADCONFIG140_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x230 14. "PADCONFIG140_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x230 11.--13. "PADCONFIG140_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x230 8. "PADCONFIG140_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x230 7. "PADCONFIG140_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x230 0.--3. 1. "PADCONFIG140_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x234 "CFG0_PADCONFIG141_PROXY" bitfld.long 0x234 31. "PADCONFIG141_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x234 30. "PADCONFIG141_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x234 29. "PADCONFIG141_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x234 28. "PADCONFIG141_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x234 27. "PADCONFIG141_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x234 26. "PADCONFIG141_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x234 25. "PADCONFIG141_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x234 24. "PADCONFIG141_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x234 23. "PADCONFIG141_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x234 22. "PADCONFIG141_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x234 21. "PADCONFIG141_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x234 19.--20. "PADCONFIG141_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x234 18. "PADCONFIG141_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x234 17. "PADCONFIG141_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x234 16. "PADCONFIG141_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x234 15. "PADCONFIG141_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x234 14. "PADCONFIG141_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x234 11.--13. "PADCONFIG141_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x234 8. "PADCONFIG141_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x234 7. "PADCONFIG141_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x234 0.--3. 1. "PADCONFIG141_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x238 "CFG0_PADCONFIG142_PROXY" bitfld.long 0x238 31. "PADCONFIG142_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x238 30. "PADCONFIG142_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x238 29. "PADCONFIG142_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x238 28. "PADCONFIG142_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x238 27. "PADCONFIG142_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x238 26. "PADCONFIG142_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x238 25. "PADCONFIG142_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x238 24. "PADCONFIG142_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x238 23. "PADCONFIG142_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x238 22. "PADCONFIG142_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x238 21. "PADCONFIG142_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x238 19.--20. "PADCONFIG142_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x238 18. "PADCONFIG142_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x238 17. "PADCONFIG142_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x238 16. "PADCONFIG142_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x238 15. "PADCONFIG142_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x238 14. "PADCONFIG142_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x238 11.--13. "PADCONFIG142_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x238 8. "PADCONFIG142_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x238 7. "PADCONFIG142_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x238 0.--3. 1. "PADCONFIG142_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x23C "CFG0_PADCONFIG143_PROXY" bitfld.long 0x23C 31. "PADCONFIG143_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x23C 30. "PADCONFIG143_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x23C 29. "PADCONFIG143_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x23C 28. "PADCONFIG143_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x23C 27. "PADCONFIG143_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x23C 26. "PADCONFIG143_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x23C 25. "PADCONFIG143_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x23C 24. "PADCONFIG143_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x23C 23. "PADCONFIG143_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x23C 22. "PADCONFIG143_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x23C 21. "PADCONFIG143_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x23C 19.--20. "PADCONFIG143_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x23C 18. "PADCONFIG143_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x23C 17. "PADCONFIG143_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x23C 16. "PADCONFIG143_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x23C 15. "PADCONFIG143_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x23C 14. "PADCONFIG143_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x23C 11.--13. "PADCONFIG143_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x23C 8. "PADCONFIG143_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x23C 7. "PADCONFIG143_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x23C 0.--3. 1. "PADCONFIG143_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x240 "CFG0_PADCONFIG144_PROXY" bitfld.long 0x240 31. "PADCONFIG144_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x240 30. "PADCONFIG144_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x240 29. "PADCONFIG144_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x240 28. "PADCONFIG144_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x240 27. "PADCONFIG144_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x240 26. "PADCONFIG144_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x240 25. "PADCONFIG144_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x240 24. "PADCONFIG144_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x240 23. "PADCONFIG144_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x240 22. "PADCONFIG144_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x240 21. "PADCONFIG144_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x240 19.--20. "PADCONFIG144_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x240 18. "PADCONFIG144_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x240 17. "PADCONFIG144_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x240 16. "PADCONFIG144_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x240 15. "PADCONFIG144_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x240 14. "PADCONFIG144_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x240 11.--13. "PADCONFIG144_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x240 8. "PADCONFIG144_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x240 7. "PADCONFIG144_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x240 0.--3. 1. "PADCONFIG144_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x244 "CFG0_PADCONFIG145_PROXY" bitfld.long 0x244 31. "PADCONFIG145_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x244 30. "PADCONFIG145_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x244 29. "PADCONFIG145_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x244 28. "PADCONFIG145_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x244 27. "PADCONFIG145_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x244 26. "PADCONFIG145_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x244 25. "PADCONFIG145_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x244 24. "PADCONFIG145_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x244 23. "PADCONFIG145_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x244 22. "PADCONFIG145_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x244 21. "PADCONFIG145_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x244 19.--20. "PADCONFIG145_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x244 18. "PADCONFIG145_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x244 17. "PADCONFIG145_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x244 16. "PADCONFIG145_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x244 15. "PADCONFIG145_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x244 14. "PADCONFIG145_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x244 11.--13. "PADCONFIG145_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x244 8. "PADCONFIG145_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x244 7. "PADCONFIG145_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x244 0.--3. 1. "PADCONFIG145_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x248 "CFG0_PADCONFIG146_PROXY" bitfld.long 0x248 31. "PADCONFIG146_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x248 30. "PADCONFIG146_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x248 29. "PADCONFIG146_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x248 28. "PADCONFIG146_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x248 27. "PADCONFIG146_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x248 26. "PADCONFIG146_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x248 25. "PADCONFIG146_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x248 24. "PADCONFIG146_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x248 23. "PADCONFIG146_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x248 22. "PADCONFIG146_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x248 21. "PADCONFIG146_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x248 19.--20. "PADCONFIG146_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x248 18. "PADCONFIG146_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x248 17. "PADCONFIG146_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x248 16. "PADCONFIG146_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x248 15. "PADCONFIG146_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x248 14. "PADCONFIG146_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x248 11.--13. "PADCONFIG146_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x248 8. "PADCONFIG146_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x248 7. "PADCONFIG146_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x248 0.--3. 1. "PADCONFIG146_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x24C "CFG0_PADCONFIG147_PROXY" bitfld.long 0x24C 31. "PADCONFIG147_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x24C 30. "PADCONFIG147_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x24C 29. "PADCONFIG147_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x24C 28. "PADCONFIG147_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x24C 27. "PADCONFIG147_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x24C 26. "PADCONFIG147_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x24C 25. "PADCONFIG147_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x24C 24. "PADCONFIG147_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x24C 23. "PADCONFIG147_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x24C 22. "PADCONFIG147_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x24C 21. "PADCONFIG147_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x24C 19.--20. "PADCONFIG147_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24C 18. "PADCONFIG147_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x24C 17. "PADCONFIG147_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x24C 16. "PADCONFIG147_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x24C 15. "PADCONFIG147_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x24C 14. "PADCONFIG147_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x24C 11.--13. "PADCONFIG147_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24C 8. "PADCONFIG147_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x24C 7. "PADCONFIG147_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x24C 0.--3. 1. "PADCONFIG147_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x250 "CFG0_PADCONFIG148_PROXY" bitfld.long 0x250 31. "PADCONFIG148_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x250 30. "PADCONFIG148_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x250 29. "PADCONFIG148_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x250 28. "PADCONFIG148_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x250 27. "PADCONFIG148_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x250 26. "PADCONFIG148_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x250 25. "PADCONFIG148_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x250 24. "PADCONFIG148_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x250 23. "PADCONFIG148_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x250 22. "PADCONFIG148_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x250 21. "PADCONFIG148_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x250 19.--20. "PADCONFIG148_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x250 18. "PADCONFIG148_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x250 17. "PADCONFIG148_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x250 16. "PADCONFIG148_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x250 15. "PADCONFIG148_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x250 14. "PADCONFIG148_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x250 11.--13. "PADCONFIG148_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x250 8. "PADCONFIG148_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x250 7. "PADCONFIG148_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x250 0.--3. 1. "PADCONFIG148_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x254 "CFG0_PADCONFIG149_PROXY" bitfld.long 0x254 31. "PADCONFIG149_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x254 30. "PADCONFIG149_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x254 29. "PADCONFIG149_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x254 28. "PADCONFIG149_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x254 27. "PADCONFIG149_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x254 26. "PADCONFIG149_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x254 25. "PADCONFIG149_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x254 24. "PADCONFIG149_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x254 23. "PADCONFIG149_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x254 22. "PADCONFIG149_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x254 21. "PADCONFIG149_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x254 19.--20. "PADCONFIG149_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x254 18. "PADCONFIG149_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x254 17. "PADCONFIG149_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x254 16. "PADCONFIG149_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x254 15. "PADCONFIG149_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x254 14. "PADCONFIG149_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x254 11.--13. "PADCONFIG149_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x254 8. "PADCONFIG149_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x254 7. "PADCONFIG149_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x254 0.--3. 1. "PADCONFIG149_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." line.long 0x258 "CFG0_PADCONFIG150_PROXY" bitfld.long 0x258 31. "PADCONFIG150_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x258 30. "PADCONFIG150_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x258 29. "PADCONFIG150_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x258 28. "PADCONFIG150_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x258 27. "PADCONFIG150_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x258 26. "PADCONFIG150_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x258 25. "PADCONFIG150_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x258 24. "PADCONFIG150_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x258 23. "PADCONFIG150_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x258 22. "PADCONFIG150_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x258 21. "PADCONFIG150_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x258 19.--20. "PADCONFIG150_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x258 18. "PADCONFIG150_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x258 17. "PADCONFIG150_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x258 16. "PADCONFIG150_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x258 15. "PADCONFIG150_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x258 14. "PADCONFIG150_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x258 11.--13. "PADCONFIG150_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x258 8. "PADCONFIG150_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x258 7. "PADCONFIG150_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x258 0.--3. 1. "PADCONFIG150_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111.." group.long 0x7008++0x7 line.long 0x0 "CFG0_LOCK1_KICK0_PROXY" hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK1_KICK1_PROXY" hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1_PROXY,- KICK1 component" group.long 0x7100++0x13 line.long 0x0 "CFG0_CLAIMREG_P1_R0" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0,Claim bits for Partition 1" line.long 0x4 "CFG0_CLAIMREG_P1_R1" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1,Claim bits for Partition 1" line.long 0x8 "CFG0_CLAIMREG_P1_R2" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2,Claim bits for Partition 1" line.long 0xC "CFG0_CLAIMREG_P1_R3" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P1_R3,Claim bits for Partition 1" line.long 0x10 "CFG0_CLAIMREG_P1_R4" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P1_R4,Claim bits for Partition 1" tree.end tree "PBIST" base ad:0x0 tree "PBIST0" base ad:0x3F110000 group.long 0x0++0x7F line.long 0x0 "MEM_RF0L" hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L" hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L" hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L" hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L" hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L" hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L" hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L" hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L" hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L" hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L" hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L" hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L" hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L" hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L" hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L" hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U" hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U" hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U" hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U" hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U" hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U" hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U" hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U" hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U" hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U" hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U" hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U" hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U" hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U" hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U" hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U" hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" group.long 0x100++0x27 line.long 0x0 "MEM_A0" hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1" hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2" hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3" hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0" hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1" hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2" hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3" hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D" hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E" hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" group.long 0x130++0x3F line.long 0x0 "MEM_CA0" hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1" hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2" hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3" hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0" hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1" hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2" hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3" hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0" hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1" hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2" hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3" hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT" hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR" hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS" hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR" bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" group.quad 0x170++0x7 line.quad 0x0 "MEM_SCR" hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" group.long 0x178++0x13 line.long 0x0 "MEM_CSR" hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY" hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT" bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID" hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER" bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF" bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC" hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA" hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0" hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1" hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE" bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ" bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS" bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" group.long 0x1C0++0x7 line.long 0x0 "MEM_ROM" bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO" hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" group.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO" hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end tree.end tree "PDMA" base ad:0x0 tree "PDMA0" base ad:0xC00000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "PDMA1" base ad:0xC01000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1" bitfld.long 0x4 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1" bitfld.long 0x4 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1" bitfld.long 0x0 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1" bitfld.long 0x0 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "PLL0_CFG" base ad:0x680000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_pll0_PID" bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x8++0x3 line.long 0x0 "CFG_pll0_CFG" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x10++0x7 line.long 0x0 "CFG_pll0_LOCKKEY0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll0_LOCKKEY1" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers" group.long 0x20++0x3 line.long 0x0 "CFG_pll0_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1" rgroup.long 0x24++0x3 line.long 0x0 "CFG_pll0_STAT" bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x30++0xB line.long 0x0 "CFG_pll0_FREQ_CTRL0" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll0_FREQ_CTRL1" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll0_DIV_CTRL" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x40++0x7 line.long 0x0 "CFG_pll0_SS_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "CFG_pll0_SS_SPREAD" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x60++0x3 line.long 0x0 "CFG_pll0_CAL_CTRL" bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1" bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1" bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1" hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x64++0x3 line.long 0x0 "CFG_pll0_CAL_STAT" bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" group.long 0x80++0x27 line.long 0x0 "CFG_pll0_HSDIV_CTRL0" bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll0_HSDIV_CTRL1" bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "CFG_pll0_HSDIV_CTRL2" bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "CFG_pll0_HSDIV_CTRL3" bitfld.long 0xC 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "CFG_pll0_HSDIV_CTRL4" bitfld.long 0x10 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x14 "CFG_pll0_HSDIV_CTRL5" bitfld.long 0x14 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x14 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x14 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x14 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x18 "CFG_pll0_HSDIV_CTRL6" bitfld.long 0x18 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x18 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x18 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x18 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x1C "CFG_pll0_HSDIV_CTRL7" bitfld.long 0x1C 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x1C 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x1C 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x1C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x20 "CFG_pll0_HSDIV_CTRL8" bitfld.long 0x20 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x20 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x20 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x20 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x24 "CFG_pll0_HSDIV_CTRL9" bitfld.long 0x24 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x24 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x24 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x24 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x1000++0x3 line.long 0x0 "CFG_pll1_PID" bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x1008++0x3 line.long 0x0 "CFG_pll1_CFG" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x1010++0x7 line.long 0x0 "CFG_pll1_LOCKKEY0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll1_LOCKKEY1" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers" group.long 0x1020++0x3 line.long 0x0 "CFG_pll1_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1" rgroup.long 0x1024++0x3 line.long 0x0 "CFG_pll1_STAT" bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x1030++0xB line.long 0x0 "CFG_pll1_FREQ_CTRL0" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll1_FREQ_CTRL1" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll1_DIV_CTRL" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x1040++0x7 line.long 0x0 "CFG_pll1_SS_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "CFG_pll1_SS_SPREAD" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x1060++0x3 line.long 0x0 "CFG_pll1_CAL_CTRL" bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1" bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1" bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1" hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x1064++0x3 line.long 0x0 "CFG_pll1_CAL_STAT" bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" group.long 0x1080++0x1B line.long 0x0 "CFG_pll1_HSDIV_CTRL0" bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll1_HSDIV_CTRL1" bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "CFG_pll1_HSDIV_CTRL2" bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "CFG_pll1_HSDIV_CTRL3" bitfld.long 0xC 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "CFG_pll1_HSDIV_CTRL4" bitfld.long 0x10 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x14 "CFG_pll1_HSDIV_CTRL5" bitfld.long 0x14 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x14 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x14 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x14 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x18 "CFG_pll1_HSDIV_CTRL6" bitfld.long 0x18 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x18 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x18 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x18 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x2000++0x3 line.long 0x0 "CFG_pll2_PID" bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x2008++0x3 line.long 0x0 "CFG_pll2_CFG" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x2010++0x7 line.long 0x0 "CFG_pll2_LOCKKEY0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll2_LOCKKEY1" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers" group.long 0x2020++0x3 line.long 0x0 "CFG_pll2_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1" rgroup.long 0x2024++0x3 line.long 0x0 "CFG_pll2_STAT" bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x2030++0xB line.long 0x0 "CFG_pll2_FREQ_CTRL0" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll2_FREQ_CTRL1" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll2_DIV_CTRL" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x2040++0x7 line.long 0x0 "CFG_pll2_SS_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "CFG_pll2_SS_SPREAD" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x2060++0x3 line.long 0x0 "CFG_pll2_CAL_CTRL" bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1" bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1" bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1" hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x2064++0x3 line.long 0x0 "CFG_pll2_CAL_STAT" bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" group.long 0x2080++0x27 line.long 0x0 "CFG_pll2_HSDIV_CTRL0" bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll2_HSDIV_CTRL1" bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "CFG_pll2_HSDIV_CTRL2" bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "CFG_pll2_HSDIV_CTRL3" bitfld.long 0xC 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "CFG_pll2_HSDIV_CTRL4" bitfld.long 0x10 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x14 "CFG_pll2_HSDIV_CTRL5" bitfld.long 0x14 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x14 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x14 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x14 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x18 "CFG_pll2_HSDIV_CTRL6" bitfld.long 0x18 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x18 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x18 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x18 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x1C "CFG_pll2_HSDIV_CTRL7" bitfld.long 0x1C 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x1C 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x1C 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x1C 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x20 "CFG_pll2_HSDIV_CTRL8" bitfld.long 0x20 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x20 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x20 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x20 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x24 "CFG_pll2_HSDIV_CTRL9" bitfld.long 0x24 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x24 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x24 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x24 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x5000++0x3 line.long 0x0 "CFG_pll5_PID" bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x5008++0x3 line.long 0x0 "CFG_pll5_CFG" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x5010++0x7 line.long 0x0 "CFG_pll5_LOCKKEY0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition5 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll5_LOCKKEY1" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition5 registers" group.long 0x5020++0x3 line.long 0x0 "CFG_pll5_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1" rgroup.long 0x5024++0x3 line.long 0x0 "CFG_pll5_STAT" bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x5030++0xB line.long 0x0 "CFG_pll5_FREQ_CTRL0" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll5_FREQ_CTRL1" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll5_DIV_CTRL" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x5040++0x7 line.long 0x0 "CFG_pll5_SS_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "CFG_pll5_SS_SPREAD" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x5060++0x3 line.long 0x0 "CFG_pll5_CAL_CTRL" bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1" bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1" bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1" hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x5064++0x3 line.long 0x0 "CFG_pll5_CAL_STAT" bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" group.long 0x5080++0xB line.long 0x0 "CFG_pll5_HSDIV_CTRL0" bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll5_HSDIV_CTRL1" bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "CFG_pll5_HSDIV_CTRL2" bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x7000++0x3 line.long 0x0 "CFG_pll7_PID" bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x7008++0x3 line.long 0x0 "CFG_pll7_CFG" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x7010++0x7 line.long 0x0 "CFG_pll7_LOCKKEY0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition7 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll7_LOCKKEY1" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition7 registers" group.long 0x7020++0x3 line.long 0x0 "CFG_pll7_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1" rgroup.long 0x7024++0x3 line.long 0x0 "CFG_pll7_STAT" bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x7030++0xB line.long 0x0 "CFG_pll7_FREQ_CTRL0" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll7_FREQ_CTRL1" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll7_DIV_CTRL" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x7040++0x7 line.long 0x0 "CFG_pll7_SS_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "CFG_pll7_SS_SPREAD" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x7060++0x3 line.long 0x0 "CFG_pll7_CAL_CTRL" bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1" bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1" bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1" hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x7064++0x3 line.long 0x0 "CFG_pll7_CAL_STAT" bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" group.long 0x7080++0x3 line.long 0x0 "CFG_pll7_HSDIV_CTRL0" bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x8000++0x3 line.long 0x0 "CFG_pll8_PID" bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x8008++0x3 line.long 0x0 "CFG_pll8_CFG" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x8010++0x7 line.long 0x0 "CFG_pll8_LOCKKEY0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition8 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll8_LOCKKEY1" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition8 registers" group.long 0x8020++0x3 line.long 0x0 "CFG_pll8_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1" rgroup.long 0x8024++0x3 line.long 0x0 "CFG_pll8_STAT" bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x8030++0xB line.long 0x0 "CFG_pll8_FREQ_CTRL0" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll8_FREQ_CTRL1" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll8_DIV_CTRL" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x8040++0x7 line.long 0x0 "CFG_pll8_SS_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "CFG_pll8_SS_SPREAD" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x8060++0x3 line.long 0x0 "CFG_pll8_CAL_CTRL" bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1" bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1" bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1" hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x8064++0x3 line.long 0x0 "CFG_pll8_CAL_STAT" bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" group.long 0x8080++0x3 line.long 0x0 "CFG_pll8_HSDIV_CTRL0" bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0xC000++0x3 line.long 0x0 "CFG_pll12_PID" bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0xC008++0x3 line.long 0x0 "CFG_pll12_CFG" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0xC010++0x7 line.long 0x0 "CFG_pll12_LOCKKEY0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition12 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll12_LOCKKEY1" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition12 registers" group.long 0xC020++0x3 line.long 0x0 "CFG_pll12_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1" rgroup.long 0xC024++0x3 line.long 0x0 "CFG_pll12_STAT" bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0xC030++0xB line.long 0x0 "CFG_pll12_FREQ_CTRL0" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll12_FREQ_CTRL1" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll12_DIV_CTRL" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0xC040++0x7 line.long 0x0 "CFG_pll12_SS_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "CFG_pll12_SS_SPREAD" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0xC060++0x3 line.long 0x0 "CFG_pll12_CAL_CTRL" bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1" bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1" bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1" hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0xC064++0x3 line.long 0x0 "CFG_pll12_CAL_STAT" bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" group.long 0xC080++0x3 line.long 0x0 "CFG_pll12_HSDIV_CTRL0" bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0xF000++0x3 line.long 0x0 "CFG_pll15_PID" bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0xF008++0x3 line.long 0x0 "CFG_pll15_CFG" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0xF010++0x7 line.long 0x0 "CFG_pll15_LOCKKEY0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition15 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll15_LOCKKEY1" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition15 registers" group.long 0xF020++0x3 line.long 0x0 "CFG_pll15_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1" rgroup.long 0xF024++0x3 line.long 0x0 "CFG_pll15_STAT" bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0xF030++0xB line.long 0x0 "CFG_pll15_FREQ_CTRL0" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll15_FREQ_CTRL1" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll15_DIV_CTRL" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0xF040++0x7 line.long 0x0 "CFG_pll15_SS_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "CFG_pll15_SS_SPREAD" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0xF060++0x3 line.long 0x0 "CFG_pll15_CAL_CTRL" bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1" bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1" bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1" hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0xF064++0x3 line.long 0x0 "CFG_pll15_CAL_STAT" bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" group.long 0xF080++0xB line.long 0x0 "CFG_pll15_HSDIV_CTRL0" bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll15_HSDIV_CTRL1" bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "CFG_pll15_HSDIV_CTRL2" bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" rgroup.long 0x11000++0x3 line.long 0x0 "CFG_pll17_PID" bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x11008++0x3 line.long 0x0 "CFG_pll17_CFG" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x11010++0x7 line.long 0x0 "CFG_pll17_LOCKKEY0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition17 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll17_LOCKKEY1" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition17 registers" group.long 0x11020++0x3 line.long 0x0 "CFG_pll17_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1" rgroup.long 0x11024++0x3 line.long 0x0 "CFG_pll17_STAT" bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x11030++0xB line.long 0x0 "CFG_pll17_FREQ_CTRL0" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll17_FREQ_CTRL1" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll17_DIV_CTRL" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x11040++0x7 line.long 0x0 "CFG_pll17_SS_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "CFG_pll17_SS_SPREAD" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x11060++0x3 line.long 0x0 "CFG_pll17_CAL_CTRL" bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1" bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1" bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1" hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x11064++0x3 line.long 0x0 "CFG_pll17_CAL_STAT" bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" group.long 0x11080++0x3 line.long 0x0 "CFG_pll17_HSDIV_CTRL0" bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" tree.end tree "PSC" base ad:0x0 tree "PSC0" base ad:0x400000 rgroup.long 0x0++0x3 line.long 0x0 "VBUS_PID,The peripheral identification register is a constant register that contains the ID and ID revision number for that module. The PID stores version information used to identify the module. All bits within this register are read-only (writes have.." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release" bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x7 line.long 0x0 "VBUS_GBLCTL,This register contains global control to PSC." hexmask.long.byte 0x0 8.--15. 1. "IO_ANA_CTL,General purpose IO/Analog PowerDown control. Directly drives io_ana_pdctl_po[7:0] outputs." line.long 0x4 "VBUS_GBLSTAT,This register shows the PSC global status." hexmask.long.word 0x4 16.--27. 1. "EF_SMRFLEX,Smart reflex class0 bits" bitfld.long 0x4 0. "OVRIDE,PSC Override Status" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "VBUS_INTEVAL,This register has no storage. Read from this register returns 0." bitfld.long 0x0 19. "GOSET,GOSTAT Interrupt Set" "0,1" bitfld.long 0x0 18. "EPCSET,External Power Control Interrupt Set" "0,1" bitfld.long 0x0 17. "ERRSET,Combined Interrupt Set" "0,1" newline bitfld.long 0x0 2. "EPCEV,External Power Control Interrupt Set" "0,1" bitfld.long 0x0 1. "ERREV,Re_evaluate Error Interrupt" "0,1" bitfld.long 0x0 0. "ALLEV,Re_evaluate combined PSC interrupt" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VBUS_MERRPR,This register records pending error conditions for all modules. Each bit represents one module (index 0 for modules 0-31. index 1 for modules 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "M,Records pending error conditions. Each bit n represents a module." group.long 0x50++0x3 line.long 0x0 "VBUS_MERRCR,This register has no storage. Read from this register returns 0. Each bit represents one module (index 0 for modules 0-31. index 1 for modules 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "M,Write of 1 clears the corresponding MERRPR bit." rgroup.long 0x60++0x3 line.long 0x0 "VBUS_PERRPR,This register records pending error conditions for each power domain. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "P,Power Domain n Error Condition. Each bit n represents a power domain." group.long 0x68++0x3 line.long 0x0 "VBUS_PERRCR,This register has no storage. Read from this register returns 0. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "P,Write of 1 clears the corresponding PERRPR bit." rgroup.long 0x70++0x3 line.long 0x0 "VBUS_EPCPR,This register records pending external power control conditions. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "EPC,External Power Control Intervention Request for Power Domain n" group.long 0x78++0x3 line.long 0x0 "VBUS_EPCCR,This register has no storage. Read from this register returns 0. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "EPC,Write of 1 clears the corresponding EPCPR bit" rgroup.long 0x100++0x3 line.long 0x0 "VBUS_RAILSTAT,This register is a read-only and shows the current rail requestor whose request is being granted and the current value of the counter associated with this requestor." hexmask.long.byte 0x0 24.--28. 1. "RAILNUM,Indicates Current Rail Requestor being processed by GPSC" hexmask.long.byte 0x0 0.--7. 1. "RAILCNT,Indicates the current rail counter value" group.long 0x104++0x7 line.long 0x0 "VBUS_RAILCTL,This register is user programmable. It holds the counter values for rail counter. User can select one of the two counter values to be used for each power domain (see RAILSEL register)." hexmask.long.byte 0x0 8.--15. 1. "RAILCTR1,Rail Counter Value 1" hexmask.long.byte 0x0 0.--7. 1. "RAILCTR0,Rail Counter Value 0" line.long 0x4 "VBUS_RAILSEL,User can use this register to select the counter value (RAILCTL) for each power domain." hexmask.long 0x4 0.--31. 1. "P,Rail Counter Select for Power Domain" group.long 0x120++0x3 line.long 0x0 "VBUS_PTCMD,This is a pseudo-command register with no actual storage. Reads return 0. One bit for each power domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "GO,Power Domain n GO Transition" rgroup.long 0x128++0x3 line.long 0x0 "VBUS_PTSTAT,This is a status register. One bit for each power domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "GOSTAT,Power Domain n Transition Command Status" rgroup.long 0x200++0x3 line.long 0x0 "VBUS_PDSTAT,This is a status register. One register per power domain. Each register contains the status for the given power domain." bitfld.long 0x0 11. "EMUIHB,Emulation Alters Domain State" "0,1" bitfld.long 0x0 10. "PWRBAD,Power Bad error" "0,1" bitfld.long 0x0 9. "PORDONE,POR Done Input Status" "0,1" newline bitfld.long 0x0 8. "PORZ,PORz output actual status" "0,1" hexmask.long.byte 0x0 0.--4. 1. "STATE,Current Power Domain State" group.long 0x300++0x3 line.long 0x0 "VBUS_PDCTL,This is a control register. One register per power domain." bitfld.long 0x0 31. "FORCE,Force Bit" "0,1" bitfld.long 0x0 29. "PWRSW,Power shorting Switch Control" "0,1" bitfld.long 0x0 28. "ISO,Isolation Cell control" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "WAKECNT,RAM wake count delay value" bitfld.long 0x0 12.--14. "PDMODE,Power Down mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. "EMUIHBIE,Emulation alters domain state" "0,1" newline bitfld.long 0x0 8. "EPCGOOD,External Power Control Power Good Indication" "0,1" bitfld.long 0x0 0. "NEXT,User_Desired Next Power Domain State" "0,1" rgroup.long 0x400++0x3 line.long 0x0 "VBUS_PDCFG,This is a status register. It shows PSC settings for easy debug." bitfld.long 0x0 3. "ICEPICK,Icepick support" "0,1" bitfld.long 0x0 1. "MEMSLPKWK,Memory sleep-wake domain" "0,1" bitfld.long 0x0 0. "ALWAYSON,Always on power domain" "0,1" rgroup.long 0x600++0x3 line.long 0x0 "VBUS_MDCFG,This is a constant register showing some PSC settings for easy debug. This register is read only." hexmask.long.byte 0x0 16.--20. 1. "PWRDOM,Indicates which power domain this module belongs to" bitfld.long 0x0 15. "AUTOONLY,0: This LPSC supports all modes 1: This LPSC supports Enable AutoSleep or AutoWake only" "0: This LPSC supports all modes,1: This LPSC supports Enable" bitfld.long 0x0 14. "RESETISO,0: This LPSC does not support Reset Isolation 1: This LPSC supports Reset Isolation" "0: This LPSC does not support Reset Isolation,1: This LPSC supports Reset Isolation" newline bitfld.long 0x0 13. "NEXTLOCK,0: MDCTL.NEXT field is writable 1: MDCTL.NEXT field is locked" "0: MDCTL,1: MDCTL" bitfld.long 0x0 12. "ASYNC,Async Lpsc" "0,1" bitfld.long 0x0 11. "ICEPICK,IcePick support" "0,1" newline bitfld.long 0x0 10. "PERMDIS,Permanently disable" "0,1" bitfld.long 0x0 9. "PLLHANDSHAKE,RTL parameter PLL_HANDSHAKE" "0,1" bitfld.long 0x0 6.--8. "NUMSCRDISBALE,Number of PWR_SCR_DISABLE interfaces required on LPSC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "NUMCLKEN,Number of PWR_CLK_EN interfaces required on LPSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "NUMCLK,Number of PWR_CLKSTOP interfaces required on LPSC" "0,1,2,3,4,5,6,7" rgroup.long 0x800++0x3 line.long 0x0 "VBUS_MDSTAT,This register shows the status of each module. Requires one register per module on the device." bitfld.long 0x0 17. "EMUIHB,Emulation Alters Module State. Inhibits Module Inactive or Force Module Active." "0,1" bitfld.long 0x0 16. "EMURST,Emulation Alters Reset" "0,1" bitfld.long 0x0 12. "MCKOUT,Actual modclk output to module" "0,1" newline bitfld.long 0x0 11. "MRSTDONE,Module reset initialization done status" "0,1" bitfld.long 0x0 10. "MRSTZ,Module reset actual status" "0,1" bitfld.long 0x0 9. "LRSTDONE,Module local reset initialization done status" "0,1" newline bitfld.long 0x0 8. "LRSTZ,Module local reset actual status" "0,1" hexmask.long.byte 0x0 0.--5. 1. "STATE,These bits indicate the current module state" group.long 0xA00++0x3 line.long 0x0 "VBUS_MDCTL,This register provides specific control for the individual module. One register per module on the device." bitfld.long 0x0 31. "FORCE,Force Bit" "0,1" bitfld.long 0x0 12. "RESETISO,Reset Isolation" "0,1" bitfld.long 0x0 11. "BLKCHIP1RST,Block Chip_1_Reset" "0,1" newline bitfld.long 0x0 10. "EMUIHBIE,Emulation Alters Module State. Inhibits Module Inactive or Force Module Active." "0,1" bitfld.long 0x0 9. "EMURSTIE,Emulation Alter Reset Interrupt Enable" "0,1" bitfld.long 0x0 8. "LRSTZ,Module local reset control" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "NEXT,Module Next State" tree.end tree "PSC0_ECC_AGGR_0_REGS" base ad:0x700400 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "TABLE_PEND,Interrupt Pending Status for table_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "TABLE_ENABLE_SET,Interrupt Enable Set Register for table_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "TABLE_ENABLE_CLR,Interrupt Enable Clear Register for table_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "TABLE_PEND,Interrupt Pending Status for table_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "TABLE_ENABLE_SET,Interrupt Enable Set Register for table_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "TABLE_ENABLE_CLR,Interrupt Enable Clear Register for table_pend" "0,1" group.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "PSC0_FW_0_FW" base ad:0x45020000 group.long 0x0++0xF line.long 0x0 "FW_REGS_dst_fwch_region_0_ch_0_control,The FW Region 0 Channel 0 Control Register defines the control fields for the slave slv0.slv region 0 channel 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_dst_fwch_region_0_ch_0_permission_0,The FW Region 0 Channel 0 Permission 0 Register defines the permissions for the slave slv0.slv region 0 channel 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_dst_fwch_region_0_ch_0_permission_1,The FW Region 0 Channel 0 Permission 1 Register defines the permissions for the slave slv0.slv region 0 channel 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_dst_fwch_region_0_ch_0_permission_2,The FW Region 0 Channel 0 Permission 2 Register defines the permissions for the slave slv0.slv region 0 channel 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" group.long 0x20++0xF line.long 0x0 "FW_REGS_dst_fwch_region_1_ch_0_control,The FW Region 1 Channel 0 Control Register defines the control fields for the slave slv0.slv region 1 channel 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_dst_fwch_region_1_ch_0_permission_0,The FW Region 1 Channel 0 Permission 0 Register defines the permissions for the slave slv0.slv region 1 channel 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_dst_fwch_region_1_ch_0_permission_1,The FW Region 1 Channel 0 Permission 1 Register defines the permissions for the slave slv0.slv region 1 channel 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_dst_fwch_region_1_ch_0_permission_2,The FW Region 1 Channel 0 Permission 2 Register defines the permissions for the slave slv0.slv region 1 channel 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" group.long 0x40++0xF line.long 0x0 "FW_REGS_dst_fwch_region_2_ch_0_control,The FW Region 2 Channel 0 Control Register defines the control fields for the slave slv0.slv region 2 channel 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_dst_fwch_region_2_ch_0_permission_0,The FW Region 2 Channel 0 Permission 0 Register defines the permissions for the slave slv0.slv region 2 channel 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_dst_fwch_region_2_ch_0_permission_1,The FW Region 2 Channel 0 Permission 1 Register defines the permissions for the slave slv0.slv region 2 channel 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_dst_fwch_region_2_ch_0_permission_2,The FW Region 2 Channel 0 Permission 2 Register defines the permissions for the slave slv0.slv region 2 channel 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" group.long 0x60++0xF line.long 0x0 "FW_REGS_dst_fwch_region_3_ch_0_control,The FW Region 3 Channel 0 Control Register defines the control fields for the slave slv0.slv region 3 channel 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_dst_fwch_region_3_ch_0_permission_0,The FW Region 3 Channel 0 Permission 0 Register defines the permissions for the slave slv0.slv region 3 channel 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_dst_fwch_region_3_ch_0_permission_1,The FW Region 3 Channel 0 Permission 1 Register defines the permissions for the slave slv0.slv region 3 channel 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_dst_fwch_region_3_ch_0_permission_2,The FW Region 3 Channel 0 Permission 2 Register defines the permissions for the slave slv0.slv region 3 channel 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" group.long 0x80++0xF line.long 0x0 "FW_REGS_dst_fwch_region_4_ch_0_control,The FW Region 4 Channel 0 Control Register defines the control fields for the slave slv0.slv region 4 channel 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_dst_fwch_region_4_ch_0_permission_0,The FW Region 4 Channel 0 Permission 0 Register defines the permissions for the slave slv0.slv region 4 channel 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_dst_fwch_region_4_ch_0_permission_1,The FW Region 4 Channel 0 Permission 1 Register defines the permissions for the slave slv0.slv region 4 channel 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_dst_fwch_region_4_ch_0_permission_2,The FW Region 4 Channel 0 Permission 2 Register defines the permissions for the slave slv0.slv region 4 channel 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" tree.end tree "PSC0_FW_0_GLB" base ad:0x45B09000 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end tree.end tree "PSRAMECC" base ad:0x0 tree "PSRAMECC0" tree "PSRAMECC0_ECC_AGGR" base ad:0x700000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" group.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end base ad:0x0 tree "PSRAMECC0_RAM" group.long 0x0++0x3 line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree.end tree "PSRAMECC1" tree "PSRAMECC1_ECC_AGGR" base ad:0x701000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1" group.long 0x200++0xF line.long 0x0 "REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "PSRAMECC1_RAM" base ad:0x900000 group.long 0x0++0x3 line.long 0x0 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage." hexmask.long.byte 0x0 24.--31. 1. "BYTE3,This is the MS byte" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,This is the UM byte" hexmask.long.byte 0x0 8.--15. 1. "BYTE1,This is the LM byte" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,This is the LS byte" tree.end tree.end tree.end tree "RTI" base ad:0x0 tree "RTI0_CFG" base ad:0xE000000 group.long 0x0++0x1B line.long 0x0 "CFG_GCTRL" hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL" bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL" bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL" bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0" hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0" hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." group.long 0x30++0xB line.long 0x0 "CFG_FRC1" hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1" hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." group.long 0x50++0x27 line.long 0x0 "CFG_COMP0" hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1" hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2" hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2" hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3" hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP" hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP" hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." group.long 0x80++0xB line.long 0x0 "CFG_SETINT" bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT" bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG" bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" group.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL" hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD" hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS" bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY" hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR" hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." group.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL" hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL" hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE" hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR" hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR" hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR" hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR" hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree "RTI1_CFG" base ad:0xE010000 group.long 0x0++0x1B line.long 0x0 "CFG_GCTRL" hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL" bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL" bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL" bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0" hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0" hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." group.long 0x30++0xB line.long 0x0 "CFG_FRC1" hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1" hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." group.long 0x50++0x27 line.long 0x0 "CFG_COMP0" hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1" hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2" hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2" hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3" hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP" hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP" hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." group.long 0x80++0xB line.long 0x0 "CFG_SETINT" bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT" bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG" bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" group.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL" hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD" hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS" bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY" hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR" hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." group.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL" hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL" hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE" hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR" hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR" hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR" hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR" hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree "RTI2_CFG" base ad:0xE020000 group.long 0x0++0x1B line.long 0x0 "CFG_GCTRL" hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL" bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL" bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL" bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0" hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0" hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." group.long 0x30++0xB line.long 0x0 "CFG_FRC1" hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1" hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." group.long 0x50++0x27 line.long 0x0 "CFG_COMP0" hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1" hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2" hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2" hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3" hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP" hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP" hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." group.long 0x80++0xB line.long 0x0 "CFG_SETINT" bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT" bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG" bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" group.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL" hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD" hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS" bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY" hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR" hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." group.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL" hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL" hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE" hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR" hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR" hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR" hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR" hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree "RTI3_CFG" base ad:0xE030000 group.long 0x0++0x1B line.long 0x0 "CFG_GCTRL" hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL" bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL" bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL" bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0" hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0" hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." group.long 0x30++0xB line.long 0x0 "CFG_FRC1" hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1" hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." group.long 0x50++0x27 line.long 0x0 "CFG_COMP0" hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1" hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2" hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2" hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3" hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP" hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP" hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." group.long 0x80++0xB line.long 0x0 "CFG_SETINT" bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT" bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG" bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" group.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL" hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD" hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS" bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY" hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR" hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." group.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL" hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL" hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE" hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR" hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR" hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR" hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR" hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree "RTI4_CFG" base ad:0xE040000 group.long 0x0++0x1B line.long 0x0 "CFG_GCTRL" hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL" bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL" bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL" bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0" hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0" hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." group.long 0x30++0xB line.long 0x0 "CFG_FRC1" hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1" hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." group.long 0x50++0x27 line.long 0x0 "CFG_COMP0" hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1" hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2" hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2" hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3" hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP" hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP" hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." group.long 0x80++0xB line.long 0x0 "CFG_SETINT" bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT" bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG" bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" group.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL" hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD" hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS" bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY" hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR" hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." group.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL" hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL" hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE" hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR" hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR" hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR" hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR" hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "SPINLOCK0" base ad:0x2A000000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module family." hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor revision. Y of X.Y.R.Z" group.long 0x10++0x3 line.long 0x0 "REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock" bitfld.long 0x0 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware. During reads it always returns 0 It has the same effect as the hardware reset Writing a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the.." "0,1" rgroup.long 0x14++0x3 line.long 0x0 "REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module" hexmask.long.byte 0x0 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32. e.g. For 256 spin locks this will return the number 0x08" bitfld.long 0x0 7. "IN_USE7,In-Use flag 7 covering lock registers 224 - 255. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 224 - 255 are in the Not Taken state Read 1 : At least one of the lock registers 224.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IN_USE6,In-Use flag 6 covering lock registers 192 - 223. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 192 - 223 are in the Not Taken state Read 1 : At least one of the lock registers 192.." "0: All lock registers 192,1: At least one of the lock registers 192" bitfld.long 0x0 5. "IN_USE5,In-Use flag 5 covering lock registers 160 - 191. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 160 - 191 are in the Not Taken state Read 1 : At least one of the lock registers 160.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IN_USE4,In-Use flag 4 covering lock registers 128 - 159. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 128 - 159 are in the Not Taken state Read 1 : At least one of the lock registers 128.." "0: All lock registers 128,1: At least one of the lock registers 128" bitfld.long 0x0 3. "IN_USE3,In-Use flag 3 covering lock registers 96 - 127. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 96 - 127 are in the Not Taken state Read 1 : At least one of the lock registers 96 -.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IN_USE2,In-Use flag 2 covering lock registers 64 - 95. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 64 - 95 are in the Not Taken state Read 1 : At least one of the lock registers 64 - 95.." "0: All lock registers 64,1: At least one of the lock registers 64" bitfld.long 0x0 1. "IN_USE1,In-Use flag 1 covering lock registers 32 - 63. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 32 - 63 are in the Not Taken state Read 1 : At least one of the lock registers 32 - 63.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IN_USE0,In-Use flag 0 covering lock registers 0 - 31. If no lock registers are implemented in this range then this flag always reads as 0 Read 0 : All lock registers 0 - 31 are in the Not Taken state Read 1 : At least one of the lock registers 0 - 31.." "0: All lock registers 0,1: At least one of the lock registers 0" group.long 0x800++0x3 line.long 0x0 "REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'" bitfld.long 0x0 0. "TAKEN,Lock Status Read 0 : Lock was previously free. The reader now has been granted the lock. Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry. Write 0 : Free the lock by setting TAKEN to zero. Write 1 : No.." "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "STM0" base ad:0x0 tree "STM0_CTI_CSCTI" base ad:0x73D201000 group.long 0x0++0x3 line.long 0x0 "CTI__CFG__CSCTI_CFG_CTICONTROL,The CTI Control Register enables the CTI. >" bitfld.long 0x0 0. "GLBEN,Enables or disables the ECT." "0,1" group.long 0x10++0x2F line.long 0x0 "CTI__CFG__CSCTI_CFG_CTIINTACK,The CTI Interrupt Acknowledge Register is write-only. Any bits written as a 1 cause the ctitrigout output signal to be acknowledged. The acknowledgement is cleared when MAPTRIGOUT is deactivated. This register is used when.." hexmask.long.byte 0x0 0.--7. 1. "INTACK,Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register the corresponding ctitrigout is acknowledged and is cleared when MAPTRIGOUT is LOW." line.long 0x4 "CTI__CFG__CSCTI_CFG_CTIAPPSET,The CTI Application Trigger Set Register is read/write. A write to this register causes a channel event to be raised. corresponding to the bit written to." hexmask.long.byte 0x4 0.--3. 1. "APPSET,Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel. Read : 0 = application trigger inactive (reset). 1 = application trigger active. Write : 0 = no effect. 1 = generate.." line.long 0x8 "CTI__CFG__CSCTI_CFG_CTIAPPCLEAR,The CTI Interrupt Acknowledge Register is write-only. A write to this register causes a channel event to be cleared. corresponding to the bit written to." hexmask.long.byte 0x8 0.--3. 1. "APPCLEAR,Clears corresponding bits in the CTIAPPSET register. There is one bit of the register for each channel. When a 1 is written to a bit in this register the corresponding application trigger is disabled in the CTIAPPSET register. Writing a 0 to.." line.long 0xC "CTI__CFG__CSCTI_CFG_CTIAPPPULSE,The CTI Application Pulse Register is write-only. A write to this register causes a channel event pulse. one cticlk period. to be generated. corresponding to the bit written to. The pulse external to the ECT can be.." hexmask.long.byte 0xC 0.--3. 1. "APPULSE,Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. When a 1 is written to a bit in this register a corresponding channel event pulse is generated for one cticlk.." line.long 0x10 "CTI__CFG__CSCTI_CFG_CTIINEN0,The CTI Trigger 0 to Channel Enable Register enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.." hexmask.long.byte 0x10 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register it enables the ctitrigin signal to generate.." line.long 0x14 "CTI__CFG__CSCTI_CFG_CTIINEN1,The CTI Trigger 1 to Channel Enable Register enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.." hexmask.long.byte 0x14 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register it enables the ctitrigin signal to generate.." line.long 0x18 "CTI__CFG__CSCTI_CFG_CTIINEN2,The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.." hexmask.long.byte 0x18 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register it enables the ctitrigin signal to generate.." line.long 0x1C "CTI__CFG__CSCTI_CFG_CTIINEN3,The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.." hexmask.long.byte 0x1C 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register it enables the ctitrigin signal to generate.." line.long 0x20 "CTI__CFG__CSCTI_CFG_CTIINEN4,The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.." hexmask.long.byte 0x20 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register it enables the ctitrigin signal to generate.." line.long 0x24 "CTI__CFG__CSCTI_CFG_CTIINEN5,The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.." hexmask.long.byte 0x24 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register it enables the ctitrigin signal to generate.." line.long 0x28 "CTI__CFG__CSCTI_CFG_CTIINEN6,The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.." hexmask.long.byte 0x28 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register it enables the ctitrigin signal to generate.." line.long 0x2C "CTI__CFG__CSCTI_CFG_CTIINEN7,The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI. Within this register there is one bit for each of the four channels.." hexmask.long.byte 0x2C 0.--3. 1. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register it enables the ctitrigin signal to generate.." group.long 0xA0++0x1F line.long 0x0 "CTI__CFG__CSCTI_CFG_CTIOUTEN0,The CTI Channel to Trigger 0 Enable Registers define which channels can generate a ctitrigout[0] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.." hexmask.long.byte 0x0 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[1] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.." line.long 0x4 "CTI__CFG__CSCTI_CFG_CTIOUTEN1,The CTI Channel to Trigger 1 Enable Registers define which channels can generate a ctitrigout[1] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.." hexmask.long.byte 0x4 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[1] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.." line.long 0x8 "CTI__CFG__CSCTI_CFG_CTIOUTEN2,The CTI Channel to Trigger 2 Enable Registers define which channels can generate a ctitrigout[2] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.." hexmask.long.byte 0x8 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[2] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.." line.long 0xC "CTI__CFG__CSCTI_CFG_CTIOUTEN3,The CTI Channel to Trigger 3 Enable Registers define which channels can generate a ctitrigout[3] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.." hexmask.long.byte 0xC 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[3] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.." line.long 0x10 "CTI__CFG__CSCTI_CFG_CTIOUTEN4,The CTI Channel to Trigger 4 Enable Registers define which channels can generate a ctitrigout[4] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.." hexmask.long.byte 0x10 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[4] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.." line.long 0x14 "CTI__CFG__CSCTI_CFG_CTIOUTEN5,The CTI Channel to Trigger 5 Enable Registers define which channels can generate a ctitrigout[5] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.." hexmask.long.byte 0x14 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[5] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.." line.long 0x18 "CTI__CFG__CSCTI_CFG_CTIOUTEN6,The CTI Channel to Trigger 6 Enable Registers define which channels can generate a ctitrigout[6] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.." hexmask.long.byte 0x18 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[6] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.." line.long 0x1C "CTI__CFG__CSCTI_CFG_CTIOUTEN7,The CTI Channel to Trigger 7 Enable Registers define which channels can generate a ctitrigout[7] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from.." hexmask.long.byte 0x1C 0.--3. 1. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[7] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this.." rgroup.long 0x130++0xF line.long 0x0 "CTI__CFG__CSCTI_CFG_CTITRIGINSTATUS,The CTI Trigger In Status Register provides the status of the ctitrigin inputs." hexmask.long.byte 0x0 0.--7. 1. "TRIGINSTATUS,Shows the status of the ctitrigin inputs. 1 = ctitrigin is active. 0 = ctitrigin is inactive. Because the register provides a view of the raw ctitrigin inputs the reset value is unknown. There is one bit of the field for each trigger.." line.long 0x4 "CTI__CFG__CSCTI_CFG_CTITRIGOUTSTATUS,The CTI Trigger Out Status Register provides the status of the ctitrigout outputs." hexmask.long.byte 0x4 0.--7. 1. "TRIGOUTSTATUS,Shows the status of the ctitrigout outputs. 1 = ctitrigout is active. 0 = ctitrigout is inactive. There is one bit of the field for each trigger output." line.long 0x8 "CTI__CFG__CSCTI_CFG_CTICHINSTATUS,The CTI Channel In Status Register provides the status of the ctichin inputs." hexmask.long.byte 0x8 0.--3. 1. "CTICHINSTATUS,Shows the status of the ctichin inputs. 1 = ctichin is active. 0 = ctichin is inactive. Because the register provides a view of the raw ctichin inputs the reset value is unknown. There is one bit of the field for each channel input." line.long 0xC "CTI__CFG__CSCTI_CFG_CTICHOUTSTATUS,The CTI Channel Out Status Register provides the status of the CTI ctichout outputs." hexmask.long.byte 0xC 0.--3. 1. "CTICHOUTSTATUS,Shows the status of the ctichout outputs. 1 = ctichout is active. 0 = ctichout is inactive. There is one bit of the field for each channel output." group.long 0x140++0x7 line.long 0x0 "CTI__CFG__CSCTI_CFG_CTIGATE,The Gate Enable Register prevents the channels from propagating through the CTM to other CTIs. This enables local cross-triggering. for example for causing an interrupt when the ETM trigger occurs. It can be used effectively.." bitfld.long 0x0 3. "CTIGATEEN3,Enable CTICHOUT3. Set to 0 to disable channel propagation." "0,1" bitfld.long 0x0 2. "CTIGATEEN2,Enable CTICHOUT2. Set to 0 to disable channel propagation." "0,1" newline bitfld.long 0x0 1. "CTIGATEEN1,Enable CTICHOUT1. Set to 0 to disable channel propagation." "0,1" bitfld.long 0x0 0. "CTIGATEEN0,Enable CTICHOUT0. Set to 0 to disable channel propagation." "0,1" line.long 0x4 "CTI__CFG__CSCTI_CFG_ASICCTL,Implementation-defined ASIC control. value written to the register is output on asicctl[7 : 0]." hexmask.long.byte 0x4 0.--7. 1. "ASICCTL,Implementation-defined ASIC control value written to the register is output on asicctl[7 : 0]. If external multiplexing of trigger signals is implemented then the number of multiplexed signals on each trigger must be reflected within the.." group.long 0xEDC++0xF line.long 0x0 "CTI__CFG__CSCTI_CFG_ITCHINACK,This register is a write-only register. It can be used to set the value of the CTCHINACK outputs." hexmask.long.byte 0x0 0.--3. 1. "CTCHINACK,Set the value of the CTCHINACK outputs." line.long 0x4 "CTI__CFG__CSCTI_CFG_ITTRIGINACK,This register is a write-only register. It can be used to set the value of the CTTRIGINACK outputs." hexmask.long.byte 0x4 0.--7. 1. "CTTRIGINACK,Set the value of the CTTRIGINACK outputs." line.long 0x8 "CTI__CFG__CSCTI_CFG_ITCHOUT,This register is a write-only register. It can be used to set the value of the CTCHOUT outputs." hexmask.long.byte 0x8 0.--3. 1. "CTCHOUT,Set the value of the CTCHOUT outputs." line.long 0xC "CTI__CFG__CSCTI_CFG_ITTRIGOUT,This register is a write-only register. It can be used to set the value of the CTTRIGOUT outputs." hexmask.long.byte 0xC 0.--7. 1. "CTTRIGOUT,Set the value of the CTTRIGOUT outputs." rgroup.long 0xEEC++0xF line.long 0x0 "CTI__CFG__CSCTI_CFG_ITCHOUTACK,This register is a read-only register. It can be used to read the values of the CTCHOUTACK inputs." hexmask.long.byte 0x0 0.--3. 1. "CTCHOUTACK,Read the values of the CTCHOUTACK inputs." line.long 0x4 "CTI__CFG__CSCTI_CFG_ITTRIGOUTACK,This register is a read-only register. It can be used to read the values of the CTTRIGOUTACK inputs." hexmask.long.byte 0x4 0.--7. 1. "CTTRIGOUTACK,Read the value of the CTTRIGOUTACK inputs." line.long 0x8 "CTI__CFG__CSCTI_CFG_ITCHIN,This register is a read-only register. It can be used to read the values of the CTCHIN inputs." hexmask.long.byte 0x8 0.--3. 1. "CTCHIN,Read the value of the CTCHIN inputs." line.long 0xC "CTI__CFG__CSCTI_CFG_ITTRIGIN,This register is a read-only register. It can be used to read the values of the CTTRIGIN inputs." hexmask.long.byte 0xC 0.--7. 1. "CTTRIGIN,Read the values of the CTTRIGIN inputs." group.long 0xF00++0x3 line.long 0x0 "CTI__CFG__CSCTI_CFG_ITCTRL,This register is used to enable topology detection. For more information see the CoreSight Architecture Specification. This register enables the component to switch from a functional mode. the default behavior. to integration.." bitfld.long 0x0 0. "INTEGRATION_MODE,Allows the component to switch from functional mode to integration mode or back." "0,1" group.long 0xFA0++0x7 line.long 0x0 "CTI__CFG__CSCTI_CFG_CLAIMSET,This is used in conjunction with Claim Tag Clear Register. CLAIMCLR. This register forms one half of the Claim Tag value. This location allows individual bits to be set. write. and returns the number of bits that can be set..." hexmask.long.byte 0x0 0.--3. 1. "CLAIMSET,This claim tag bit is implemented" line.long 0x4 "CTI__CFG__CSCTI_CFG_CLAIMCLR,This register is used in conjunction with Claim Tag Set Register. CLAIMSET. This register forms one half of the Claim Tag value. This location enables individual bits to be cleared. write. and returns the current Claim Tag.." hexmask.long.byte 0x4 0.--3. 1. "CLAIMCLR,The value present reflects the current setting of the Claim Tag." group.long 0xFB0++0x3 line.long 0x0 "CTI__CFG__CSCTI_CFG_LAR,This is used to enable write access to device registers. External accesses from a debugger (paddrdbg31 = 1) are not subject to the Lock Registers. A debugger does not have to unlock the component in order to write and modify the.." hexmask.long 0x0 0.--31. 1. "ACCESS_W,A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than 0xC5ACCE55 will have the affect of removing write access." rgroup.long 0xFB4++0x7 line.long 0x0 "CTI__CFG__CSCTI_CFG_LSR,This indicates the status of the Lock control mechanism. This lock prevents accidental writes by code under debug. When locked. write access is blocked to all registers. except the Lock Access Register. External accesses from a.." bitfld.long 0x0 2. "LOCKTYPE,Indicates if the Lock Access Register (0xFB0) is implemented as 8-bit or 32-bit" "0,1" bitfld.long 0x0 1. "LOCKGRANT,Returns the current status of the Lock. This bit reads as 0 when read from an external debugger (paddrdbg31 = 1) since external debugger accesses are not subject to Lock Registers." "0,1" newline bitfld.long 0x0 0. "LOCKEXIST,Indicates that a lock control mechanism exists for this device. This bit reads as 0 when read from an external debugger (paddrdbg31 = 1) since external debugger accesses are not subject to Lock Registers." "0,1" line.long 0x4 "CTI__CFG__CSCTI_CFG_AUTHSTATUS,Reports what functionality is currently permitted by the authentication interface." bitfld.long 0x4 6.--7. "SNID,Indicates the security level for secure non-invasive debug" "0,1,2,3" bitfld.long 0x4 4.--5. "SID,Indicates the security level for secure invasive debug" "0,1,2,3" newline bitfld.long 0x4 2.--3. "NSNID,Indicates the security level for non-secure non-invasive debug" "0,1,2,3" bitfld.long 0x4 0.--1. "NSID,Indicates the security level for non-secure invasive debug" "0,1,2,3" rgroup.long 0xFC8++0xB line.long 0x0 "CTI__CFG__CSCTI_CFG_DEVID,This register indicates the capabilities of the CTI." hexmask.long.byte 0x0 16.--19. 1. "NUMCH,Number of ECT channels available." hexmask.long.byte 0x0 8.--15. 1. "NUMTRIG,Number of ECT triggers available." newline hexmask.long.byte 0x0 0.--4. 1. "EXTMUXNUM,Indicates the number of multiplexing available on Trigger Inputs and Trigger Outputs using asicctl. Default value of 5'b00000 indicating no multiplexing present. Reflects the value of the Verilog define EXTMUXNUM that the user must alter.." line.long 0x4 "CTI__CFG__CSCTI_CFG_DEVTYPE,It provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information." hexmask.long.byte 0x4 4.--7. 1. "SUB_TYPE,Sub-classification within the major category" hexmask.long.byte 0x4 0.--3. 1. "MAJOR_TYPE,Major classification grouping for this debug/trace component" line.long 0x8 "CTI__CFG__CSCTI_CFG_PERIPHID4,Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator." hexmask.long.byte 0x8 4.--7. 1. "SIZE,This is a 4-bit value that indicates the total contiguous size of the memory window used by this component in powers of 2 from the standard 4KB. If a component only requires the standard 4KB then this should read as 0x0 4KB only for 8KB set to.." hexmask.long.byte 0x8 0.--3. 1. "DES_2,JEDEC continuation code indicating the designer of the component (along with the identity code)" rgroup.long 0xFE0++0x1F line.long 0x0 "CTI__CFG__CSCTI_CFG_PERIPHID0,Part of the set of Peripheral Identification registers. Contains part of the designer specific part number." hexmask.long.byte 0x0 0.--7. 1. "PART_0,Bits [7 : 0] of the component's part number. This is selected by the designer of the component." line.long 0x4 "CTI__CFG__CSCTI_CFG_PERIPHID1,Part of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity." hexmask.long.byte 0x4 4.--7. 1. "DES_0,Bits 3 : 0 of the JEDEC identity code indicating the designer of the component (along with the continuation code)" hexmask.long.byte 0x4 0.--3. 1. "PART_1,Bits [11 : 8] of the component's part number. This is selected by the designer of the component." line.long 0x8 "CTI__CFG__CSCTI_CFG_PERIPHID2,Part of the set of Peripheral Identification registers. Contains part of the designer identity and the product revision." hexmask.long.byte 0x8 4.--7. 1. "REVISION,The Revision field is an incremental value starting at 0x0 for the first design of this component. This only increases by 1 for both major and minor revisions and is simply used as a look-up to establish the exact major/minor revision." bitfld.long 0x8 3. "JEDEC,Always set. Indicates that a JEDEC assigned value is used" "0,1" newline bitfld.long 0x8 0.--2. "DES_1,Bits 6 : 4 of the JEDEC identity code indicating the designer of the component (along with the continuation code)" "?,?,?,?,?,?,6: 4 of the JEDEC identity code indicating the..,?" line.long 0xC "CTI__CFG__CSCTI_CFG_PERIPHID3,Part of the set of Peripheral Identification registers. Contains the RevAnd and Customer Modified fields." hexmask.long.byte 0xC 4.--7. 1. "REVAND,This field indicates minor errata fixes specific to this design for example metal fixes after implementation. In most cases this field is zero. It is recommended that component designers ensure this field can be changed by a metal fix if.." hexmask.long.byte 0xC 0.--3. 1. "CMOD,Where the component is reusable IP this value indicates if the customer has modified the behavior of the component. In most cases this field is zero." line.long 0x10 "CTI__CFG__CSCTI_CFG_COMPID0,Reserved Reserved Reserved A component identification register. that indicates that the identification registers are present." hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Contains bits [7 : 0] of the component identification" line.long 0x14 "CTI__CFG__CSCTI_CFG_COMPID1,A component identification register. that indicates that the identification registers are present. This register also indicates the component class." hexmask.long.byte 0x14 4.--7. 1. "CLASS,Class of the component. E.g. ROM table CoreSight component etc. Constitutes bits [15 : 12] of the component identification." hexmask.long.byte 0x14 0.--3. 1. "PRMBL_1,Contains bits [11 : 8] of the component identification" line.long 0x18 "CTI__CFG__CSCTI_CFG_COMPID2,A component identification register. that indicates that the identification registers are present." hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Contains bits [23 : 16] of the component identification" line.long 0x1C "CTI__CFG__CSCTI_CFG_COMPID3,A component identification register. that indicates that the identification registers are present." hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Contains bits [31 : 24] of the component identification" tree.end tree "STM0_CXSTM" base ad:0x73D200000 wgroup.long 0xC04++0x7 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDMASTARTR,This write-only register is used to start a DMA transfer.

A write of one when the DMA peripheral request interface is idle starts a DMA transfer. A write of zero has no effect. A write of one when the.." bitfld.long 0x0 0. "START" "0,1" line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDMASTOPR,This write-only register is used to stop a DMA transfer.

A write of one stops an active DMA transfer. A write of zero has no effect. A write of one when the DMA peripheral request interface is idle has.." bitfld.long 0x4 0. "STOP" "0,1" rgroup.long 0xC0C++0x3 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDMASTATR,This read-only register is used to determine the status of the DMA peripheral request interface." bitfld.long 0x0 0. "STATUS" "0,1" group.long 0xC10++0x3 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDMACTLR,Controls the DMA transfer request mechanism." bitfld.long 0x0 2.--3. "SENS" "0,1,2,3" rgroup.long 0xCFC++0x3 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDMAIDR,This read-only register indicates the DMA features of the STM" hexmask.long.byte 0x0 8.--11. 1. "VENDSPEC" hexmask.long.byte 0x0 4.--7. 1. "CLASSREV" hexmask.long.byte 0x0 0.--3. 1. "CLASS" group.long 0xD00++0x3 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEER,This read/write register is used to enable hardware events to generate trace.

The register defined one bit per hardware event. Writing 1 enables the appropriate hardware event. writing 0 disables the.." hexmask.long 0x0 0.--31. 1. "HEE" group.long 0xD20++0x3 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHETER,This register is used to enable trigger generation on hardware events." hexmask.long 0x0 0.--31. 1. "HETE" group.long 0xD60++0xB line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEBSR,This register is used to select the Hardware Event bank" bitfld.long 0x0 0. "HEBS" "0,1" line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEMCR,This register is used to control the primary functions of Hardware Event tracing." bitfld.long 0x4 7. "ATBTRIGEN" "0,1" bitfld.long 0x4 6. "TRIGCLEAR" "0,1" rbitfld.long 0x4 5. "TRIGSTATUS" "0,1" bitfld.long 0x4 4. "TRIGCTL" "0,1" newline rbitfld.long 0x4 2. "ERRDETECT" "0,1" bitfld.long 0x4 1. "COMPEN" "0,1" bitfld.long 0x4 0. "EN" "0,1" line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEEXTMUXR,This register is used to control hardware event multiplexors external to the STM" hexmask.long.byte 0x8 0.--7. 1. "EXTMUX" rgroup.long 0xDF4++0xB line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEMASTR,Indicates the STPv2 master number of hardware event trace. This number is the master number presented in STPv2." hexmask.long.word 0x0 0.--15. 1. "MASTER" line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEFEAT1R,Indicates the features of the STM." bitfld.long 0x4 28.--30. "HEEXTMUXSIZE" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 15.--23. 1. "NUMHE" bitfld.long 0x4 4.--5. "HECOMP" "0,1,2,3" bitfld.long 0x4 3. "HEMASTR" "0,1" newline bitfld.long 0x4 2. "HEERR" "0,1" bitfld.long 0x4 0. "HETER" "0,1" line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEIDR,Indicates the features of hardware event tracing in the STM." hexmask.long.byte 0x8 8.--11. 1. "VENDSPEC" hexmask.long.byte 0x8 4.--7. 1. "CLASSREV" hexmask.long.byte 0x8 0.--3. 1. "CLASS" group.long 0xE00++0x3 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPER,This read/write only register is used to enable the stimulus registers to generate trace.

The register defines one bit per stimulus register. Writing 1 enables the appropriate stimulus port. writing 0.." hexmask.long 0x0 0.--31. 1. "SPE" group.long 0xE20++0x3 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPTER,This register is used to enable trigger generation on writes to enabled stimulus port registers." hexmask.long 0x0 0.--31. 1. "SPTE" group.long 0xE60++0x13 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPSCR,This register allows a debugger to program which stimulus ports the STMSPER and STMSPTER apply to." hexmask.long.word 0x0 20.--31. 1. "PORTSEL" bitfld.long 0x0 0.--1. "PORTCTL" "0,1,2,3" line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPMSCR,This register allows a debugger to program which masters the STMSPSCR applies to." hexmask.long.byte 0x4 15.--22. 1. "MASTSEL" bitfld.long 0x4 0. "MASTCTL" "0,1" line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPOVERRIDER,This register allows a debugger to override various features of the STM." hexmask.long.tbyte 0x8 15.--31. 1. "PORTSEL" bitfld.long 0x8 2. "OVERTS" "0,1" bitfld.long 0x8 0.--1. "OVERCTL" "0,1,2,3" line.long 0xC "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPMOVERRIDER,This register allows a debugger to choose which masters the STMSPOVERRIDERR applies to." hexmask.long.byte 0xC 15.--22. 1. "MASTSEL" bitfld.long 0xC 0. "MASTCTL" "0,1" line.long 0x10 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPTRIGCSR,This register is used to control the STM triggers caused by STMSPTER." bitfld.long 0x10 4. "ATBTRIGEN_DIR" "0,1" bitfld.long 0x10 3. "ATBTRIGEN_TE" "0,1" bitfld.long 0x10 2. "TRIGCLEAR" "0,1" rbitfld.long 0x10 1. "TRIGSTATUS" "0,1" newline bitfld.long 0x10 0. "TRIGCTL" "0,1" group.long 0xE80++0x3 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMTCSR,Controls the STM settings." rbitfld.long 0x0 23. "BUSY" "0,1" hexmask.long.byte 0x0 16.--22. 1. "TRACEID" bitfld.long 0x0 5. "COMPEN" "0,1" rbitfld.long 0x0 2. "SYNCEN" "0,1" newline bitfld.long 0x0 1. "TSEN" "0,1" bitfld.long 0x0 0. "EN" "0,1" wgroup.long 0xE84++0x3 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMTSSTIMR,This write-only register is used to force the next packet caused by a stimulus port write to have a timestamp output." bitfld.long 0x0 0. "FORCETS" "0,1" group.long 0xE8C++0xB line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMTSFREQR,This read-write register is used to indicate the frequency of the timestamp counter. The unit of measurement is increments per second. When the STPv2 protocol is used. this register contains the value output.." hexmask.long 0x0 0.--31. 1. "FREQ" line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSYNCR,This register controls the interval between synchronization packets. in terms of the number of bytes of trace generated.

This register only provides a hint of the desired synchronization frequency..." bitfld.long 0x4 12. "MODE" "0,1" hexmask.long.word 0x4 3.--11. 1. "COUNT" line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMAUXCR,Used for IMPLEMENTATION DEFINED STM controls." bitfld.long 0x8 7. "QHWEVOVERRIDE" "0,1" bitfld.long 0x8 2. "PRIORINVDIS" "0,1" bitfld.long 0x8 1. "ASYNCPE" "0,1" bitfld.long 0x8 0. "FIFOAF" "0,1" rgroup.long 0xEA0++0xB line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMFEAT1R,Indicates the features of the STM." bitfld.long 0x0 22.--23. "SWOEN" "0,1,2,3" bitfld.long 0x0 20.--21. "SYNCEN" "0,1,2,3" bitfld.long 0x0 18.--19. "HWTEN" "0,1,2,3" bitfld.long 0x0 16.--17. "TSPRESCALE" "0,1,2,3" newline bitfld.long 0x0 14.--15. "TRIGCTL" "0,1,2,3" hexmask.long.byte 0x0 10.--13. 1. "TRACEBUS" bitfld.long 0x0 8.--9. "SYNC" "0,1,2,3" bitfld.long 0x0 7. "FORCETS" "0,1" newline bitfld.long 0x0 6. "TSFREQ" "0,1" bitfld.long 0x0 4.--5. "TS" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "PROT" line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMFEAT2R,Indicates the features of the STM." bitfld.long 0x4 16.--17. "SPTYPE" "0,1,2,3" hexmask.long.byte 0x4 12.--15. 1. "DSIZE" bitfld.long 0x4 9.--10. "SPTRTYPE" "0,1,2,3" bitfld.long 0x4 7.--8. "PRIVMASK" "0,1,2,3" newline bitfld.long 0x4 6. "SPOVERRIDE" "0,1" bitfld.long 0x4 4.--5. "SPCOMP" "0,1,2,3" bitfld.long 0x4 2. "SPER" "0,1" bitfld.long 0x4 0.--1. "SPTER" "0,1,2,3" line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMFEAT3R,Indicates the features of the STM." hexmask.long.byte 0x8 0.--6. 1. "NUMMAST" wgroup.long 0xEE8++0x7 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITTRIGGER,Integration Test for Cross-Trigger Outputs Register" bitfld.long 0x0 3. "ASYNCOUT_W" "0,1" bitfld.long 0x0 2. "TRIGOUTHETE_W" "0,1" bitfld.long 0x0 1. "TRIGOUTSW_W" "0,1" bitfld.long 0x0 0. "TRIGOUTSPTE_W" "0,1" line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITATBDATA0,Controls the value of the ATDATAM output in integration mode:" bitfld.long 0x4 8. "ATDATAM63_W" "0,1" bitfld.long 0x4 7. "ATDATAM55_W" "0,1" bitfld.long 0x4 6. "ATDATAM47_W" "0,1" bitfld.long 0x4 5. "ATDATAM39_W" "0,1" newline bitfld.long 0x4 4. "ATDATAM31_W" "0,1" bitfld.long 0x4 3. "ATDATAM23_W" "0,1" bitfld.long 0x4 2. "ATDATAM15_W" "0,1" bitfld.long 0x4 1. "ATDATAM7_W" "0,1" newline bitfld.long 0x4 0. "ATDATAM0_W" "0,1" rgroup.long 0xEF0++0x3 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITATBCTR2,Returns the value of the ATREADYM and AFVALIDM inputs in integration mode." bitfld.long 0x0 1. "AFVALIDM_R" "0,1" bitfld.long 0x0 0. "ATREADYM_R" "0,1" wgroup.long 0xEF4++0x7 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITATBID,Controls the value of the ATIDM output in integration mode." hexmask.long.byte 0x0 0.--6. 1. "ATIDM_W" line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITATBCTR0,Controls the value of the ATVALIDM. AFREADYM. and ATBYTESM outputs in integration mode." bitfld.long 0x4 8.--10. "ATBYTESM_W" "0,1,2,3,4,5,6,7" bitfld.long 0x4 1. "AFREADYM_W" "0,1" bitfld.long 0x4 0. "ATVALIDM_W" "0,1" group.long 0xF00++0x3 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITCTRL,Used to enable topology detection. See the CoreSight Architecture Specification for more information. This register enables the component to switch between functional mode and integration mode. The default.." bitfld.long 0x0 0. "IME" "0,1" rgroup.long 0xFA0++0x7 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCLAIMSET,This is used in conjunction with Claim Tag Clear Register. STMCLAIMCLR. This register forms one half of the Claim Tag value. This location allows individual bits to be set. write. and returns the number of.." hexmask.long.byte 0x0 0.--3. 1. "SET" line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCLAIMCLR,This register is used in conjunction with Claim Tag Set Register. STMCLAIMSET. This register forms one half of the Claim Tag value. This location enables individual bits to be cleared. write. and returns.." hexmask.long.byte 0x4 0.--3. 1. "CLR" wgroup.long 0xFB0++0x3 line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMLAR,Enables write access to device registers." hexmask.long 0x0 0.--31. 1. "KEY" rgroup.long 0xFB4++0xB line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMLSR,Indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. The lock mechanism does not impact accesses to the extended stimulus port registers. This register.." bitfld.long 0x0 2. "NTT" "0,1" bitfld.long 0x0 1. "SLK" "0,1" bitfld.long 0x0 0. "SLI" "0,1" line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMAUTHSTATUS,Reports the required security level and current status of the authentication interface." bitfld.long 0x4 6.--7. "SNID" "0,1,2,3" bitfld.long 0x4 4.--5. "SID" "0,1,2,3" bitfld.long 0x4 2.--3. "NSNID" "0,1,2,3" bitfld.long 0x4 0.--1. "NSID" "0,1,2,3" line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDEVARCH,Indicates the architect and architecture of the STM. For the STM-500. the architect is ARM. and the architecture is STMv1.1" hexmask.long.word 0x8 21.--31. 1. "ARCHITECT" bitfld.long 0x8 20. "PRESENT" "0,1" hexmask.long.byte 0x8 16.--19. 1. "REVISION" hexmask.long.word 0x8 0.--14. 1. "ARCHID" rgroup.long 0xFC8++0xB line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDEVID,Indicates the capabilities of the CoreSight STM." hexmask.long.tbyte 0x0 0.--16. 1. "NUMSP" line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDEVTYPE,Provides a debugger with information about the component when the part number is not recognized. The debugger can then report this information." hexmask.long.byte 0x4 4.--7. 1. "SUB" hexmask.long.byte 0x4 0.--3. 1. "MAJOR" line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR4,Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator." hexmask.long.byte 0x8 4.--7. 1. "SIZE" hexmask.long.byte 0x8 0.--3. 1. "DES_2" group.long 0xFD4++0xB line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR5,Reserved" line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR6,Reserved" line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR7,Reserved" rgroup.long 0xFE0++0x1F line.long 0x0 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR0,Part of the set of Peripheral Identification registers. Contains part of the designer specific part number." hexmask.long.byte 0x0 0.--7. 1. "PART_0" line.long 0x4 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR1,Part of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity." hexmask.long.byte 0x4 4.--7. 1. "DES_0" hexmask.long.byte 0x4 0.--3. 1. "PART_1" line.long 0x8 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR2,Part of the set of Peripheral Identification registers. Contains part of the designer identity and the product revision." hexmask.long.byte 0x8 4.--7. 1. "REVISION" bitfld.long 0x8 3. "JEDEC" "0,1" bitfld.long 0x8 0.--2. "DES_1" "0,1,2,3,4,5,6,7" line.long 0xC "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR3,Part of the set of Peripheral Identification registers. Contains the RevAnd and Customer_Modified bit fields." hexmask.long.byte 0xC 4.--7. 1. "REVAND" hexmask.long.byte 0xC 0.--3. 1. "CMOD" line.long 0x10 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCIDR0,A component identification register. that indicates that the identification registers are present." hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0" line.long 0x14 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCIDR1,A component identification register. that indicates that the identification registers are present. This register also indicates the component class." hexmask.long.byte 0x14 4.--7. 1. "CLASS" hexmask.long.byte 0x14 0.--3. 1. "PRMBL_1" line.long 0x18 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCIDR2,A component identification register. that indicates that the identification registers are present." hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2" line.long 0x1C "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCIDR3,A component identification register. that indicates that the identification registers are present." hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3" tree.end tree.end tree "TIMER" base ad:0x0 tree "TIMER0_CFG" base ad:0x2400000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" group.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" group.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" group.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" group.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER1_CFG" base ad:0x2410000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" group.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" group.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" group.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" group.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER2_CFG" base ad:0x2420000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" group.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" group.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" group.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" group.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER3_CFG" base ad:0x2430000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" group.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" group.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" group.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" group.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER4_CFG" base ad:0x2440000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" group.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" group.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" group.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" group.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER5_CFG" base ad:0x2450000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" group.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" group.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" group.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" group.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER6_CFG" base ad:0x2460000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" group.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" group.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" group.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" group.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree "TIMER7_CFG" base ad:0x2470000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" group.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" group.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" group.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" group.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end tree.end tree "TIMESYNC_EVENT_ROUTER0_INTR_ROUTER_CFG" base ad:0xA40000 rgroup.long 0x0++0x3 line.long 0x0 "INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.byte 0x0 0.--4. 1. "MUX_CNTL,Mux control for interrupt N" tree.end tree "UART" base ad:0x0 tree "UART0" base ad:0x2800000 group.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "NOT_USED1" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" newline bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" group.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE" newline bitfld.long 0x0 0. "IT_PENDING" "0,1" group.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" newline bitfld.long 0x0 3. "PARITY_EN" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR" "0,1" newline bitfld.long 0x4 5. "XON_EN" "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN" "0,1" newline bitfld.long 0x4 3. "CD_STS_CH" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH" "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR" "0,1" group.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL" "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE" "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG" "0,1" newline bitfld.long 0x0 3. "ABORT" "0,1" newline bitfld.long 0x0 2. "CRC" "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "RX_FIFO_STS" "0,1" newline bitfld.long 0x0 6. "TX_SR_E" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E" "0,1" newline bitfld.long 0x0 4. "RX_BI" "0,1" newline bitfld.long 0x0 3. "RX_FE" "0,1" newline bitfld.long 0x0 2. "RX_PE" "0,1" newline bitfld.long 0x0 1. "RX_OE" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" group.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT" "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 5.--7. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR" "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR" "0,1" newline bitfld.long 0x0 0. "RESERVED0" "0,1" group.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." group.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "RX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 5. "DSR_IT" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE" "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL" "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST" "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL" "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY" "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL" line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL" group.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS" "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1" newline rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1" newline rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART1" base ad:0x2810000 group.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "NOT_USED1" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" newline bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" group.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE" newline bitfld.long 0x0 0. "IT_PENDING" "0,1" group.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" newline bitfld.long 0x0 3. "PARITY_EN" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR" "0,1" newline bitfld.long 0x4 5. "XON_EN" "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN" "0,1" newline bitfld.long 0x4 3. "CD_STS_CH" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH" "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR" "0,1" group.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL" "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE" "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG" "0,1" newline bitfld.long 0x0 3. "ABORT" "0,1" newline bitfld.long 0x0 2. "CRC" "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "RX_FIFO_STS" "0,1" newline bitfld.long 0x0 6. "TX_SR_E" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E" "0,1" newline bitfld.long 0x0 4. "RX_BI" "0,1" newline bitfld.long 0x0 3. "RX_FE" "0,1" newline bitfld.long 0x0 2. "RX_PE" "0,1" newline bitfld.long 0x0 1. "RX_OE" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" group.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT" "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 5.--7. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR" "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR" "0,1" newline bitfld.long 0x0 0. "RESERVED0" "0,1" group.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." group.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "RX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 5. "DSR_IT" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE" "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL" "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST" "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL" "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY" "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL" line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL" group.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS" "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1" newline rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1" newline rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART2" base ad:0x2820000 group.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "NOT_USED1" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" newline bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" group.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE" newline bitfld.long 0x0 0. "IT_PENDING" "0,1" group.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" newline bitfld.long 0x0 3. "PARITY_EN" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR" "0,1" newline bitfld.long 0x4 5. "XON_EN" "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN" "0,1" newline bitfld.long 0x4 3. "CD_STS_CH" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH" "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR" "0,1" group.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL" "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE" "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG" "0,1" newline bitfld.long 0x0 3. "ABORT" "0,1" newline bitfld.long 0x0 2. "CRC" "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "RX_FIFO_STS" "0,1" newline bitfld.long 0x0 6. "TX_SR_E" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E" "0,1" newline bitfld.long 0x0 4. "RX_BI" "0,1" newline bitfld.long 0x0 3. "RX_FE" "0,1" newline bitfld.long 0x0 2. "RX_PE" "0,1" newline bitfld.long 0x0 1. "RX_OE" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" group.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT" "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 5.--7. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR" "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR" "0,1" newline bitfld.long 0x0 0. "RESERVED0" "0,1" group.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." group.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "RX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 5. "DSR_IT" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE" "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL" "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST" "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL" "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY" "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL" line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL" group.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS" "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1" newline rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1" newline rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART3" base ad:0x2830000 group.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "NOT_USED1" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" newline bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" group.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE" newline bitfld.long 0x0 0. "IT_PENDING" "0,1" group.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" newline bitfld.long 0x0 3. "PARITY_EN" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR" "0,1" newline bitfld.long 0x4 5. "XON_EN" "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN" "0,1" newline bitfld.long 0x4 3. "CD_STS_CH" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH" "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR" "0,1" group.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL" "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE" "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG" "0,1" newline bitfld.long 0x0 3. "ABORT" "0,1" newline bitfld.long 0x0 2. "CRC" "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "RX_FIFO_STS" "0,1" newline bitfld.long 0x0 6. "TX_SR_E" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E" "0,1" newline bitfld.long 0x0 4. "RX_BI" "0,1" newline bitfld.long 0x0 3. "RX_FE" "0,1" newline bitfld.long 0x0 2. "RX_PE" "0,1" newline bitfld.long 0x0 1. "RX_OE" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" group.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT" "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 5.--7. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR" "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR" "0,1" newline bitfld.long 0x0 0. "RESERVED0" "0,1" group.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." group.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "RX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 5. "DSR_IT" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE" "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL" "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST" "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL" "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY" "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL" line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL" group.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS" "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1" newline rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1" newline rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART4" base ad:0x2840000 group.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "NOT_USED1" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" newline bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" group.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE" newline bitfld.long 0x0 0. "IT_PENDING" "0,1" group.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" newline bitfld.long 0x0 3. "PARITY_EN" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR" "0,1" newline bitfld.long 0x4 5. "XON_EN" "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN" "0,1" newline bitfld.long 0x4 3. "CD_STS_CH" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH" "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR" "0,1" group.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL" "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE" "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG" "0,1" newline bitfld.long 0x0 3. "ABORT" "0,1" newline bitfld.long 0x0 2. "CRC" "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "RX_FIFO_STS" "0,1" newline bitfld.long 0x0 6. "TX_SR_E" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E" "0,1" newline bitfld.long 0x0 4. "RX_BI" "0,1" newline bitfld.long 0x0 3. "RX_FE" "0,1" newline bitfld.long 0x0 2. "RX_PE" "0,1" newline bitfld.long 0x0 1. "RX_OE" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" group.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT" "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 5.--7. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR" "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR" "0,1" newline bitfld.long 0x0 0. "RESERVED0" "0,1" group.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." group.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "RX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 5. "DSR_IT" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE" "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL" "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST" "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL" "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY" "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL" line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL" group.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS" "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1" newline rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1" newline rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART5" base ad:0x2850000 group.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "NOT_USED1" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" newline bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" group.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE" newline bitfld.long 0x0 0. "IT_PENDING" "0,1" group.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" newline bitfld.long 0x0 3. "PARITY_EN" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR" "0,1" newline bitfld.long 0x4 5. "XON_EN" "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN" "0,1" newline bitfld.long 0x4 3. "CD_STS_CH" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH" "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR" "0,1" group.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL" "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE" "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG" "0,1" newline bitfld.long 0x0 3. "ABORT" "0,1" newline bitfld.long 0x0 2. "CRC" "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "RX_FIFO_STS" "0,1" newline bitfld.long 0x0 6. "TX_SR_E" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E" "0,1" newline bitfld.long 0x0 4. "RX_BI" "0,1" newline bitfld.long 0x0 3. "RX_FE" "0,1" newline bitfld.long 0x0 2. "RX_PE" "0,1" newline bitfld.long 0x0 1. "RX_OE" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" group.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT" "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 5.--7. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR" "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR" "0,1" newline bitfld.long 0x0 0. "RESERVED0" "0,1" group.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." group.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "RX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 5. "DSR_IT" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE" "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL" "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST" "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL" "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY" "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL" line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL" group.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS" "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1" newline rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1" newline rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART6" base ad:0x2860000 group.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "NOT_USED1" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" newline bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" group.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE" newline bitfld.long 0x0 0. "IT_PENDING" "0,1" group.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" newline bitfld.long 0x0 3. "PARITY_EN" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR" "0,1" newline bitfld.long 0x4 5. "XON_EN" "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN" "0,1" newline bitfld.long 0x4 3. "CD_STS_CH" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH" "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR" "0,1" group.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL" "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE" "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG" "0,1" newline bitfld.long 0x0 3. "ABORT" "0,1" newline bitfld.long 0x0 2. "CRC" "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "RX_FIFO_STS" "0,1" newline bitfld.long 0x0 6. "TX_SR_E" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E" "0,1" newline bitfld.long 0x0 4. "RX_BI" "0,1" newline bitfld.long 0x0 3. "RX_FE" "0,1" newline bitfld.long 0x0 2. "RX_PE" "0,1" newline bitfld.long 0x0 1. "RX_OE" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" group.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT" "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 5.--7. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR" "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR" "0,1" newline bitfld.long 0x0 0. "RESERVED0" "0,1" group.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." group.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "RX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 5. "DSR_IT" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE" "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL" "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST" "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL" "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY" "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL" line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL" group.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS" "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1" newline rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1" newline rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "VPAC" base ad:0x0 tree "VPAC0_ECC_AGGR_0_IVPAC_TOP_0_CFG_SLV_KSDW_ECC_AGGR_CFG" base ad:0x2B604000 rgroup.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "UTC0_DRU_RING_MEMORY_ECC_PEND,Interrupt Pending Status for utc0_dru_ring_memory_ecc_pend" "0,1" newline bitfld.long 0x4 4. "UTC0_DRU_STATE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_dru_state_buffer0_ecc_pend" "0,1" newline bitfld.long 0x4 3. "UTC0_DRU_QUEUE_BUFFER2_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer2_ecc_pend" "0,1" newline bitfld.long 0x4 2. "UTC0_DRU_QUEUE_BUFFER1_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x4 1. "UTC0_DRU_QUEUE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x4 0. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "UTC0_DRU_RING_MEMORY_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_ring_memory_ecc_pend" "0,1" newline bitfld.long 0x0 4. "UTC0_DRU_STATE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_state_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 3. "UTC0_DRU_QUEUE_BUFFER2_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer2_ecc_pend" "0,1" newline bitfld.long 0x0 2. "UTC0_DRU_QUEUE_BUFFER1_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x0 1. "UTC0_DRU_QUEUE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 0. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "UTC0_DRU_RING_MEMORY_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_ring_memory_ecc_pend" "0,1" newline bitfld.long 0x0 4. "UTC0_DRU_STATE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_state_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 3. "UTC0_DRU_QUEUE_BUFFER2_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer2_ecc_pend" "0,1" newline bitfld.long 0x0 2. "UTC0_DRU_QUEUE_BUFFER1_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x0 1. "UTC0_DRU_QUEUE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 0. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 5. "UTC0_DRU_RING_MEMORY_ECC_PEND,Interrupt Pending Status for utc0_dru_ring_memory_ecc_pend" "0,1" newline bitfld.long 0x4 4. "UTC0_DRU_STATE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_dru_state_buffer0_ecc_pend" "0,1" newline bitfld.long 0x4 3. "UTC0_DRU_QUEUE_BUFFER2_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer2_ecc_pend" "0,1" newline bitfld.long 0x4 2. "UTC0_DRU_QUEUE_BUFFER1_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x4 1. "UTC0_DRU_QUEUE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x4 0. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_PEND,Interrupt Pending Status for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 5. "UTC0_DRU_RING_MEMORY_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_ring_memory_ecc_pend" "0,1" newline bitfld.long 0x0 4. "UTC0_DRU_STATE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_state_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 3. "UTC0_DRU_QUEUE_BUFFER2_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer2_ecc_pend" "0,1" newline bitfld.long 0x0 2. "UTC0_DRU_QUEUE_BUFFER1_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x0 1. "UTC0_DRU_QUEUE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 0. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_SET,Interrupt Enable Set Register for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 5. "UTC0_DRU_RING_MEMORY_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_ring_memory_ecc_pend" "0,1" newline bitfld.long 0x0 4. "UTC0_DRU_STATE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_state_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 3. "UTC0_DRU_QUEUE_BUFFER2_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer2_ecc_pend" "0,1" newline bitfld.long 0x0 2. "UTC0_DRU_QUEUE_BUFFER1_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer1_ecc_pend" "0,1" newline bitfld.long 0x0 1. "UTC0_DRU_QUEUE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_dru_queue_buffer0_ecc_pend" "0,1" newline bitfld.long 0x0 0. "UTC0_TPRAM_DRU_RESPONSE_BUFFER0_ECC_ENABLE_CLR,Interrupt Enable Clear Register for utc0_tpram_dru_response_buffer0_ecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "IVPAC_TOP_0__CFG_SLV__KSDW_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "VPAC0_LDC0_ECC_AGGR_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_LDC0_S_VBUSP_KSDW_ECC_AGGR_CFG" base ad:0x2B607000 rgroup.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 11. "MESHMEM_B3_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b3_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "MESHMEM_B2_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b2_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "MESHMEM_B1_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b1_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "MESHMEM_B0_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b0_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "MESHMEM_B3_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b3_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "MESHMEM_B2_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b2_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "MESHMEM_B1_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b1_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "MESHMEM_B0_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b0_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "DUALC_LUT_B1_RAMECC_PEND,Interrupt Pending Status for dualc_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "DUALC_LUT_B0_RAMECC_PEND,Interrupt Pending Status for dualc_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "DUALY_LUT_B1_RAMECC_PEND,Interrupt Pending Status for dualy_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "DUALY_LUT_B0_RAMECC_PEND,Interrupt Pending Status for dualy_lut_b0_ramecc_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 11. "MESHMEM_B3_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b3_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "MESHMEM_B2_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b2_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "MESHMEM_B1_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b1_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "MESHMEM_B0_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b0_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "MESHMEM_B3_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b3_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "MESHMEM_B2_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b2_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "MESHMEM_B1_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b1_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "MESHMEM_B0_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b0_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "DUALC_LUT_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualc_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "DUALC_LUT_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualc_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "DUALY_LUT_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualy_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "DUALY_LUT_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualy_lut_b0_ramecc_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 11. "MESHMEM_B3_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b3_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "MESHMEM_B2_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b2_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "MESHMEM_B1_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b1_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "MESHMEM_B0_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b0_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "MESHMEM_B3_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b3_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "MESHMEM_B2_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b2_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "MESHMEM_B1_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b1_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "MESHMEM_B0_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b0_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "DUALC_LUT_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualc_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "DUALC_LUT_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualc_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "DUALY_LUT_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualy_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "DUALY_LUT_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualy_lut_b0_ramecc_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 11. "MESHMEM_B3_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b3_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "MESHMEM_B2_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b2_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "MESHMEM_B1_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b1_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "MESHMEM_B0_P1_RAMECC_PEND,Interrupt Pending Status for meshmem_b0_p1_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "MESHMEM_B3_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b3_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "MESHMEM_B2_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b2_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "MESHMEM_B1_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b1_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "MESHMEM_B0_P0_RAMECC_PEND,Interrupt Pending Status for meshmem_b0_p0_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "DUALC_LUT_B1_RAMECC_PEND,Interrupt Pending Status for dualc_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "DUALC_LUT_B0_RAMECC_PEND,Interrupt Pending Status for dualc_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "DUALY_LUT_B1_RAMECC_PEND,Interrupt Pending Status for dualy_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "DUALY_LUT_B0_RAMECC_PEND,Interrupt Pending Status for dualy_lut_b0_ramecc_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 11. "MESHMEM_B3_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b3_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "MESHMEM_B2_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b2_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "MESHMEM_B1_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b1_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "MESHMEM_B0_P1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b0_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "MESHMEM_B3_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b3_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "MESHMEM_B2_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b2_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "MESHMEM_B1_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b1_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "MESHMEM_B0_P0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshmem_b0_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "DUALC_LUT_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualc_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "DUALC_LUT_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualc_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "DUALY_LUT_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualy_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "DUALY_LUT_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dualy_lut_b0_ramecc_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 11. "MESHMEM_B3_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b3_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "MESHMEM_B2_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b2_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "MESHMEM_B1_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b1_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "MESHMEM_B0_P1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b0_p1_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "MESHMEM_B3_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b3_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "MESHMEM_B2_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b2_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "MESHMEM_B1_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b1_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "MESHMEM_B0_P0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshmem_b0_p0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "DUALC_LUT_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualc_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "DUALC_LUT_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualc_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "DUALY_LUT_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualy_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "DUALY_LUT_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dualy_lut_b0_ramecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "VPAC0_VISS0_ECC_AGGR_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_KSDW_ECC_AGGR_CFG" base ad:0x2B605000 rgroup.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_misc_status,Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x10++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets." hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data" group.long 0x3C++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "FCC_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "FCC_LUT0_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "FCC_LUT0_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "FCC_CONT_LUT3_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "FCC_CONT_LUT3_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut3_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "FCC_CONT_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "FCC_CONT_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "FCC_CONT_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "FCC_CONT_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "FCC_HIST_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "FCC_HIST_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "STAT_MEM7_RAMECC_PEND,Interrupt Pending Status for stat_mem7_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "STAT_MEM6_RAMECC_PEND,Interrupt Pending Status for stat_mem6_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "STAT_MEM5_RAMECC_PEND,Interrupt Pending Status for stat_mem5_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "STAT_MEM4_RAMECC_PEND,Interrupt Pending Status for stat_mem4_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "STAT_MEM3_RAMECC_PEND,Interrupt Pending Status for stat_mem3_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "STAT_MEM2_RAMECC_PEND,Interrupt Pending Status for stat_mem2_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "STAT_MEM1_RAMECC_PEND,Interrupt Pending Status for stat_mem1_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "STAT_MEM0_RAMECC_PEND,Interrupt Pending Status for stat_mem0_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "DPC_STATS_RAM_RAMECC_PEND,Interrupt Pending Status for dpc_stats_ram_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "H3A_LUT_RAM1_RAMECC_PEND,Interrupt Pending Status for h3a_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "H3A_LUT_RAM0_RAMECC_PEND,Interrupt Pending Status for h3a_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "LSC_RAMECC_PEND,Interrupt Pending Status for lsc_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "DPC_LUT_RAMECC_PEND,Interrupt Pending Status for dpc_lut_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "WDR_LUT_RAM1_RAMECC_PEND,Interrupt Pending Status for wdr_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "WDR_LUT_RAM0_RAMECC_PEND,Interrupt Pending Status for wdr_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "LUT3_RAM1_RAMECC_PEND,Interrupt Pending Status for lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "LUT3_RAM0_RAMECC_PEND,Interrupt Pending Status for lut3_ram0_ramecc_pend" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 29. "PCID_REMAPLUT_RAMECC_B1_PEND,Interrupt Pending Status for pcid_remaplut_ramecc_b1_pend" "0,1" newline bitfld.long 0x8 28. "PCID_REMAPLUT_RAMECC_B0_PEND,Interrupt Pending Status for pcid_remaplut_ramecc_b0_pend" "0,1" newline bitfld.long 0x8 27. "MESHLUT_RAMECC_PEND,Interrupt Pending Status for meshlut_ramecc_pend" "0,1" newline bitfld.long 0x8 26. "DLUT3_1_RAMECC_PEND,Interrupt Pending Status for dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 25. "DLUT3_0_RAMECC_PEND,Interrupt Pending Status for dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 24. "DLUT2_1_RAMECC_PEND,Interrupt Pending Status for dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 23. "DLUT2_0_RAMECC_PEND,Interrupt Pending Status for dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 22. "DLUT1_1_RAMECC_PEND,Interrupt Pending Status for dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 21. "DLUT1_0_RAMECC_PEND,Interrupt Pending Status for dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 20. "DLUT0_1_RAMECC_PEND,Interrupt Pending Status for dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 19. "DLUT0_0_RAMECC_PEND,Interrupt Pending Status for dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 18. "CLUT3_1_RAMECC_PEND,Interrupt Pending Status for clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 17. "CLUT3_0_RAMECC_PEND,Interrupt Pending Status for clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 16. "CLUT2_1_RAMECC_PEND,Interrupt Pending Status for clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 15. "CLUT2_0_RAMECC_PEND,Interrupt Pending Status for clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 14. "CLUT1_1_RAMECC_PEND,Interrupt Pending Status for clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 13. "CLUT1_0_RAMECC_PEND,Interrupt Pending Status for clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 12. "CLUT0_1_RAMECC_PEND,Interrupt Pending Status for clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 11. "CLUT0_0_RAMECC_PEND,Interrupt Pending Status for clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 10. "HIST_DATA_B1_RAMECC_PEND,Interrupt Pending Status for hist_data_b1_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "HIST_DATA_B0_RAMECC_PEND,Interrupt Pending Status for hist_data_b0_ramecc_pend" "0,1" newline bitfld.long 0x8 8. "HIST_LUT_B1_RAMECC_PEND,Interrupt Pending Status for hist_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x8 7. "HIST_LUT_B0_RAMECC_PEND,Interrupt Pending Status for hist_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x8 6. "EELUT_1_RAMECC_PEND,Interrupt Pending Status for eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "EELUT_0_RAMECC_PEND,Interrupt Pending Status for eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "LUT_1_RAMECC_PEND,Interrupt Pending Status for lut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 3. "LUT_0_RAMECC_PEND,Interrupt Pending Status for lut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 2. "FCC_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 1. "FCC_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 0. "FCC_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut1_ram1_ramecc_pend" "0,1" group.long 0x80++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "FCC_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "FCC_LUT0_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "FCC_LUT0_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut3_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "FCC_HIST_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "FCC_HIST_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "STAT_MEM7_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem7_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "STAT_MEM6_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem6_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "STAT_MEM5_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem5_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "STAT_MEM4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem4_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "STAT_MEM3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem3_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "STAT_MEM2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem2_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "STAT_MEM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem1_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "STAT_MEM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem0_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "DPC_STATS_RAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dpc_stats_ram_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "H3A_LUT_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for h3a_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "H3A_LUT_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for h3a_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "LSC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lsc_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "DPC_LUT_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dpc_lut_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "WDR_LUT_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for wdr_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "WDR_LUT_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for wdr_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "LUT3_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "LUT3_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut3_ram0_ramecc_pend" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 29. "PCID_REMAPLUT_RAMECC_B1_ENABLE_SET,Interrupt Enable Set Register for pcid_remaplut_ramecc_b1_pend" "0,1" newline bitfld.long 0x4 28. "PCID_REMAPLUT_RAMECC_B0_ENABLE_SET,Interrupt Enable Set Register for pcid_remaplut_ramecc_b0_pend" "0,1" newline bitfld.long 0x4 27. "MESHLUT_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshlut_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "DLUT3_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "DLUT3_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "DLUT2_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "DLUT2_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "DLUT1_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "DLUT1_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "DLUT0_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "DLUT0_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "CLUT3_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "CLUT3_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "CLUT2_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "CLUT2_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "CLUT1_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "CLUT1_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "CLUT0_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "CLUT0_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "HIST_DATA_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_data_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "HIST_DATA_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_data_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "HIST_LUT_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "HIST_LUT_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "EELUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "EELUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "LUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "LUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "FCC_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "FCC_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "FCC_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut1_ram1_ramecc_pend" "0,1" group.long 0xC0++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "FCC_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "FCC_LUT0_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "FCC_LUT0_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut3_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "FCC_HIST_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "FCC_HIST_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "STAT_MEM7_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem7_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "STAT_MEM6_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem6_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "STAT_MEM5_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem5_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "STAT_MEM4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem4_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "STAT_MEM3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem3_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "STAT_MEM2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem2_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "STAT_MEM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem1_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "STAT_MEM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem0_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "DPC_STATS_RAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dpc_stats_ram_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "H3A_LUT_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for h3a_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "H3A_LUT_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for h3a_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "LSC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lsc_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "DPC_LUT_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dpc_lut_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "WDR_LUT_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for wdr_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "WDR_LUT_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for wdr_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "LUT3_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "LUT3_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut3_ram0_ramecc_pend" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_sec_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 29. "PCID_REMAPLUT_RAMECC_B1_ENABLE_CLR,Interrupt Enable Clear Register for pcid_remaplut_ramecc_b1_pend" "0,1" newline bitfld.long 0x4 28. "PCID_REMAPLUT_RAMECC_B0_ENABLE_CLR,Interrupt Enable Clear Register for pcid_remaplut_ramecc_b0_pend" "0,1" newline bitfld.long 0x4 27. "MESHLUT_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshlut_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "DLUT3_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "DLUT3_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "DLUT2_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "DLUT2_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "DLUT1_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "DLUT1_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "DLUT0_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "DLUT0_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "CLUT3_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "CLUT3_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "CLUT2_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "CLUT2_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "CLUT1_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "CLUT1_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "CLUT0_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "CLUT0_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "HIST_DATA_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_data_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "HIST_DATA_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_data_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "HIST_LUT_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "HIST_LUT_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "EELUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "EELUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "LUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "LUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "FCC_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "FCC_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "FCC_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut1_ram1_ramecc_pend" "0,1" group.long 0x13C++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0" bitfld.long 0x4 31. "FCC_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 30. "FCC_LUT0_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 29. "FCC_LUT0_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 28. "FCC_CONT_LUT3_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 27. "FCC_CONT_LUT3_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut3_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "FCC_CONT_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "FCC_CONT_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "FCC_CONT_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "FCC_CONT_LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "FCC_HIST_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "FCC_HIST_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "STAT_MEM7_RAMECC_PEND,Interrupt Pending Status for stat_mem7_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "STAT_MEM6_RAMECC_PEND,Interrupt Pending Status for stat_mem6_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "STAT_MEM5_RAMECC_PEND,Interrupt Pending Status for stat_mem5_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "STAT_MEM4_RAMECC_PEND,Interrupt Pending Status for stat_mem4_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "STAT_MEM3_RAMECC_PEND,Interrupt Pending Status for stat_mem3_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "STAT_MEM2_RAMECC_PEND,Interrupt Pending Status for stat_mem2_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "STAT_MEM1_RAMECC_PEND,Interrupt Pending Status for stat_mem1_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "STAT_MEM0_RAMECC_PEND,Interrupt Pending Status for stat_mem0_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "DPC_STATS_RAM_RAMECC_PEND,Interrupt Pending Status for dpc_stats_ram_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "H3A_LUT_RAM1_RAMECC_PEND,Interrupt Pending Status for h3a_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "H3A_LUT_RAM0_RAMECC_PEND,Interrupt Pending Status for h3a_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "LSC_RAMECC_PEND,Interrupt Pending Status for lsc_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "DPC_LUT_RAMECC_PEND,Interrupt Pending Status for dpc_lut_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "WDR_LUT_RAM1_RAMECC_PEND,Interrupt Pending Status for wdr_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "WDR_LUT_RAM0_RAMECC_PEND,Interrupt Pending Status for wdr_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "LUT1_RAM0_RAMECC_PEND,Interrupt Pending Status for lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "LUT3_RAM1_RAMECC_PEND,Interrupt Pending Status for lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "LUT3_RAM0_RAMECC_PEND,Interrupt Pending Status for lut3_ram0_ramecc_pend" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_status_reg1,Interrupt Status Register 1" bitfld.long 0x8 29. "PCID_REMAPLUT_RAMECC_B1_PEND,Interrupt Pending Status for pcid_remaplut_ramecc_b1_pend" "0,1" newline bitfld.long 0x8 28. "PCID_REMAPLUT_RAMECC_B0_PEND,Interrupt Pending Status for pcid_remaplut_ramecc_b0_pend" "0,1" newline bitfld.long 0x8 27. "MESHLUT_RAMECC_PEND,Interrupt Pending Status for meshlut_ramecc_pend" "0,1" newline bitfld.long 0x8 26. "DLUT3_1_RAMECC_PEND,Interrupt Pending Status for dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 25. "DLUT3_0_RAMECC_PEND,Interrupt Pending Status for dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 24. "DLUT2_1_RAMECC_PEND,Interrupt Pending Status for dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 23. "DLUT2_0_RAMECC_PEND,Interrupt Pending Status for dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 22. "DLUT1_1_RAMECC_PEND,Interrupt Pending Status for dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 21. "DLUT1_0_RAMECC_PEND,Interrupt Pending Status for dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 20. "DLUT0_1_RAMECC_PEND,Interrupt Pending Status for dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 19. "DLUT0_0_RAMECC_PEND,Interrupt Pending Status for dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 18. "CLUT3_1_RAMECC_PEND,Interrupt Pending Status for clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x8 17. "CLUT3_0_RAMECC_PEND,Interrupt Pending Status for clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x8 16. "CLUT2_1_RAMECC_PEND,Interrupt Pending Status for clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x8 15. "CLUT2_0_RAMECC_PEND,Interrupt Pending Status for clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x8 14. "CLUT1_1_RAMECC_PEND,Interrupt Pending Status for clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x8 13. "CLUT1_0_RAMECC_PEND,Interrupt Pending Status for clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x8 12. "CLUT0_1_RAMECC_PEND,Interrupt Pending Status for clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x8 11. "CLUT0_0_RAMECC_PEND,Interrupt Pending Status for clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x8 10. "HIST_DATA_B1_RAMECC_PEND,Interrupt Pending Status for hist_data_b1_ramecc_pend" "0,1" newline bitfld.long 0x8 9. "HIST_DATA_B0_RAMECC_PEND,Interrupt Pending Status for hist_data_b0_ramecc_pend" "0,1" newline bitfld.long 0x8 8. "HIST_LUT_B1_RAMECC_PEND,Interrupt Pending Status for hist_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x8 7. "HIST_LUT_B0_RAMECC_PEND,Interrupt Pending Status for hist_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x8 6. "EELUT_1_RAMECC_PEND,Interrupt Pending Status for eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 5. "EELUT_0_RAMECC_PEND,Interrupt Pending Status for eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 4. "LUT_1_RAMECC_PEND,Interrupt Pending Status for lut_1_ramecc_pend" "0,1" newline bitfld.long 0x8 3. "LUT_0_RAMECC_PEND,Interrupt Pending Status for lut_0_ramecc_pend" "0,1" newline bitfld.long 0x8 2. "FCC_LUT2_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x8 1. "FCC_LUT2_RAM0_RAMECC_PEND,Interrupt Pending Status for fcc_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x8 0. "FCC_LUT1_RAM1_RAMECC_PEND,Interrupt Pending Status for fcc_lut1_ram1_ramecc_pend" "0,1" group.long 0x180++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0" bitfld.long 0x0 31. "FCC_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "FCC_LUT0_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "FCC_LUT0_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut3_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "FCC_HIST_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "FCC_HIST_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "STAT_MEM7_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem7_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "STAT_MEM6_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem6_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "STAT_MEM5_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem5_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "STAT_MEM4_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem4_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "STAT_MEM3_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem3_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "STAT_MEM2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem2_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "STAT_MEM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem1_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "STAT_MEM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for stat_mem0_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "DPC_STATS_RAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dpc_stats_ram_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "H3A_LUT_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for h3a_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "H3A_LUT_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for h3a_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "LSC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lsc_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "DPC_LUT_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dpc_lut_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "WDR_LUT_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for wdr_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "WDR_LUT_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for wdr_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "LUT1_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "LUT3_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "LUT3_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut3_ram0_ramecc_pend" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_enable_set_reg1,Interrupt Enable Set Register 1" bitfld.long 0x4 29. "PCID_REMAPLUT_RAMECC_B1_ENABLE_SET,Interrupt Enable Set Register for pcid_remaplut_ramecc_b1_pend" "0,1" newline bitfld.long 0x4 28. "PCID_REMAPLUT_RAMECC_B0_ENABLE_SET,Interrupt Enable Set Register for pcid_remaplut_ramecc_b0_pend" "0,1" newline bitfld.long 0x4 27. "MESHLUT_RAMECC_ENABLE_SET,Interrupt Enable Set Register for meshlut_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "DLUT3_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "DLUT3_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "DLUT2_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "DLUT2_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "DLUT1_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "DLUT1_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "DLUT0_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "DLUT0_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "CLUT3_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "CLUT3_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "CLUT2_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "CLUT2_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "CLUT1_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "CLUT1_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "CLUT0_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "CLUT0_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "HIST_DATA_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_data_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "HIST_DATA_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_data_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "HIST_LUT_B1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "HIST_LUT_B0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for hist_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "EELUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "EELUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "LUT_1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "LUT_0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "FCC_LUT2_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "FCC_LUT2_RAM0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "FCC_LUT1_RAM1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for fcc_lut1_ram1_ramecc_pend" "0,1" group.long 0x1C0++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0" bitfld.long 0x0 31. "FCC_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 30. "FCC_LUT0_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut0_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 29. "FCC_LUT0_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut0_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 28. "FCC_CONT_LUT3_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 27. "FCC_CONT_LUT3_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut3_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 26. "FCC_CONT_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 25. "FCC_CONT_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 24. "FCC_CONT_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 23. "FCC_CONT_LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_cont_lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 22. "FCC_HIST_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_hist_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 21. "FCC_HIST_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_hist_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 20. "STAT_MEM7_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem7_ramecc_pend" "0,1" newline bitfld.long 0x0 19. "STAT_MEM6_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem6_ramecc_pend" "0,1" newline bitfld.long 0x0 18. "STAT_MEM5_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem5_ramecc_pend" "0,1" newline bitfld.long 0x0 17. "STAT_MEM4_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem4_ramecc_pend" "0,1" newline bitfld.long 0x0 16. "STAT_MEM3_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem3_ramecc_pend" "0,1" newline bitfld.long 0x0 15. "STAT_MEM2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem2_ramecc_pend" "0,1" newline bitfld.long 0x0 14. "STAT_MEM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem1_ramecc_pend" "0,1" newline bitfld.long 0x0 13. "STAT_MEM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for stat_mem0_ramecc_pend" "0,1" newline bitfld.long 0x0 12. "DPC_STATS_RAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dpc_stats_ram_ramecc_pend" "0,1" newline bitfld.long 0x0 11. "H3A_LUT_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for h3a_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 10. "H3A_LUT_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for h3a_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 9. "LSC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lsc_ramecc_pend" "0,1" newline bitfld.long 0x0 8. "DPC_LUT_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dpc_lut_ramecc_pend" "0,1" newline bitfld.long 0x0 7. "WDR_LUT_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for wdr_lut_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 6. "WDR_LUT_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for wdr_lut_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 5. "LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut1_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 4. "LUT1_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut1_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 3. "LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 2. "LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x0 1. "LUT3_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut3_ram1_ramecc_pend" "0,1" newline bitfld.long 0x0 0. "LUT3_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut3_ram0_ramecc_pend" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_ded_enable_clr_reg1,Interrupt Enable Clear Register 1" bitfld.long 0x4 29. "PCID_REMAPLUT_RAMECC_B1_ENABLE_CLR,Interrupt Enable Clear Register for pcid_remaplut_ramecc_b1_pend" "0,1" newline bitfld.long 0x4 28. "PCID_REMAPLUT_RAMECC_B0_ENABLE_CLR,Interrupt Enable Clear Register for pcid_remaplut_ramecc_b0_pend" "0,1" newline bitfld.long 0x4 27. "MESHLUT_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for meshlut_ramecc_pend" "0,1" newline bitfld.long 0x4 26. "DLUT3_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 25. "DLUT3_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 24. "DLUT2_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 23. "DLUT2_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 22. "DLUT1_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 21. "DLUT1_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 20. "DLUT0_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 19. "DLUT0_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dlut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 18. "CLUT3_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut3_1_ramecc_pend" "0,1" newline bitfld.long 0x4 17. "CLUT3_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut3_0_ramecc_pend" "0,1" newline bitfld.long 0x4 16. "CLUT2_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut2_1_ramecc_pend" "0,1" newline bitfld.long 0x4 15. "CLUT2_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut2_0_ramecc_pend" "0,1" newline bitfld.long 0x4 14. "CLUT1_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut1_1_ramecc_pend" "0,1" newline bitfld.long 0x4 13. "CLUT1_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut1_0_ramecc_pend" "0,1" newline bitfld.long 0x4 12. "CLUT0_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut0_1_ramecc_pend" "0,1" newline bitfld.long 0x4 11. "CLUT0_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for clut0_0_ramecc_pend" "0,1" newline bitfld.long 0x4 10. "HIST_DATA_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_data_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 9. "HIST_DATA_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_data_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 8. "HIST_LUT_B1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_lut_b1_ramecc_pend" "0,1" newline bitfld.long 0x4 7. "HIST_LUT_B0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for hist_lut_b0_ramecc_pend" "0,1" newline bitfld.long 0x4 6. "EELUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for eelut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 5. "EELUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for eelut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 4. "LUT_1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut_1_ramecc_pend" "0,1" newline bitfld.long 0x4 3. "LUT_0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lut_0_ramecc_pend" "0,1" newline bitfld.long 0x4 2. "FCC_LUT2_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut2_ram1_ramecc_pend" "0,1" newline bitfld.long 0x4 1. "FCC_LUT2_RAM0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut2_ram0_ramecc_pend" "0,1" newline bitfld.long 0x4 0. "FCC_LUT1_RAM1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for fcc_lut1_ram1_ramecc_pend" "0,1" group.long 0x200++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register" bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" newline bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register" bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" newline bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register" bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__KSDW_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register" bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "VPAC_RSWS_BW_LIMITER7_REGS" base ad:0x30400000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,PID function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" group.long 0x4++0x3 line.long 0x0 "REGS_CTRL,This register controls the overall behavior of the rate limiter module" bitfld.long 0x0 4. "REGION_FILTER_EN,Enable the region filter which will only apply the bandwith and transaction limits to the configured address regions" "0,1" bitfld.long 0x0 3. "WR_TXN_ENABLE,Enable limiting maximum outstanding write transactions" "0,1" bitfld.long 0x0 2. "RD_TXN_ENABLE,Enable limiting maximum outstanding read transactions" "0,1" bitfld.long 0x0 1. "WR_BW_ENABLE,Enable write bandwidth limiting" "0,1" bitfld.long 0x0 0. "RD_BW_ENABLE,Enable read bandwidth limiting" "0,1" group.long 0x100++0xB line.long 0x0 "REGS_RD_BW_CIR,Read Bandwidth Committed Information Rate" hexmask.long 0x0 0.--31. 1. "CIR,Committed Information Rate" line.long 0x4 "REGS_RD_BW_PIR,Read Bandwidth Peak Information Rate" hexmask.long 0x4 0.--31. 1. "PIR,Peak Information Rate" line.long 0x8 "REGS_RD_BW_BURST_OFFSET,Read Bandwidth Burst Offset" hexmask.long.word 0x8 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity. Peak Information Rate will still apply" rgroup.long 0x10C++0x3 line.long 0x0 "REGS_RD_BW_INFO,Read Bandwidth State machine information. Primarly for verification purposes" bitfld.long 0x0 0.--1. "COLOR,Read Bandwidth three-color marker output from rategen submodule" "0,1,2,3" group.long 0x120++0x7 line.long 0x0 "REGS_RD_BW_STATS,Read Bandwidth Statistics Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable read bandwidth statistics" "0,1" line.long 0x4 "REGS_RD_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR" hexmask.long 0x4 0.--31. 1. "THRESHOLD,Read bandwidth stats threshold in bytes. Note that this is total bytes unlike CIR and PIR. CIR and PIR are based on a rolling window and the statistics threshold is based on a fixed window. This will still take into account DDR bytes used so.." rgroup.long 0x128++0x13 line.long 0x0 "REGS_RD_BW_WINDOWS_CNT,Read Bandwidth Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Read bandwidth window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_RD_BW_CIR_CNT,Read Bandwidth Statistics - CIR Count" hexmask.long 0x4 0.--31. 1. "VAL,The total number of statistics windows in which Read Commit Information Rate occurred. Note that if PIR is set to a lower value than CIR or if the burst offset feature is used this will also count times that PIR is reached." line.long 0x8 "REGS_RD_BW_PIR_CNT,Read Bandwidth Statistics - PIR Count" hexmask.long 0x8 0.--31. 1. "VAL,The total number of statistics windows in which Read Peak Information Rate occurred" line.long 0xC "REGS_RD_BW_THRSHLD_CNT,Read Bandwidth Statistics - Threshold Count" hexmask.long 0xC 0.--31. 1. "VAL,The total number of statistics windows in which Read bytes transferred exceeded the statistics threshold" line.long 0x10 "REGS_RD_BYTES_MAX,The maximum number of bytes seen in a single statitsics window. This can be compared with the window size to calculate the maximum bandwidth seen" hexmask.long 0x10 0.--31. 1. "VAL,Max number of bytes in a single window. This number accounts for DDR bandwidth consumed not simply the accumulation of the packet bytecnt values across a window. The max bandwidth calculation is the total bytes value in this MMR divided by the.." group.long 0x200++0xB line.long 0x0 "REGS_WR_BW_CIR,Write Bandwidth Committed Information Rate" hexmask.long 0x0 0.--31. 1. "CIR,Committed Information Rate" line.long 0x4 "REGS_WR_BW_PIR,Write Bandwidth Peak Information Rate" hexmask.long 0x4 0.--31. 1. "PIR,Peak Information Rate" line.long 0x8 "REGS_WR_BW_BURST_OFFSET,Write Bandwidth Burst Offset" hexmask.long.word 0x8 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity. Peak Information Rate will still apply" rgroup.long 0x20C++0x3 line.long 0x0 "REGS_WR_BW_INFO,Write Bandwidth State machine information. Primarly for verification purposes" bitfld.long 0x0 0.--1. "COLOR,Write Bandwidth three-color marker output from rategen submodule" "0,1,2,3" group.long 0x220++0x7 line.long 0x0 "REGS_WR_BW_STATS,Write Bandwidth Statistics Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable write bandwidth statistics" "0,1" line.long 0x4 "REGS_WR_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR" hexmask.long 0x4 0.--31. 1. "THRESHOLD,Write bandwidth stats threshold in bytes. Note that this is total bytes unlike CIR and PIR. CIR and PIR are based on a rolling window and the statistics threshold is based on a fixed window. This will still take into account DDR bytes used .." rgroup.long 0x228++0x13 line.long 0x0 "REGS_WR_BW_WINDOWS_CNT,Write Bandwidth Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Write bandwidth window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_WR_BW_CIR_CNT,Write Bandwidth Statistics - CIR Count" hexmask.long 0x4 0.--31. 1. "VAL,The total number of statistics windows in which Write Commit Information Rate occurred. Note that if PIR is set to a lower value than CIR or if the burst offset feature is used this will also count times that PIR is reached." line.long 0x8 "REGS_WR_BW_PIR_CNT,Write Bandwidth Statistics - PIR Count" hexmask.long 0x8 0.--31. 1. "VAL,The total number of statistics windows in which Write Peak Information Rate occurred" line.long 0xC "REGS_WR_BW_THRSHLD_CNT,Write Bandwidth Statistics - Threshold Count" hexmask.long 0xC 0.--31. 1. "VAL,The total number of statistics windows in which Write bytes transferred exceeded the statistics threshold" line.long 0x10 "REGS_WR_BYTES_MAX,The maximum number of bytes seen in a single statitsics window. This can be compared with the window size to calculate the maximum bandwidth seen" hexmask.long 0x10 0.--31. 1. "VAL,Max number of bytes in a single window. This number accounts for DDR bandwidth consumed not simply the accumulation of the packet bytecnt values across a window. The max bandwidth calculation is the total bytes value in this MMR divided by the.." group.long 0x300++0x3 line.long 0x0 "REGS_RD_TXN,The maximum number of outstanding read transactions the rate limiter will allow" hexmask.long.word 0x0 0.--15. 1. "LIMIT,The maximum number of outstanding read transactions allowed. NOTE: This cannot be programmed to a zero. If a zero is written it will default to the reset value of 16'd64 as a limit of zero outstanding transactions would hang the interface." rgroup.long 0x30C++0x3 line.long 0x0 "REGS_RD_TXN_INFO,Read Transaction State machine information. Primarly for verification purposes" hexmask.long.byte 0x0 0.--6. 1. "OCC,Read transaction scoreboard occupancy" group.long 0x320++0x7 line.long 0x0 "REGS_RD_TXN_STATS,Read Transaction Stats Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable read transaction statistics" "0,1" line.long 0x4 "REGS_RD_TXN_STATS_THRSHLD,A statistics threshold separate from the read transaction limit" hexmask.long.word 0x4 0.--15. 1. "THRESHOLD,Read transaction statistics threshold. The threshold can be set to any value though it will saturate at the outstanding transaction limit if it is set to a value greater than the programmed outstanding read transaction limit" rgroup.long 0x328++0x17 line.long 0x0 "REGS_RD_TXN_WINDOWS_CNT,Read Transaction Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Read transaction window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_RD_TXN_LMT_CNT,Read Transaction Statistics - number of windows in which the outstanding transaction limit was reached" hexmask.long 0x4 0.--31. 1. "VAL,The number of statistics windows in which the outstanding read transaction limit was reached" line.long 0x8 "REGS_RD_TXN_THRSHLD_CNT,Read Transaction Statistics - number of windows in which the statistics threshold was reached" hexmask.long 0x8 0.--31. 1. "VAL,The number of statistics windows in which the number of outstanding read transactions was greater than or equal to the threshold in RD_TXN_STATS_THRSHLD" line.long 0xC "REGS_RD_TXN_LIMIT_TOTAL,Read Transaction Statistics - Cycles at Outstanding Read Transactions Limit" hexmask.long 0xC 0.--31. 1. "VAL,The total number of cycles with the read transactions outstanding at the programmed limit since statistics collection began" line.long 0x10 "REGS_RD_TXN_THRSHLD_TOTAL,Read Transaction Statistics - Cycles at the Statistics Threshold" hexmask.long 0x10 0.--31. 1. "VAL,The total number of cycles with read transactions outstanding greater than or equal to the statistics threshold in RD_TXN_STATS_THRSHLD since statistics collection began" line.long 0x14 "REGS_RD_TXN_MAX,Read Transaction Statistics - Max Observed Outstanding Read Transactions" hexmask.long.word 0x14 0.--15. 1. "VAL,The maximum outstanding read transactions at any point in time regardless of the programmed limit" group.long 0x400++0x3 line.long 0x0 "REGS_WR_TXN,The maximum number of outstanding write transactions the rate limiter will allow" hexmask.long.word 0x0 0.--15. 1. "LIMIT,The maximum number of outstanding write transactions allowed. NOTE: This cannot be programmed to a zero. If a zero is written it will default to the reset value of 16'd64 as a limit of zero outstanding transactions would hang the interface." rgroup.long 0x40C++0x3 line.long 0x0 "REGS_WR_TXN_INFO,Write Transaction State machine information. Primarly for verification purposes" hexmask.long.byte 0x0 0.--6. 1. "OCC,Write transaction scoreboard occupancy" group.long 0x420++0x7 line.long 0x0 "REGS_WR_TXN_STATS,Write Transaction Stats Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable write transaction statistics" "0,1" line.long 0x4 "REGS_WR_TXN_STATS_THRSHLD,A statistics threshold separate from the write transaction limit" hexmask.long.word 0x4 0.--15. 1. "THRESHOLD,Write transaction statistics threshold. The threshold can be set to any value though it will saturate at the outstanding transaction limit if it is set to a value greater than the programmed outstanding write transaction limit" rgroup.long 0x428++0x17 line.long 0x0 "REGS_WR_TXN_WINDOWS_CNT,Write Transaction Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Write transaction window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_WR_TXN_LMT_CNT,Write Transaction Statistics - number of windows in which the outstanding transaction limit was reached" hexmask.long 0x4 0.--31. 1. "VAL,The number of statistics windows in which the outstanding write transaction limit was reached" line.long 0x8 "REGS_WR_TXN_THRSHLD_CNT,Write Transaction Statistics - number of windows in which the statistics threshold was reached" hexmask.long 0x8 0.--31. 1. "VAL,The number of statistics windows in which the number of outstanding write transactions was greater than or equal to the threshold in WR_TXN_STATS_THRSHLD" line.long 0xC "REGS_WR_TXN_LIMIT_TOTAL,Write Transaction Statistics - Cycles at Outstanding Write Transactions Limit" hexmask.long 0xC 0.--31. 1. "VAL,The total number of cycles with the write transactions outstanding at the programmed limit since statistics collection began" line.long 0x10 "REGS_WR_TXN_THRSHLD_TOTAL,Write Transaction Statistics - Cycles at the Statistics Threshold" hexmask.long 0x10 0.--31. 1. "VAL,The total number of cycles with write transactions outstanding greater than or equal to the statistics threshold in WR_TXN_STATS_THRSHLD since statistics collection began" line.long 0x14 "REGS_WR_TXN_MAX,Write Transaction Statistics - Max Observed Outstanding Write Transactions" hexmask.long.word 0x14 0.--15. 1. "VAL,The maximum outstanding write transactions at any point in time regardless of the programmed limit" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "VPAC_RSWS_BW_LIMITER8_REGS" base ad:0x30407000 rgroup.long 0x0++0x3 line.long 0x0 "REGS_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space" bitfld.long 0x0 30.--31. "SCHEME,PID scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,PID bu identifier" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,PID function identifier" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,PID RTL version number" bitfld.long 0x0 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,PID custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,PID Minor revision number" group.long 0x4++0x3 line.long 0x0 "REGS_CTRL,This register controls the overall behavior of the rate limiter module" bitfld.long 0x0 4. "REGION_FILTER_EN,Enable the region filter which will only apply the bandwith and transaction limits to the configured address regions" "0,1" bitfld.long 0x0 3. "WR_TXN_ENABLE,Enable limiting maximum outstanding write transactions" "0,1" bitfld.long 0x0 2. "RD_TXN_ENABLE,Enable limiting maximum outstanding read transactions" "0,1" bitfld.long 0x0 1. "WR_BW_ENABLE,Enable write bandwidth limiting" "0,1" bitfld.long 0x0 0. "RD_BW_ENABLE,Enable read bandwidth limiting" "0,1" group.long 0x100++0xB line.long 0x0 "REGS_RD_BW_CIR,Read Bandwidth Committed Information Rate" hexmask.long 0x0 0.--31. 1. "CIR,Committed Information Rate" line.long 0x4 "REGS_RD_BW_PIR,Read Bandwidth Peak Information Rate" hexmask.long 0x4 0.--31. 1. "PIR,Peak Information Rate" line.long 0x8 "REGS_RD_BW_BURST_OFFSET,Read Bandwidth Burst Offset" hexmask.long.word 0x8 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity. Peak Information Rate will still apply" rgroup.long 0x10C++0x3 line.long 0x0 "REGS_RD_BW_INFO,Read Bandwidth State machine information. Primarly for verification purposes" bitfld.long 0x0 0.--1. "COLOR,Read Bandwidth three-color marker output from rategen submodule" "0,1,2,3" group.long 0x120++0x7 line.long 0x0 "REGS_RD_BW_STATS,Read Bandwidth Statistics Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable read bandwidth statistics" "0,1" line.long 0x4 "REGS_RD_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR" hexmask.long 0x4 0.--31. 1. "THRESHOLD,Read bandwidth stats threshold in bytes. Note that this is total bytes unlike CIR and PIR. CIR and PIR are based on a rolling window and the statistics threshold is based on a fixed window. This will still take into account DDR bytes used so.." rgroup.long 0x128++0x13 line.long 0x0 "REGS_RD_BW_WINDOWS_CNT,Read Bandwidth Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Read bandwidth window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_RD_BW_CIR_CNT,Read Bandwidth Statistics - CIR Count" hexmask.long 0x4 0.--31. 1. "VAL,The total number of statistics windows in which Read Commit Information Rate occurred. Note that if PIR is set to a lower value than CIR or if the burst offset feature is used this will also count times that PIR is reached." line.long 0x8 "REGS_RD_BW_PIR_CNT,Read Bandwidth Statistics - PIR Count" hexmask.long 0x8 0.--31. 1. "VAL,The total number of statistics windows in which Read Peak Information Rate occurred" line.long 0xC "REGS_RD_BW_THRSHLD_CNT,Read Bandwidth Statistics - Threshold Count" hexmask.long 0xC 0.--31. 1. "VAL,The total number of statistics windows in which Read bytes transferred exceeded the statistics threshold" line.long 0x10 "REGS_RD_BYTES_MAX,The maximum number of bytes seen in a single statitsics window. This can be compared with the window size to calculate the maximum bandwidth seen" hexmask.long 0x10 0.--31. 1. "VAL,Max number of bytes in a single window. This number accounts for DDR bandwidth consumed not simply the accumulation of the packet bytecnt values across a window. The max bandwidth calculation is the total bytes value in this MMR divided by the.." group.long 0x200++0xB line.long 0x0 "REGS_WR_BW_CIR,Write Bandwidth Committed Information Rate" hexmask.long 0x0 0.--31. 1. "CIR,Committed Information Rate" line.long 0x4 "REGS_WR_BW_PIR,Write Bandwidth Peak Information Rate" hexmask.long 0x4 0.--31. 1. "PIR,Peak Information Rate" line.long 0x8 "REGS_WR_BW_BURST_OFFSET,Write Bandwidth Burst Offset" hexmask.long.word 0x8 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity. Peak Information Rate will still apply" rgroup.long 0x20C++0x3 line.long 0x0 "REGS_WR_BW_INFO,Write Bandwidth State machine information. Primarly for verification purposes" bitfld.long 0x0 0.--1. "COLOR,Write Bandwidth three-color marker output from rategen submodule" "0,1,2,3" group.long 0x220++0x7 line.long 0x0 "REGS_WR_BW_STATS,Write Bandwidth Statistics Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable write bandwidth statistics" "0,1" line.long 0x4 "REGS_WR_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR" hexmask.long 0x4 0.--31. 1. "THRESHOLD,Write bandwidth stats threshold in bytes. Note that this is total bytes unlike CIR and PIR. CIR and PIR are based on a rolling window and the statistics threshold is based on a fixed window. This will still take into account DDR bytes used .." rgroup.long 0x228++0x13 line.long 0x0 "REGS_WR_BW_WINDOWS_CNT,Write Bandwidth Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Write bandwidth window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_WR_BW_CIR_CNT,Write Bandwidth Statistics - CIR Count" hexmask.long 0x4 0.--31. 1. "VAL,The total number of statistics windows in which Write Commit Information Rate occurred. Note that if PIR is set to a lower value than CIR or if the burst offset feature is used this will also count times that PIR is reached." line.long 0x8 "REGS_WR_BW_PIR_CNT,Write Bandwidth Statistics - PIR Count" hexmask.long 0x8 0.--31. 1. "VAL,The total number of statistics windows in which Write Peak Information Rate occurred" line.long 0xC "REGS_WR_BW_THRSHLD_CNT,Write Bandwidth Statistics - Threshold Count" hexmask.long 0xC 0.--31. 1. "VAL,The total number of statistics windows in which Write bytes transferred exceeded the statistics threshold" line.long 0x10 "REGS_WR_BYTES_MAX,The maximum number of bytes seen in a single statitsics window. This can be compared with the window size to calculate the maximum bandwidth seen" hexmask.long 0x10 0.--31. 1. "VAL,Max number of bytes in a single window. This number accounts for DDR bandwidth consumed not simply the accumulation of the packet bytecnt values across a window. The max bandwidth calculation is the total bytes value in this MMR divided by the.." group.long 0x300++0x3 line.long 0x0 "REGS_RD_TXN,The maximum number of outstanding read transactions the rate limiter will allow" hexmask.long.word 0x0 0.--15. 1. "LIMIT,The maximum number of outstanding read transactions allowed. NOTE: This cannot be programmed to a zero. If a zero is written it will default to the reset value of 16'd64 as a limit of zero outstanding transactions would hang the interface." rgroup.long 0x30C++0x3 line.long 0x0 "REGS_RD_TXN_INFO,Read Transaction State machine information. Primarly for verification purposes" hexmask.long.byte 0x0 0.--6. 1. "OCC,Read transaction scoreboard occupancy" group.long 0x320++0x7 line.long 0x0 "REGS_RD_TXN_STATS,Read Transaction Stats Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable read transaction statistics" "0,1" line.long 0x4 "REGS_RD_TXN_STATS_THRSHLD,A statistics threshold separate from the read transaction limit" hexmask.long.word 0x4 0.--15. 1. "THRESHOLD,Read transaction statistics threshold. The threshold can be set to any value though it will saturate at the outstanding transaction limit if it is set to a value greater than the programmed outstanding read transaction limit" rgroup.long 0x328++0x17 line.long 0x0 "REGS_RD_TXN_WINDOWS_CNT,Read Transaction Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Read transaction window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_RD_TXN_LMT_CNT,Read Transaction Statistics - number of windows in which the outstanding transaction limit was reached" hexmask.long 0x4 0.--31. 1. "VAL,The number of statistics windows in which the outstanding read transaction limit was reached" line.long 0x8 "REGS_RD_TXN_THRSHLD_CNT,Read Transaction Statistics - number of windows in which the statistics threshold was reached" hexmask.long 0x8 0.--31. 1. "VAL,The number of statistics windows in which the number of outstanding read transactions was greater than or equal to the threshold in RD_TXN_STATS_THRSHLD" line.long 0xC "REGS_RD_TXN_LIMIT_TOTAL,Read Transaction Statistics - Cycles at Outstanding Read Transactions Limit" hexmask.long 0xC 0.--31. 1. "VAL,The total number of cycles with the read transactions outstanding at the programmed limit since statistics collection began" line.long 0x10 "REGS_RD_TXN_THRSHLD_TOTAL,Read Transaction Statistics - Cycles at the Statistics Threshold" hexmask.long 0x10 0.--31. 1. "VAL,The total number of cycles with read transactions outstanding greater than or equal to the statistics threshold in RD_TXN_STATS_THRSHLD since statistics collection began" line.long 0x14 "REGS_RD_TXN_MAX,Read Transaction Statistics - Max Observed Outstanding Read Transactions" hexmask.long.word 0x14 0.--15. 1. "VAL,The maximum outstanding read transactions at any point in time regardless of the programmed limit" group.long 0x400++0x3 line.long 0x0 "REGS_WR_TXN,The maximum number of outstanding write transactions the rate limiter will allow" hexmask.long.word 0x0 0.--15. 1. "LIMIT,The maximum number of outstanding write transactions allowed. NOTE: This cannot be programmed to a zero. If a zero is written it will default to the reset value of 16'd64 as a limit of zero outstanding transactions would hang the interface." rgroup.long 0x40C++0x3 line.long 0x0 "REGS_WR_TXN_INFO,Write Transaction State machine information. Primarly for verification purposes" hexmask.long.byte 0x0 0.--6. 1. "OCC,Write transaction scoreboard occupancy" group.long 0x420++0x7 line.long 0x0 "REGS_WR_TXN_STATS,Write Transaction Stats Control Register" hexmask.long.word 0x0 16.--31. 1. "WINDOW,Statistics window size. This cannot be set to 0. If 16'd0 is written it will be set to the reset value of 16'd1024" rbitfld.long 0x0 9. "OVERFLOW,Statistics overflow error" "0,1" bitfld.long 0x0 8. "CLR,Clear statistics data. Resets statistics counters at 0" "0,1" bitfld.long 0x0 0. "EN,Enable write transaction statistics" "0,1" line.long 0x4 "REGS_WR_TXN_STATS_THRSHLD,A statistics threshold separate from the write transaction limit" hexmask.long.word 0x4 0.--15. 1. "THRESHOLD,Write transaction statistics threshold. The threshold can be set to any value though it will saturate at the outstanding transaction limit if it is set to a value greater than the programmed outstanding write transaction limit" rgroup.long 0x428++0x17 line.long 0x0 "REGS_WR_TXN_WINDOWS_CNT,Write Transaction Statistics - Window Count" hexmask.long 0x0 0.--31. 1. "VAL,Write transaction window count - the number of windows elapsed since statistics collection began" line.long 0x4 "REGS_WR_TXN_LMT_CNT,Write Transaction Statistics - number of windows in which the outstanding transaction limit was reached" hexmask.long 0x4 0.--31. 1. "VAL,The number of statistics windows in which the outstanding write transaction limit was reached" line.long 0x8 "REGS_WR_TXN_THRSHLD_CNT,Write Transaction Statistics - number of windows in which the statistics threshold was reached" hexmask.long 0x8 0.--31. 1. "VAL,The number of statistics windows in which the number of outstanding write transactions was greater than or equal to the threshold in WR_TXN_STATS_THRSHLD" line.long 0xC "REGS_WR_TXN_LIMIT_TOTAL,Write Transaction Statistics - Cycles at Outstanding Write Transactions Limit" hexmask.long 0xC 0.--31. 1. "VAL,The total number of cycles with the write transactions outstanding at the programmed limit since statistics collection began" line.long 0x10 "REGS_WR_TXN_THRSHLD_TOTAL,Write Transaction Statistics - Cycles at the Statistics Threshold" hexmask.long 0x10 0.--31. 1. "VAL,The total number of cycles with write transactions outstanding greater than or equal to the statistics threshold in WR_TXN_STATS_THRSHLD since statistics collection began" line.long 0x14 "REGS_WR_TXN_MAX,Write Transaction Statistics - Max Observed Outstanding Write Transactions" hexmask.long.word 0x14 0.--15. 1. "VAL,The maximum outstanding write transactions at any point in time regardless of the programmed limit" tree.end endif tree "VPAC0_COMMON_0" tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_CP_INTD_CFG_INTD_CFG" base ad:0x2C004000 rgroup.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_REVISION,Revision Register" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTLVER,RTL revisions" newline bitfld.long 0x0 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINREV,Minor revision" group.long 0x10++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_eoi_reg,End of Interrupt Register" hexmask.long.byte 0x0 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector" rgroup.long 0x14++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg,Interrupt Vector Register" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR,Interrupt Vector Register" group.long 0x100++0x17F line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_0,Enable Register 0" bitfld.long 0x0 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_DPC_STATS_READ_ERR,Enable Set for level_vpac_out_0_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x0 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_CR_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x0 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for level_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x0 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x0 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x0 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x0 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x0 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x0 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x0 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x0 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x0 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x0 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x0 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x0 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x0 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x0 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x0 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x0 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x0 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x0 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x0 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x0 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x0 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x0 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x0 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x0 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x0 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_1,Enable Register 1" bitfld.long 0x4 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x4 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x4 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x4 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x4 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x4 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x4 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x4 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x4 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_2,Enable Register 2" bitfld.long 0x8 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x8 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x8 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x8 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_3,Enable Register 3" bitfld.long 0xC 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xC 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xC 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xC 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xC 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xC 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_0_en_spare_pend_1_level" "0,1" newline bitfld.long 0xC 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_0_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xC 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_0_en_spare_pend_0_level" "0,1" newline bitfld.long 0xC 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_0_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xC 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_DEC_1,Enable Set for level_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xC 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_DEC_0,Enable Set for level_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xC 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_6,Enable Set for level_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xC 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_5,Enable Set for level_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xC 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_4,Enable Set for level_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xC 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_2,Enable Set for level_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xC 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_0,Enable Set for level_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xC 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_6,Enable Set for level_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xC 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_5,Enable Set for level_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xC 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_4,Enable Set for level_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xC 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_3,Enable Set for level_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xC 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_2,Enable Set for level_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xC 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_1,Enable Set for level_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xC 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_0,Enable Set for level_vpac_out_0_en_pipe_done_0" "0,1" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_4,Enable Register 4" bitfld.long 0x10 31. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0x10 30. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0x10 29. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0x10 28. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0x10 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0x10 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0x10 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0x10 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0x10 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0x10 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0x10 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0x10 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0x10 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0x10 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0x10 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0x10 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0x10 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0x10 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0x10 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0x10 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0x10 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0x10 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0x10 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0x10 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0x10 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0x10 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0x10 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0x10 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0x10 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0x10 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0x10 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0x10 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_5,Enable Register 5" bitfld.long 0x14 31. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_63,Enable Set for level_vpac_out_0_en_utc0_complete_63" "0,1" newline bitfld.long 0x14 30. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_62,Enable Set for level_vpac_out_0_en_utc0_complete_62" "0,1" newline bitfld.long 0x14 29. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_61,Enable Set for level_vpac_out_0_en_utc0_complete_61" "0,1" newline bitfld.long 0x14 28. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_60,Enable Set for level_vpac_out_0_en_utc0_complete_60" "0,1" newline bitfld.long 0x14 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_59,Enable Set for level_vpac_out_0_en_utc0_complete_59" "0,1" newline bitfld.long 0x14 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_58,Enable Set for level_vpac_out_0_en_utc0_complete_58" "0,1" newline bitfld.long 0x14 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_57,Enable Set for level_vpac_out_0_en_utc0_complete_57" "0,1" newline bitfld.long 0x14 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_56,Enable Set for level_vpac_out_0_en_utc0_complete_56" "0,1" newline bitfld.long 0x14 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_55,Enable Set for level_vpac_out_0_en_utc0_complete_55" "0,1" newline bitfld.long 0x14 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_54,Enable Set for level_vpac_out_0_en_utc0_complete_54" "0,1" newline bitfld.long 0x14 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_53,Enable Set for level_vpac_out_0_en_utc0_complete_53" "0,1" newline bitfld.long 0x14 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_52,Enable Set for level_vpac_out_0_en_utc0_complete_52" "0,1" newline bitfld.long 0x14 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_51,Enable Set for level_vpac_out_0_en_utc0_complete_51" "0,1" newline bitfld.long 0x14 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_50,Enable Set for level_vpac_out_0_en_utc0_complete_50" "0,1" newline bitfld.long 0x14 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_49,Enable Set for level_vpac_out_0_en_utc0_complete_49" "0,1" newline bitfld.long 0x14 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_48,Enable Set for level_vpac_out_0_en_utc0_complete_48" "0,1" newline bitfld.long 0x14 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_47,Enable Set for level_vpac_out_0_en_utc0_complete_47" "0,1" newline bitfld.long 0x14 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_46,Enable Set for level_vpac_out_0_en_utc0_complete_46" "0,1" newline bitfld.long 0x14 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_45,Enable Set for level_vpac_out_0_en_utc0_complete_45" "0,1" newline bitfld.long 0x14 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_44,Enable Set for level_vpac_out_0_en_utc0_complete_44" "0,1" newline bitfld.long 0x14 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_43,Enable Set for level_vpac_out_0_en_utc0_complete_43" "0,1" newline bitfld.long 0x14 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_42,Enable Set for level_vpac_out_0_en_utc0_complete_42" "0,1" newline bitfld.long 0x14 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_41,Enable Set for level_vpac_out_0_en_utc0_complete_41" "0,1" newline bitfld.long 0x14 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_40,Enable Set for level_vpac_out_0_en_utc0_complete_40" "0,1" newline bitfld.long 0x14 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_39,Enable Set for level_vpac_out_0_en_utc0_complete_39" "0,1" newline bitfld.long 0x14 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_38,Enable Set for level_vpac_out_0_en_utc0_complete_38" "0,1" newline bitfld.long 0x14 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_37,Enable Set for level_vpac_out_0_en_utc0_complete_37" "0,1" newline bitfld.long 0x14 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_36,Enable Set for level_vpac_out_0_en_utc0_complete_36" "0,1" newline bitfld.long 0x14 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_35,Enable Set for level_vpac_out_0_en_utc0_complete_35" "0,1" newline bitfld.long 0x14 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_34,Enable Set for level_vpac_out_0_en_utc0_complete_34" "0,1" newline bitfld.long 0x14 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_33,Enable Set for level_vpac_out_0_en_utc0_complete_33" "0,1" newline bitfld.long 0x14 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_32,Enable Set for level_vpac_out_0_en_utc0_complete_32" "0,1" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_6,Enable Register 6" bitfld.long 0x18 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_RSVD_UNUSED,Enable Set for level_vpac_out_0_en_utc1_rsvd_unused" "0,1" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_0_7,Enable Register 7" bitfld.long 0x1C 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_CTM_PULSE,Enable Set for level_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x1C 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0x1C 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_ERROR,Enable Set for level_vpac_out_0_en_utc0_error" "0,1" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_0,Enable Register 8" bitfld.long 0x20 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_DPC_STATS_READ_ERR,Enable Set for level_vpac_out_1_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x20 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_CR_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x20 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for level_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x20 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x20 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x20 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x20 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x20 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x20 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x20 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x20 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x20 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x20 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x20 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x20 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x20 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x20 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x20 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x20 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x20 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x20 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x20 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x20 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x20 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x20 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x20 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x20 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x20 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_1,Enable Register 9" bitfld.long 0x24 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x24 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x24 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x24 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x24 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x24 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x24 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x24 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x24 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_2,Enable Register 10" bitfld.long 0x28 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x28 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x28 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x28 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_3,Enable Register 11" bitfld.long 0x2C 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x2C 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x2C 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x2C 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x2C 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x2C 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_1_en_spare_pend_1_level" "0,1" newline bitfld.long 0x2C 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_1_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x2C 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_1_en_spare_pend_0_level" "0,1" newline bitfld.long 0x2C 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_1_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x2C 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_DEC_1,Enable Set for level_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x2C 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_DEC_0,Enable Set for level_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x2C 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_6,Enable Set for level_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0x2C 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_5,Enable Set for level_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0x2C 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_4,Enable Set for level_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0x2C 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_2,Enable Set for level_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0x2C 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_0,Enable Set for level_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0x2C 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_6,Enable Set for level_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0x2C 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_5,Enable Set for level_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0x2C 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_4,Enable Set for level_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0x2C 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_3,Enable Set for level_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x2C 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_2,Enable Set for level_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x2C 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_1,Enable Set for level_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x2C 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_0,Enable Set for level_vpac_out_1_en_pipe_done_0" "0,1" line.long 0x30 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_4,Enable Register 12" bitfld.long 0x30 31. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0x30 30. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0x30 29. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0x30 28. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0x30 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0x30 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0x30 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0x30 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0x30 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0x30 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0x30 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0x30 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0x30 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0x30 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0x30 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0x30 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0x30 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0x30 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0x30 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0x30 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0x30 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0x30 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0x30 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0x30 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0x30 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0x30 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0x30 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0x30 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0x30 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0x30 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0x30 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0x30 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_5,Enable Register 13" bitfld.long 0x34 31. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_63,Enable Set for level_vpac_out_1_en_utc0_complete_63" "0,1" newline bitfld.long 0x34 30. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_62,Enable Set for level_vpac_out_1_en_utc0_complete_62" "0,1" newline bitfld.long 0x34 29. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_61,Enable Set for level_vpac_out_1_en_utc0_complete_61" "0,1" newline bitfld.long 0x34 28. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_60,Enable Set for level_vpac_out_1_en_utc0_complete_60" "0,1" newline bitfld.long 0x34 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_59,Enable Set for level_vpac_out_1_en_utc0_complete_59" "0,1" newline bitfld.long 0x34 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_58,Enable Set for level_vpac_out_1_en_utc0_complete_58" "0,1" newline bitfld.long 0x34 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_57,Enable Set for level_vpac_out_1_en_utc0_complete_57" "0,1" newline bitfld.long 0x34 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_56,Enable Set for level_vpac_out_1_en_utc0_complete_56" "0,1" newline bitfld.long 0x34 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_55,Enable Set for level_vpac_out_1_en_utc0_complete_55" "0,1" newline bitfld.long 0x34 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_54,Enable Set for level_vpac_out_1_en_utc0_complete_54" "0,1" newline bitfld.long 0x34 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_53,Enable Set for level_vpac_out_1_en_utc0_complete_53" "0,1" newline bitfld.long 0x34 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_52,Enable Set for level_vpac_out_1_en_utc0_complete_52" "0,1" newline bitfld.long 0x34 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_51,Enable Set for level_vpac_out_1_en_utc0_complete_51" "0,1" newline bitfld.long 0x34 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_50,Enable Set for level_vpac_out_1_en_utc0_complete_50" "0,1" newline bitfld.long 0x34 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_49,Enable Set for level_vpac_out_1_en_utc0_complete_49" "0,1" newline bitfld.long 0x34 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_48,Enable Set for level_vpac_out_1_en_utc0_complete_48" "0,1" newline bitfld.long 0x34 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_47,Enable Set for level_vpac_out_1_en_utc0_complete_47" "0,1" newline bitfld.long 0x34 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_46,Enable Set for level_vpac_out_1_en_utc0_complete_46" "0,1" newline bitfld.long 0x34 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_45,Enable Set for level_vpac_out_1_en_utc0_complete_45" "0,1" newline bitfld.long 0x34 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_44,Enable Set for level_vpac_out_1_en_utc0_complete_44" "0,1" newline bitfld.long 0x34 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_43,Enable Set for level_vpac_out_1_en_utc0_complete_43" "0,1" newline bitfld.long 0x34 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_42,Enable Set for level_vpac_out_1_en_utc0_complete_42" "0,1" newline bitfld.long 0x34 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_41,Enable Set for level_vpac_out_1_en_utc0_complete_41" "0,1" newline bitfld.long 0x34 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_40,Enable Set for level_vpac_out_1_en_utc0_complete_40" "0,1" newline bitfld.long 0x34 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_39,Enable Set for level_vpac_out_1_en_utc0_complete_39" "0,1" newline bitfld.long 0x34 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_38,Enable Set for level_vpac_out_1_en_utc0_complete_38" "0,1" newline bitfld.long 0x34 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_37,Enable Set for level_vpac_out_1_en_utc0_complete_37" "0,1" newline bitfld.long 0x34 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_36,Enable Set for level_vpac_out_1_en_utc0_complete_36" "0,1" newline bitfld.long 0x34 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_35,Enable Set for level_vpac_out_1_en_utc0_complete_35" "0,1" newline bitfld.long 0x34 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_34,Enable Set for level_vpac_out_1_en_utc0_complete_34" "0,1" newline bitfld.long 0x34 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_33,Enable Set for level_vpac_out_1_en_utc0_complete_33" "0,1" newline bitfld.long 0x34 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_32,Enable Set for level_vpac_out_1_en_utc0_complete_32" "0,1" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_6,Enable Register 14" bitfld.long 0x38 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_RSVD_UNUSED,Enable Set for level_vpac_out_1_en_utc1_rsvd_unused" "0,1" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_1_7,Enable Register 15" bitfld.long 0x3C 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_CTM_PULSE,Enable Set for level_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x3C 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0x3C 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_ERROR,Enable Set for level_vpac_out_1_en_utc0_error" "0,1" line.long 0x40 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_0,Enable Register 16" bitfld.long 0x40 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_DPC_STATS_READ_ERR,Enable Set for level_vpac_out_2_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x40 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_CR_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x40 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for level_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x40 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x40 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x40 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x40 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x40 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x40 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x40 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x40 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x40 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x40 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x40 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x40 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x40 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x40 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x40 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x40 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x40 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x40 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x40 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x40 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x40 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x40 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x40 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x40 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x40 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x44 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_1,Enable Register 17" bitfld.long 0x44 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x44 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x44 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x44 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x44 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x44 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x44 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x44 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x44 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x48 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_2,Enable Register 18" bitfld.long 0x48 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x48 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x48 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x48 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x4C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_3,Enable Register 19" bitfld.long 0x4C 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x4C 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x4C 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x4C 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x4C 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x4C 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_2_en_spare_pend_1_level" "0,1" newline bitfld.long 0x4C 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_2_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x4C 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_2_en_spare_pend_0_level" "0,1" newline bitfld.long 0x4C 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_2_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x4C 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_DEC_1,Enable Set for level_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x4C 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_DEC_0,Enable Set for level_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x4C 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_6,Enable Set for level_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x4C 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_5,Enable Set for level_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x4C 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_4,Enable Set for level_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x4C 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_2,Enable Set for level_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x4C 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_0,Enable Set for level_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x4C 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_6,Enable Set for level_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x4C 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_5,Enable Set for level_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x4C 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_4,Enable Set for level_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x4C 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_3,Enable Set for level_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x4C 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_2,Enable Set for level_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x4C 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_1,Enable Set for level_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x4C 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_0,Enable Set for level_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x50 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_4,Enable Register 20" bitfld.long 0x50 31. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x50 30. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x50 29. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x50 28. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x50 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x50 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x50 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x50 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x50 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x50 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x50 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x50 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x50 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x50 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x50 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x50 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x50 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x50 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x50 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x50 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x50 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x50 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x50 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x50 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x50 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x50 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x50 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x50 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x50 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x50 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x50 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x50 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x54 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_5,Enable Register 21" bitfld.long 0x54 31. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_63,Enable Set for level_vpac_out_2_en_utc0_complete_63" "0,1" newline bitfld.long 0x54 30. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_62,Enable Set for level_vpac_out_2_en_utc0_complete_62" "0,1" newline bitfld.long 0x54 29. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_61,Enable Set for level_vpac_out_2_en_utc0_complete_61" "0,1" newline bitfld.long 0x54 28. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_60,Enable Set for level_vpac_out_2_en_utc0_complete_60" "0,1" newline bitfld.long 0x54 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_59,Enable Set for level_vpac_out_2_en_utc0_complete_59" "0,1" newline bitfld.long 0x54 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_58,Enable Set for level_vpac_out_2_en_utc0_complete_58" "0,1" newline bitfld.long 0x54 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_57,Enable Set for level_vpac_out_2_en_utc0_complete_57" "0,1" newline bitfld.long 0x54 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_56,Enable Set for level_vpac_out_2_en_utc0_complete_56" "0,1" newline bitfld.long 0x54 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_55,Enable Set for level_vpac_out_2_en_utc0_complete_55" "0,1" newline bitfld.long 0x54 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_54,Enable Set for level_vpac_out_2_en_utc0_complete_54" "0,1" newline bitfld.long 0x54 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_53,Enable Set for level_vpac_out_2_en_utc0_complete_53" "0,1" newline bitfld.long 0x54 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_52,Enable Set for level_vpac_out_2_en_utc0_complete_52" "0,1" newline bitfld.long 0x54 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_51,Enable Set for level_vpac_out_2_en_utc0_complete_51" "0,1" newline bitfld.long 0x54 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_50,Enable Set for level_vpac_out_2_en_utc0_complete_50" "0,1" newline bitfld.long 0x54 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_49,Enable Set for level_vpac_out_2_en_utc0_complete_49" "0,1" newline bitfld.long 0x54 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_48,Enable Set for level_vpac_out_2_en_utc0_complete_48" "0,1" newline bitfld.long 0x54 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_47,Enable Set for level_vpac_out_2_en_utc0_complete_47" "0,1" newline bitfld.long 0x54 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_46,Enable Set for level_vpac_out_2_en_utc0_complete_46" "0,1" newline bitfld.long 0x54 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_45,Enable Set for level_vpac_out_2_en_utc0_complete_45" "0,1" newline bitfld.long 0x54 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_44,Enable Set for level_vpac_out_2_en_utc0_complete_44" "0,1" newline bitfld.long 0x54 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_43,Enable Set for level_vpac_out_2_en_utc0_complete_43" "0,1" newline bitfld.long 0x54 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_42,Enable Set for level_vpac_out_2_en_utc0_complete_42" "0,1" newline bitfld.long 0x54 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_41,Enable Set for level_vpac_out_2_en_utc0_complete_41" "0,1" newline bitfld.long 0x54 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_40,Enable Set for level_vpac_out_2_en_utc0_complete_40" "0,1" newline bitfld.long 0x54 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_39,Enable Set for level_vpac_out_2_en_utc0_complete_39" "0,1" newline bitfld.long 0x54 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_38,Enable Set for level_vpac_out_2_en_utc0_complete_38" "0,1" newline bitfld.long 0x54 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_37,Enable Set for level_vpac_out_2_en_utc0_complete_37" "0,1" newline bitfld.long 0x54 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_36,Enable Set for level_vpac_out_2_en_utc0_complete_36" "0,1" newline bitfld.long 0x54 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_35,Enable Set for level_vpac_out_2_en_utc0_complete_35" "0,1" newline bitfld.long 0x54 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_34,Enable Set for level_vpac_out_2_en_utc0_complete_34" "0,1" newline bitfld.long 0x54 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_33,Enable Set for level_vpac_out_2_en_utc0_complete_33" "0,1" newline bitfld.long 0x54 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_32,Enable Set for level_vpac_out_2_en_utc0_complete_32" "0,1" line.long 0x58 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_6,Enable Register 22" bitfld.long 0x58 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_RSVD_UNUSED,Enable Set for level_vpac_out_2_en_utc1_rsvd_unused" "0,1" line.long 0x5C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_2_7,Enable Register 23" bitfld.long 0x5C 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_CTM_PULSE,Enable Set for level_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x5C 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x5C 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_ERROR,Enable Set for level_vpac_out_2_en_utc0_error" "0,1" line.long 0x60 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_0,Enable Register 24" bitfld.long 0x60 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_DPC_STATS_READ_ERR,Enable Set for level_vpac_out_3_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x60 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_CR_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x60 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for level_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x60 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x60 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x60 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x60 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x60 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x60 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x60 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x60 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x60 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x60 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x60 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x60 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x60 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x60 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x60 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x60 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x60 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x60 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x60 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x60 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x60 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x60 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x60 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x60 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x60 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x64 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_1,Enable Register 25" bitfld.long 0x64 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x64 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x64 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x64 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x64 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x64 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x64 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x64 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x64 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x68 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_2,Enable Register 26" bitfld.long 0x68 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x68 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x68 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x68 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x6C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_3,Enable Register 27" bitfld.long 0x6C 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x6C 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x6C 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x6C 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x6C 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x6C 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_3_en_spare_pend_1_level" "0,1" newline bitfld.long 0x6C 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_3_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x6C 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_3_en_spare_pend_0_level" "0,1" newline bitfld.long 0x6C 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_3_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x6C 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_DEC_1,Enable Set for level_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x6C 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_DEC_0,Enable Set for level_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x6C 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_6,Enable Set for level_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x6C 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_5,Enable Set for level_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x6C 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_4,Enable Set for level_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x6C 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_2,Enable Set for level_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x6C 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_0,Enable Set for level_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x6C 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_6,Enable Set for level_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x6C 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_5,Enable Set for level_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x6C 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_4,Enable Set for level_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x6C 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_3,Enable Set for level_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x6C 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_2,Enable Set for level_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x6C 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_1,Enable Set for level_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x6C 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_0,Enable Set for level_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x70 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_4,Enable Register 28" bitfld.long 0x70 31. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x70 30. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x70 29. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x70 28. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x70 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x70 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x70 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x70 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x70 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x70 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x70 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x70 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x70 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x70 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x70 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x70 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x70 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x70 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x70 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x70 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x70 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x70 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x70 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x70 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x70 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x70 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x70 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x70 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x70 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x70 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x70 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x70 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x74 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_5,Enable Register 29" bitfld.long 0x74 31. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_63,Enable Set for level_vpac_out_3_en_utc0_complete_63" "0,1" newline bitfld.long 0x74 30. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_62,Enable Set for level_vpac_out_3_en_utc0_complete_62" "0,1" newline bitfld.long 0x74 29. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_61,Enable Set for level_vpac_out_3_en_utc0_complete_61" "0,1" newline bitfld.long 0x74 28. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_60,Enable Set for level_vpac_out_3_en_utc0_complete_60" "0,1" newline bitfld.long 0x74 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_59,Enable Set for level_vpac_out_3_en_utc0_complete_59" "0,1" newline bitfld.long 0x74 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_58,Enable Set for level_vpac_out_3_en_utc0_complete_58" "0,1" newline bitfld.long 0x74 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_57,Enable Set for level_vpac_out_3_en_utc0_complete_57" "0,1" newline bitfld.long 0x74 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_56,Enable Set for level_vpac_out_3_en_utc0_complete_56" "0,1" newline bitfld.long 0x74 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_55,Enable Set for level_vpac_out_3_en_utc0_complete_55" "0,1" newline bitfld.long 0x74 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_54,Enable Set for level_vpac_out_3_en_utc0_complete_54" "0,1" newline bitfld.long 0x74 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_53,Enable Set for level_vpac_out_3_en_utc0_complete_53" "0,1" newline bitfld.long 0x74 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_52,Enable Set for level_vpac_out_3_en_utc0_complete_52" "0,1" newline bitfld.long 0x74 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_51,Enable Set for level_vpac_out_3_en_utc0_complete_51" "0,1" newline bitfld.long 0x74 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_50,Enable Set for level_vpac_out_3_en_utc0_complete_50" "0,1" newline bitfld.long 0x74 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_49,Enable Set for level_vpac_out_3_en_utc0_complete_49" "0,1" newline bitfld.long 0x74 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_48,Enable Set for level_vpac_out_3_en_utc0_complete_48" "0,1" newline bitfld.long 0x74 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_47,Enable Set for level_vpac_out_3_en_utc0_complete_47" "0,1" newline bitfld.long 0x74 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_46,Enable Set for level_vpac_out_3_en_utc0_complete_46" "0,1" newline bitfld.long 0x74 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_45,Enable Set for level_vpac_out_3_en_utc0_complete_45" "0,1" newline bitfld.long 0x74 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_44,Enable Set for level_vpac_out_3_en_utc0_complete_44" "0,1" newline bitfld.long 0x74 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_43,Enable Set for level_vpac_out_3_en_utc0_complete_43" "0,1" newline bitfld.long 0x74 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_42,Enable Set for level_vpac_out_3_en_utc0_complete_42" "0,1" newline bitfld.long 0x74 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_41,Enable Set for level_vpac_out_3_en_utc0_complete_41" "0,1" newline bitfld.long 0x74 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_40,Enable Set for level_vpac_out_3_en_utc0_complete_40" "0,1" newline bitfld.long 0x74 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_39,Enable Set for level_vpac_out_3_en_utc0_complete_39" "0,1" newline bitfld.long 0x74 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_38,Enable Set for level_vpac_out_3_en_utc0_complete_38" "0,1" newline bitfld.long 0x74 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_37,Enable Set for level_vpac_out_3_en_utc0_complete_37" "0,1" newline bitfld.long 0x74 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_36,Enable Set for level_vpac_out_3_en_utc0_complete_36" "0,1" newline bitfld.long 0x74 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_35,Enable Set for level_vpac_out_3_en_utc0_complete_35" "0,1" newline bitfld.long 0x74 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_34,Enable Set for level_vpac_out_3_en_utc0_complete_34" "0,1" newline bitfld.long 0x74 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_33,Enable Set for level_vpac_out_3_en_utc0_complete_33" "0,1" newline bitfld.long 0x74 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_32,Enable Set for level_vpac_out_3_en_utc0_complete_32" "0,1" line.long 0x78 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_6,Enable Register 30" bitfld.long 0x78 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_RSVD_UNUSED,Enable Set for level_vpac_out_3_en_utc1_rsvd_unused" "0,1" line.long 0x7C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_3_7,Enable Register 31" bitfld.long 0x7C 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_CTM_PULSE,Enable Set for level_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x7C 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x7C 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_ERROR,Enable Set for level_vpac_out_3_en_utc0_error" "0,1" line.long 0x80 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_0,Enable Register 32" bitfld.long 0x80 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_DPC_STATS_READ_ERR,Enable Set for level_vpac_out_4_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x80 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_CR_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x80 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for level_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x80 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x80 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x80 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x80 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x80 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x80 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x80 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x80 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x80 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x80 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x80 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x80 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x80 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x80 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x80 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x80 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x80 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x80 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x80 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x80 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x80 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x80 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x80 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x80 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x80 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x84 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_1,Enable Register 33" bitfld.long 0x84 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x84 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x84 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x84 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x84 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x84 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x84 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x84 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x84 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x88 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_2,Enable Register 34" bitfld.long 0x88 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x88 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x88 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x88 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x8C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_3,Enable Register 35" bitfld.long 0x8C 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x8C 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x8C 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x8C 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x8C 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x8C 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_4_en_spare_pend_1_level" "0,1" newline bitfld.long 0x8C 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_4_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x8C 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_4_en_spare_pend_0_level" "0,1" newline bitfld.long 0x8C 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_4_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x8C 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_DEC_1,Enable Set for level_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x8C 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_DEC_0,Enable Set for level_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x8C 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_6,Enable Set for level_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x8C 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_5,Enable Set for level_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x8C 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_4,Enable Set for level_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x8C 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_2,Enable Set for level_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x8C 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_0,Enable Set for level_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x8C 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_6,Enable Set for level_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x8C 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_5,Enable Set for level_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x8C 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_4,Enable Set for level_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x8C 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_3,Enable Set for level_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x8C 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_2,Enable Set for level_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x8C 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_1,Enable Set for level_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x8C 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_0,Enable Set for level_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x90 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_4,Enable Register 36" bitfld.long 0x90 31. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x90 30. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x90 29. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x90 28. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x90 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x90 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x90 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x90 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x90 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x90 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x90 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x90 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x90 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x90 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x90 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x90 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x90 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x90 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x90 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x90 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x90 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x90 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x90 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x90 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x90 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x90 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x90 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x90 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x90 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x90 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x90 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x90 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x94 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_5,Enable Register 37" bitfld.long 0x94 31. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_63,Enable Set for level_vpac_out_4_en_utc0_complete_63" "0,1" newline bitfld.long 0x94 30. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_62,Enable Set for level_vpac_out_4_en_utc0_complete_62" "0,1" newline bitfld.long 0x94 29. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_61,Enable Set for level_vpac_out_4_en_utc0_complete_61" "0,1" newline bitfld.long 0x94 28. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_60,Enable Set for level_vpac_out_4_en_utc0_complete_60" "0,1" newline bitfld.long 0x94 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_59,Enable Set for level_vpac_out_4_en_utc0_complete_59" "0,1" newline bitfld.long 0x94 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_58,Enable Set for level_vpac_out_4_en_utc0_complete_58" "0,1" newline bitfld.long 0x94 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_57,Enable Set for level_vpac_out_4_en_utc0_complete_57" "0,1" newline bitfld.long 0x94 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_56,Enable Set for level_vpac_out_4_en_utc0_complete_56" "0,1" newline bitfld.long 0x94 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_55,Enable Set for level_vpac_out_4_en_utc0_complete_55" "0,1" newline bitfld.long 0x94 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_54,Enable Set for level_vpac_out_4_en_utc0_complete_54" "0,1" newline bitfld.long 0x94 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_53,Enable Set for level_vpac_out_4_en_utc0_complete_53" "0,1" newline bitfld.long 0x94 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_52,Enable Set for level_vpac_out_4_en_utc0_complete_52" "0,1" newline bitfld.long 0x94 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_51,Enable Set for level_vpac_out_4_en_utc0_complete_51" "0,1" newline bitfld.long 0x94 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_50,Enable Set for level_vpac_out_4_en_utc0_complete_50" "0,1" newline bitfld.long 0x94 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_49,Enable Set for level_vpac_out_4_en_utc0_complete_49" "0,1" newline bitfld.long 0x94 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_48,Enable Set for level_vpac_out_4_en_utc0_complete_48" "0,1" newline bitfld.long 0x94 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_47,Enable Set for level_vpac_out_4_en_utc0_complete_47" "0,1" newline bitfld.long 0x94 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_46,Enable Set for level_vpac_out_4_en_utc0_complete_46" "0,1" newline bitfld.long 0x94 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_45,Enable Set for level_vpac_out_4_en_utc0_complete_45" "0,1" newline bitfld.long 0x94 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_44,Enable Set for level_vpac_out_4_en_utc0_complete_44" "0,1" newline bitfld.long 0x94 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_43,Enable Set for level_vpac_out_4_en_utc0_complete_43" "0,1" newline bitfld.long 0x94 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_42,Enable Set for level_vpac_out_4_en_utc0_complete_42" "0,1" newline bitfld.long 0x94 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_41,Enable Set for level_vpac_out_4_en_utc0_complete_41" "0,1" newline bitfld.long 0x94 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_40,Enable Set for level_vpac_out_4_en_utc0_complete_40" "0,1" newline bitfld.long 0x94 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_39,Enable Set for level_vpac_out_4_en_utc0_complete_39" "0,1" newline bitfld.long 0x94 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_38,Enable Set for level_vpac_out_4_en_utc0_complete_38" "0,1" newline bitfld.long 0x94 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_37,Enable Set for level_vpac_out_4_en_utc0_complete_37" "0,1" newline bitfld.long 0x94 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_36,Enable Set for level_vpac_out_4_en_utc0_complete_36" "0,1" newline bitfld.long 0x94 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_35,Enable Set for level_vpac_out_4_en_utc0_complete_35" "0,1" newline bitfld.long 0x94 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_34,Enable Set for level_vpac_out_4_en_utc0_complete_34" "0,1" newline bitfld.long 0x94 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_33,Enable Set for level_vpac_out_4_en_utc0_complete_33" "0,1" newline bitfld.long 0x94 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_32,Enable Set for level_vpac_out_4_en_utc0_complete_32" "0,1" line.long 0x98 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_6,Enable Register 38" bitfld.long 0x98 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_RSVD_UNUSED,Enable Set for level_vpac_out_4_en_utc1_rsvd_unused" "0,1" line.long 0x9C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_4_7,Enable Register 39" bitfld.long 0x9C 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_CTM_PULSE,Enable Set for level_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x9C 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x9C 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_ERROR,Enable Set for level_vpac_out_4_en_utc0_error" "0,1" line.long 0xA0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_0,Enable Register 40" bitfld.long 0xA0 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_DPC_STATS_READ_ERR,Enable Set for level_vpac_out_5_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0xA0 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_CR_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xA0 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for level_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xA0 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for level_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xA0 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for level_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xA0 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA0 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA0 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for level_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xA0 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for level_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xA0 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_EE_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xA0 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for level_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xA0 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for level_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xA0 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xA0 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCFA_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xA0 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_VP_ERR,Enable Set for level_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xA0 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for level_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xA0 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for level_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xA0 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_DONE,Enable Set for level_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xA0 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_START,Enable Set for level_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xA0 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xA0 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for level_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xA0 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for level_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xA0 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xA0 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for level_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xA0 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for level_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xA0 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_AF_PULSE,Enable Set for level_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xA0 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for level_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xA0 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_CFG_ERR,Enable Set for level_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0xA4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_1,Enable Register 41" bitfld.long 0xA4 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_VBUSM_RD_ERR,Enable Set for level_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xA4 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_SL2_WR_ERR,Enable Set for level_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xA4 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_FR_DONE_EVT,Enable Set for level_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xA4 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_INT_SZOVF,Enable Set for level_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xA4 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_IFR_OUTOFBOUND,Enable Set for level_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xA4 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for level_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xA4 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for level_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xA4 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xA4 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for level_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xA8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_2,Enable Register 42" bitfld.long 0xA8 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_SL2_WR_ERR,Enable Set for level_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA8 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_SL2_RD_ERR,Enable Set for level_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA8 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for level_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xA8 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for level_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xAC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_3,Enable Register 43" bitfld.long 0xAC 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_6,Enable Set for level_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xAC 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_5,Enable Set for level_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xAC 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_4,Enable Set for level_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xAC 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_2,Enable Set for level_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xAC 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_0,Enable Set for level_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xAC 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_1_LEVEL,Enable Set for level_vpac_out_5_en_spare_pend_1_level" "0,1" newline bitfld.long 0xAC 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_1_PULSE,Enable Set for level_vpac_out_5_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xAC 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_0_LEVEL,Enable Set for level_vpac_out_5_en_spare_pend_0_level" "0,1" newline bitfld.long 0xAC 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_0_PULSE,Enable Set for level_vpac_out_5_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xAC 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_DEC_1,Enable Set for level_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0xAC 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_DEC_0,Enable Set for level_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0xAC 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_6,Enable Set for level_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0xAC 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_5,Enable Set for level_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0xAC 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_4,Enable Set for level_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0xAC 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_2,Enable Set for level_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0xAC 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_0,Enable Set for level_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0xAC 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_6,Enable Set for level_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0xAC 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_5,Enable Set for level_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0xAC 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_4,Enable Set for level_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0xAC 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_3,Enable Set for level_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0xAC 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_2,Enable Set for level_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0xAC 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_1,Enable Set for level_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0xAC 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_0,Enable Set for level_vpac_out_5_en_pipe_done_0" "0,1" line.long 0xB0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_4,Enable Register 44" bitfld.long 0xB0 31. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_31,Enable Set for level_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0xB0 30. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_30,Enable Set for level_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0xB0 29. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_29,Enable Set for level_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0xB0 28. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_28,Enable Set for level_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0xB0 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_27,Enable Set for level_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0xB0 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_26,Enable Set for level_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0xB0 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_25,Enable Set for level_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0xB0 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_24,Enable Set for level_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0xB0 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_23,Enable Set for level_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0xB0 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_22,Enable Set for level_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0xB0 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_21,Enable Set for level_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0xB0 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_20,Enable Set for level_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0xB0 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_19,Enable Set for level_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0xB0 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_18,Enable Set for level_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0xB0 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_17,Enable Set for level_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0xB0 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_16,Enable Set for level_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0xB0 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_15,Enable Set for level_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0xB0 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_14,Enable Set for level_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0xB0 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_13,Enable Set for level_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0xB0 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_12,Enable Set for level_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0xB0 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_11,Enable Set for level_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0xB0 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_10,Enable Set for level_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0xB0 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_9,Enable Set for level_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0xB0 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_8,Enable Set for level_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0xB0 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_7,Enable Set for level_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0xB0 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_6,Enable Set for level_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0xB0 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_5,Enable Set for level_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0xB0 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_4,Enable Set for level_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0xB0 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_3,Enable Set for level_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0xB0 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_2,Enable Set for level_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0xB0 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_1,Enable Set for level_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0xB0 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_0,Enable Set for level_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0xB4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_5,Enable Register 45" bitfld.long 0xB4 31. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_63,Enable Set for level_vpac_out_5_en_utc0_complete_63" "0,1" newline bitfld.long 0xB4 30. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_62,Enable Set for level_vpac_out_5_en_utc0_complete_62" "0,1" newline bitfld.long 0xB4 29. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_61,Enable Set for level_vpac_out_5_en_utc0_complete_61" "0,1" newline bitfld.long 0xB4 28. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_60,Enable Set for level_vpac_out_5_en_utc0_complete_60" "0,1" newline bitfld.long 0xB4 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_59,Enable Set for level_vpac_out_5_en_utc0_complete_59" "0,1" newline bitfld.long 0xB4 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_58,Enable Set for level_vpac_out_5_en_utc0_complete_58" "0,1" newline bitfld.long 0xB4 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_57,Enable Set for level_vpac_out_5_en_utc0_complete_57" "0,1" newline bitfld.long 0xB4 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_56,Enable Set for level_vpac_out_5_en_utc0_complete_56" "0,1" newline bitfld.long 0xB4 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_55,Enable Set for level_vpac_out_5_en_utc0_complete_55" "0,1" newline bitfld.long 0xB4 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_54,Enable Set for level_vpac_out_5_en_utc0_complete_54" "0,1" newline bitfld.long 0xB4 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_53,Enable Set for level_vpac_out_5_en_utc0_complete_53" "0,1" newline bitfld.long 0xB4 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_52,Enable Set for level_vpac_out_5_en_utc0_complete_52" "0,1" newline bitfld.long 0xB4 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_51,Enable Set for level_vpac_out_5_en_utc0_complete_51" "0,1" newline bitfld.long 0xB4 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_50,Enable Set for level_vpac_out_5_en_utc0_complete_50" "0,1" newline bitfld.long 0xB4 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_49,Enable Set for level_vpac_out_5_en_utc0_complete_49" "0,1" newline bitfld.long 0xB4 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_48,Enable Set for level_vpac_out_5_en_utc0_complete_48" "0,1" newline bitfld.long 0xB4 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_47,Enable Set for level_vpac_out_5_en_utc0_complete_47" "0,1" newline bitfld.long 0xB4 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_46,Enable Set for level_vpac_out_5_en_utc0_complete_46" "0,1" newline bitfld.long 0xB4 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_45,Enable Set for level_vpac_out_5_en_utc0_complete_45" "0,1" newline bitfld.long 0xB4 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_44,Enable Set for level_vpac_out_5_en_utc0_complete_44" "0,1" newline bitfld.long 0xB4 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_43,Enable Set for level_vpac_out_5_en_utc0_complete_43" "0,1" newline bitfld.long 0xB4 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_42,Enable Set for level_vpac_out_5_en_utc0_complete_42" "0,1" newline bitfld.long 0xB4 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_41,Enable Set for level_vpac_out_5_en_utc0_complete_41" "0,1" newline bitfld.long 0xB4 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_40,Enable Set for level_vpac_out_5_en_utc0_complete_40" "0,1" newline bitfld.long 0xB4 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_39,Enable Set for level_vpac_out_5_en_utc0_complete_39" "0,1" newline bitfld.long 0xB4 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_38,Enable Set for level_vpac_out_5_en_utc0_complete_38" "0,1" newline bitfld.long 0xB4 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_37,Enable Set for level_vpac_out_5_en_utc0_complete_37" "0,1" newline bitfld.long 0xB4 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_36,Enable Set for level_vpac_out_5_en_utc0_complete_36" "0,1" newline bitfld.long 0xB4 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_35,Enable Set for level_vpac_out_5_en_utc0_complete_35" "0,1" newline bitfld.long 0xB4 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_34,Enable Set for level_vpac_out_5_en_utc0_complete_34" "0,1" newline bitfld.long 0xB4 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_33,Enable Set for level_vpac_out_5_en_utc0_complete_33" "0,1" newline bitfld.long 0xB4 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_32,Enable Set for level_vpac_out_5_en_utc0_complete_32" "0,1" line.long 0xB8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_6,Enable Register 46" bitfld.long 0xB8 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_RSVD_UNUSED,Enable Set for level_vpac_out_5_en_utc1_rsvd_unused" "0,1" line.long 0xBC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_vpac_out_5_7,Enable Register 47" bitfld.long 0xBC 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_CTM_PULSE,Enable Set for level_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0xBC 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_PROT_ERR,Enable Set for level_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0xBC 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_ERROR,Enable Set for level_vpac_out_5_en_utc0_error" "0,1" line.long 0xC0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_0,Enable Register 48" bitfld.long 0xC0 27. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_DPC_STATS_READ_ERR,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0xC0 26. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_CR_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xC0 25. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xC0 24. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xC0 23. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xC0 22. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC0 21. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC0 20. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xC0 19. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xC0 18. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xC0 17. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xC0 16. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xC0 15. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xC0 14. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xC0 13. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xC0 12. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xC0 11. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xC0 10. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xC0 9. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xC0 8. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xC0 7. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xC0 6. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xC0 5. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xC0 4. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xC0 3. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xC0 2. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xC0 1. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xC0 0. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0xC4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_1,Enable Register 49" bitfld.long 0xC4 8. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xC4 7. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xC4 6. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xC4 5. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xC4 4. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xC4 3. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xC4 2. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xC4 1. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xC4 0. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xC8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_2,Enable Register 50" bitfld.long 0xC8 3. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC8 2. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC8 1. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xC8 0. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xCC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_3,Enable Register 51" bitfld.long 0xCC 26. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xCC 25. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xCC 24. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xCC 22. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xCC 20. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xCC 19. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_0_en_spare_pend_1_level" "0,1" newline bitfld.long 0xCC 18. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_0_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xCC 17. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_0_en_spare_pend_0_level" "0,1" newline bitfld.long 0xCC 16. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_0_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xCC 15. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xCC 14. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xCC 13. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_6,Enable Set for pulse_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xCC 12. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_5,Enable Set for pulse_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xCC 11. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_4,Enable Set for pulse_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xCC 9. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_2,Enable Set for pulse_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xCC 7. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_0,Enable Set for pulse_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xCC 6. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xCC 5. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xCC 4. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xCC 3. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xCC 2. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xCC 1. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xCC 0. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_0_en_pipe_done_0" "0,1" line.long 0xD0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_4,Enable Register 52" bitfld.long 0xD0 31. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0xD0 30. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0xD0 29. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0xD0 28. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0xD0 27. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0xD0 26. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0xD0 25. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0xD0 24. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0xD0 23. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0xD0 22. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0xD0 21. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0xD0 20. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0xD0 19. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0xD0 18. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0xD0 17. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0xD0 16. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0xD0 15. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0xD0 14. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0xD0 13. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0xD0 12. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0xD0 11. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0xD0 10. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0xD0 9. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0xD0 8. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0xD0 7. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0xD0 6. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0xD0 5. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0xD0 4. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0xD0 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0xD0 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0xD0 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0xD0 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0xD4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_5,Enable Register 53" bitfld.long 0xD4 31. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_63,Enable Set for pulse_vpac_out_0_en_utc0_complete_63" "0,1" newline bitfld.long 0xD4 30. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_62,Enable Set for pulse_vpac_out_0_en_utc0_complete_62" "0,1" newline bitfld.long 0xD4 29. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_61,Enable Set for pulse_vpac_out_0_en_utc0_complete_61" "0,1" newline bitfld.long 0xD4 28. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_60,Enable Set for pulse_vpac_out_0_en_utc0_complete_60" "0,1" newline bitfld.long 0xD4 27. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_59,Enable Set for pulse_vpac_out_0_en_utc0_complete_59" "0,1" newline bitfld.long 0xD4 26. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_58,Enable Set for pulse_vpac_out_0_en_utc0_complete_58" "0,1" newline bitfld.long 0xD4 25. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_57,Enable Set for pulse_vpac_out_0_en_utc0_complete_57" "0,1" newline bitfld.long 0xD4 24. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_56,Enable Set for pulse_vpac_out_0_en_utc0_complete_56" "0,1" newline bitfld.long 0xD4 23. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_55,Enable Set for pulse_vpac_out_0_en_utc0_complete_55" "0,1" newline bitfld.long 0xD4 22. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_54,Enable Set for pulse_vpac_out_0_en_utc0_complete_54" "0,1" newline bitfld.long 0xD4 21. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_53,Enable Set for pulse_vpac_out_0_en_utc0_complete_53" "0,1" newline bitfld.long 0xD4 20. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_52,Enable Set for pulse_vpac_out_0_en_utc0_complete_52" "0,1" newline bitfld.long 0xD4 19. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_51,Enable Set for pulse_vpac_out_0_en_utc0_complete_51" "0,1" newline bitfld.long 0xD4 18. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_50,Enable Set for pulse_vpac_out_0_en_utc0_complete_50" "0,1" newline bitfld.long 0xD4 17. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_49,Enable Set for pulse_vpac_out_0_en_utc0_complete_49" "0,1" newline bitfld.long 0xD4 16. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_48,Enable Set for pulse_vpac_out_0_en_utc0_complete_48" "0,1" newline bitfld.long 0xD4 15. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_47,Enable Set for pulse_vpac_out_0_en_utc0_complete_47" "0,1" newline bitfld.long 0xD4 14. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_46,Enable Set for pulse_vpac_out_0_en_utc0_complete_46" "0,1" newline bitfld.long 0xD4 13. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_45,Enable Set for pulse_vpac_out_0_en_utc0_complete_45" "0,1" newline bitfld.long 0xD4 12. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_44,Enable Set for pulse_vpac_out_0_en_utc0_complete_44" "0,1" newline bitfld.long 0xD4 11. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_43,Enable Set for pulse_vpac_out_0_en_utc0_complete_43" "0,1" newline bitfld.long 0xD4 10. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_42,Enable Set for pulse_vpac_out_0_en_utc0_complete_42" "0,1" newline bitfld.long 0xD4 9. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_41,Enable Set for pulse_vpac_out_0_en_utc0_complete_41" "0,1" newline bitfld.long 0xD4 8. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_40,Enable Set for pulse_vpac_out_0_en_utc0_complete_40" "0,1" newline bitfld.long 0xD4 7. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_39,Enable Set for pulse_vpac_out_0_en_utc0_complete_39" "0,1" newline bitfld.long 0xD4 6. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_38,Enable Set for pulse_vpac_out_0_en_utc0_complete_38" "0,1" newline bitfld.long 0xD4 5. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_37,Enable Set for pulse_vpac_out_0_en_utc0_complete_37" "0,1" newline bitfld.long 0xD4 4. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_36,Enable Set for pulse_vpac_out_0_en_utc0_complete_36" "0,1" newline bitfld.long 0xD4 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_35,Enable Set for pulse_vpac_out_0_en_utc0_complete_35" "0,1" newline bitfld.long 0xD4 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_34,Enable Set for pulse_vpac_out_0_en_utc0_complete_34" "0,1" newline bitfld.long 0xD4 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_33,Enable Set for pulse_vpac_out_0_en_utc0_complete_33" "0,1" newline bitfld.long 0xD4 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_32,Enable Set for pulse_vpac_out_0_en_utc0_complete_32" "0,1" line.long 0xD8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_6,Enable Register 54" bitfld.long 0xD8 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_RSVD_UNUSED,Enable Set for pulse_vpac_out_0_en_utc1_rsvd_unused" "0,1" line.long 0xDC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_0_7,Enable Register 55" bitfld.long 0xDC 4. "ENABLE_PULSE_VPAC_OUT_0_EN_CTM_PULSE,Enable Set for pulse_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0xDC 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0xDC 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_0_en_utc0_error" "0,1" line.long 0xE0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_0,Enable Register 56" bitfld.long 0xE0 27. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_DPC_STATS_READ_ERR,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0xE0 26. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_CR_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xE0 25. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xE0 24. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xE0 23. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xE0 22. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE0 21. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE0 20. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xE0 19. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xE0 18. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xE0 17. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xE0 16. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xE0 15. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xE0 14. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xE0 13. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xE0 12. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xE0 11. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xE0 10. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xE0 9. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xE0 8. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xE0 7. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xE0 6. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xE0 5. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xE0 4. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xE0 3. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xE0 2. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xE0 1. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xE0 0. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0xE4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_1,Enable Register 57" bitfld.long 0xE4 8. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xE4 7. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xE4 6. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xE4 5. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xE4 4. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xE4 3. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xE4 2. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xE4 1. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xE4 0. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xE8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_2,Enable Register 58" bitfld.long 0xE8 3. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE8 2. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE8 1. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xE8 0. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xEC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_3,Enable Register 59" bitfld.long 0xEC 26. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xEC 25. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xEC 24. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xEC 22. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xEC 20. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xEC 19. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_1_en_spare_pend_1_level" "0,1" newline bitfld.long 0xEC 18. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_1_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xEC 17. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_1_en_spare_pend_0_level" "0,1" newline bitfld.long 0xEC 16. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_1_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xEC 15. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0xEC 14. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0xEC 13. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_6,Enable Set for pulse_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0xEC 12. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_5,Enable Set for pulse_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0xEC 11. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_4,Enable Set for pulse_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0xEC 9. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_2,Enable Set for pulse_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0xEC 7. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_0,Enable Set for pulse_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0xEC 6. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0xEC 5. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0xEC 4. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0xEC 3. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0xEC 2. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0xEC 1. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0xEC 0. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_1_en_pipe_done_0" "0,1" line.long 0xF0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_4,Enable Register 60" bitfld.long 0xF0 31. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0xF0 30. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0xF0 29. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0xF0 28. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0xF0 27. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0xF0 26. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0xF0 25. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0xF0 24. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0xF0 23. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0xF0 22. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0xF0 21. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0xF0 20. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0xF0 19. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0xF0 18. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0xF0 17. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0xF0 16. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0xF0 15. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0xF0 14. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0xF0 13. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0xF0 12. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0xF0 11. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0xF0 10. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0xF0 9. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0xF0 8. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0xF0 7. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0xF0 6. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0xF0 5. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0xF0 4. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0xF0 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0xF0 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0xF0 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0xF0 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0xF4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_5,Enable Register 61" bitfld.long 0xF4 31. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_63,Enable Set for pulse_vpac_out_1_en_utc0_complete_63" "0,1" newline bitfld.long 0xF4 30. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_62,Enable Set for pulse_vpac_out_1_en_utc0_complete_62" "0,1" newline bitfld.long 0xF4 29. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_61,Enable Set for pulse_vpac_out_1_en_utc0_complete_61" "0,1" newline bitfld.long 0xF4 28. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_60,Enable Set for pulse_vpac_out_1_en_utc0_complete_60" "0,1" newline bitfld.long 0xF4 27. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_59,Enable Set for pulse_vpac_out_1_en_utc0_complete_59" "0,1" newline bitfld.long 0xF4 26. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_58,Enable Set for pulse_vpac_out_1_en_utc0_complete_58" "0,1" newline bitfld.long 0xF4 25. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_57,Enable Set for pulse_vpac_out_1_en_utc0_complete_57" "0,1" newline bitfld.long 0xF4 24. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_56,Enable Set for pulse_vpac_out_1_en_utc0_complete_56" "0,1" newline bitfld.long 0xF4 23. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_55,Enable Set for pulse_vpac_out_1_en_utc0_complete_55" "0,1" newline bitfld.long 0xF4 22. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_54,Enable Set for pulse_vpac_out_1_en_utc0_complete_54" "0,1" newline bitfld.long 0xF4 21. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_53,Enable Set for pulse_vpac_out_1_en_utc0_complete_53" "0,1" newline bitfld.long 0xF4 20. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_52,Enable Set for pulse_vpac_out_1_en_utc0_complete_52" "0,1" newline bitfld.long 0xF4 19. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_51,Enable Set for pulse_vpac_out_1_en_utc0_complete_51" "0,1" newline bitfld.long 0xF4 18. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_50,Enable Set for pulse_vpac_out_1_en_utc0_complete_50" "0,1" newline bitfld.long 0xF4 17. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_49,Enable Set for pulse_vpac_out_1_en_utc0_complete_49" "0,1" newline bitfld.long 0xF4 16. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_48,Enable Set for pulse_vpac_out_1_en_utc0_complete_48" "0,1" newline bitfld.long 0xF4 15. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_47,Enable Set for pulse_vpac_out_1_en_utc0_complete_47" "0,1" newline bitfld.long 0xF4 14. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_46,Enable Set for pulse_vpac_out_1_en_utc0_complete_46" "0,1" newline bitfld.long 0xF4 13. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_45,Enable Set for pulse_vpac_out_1_en_utc0_complete_45" "0,1" newline bitfld.long 0xF4 12. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_44,Enable Set for pulse_vpac_out_1_en_utc0_complete_44" "0,1" newline bitfld.long 0xF4 11. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_43,Enable Set for pulse_vpac_out_1_en_utc0_complete_43" "0,1" newline bitfld.long 0xF4 10. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_42,Enable Set for pulse_vpac_out_1_en_utc0_complete_42" "0,1" newline bitfld.long 0xF4 9. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_41,Enable Set for pulse_vpac_out_1_en_utc0_complete_41" "0,1" newline bitfld.long 0xF4 8. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_40,Enable Set for pulse_vpac_out_1_en_utc0_complete_40" "0,1" newline bitfld.long 0xF4 7. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_39,Enable Set for pulse_vpac_out_1_en_utc0_complete_39" "0,1" newline bitfld.long 0xF4 6. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_38,Enable Set for pulse_vpac_out_1_en_utc0_complete_38" "0,1" newline bitfld.long 0xF4 5. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_37,Enable Set for pulse_vpac_out_1_en_utc0_complete_37" "0,1" newline bitfld.long 0xF4 4. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_36,Enable Set for pulse_vpac_out_1_en_utc0_complete_36" "0,1" newline bitfld.long 0xF4 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_35,Enable Set for pulse_vpac_out_1_en_utc0_complete_35" "0,1" newline bitfld.long 0xF4 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_34,Enable Set for pulse_vpac_out_1_en_utc0_complete_34" "0,1" newline bitfld.long 0xF4 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_33,Enable Set for pulse_vpac_out_1_en_utc0_complete_33" "0,1" newline bitfld.long 0xF4 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_32,Enable Set for pulse_vpac_out_1_en_utc0_complete_32" "0,1" line.long 0xF8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_6,Enable Register 62" bitfld.long 0xF8 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_RSVD_UNUSED,Enable Set for pulse_vpac_out_1_en_utc1_rsvd_unused" "0,1" line.long 0xFC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_1_7,Enable Register 63" bitfld.long 0xFC 4. "ENABLE_PULSE_VPAC_OUT_1_EN_CTM_PULSE,Enable Set for pulse_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0xFC 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0xFC 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_1_en_utc0_error" "0,1" line.long 0x100 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_0,Enable Register 64" bitfld.long 0x100 27. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_DPC_STATS_READ_ERR,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x100 26. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_CR_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x100 25. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x100 24. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x100 23. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x100 22. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x100 21. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x100 20. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x100 19. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x100 18. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x100 17. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x100 16. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x100 15. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x100 14. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x100 13. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x100 12. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x100 11. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x100 10. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x100 9. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x100 8. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x100 7. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x100 6. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x100 5. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x100 4. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x100 3. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x100 2. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x100 1. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x100 0. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x104 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_1,Enable Register 65" bitfld.long 0x104 8. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x104 7. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x104 6. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x104 5. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x104 4. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x104 3. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x104 2. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x104 1. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x104 0. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x108 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_2,Enable Register 66" bitfld.long 0x108 3. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x108 2. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x108 1. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x108 0. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x10C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_3,Enable Register 67" bitfld.long 0x10C 26. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x10C 25. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x10C 24. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x10C 22. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x10C 20. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x10C 19. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_2_en_spare_pend_1_level" "0,1" newline bitfld.long 0x10C 18. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_2_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x10C 17. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_2_en_spare_pend_0_level" "0,1" newline bitfld.long 0x10C 16. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_2_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x10C 15. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x10C 14. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x10C 13. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_6,Enable Set for pulse_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x10C 12. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_5,Enable Set for pulse_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x10C 11. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_4,Enable Set for pulse_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x10C 9. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_2,Enable Set for pulse_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x10C 7. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_0,Enable Set for pulse_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x10C 6. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x10C 5. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x10C 4. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x10C 3. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x10C 2. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x10C 1. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x10C 0. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x110 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_4,Enable Register 68" bitfld.long 0x110 31. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x110 30. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x110 29. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x110 28. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x110 27. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x110 26. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x110 25. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x110 24. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x110 23. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x110 22. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x110 21. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x110 20. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x110 19. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x110 18. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x110 17. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x110 16. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x110 15. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x110 14. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x110 13. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x110 12. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x110 11. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x110 10. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x110 9. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x110 8. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x110 7. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x110 6. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x110 5. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x110 4. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x110 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x110 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x110 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x110 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x114 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_5,Enable Register 69" bitfld.long 0x114 31. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_63,Enable Set for pulse_vpac_out_2_en_utc0_complete_63" "0,1" newline bitfld.long 0x114 30. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_62,Enable Set for pulse_vpac_out_2_en_utc0_complete_62" "0,1" newline bitfld.long 0x114 29. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_61,Enable Set for pulse_vpac_out_2_en_utc0_complete_61" "0,1" newline bitfld.long 0x114 28. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_60,Enable Set for pulse_vpac_out_2_en_utc0_complete_60" "0,1" newline bitfld.long 0x114 27. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_59,Enable Set for pulse_vpac_out_2_en_utc0_complete_59" "0,1" newline bitfld.long 0x114 26. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_58,Enable Set for pulse_vpac_out_2_en_utc0_complete_58" "0,1" newline bitfld.long 0x114 25. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_57,Enable Set for pulse_vpac_out_2_en_utc0_complete_57" "0,1" newline bitfld.long 0x114 24. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_56,Enable Set for pulse_vpac_out_2_en_utc0_complete_56" "0,1" newline bitfld.long 0x114 23. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_55,Enable Set for pulse_vpac_out_2_en_utc0_complete_55" "0,1" newline bitfld.long 0x114 22. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_54,Enable Set for pulse_vpac_out_2_en_utc0_complete_54" "0,1" newline bitfld.long 0x114 21. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_53,Enable Set for pulse_vpac_out_2_en_utc0_complete_53" "0,1" newline bitfld.long 0x114 20. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_52,Enable Set for pulse_vpac_out_2_en_utc0_complete_52" "0,1" newline bitfld.long 0x114 19. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_51,Enable Set for pulse_vpac_out_2_en_utc0_complete_51" "0,1" newline bitfld.long 0x114 18. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_50,Enable Set for pulse_vpac_out_2_en_utc0_complete_50" "0,1" newline bitfld.long 0x114 17. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_49,Enable Set for pulse_vpac_out_2_en_utc0_complete_49" "0,1" newline bitfld.long 0x114 16. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_48,Enable Set for pulse_vpac_out_2_en_utc0_complete_48" "0,1" newline bitfld.long 0x114 15. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_47,Enable Set for pulse_vpac_out_2_en_utc0_complete_47" "0,1" newline bitfld.long 0x114 14. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_46,Enable Set for pulse_vpac_out_2_en_utc0_complete_46" "0,1" newline bitfld.long 0x114 13. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_45,Enable Set for pulse_vpac_out_2_en_utc0_complete_45" "0,1" newline bitfld.long 0x114 12. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_44,Enable Set for pulse_vpac_out_2_en_utc0_complete_44" "0,1" newline bitfld.long 0x114 11. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_43,Enable Set for pulse_vpac_out_2_en_utc0_complete_43" "0,1" newline bitfld.long 0x114 10. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_42,Enable Set for pulse_vpac_out_2_en_utc0_complete_42" "0,1" newline bitfld.long 0x114 9. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_41,Enable Set for pulse_vpac_out_2_en_utc0_complete_41" "0,1" newline bitfld.long 0x114 8. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_40,Enable Set for pulse_vpac_out_2_en_utc0_complete_40" "0,1" newline bitfld.long 0x114 7. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_39,Enable Set for pulse_vpac_out_2_en_utc0_complete_39" "0,1" newline bitfld.long 0x114 6. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_38,Enable Set for pulse_vpac_out_2_en_utc0_complete_38" "0,1" newline bitfld.long 0x114 5. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_37,Enable Set for pulse_vpac_out_2_en_utc0_complete_37" "0,1" newline bitfld.long 0x114 4. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_36,Enable Set for pulse_vpac_out_2_en_utc0_complete_36" "0,1" newline bitfld.long 0x114 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_35,Enable Set for pulse_vpac_out_2_en_utc0_complete_35" "0,1" newline bitfld.long 0x114 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_34,Enable Set for pulse_vpac_out_2_en_utc0_complete_34" "0,1" newline bitfld.long 0x114 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_33,Enable Set for pulse_vpac_out_2_en_utc0_complete_33" "0,1" newline bitfld.long 0x114 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_32,Enable Set for pulse_vpac_out_2_en_utc0_complete_32" "0,1" line.long 0x118 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_6,Enable Register 70" bitfld.long 0x118 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_RSVD_UNUSED,Enable Set for pulse_vpac_out_2_en_utc1_rsvd_unused" "0,1" line.long 0x11C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_2_7,Enable Register 71" bitfld.long 0x11C 4. "ENABLE_PULSE_VPAC_OUT_2_EN_CTM_PULSE,Enable Set for pulse_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x11C 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x11C 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_2_en_utc0_error" "0,1" line.long 0x120 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_0,Enable Register 72" bitfld.long 0x120 27. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_DPC_STATS_READ_ERR,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x120 26. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_CR_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x120 25. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x120 24. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x120 23. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x120 22. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x120 21. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x120 20. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x120 19. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x120 18. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x120 17. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x120 16. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x120 15. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x120 14. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x120 13. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x120 12. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x120 11. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x120 10. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x120 9. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x120 8. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x120 7. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x120 6. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x120 5. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x120 4. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x120 3. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x120 2. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x120 1. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x120 0. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x124 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_1,Enable Register 73" bitfld.long 0x124 8. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x124 7. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x124 6. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x124 5. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x124 4. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x124 3. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x124 2. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x124 1. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x124 0. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x128 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_2,Enable Register 74" bitfld.long 0x128 3. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x128 2. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x128 1. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x128 0. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x12C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_3,Enable Register 75" bitfld.long 0x12C 26. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x12C 25. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x12C 24. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x12C 22. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x12C 20. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x12C 19. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_3_en_spare_pend_1_level" "0,1" newline bitfld.long 0x12C 18. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_3_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x12C 17. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_3_en_spare_pend_0_level" "0,1" newline bitfld.long 0x12C 16. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_3_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x12C 15. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x12C 14. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x12C 13. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_6,Enable Set for pulse_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x12C 12. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_5,Enable Set for pulse_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x12C 11. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_4,Enable Set for pulse_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x12C 9. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_2,Enable Set for pulse_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x12C 7. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_0,Enable Set for pulse_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x12C 6. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x12C 5. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x12C 4. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x12C 3. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x12C 2. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x12C 1. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x12C 0. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x130 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_4,Enable Register 76" bitfld.long 0x130 31. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x130 30. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x130 29. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x130 28. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x130 27. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x130 26. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x130 25. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x130 24. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x130 23. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x130 22. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x130 21. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x130 20. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x130 19. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x130 18. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x130 17. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x130 16. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x130 15. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x130 14. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x130 13. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x130 12. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x130 11. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x130 10. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x130 9. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x130 8. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x130 7. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x130 6. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x130 5. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x130 4. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x130 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x130 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x130 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x130 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x134 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_5,Enable Register 77" bitfld.long 0x134 31. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_63,Enable Set for pulse_vpac_out_3_en_utc0_complete_63" "0,1" newline bitfld.long 0x134 30. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_62,Enable Set for pulse_vpac_out_3_en_utc0_complete_62" "0,1" newline bitfld.long 0x134 29. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_61,Enable Set for pulse_vpac_out_3_en_utc0_complete_61" "0,1" newline bitfld.long 0x134 28. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_60,Enable Set for pulse_vpac_out_3_en_utc0_complete_60" "0,1" newline bitfld.long 0x134 27. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_59,Enable Set for pulse_vpac_out_3_en_utc0_complete_59" "0,1" newline bitfld.long 0x134 26. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_58,Enable Set for pulse_vpac_out_3_en_utc0_complete_58" "0,1" newline bitfld.long 0x134 25. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_57,Enable Set for pulse_vpac_out_3_en_utc0_complete_57" "0,1" newline bitfld.long 0x134 24. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_56,Enable Set for pulse_vpac_out_3_en_utc0_complete_56" "0,1" newline bitfld.long 0x134 23. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_55,Enable Set for pulse_vpac_out_3_en_utc0_complete_55" "0,1" newline bitfld.long 0x134 22. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_54,Enable Set for pulse_vpac_out_3_en_utc0_complete_54" "0,1" newline bitfld.long 0x134 21. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_53,Enable Set for pulse_vpac_out_3_en_utc0_complete_53" "0,1" newline bitfld.long 0x134 20. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_52,Enable Set for pulse_vpac_out_3_en_utc0_complete_52" "0,1" newline bitfld.long 0x134 19. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_51,Enable Set for pulse_vpac_out_3_en_utc0_complete_51" "0,1" newline bitfld.long 0x134 18. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_50,Enable Set for pulse_vpac_out_3_en_utc0_complete_50" "0,1" newline bitfld.long 0x134 17. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_49,Enable Set for pulse_vpac_out_3_en_utc0_complete_49" "0,1" newline bitfld.long 0x134 16. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_48,Enable Set for pulse_vpac_out_3_en_utc0_complete_48" "0,1" newline bitfld.long 0x134 15. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_47,Enable Set for pulse_vpac_out_3_en_utc0_complete_47" "0,1" newline bitfld.long 0x134 14. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_46,Enable Set for pulse_vpac_out_3_en_utc0_complete_46" "0,1" newline bitfld.long 0x134 13. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_45,Enable Set for pulse_vpac_out_3_en_utc0_complete_45" "0,1" newline bitfld.long 0x134 12. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_44,Enable Set for pulse_vpac_out_3_en_utc0_complete_44" "0,1" newline bitfld.long 0x134 11. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_43,Enable Set for pulse_vpac_out_3_en_utc0_complete_43" "0,1" newline bitfld.long 0x134 10. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_42,Enable Set for pulse_vpac_out_3_en_utc0_complete_42" "0,1" newline bitfld.long 0x134 9. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_41,Enable Set for pulse_vpac_out_3_en_utc0_complete_41" "0,1" newline bitfld.long 0x134 8. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_40,Enable Set for pulse_vpac_out_3_en_utc0_complete_40" "0,1" newline bitfld.long 0x134 7. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_39,Enable Set for pulse_vpac_out_3_en_utc0_complete_39" "0,1" newline bitfld.long 0x134 6. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_38,Enable Set for pulse_vpac_out_3_en_utc0_complete_38" "0,1" newline bitfld.long 0x134 5. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_37,Enable Set for pulse_vpac_out_3_en_utc0_complete_37" "0,1" newline bitfld.long 0x134 4. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_36,Enable Set for pulse_vpac_out_3_en_utc0_complete_36" "0,1" newline bitfld.long 0x134 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_35,Enable Set for pulse_vpac_out_3_en_utc0_complete_35" "0,1" newline bitfld.long 0x134 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_34,Enable Set for pulse_vpac_out_3_en_utc0_complete_34" "0,1" newline bitfld.long 0x134 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_33,Enable Set for pulse_vpac_out_3_en_utc0_complete_33" "0,1" newline bitfld.long 0x134 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_32,Enable Set for pulse_vpac_out_3_en_utc0_complete_32" "0,1" line.long 0x138 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_6,Enable Register 78" bitfld.long 0x138 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_RSVD_UNUSED,Enable Set for pulse_vpac_out_3_en_utc1_rsvd_unused" "0,1" line.long 0x13C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_3_7,Enable Register 79" bitfld.long 0x13C 4. "ENABLE_PULSE_VPAC_OUT_3_EN_CTM_PULSE,Enable Set for pulse_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x13C 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x13C 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_3_en_utc0_error" "0,1" line.long 0x140 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_0,Enable Register 80" bitfld.long 0x140 27. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_DPC_STATS_READ_ERR,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x140 26. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_CR_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x140 25. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x140 24. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x140 23. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x140 22. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x140 21. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x140 20. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x140 19. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x140 18. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x140 17. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x140 16. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x140 15. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x140 14. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x140 13. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x140 12. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x140 11. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x140 10. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x140 9. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x140 8. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x140 7. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x140 6. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x140 5. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x140 4. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x140 3. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x140 2. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x140 1. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x140 0. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x144 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_1,Enable Register 81" bitfld.long 0x144 8. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x144 7. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x144 6. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x144 5. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x144 4. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x144 3. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x144 2. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x144 1. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x144 0. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x148 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_2,Enable Register 82" bitfld.long 0x148 3. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x148 2. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x148 1. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x148 0. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x14C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_3,Enable Register 83" bitfld.long 0x14C 26. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x14C 25. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x14C 24. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x14C 22. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x14C 20. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x14C 19. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_4_en_spare_pend_1_level" "0,1" newline bitfld.long 0x14C 18. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_4_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x14C 17. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_4_en_spare_pend_0_level" "0,1" newline bitfld.long 0x14C 16. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_4_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x14C 15. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x14C 14. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x14C 13. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_6,Enable Set for pulse_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x14C 12. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_5,Enable Set for pulse_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x14C 11. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_4,Enable Set for pulse_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x14C 9. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_2,Enable Set for pulse_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x14C 7. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_0,Enable Set for pulse_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x14C 6. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x14C 5. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x14C 4. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x14C 3. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x14C 2. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x14C 1. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x14C 0. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x150 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_4,Enable Register 84" bitfld.long 0x150 31. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x150 30. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x150 29. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x150 28. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x150 27. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x150 26. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x150 25. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x150 24. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x150 23. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x150 22. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x150 21. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x150 20. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x150 19. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x150 18. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x150 17. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x150 16. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x150 15. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x150 14. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x150 13. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x150 12. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x150 11. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x150 10. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x150 9. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x150 8. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x150 7. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x150 6. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x150 5. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x150 4. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x150 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x150 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x150 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x150 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x154 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_5,Enable Register 85" bitfld.long 0x154 31. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_63,Enable Set for pulse_vpac_out_4_en_utc0_complete_63" "0,1" newline bitfld.long 0x154 30. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_62,Enable Set for pulse_vpac_out_4_en_utc0_complete_62" "0,1" newline bitfld.long 0x154 29. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_61,Enable Set for pulse_vpac_out_4_en_utc0_complete_61" "0,1" newline bitfld.long 0x154 28. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_60,Enable Set for pulse_vpac_out_4_en_utc0_complete_60" "0,1" newline bitfld.long 0x154 27. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_59,Enable Set for pulse_vpac_out_4_en_utc0_complete_59" "0,1" newline bitfld.long 0x154 26. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_58,Enable Set for pulse_vpac_out_4_en_utc0_complete_58" "0,1" newline bitfld.long 0x154 25. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_57,Enable Set for pulse_vpac_out_4_en_utc0_complete_57" "0,1" newline bitfld.long 0x154 24. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_56,Enable Set for pulse_vpac_out_4_en_utc0_complete_56" "0,1" newline bitfld.long 0x154 23. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_55,Enable Set for pulse_vpac_out_4_en_utc0_complete_55" "0,1" newline bitfld.long 0x154 22. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_54,Enable Set for pulse_vpac_out_4_en_utc0_complete_54" "0,1" newline bitfld.long 0x154 21. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_53,Enable Set for pulse_vpac_out_4_en_utc0_complete_53" "0,1" newline bitfld.long 0x154 20. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_52,Enable Set for pulse_vpac_out_4_en_utc0_complete_52" "0,1" newline bitfld.long 0x154 19. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_51,Enable Set for pulse_vpac_out_4_en_utc0_complete_51" "0,1" newline bitfld.long 0x154 18. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_50,Enable Set for pulse_vpac_out_4_en_utc0_complete_50" "0,1" newline bitfld.long 0x154 17. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_49,Enable Set for pulse_vpac_out_4_en_utc0_complete_49" "0,1" newline bitfld.long 0x154 16. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_48,Enable Set for pulse_vpac_out_4_en_utc0_complete_48" "0,1" newline bitfld.long 0x154 15. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_47,Enable Set for pulse_vpac_out_4_en_utc0_complete_47" "0,1" newline bitfld.long 0x154 14. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_46,Enable Set for pulse_vpac_out_4_en_utc0_complete_46" "0,1" newline bitfld.long 0x154 13. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_45,Enable Set for pulse_vpac_out_4_en_utc0_complete_45" "0,1" newline bitfld.long 0x154 12. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_44,Enable Set for pulse_vpac_out_4_en_utc0_complete_44" "0,1" newline bitfld.long 0x154 11. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_43,Enable Set for pulse_vpac_out_4_en_utc0_complete_43" "0,1" newline bitfld.long 0x154 10. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_42,Enable Set for pulse_vpac_out_4_en_utc0_complete_42" "0,1" newline bitfld.long 0x154 9. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_41,Enable Set for pulse_vpac_out_4_en_utc0_complete_41" "0,1" newline bitfld.long 0x154 8. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_40,Enable Set for pulse_vpac_out_4_en_utc0_complete_40" "0,1" newline bitfld.long 0x154 7. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_39,Enable Set for pulse_vpac_out_4_en_utc0_complete_39" "0,1" newline bitfld.long 0x154 6. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_38,Enable Set for pulse_vpac_out_4_en_utc0_complete_38" "0,1" newline bitfld.long 0x154 5. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_37,Enable Set for pulse_vpac_out_4_en_utc0_complete_37" "0,1" newline bitfld.long 0x154 4. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_36,Enable Set for pulse_vpac_out_4_en_utc0_complete_36" "0,1" newline bitfld.long 0x154 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_35,Enable Set for pulse_vpac_out_4_en_utc0_complete_35" "0,1" newline bitfld.long 0x154 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_34,Enable Set for pulse_vpac_out_4_en_utc0_complete_34" "0,1" newline bitfld.long 0x154 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_33,Enable Set for pulse_vpac_out_4_en_utc0_complete_33" "0,1" newline bitfld.long 0x154 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_32,Enable Set for pulse_vpac_out_4_en_utc0_complete_32" "0,1" line.long 0x158 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_6,Enable Register 86" bitfld.long 0x158 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_RSVD_UNUSED,Enable Set for pulse_vpac_out_4_en_utc1_rsvd_unused" "0,1" line.long 0x15C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_4_7,Enable Register 87" bitfld.long 0x15C 4. "ENABLE_PULSE_VPAC_OUT_4_EN_CTM_PULSE,Enable Set for pulse_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x15C 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x15C 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_4_en_utc0_error" "0,1" line.long 0x160 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_0,Enable Register 88" bitfld.long 0x160 27. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_DPC_STATS_READ_ERR,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x160 26. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_CR_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x160 25. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_X_Y_POINTER,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x160 24. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_OUT_FR_START_EVT,Enable Set for pulse_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x160 23. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_CAL_VP_ERR,Enable Set for pulse_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x160 22. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x160 21. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x160 20. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_FR_DONE_EVT,Enable Set for pulse_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x160 19. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_EE_SYNCOVF_ERR,Enable Set for pulse_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x160 18. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_EE_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x160 17. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_HIST_READ_ERR,Enable Set for pulse_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x160 16. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_OUTIF_OVF_ERR,Enable Set for pulse_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x160 15. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x160 14. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCFA_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x160 13. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_VP_ERR,Enable Set for pulse_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x160 12. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_VSYNC_ERR,Enable Set for pulse_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x160 11. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_HSYNC_ERR,Enable Set for pulse_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x160 10. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_DONE,Enable Set for pulse_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x160 9. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_START,Enable Set for pulse_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x160 8. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x160 7. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_VBLANK_ERR,Enable Set for pulse_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x160 6. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_HBLANK_ERR,Enable Set for pulse_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x160 5. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_LINEMEM_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x160 4. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x160 3. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_PULSE,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x160 2. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_AF_PULSE,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x160 1. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_AEW_PULSE,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x160 0. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_CFG_ERR,Enable Set for pulse_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0x164 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_1,Enable Register 89" bitfld.long 0x164 8. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_VBUSM_RD_ERR,Enable Set for pulse_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x164 7. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_SL2_WR_ERR,Enable Set for pulse_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x164 6. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_FR_DONE_EVT,Enable Set for pulse_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x164 5. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_INT_SZOVF,Enable Set for pulse_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x164 4. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_IFR_OUTOFBOUND,Enable Set for pulse_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x164 3. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_MESH_IBLK_MEMOVF,Enable Set for pulse_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x164 2. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_PIX_IBLK_MEMOVF,Enable Set for pulse_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x164 1. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_MESH_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x164 0. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_PIX_IBLK_OUTOFBOUND,Enable Set for pulse_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x168 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_2,Enable Register 90" bitfld.long 0x168 3. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_SL2_WR_ERR,Enable Set for pulse_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x168 2. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_SL2_RD_ERR,Enable Set for pulse_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x168 1. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_1,Enable Set for pulse_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x168 0. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_0,Enable Set for pulse_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x16C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_3,Enable Register 91" bitfld.long 0x16C 26. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_6,Enable Set for pulse_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x16C 25. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_5,Enable Set for pulse_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x16C 24. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_4,Enable Set for pulse_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x16C 22. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_2,Enable Set for pulse_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x16C 20. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_0,Enable Set for pulse_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x16C 19. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_1_LEVEL,Enable Set for pulse_vpac_out_5_en_spare_pend_1_level" "0,1" newline bitfld.long 0x16C 18. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_1_PULSE,Enable Set for pulse_vpac_out_5_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x16C 17. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_0_LEVEL,Enable Set for pulse_vpac_out_5_en_spare_pend_0_level" "0,1" newline bitfld.long 0x16C 16. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_0_PULSE,Enable Set for pulse_vpac_out_5_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x16C 15. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_DEC_1,Enable Set for pulse_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0x16C 14. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_DEC_0,Enable Set for pulse_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0x16C 13. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_6,Enable Set for pulse_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0x16C 12. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_5,Enable Set for pulse_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0x16C 11. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_4,Enable Set for pulse_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0x16C 9. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_2,Enable Set for pulse_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0x16C 7. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_0,Enable Set for pulse_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0x16C 6. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_6,Enable Set for pulse_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0x16C 5. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_5,Enable Set for pulse_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0x16C 4. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_4,Enable Set for pulse_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0x16C 3. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_3,Enable Set for pulse_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0x16C 2. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_2,Enable Set for pulse_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0x16C 1. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_1,Enable Set for pulse_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0x16C 0. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_0,Enable Set for pulse_vpac_out_5_en_pipe_done_0" "0,1" line.long 0x170 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_4,Enable Register 92" bitfld.long 0x170 31. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_31,Enable Set for pulse_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0x170 30. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_30,Enable Set for pulse_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0x170 29. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_29,Enable Set for pulse_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0x170 28. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_28,Enable Set for pulse_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0x170 27. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_27,Enable Set for pulse_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0x170 26. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_26,Enable Set for pulse_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0x170 25. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_25,Enable Set for pulse_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0x170 24. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_24,Enable Set for pulse_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0x170 23. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_23,Enable Set for pulse_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0x170 22. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_22,Enable Set for pulse_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0x170 21. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_21,Enable Set for pulse_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0x170 20. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_20,Enable Set for pulse_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0x170 19. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_19,Enable Set for pulse_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0x170 18. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_18,Enable Set for pulse_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0x170 17. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_17,Enable Set for pulse_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0x170 16. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_16,Enable Set for pulse_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0x170 15. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_15,Enable Set for pulse_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0x170 14. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_14,Enable Set for pulse_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0x170 13. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_13,Enable Set for pulse_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0x170 12. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_12,Enable Set for pulse_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0x170 11. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_11,Enable Set for pulse_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0x170 10. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_10,Enable Set for pulse_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0x170 9. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_9,Enable Set for pulse_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0x170 8. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_8,Enable Set for pulse_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0x170 7. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_7,Enable Set for pulse_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0x170 6. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_6,Enable Set for pulse_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0x170 5. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_5,Enable Set for pulse_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0x170 4. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_4,Enable Set for pulse_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0x170 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_3,Enable Set for pulse_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0x170 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_2,Enable Set for pulse_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0x170 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_1,Enable Set for pulse_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0x170 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_0,Enable Set for pulse_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0x174 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_5,Enable Register 93" bitfld.long 0x174 31. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_63,Enable Set for pulse_vpac_out_5_en_utc0_complete_63" "0,1" newline bitfld.long 0x174 30. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_62,Enable Set for pulse_vpac_out_5_en_utc0_complete_62" "0,1" newline bitfld.long 0x174 29. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_61,Enable Set for pulse_vpac_out_5_en_utc0_complete_61" "0,1" newline bitfld.long 0x174 28. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_60,Enable Set for pulse_vpac_out_5_en_utc0_complete_60" "0,1" newline bitfld.long 0x174 27. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_59,Enable Set for pulse_vpac_out_5_en_utc0_complete_59" "0,1" newline bitfld.long 0x174 26. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_58,Enable Set for pulse_vpac_out_5_en_utc0_complete_58" "0,1" newline bitfld.long 0x174 25. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_57,Enable Set for pulse_vpac_out_5_en_utc0_complete_57" "0,1" newline bitfld.long 0x174 24. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_56,Enable Set for pulse_vpac_out_5_en_utc0_complete_56" "0,1" newline bitfld.long 0x174 23. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_55,Enable Set for pulse_vpac_out_5_en_utc0_complete_55" "0,1" newline bitfld.long 0x174 22. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_54,Enable Set for pulse_vpac_out_5_en_utc0_complete_54" "0,1" newline bitfld.long 0x174 21. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_53,Enable Set for pulse_vpac_out_5_en_utc0_complete_53" "0,1" newline bitfld.long 0x174 20. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_52,Enable Set for pulse_vpac_out_5_en_utc0_complete_52" "0,1" newline bitfld.long 0x174 19. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_51,Enable Set for pulse_vpac_out_5_en_utc0_complete_51" "0,1" newline bitfld.long 0x174 18. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_50,Enable Set for pulse_vpac_out_5_en_utc0_complete_50" "0,1" newline bitfld.long 0x174 17. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_49,Enable Set for pulse_vpac_out_5_en_utc0_complete_49" "0,1" newline bitfld.long 0x174 16. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_48,Enable Set for pulse_vpac_out_5_en_utc0_complete_48" "0,1" newline bitfld.long 0x174 15. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_47,Enable Set for pulse_vpac_out_5_en_utc0_complete_47" "0,1" newline bitfld.long 0x174 14. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_46,Enable Set for pulse_vpac_out_5_en_utc0_complete_46" "0,1" newline bitfld.long 0x174 13. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_45,Enable Set for pulse_vpac_out_5_en_utc0_complete_45" "0,1" newline bitfld.long 0x174 12. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_44,Enable Set for pulse_vpac_out_5_en_utc0_complete_44" "0,1" newline bitfld.long 0x174 11. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_43,Enable Set for pulse_vpac_out_5_en_utc0_complete_43" "0,1" newline bitfld.long 0x174 10. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_42,Enable Set for pulse_vpac_out_5_en_utc0_complete_42" "0,1" newline bitfld.long 0x174 9. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_41,Enable Set for pulse_vpac_out_5_en_utc0_complete_41" "0,1" newline bitfld.long 0x174 8. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_40,Enable Set for pulse_vpac_out_5_en_utc0_complete_40" "0,1" newline bitfld.long 0x174 7. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_39,Enable Set for pulse_vpac_out_5_en_utc0_complete_39" "0,1" newline bitfld.long 0x174 6. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_38,Enable Set for pulse_vpac_out_5_en_utc0_complete_38" "0,1" newline bitfld.long 0x174 5. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_37,Enable Set for pulse_vpac_out_5_en_utc0_complete_37" "0,1" newline bitfld.long 0x174 4. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_36,Enable Set for pulse_vpac_out_5_en_utc0_complete_36" "0,1" newline bitfld.long 0x174 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_35,Enable Set for pulse_vpac_out_5_en_utc0_complete_35" "0,1" newline bitfld.long 0x174 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_34,Enable Set for pulse_vpac_out_5_en_utc0_complete_34" "0,1" newline bitfld.long 0x174 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_33,Enable Set for pulse_vpac_out_5_en_utc0_complete_33" "0,1" newline bitfld.long 0x174 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_32,Enable Set for pulse_vpac_out_5_en_utc0_complete_32" "0,1" line.long 0x178 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_6,Enable Register 94" bitfld.long 0x178 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_RSVD_UNUSED,Enable Set for pulse_vpac_out_5_en_utc1_rsvd_unused" "0,1" line.long 0x17C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_vpac_out_5_7,Enable Register 95" bitfld.long 0x17C 4. "ENABLE_PULSE_VPAC_OUT_5_EN_CTM_PULSE,Enable Set for pulse_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0x17C 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_PROT_ERR,Enable Set for pulse_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0x17C 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_ERROR,Enable Set for pulse_vpac_out_5_en_utc0_error" "0,1" group.long 0x300++0x17F line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_0,Enable Clear Register 0" bitfld.long 0x0 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x0 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x0 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x0 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x0 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x0 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x0 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x0 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x0 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x0 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x0 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x0 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x0 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x0 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x0 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x0 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x0 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x0 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x0 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x0 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x0 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x0 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x0 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x0 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x0 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x0 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x0 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x0 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_1,Enable Clear Register 1" bitfld.long 0x4 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x4 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x4 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x4 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x4 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x4 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x4 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x4 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x4 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_2,Enable Clear Register 2" bitfld.long 0x8 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x8 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x8 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x8 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_3,Enable Clear Register 3" bitfld.long 0xC 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xC 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xC 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xC 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xC 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xC 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_0_en_spare_pend_1_level" "0,1" newline bitfld.long 0xC 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_0_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xC 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_0_en_spare_pend_0_level" "0,1" newline bitfld.long 0xC 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_0_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xC 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xC 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xC 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xC 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xC 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xC 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xC 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xC 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xC 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xC 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xC 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xC 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xC 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xC 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_0_en_pipe_done_0" "0,1" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_4,Enable Clear Register 4" bitfld.long 0x10 31. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0x10 30. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0x10 29. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0x10 28. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0x10 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0x10 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0x10 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0x10 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0x10 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0x10 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0x10 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0x10 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0x10 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0x10 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0x10 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0x10 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0x10 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0x10 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0x10 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0x10 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0x10 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0x10 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0x10 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0x10 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0x10 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0x10 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0x10 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0x10 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0x10 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0x10 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0x10 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0x10 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_5,Enable Clear Register 5" bitfld.long 0x14 31. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_63_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_63" "0,1" newline bitfld.long 0x14 30. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_62_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_62" "0,1" newline bitfld.long 0x14 29. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_61_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_61" "0,1" newline bitfld.long 0x14 28. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_60_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_60" "0,1" newline bitfld.long 0x14 27. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_59_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_59" "0,1" newline bitfld.long 0x14 26. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_58_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_58" "0,1" newline bitfld.long 0x14 25. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_57_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_57" "0,1" newline bitfld.long 0x14 24. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_56_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_56" "0,1" newline bitfld.long 0x14 23. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_55_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_55" "0,1" newline bitfld.long 0x14 22. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_54_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_54" "0,1" newline bitfld.long 0x14 21. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_53_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_53" "0,1" newline bitfld.long 0x14 20. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_52_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_52" "0,1" newline bitfld.long 0x14 19. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_51_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_51" "0,1" newline bitfld.long 0x14 18. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_50_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_50" "0,1" newline bitfld.long 0x14 17. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_49_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_49" "0,1" newline bitfld.long 0x14 16. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_48_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_48" "0,1" newline bitfld.long 0x14 15. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_47_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_47" "0,1" newline bitfld.long 0x14 14. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_46_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_46" "0,1" newline bitfld.long 0x14 13. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_45_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_45" "0,1" newline bitfld.long 0x14 12. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_44_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_44" "0,1" newline bitfld.long 0x14 11. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_43_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_43" "0,1" newline bitfld.long 0x14 10. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_42_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_42" "0,1" newline bitfld.long 0x14 9. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_41_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_41" "0,1" newline bitfld.long 0x14 8. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_40_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_40" "0,1" newline bitfld.long 0x14 7. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_39_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_39" "0,1" newline bitfld.long 0x14 6. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_38_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_38" "0,1" newline bitfld.long 0x14 5. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_37_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_37" "0,1" newline bitfld.long 0x14 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_36_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_36" "0,1" newline bitfld.long 0x14 3. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_35_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_35" "0,1" newline bitfld.long 0x14 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_34_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_34" "0,1" newline bitfld.long 0x14 1. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_33_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_33" "0,1" newline bitfld.long 0x14 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_COMPLETE_32_CLR,Enable Clear for level_vpac_out_0_en_utc0_complete_32" "0,1" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_6,Enable Clear Register 6" bitfld.long 0x18 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC1_RSVD_UNUSED_CLR,Enable Clear for level_vpac_out_0_en_utc1_rsvd_unused" "0,1" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_0_7,Enable Clear Register 7" bitfld.long 0x1C 4. "ENABLE_LEVEL_VPAC_OUT_0_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x1C 2. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0x1C 0. "ENABLE_LEVEL_VPAC_OUT_0_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_0_en_utc0_error" "0,1" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_0,Enable Clear Register 8" bitfld.long 0x20 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x20 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x20 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x20 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x20 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x20 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x20 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x20 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x20 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x20 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x20 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x20 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x20 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x20 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x20 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x20 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x20 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x20 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x20 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x20 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x20 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x20 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x20 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x20 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x20 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x20 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x20 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x20 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_1,Enable Clear Register 9" bitfld.long 0x24 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x24 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x24 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x24 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x24 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x24 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x24 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x24 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x24 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_2,Enable Clear Register 10" bitfld.long 0x28 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x28 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x28 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x28 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_3,Enable Clear Register 11" bitfld.long 0x2C 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x2C 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x2C 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x2C 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x2C 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x2C 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_1_en_spare_pend_1_level" "0,1" newline bitfld.long 0x2C 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_1_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x2C 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_1_en_spare_pend_0_level" "0,1" newline bitfld.long 0x2C 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_1_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x2C 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x2C 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x2C 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0x2C 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0x2C 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0x2C 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0x2C 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0x2C 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0x2C 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0x2C 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0x2C 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x2C 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x2C 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x2C 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_1_en_pipe_done_0" "0,1" line.long 0x30 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_4,Enable Clear Register 12" bitfld.long 0x30 31. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0x30 30. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0x30 29. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0x30 28. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0x30 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0x30 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0x30 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0x30 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0x30 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0x30 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0x30 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0x30 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0x30 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0x30 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0x30 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0x30 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0x30 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0x30 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0x30 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0x30 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0x30 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0x30 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0x30 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0x30 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0x30 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0x30 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0x30 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0x30 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0x30 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0x30 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0x30 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0x30 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_5,Enable Clear Register 13" bitfld.long 0x34 31. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_63_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_63" "0,1" newline bitfld.long 0x34 30. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_62_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_62" "0,1" newline bitfld.long 0x34 29. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_61_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_61" "0,1" newline bitfld.long 0x34 28. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_60_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_60" "0,1" newline bitfld.long 0x34 27. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_59_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_59" "0,1" newline bitfld.long 0x34 26. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_58_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_58" "0,1" newline bitfld.long 0x34 25. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_57_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_57" "0,1" newline bitfld.long 0x34 24. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_56_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_56" "0,1" newline bitfld.long 0x34 23. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_55_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_55" "0,1" newline bitfld.long 0x34 22. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_54_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_54" "0,1" newline bitfld.long 0x34 21. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_53_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_53" "0,1" newline bitfld.long 0x34 20. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_52_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_52" "0,1" newline bitfld.long 0x34 19. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_51_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_51" "0,1" newline bitfld.long 0x34 18. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_50_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_50" "0,1" newline bitfld.long 0x34 17. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_49_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_49" "0,1" newline bitfld.long 0x34 16. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_48_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_48" "0,1" newline bitfld.long 0x34 15. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_47_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_47" "0,1" newline bitfld.long 0x34 14. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_46_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_46" "0,1" newline bitfld.long 0x34 13. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_45_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_45" "0,1" newline bitfld.long 0x34 12. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_44_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_44" "0,1" newline bitfld.long 0x34 11. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_43_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_43" "0,1" newline bitfld.long 0x34 10. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_42_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_42" "0,1" newline bitfld.long 0x34 9. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_41_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_41" "0,1" newline bitfld.long 0x34 8. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_40_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_40" "0,1" newline bitfld.long 0x34 7. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_39_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_39" "0,1" newline bitfld.long 0x34 6. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_38_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_38" "0,1" newline bitfld.long 0x34 5. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_37_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_37" "0,1" newline bitfld.long 0x34 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_36_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_36" "0,1" newline bitfld.long 0x34 3. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_35_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_35" "0,1" newline bitfld.long 0x34 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_34_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_34" "0,1" newline bitfld.long 0x34 1. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_33_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_33" "0,1" newline bitfld.long 0x34 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_COMPLETE_32_CLR,Enable Clear for level_vpac_out_1_en_utc0_complete_32" "0,1" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_6,Enable Clear Register 14" bitfld.long 0x38 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC1_RSVD_UNUSED_CLR,Enable Clear for level_vpac_out_1_en_utc1_rsvd_unused" "0,1" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_1_7,Enable Clear Register 15" bitfld.long 0x3C 4. "ENABLE_LEVEL_VPAC_OUT_1_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x3C 2. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0x3C 0. "ENABLE_LEVEL_VPAC_OUT_1_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_1_en_utc0_error" "0,1" line.long 0x40 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_0,Enable Clear Register 16" bitfld.long 0x40 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x40 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x40 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x40 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x40 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x40 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x40 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x40 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x40 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x40 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x40 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x40 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x40 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x40 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x40 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x40 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x40 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x40 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x40 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x40 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x40 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x40 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x40 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x40 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x40 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x40 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x40 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x40 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x44 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_1,Enable Clear Register 17" bitfld.long 0x44 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x44 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x44 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x44 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x44 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x44 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x44 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x44 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x44 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x48 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_2,Enable Clear Register 18" bitfld.long 0x48 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x48 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x48 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x48 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x4C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_3,Enable Clear Register 19" bitfld.long 0x4C 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x4C 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x4C 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x4C 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x4C 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x4C 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_2_en_spare_pend_1_level" "0,1" newline bitfld.long 0x4C 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_2_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x4C 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_2_en_spare_pend_0_level" "0,1" newline bitfld.long 0x4C 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_2_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x4C 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x4C 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x4C 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x4C 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x4C 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x4C 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x4C 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x4C 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x4C 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x4C 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x4C 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x4C 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x4C 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x4C 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x50 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_4,Enable Clear Register 20" bitfld.long 0x50 31. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x50 30. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x50 29. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x50 28. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x50 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x50 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x50 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x50 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x50 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x50 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x50 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x50 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x50 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x50 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x50 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x50 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x50 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x50 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x50 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x50 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x50 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x50 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x50 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x50 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x50 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x50 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x50 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x50 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x50 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x50 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x50 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x50 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x54 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_5,Enable Clear Register 21" bitfld.long 0x54 31. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_63_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_63" "0,1" newline bitfld.long 0x54 30. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_62_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_62" "0,1" newline bitfld.long 0x54 29. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_61_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_61" "0,1" newline bitfld.long 0x54 28. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_60_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_60" "0,1" newline bitfld.long 0x54 27. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_59_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_59" "0,1" newline bitfld.long 0x54 26. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_58_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_58" "0,1" newline bitfld.long 0x54 25. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_57_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_57" "0,1" newline bitfld.long 0x54 24. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_56_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_56" "0,1" newline bitfld.long 0x54 23. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_55_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_55" "0,1" newline bitfld.long 0x54 22. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_54_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_54" "0,1" newline bitfld.long 0x54 21. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_53_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_53" "0,1" newline bitfld.long 0x54 20. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_52_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_52" "0,1" newline bitfld.long 0x54 19. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_51_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_51" "0,1" newline bitfld.long 0x54 18. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_50_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_50" "0,1" newline bitfld.long 0x54 17. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_49_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_49" "0,1" newline bitfld.long 0x54 16. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_48_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_48" "0,1" newline bitfld.long 0x54 15. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_47_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_47" "0,1" newline bitfld.long 0x54 14. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_46_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_46" "0,1" newline bitfld.long 0x54 13. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_45_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_45" "0,1" newline bitfld.long 0x54 12. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_44_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_44" "0,1" newline bitfld.long 0x54 11. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_43_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_43" "0,1" newline bitfld.long 0x54 10. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_42_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_42" "0,1" newline bitfld.long 0x54 9. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_41_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_41" "0,1" newline bitfld.long 0x54 8. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_40_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_40" "0,1" newline bitfld.long 0x54 7. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_39_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_39" "0,1" newline bitfld.long 0x54 6. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_38_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_38" "0,1" newline bitfld.long 0x54 5. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_37_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_37" "0,1" newline bitfld.long 0x54 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_36_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_36" "0,1" newline bitfld.long 0x54 3. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_35_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_35" "0,1" newline bitfld.long 0x54 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_34_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_34" "0,1" newline bitfld.long 0x54 1. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_33_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_33" "0,1" newline bitfld.long 0x54 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_COMPLETE_32_CLR,Enable Clear for level_vpac_out_2_en_utc0_complete_32" "0,1" line.long 0x58 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_6,Enable Clear Register 22" bitfld.long 0x58 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC1_RSVD_UNUSED_CLR,Enable Clear for level_vpac_out_2_en_utc1_rsvd_unused" "0,1" line.long 0x5C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_2_7,Enable Clear Register 23" bitfld.long 0x5C 4. "ENABLE_LEVEL_VPAC_OUT_2_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x5C 2. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x5C 0. "ENABLE_LEVEL_VPAC_OUT_2_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_2_en_utc0_error" "0,1" line.long 0x60 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_0,Enable Clear Register 24" bitfld.long 0x60 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x60 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x60 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x60 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x60 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x60 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x60 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x60 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x60 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x60 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x60 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x60 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x60 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x60 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x60 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x60 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x60 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x60 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x60 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x60 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x60 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x60 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x60 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x60 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x60 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x60 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x60 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x60 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x64 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_1,Enable Clear Register 25" bitfld.long 0x64 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x64 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x64 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x64 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x64 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x64 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x64 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x64 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x64 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x68 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_2,Enable Clear Register 26" bitfld.long 0x68 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x68 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x68 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x68 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x6C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_3,Enable Clear Register 27" bitfld.long 0x6C 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x6C 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x6C 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x6C 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x6C 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x6C 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_3_en_spare_pend_1_level" "0,1" newline bitfld.long 0x6C 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_3_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x6C 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_3_en_spare_pend_0_level" "0,1" newline bitfld.long 0x6C 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_3_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x6C 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x6C 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x6C 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x6C 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x6C 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x6C 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x6C 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x6C 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x6C 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x6C 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x6C 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x6C 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x6C 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x6C 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x70 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_4,Enable Clear Register 28" bitfld.long 0x70 31. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x70 30. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x70 29. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x70 28. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x70 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x70 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x70 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x70 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x70 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x70 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x70 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x70 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x70 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x70 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x70 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x70 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x70 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x70 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x70 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x70 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x70 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x70 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x70 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x70 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x70 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x70 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x70 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x70 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x70 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x70 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x70 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x70 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x74 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_5,Enable Clear Register 29" bitfld.long 0x74 31. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_63_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_63" "0,1" newline bitfld.long 0x74 30. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_62_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_62" "0,1" newline bitfld.long 0x74 29. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_61_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_61" "0,1" newline bitfld.long 0x74 28. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_60_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_60" "0,1" newline bitfld.long 0x74 27. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_59_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_59" "0,1" newline bitfld.long 0x74 26. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_58_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_58" "0,1" newline bitfld.long 0x74 25. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_57_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_57" "0,1" newline bitfld.long 0x74 24. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_56_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_56" "0,1" newline bitfld.long 0x74 23. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_55_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_55" "0,1" newline bitfld.long 0x74 22. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_54_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_54" "0,1" newline bitfld.long 0x74 21. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_53_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_53" "0,1" newline bitfld.long 0x74 20. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_52_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_52" "0,1" newline bitfld.long 0x74 19. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_51_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_51" "0,1" newline bitfld.long 0x74 18. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_50_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_50" "0,1" newline bitfld.long 0x74 17. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_49_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_49" "0,1" newline bitfld.long 0x74 16. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_48_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_48" "0,1" newline bitfld.long 0x74 15. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_47_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_47" "0,1" newline bitfld.long 0x74 14. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_46_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_46" "0,1" newline bitfld.long 0x74 13. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_45_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_45" "0,1" newline bitfld.long 0x74 12. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_44_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_44" "0,1" newline bitfld.long 0x74 11. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_43_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_43" "0,1" newline bitfld.long 0x74 10. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_42_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_42" "0,1" newline bitfld.long 0x74 9. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_41_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_41" "0,1" newline bitfld.long 0x74 8. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_40_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_40" "0,1" newline bitfld.long 0x74 7. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_39_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_39" "0,1" newline bitfld.long 0x74 6. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_38_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_38" "0,1" newline bitfld.long 0x74 5. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_37_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_37" "0,1" newline bitfld.long 0x74 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_36_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_36" "0,1" newline bitfld.long 0x74 3. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_35_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_35" "0,1" newline bitfld.long 0x74 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_34_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_34" "0,1" newline bitfld.long 0x74 1. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_33_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_33" "0,1" newline bitfld.long 0x74 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_COMPLETE_32_CLR,Enable Clear for level_vpac_out_3_en_utc0_complete_32" "0,1" line.long 0x78 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_6,Enable Clear Register 30" bitfld.long 0x78 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC1_RSVD_UNUSED_CLR,Enable Clear for level_vpac_out_3_en_utc1_rsvd_unused" "0,1" line.long 0x7C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_3_7,Enable Clear Register 31" bitfld.long 0x7C 4. "ENABLE_LEVEL_VPAC_OUT_3_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x7C 2. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x7C 0. "ENABLE_LEVEL_VPAC_OUT_3_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_3_en_utc0_error" "0,1" line.long 0x80 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_0,Enable Clear Register 32" bitfld.long 0x80 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x80 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x80 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x80 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x80 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x80 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x80 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x80 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x80 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x80 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x80 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x80 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x80 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x80 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x80 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x80 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x80 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x80 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x80 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x80 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x80 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x80 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x80 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x80 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x80 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x80 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x80 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x80 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x84 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_1,Enable Clear Register 33" bitfld.long 0x84 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x84 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x84 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x84 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x84 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x84 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x84 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x84 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x84 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x88 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_2,Enable Clear Register 34" bitfld.long 0x88 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x88 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x88 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x88 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x8C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_3,Enable Clear Register 35" bitfld.long 0x8C 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x8C 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x8C 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x8C 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x8C 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x8C 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_4_en_spare_pend_1_level" "0,1" newline bitfld.long 0x8C 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_4_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x8C 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_4_en_spare_pend_0_level" "0,1" newline bitfld.long 0x8C 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_4_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x8C 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x8C 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x8C 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x8C 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x8C 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x8C 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x8C 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x8C 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x8C 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x8C 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x8C 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x8C 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x8C 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x8C 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x90 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_4,Enable Clear Register 36" bitfld.long 0x90 31. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x90 30. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x90 29. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x90 28. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x90 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x90 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x90 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x90 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x90 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x90 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x90 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x90 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x90 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x90 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x90 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x90 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x90 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x90 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x90 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x90 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x90 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x90 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x90 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x90 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x90 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x90 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x90 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x90 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x90 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x90 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x90 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x90 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x94 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_5,Enable Clear Register 37" bitfld.long 0x94 31. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_63_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_63" "0,1" newline bitfld.long 0x94 30. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_62_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_62" "0,1" newline bitfld.long 0x94 29. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_61_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_61" "0,1" newline bitfld.long 0x94 28. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_60_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_60" "0,1" newline bitfld.long 0x94 27. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_59_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_59" "0,1" newline bitfld.long 0x94 26. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_58_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_58" "0,1" newline bitfld.long 0x94 25. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_57_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_57" "0,1" newline bitfld.long 0x94 24. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_56_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_56" "0,1" newline bitfld.long 0x94 23. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_55_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_55" "0,1" newline bitfld.long 0x94 22. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_54_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_54" "0,1" newline bitfld.long 0x94 21. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_53_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_53" "0,1" newline bitfld.long 0x94 20. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_52_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_52" "0,1" newline bitfld.long 0x94 19. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_51_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_51" "0,1" newline bitfld.long 0x94 18. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_50_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_50" "0,1" newline bitfld.long 0x94 17. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_49_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_49" "0,1" newline bitfld.long 0x94 16. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_48_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_48" "0,1" newline bitfld.long 0x94 15. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_47_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_47" "0,1" newline bitfld.long 0x94 14. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_46_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_46" "0,1" newline bitfld.long 0x94 13. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_45_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_45" "0,1" newline bitfld.long 0x94 12. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_44_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_44" "0,1" newline bitfld.long 0x94 11. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_43_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_43" "0,1" newline bitfld.long 0x94 10. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_42_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_42" "0,1" newline bitfld.long 0x94 9. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_41_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_41" "0,1" newline bitfld.long 0x94 8. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_40_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_40" "0,1" newline bitfld.long 0x94 7. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_39_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_39" "0,1" newline bitfld.long 0x94 6. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_38_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_38" "0,1" newline bitfld.long 0x94 5. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_37_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_37" "0,1" newline bitfld.long 0x94 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_36_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_36" "0,1" newline bitfld.long 0x94 3. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_35_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_35" "0,1" newline bitfld.long 0x94 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_34_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_34" "0,1" newline bitfld.long 0x94 1. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_33_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_33" "0,1" newline bitfld.long 0x94 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_COMPLETE_32_CLR,Enable Clear for level_vpac_out_4_en_utc0_complete_32" "0,1" line.long 0x98 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_6,Enable Clear Register 38" bitfld.long 0x98 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC1_RSVD_UNUSED_CLR,Enable Clear for level_vpac_out_4_en_utc1_rsvd_unused" "0,1" line.long 0x9C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_4_7,Enable Clear Register 39" bitfld.long 0x9C 4. "ENABLE_LEVEL_VPAC_OUT_4_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x9C 2. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x9C 0. "ENABLE_LEVEL_VPAC_OUT_4_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_4_en_utc0_error" "0,1" line.long 0xA0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_0,Enable Clear Register 40" bitfld.long 0xA0 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0xA0 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xA0 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xA0 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for level_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xA0 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xA0 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA0 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA0 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xA0 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xA0 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xA0 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xA0 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xA0 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xA0 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xA0 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xA0 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xA0 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xA0 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xA0 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xA0 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xA0 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xA0 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xA0 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xA0 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xA0 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xA0 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xA0 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xA0 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for level_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0xA4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_1,Enable Clear Register 41" bitfld.long 0xA4 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for level_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xA4 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xA4 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for level_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xA4 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_INT_SZOVF_CLR,Enable Clear for level_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xA4 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xA4 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xA4 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for level_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xA4 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xA4 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for level_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xA8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_2,Enable Clear Register 42" bitfld.long 0xA8 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for level_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA8 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for level_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA8 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for level_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xA8 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for level_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xAC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_3,Enable Clear Register 43" bitfld.long 0xAC 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for level_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xAC 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for level_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xAC 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for level_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xAC 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for level_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xAC 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for level_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xAC 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for level_vpac_out_5_en_spare_pend_1_level" "0,1" newline bitfld.long 0xAC 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for level_vpac_out_5_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xAC 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for level_vpac_out_5_en_spare_pend_0_level" "0,1" newline bitfld.long 0xAC 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for level_vpac_out_5_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xAC 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_DEC_1_CLR,Enable Clear for level_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0xAC 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_SPARE_DEC_0_CLR,Enable Clear for level_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0xAC 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_6_CLR,Enable Clear for level_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0xAC 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_5_CLR,Enable Clear for level_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0xAC 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_4_CLR,Enable Clear for level_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0xAC 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_2_CLR,Enable Clear for level_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0xAC 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_TDONE_0_CLR,Enable Clear for level_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0xAC 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_6_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0xAC 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_5_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0xAC 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_4_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0xAC 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_3_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0xAC 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_2_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0xAC 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_1_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0xAC 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_PIPE_DONE_0_CLR,Enable Clear for level_vpac_out_5_en_pipe_done_0" "0,1" line.long 0xB0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_4,Enable Clear Register 44" bitfld.long 0xB0 31. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_31_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0xB0 30. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_30_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0xB0 29. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_29_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0xB0 28. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_28_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0xB0 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_27_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0xB0 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_26_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0xB0 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_25_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0xB0 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_24_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0xB0 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_23_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0xB0 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_22_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0xB0 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_21_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0xB0 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_20_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0xB0 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_19_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0xB0 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_18_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0xB0 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_17_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0xB0 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_16_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0xB0 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_15_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0xB0 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_14_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0xB0 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_13_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0xB0 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_12_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0xB0 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_11_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0xB0 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_10_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0xB0 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_9_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0xB0 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_8_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0xB0 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_7_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0xB0 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_6_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0xB0 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_5_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0xB0 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_4_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0xB0 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_3_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0xB0 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_2_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0xB0 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_1_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0xB0 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_0_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0xB4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_5,Enable Clear Register 45" bitfld.long 0xB4 31. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_63_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_63" "0,1" newline bitfld.long 0xB4 30. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_62_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_62" "0,1" newline bitfld.long 0xB4 29. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_61_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_61" "0,1" newline bitfld.long 0xB4 28. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_60_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_60" "0,1" newline bitfld.long 0xB4 27. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_59_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_59" "0,1" newline bitfld.long 0xB4 26. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_58_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_58" "0,1" newline bitfld.long 0xB4 25. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_57_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_57" "0,1" newline bitfld.long 0xB4 24. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_56_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_56" "0,1" newline bitfld.long 0xB4 23. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_55_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_55" "0,1" newline bitfld.long 0xB4 22. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_54_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_54" "0,1" newline bitfld.long 0xB4 21. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_53_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_53" "0,1" newline bitfld.long 0xB4 20. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_52_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_52" "0,1" newline bitfld.long 0xB4 19. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_51_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_51" "0,1" newline bitfld.long 0xB4 18. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_50_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_50" "0,1" newline bitfld.long 0xB4 17. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_49_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_49" "0,1" newline bitfld.long 0xB4 16. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_48_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_48" "0,1" newline bitfld.long 0xB4 15. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_47_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_47" "0,1" newline bitfld.long 0xB4 14. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_46_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_46" "0,1" newline bitfld.long 0xB4 13. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_45_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_45" "0,1" newline bitfld.long 0xB4 12. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_44_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_44" "0,1" newline bitfld.long 0xB4 11. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_43_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_43" "0,1" newline bitfld.long 0xB4 10. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_42_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_42" "0,1" newline bitfld.long 0xB4 9. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_41_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_41" "0,1" newline bitfld.long 0xB4 8. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_40_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_40" "0,1" newline bitfld.long 0xB4 7. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_39_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_39" "0,1" newline bitfld.long 0xB4 6. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_38_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_38" "0,1" newline bitfld.long 0xB4 5. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_37_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_37" "0,1" newline bitfld.long 0xB4 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_36_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_36" "0,1" newline bitfld.long 0xB4 3. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_35_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_35" "0,1" newline bitfld.long 0xB4 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_34_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_34" "0,1" newline bitfld.long 0xB4 1. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_33_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_33" "0,1" newline bitfld.long 0xB4 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_COMPLETE_32_CLR,Enable Clear for level_vpac_out_5_en_utc0_complete_32" "0,1" line.long 0xB8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_6,Enable Clear Register 46" bitfld.long 0xB8 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC1_RSVD_UNUSED_CLR,Enable Clear for level_vpac_out_5_en_utc1_rsvd_unused" "0,1" line.long 0xBC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_vpac_out_5_7,Enable Clear Register 47" bitfld.long 0xBC 4. "ENABLE_LEVEL_VPAC_OUT_5_EN_CTM_PULSE_CLR,Enable Clear for level_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0xBC 2. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_PROT_ERR_CLR,Enable Clear for level_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0xBC 0. "ENABLE_LEVEL_VPAC_OUT_5_EN_UTC0_ERROR_CLR,Enable Clear for level_vpac_out_5_en_utc0_error" "0,1" line.long 0xC0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_0,Enable Clear Register 48" bitfld.long 0xC0 27. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0xC0 26. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xC0 25. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xC0 24. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xC0 23. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xC0 22. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC0 21. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC0 20. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xC0 19. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xC0 18. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xC0 17. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xC0 16. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xC0 15. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xC0 14. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xC0 13. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xC0 12. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xC0 11. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xC0 10. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xC0 9. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xC0 8. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xC0 7. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xC0 6. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xC0 5. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xC0 4. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xC0 3. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xC0 2. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xC0 1. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xC0 0. "ENABLE_PULSE_VPAC_OUT_0_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0xC4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_1,Enable Clear Register 49" bitfld.long 0xC4 8. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xC4 7. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xC4 6. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xC4 5. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xC4 4. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xC4 3. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xC4 2. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xC4 1. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xC4 0. "ENABLE_PULSE_VPAC_OUT_0_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xC8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_2,Enable Clear Register 50" bitfld.long 0xC8 3. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC8 2. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC8 1. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xC8 0. "ENABLE_PULSE_VPAC_OUT_0_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xCC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_3,Enable Clear Register 51" bitfld.long 0xCC 26. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xCC 25. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xCC 24. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xCC 22. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xCC 20. "ENABLE_PULSE_VPAC_OUT_0_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xCC 19. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_0_en_spare_pend_1_level" "0,1" newline bitfld.long 0xCC 18. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xCC 17. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_0_en_spare_pend_0_level" "0,1" newline bitfld.long 0xCC 16. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xCC 15. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xCC 14. "ENABLE_PULSE_VPAC_OUT_0_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xCC 13. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xCC 12. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xCC 11. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xCC 9. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xCC 7. "ENABLE_PULSE_VPAC_OUT_0_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xCC 6. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xCC 5. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xCC 4. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xCC 3. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xCC 2. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xCC 1. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xCC 0. "ENABLE_PULSE_VPAC_OUT_0_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_0_en_pipe_done_0" "0,1" line.long 0xD0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_4,Enable Clear Register 52" bitfld.long 0xD0 31. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0xD0 30. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0xD0 29. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0xD0 28. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0xD0 27. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0xD0 26. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0xD0 25. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0xD0 24. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0xD0 23. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0xD0 22. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0xD0 21. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0xD0 20. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0xD0 19. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0xD0 18. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0xD0 17. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0xD0 16. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0xD0 15. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0xD0 14. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0xD0 13. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0xD0 12. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0xD0 11. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0xD0 10. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0xD0 9. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0xD0 8. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0xD0 7. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0xD0 6. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0xD0 5. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0xD0 4. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0xD0 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0xD0 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0xD0 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0xD0 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0xD4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_5,Enable Clear Register 53" bitfld.long 0xD4 31. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_63" "0,1" newline bitfld.long 0xD4 30. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_62" "0,1" newline bitfld.long 0xD4 29. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_61" "0,1" newline bitfld.long 0xD4 28. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_60" "0,1" newline bitfld.long 0xD4 27. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_59" "0,1" newline bitfld.long 0xD4 26. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_58" "0,1" newline bitfld.long 0xD4 25. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_57" "0,1" newline bitfld.long 0xD4 24. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_56" "0,1" newline bitfld.long 0xD4 23. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_55" "0,1" newline bitfld.long 0xD4 22. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_54" "0,1" newline bitfld.long 0xD4 21. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_53" "0,1" newline bitfld.long 0xD4 20. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_52" "0,1" newline bitfld.long 0xD4 19. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_51" "0,1" newline bitfld.long 0xD4 18. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_50" "0,1" newline bitfld.long 0xD4 17. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_49" "0,1" newline bitfld.long 0xD4 16. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_48" "0,1" newline bitfld.long 0xD4 15. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_47" "0,1" newline bitfld.long 0xD4 14. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_46" "0,1" newline bitfld.long 0xD4 13. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_45" "0,1" newline bitfld.long 0xD4 12. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_44" "0,1" newline bitfld.long 0xD4 11. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_43" "0,1" newline bitfld.long 0xD4 10. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_42" "0,1" newline bitfld.long 0xD4 9. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_41" "0,1" newline bitfld.long 0xD4 8. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_40" "0,1" newline bitfld.long 0xD4 7. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_39" "0,1" newline bitfld.long 0xD4 6. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_38" "0,1" newline bitfld.long 0xD4 5. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_37" "0,1" newline bitfld.long 0xD4 4. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_36" "0,1" newline bitfld.long 0xD4 3. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_35" "0,1" newline bitfld.long 0xD4 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_34" "0,1" newline bitfld.long 0xD4 1. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_33" "0,1" newline bitfld.long 0xD4 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_complete_32" "0,1" line.long 0xD8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_6,Enable Clear Register 54" bitfld.long 0xD8 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC1_RSVD_UNUSED_CLR,Enable Clear for pulse_vpac_out_0_en_utc1_rsvd_unused" "0,1" line.long 0xDC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_0_7,Enable Clear Register 55" bitfld.long 0xDC 4. "ENABLE_PULSE_VPAC_OUT_0_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0xDC 2. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0xDC 0. "ENABLE_PULSE_VPAC_OUT_0_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_0_en_utc0_error" "0,1" line.long 0xE0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_0,Enable Clear Register 56" bitfld.long 0xE0 27. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0xE0 26. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xE0 25. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xE0 24. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xE0 23. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xE0 22. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE0 21. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE0 20. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xE0 19. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xE0 18. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xE0 17. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xE0 16. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xE0 15. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xE0 14. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xE0 13. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xE0 12. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xE0 11. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xE0 10. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xE0 9. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xE0 8. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xE0 7. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xE0 6. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xE0 5. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xE0 4. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xE0 3. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xE0 2. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xE0 1. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xE0 0. "ENABLE_PULSE_VPAC_OUT_1_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0xE4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_1,Enable Clear Register 57" bitfld.long 0xE4 8. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xE4 7. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xE4 6. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xE4 5. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xE4 4. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xE4 3. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xE4 2. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xE4 1. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xE4 0. "ENABLE_PULSE_VPAC_OUT_1_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xE8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_2,Enable Clear Register 58" bitfld.long 0xE8 3. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE8 2. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE8 1. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xE8 0. "ENABLE_PULSE_VPAC_OUT_1_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xEC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_3,Enable Clear Register 59" bitfld.long 0xEC 26. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xEC 25. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xEC 24. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xEC 22. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xEC 20. "ENABLE_PULSE_VPAC_OUT_1_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xEC 19. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_1_en_spare_pend_1_level" "0,1" newline bitfld.long 0xEC 18. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0xEC 17. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_1_en_spare_pend_0_level" "0,1" newline bitfld.long 0xEC 16. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xEC 15. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0xEC 14. "ENABLE_PULSE_VPAC_OUT_1_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0xEC 13. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0xEC 12. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0xEC 11. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0xEC 9. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0xEC 7. "ENABLE_PULSE_VPAC_OUT_1_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0xEC 6. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0xEC 5. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0xEC 4. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0xEC 3. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0xEC 2. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0xEC 1. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0xEC 0. "ENABLE_PULSE_VPAC_OUT_1_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_1_en_pipe_done_0" "0,1" line.long 0xF0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_4,Enable Clear Register 60" bitfld.long 0xF0 31. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0xF0 30. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0xF0 29. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0xF0 28. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0xF0 27. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0xF0 26. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0xF0 25. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0xF0 24. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0xF0 23. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0xF0 22. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0xF0 21. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0xF0 20. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0xF0 19. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0xF0 18. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0xF0 17. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0xF0 16. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0xF0 15. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0xF0 14. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0xF0 13. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0xF0 12. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0xF0 11. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0xF0 10. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0xF0 9. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0xF0 8. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0xF0 7. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0xF0 6. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0xF0 5. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0xF0 4. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0xF0 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0xF0 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0xF0 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0xF0 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0xF4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_5,Enable Clear Register 61" bitfld.long 0xF4 31. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_63" "0,1" newline bitfld.long 0xF4 30. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_62" "0,1" newline bitfld.long 0xF4 29. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_61" "0,1" newline bitfld.long 0xF4 28. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_60" "0,1" newline bitfld.long 0xF4 27. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_59" "0,1" newline bitfld.long 0xF4 26. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_58" "0,1" newline bitfld.long 0xF4 25. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_57" "0,1" newline bitfld.long 0xF4 24. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_56" "0,1" newline bitfld.long 0xF4 23. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_55" "0,1" newline bitfld.long 0xF4 22. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_54" "0,1" newline bitfld.long 0xF4 21. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_53" "0,1" newline bitfld.long 0xF4 20. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_52" "0,1" newline bitfld.long 0xF4 19. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_51" "0,1" newline bitfld.long 0xF4 18. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_50" "0,1" newline bitfld.long 0xF4 17. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_49" "0,1" newline bitfld.long 0xF4 16. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_48" "0,1" newline bitfld.long 0xF4 15. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_47" "0,1" newline bitfld.long 0xF4 14. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_46" "0,1" newline bitfld.long 0xF4 13. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_45" "0,1" newline bitfld.long 0xF4 12. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_44" "0,1" newline bitfld.long 0xF4 11. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_43" "0,1" newline bitfld.long 0xF4 10. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_42" "0,1" newline bitfld.long 0xF4 9. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_41" "0,1" newline bitfld.long 0xF4 8. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_40" "0,1" newline bitfld.long 0xF4 7. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_39" "0,1" newline bitfld.long 0xF4 6. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_38" "0,1" newline bitfld.long 0xF4 5. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_37" "0,1" newline bitfld.long 0xF4 4. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_36" "0,1" newline bitfld.long 0xF4 3. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_35" "0,1" newline bitfld.long 0xF4 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_34" "0,1" newline bitfld.long 0xF4 1. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_33" "0,1" newline bitfld.long 0xF4 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_complete_32" "0,1" line.long 0xF8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_6,Enable Clear Register 62" bitfld.long 0xF8 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC1_RSVD_UNUSED_CLR,Enable Clear for pulse_vpac_out_1_en_utc1_rsvd_unused" "0,1" line.long 0xFC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_1_7,Enable Clear Register 63" bitfld.long 0xFC 4. "ENABLE_PULSE_VPAC_OUT_1_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0xFC 2. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0xFC 0. "ENABLE_PULSE_VPAC_OUT_1_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_1_en_utc0_error" "0,1" line.long 0x100 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_0,Enable Clear Register 64" bitfld.long 0x100 27. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x100 26. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x100 25. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x100 24. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x100 23. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x100 22. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x100 21. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x100 20. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x100 19. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x100 18. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x100 17. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x100 16. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x100 15. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x100 14. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x100 13. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x100 12. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x100 11. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x100 10. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x100 9. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x100 8. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x100 7. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x100 6. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x100 5. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x100 4. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x100 3. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x100 2. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x100 1. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x100 0. "ENABLE_PULSE_VPAC_OUT_2_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x104 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_1,Enable Clear Register 65" bitfld.long 0x104 8. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x104 7. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x104 6. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x104 5. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x104 4. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x104 3. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x104 2. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x104 1. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x104 0. "ENABLE_PULSE_VPAC_OUT_2_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x108 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_2,Enable Clear Register 66" bitfld.long 0x108 3. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x108 2. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x108 1. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x108 0. "ENABLE_PULSE_VPAC_OUT_2_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x10C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_3,Enable Clear Register 67" bitfld.long 0x10C 26. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x10C 25. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x10C 24. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x10C 22. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x10C 20. "ENABLE_PULSE_VPAC_OUT_2_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x10C 19. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_2_en_spare_pend_1_level" "0,1" newline bitfld.long 0x10C 18. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x10C 17. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_2_en_spare_pend_0_level" "0,1" newline bitfld.long 0x10C 16. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x10C 15. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x10C 14. "ENABLE_PULSE_VPAC_OUT_2_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x10C 13. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x10C 12. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x10C 11. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x10C 9. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x10C 7. "ENABLE_PULSE_VPAC_OUT_2_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x10C 6. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x10C 5. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x10C 4. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x10C 3. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x10C 2. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x10C 1. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x10C 0. "ENABLE_PULSE_VPAC_OUT_2_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x110 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_4,Enable Clear Register 68" bitfld.long 0x110 31. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x110 30. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x110 29. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x110 28. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x110 27. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x110 26. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x110 25. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x110 24. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x110 23. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x110 22. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x110 21. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x110 20. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x110 19. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x110 18. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x110 17. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x110 16. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x110 15. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x110 14. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x110 13. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x110 12. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x110 11. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x110 10. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x110 9. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x110 8. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x110 7. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x110 6. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x110 5. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x110 4. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x110 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x110 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x110 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x110 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x114 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_5,Enable Clear Register 69" bitfld.long 0x114 31. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_63" "0,1" newline bitfld.long 0x114 30. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_62" "0,1" newline bitfld.long 0x114 29. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_61" "0,1" newline bitfld.long 0x114 28. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_60" "0,1" newline bitfld.long 0x114 27. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_59" "0,1" newline bitfld.long 0x114 26. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_58" "0,1" newline bitfld.long 0x114 25. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_57" "0,1" newline bitfld.long 0x114 24. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_56" "0,1" newline bitfld.long 0x114 23. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_55" "0,1" newline bitfld.long 0x114 22. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_54" "0,1" newline bitfld.long 0x114 21. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_53" "0,1" newline bitfld.long 0x114 20. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_52" "0,1" newline bitfld.long 0x114 19. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_51" "0,1" newline bitfld.long 0x114 18. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_50" "0,1" newline bitfld.long 0x114 17. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_49" "0,1" newline bitfld.long 0x114 16. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_48" "0,1" newline bitfld.long 0x114 15. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_47" "0,1" newline bitfld.long 0x114 14. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_46" "0,1" newline bitfld.long 0x114 13. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_45" "0,1" newline bitfld.long 0x114 12. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_44" "0,1" newline bitfld.long 0x114 11. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_43" "0,1" newline bitfld.long 0x114 10. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_42" "0,1" newline bitfld.long 0x114 9. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_41" "0,1" newline bitfld.long 0x114 8. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_40" "0,1" newline bitfld.long 0x114 7. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_39" "0,1" newline bitfld.long 0x114 6. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_38" "0,1" newline bitfld.long 0x114 5. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_37" "0,1" newline bitfld.long 0x114 4. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_36" "0,1" newline bitfld.long 0x114 3. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_35" "0,1" newline bitfld.long 0x114 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_34" "0,1" newline bitfld.long 0x114 1. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_33" "0,1" newline bitfld.long 0x114 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_complete_32" "0,1" line.long 0x118 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_6,Enable Clear Register 70" bitfld.long 0x118 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC1_RSVD_UNUSED_CLR,Enable Clear for pulse_vpac_out_2_en_utc1_rsvd_unused" "0,1" line.long 0x11C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_2_7,Enable Clear Register 71" bitfld.long 0x11C 4. "ENABLE_PULSE_VPAC_OUT_2_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x11C 2. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x11C 0. "ENABLE_PULSE_VPAC_OUT_2_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_2_en_utc0_error" "0,1" line.long 0x120 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_0,Enable Clear Register 72" bitfld.long 0x120 27. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x120 26. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x120 25. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x120 24. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x120 23. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x120 22. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x120 21. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x120 20. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x120 19. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x120 18. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x120 17. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x120 16. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x120 15. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x120 14. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x120 13. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x120 12. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x120 11. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x120 10. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x120 9. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x120 8. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x120 7. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x120 6. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x120 5. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x120 4. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x120 3. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x120 2. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x120 1. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x120 0. "ENABLE_PULSE_VPAC_OUT_3_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x124 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_1,Enable Clear Register 73" bitfld.long 0x124 8. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x124 7. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x124 6. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x124 5. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x124 4. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x124 3. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x124 2. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x124 1. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x124 0. "ENABLE_PULSE_VPAC_OUT_3_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x128 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_2,Enable Clear Register 74" bitfld.long 0x128 3. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x128 2. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x128 1. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x128 0. "ENABLE_PULSE_VPAC_OUT_3_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x12C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_3,Enable Clear Register 75" bitfld.long 0x12C 26. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x12C 25. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x12C 24. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x12C 22. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x12C 20. "ENABLE_PULSE_VPAC_OUT_3_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x12C 19. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_3_en_spare_pend_1_level" "0,1" newline bitfld.long 0x12C 18. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x12C 17. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_3_en_spare_pend_0_level" "0,1" newline bitfld.long 0x12C 16. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x12C 15. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x12C 14. "ENABLE_PULSE_VPAC_OUT_3_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x12C 13. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x12C 12. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x12C 11. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x12C 9. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x12C 7. "ENABLE_PULSE_VPAC_OUT_3_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x12C 6. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x12C 5. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x12C 4. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x12C 3. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x12C 2. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x12C 1. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x12C 0. "ENABLE_PULSE_VPAC_OUT_3_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x130 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_4,Enable Clear Register 76" bitfld.long 0x130 31. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x130 30. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x130 29. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x130 28. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x130 27. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x130 26. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x130 25. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x130 24. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x130 23. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x130 22. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x130 21. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x130 20. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x130 19. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x130 18. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x130 17. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x130 16. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x130 15. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x130 14. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x130 13. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x130 12. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x130 11. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x130 10. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x130 9. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x130 8. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x130 7. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x130 6. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x130 5. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x130 4. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x130 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x130 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x130 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x130 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x134 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_5,Enable Clear Register 77" bitfld.long 0x134 31. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_63" "0,1" newline bitfld.long 0x134 30. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_62" "0,1" newline bitfld.long 0x134 29. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_61" "0,1" newline bitfld.long 0x134 28. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_60" "0,1" newline bitfld.long 0x134 27. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_59" "0,1" newline bitfld.long 0x134 26. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_58" "0,1" newline bitfld.long 0x134 25. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_57" "0,1" newline bitfld.long 0x134 24. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_56" "0,1" newline bitfld.long 0x134 23. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_55" "0,1" newline bitfld.long 0x134 22. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_54" "0,1" newline bitfld.long 0x134 21. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_53" "0,1" newline bitfld.long 0x134 20. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_52" "0,1" newline bitfld.long 0x134 19. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_51" "0,1" newline bitfld.long 0x134 18. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_50" "0,1" newline bitfld.long 0x134 17. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_49" "0,1" newline bitfld.long 0x134 16. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_48" "0,1" newline bitfld.long 0x134 15. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_47" "0,1" newline bitfld.long 0x134 14. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_46" "0,1" newline bitfld.long 0x134 13. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_45" "0,1" newline bitfld.long 0x134 12. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_44" "0,1" newline bitfld.long 0x134 11. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_43" "0,1" newline bitfld.long 0x134 10. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_42" "0,1" newline bitfld.long 0x134 9. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_41" "0,1" newline bitfld.long 0x134 8. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_40" "0,1" newline bitfld.long 0x134 7. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_39" "0,1" newline bitfld.long 0x134 6. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_38" "0,1" newline bitfld.long 0x134 5. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_37" "0,1" newline bitfld.long 0x134 4. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_36" "0,1" newline bitfld.long 0x134 3. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_35" "0,1" newline bitfld.long 0x134 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_34" "0,1" newline bitfld.long 0x134 1. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_33" "0,1" newline bitfld.long 0x134 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_complete_32" "0,1" line.long 0x138 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_6,Enable Clear Register 78" bitfld.long 0x138 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC1_RSVD_UNUSED_CLR,Enable Clear for pulse_vpac_out_3_en_utc1_rsvd_unused" "0,1" line.long 0x13C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_3_7,Enable Clear Register 79" bitfld.long 0x13C 4. "ENABLE_PULSE_VPAC_OUT_3_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x13C 2. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x13C 0. "ENABLE_PULSE_VPAC_OUT_3_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_3_en_utc0_error" "0,1" line.long 0x140 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_0,Enable Clear Register 80" bitfld.long 0x140 27. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x140 26. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x140 25. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x140 24. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x140 23. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x140 22. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x140 21. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x140 20. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x140 19. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x140 18. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x140 17. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x140 16. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x140 15. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x140 14. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x140 13. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x140 12. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x140 11. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x140 10. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x140 9. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x140 8. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x140 7. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x140 6. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x140 5. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x140 4. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x140 3. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x140 2. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x140 1. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x140 0. "ENABLE_PULSE_VPAC_OUT_4_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x144 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_1,Enable Clear Register 81" bitfld.long 0x144 8. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x144 7. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x144 6. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x144 5. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x144 4. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x144 3. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x144 2. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x144 1. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x144 0. "ENABLE_PULSE_VPAC_OUT_4_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x148 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_2,Enable Clear Register 82" bitfld.long 0x148 3. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x148 2. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x148 1. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x148 0. "ENABLE_PULSE_VPAC_OUT_4_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x14C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_3,Enable Clear Register 83" bitfld.long 0x14C 26. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x14C 25. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x14C 24. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x14C 22. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x14C 20. "ENABLE_PULSE_VPAC_OUT_4_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x14C 19. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_4_en_spare_pend_1_level" "0,1" newline bitfld.long 0x14C 18. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x14C 17. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_4_en_spare_pend_0_level" "0,1" newline bitfld.long 0x14C 16. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x14C 15. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x14C 14. "ENABLE_PULSE_VPAC_OUT_4_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x14C 13. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x14C 12. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x14C 11. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x14C 9. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x14C 7. "ENABLE_PULSE_VPAC_OUT_4_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x14C 6. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x14C 5. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x14C 4. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x14C 3. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x14C 2. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x14C 1. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x14C 0. "ENABLE_PULSE_VPAC_OUT_4_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x150 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_4,Enable Clear Register 84" bitfld.long 0x150 31. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x150 30. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x150 29. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x150 28. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x150 27. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x150 26. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x150 25. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x150 24. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x150 23. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x150 22. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x150 21. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x150 20. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x150 19. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x150 18. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x150 17. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x150 16. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x150 15. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x150 14. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x150 13. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x150 12. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x150 11. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x150 10. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x150 9. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x150 8. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x150 7. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x150 6. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x150 5. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x150 4. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x150 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x150 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x150 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x150 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x154 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_5,Enable Clear Register 85" bitfld.long 0x154 31. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_63" "0,1" newline bitfld.long 0x154 30. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_62" "0,1" newline bitfld.long 0x154 29. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_61" "0,1" newline bitfld.long 0x154 28. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_60" "0,1" newline bitfld.long 0x154 27. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_59" "0,1" newline bitfld.long 0x154 26. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_58" "0,1" newline bitfld.long 0x154 25. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_57" "0,1" newline bitfld.long 0x154 24. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_56" "0,1" newline bitfld.long 0x154 23. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_55" "0,1" newline bitfld.long 0x154 22. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_54" "0,1" newline bitfld.long 0x154 21. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_53" "0,1" newline bitfld.long 0x154 20. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_52" "0,1" newline bitfld.long 0x154 19. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_51" "0,1" newline bitfld.long 0x154 18. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_50" "0,1" newline bitfld.long 0x154 17. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_49" "0,1" newline bitfld.long 0x154 16. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_48" "0,1" newline bitfld.long 0x154 15. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_47" "0,1" newline bitfld.long 0x154 14. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_46" "0,1" newline bitfld.long 0x154 13. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_45" "0,1" newline bitfld.long 0x154 12. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_44" "0,1" newline bitfld.long 0x154 11. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_43" "0,1" newline bitfld.long 0x154 10. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_42" "0,1" newline bitfld.long 0x154 9. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_41" "0,1" newline bitfld.long 0x154 8. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_40" "0,1" newline bitfld.long 0x154 7. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_39" "0,1" newline bitfld.long 0x154 6. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_38" "0,1" newline bitfld.long 0x154 5. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_37" "0,1" newline bitfld.long 0x154 4. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_36" "0,1" newline bitfld.long 0x154 3. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_35" "0,1" newline bitfld.long 0x154 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_34" "0,1" newline bitfld.long 0x154 1. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_33" "0,1" newline bitfld.long 0x154 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_complete_32" "0,1" line.long 0x158 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_6,Enable Clear Register 86" bitfld.long 0x158 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC1_RSVD_UNUSED_CLR,Enable Clear for pulse_vpac_out_4_en_utc1_rsvd_unused" "0,1" line.long 0x15C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_4_7,Enable Clear Register 87" bitfld.long 0x15C 4. "ENABLE_PULSE_VPAC_OUT_4_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x15C 2. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x15C 0. "ENABLE_PULSE_VPAC_OUT_4_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_4_en_utc0_error" "0,1" line.long 0x160 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_0,Enable Clear Register 88" bitfld.long 0x160 27. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x160 26. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_CR_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x160 25. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_X_Y_POINTER_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x160 24. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_OUT_FR_START_EVT_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x160 23. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_CAL_VP_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x160 22. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x160 21. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x160 20. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_LSE_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x160 19. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_EE_SYNCOVF_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x160 18. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_EE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x160 17. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_HIST_READ_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x160 16. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_OUTIF_OVF_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x160 15. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCC_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x160 14. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_FCFA_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x160 13. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_VP_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x160 12. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_VSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x160 11. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_HSYNC_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x160 10. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_DONE_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x160 9. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_FILT_START_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x160 8. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_GLBCE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x160 7. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_VBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x160 6. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_HBLANK_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x160 5. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x160 4. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x160 3. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_H3A_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x160 2. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_AF_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x160 1. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_AEW_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x160 0. "ENABLE_PULSE_VPAC_OUT_5_EN_VISS0_RAWFE_CFG_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0x164 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_1,Enable Clear Register 89" bitfld.long 0x164 8. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_VBUSM_RD_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x164 7. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x164 6. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_FR_DONE_EVT_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x164 5. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_INT_SZOVF_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x164 4. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_IFR_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x164 3. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_MESH_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x164 2. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_PIX_IBLK_MEMOVF_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x164 1. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x164 0. "ENABLE_PULSE_VPAC_OUT_5_EN_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Enable Clear for pulse_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x168 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_2,Enable Clear Register 90" bitfld.long 0x168 3. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_SL2_WR_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x168 2. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_SL2_RD_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x168 1. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_1_CLR,Enable Clear for pulse_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x168 0. "ENABLE_PULSE_VPAC_OUT_5_EN_MSC_LSE_FR_DONE_EVT_0_CLR,Enable Clear for pulse_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x16C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_3,Enable Clear Register 91" bitfld.long 0x16C 26. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_6_CLR,Enable Clear for pulse_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x16C 25. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_5_CLR,Enable Clear for pulse_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x16C 24. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_4_CLR,Enable Clear for pulse_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x16C 22. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_2_CLR,Enable Clear for pulse_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x16C 20. "ENABLE_PULSE_VPAC_OUT_5_EN_WATCHDOGTIMER_ERR_0_CLR,Enable Clear for pulse_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x16C 19. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_1_LEVEL_CLR,Enable Clear for pulse_vpac_out_5_en_spare_pend_1_level" "0,1" newline bitfld.long 0x16C 18. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_1_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_spare_pend_1_pulse" "0,1" newline bitfld.long 0x16C 17. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_0_LEVEL_CLR,Enable Clear for pulse_vpac_out_5_en_spare_pend_0_level" "0,1" newline bitfld.long 0x16C 16. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_PEND_0_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x16C 15. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_DEC_1_CLR,Enable Clear for pulse_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0x16C 14. "ENABLE_PULSE_VPAC_OUT_5_EN_SPARE_DEC_0_CLR,Enable Clear for pulse_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0x16C 13. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_6_CLR,Enable Clear for pulse_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0x16C 12. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_5_CLR,Enable Clear for pulse_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0x16C 11. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_4_CLR,Enable Clear for pulse_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0x16C 9. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_2_CLR,Enable Clear for pulse_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0x16C 7. "ENABLE_PULSE_VPAC_OUT_5_EN_TDONE_0_CLR,Enable Clear for pulse_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0x16C 6. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_6_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0x16C 5. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_5_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0x16C 4. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_4_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0x16C 3. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_3_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0x16C 2. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_2_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0x16C 1. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_1_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0x16C 0. "ENABLE_PULSE_VPAC_OUT_5_EN_PIPE_DONE_0_CLR,Enable Clear for pulse_vpac_out_5_en_pipe_done_0" "0,1" line.long 0x170 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_4,Enable Clear Register 92" bitfld.long 0x170 31. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_31_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0x170 30. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_30_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0x170 29. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_29_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0x170 28. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_28_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0x170 27. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_27_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0x170 26. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_26_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0x170 25. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_25_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0x170 24. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_24_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0x170 23. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_23_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0x170 22. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_22_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0x170 21. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_21_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0x170 20. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_20_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0x170 19. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_19_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0x170 18. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_18_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0x170 17. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_17_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0x170 16. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_16_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0x170 15. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_15_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0x170 14. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_14_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0x170 13. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_13_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0x170 12. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_12_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0x170 11. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_11_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0x170 10. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_10_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0x170 9. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_9_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0x170 8. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_8_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0x170 7. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_7_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0x170 6. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_6_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0x170 5. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_5_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0x170 4. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_4_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0x170 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_3_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0x170 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_2_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0x170 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_1_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0x170 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_0_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0x174 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_5,Enable Clear Register 93" bitfld.long 0x174 31. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_63_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_63" "0,1" newline bitfld.long 0x174 30. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_62_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_62" "0,1" newline bitfld.long 0x174 29. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_61_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_61" "0,1" newline bitfld.long 0x174 28. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_60_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_60" "0,1" newline bitfld.long 0x174 27. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_59_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_59" "0,1" newline bitfld.long 0x174 26. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_58_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_58" "0,1" newline bitfld.long 0x174 25. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_57_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_57" "0,1" newline bitfld.long 0x174 24. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_56_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_56" "0,1" newline bitfld.long 0x174 23. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_55_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_55" "0,1" newline bitfld.long 0x174 22. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_54_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_54" "0,1" newline bitfld.long 0x174 21. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_53_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_53" "0,1" newline bitfld.long 0x174 20. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_52_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_52" "0,1" newline bitfld.long 0x174 19. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_51_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_51" "0,1" newline bitfld.long 0x174 18. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_50_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_50" "0,1" newline bitfld.long 0x174 17. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_49_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_49" "0,1" newline bitfld.long 0x174 16. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_48_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_48" "0,1" newline bitfld.long 0x174 15. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_47_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_47" "0,1" newline bitfld.long 0x174 14. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_46_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_46" "0,1" newline bitfld.long 0x174 13. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_45_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_45" "0,1" newline bitfld.long 0x174 12. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_44_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_44" "0,1" newline bitfld.long 0x174 11. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_43_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_43" "0,1" newline bitfld.long 0x174 10. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_42_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_42" "0,1" newline bitfld.long 0x174 9. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_41_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_41" "0,1" newline bitfld.long 0x174 8. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_40_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_40" "0,1" newline bitfld.long 0x174 7. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_39_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_39" "0,1" newline bitfld.long 0x174 6. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_38_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_38" "0,1" newline bitfld.long 0x174 5. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_37_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_37" "0,1" newline bitfld.long 0x174 4. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_36_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_36" "0,1" newline bitfld.long 0x174 3. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_35_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_35" "0,1" newline bitfld.long 0x174 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_34_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_34" "0,1" newline bitfld.long 0x174 1. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_33_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_33" "0,1" newline bitfld.long 0x174 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_COMPLETE_32_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_complete_32" "0,1" line.long 0x178 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_6,Enable Clear Register 94" bitfld.long 0x178 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC1_RSVD_UNUSED_CLR,Enable Clear for pulse_vpac_out_5_en_utc1_rsvd_unused" "0,1" line.long 0x17C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_vpac_out_5_7,Enable Clear Register 95" bitfld.long 0x17C 4. "ENABLE_PULSE_VPAC_OUT_5_EN_CTM_PULSE_CLR,Enable Clear for pulse_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0x17C 2. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_PROT_ERR_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0x17C 0. "ENABLE_PULSE_VPAC_OUT_5_EN_UTC0_ERROR_CLR,Enable Clear for pulse_vpac_out_5_en_utc0_error" "0,1" group.long 0x500++0x17F line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_0,Status Register 0" bitfld.long 0x0 27. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_DPC_STATS_READ_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x0 26. "STATUS_LEVEL_VPAC_OUT_0_VISS0_CR_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x0 25. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x0 24. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x0 23. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x0 22. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x0 21. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x0 20. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x0 19. "STATUS_LEVEL_VPAC_OUT_0_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x0 18. "STATUS_LEVEL_VPAC_OUT_0_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x0 17. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x0 16. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x0 15. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x0 14. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x0 13. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x0 12. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x0 11. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x0 10. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x0 9. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x0 8. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x0 7. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x0 6. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x0 5. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x0 4. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x0 3. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x0 2. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x0 1. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x0 0. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_1,Status Register 1" bitfld.long 0x4 8. "STATUS_LEVEL_VPAC_OUT_0_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x4 7. "STATUS_LEVEL_VPAC_OUT_0_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x4 6. "STATUS_LEVEL_VPAC_OUT_0_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x4 5. "STATUS_LEVEL_VPAC_OUT_0_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x4 4. "STATUS_LEVEL_VPAC_OUT_0_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x4 3. "STATUS_LEVEL_VPAC_OUT_0_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x4 2. "STATUS_LEVEL_VPAC_OUT_0_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x4 1. "STATUS_LEVEL_VPAC_OUT_0_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x4 0. "STATUS_LEVEL_VPAC_OUT_0_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_2,Status Register 2" bitfld.long 0x8 3. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x8 2. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x8 1. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x8 0. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_3,Status Register 3" bitfld.long 0xC 26. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xC 25. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xC 24. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xC 22. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xC 20. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0xC 19. "STATUS_LEVEL_VPAC_OUT_0_SPARE_PEND_1_LEVEL,Status for level_vpac_out_0_en_spare_pend_1_level" "0,1" newline rbitfld.long 0xC 18. "STATUS_LEVEL_VPAC_OUT_0_SPARE_PEND_1_PULSE,Status for level_vpac_out_0_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0xC 17. "STATUS_LEVEL_VPAC_OUT_0_SPARE_PEND_0_LEVEL,Status for level_vpac_out_0_en_spare_pend_0_level" "0,1" newline rbitfld.long 0xC 16. "STATUS_LEVEL_VPAC_OUT_0_SPARE_PEND_0_PULSE,Status for level_vpac_out_0_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xC 15. "STATUS_LEVEL_VPAC_OUT_0_SPARE_DEC_1,Status write 1 to set for level_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xC 14. "STATUS_LEVEL_VPAC_OUT_0_SPARE_DEC_0,Status write 1 to set for level_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xC 13. "STATUS_LEVEL_VPAC_OUT_0_TDONE_6,Status write 1 to set for level_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xC 12. "STATUS_LEVEL_VPAC_OUT_0_TDONE_5,Status write 1 to set for level_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xC 11. "STATUS_LEVEL_VPAC_OUT_0_TDONE_4,Status write 1 to set for level_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xC 9. "STATUS_LEVEL_VPAC_OUT_0_TDONE_2,Status write 1 to set for level_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xC 7. "STATUS_LEVEL_VPAC_OUT_0_TDONE_0,Status write 1 to set for level_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xC 6. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_6,Status write 1 to set for level_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xC 5. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_5,Status write 1 to set for level_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xC 4. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_4,Status write 1 to set for level_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xC 3. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_3,Status write 1 to set for level_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xC 2. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_2,Status write 1 to set for level_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xC 1. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_1,Status write 1 to set for level_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xC 0. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_0,Status write 1 to set for level_vpac_out_0_en_pipe_done_0" "0,1" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_4,Status Register 4" bitfld.long 0x10 31. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0x10 30. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0x10 29. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0x10 28. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0x10 27. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0x10 26. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0x10 25. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0x10 24. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0x10 23. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0x10 22. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0x10 21. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0x10 20. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0x10 19. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0x10 18. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0x10 17. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0x10 16. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0x10 15. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0x10 14. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0x10 13. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0x10 12. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0x10 11. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0x10 10. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0x10 9. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0x10 8. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0x10 7. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0x10 6. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0x10 5. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0x10 4. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0x10 3. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0x10 2. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0x10 1. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0x10 0. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_5,Status Register 5" bitfld.long 0x14 31. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_63,Status write 1 to set for level_vpac_out_0_en_utc0_complete_63" "0,1" newline bitfld.long 0x14 30. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_62,Status write 1 to set for level_vpac_out_0_en_utc0_complete_62" "0,1" newline bitfld.long 0x14 29. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_61,Status write 1 to set for level_vpac_out_0_en_utc0_complete_61" "0,1" newline bitfld.long 0x14 28. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_60,Status write 1 to set for level_vpac_out_0_en_utc0_complete_60" "0,1" newline bitfld.long 0x14 27. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_59,Status write 1 to set for level_vpac_out_0_en_utc0_complete_59" "0,1" newline bitfld.long 0x14 26. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_58,Status write 1 to set for level_vpac_out_0_en_utc0_complete_58" "0,1" newline bitfld.long 0x14 25. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_57,Status write 1 to set for level_vpac_out_0_en_utc0_complete_57" "0,1" newline bitfld.long 0x14 24. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_56,Status write 1 to set for level_vpac_out_0_en_utc0_complete_56" "0,1" newline bitfld.long 0x14 23. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_55,Status write 1 to set for level_vpac_out_0_en_utc0_complete_55" "0,1" newline bitfld.long 0x14 22. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_54,Status write 1 to set for level_vpac_out_0_en_utc0_complete_54" "0,1" newline bitfld.long 0x14 21. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_53,Status write 1 to set for level_vpac_out_0_en_utc0_complete_53" "0,1" newline bitfld.long 0x14 20. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_52,Status write 1 to set for level_vpac_out_0_en_utc0_complete_52" "0,1" newline bitfld.long 0x14 19. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_51,Status write 1 to set for level_vpac_out_0_en_utc0_complete_51" "0,1" newline bitfld.long 0x14 18. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_50,Status write 1 to set for level_vpac_out_0_en_utc0_complete_50" "0,1" newline bitfld.long 0x14 17. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_49,Status write 1 to set for level_vpac_out_0_en_utc0_complete_49" "0,1" newline bitfld.long 0x14 16. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_48,Status write 1 to set for level_vpac_out_0_en_utc0_complete_48" "0,1" newline bitfld.long 0x14 15. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_47,Status write 1 to set for level_vpac_out_0_en_utc0_complete_47" "0,1" newline bitfld.long 0x14 14. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_46,Status write 1 to set for level_vpac_out_0_en_utc0_complete_46" "0,1" newline bitfld.long 0x14 13. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_45,Status write 1 to set for level_vpac_out_0_en_utc0_complete_45" "0,1" newline bitfld.long 0x14 12. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_44,Status write 1 to set for level_vpac_out_0_en_utc0_complete_44" "0,1" newline bitfld.long 0x14 11. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_43,Status write 1 to set for level_vpac_out_0_en_utc0_complete_43" "0,1" newline bitfld.long 0x14 10. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_42,Status write 1 to set for level_vpac_out_0_en_utc0_complete_42" "0,1" newline bitfld.long 0x14 9. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_41,Status write 1 to set for level_vpac_out_0_en_utc0_complete_41" "0,1" newline bitfld.long 0x14 8. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_40,Status write 1 to set for level_vpac_out_0_en_utc0_complete_40" "0,1" newline bitfld.long 0x14 7. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_39,Status write 1 to set for level_vpac_out_0_en_utc0_complete_39" "0,1" newline bitfld.long 0x14 6. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_38,Status write 1 to set for level_vpac_out_0_en_utc0_complete_38" "0,1" newline bitfld.long 0x14 5. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_37,Status write 1 to set for level_vpac_out_0_en_utc0_complete_37" "0,1" newline bitfld.long 0x14 4. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_36,Status write 1 to set for level_vpac_out_0_en_utc0_complete_36" "0,1" newline bitfld.long 0x14 3. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_35,Status write 1 to set for level_vpac_out_0_en_utc0_complete_35" "0,1" newline bitfld.long 0x14 2. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_34,Status write 1 to set for level_vpac_out_0_en_utc0_complete_34" "0,1" newline bitfld.long 0x14 1. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_33,Status write 1 to set for level_vpac_out_0_en_utc0_complete_33" "0,1" newline bitfld.long 0x14 0. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_32,Status write 1 to set for level_vpac_out_0_en_utc0_complete_32" "0,1" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_6,Status Register 6" bitfld.long 0x18 0. "STATUS_LEVEL_VPAC_OUT_0_UTC1_RSVD_UNUSED,Status write 1 to set for level_vpac_out_0_en_utc1_rsvd_unused" "0,1" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_0_7,Status Register 7" bitfld.long 0x1C 4. "STATUS_LEVEL_VPAC_OUT_0_CTM_PULSE,Status write 1 to set for level_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x1C 2. "STATUS_LEVEL_VPAC_OUT_0_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0x1C 0. "STATUS_LEVEL_VPAC_OUT_0_UTC0_ERROR,Status write 1 to set for level_vpac_out_0_en_utc0_error" "0,1" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_0,Status Register 8" bitfld.long 0x20 27. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_DPC_STATS_READ_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x20 26. "STATUS_LEVEL_VPAC_OUT_1_VISS0_CR_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x20 25. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x20 24. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x20 23. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x20 22. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x20 21. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x20 20. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x20 19. "STATUS_LEVEL_VPAC_OUT_1_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x20 18. "STATUS_LEVEL_VPAC_OUT_1_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x20 17. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x20 16. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x20 15. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x20 14. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x20 13. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x20 12. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x20 11. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x20 10. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x20 9. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x20 8. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x20 7. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x20 6. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x20 5. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x20 4. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x20 3. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x20 2. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x20 1. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x20 0. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_1,Status Register 9" bitfld.long 0x24 8. "STATUS_LEVEL_VPAC_OUT_1_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x24 7. "STATUS_LEVEL_VPAC_OUT_1_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x24 6. "STATUS_LEVEL_VPAC_OUT_1_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x24 5. "STATUS_LEVEL_VPAC_OUT_1_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x24 4. "STATUS_LEVEL_VPAC_OUT_1_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x24 3. "STATUS_LEVEL_VPAC_OUT_1_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x24 2. "STATUS_LEVEL_VPAC_OUT_1_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x24 1. "STATUS_LEVEL_VPAC_OUT_1_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x24 0. "STATUS_LEVEL_VPAC_OUT_1_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_2,Status Register 10" bitfld.long 0x28 3. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x28 2. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x28 1. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x28 0. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_3,Status Register 11" bitfld.long 0x2C 26. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x2C 25. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x2C 24. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x2C 22. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x2C 20. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x2C 19. "STATUS_LEVEL_VPAC_OUT_1_SPARE_PEND_1_LEVEL,Status for level_vpac_out_1_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x2C 18. "STATUS_LEVEL_VPAC_OUT_1_SPARE_PEND_1_PULSE,Status for level_vpac_out_1_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x2C 17. "STATUS_LEVEL_VPAC_OUT_1_SPARE_PEND_0_LEVEL,Status for level_vpac_out_1_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x2C 16. "STATUS_LEVEL_VPAC_OUT_1_SPARE_PEND_0_PULSE,Status for level_vpac_out_1_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x2C 15. "STATUS_LEVEL_VPAC_OUT_1_SPARE_DEC_1,Status write 1 to set for level_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x2C 14. "STATUS_LEVEL_VPAC_OUT_1_SPARE_DEC_0,Status write 1 to set for level_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x2C 13. "STATUS_LEVEL_VPAC_OUT_1_TDONE_6,Status write 1 to set for level_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0x2C 12. "STATUS_LEVEL_VPAC_OUT_1_TDONE_5,Status write 1 to set for level_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0x2C 11. "STATUS_LEVEL_VPAC_OUT_1_TDONE_4,Status write 1 to set for level_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0x2C 9. "STATUS_LEVEL_VPAC_OUT_1_TDONE_2,Status write 1 to set for level_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0x2C 7. "STATUS_LEVEL_VPAC_OUT_1_TDONE_0,Status write 1 to set for level_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0x2C 6. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_6,Status write 1 to set for level_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0x2C 5. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_5,Status write 1 to set for level_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0x2C 4. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_4,Status write 1 to set for level_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0x2C 3. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_3,Status write 1 to set for level_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x2C 2. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_2,Status write 1 to set for level_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x2C 1. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_1,Status write 1 to set for level_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x2C 0. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_0,Status write 1 to set for level_vpac_out_1_en_pipe_done_0" "0,1" line.long 0x30 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_4,Status Register 12" bitfld.long 0x30 31. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0x30 30. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0x30 29. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0x30 28. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0x30 27. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0x30 26. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0x30 25. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0x30 24. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0x30 23. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0x30 22. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0x30 21. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0x30 20. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0x30 19. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0x30 18. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0x30 17. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0x30 16. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0x30 15. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0x30 14. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0x30 13. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0x30 12. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0x30 11. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0x30 10. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0x30 9. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0x30 8. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0x30 7. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0x30 6. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0x30 5. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0x30 4. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0x30 3. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0x30 2. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0x30 1. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0x30 0. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_5,Status Register 13" bitfld.long 0x34 31. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_63,Status write 1 to set for level_vpac_out_1_en_utc0_complete_63" "0,1" newline bitfld.long 0x34 30. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_62,Status write 1 to set for level_vpac_out_1_en_utc0_complete_62" "0,1" newline bitfld.long 0x34 29. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_61,Status write 1 to set for level_vpac_out_1_en_utc0_complete_61" "0,1" newline bitfld.long 0x34 28. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_60,Status write 1 to set for level_vpac_out_1_en_utc0_complete_60" "0,1" newline bitfld.long 0x34 27. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_59,Status write 1 to set for level_vpac_out_1_en_utc0_complete_59" "0,1" newline bitfld.long 0x34 26. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_58,Status write 1 to set for level_vpac_out_1_en_utc0_complete_58" "0,1" newline bitfld.long 0x34 25. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_57,Status write 1 to set for level_vpac_out_1_en_utc0_complete_57" "0,1" newline bitfld.long 0x34 24. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_56,Status write 1 to set for level_vpac_out_1_en_utc0_complete_56" "0,1" newline bitfld.long 0x34 23. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_55,Status write 1 to set for level_vpac_out_1_en_utc0_complete_55" "0,1" newline bitfld.long 0x34 22. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_54,Status write 1 to set for level_vpac_out_1_en_utc0_complete_54" "0,1" newline bitfld.long 0x34 21. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_53,Status write 1 to set for level_vpac_out_1_en_utc0_complete_53" "0,1" newline bitfld.long 0x34 20. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_52,Status write 1 to set for level_vpac_out_1_en_utc0_complete_52" "0,1" newline bitfld.long 0x34 19. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_51,Status write 1 to set for level_vpac_out_1_en_utc0_complete_51" "0,1" newline bitfld.long 0x34 18. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_50,Status write 1 to set for level_vpac_out_1_en_utc0_complete_50" "0,1" newline bitfld.long 0x34 17. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_49,Status write 1 to set for level_vpac_out_1_en_utc0_complete_49" "0,1" newline bitfld.long 0x34 16. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_48,Status write 1 to set for level_vpac_out_1_en_utc0_complete_48" "0,1" newline bitfld.long 0x34 15. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_47,Status write 1 to set for level_vpac_out_1_en_utc0_complete_47" "0,1" newline bitfld.long 0x34 14. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_46,Status write 1 to set for level_vpac_out_1_en_utc0_complete_46" "0,1" newline bitfld.long 0x34 13. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_45,Status write 1 to set for level_vpac_out_1_en_utc0_complete_45" "0,1" newline bitfld.long 0x34 12. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_44,Status write 1 to set for level_vpac_out_1_en_utc0_complete_44" "0,1" newline bitfld.long 0x34 11. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_43,Status write 1 to set for level_vpac_out_1_en_utc0_complete_43" "0,1" newline bitfld.long 0x34 10. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_42,Status write 1 to set for level_vpac_out_1_en_utc0_complete_42" "0,1" newline bitfld.long 0x34 9. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_41,Status write 1 to set for level_vpac_out_1_en_utc0_complete_41" "0,1" newline bitfld.long 0x34 8. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_40,Status write 1 to set for level_vpac_out_1_en_utc0_complete_40" "0,1" newline bitfld.long 0x34 7. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_39,Status write 1 to set for level_vpac_out_1_en_utc0_complete_39" "0,1" newline bitfld.long 0x34 6. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_38,Status write 1 to set for level_vpac_out_1_en_utc0_complete_38" "0,1" newline bitfld.long 0x34 5. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_37,Status write 1 to set for level_vpac_out_1_en_utc0_complete_37" "0,1" newline bitfld.long 0x34 4. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_36,Status write 1 to set for level_vpac_out_1_en_utc0_complete_36" "0,1" newline bitfld.long 0x34 3. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_35,Status write 1 to set for level_vpac_out_1_en_utc0_complete_35" "0,1" newline bitfld.long 0x34 2. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_34,Status write 1 to set for level_vpac_out_1_en_utc0_complete_34" "0,1" newline bitfld.long 0x34 1. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_33,Status write 1 to set for level_vpac_out_1_en_utc0_complete_33" "0,1" newline bitfld.long 0x34 0. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_32,Status write 1 to set for level_vpac_out_1_en_utc0_complete_32" "0,1" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_6,Status Register 14" bitfld.long 0x38 0. "STATUS_LEVEL_VPAC_OUT_1_UTC1_RSVD_UNUSED,Status write 1 to set for level_vpac_out_1_en_utc1_rsvd_unused" "0,1" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_1_7,Status Register 15" bitfld.long 0x3C 4. "STATUS_LEVEL_VPAC_OUT_1_CTM_PULSE,Status write 1 to set for level_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x3C 2. "STATUS_LEVEL_VPAC_OUT_1_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0x3C 0. "STATUS_LEVEL_VPAC_OUT_1_UTC0_ERROR,Status write 1 to set for level_vpac_out_1_en_utc0_error" "0,1" line.long 0x40 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_0,Status Register 16" bitfld.long 0x40 27. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_DPC_STATS_READ_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x40 26. "STATUS_LEVEL_VPAC_OUT_2_VISS0_CR_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x40 25. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x40 24. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x40 23. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x40 22. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x40 21. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x40 20. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x40 19. "STATUS_LEVEL_VPAC_OUT_2_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x40 18. "STATUS_LEVEL_VPAC_OUT_2_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x40 17. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x40 16. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x40 15. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x40 14. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x40 13. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x40 12. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x40 11. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x40 10. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x40 9. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x40 8. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x40 7. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x40 6. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x40 5. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x40 4. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x40 3. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x40 2. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x40 1. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x40 0. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x44 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_1,Status Register 17" bitfld.long 0x44 8. "STATUS_LEVEL_VPAC_OUT_2_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x44 7. "STATUS_LEVEL_VPAC_OUT_2_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x44 6. "STATUS_LEVEL_VPAC_OUT_2_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x44 5. "STATUS_LEVEL_VPAC_OUT_2_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x44 4. "STATUS_LEVEL_VPAC_OUT_2_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x44 3. "STATUS_LEVEL_VPAC_OUT_2_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x44 2. "STATUS_LEVEL_VPAC_OUT_2_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x44 1. "STATUS_LEVEL_VPAC_OUT_2_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x44 0. "STATUS_LEVEL_VPAC_OUT_2_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x48 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_2,Status Register 18" bitfld.long 0x48 3. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x48 2. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x48 1. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x48 0. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x4C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_3,Status Register 19" bitfld.long 0x4C 26. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x4C 25. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x4C 24. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x4C 22. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x4C 20. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x4C 19. "STATUS_LEVEL_VPAC_OUT_2_SPARE_PEND_1_LEVEL,Status for level_vpac_out_2_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x4C 18. "STATUS_LEVEL_VPAC_OUT_2_SPARE_PEND_1_PULSE,Status for level_vpac_out_2_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x4C 17. "STATUS_LEVEL_VPAC_OUT_2_SPARE_PEND_0_LEVEL,Status for level_vpac_out_2_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x4C 16. "STATUS_LEVEL_VPAC_OUT_2_SPARE_PEND_0_PULSE,Status for level_vpac_out_2_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x4C 15. "STATUS_LEVEL_VPAC_OUT_2_SPARE_DEC_1,Status write 1 to set for level_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x4C 14. "STATUS_LEVEL_VPAC_OUT_2_SPARE_DEC_0,Status write 1 to set for level_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x4C 13. "STATUS_LEVEL_VPAC_OUT_2_TDONE_6,Status write 1 to set for level_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x4C 12. "STATUS_LEVEL_VPAC_OUT_2_TDONE_5,Status write 1 to set for level_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x4C 11. "STATUS_LEVEL_VPAC_OUT_2_TDONE_4,Status write 1 to set for level_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x4C 9. "STATUS_LEVEL_VPAC_OUT_2_TDONE_2,Status write 1 to set for level_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x4C 7. "STATUS_LEVEL_VPAC_OUT_2_TDONE_0,Status write 1 to set for level_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x4C 6. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_6,Status write 1 to set for level_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x4C 5. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_5,Status write 1 to set for level_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x4C 4. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_4,Status write 1 to set for level_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x4C 3. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_3,Status write 1 to set for level_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x4C 2. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_2,Status write 1 to set for level_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x4C 1. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_1,Status write 1 to set for level_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x4C 0. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_0,Status write 1 to set for level_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x50 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_4,Status Register 20" bitfld.long 0x50 31. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x50 30. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x50 29. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x50 28. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x50 27. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x50 26. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x50 25. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x50 24. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x50 23. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x50 22. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x50 21. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x50 20. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x50 19. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x50 18. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x50 17. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x50 16. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x50 15. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x50 14. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x50 13. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x50 12. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x50 11. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x50 10. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x50 9. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x50 8. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x50 7. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x50 6. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x50 5. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x50 4. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x50 3. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x50 2. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x50 1. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x50 0. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x54 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_5,Status Register 21" bitfld.long 0x54 31. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_63,Status write 1 to set for level_vpac_out_2_en_utc0_complete_63" "0,1" newline bitfld.long 0x54 30. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_62,Status write 1 to set for level_vpac_out_2_en_utc0_complete_62" "0,1" newline bitfld.long 0x54 29. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_61,Status write 1 to set for level_vpac_out_2_en_utc0_complete_61" "0,1" newline bitfld.long 0x54 28. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_60,Status write 1 to set for level_vpac_out_2_en_utc0_complete_60" "0,1" newline bitfld.long 0x54 27. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_59,Status write 1 to set for level_vpac_out_2_en_utc0_complete_59" "0,1" newline bitfld.long 0x54 26. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_58,Status write 1 to set for level_vpac_out_2_en_utc0_complete_58" "0,1" newline bitfld.long 0x54 25. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_57,Status write 1 to set for level_vpac_out_2_en_utc0_complete_57" "0,1" newline bitfld.long 0x54 24. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_56,Status write 1 to set for level_vpac_out_2_en_utc0_complete_56" "0,1" newline bitfld.long 0x54 23. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_55,Status write 1 to set for level_vpac_out_2_en_utc0_complete_55" "0,1" newline bitfld.long 0x54 22. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_54,Status write 1 to set for level_vpac_out_2_en_utc0_complete_54" "0,1" newline bitfld.long 0x54 21. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_53,Status write 1 to set for level_vpac_out_2_en_utc0_complete_53" "0,1" newline bitfld.long 0x54 20. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_52,Status write 1 to set for level_vpac_out_2_en_utc0_complete_52" "0,1" newline bitfld.long 0x54 19. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_51,Status write 1 to set for level_vpac_out_2_en_utc0_complete_51" "0,1" newline bitfld.long 0x54 18. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_50,Status write 1 to set for level_vpac_out_2_en_utc0_complete_50" "0,1" newline bitfld.long 0x54 17. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_49,Status write 1 to set for level_vpac_out_2_en_utc0_complete_49" "0,1" newline bitfld.long 0x54 16. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_48,Status write 1 to set for level_vpac_out_2_en_utc0_complete_48" "0,1" newline bitfld.long 0x54 15. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_47,Status write 1 to set for level_vpac_out_2_en_utc0_complete_47" "0,1" newline bitfld.long 0x54 14. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_46,Status write 1 to set for level_vpac_out_2_en_utc0_complete_46" "0,1" newline bitfld.long 0x54 13. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_45,Status write 1 to set for level_vpac_out_2_en_utc0_complete_45" "0,1" newline bitfld.long 0x54 12. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_44,Status write 1 to set for level_vpac_out_2_en_utc0_complete_44" "0,1" newline bitfld.long 0x54 11. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_43,Status write 1 to set for level_vpac_out_2_en_utc0_complete_43" "0,1" newline bitfld.long 0x54 10. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_42,Status write 1 to set for level_vpac_out_2_en_utc0_complete_42" "0,1" newline bitfld.long 0x54 9. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_41,Status write 1 to set for level_vpac_out_2_en_utc0_complete_41" "0,1" newline bitfld.long 0x54 8. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_40,Status write 1 to set for level_vpac_out_2_en_utc0_complete_40" "0,1" newline bitfld.long 0x54 7. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_39,Status write 1 to set for level_vpac_out_2_en_utc0_complete_39" "0,1" newline bitfld.long 0x54 6. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_38,Status write 1 to set for level_vpac_out_2_en_utc0_complete_38" "0,1" newline bitfld.long 0x54 5. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_37,Status write 1 to set for level_vpac_out_2_en_utc0_complete_37" "0,1" newline bitfld.long 0x54 4. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_36,Status write 1 to set for level_vpac_out_2_en_utc0_complete_36" "0,1" newline bitfld.long 0x54 3. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_35,Status write 1 to set for level_vpac_out_2_en_utc0_complete_35" "0,1" newline bitfld.long 0x54 2. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_34,Status write 1 to set for level_vpac_out_2_en_utc0_complete_34" "0,1" newline bitfld.long 0x54 1. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_33,Status write 1 to set for level_vpac_out_2_en_utc0_complete_33" "0,1" newline bitfld.long 0x54 0. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_32,Status write 1 to set for level_vpac_out_2_en_utc0_complete_32" "0,1" line.long 0x58 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_6,Status Register 22" bitfld.long 0x58 0. "STATUS_LEVEL_VPAC_OUT_2_UTC1_RSVD_UNUSED,Status write 1 to set for level_vpac_out_2_en_utc1_rsvd_unused" "0,1" line.long 0x5C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_2_7,Status Register 23" bitfld.long 0x5C 4. "STATUS_LEVEL_VPAC_OUT_2_CTM_PULSE,Status write 1 to set for level_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x5C 2. "STATUS_LEVEL_VPAC_OUT_2_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x5C 0. "STATUS_LEVEL_VPAC_OUT_2_UTC0_ERROR,Status write 1 to set for level_vpac_out_2_en_utc0_error" "0,1" line.long 0x60 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_0,Status Register 24" bitfld.long 0x60 27. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_DPC_STATS_READ_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x60 26. "STATUS_LEVEL_VPAC_OUT_3_VISS0_CR_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x60 25. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x60 24. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x60 23. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x60 22. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x60 21. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x60 20. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x60 19. "STATUS_LEVEL_VPAC_OUT_3_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x60 18. "STATUS_LEVEL_VPAC_OUT_3_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x60 17. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x60 16. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x60 15. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x60 14. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x60 13. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x60 12. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x60 11. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x60 10. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x60 9. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x60 8. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x60 7. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x60 6. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x60 5. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x60 4. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x60 3. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x60 2. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x60 1. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x60 0. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x64 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_1,Status Register 25" bitfld.long 0x64 8. "STATUS_LEVEL_VPAC_OUT_3_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x64 7. "STATUS_LEVEL_VPAC_OUT_3_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x64 6. "STATUS_LEVEL_VPAC_OUT_3_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x64 5. "STATUS_LEVEL_VPAC_OUT_3_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x64 4. "STATUS_LEVEL_VPAC_OUT_3_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x64 3. "STATUS_LEVEL_VPAC_OUT_3_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x64 2. "STATUS_LEVEL_VPAC_OUT_3_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x64 1. "STATUS_LEVEL_VPAC_OUT_3_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x64 0. "STATUS_LEVEL_VPAC_OUT_3_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x68 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_2,Status Register 26" bitfld.long 0x68 3. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x68 2. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x68 1. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x68 0. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x6C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_3,Status Register 27" bitfld.long 0x6C 26. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x6C 25. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x6C 24. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x6C 22. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x6C 20. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x6C 19. "STATUS_LEVEL_VPAC_OUT_3_SPARE_PEND_1_LEVEL,Status for level_vpac_out_3_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x6C 18. "STATUS_LEVEL_VPAC_OUT_3_SPARE_PEND_1_PULSE,Status for level_vpac_out_3_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x6C 17. "STATUS_LEVEL_VPAC_OUT_3_SPARE_PEND_0_LEVEL,Status for level_vpac_out_3_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x6C 16. "STATUS_LEVEL_VPAC_OUT_3_SPARE_PEND_0_PULSE,Status for level_vpac_out_3_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x6C 15. "STATUS_LEVEL_VPAC_OUT_3_SPARE_DEC_1,Status write 1 to set for level_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x6C 14. "STATUS_LEVEL_VPAC_OUT_3_SPARE_DEC_0,Status write 1 to set for level_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x6C 13. "STATUS_LEVEL_VPAC_OUT_3_TDONE_6,Status write 1 to set for level_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x6C 12. "STATUS_LEVEL_VPAC_OUT_3_TDONE_5,Status write 1 to set for level_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x6C 11. "STATUS_LEVEL_VPAC_OUT_3_TDONE_4,Status write 1 to set for level_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x6C 9. "STATUS_LEVEL_VPAC_OUT_3_TDONE_2,Status write 1 to set for level_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x6C 7. "STATUS_LEVEL_VPAC_OUT_3_TDONE_0,Status write 1 to set for level_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x6C 6. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_6,Status write 1 to set for level_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x6C 5. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_5,Status write 1 to set for level_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x6C 4. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_4,Status write 1 to set for level_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x6C 3. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_3,Status write 1 to set for level_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x6C 2. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_2,Status write 1 to set for level_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x6C 1. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_1,Status write 1 to set for level_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x6C 0. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_0,Status write 1 to set for level_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x70 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_4,Status Register 28" bitfld.long 0x70 31. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x70 30. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x70 29. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x70 28. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x70 27. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x70 26. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x70 25. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x70 24. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x70 23. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x70 22. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x70 21. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x70 20. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x70 19. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x70 18. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x70 17. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x70 16. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x70 15. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x70 14. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x70 13. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x70 12. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x70 11. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x70 10. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x70 9. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x70 8. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x70 7. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x70 6. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x70 5. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x70 4. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x70 3. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x70 2. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x70 1. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x70 0. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x74 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_5,Status Register 29" bitfld.long 0x74 31. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_63,Status write 1 to set for level_vpac_out_3_en_utc0_complete_63" "0,1" newline bitfld.long 0x74 30. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_62,Status write 1 to set for level_vpac_out_3_en_utc0_complete_62" "0,1" newline bitfld.long 0x74 29. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_61,Status write 1 to set for level_vpac_out_3_en_utc0_complete_61" "0,1" newline bitfld.long 0x74 28. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_60,Status write 1 to set for level_vpac_out_3_en_utc0_complete_60" "0,1" newline bitfld.long 0x74 27. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_59,Status write 1 to set for level_vpac_out_3_en_utc0_complete_59" "0,1" newline bitfld.long 0x74 26. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_58,Status write 1 to set for level_vpac_out_3_en_utc0_complete_58" "0,1" newline bitfld.long 0x74 25. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_57,Status write 1 to set for level_vpac_out_3_en_utc0_complete_57" "0,1" newline bitfld.long 0x74 24. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_56,Status write 1 to set for level_vpac_out_3_en_utc0_complete_56" "0,1" newline bitfld.long 0x74 23. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_55,Status write 1 to set for level_vpac_out_3_en_utc0_complete_55" "0,1" newline bitfld.long 0x74 22. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_54,Status write 1 to set for level_vpac_out_3_en_utc0_complete_54" "0,1" newline bitfld.long 0x74 21. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_53,Status write 1 to set for level_vpac_out_3_en_utc0_complete_53" "0,1" newline bitfld.long 0x74 20. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_52,Status write 1 to set for level_vpac_out_3_en_utc0_complete_52" "0,1" newline bitfld.long 0x74 19. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_51,Status write 1 to set for level_vpac_out_3_en_utc0_complete_51" "0,1" newline bitfld.long 0x74 18. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_50,Status write 1 to set for level_vpac_out_3_en_utc0_complete_50" "0,1" newline bitfld.long 0x74 17. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_49,Status write 1 to set for level_vpac_out_3_en_utc0_complete_49" "0,1" newline bitfld.long 0x74 16. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_48,Status write 1 to set for level_vpac_out_3_en_utc0_complete_48" "0,1" newline bitfld.long 0x74 15. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_47,Status write 1 to set for level_vpac_out_3_en_utc0_complete_47" "0,1" newline bitfld.long 0x74 14. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_46,Status write 1 to set for level_vpac_out_3_en_utc0_complete_46" "0,1" newline bitfld.long 0x74 13. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_45,Status write 1 to set for level_vpac_out_3_en_utc0_complete_45" "0,1" newline bitfld.long 0x74 12. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_44,Status write 1 to set for level_vpac_out_3_en_utc0_complete_44" "0,1" newline bitfld.long 0x74 11. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_43,Status write 1 to set for level_vpac_out_3_en_utc0_complete_43" "0,1" newline bitfld.long 0x74 10. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_42,Status write 1 to set for level_vpac_out_3_en_utc0_complete_42" "0,1" newline bitfld.long 0x74 9. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_41,Status write 1 to set for level_vpac_out_3_en_utc0_complete_41" "0,1" newline bitfld.long 0x74 8. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_40,Status write 1 to set for level_vpac_out_3_en_utc0_complete_40" "0,1" newline bitfld.long 0x74 7. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_39,Status write 1 to set for level_vpac_out_3_en_utc0_complete_39" "0,1" newline bitfld.long 0x74 6. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_38,Status write 1 to set for level_vpac_out_3_en_utc0_complete_38" "0,1" newline bitfld.long 0x74 5. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_37,Status write 1 to set for level_vpac_out_3_en_utc0_complete_37" "0,1" newline bitfld.long 0x74 4. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_36,Status write 1 to set for level_vpac_out_3_en_utc0_complete_36" "0,1" newline bitfld.long 0x74 3. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_35,Status write 1 to set for level_vpac_out_3_en_utc0_complete_35" "0,1" newline bitfld.long 0x74 2. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_34,Status write 1 to set for level_vpac_out_3_en_utc0_complete_34" "0,1" newline bitfld.long 0x74 1. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_33,Status write 1 to set for level_vpac_out_3_en_utc0_complete_33" "0,1" newline bitfld.long 0x74 0. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_32,Status write 1 to set for level_vpac_out_3_en_utc0_complete_32" "0,1" line.long 0x78 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_6,Status Register 30" bitfld.long 0x78 0. "STATUS_LEVEL_VPAC_OUT_3_UTC1_RSVD_UNUSED,Status write 1 to set for level_vpac_out_3_en_utc1_rsvd_unused" "0,1" line.long 0x7C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_3_7,Status Register 31" bitfld.long 0x7C 4. "STATUS_LEVEL_VPAC_OUT_3_CTM_PULSE,Status write 1 to set for level_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x7C 2. "STATUS_LEVEL_VPAC_OUT_3_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x7C 0. "STATUS_LEVEL_VPAC_OUT_3_UTC0_ERROR,Status write 1 to set for level_vpac_out_3_en_utc0_error" "0,1" line.long 0x80 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_0,Status Register 32" bitfld.long 0x80 27. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_DPC_STATS_READ_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x80 26. "STATUS_LEVEL_VPAC_OUT_4_VISS0_CR_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x80 25. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x80 24. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x80 23. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x80 22. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x80 21. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x80 20. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x80 19. "STATUS_LEVEL_VPAC_OUT_4_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x80 18. "STATUS_LEVEL_VPAC_OUT_4_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x80 17. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x80 16. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x80 15. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x80 14. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x80 13. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x80 12. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x80 11. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x80 10. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x80 9. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x80 8. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x80 7. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x80 6. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x80 5. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x80 4. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x80 3. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x80 2. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x80 1. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x80 0. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x84 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_1,Status Register 33" bitfld.long 0x84 8. "STATUS_LEVEL_VPAC_OUT_4_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x84 7. "STATUS_LEVEL_VPAC_OUT_4_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x84 6. "STATUS_LEVEL_VPAC_OUT_4_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x84 5. "STATUS_LEVEL_VPAC_OUT_4_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x84 4. "STATUS_LEVEL_VPAC_OUT_4_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x84 3. "STATUS_LEVEL_VPAC_OUT_4_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x84 2. "STATUS_LEVEL_VPAC_OUT_4_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x84 1. "STATUS_LEVEL_VPAC_OUT_4_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x84 0. "STATUS_LEVEL_VPAC_OUT_4_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x88 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_2,Status Register 34" bitfld.long 0x88 3. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x88 2. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x88 1. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x88 0. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x8C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_3,Status Register 35" bitfld.long 0x8C 26. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x8C 25. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x8C 24. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x8C 22. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x8C 20. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x8C 19. "STATUS_LEVEL_VPAC_OUT_4_SPARE_PEND_1_LEVEL,Status for level_vpac_out_4_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x8C 18. "STATUS_LEVEL_VPAC_OUT_4_SPARE_PEND_1_PULSE,Status for level_vpac_out_4_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x8C 17. "STATUS_LEVEL_VPAC_OUT_4_SPARE_PEND_0_LEVEL,Status for level_vpac_out_4_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x8C 16. "STATUS_LEVEL_VPAC_OUT_4_SPARE_PEND_0_PULSE,Status for level_vpac_out_4_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x8C 15. "STATUS_LEVEL_VPAC_OUT_4_SPARE_DEC_1,Status write 1 to set for level_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x8C 14. "STATUS_LEVEL_VPAC_OUT_4_SPARE_DEC_0,Status write 1 to set for level_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x8C 13. "STATUS_LEVEL_VPAC_OUT_4_TDONE_6,Status write 1 to set for level_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x8C 12. "STATUS_LEVEL_VPAC_OUT_4_TDONE_5,Status write 1 to set for level_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x8C 11. "STATUS_LEVEL_VPAC_OUT_4_TDONE_4,Status write 1 to set for level_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x8C 9. "STATUS_LEVEL_VPAC_OUT_4_TDONE_2,Status write 1 to set for level_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x8C 7. "STATUS_LEVEL_VPAC_OUT_4_TDONE_0,Status write 1 to set for level_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x8C 6. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_6,Status write 1 to set for level_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x8C 5. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_5,Status write 1 to set for level_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x8C 4. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_4,Status write 1 to set for level_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x8C 3. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_3,Status write 1 to set for level_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x8C 2. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_2,Status write 1 to set for level_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x8C 1. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_1,Status write 1 to set for level_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x8C 0. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_0,Status write 1 to set for level_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x90 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_4,Status Register 36" bitfld.long 0x90 31. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x90 30. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x90 29. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x90 28. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x90 27. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x90 26. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x90 25. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x90 24. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x90 23. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x90 22. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x90 21. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x90 20. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x90 19. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x90 18. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x90 17. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x90 16. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x90 15. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x90 14. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x90 13. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x90 12. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x90 11. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x90 10. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x90 9. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x90 8. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x90 7. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x90 6. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x90 5. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x90 4. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x90 3. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x90 2. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x90 1. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x90 0. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x94 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_5,Status Register 37" bitfld.long 0x94 31. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_63,Status write 1 to set for level_vpac_out_4_en_utc0_complete_63" "0,1" newline bitfld.long 0x94 30. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_62,Status write 1 to set for level_vpac_out_4_en_utc0_complete_62" "0,1" newline bitfld.long 0x94 29. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_61,Status write 1 to set for level_vpac_out_4_en_utc0_complete_61" "0,1" newline bitfld.long 0x94 28. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_60,Status write 1 to set for level_vpac_out_4_en_utc0_complete_60" "0,1" newline bitfld.long 0x94 27. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_59,Status write 1 to set for level_vpac_out_4_en_utc0_complete_59" "0,1" newline bitfld.long 0x94 26. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_58,Status write 1 to set for level_vpac_out_4_en_utc0_complete_58" "0,1" newline bitfld.long 0x94 25. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_57,Status write 1 to set for level_vpac_out_4_en_utc0_complete_57" "0,1" newline bitfld.long 0x94 24. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_56,Status write 1 to set for level_vpac_out_4_en_utc0_complete_56" "0,1" newline bitfld.long 0x94 23. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_55,Status write 1 to set for level_vpac_out_4_en_utc0_complete_55" "0,1" newline bitfld.long 0x94 22. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_54,Status write 1 to set for level_vpac_out_4_en_utc0_complete_54" "0,1" newline bitfld.long 0x94 21. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_53,Status write 1 to set for level_vpac_out_4_en_utc0_complete_53" "0,1" newline bitfld.long 0x94 20. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_52,Status write 1 to set for level_vpac_out_4_en_utc0_complete_52" "0,1" newline bitfld.long 0x94 19. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_51,Status write 1 to set for level_vpac_out_4_en_utc0_complete_51" "0,1" newline bitfld.long 0x94 18. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_50,Status write 1 to set for level_vpac_out_4_en_utc0_complete_50" "0,1" newline bitfld.long 0x94 17. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_49,Status write 1 to set for level_vpac_out_4_en_utc0_complete_49" "0,1" newline bitfld.long 0x94 16. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_48,Status write 1 to set for level_vpac_out_4_en_utc0_complete_48" "0,1" newline bitfld.long 0x94 15. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_47,Status write 1 to set for level_vpac_out_4_en_utc0_complete_47" "0,1" newline bitfld.long 0x94 14. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_46,Status write 1 to set for level_vpac_out_4_en_utc0_complete_46" "0,1" newline bitfld.long 0x94 13. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_45,Status write 1 to set for level_vpac_out_4_en_utc0_complete_45" "0,1" newline bitfld.long 0x94 12. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_44,Status write 1 to set for level_vpac_out_4_en_utc0_complete_44" "0,1" newline bitfld.long 0x94 11. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_43,Status write 1 to set for level_vpac_out_4_en_utc0_complete_43" "0,1" newline bitfld.long 0x94 10. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_42,Status write 1 to set for level_vpac_out_4_en_utc0_complete_42" "0,1" newline bitfld.long 0x94 9. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_41,Status write 1 to set for level_vpac_out_4_en_utc0_complete_41" "0,1" newline bitfld.long 0x94 8. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_40,Status write 1 to set for level_vpac_out_4_en_utc0_complete_40" "0,1" newline bitfld.long 0x94 7. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_39,Status write 1 to set for level_vpac_out_4_en_utc0_complete_39" "0,1" newline bitfld.long 0x94 6. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_38,Status write 1 to set for level_vpac_out_4_en_utc0_complete_38" "0,1" newline bitfld.long 0x94 5. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_37,Status write 1 to set for level_vpac_out_4_en_utc0_complete_37" "0,1" newline bitfld.long 0x94 4. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_36,Status write 1 to set for level_vpac_out_4_en_utc0_complete_36" "0,1" newline bitfld.long 0x94 3. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_35,Status write 1 to set for level_vpac_out_4_en_utc0_complete_35" "0,1" newline bitfld.long 0x94 2. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_34,Status write 1 to set for level_vpac_out_4_en_utc0_complete_34" "0,1" newline bitfld.long 0x94 1. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_33,Status write 1 to set for level_vpac_out_4_en_utc0_complete_33" "0,1" newline bitfld.long 0x94 0. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_32,Status write 1 to set for level_vpac_out_4_en_utc0_complete_32" "0,1" line.long 0x98 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_6,Status Register 38" bitfld.long 0x98 0. "STATUS_LEVEL_VPAC_OUT_4_UTC1_RSVD_UNUSED,Status write 1 to set for level_vpac_out_4_en_utc1_rsvd_unused" "0,1" line.long 0x9C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_4_7,Status Register 39" bitfld.long 0x9C 4. "STATUS_LEVEL_VPAC_OUT_4_CTM_PULSE,Status write 1 to set for level_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x9C 2. "STATUS_LEVEL_VPAC_OUT_4_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x9C 0. "STATUS_LEVEL_VPAC_OUT_4_UTC0_ERROR,Status write 1 to set for level_vpac_out_4_en_utc0_error" "0,1" line.long 0xA0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_0,Status Register 40" bitfld.long 0xA0 27. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_DPC_STATS_READ_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0xA0 26. "STATUS_LEVEL_VPAC_OUT_5_VISS0_CR_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xA0 25. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xA0 24. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for level_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xA0 23. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xA0 22. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA0 21. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA0 20. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for level_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xA0 19. "STATUS_LEVEL_VPAC_OUT_5_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xA0 18. "STATUS_LEVEL_VPAC_OUT_5_VISS0_EE_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xA0 17. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xA0 16. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xA0 15. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xA0 14. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCFA_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xA0 13. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_VP_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xA0 12. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xA0 11. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xA0 10. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_FILT_DONE,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xA0 9. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_FILT_START,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xA0 8. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xA0 7. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xA0 6. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xA0 5. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xA0 4. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xA0 3. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xA0 2. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_AF_PULSE,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xA0 1. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xA0 0. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_CFG_ERR,Status write 1 to set for level_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0xA4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_1,Status Register 41" bitfld.long 0xA4 8. "STATUS_LEVEL_VPAC_OUT_5_LDC0_VBUSM_RD_ERR,Status write 1 to set for level_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xA4 7. "STATUS_LEVEL_VPAC_OUT_5_LDC0_SL2_WR_ERR,Status write 1 to set for level_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xA4 6. "STATUS_LEVEL_VPAC_OUT_5_LDC0_FR_DONE_EVT,Status write 1 to set for level_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xA4 5. "STATUS_LEVEL_VPAC_OUT_5_LDC0_INT_SZOVF,Status write 1 to set for level_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xA4 4. "STATUS_LEVEL_VPAC_OUT_5_LDC0_IFR_OUTOFBOUND,Status write 1 to set for level_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xA4 3. "STATUS_LEVEL_VPAC_OUT_5_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xA4 2. "STATUS_LEVEL_VPAC_OUT_5_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for level_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xA4 1. "STATUS_LEVEL_VPAC_OUT_5_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xA4 0. "STATUS_LEVEL_VPAC_OUT_5_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for level_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xA8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_2,Status Register 42" bitfld.long 0xA8 3. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_SL2_WR_ERR,Status write 1 to set for level_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA8 2. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_SL2_RD_ERR,Status write 1 to set for level_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA8 1. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for level_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xA8 0. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for level_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xAC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_3,Status Register 43" bitfld.long 0xAC 26. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_6,Status write 1 to set for level_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xAC 25. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_5,Status write 1 to set for level_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xAC 24. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_4,Status write 1 to set for level_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xAC 22. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_2,Status write 1 to set for level_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xAC 20. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_0,Status write 1 to set for level_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0xAC 19. "STATUS_LEVEL_VPAC_OUT_5_SPARE_PEND_1_LEVEL,Status for level_vpac_out_5_en_spare_pend_1_level" "0,1" newline rbitfld.long 0xAC 18. "STATUS_LEVEL_VPAC_OUT_5_SPARE_PEND_1_PULSE,Status for level_vpac_out_5_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0xAC 17. "STATUS_LEVEL_VPAC_OUT_5_SPARE_PEND_0_LEVEL,Status for level_vpac_out_5_en_spare_pend_0_level" "0,1" newline rbitfld.long 0xAC 16. "STATUS_LEVEL_VPAC_OUT_5_SPARE_PEND_0_PULSE,Status for level_vpac_out_5_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xAC 15. "STATUS_LEVEL_VPAC_OUT_5_SPARE_DEC_1,Status write 1 to set for level_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0xAC 14. "STATUS_LEVEL_VPAC_OUT_5_SPARE_DEC_0,Status write 1 to set for level_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0xAC 13. "STATUS_LEVEL_VPAC_OUT_5_TDONE_6,Status write 1 to set for level_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0xAC 12. "STATUS_LEVEL_VPAC_OUT_5_TDONE_5,Status write 1 to set for level_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0xAC 11. "STATUS_LEVEL_VPAC_OUT_5_TDONE_4,Status write 1 to set for level_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0xAC 9. "STATUS_LEVEL_VPAC_OUT_5_TDONE_2,Status write 1 to set for level_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0xAC 7. "STATUS_LEVEL_VPAC_OUT_5_TDONE_0,Status write 1 to set for level_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0xAC 6. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_6,Status write 1 to set for level_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0xAC 5. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_5,Status write 1 to set for level_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0xAC 4. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_4,Status write 1 to set for level_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0xAC 3. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_3,Status write 1 to set for level_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0xAC 2. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_2,Status write 1 to set for level_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0xAC 1. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_1,Status write 1 to set for level_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0xAC 0. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_0,Status write 1 to set for level_vpac_out_5_en_pipe_done_0" "0,1" line.long 0xB0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_4,Status Register 44" bitfld.long 0xB0 31. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_31,Status write 1 to set for level_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0xB0 30. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_30,Status write 1 to set for level_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0xB0 29. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_29,Status write 1 to set for level_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0xB0 28. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_28,Status write 1 to set for level_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0xB0 27. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_27,Status write 1 to set for level_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0xB0 26. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_26,Status write 1 to set for level_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0xB0 25. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_25,Status write 1 to set for level_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0xB0 24. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_24,Status write 1 to set for level_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0xB0 23. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_23,Status write 1 to set for level_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0xB0 22. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_22,Status write 1 to set for level_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0xB0 21. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_21,Status write 1 to set for level_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0xB0 20. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_20,Status write 1 to set for level_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0xB0 19. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_19,Status write 1 to set for level_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0xB0 18. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_18,Status write 1 to set for level_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0xB0 17. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_17,Status write 1 to set for level_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0xB0 16. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_16,Status write 1 to set for level_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0xB0 15. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_15,Status write 1 to set for level_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0xB0 14. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_14,Status write 1 to set for level_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0xB0 13. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_13,Status write 1 to set for level_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0xB0 12. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_12,Status write 1 to set for level_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0xB0 11. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_11,Status write 1 to set for level_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0xB0 10. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_10,Status write 1 to set for level_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0xB0 9. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_9,Status write 1 to set for level_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0xB0 8. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_8,Status write 1 to set for level_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0xB0 7. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_7,Status write 1 to set for level_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0xB0 6. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_6,Status write 1 to set for level_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0xB0 5. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_5,Status write 1 to set for level_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0xB0 4. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_4,Status write 1 to set for level_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0xB0 3. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_3,Status write 1 to set for level_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0xB0 2. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_2,Status write 1 to set for level_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0xB0 1. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_1,Status write 1 to set for level_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0xB0 0. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_0,Status write 1 to set for level_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0xB4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_5,Status Register 45" bitfld.long 0xB4 31. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_63,Status write 1 to set for level_vpac_out_5_en_utc0_complete_63" "0,1" newline bitfld.long 0xB4 30. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_62,Status write 1 to set for level_vpac_out_5_en_utc0_complete_62" "0,1" newline bitfld.long 0xB4 29. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_61,Status write 1 to set for level_vpac_out_5_en_utc0_complete_61" "0,1" newline bitfld.long 0xB4 28. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_60,Status write 1 to set for level_vpac_out_5_en_utc0_complete_60" "0,1" newline bitfld.long 0xB4 27. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_59,Status write 1 to set for level_vpac_out_5_en_utc0_complete_59" "0,1" newline bitfld.long 0xB4 26. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_58,Status write 1 to set for level_vpac_out_5_en_utc0_complete_58" "0,1" newline bitfld.long 0xB4 25. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_57,Status write 1 to set for level_vpac_out_5_en_utc0_complete_57" "0,1" newline bitfld.long 0xB4 24. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_56,Status write 1 to set for level_vpac_out_5_en_utc0_complete_56" "0,1" newline bitfld.long 0xB4 23. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_55,Status write 1 to set for level_vpac_out_5_en_utc0_complete_55" "0,1" newline bitfld.long 0xB4 22. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_54,Status write 1 to set for level_vpac_out_5_en_utc0_complete_54" "0,1" newline bitfld.long 0xB4 21. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_53,Status write 1 to set for level_vpac_out_5_en_utc0_complete_53" "0,1" newline bitfld.long 0xB4 20. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_52,Status write 1 to set for level_vpac_out_5_en_utc0_complete_52" "0,1" newline bitfld.long 0xB4 19. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_51,Status write 1 to set for level_vpac_out_5_en_utc0_complete_51" "0,1" newline bitfld.long 0xB4 18. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_50,Status write 1 to set for level_vpac_out_5_en_utc0_complete_50" "0,1" newline bitfld.long 0xB4 17. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_49,Status write 1 to set for level_vpac_out_5_en_utc0_complete_49" "0,1" newline bitfld.long 0xB4 16. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_48,Status write 1 to set for level_vpac_out_5_en_utc0_complete_48" "0,1" newline bitfld.long 0xB4 15. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_47,Status write 1 to set for level_vpac_out_5_en_utc0_complete_47" "0,1" newline bitfld.long 0xB4 14. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_46,Status write 1 to set for level_vpac_out_5_en_utc0_complete_46" "0,1" newline bitfld.long 0xB4 13. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_45,Status write 1 to set for level_vpac_out_5_en_utc0_complete_45" "0,1" newline bitfld.long 0xB4 12. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_44,Status write 1 to set for level_vpac_out_5_en_utc0_complete_44" "0,1" newline bitfld.long 0xB4 11. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_43,Status write 1 to set for level_vpac_out_5_en_utc0_complete_43" "0,1" newline bitfld.long 0xB4 10. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_42,Status write 1 to set for level_vpac_out_5_en_utc0_complete_42" "0,1" newline bitfld.long 0xB4 9. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_41,Status write 1 to set for level_vpac_out_5_en_utc0_complete_41" "0,1" newline bitfld.long 0xB4 8. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_40,Status write 1 to set for level_vpac_out_5_en_utc0_complete_40" "0,1" newline bitfld.long 0xB4 7. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_39,Status write 1 to set for level_vpac_out_5_en_utc0_complete_39" "0,1" newline bitfld.long 0xB4 6. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_38,Status write 1 to set for level_vpac_out_5_en_utc0_complete_38" "0,1" newline bitfld.long 0xB4 5. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_37,Status write 1 to set for level_vpac_out_5_en_utc0_complete_37" "0,1" newline bitfld.long 0xB4 4. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_36,Status write 1 to set for level_vpac_out_5_en_utc0_complete_36" "0,1" newline bitfld.long 0xB4 3. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_35,Status write 1 to set for level_vpac_out_5_en_utc0_complete_35" "0,1" newline bitfld.long 0xB4 2. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_34,Status write 1 to set for level_vpac_out_5_en_utc0_complete_34" "0,1" newline bitfld.long 0xB4 1. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_33,Status write 1 to set for level_vpac_out_5_en_utc0_complete_33" "0,1" newline bitfld.long 0xB4 0. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_32,Status write 1 to set for level_vpac_out_5_en_utc0_complete_32" "0,1" line.long 0xB8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_6,Status Register 46" bitfld.long 0xB8 0. "STATUS_LEVEL_VPAC_OUT_5_UTC1_RSVD_UNUSED,Status write 1 to set for level_vpac_out_5_en_utc1_rsvd_unused" "0,1" line.long 0xBC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_vpac_out_5_7,Status Register 47" bitfld.long 0xBC 4. "STATUS_LEVEL_VPAC_OUT_5_CTM_PULSE,Status write 1 to set for level_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0xBC 2. "STATUS_LEVEL_VPAC_OUT_5_UTC0_PROT_ERR,Status write 1 to set for level_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0xBC 0. "STATUS_LEVEL_VPAC_OUT_5_UTC0_ERROR,Status write 1 to set for level_vpac_out_5_en_utc0_error" "0,1" line.long 0xC0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_0,Status Register 48" bitfld.long 0xC0 27. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_DPC_STATS_READ_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0xC0 26. "STATUS_PULSE_VPAC_OUT_0_VISS0_CR_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xC0 25. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xC0 24. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xC0 23. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xC0 22. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC0 21. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC0 20. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xC0 19. "STATUS_PULSE_VPAC_OUT_0_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xC0 18. "STATUS_PULSE_VPAC_OUT_0_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xC0 17. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xC0 16. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xC0 15. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xC0 14. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xC0 13. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xC0 12. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xC0 11. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xC0 10. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xC0 9. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xC0 8. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xC0 7. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xC0 6. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xC0 5. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xC0 4. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xC0 3. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xC0 2. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xC0 1. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xC0 0. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0xC4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_1,Status Register 49" bitfld.long 0xC4 8. "STATUS_PULSE_VPAC_OUT_0_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xC4 7. "STATUS_PULSE_VPAC_OUT_0_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xC4 6. "STATUS_PULSE_VPAC_OUT_0_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xC4 5. "STATUS_PULSE_VPAC_OUT_0_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xC4 4. "STATUS_PULSE_VPAC_OUT_0_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xC4 3. "STATUS_PULSE_VPAC_OUT_0_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xC4 2. "STATUS_PULSE_VPAC_OUT_0_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xC4 1. "STATUS_PULSE_VPAC_OUT_0_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xC4 0. "STATUS_PULSE_VPAC_OUT_0_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xC8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_2,Status Register 50" bitfld.long 0xC8 3. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC8 2. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC8 1. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xC8 0. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xCC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_3,Status Register 51" bitfld.long 0xCC 26. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xCC 25. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xCC 24. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xCC 22. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xCC 20. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0xCC 19. "STATUS_PULSE_VPAC_OUT_0_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_0_en_spare_pend_1_level" "0,1" newline rbitfld.long 0xCC 18. "STATUS_PULSE_VPAC_OUT_0_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_0_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0xCC 17. "STATUS_PULSE_VPAC_OUT_0_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_0_en_spare_pend_0_level" "0,1" newline rbitfld.long 0xCC 16. "STATUS_PULSE_VPAC_OUT_0_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_0_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xCC 15. "STATUS_PULSE_VPAC_OUT_0_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xCC 14. "STATUS_PULSE_VPAC_OUT_0_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xCC 13. "STATUS_PULSE_VPAC_OUT_0_TDONE_6,Status write 1 to set for pulse_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xCC 12. "STATUS_PULSE_VPAC_OUT_0_TDONE_5,Status write 1 to set for pulse_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xCC 11. "STATUS_PULSE_VPAC_OUT_0_TDONE_4,Status write 1 to set for pulse_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xCC 9. "STATUS_PULSE_VPAC_OUT_0_TDONE_2,Status write 1 to set for pulse_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xCC 7. "STATUS_PULSE_VPAC_OUT_0_TDONE_0,Status write 1 to set for pulse_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xCC 6. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xCC 5. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xCC 4. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xCC 3. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xCC 2. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xCC 1. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xCC 0. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_0_en_pipe_done_0" "0,1" line.long 0xD0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_4,Status Register 52" bitfld.long 0xD0 31. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0xD0 30. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0xD0 29. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0xD0 28. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0xD0 27. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0xD0 26. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0xD0 25. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0xD0 24. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0xD0 23. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0xD0 22. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0xD0 21. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0xD0 20. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0xD0 19. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0xD0 18. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0xD0 17. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0xD0 16. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0xD0 15. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0xD0 14. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0xD0 13. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0xD0 12. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0xD0 11. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0xD0 10. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0xD0 9. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0xD0 8. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0xD0 7. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0xD0 6. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0xD0 5. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0xD0 4. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0xD0 3. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0xD0 2. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0xD0 1. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0xD0 0. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0xD4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_5,Status Register 53" bitfld.long 0xD4 31. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_63,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_63" "0,1" newline bitfld.long 0xD4 30. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_62,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_62" "0,1" newline bitfld.long 0xD4 29. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_61,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_61" "0,1" newline bitfld.long 0xD4 28. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_60,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_60" "0,1" newline bitfld.long 0xD4 27. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_59,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_59" "0,1" newline bitfld.long 0xD4 26. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_58,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_58" "0,1" newline bitfld.long 0xD4 25. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_57,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_57" "0,1" newline bitfld.long 0xD4 24. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_56,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_56" "0,1" newline bitfld.long 0xD4 23. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_55,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_55" "0,1" newline bitfld.long 0xD4 22. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_54,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_54" "0,1" newline bitfld.long 0xD4 21. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_53,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_53" "0,1" newline bitfld.long 0xD4 20. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_52,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_52" "0,1" newline bitfld.long 0xD4 19. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_51,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_51" "0,1" newline bitfld.long 0xD4 18. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_50,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_50" "0,1" newline bitfld.long 0xD4 17. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_49,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_49" "0,1" newline bitfld.long 0xD4 16. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_48,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_48" "0,1" newline bitfld.long 0xD4 15. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_47,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_47" "0,1" newline bitfld.long 0xD4 14. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_46,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_46" "0,1" newline bitfld.long 0xD4 13. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_45,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_45" "0,1" newline bitfld.long 0xD4 12. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_44,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_44" "0,1" newline bitfld.long 0xD4 11. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_43,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_43" "0,1" newline bitfld.long 0xD4 10. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_42,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_42" "0,1" newline bitfld.long 0xD4 9. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_41,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_41" "0,1" newline bitfld.long 0xD4 8. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_40,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_40" "0,1" newline bitfld.long 0xD4 7. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_39,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_39" "0,1" newline bitfld.long 0xD4 6. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_38,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_38" "0,1" newline bitfld.long 0xD4 5. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_37,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_37" "0,1" newline bitfld.long 0xD4 4. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_36,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_36" "0,1" newline bitfld.long 0xD4 3. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_35,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_35" "0,1" newline bitfld.long 0xD4 2. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_34,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_34" "0,1" newline bitfld.long 0xD4 1. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_33,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_33" "0,1" newline bitfld.long 0xD4 0. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_32,Status write 1 to set for pulse_vpac_out_0_en_utc0_complete_32" "0,1" line.long 0xD8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_6,Status Register 54" bitfld.long 0xD8 0. "STATUS_PULSE_VPAC_OUT_0_UTC1_RSVD_UNUSED,Status write 1 to set for pulse_vpac_out_0_en_utc1_rsvd_unused" "0,1" line.long 0xDC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_0_7,Status Register 55" bitfld.long 0xDC 4. "STATUS_PULSE_VPAC_OUT_0_CTM_PULSE,Status write 1 to set for pulse_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0xDC 2. "STATUS_PULSE_VPAC_OUT_0_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0xDC 0. "STATUS_PULSE_VPAC_OUT_0_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_0_en_utc0_error" "0,1" line.long 0xE0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_0,Status Register 56" bitfld.long 0xE0 27. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_DPC_STATS_READ_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0xE0 26. "STATUS_PULSE_VPAC_OUT_1_VISS0_CR_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xE0 25. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xE0 24. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xE0 23. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xE0 22. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE0 21. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE0 20. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xE0 19. "STATUS_PULSE_VPAC_OUT_1_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xE0 18. "STATUS_PULSE_VPAC_OUT_1_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xE0 17. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xE0 16. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xE0 15. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xE0 14. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xE0 13. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xE0 12. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xE0 11. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xE0 10. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xE0 9. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xE0 8. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xE0 7. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xE0 6. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xE0 5. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xE0 4. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xE0 3. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xE0 2. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xE0 1. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xE0 0. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0xE4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_1,Status Register 57" bitfld.long 0xE4 8. "STATUS_PULSE_VPAC_OUT_1_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xE4 7. "STATUS_PULSE_VPAC_OUT_1_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xE4 6. "STATUS_PULSE_VPAC_OUT_1_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xE4 5. "STATUS_PULSE_VPAC_OUT_1_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xE4 4. "STATUS_PULSE_VPAC_OUT_1_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xE4 3. "STATUS_PULSE_VPAC_OUT_1_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xE4 2. "STATUS_PULSE_VPAC_OUT_1_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xE4 1. "STATUS_PULSE_VPAC_OUT_1_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xE4 0. "STATUS_PULSE_VPAC_OUT_1_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xE8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_2,Status Register 58" bitfld.long 0xE8 3. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE8 2. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE8 1. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xE8 0. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xEC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_3,Status Register 59" bitfld.long 0xEC 26. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xEC 25. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xEC 24. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xEC 22. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xEC 20. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0xEC 19. "STATUS_PULSE_VPAC_OUT_1_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_1_en_spare_pend_1_level" "0,1" newline rbitfld.long 0xEC 18. "STATUS_PULSE_VPAC_OUT_1_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_1_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0xEC 17. "STATUS_PULSE_VPAC_OUT_1_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_1_en_spare_pend_0_level" "0,1" newline rbitfld.long 0xEC 16. "STATUS_PULSE_VPAC_OUT_1_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_1_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0xEC 15. "STATUS_PULSE_VPAC_OUT_1_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0xEC 14. "STATUS_PULSE_VPAC_OUT_1_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0xEC 13. "STATUS_PULSE_VPAC_OUT_1_TDONE_6,Status write 1 to set for pulse_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0xEC 12. "STATUS_PULSE_VPAC_OUT_1_TDONE_5,Status write 1 to set for pulse_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0xEC 11. "STATUS_PULSE_VPAC_OUT_1_TDONE_4,Status write 1 to set for pulse_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0xEC 9. "STATUS_PULSE_VPAC_OUT_1_TDONE_2,Status write 1 to set for pulse_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0xEC 7. "STATUS_PULSE_VPAC_OUT_1_TDONE_0,Status write 1 to set for pulse_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0xEC 6. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0xEC 5. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0xEC 4. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0xEC 3. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0xEC 2. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0xEC 1. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0xEC 0. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_1_en_pipe_done_0" "0,1" line.long 0xF0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_4,Status Register 60" bitfld.long 0xF0 31. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0xF0 30. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0xF0 29. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0xF0 28. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0xF0 27. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0xF0 26. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0xF0 25. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0xF0 24. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0xF0 23. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0xF0 22. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0xF0 21. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0xF0 20. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0xF0 19. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0xF0 18. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0xF0 17. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0xF0 16. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0xF0 15. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0xF0 14. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0xF0 13. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0xF0 12. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0xF0 11. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0xF0 10. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0xF0 9. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0xF0 8. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0xF0 7. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0xF0 6. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0xF0 5. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0xF0 4. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0xF0 3. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0xF0 2. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0xF0 1. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0xF0 0. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0xF4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_5,Status Register 61" bitfld.long 0xF4 31. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_63,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_63" "0,1" newline bitfld.long 0xF4 30. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_62,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_62" "0,1" newline bitfld.long 0xF4 29. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_61,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_61" "0,1" newline bitfld.long 0xF4 28. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_60,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_60" "0,1" newline bitfld.long 0xF4 27. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_59,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_59" "0,1" newline bitfld.long 0xF4 26. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_58,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_58" "0,1" newline bitfld.long 0xF4 25. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_57,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_57" "0,1" newline bitfld.long 0xF4 24. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_56,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_56" "0,1" newline bitfld.long 0xF4 23. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_55,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_55" "0,1" newline bitfld.long 0xF4 22. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_54,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_54" "0,1" newline bitfld.long 0xF4 21. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_53,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_53" "0,1" newline bitfld.long 0xF4 20. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_52,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_52" "0,1" newline bitfld.long 0xF4 19. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_51,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_51" "0,1" newline bitfld.long 0xF4 18. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_50,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_50" "0,1" newline bitfld.long 0xF4 17. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_49,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_49" "0,1" newline bitfld.long 0xF4 16. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_48,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_48" "0,1" newline bitfld.long 0xF4 15. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_47,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_47" "0,1" newline bitfld.long 0xF4 14. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_46,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_46" "0,1" newline bitfld.long 0xF4 13. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_45,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_45" "0,1" newline bitfld.long 0xF4 12. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_44,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_44" "0,1" newline bitfld.long 0xF4 11. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_43,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_43" "0,1" newline bitfld.long 0xF4 10. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_42,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_42" "0,1" newline bitfld.long 0xF4 9. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_41,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_41" "0,1" newline bitfld.long 0xF4 8. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_40,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_40" "0,1" newline bitfld.long 0xF4 7. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_39,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_39" "0,1" newline bitfld.long 0xF4 6. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_38,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_38" "0,1" newline bitfld.long 0xF4 5. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_37,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_37" "0,1" newline bitfld.long 0xF4 4. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_36,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_36" "0,1" newline bitfld.long 0xF4 3. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_35,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_35" "0,1" newline bitfld.long 0xF4 2. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_34,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_34" "0,1" newline bitfld.long 0xF4 1. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_33,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_33" "0,1" newline bitfld.long 0xF4 0. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_32,Status write 1 to set for pulse_vpac_out_1_en_utc0_complete_32" "0,1" line.long 0xF8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_6,Status Register 62" bitfld.long 0xF8 0. "STATUS_PULSE_VPAC_OUT_1_UTC1_RSVD_UNUSED,Status write 1 to set for pulse_vpac_out_1_en_utc1_rsvd_unused" "0,1" line.long 0xFC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_1_7,Status Register 63" bitfld.long 0xFC 4. "STATUS_PULSE_VPAC_OUT_1_CTM_PULSE,Status write 1 to set for pulse_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0xFC 2. "STATUS_PULSE_VPAC_OUT_1_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0xFC 0. "STATUS_PULSE_VPAC_OUT_1_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_1_en_utc0_error" "0,1" line.long 0x100 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_0,Status Register 64" bitfld.long 0x100 27. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_DPC_STATS_READ_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x100 26. "STATUS_PULSE_VPAC_OUT_2_VISS0_CR_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x100 25. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x100 24. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x100 23. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x100 22. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x100 21. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x100 20. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x100 19. "STATUS_PULSE_VPAC_OUT_2_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x100 18. "STATUS_PULSE_VPAC_OUT_2_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x100 17. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x100 16. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x100 15. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x100 14. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x100 13. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x100 12. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x100 11. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x100 10. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x100 9. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x100 8. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x100 7. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x100 6. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x100 5. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x100 4. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x100 3. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x100 2. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x100 1. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x100 0. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x104 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_1,Status Register 65" bitfld.long 0x104 8. "STATUS_PULSE_VPAC_OUT_2_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x104 7. "STATUS_PULSE_VPAC_OUT_2_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x104 6. "STATUS_PULSE_VPAC_OUT_2_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x104 5. "STATUS_PULSE_VPAC_OUT_2_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x104 4. "STATUS_PULSE_VPAC_OUT_2_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x104 3. "STATUS_PULSE_VPAC_OUT_2_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x104 2. "STATUS_PULSE_VPAC_OUT_2_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x104 1. "STATUS_PULSE_VPAC_OUT_2_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x104 0. "STATUS_PULSE_VPAC_OUT_2_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x108 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_2,Status Register 66" bitfld.long 0x108 3. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x108 2. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x108 1. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x108 0. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x10C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_3,Status Register 67" bitfld.long 0x10C 26. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x10C 25. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x10C 24. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x10C 22. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x10C 20. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x10C 19. "STATUS_PULSE_VPAC_OUT_2_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_2_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x10C 18. "STATUS_PULSE_VPAC_OUT_2_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_2_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x10C 17. "STATUS_PULSE_VPAC_OUT_2_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_2_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x10C 16. "STATUS_PULSE_VPAC_OUT_2_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_2_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x10C 15. "STATUS_PULSE_VPAC_OUT_2_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x10C 14. "STATUS_PULSE_VPAC_OUT_2_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x10C 13. "STATUS_PULSE_VPAC_OUT_2_TDONE_6,Status write 1 to set for pulse_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x10C 12. "STATUS_PULSE_VPAC_OUT_2_TDONE_5,Status write 1 to set for pulse_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x10C 11. "STATUS_PULSE_VPAC_OUT_2_TDONE_4,Status write 1 to set for pulse_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x10C 9. "STATUS_PULSE_VPAC_OUT_2_TDONE_2,Status write 1 to set for pulse_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x10C 7. "STATUS_PULSE_VPAC_OUT_2_TDONE_0,Status write 1 to set for pulse_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x10C 6. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x10C 5. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x10C 4. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x10C 3. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x10C 2. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x10C 1. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x10C 0. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x110 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_4,Status Register 68" bitfld.long 0x110 31. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x110 30. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x110 29. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x110 28. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x110 27. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x110 26. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x110 25. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x110 24. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x110 23. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x110 22. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x110 21. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x110 20. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x110 19. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x110 18. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x110 17. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x110 16. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x110 15. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x110 14. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x110 13. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x110 12. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x110 11. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x110 10. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x110 9. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x110 8. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x110 7. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x110 6. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x110 5. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x110 4. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x110 3. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x110 2. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x110 1. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x110 0. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x114 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_5,Status Register 69" bitfld.long 0x114 31. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_63,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_63" "0,1" newline bitfld.long 0x114 30. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_62,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_62" "0,1" newline bitfld.long 0x114 29. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_61,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_61" "0,1" newline bitfld.long 0x114 28. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_60,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_60" "0,1" newline bitfld.long 0x114 27. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_59,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_59" "0,1" newline bitfld.long 0x114 26. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_58,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_58" "0,1" newline bitfld.long 0x114 25. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_57,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_57" "0,1" newline bitfld.long 0x114 24. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_56,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_56" "0,1" newline bitfld.long 0x114 23. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_55,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_55" "0,1" newline bitfld.long 0x114 22. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_54,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_54" "0,1" newline bitfld.long 0x114 21. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_53,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_53" "0,1" newline bitfld.long 0x114 20. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_52,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_52" "0,1" newline bitfld.long 0x114 19. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_51,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_51" "0,1" newline bitfld.long 0x114 18. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_50,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_50" "0,1" newline bitfld.long 0x114 17. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_49,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_49" "0,1" newline bitfld.long 0x114 16. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_48,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_48" "0,1" newline bitfld.long 0x114 15. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_47,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_47" "0,1" newline bitfld.long 0x114 14. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_46,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_46" "0,1" newline bitfld.long 0x114 13. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_45,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_45" "0,1" newline bitfld.long 0x114 12. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_44,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_44" "0,1" newline bitfld.long 0x114 11. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_43,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_43" "0,1" newline bitfld.long 0x114 10. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_42,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_42" "0,1" newline bitfld.long 0x114 9. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_41,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_41" "0,1" newline bitfld.long 0x114 8. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_40,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_40" "0,1" newline bitfld.long 0x114 7. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_39,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_39" "0,1" newline bitfld.long 0x114 6. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_38,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_38" "0,1" newline bitfld.long 0x114 5. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_37,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_37" "0,1" newline bitfld.long 0x114 4. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_36,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_36" "0,1" newline bitfld.long 0x114 3. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_35,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_35" "0,1" newline bitfld.long 0x114 2. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_34,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_34" "0,1" newline bitfld.long 0x114 1. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_33,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_33" "0,1" newline bitfld.long 0x114 0. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_32,Status write 1 to set for pulse_vpac_out_2_en_utc0_complete_32" "0,1" line.long 0x118 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_6,Status Register 70" bitfld.long 0x118 0. "STATUS_PULSE_VPAC_OUT_2_UTC1_RSVD_UNUSED,Status write 1 to set for pulse_vpac_out_2_en_utc1_rsvd_unused" "0,1" line.long 0x11C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_2_7,Status Register 71" bitfld.long 0x11C 4. "STATUS_PULSE_VPAC_OUT_2_CTM_PULSE,Status write 1 to set for pulse_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x11C 2. "STATUS_PULSE_VPAC_OUT_2_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x11C 0. "STATUS_PULSE_VPAC_OUT_2_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_2_en_utc0_error" "0,1" line.long 0x120 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_0,Status Register 72" bitfld.long 0x120 27. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_DPC_STATS_READ_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x120 26. "STATUS_PULSE_VPAC_OUT_3_VISS0_CR_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x120 25. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x120 24. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x120 23. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x120 22. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x120 21. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x120 20. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x120 19. "STATUS_PULSE_VPAC_OUT_3_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x120 18. "STATUS_PULSE_VPAC_OUT_3_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x120 17. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x120 16. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x120 15. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x120 14. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x120 13. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x120 12. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x120 11. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x120 10. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x120 9. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x120 8. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x120 7. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x120 6. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x120 5. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x120 4. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x120 3. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x120 2. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x120 1. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x120 0. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x124 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_1,Status Register 73" bitfld.long 0x124 8. "STATUS_PULSE_VPAC_OUT_3_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x124 7. "STATUS_PULSE_VPAC_OUT_3_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x124 6. "STATUS_PULSE_VPAC_OUT_3_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x124 5. "STATUS_PULSE_VPAC_OUT_3_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x124 4. "STATUS_PULSE_VPAC_OUT_3_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x124 3. "STATUS_PULSE_VPAC_OUT_3_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x124 2. "STATUS_PULSE_VPAC_OUT_3_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x124 1. "STATUS_PULSE_VPAC_OUT_3_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x124 0. "STATUS_PULSE_VPAC_OUT_3_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x128 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_2,Status Register 74" bitfld.long 0x128 3. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x128 2. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x128 1. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x128 0. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x12C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_3,Status Register 75" bitfld.long 0x12C 26. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x12C 25. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x12C 24. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x12C 22. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x12C 20. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x12C 19. "STATUS_PULSE_VPAC_OUT_3_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_3_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x12C 18. "STATUS_PULSE_VPAC_OUT_3_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_3_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x12C 17. "STATUS_PULSE_VPAC_OUT_3_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_3_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x12C 16. "STATUS_PULSE_VPAC_OUT_3_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_3_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x12C 15. "STATUS_PULSE_VPAC_OUT_3_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x12C 14. "STATUS_PULSE_VPAC_OUT_3_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x12C 13. "STATUS_PULSE_VPAC_OUT_3_TDONE_6,Status write 1 to set for pulse_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x12C 12. "STATUS_PULSE_VPAC_OUT_3_TDONE_5,Status write 1 to set for pulse_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x12C 11. "STATUS_PULSE_VPAC_OUT_3_TDONE_4,Status write 1 to set for pulse_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x12C 9. "STATUS_PULSE_VPAC_OUT_3_TDONE_2,Status write 1 to set for pulse_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x12C 7. "STATUS_PULSE_VPAC_OUT_3_TDONE_0,Status write 1 to set for pulse_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x12C 6. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x12C 5. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x12C 4. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x12C 3. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x12C 2. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x12C 1. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x12C 0. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x130 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_4,Status Register 76" bitfld.long 0x130 31. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x130 30. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x130 29. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x130 28. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x130 27. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x130 26. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x130 25. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x130 24. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x130 23. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x130 22. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x130 21. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x130 20. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x130 19. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x130 18. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x130 17. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x130 16. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x130 15. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x130 14. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x130 13. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x130 12. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x130 11. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x130 10. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x130 9. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x130 8. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x130 7. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x130 6. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x130 5. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x130 4. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x130 3. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x130 2. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x130 1. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x130 0. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x134 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_5,Status Register 77" bitfld.long 0x134 31. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_63,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_63" "0,1" newline bitfld.long 0x134 30. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_62,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_62" "0,1" newline bitfld.long 0x134 29. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_61,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_61" "0,1" newline bitfld.long 0x134 28. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_60,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_60" "0,1" newline bitfld.long 0x134 27. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_59,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_59" "0,1" newline bitfld.long 0x134 26. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_58,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_58" "0,1" newline bitfld.long 0x134 25. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_57,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_57" "0,1" newline bitfld.long 0x134 24. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_56,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_56" "0,1" newline bitfld.long 0x134 23. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_55,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_55" "0,1" newline bitfld.long 0x134 22. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_54,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_54" "0,1" newline bitfld.long 0x134 21. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_53,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_53" "0,1" newline bitfld.long 0x134 20. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_52,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_52" "0,1" newline bitfld.long 0x134 19. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_51,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_51" "0,1" newline bitfld.long 0x134 18. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_50,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_50" "0,1" newline bitfld.long 0x134 17. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_49,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_49" "0,1" newline bitfld.long 0x134 16. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_48,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_48" "0,1" newline bitfld.long 0x134 15. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_47,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_47" "0,1" newline bitfld.long 0x134 14. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_46,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_46" "0,1" newline bitfld.long 0x134 13. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_45,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_45" "0,1" newline bitfld.long 0x134 12. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_44,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_44" "0,1" newline bitfld.long 0x134 11. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_43,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_43" "0,1" newline bitfld.long 0x134 10. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_42,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_42" "0,1" newline bitfld.long 0x134 9. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_41,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_41" "0,1" newline bitfld.long 0x134 8. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_40,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_40" "0,1" newline bitfld.long 0x134 7. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_39,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_39" "0,1" newline bitfld.long 0x134 6. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_38,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_38" "0,1" newline bitfld.long 0x134 5. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_37,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_37" "0,1" newline bitfld.long 0x134 4. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_36,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_36" "0,1" newline bitfld.long 0x134 3. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_35,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_35" "0,1" newline bitfld.long 0x134 2. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_34,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_34" "0,1" newline bitfld.long 0x134 1. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_33,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_33" "0,1" newline bitfld.long 0x134 0. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_32,Status write 1 to set for pulse_vpac_out_3_en_utc0_complete_32" "0,1" line.long 0x138 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_6,Status Register 78" bitfld.long 0x138 0. "STATUS_PULSE_VPAC_OUT_3_UTC1_RSVD_UNUSED,Status write 1 to set for pulse_vpac_out_3_en_utc1_rsvd_unused" "0,1" line.long 0x13C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_3_7,Status Register 79" bitfld.long 0x13C 4. "STATUS_PULSE_VPAC_OUT_3_CTM_PULSE,Status write 1 to set for pulse_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x13C 2. "STATUS_PULSE_VPAC_OUT_3_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x13C 0. "STATUS_PULSE_VPAC_OUT_3_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_3_en_utc0_error" "0,1" line.long 0x140 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_0,Status Register 80" bitfld.long 0x140 27. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_DPC_STATS_READ_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x140 26. "STATUS_PULSE_VPAC_OUT_4_VISS0_CR_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x140 25. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x140 24. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x140 23. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x140 22. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x140 21. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x140 20. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x140 19. "STATUS_PULSE_VPAC_OUT_4_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x140 18. "STATUS_PULSE_VPAC_OUT_4_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x140 17. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x140 16. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x140 15. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x140 14. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x140 13. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x140 12. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x140 11. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x140 10. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x140 9. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x140 8. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x140 7. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x140 6. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x140 5. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x140 4. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x140 3. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x140 2. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x140 1. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x140 0. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x144 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_1,Status Register 81" bitfld.long 0x144 8. "STATUS_PULSE_VPAC_OUT_4_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x144 7. "STATUS_PULSE_VPAC_OUT_4_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x144 6. "STATUS_PULSE_VPAC_OUT_4_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x144 5. "STATUS_PULSE_VPAC_OUT_4_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x144 4. "STATUS_PULSE_VPAC_OUT_4_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x144 3. "STATUS_PULSE_VPAC_OUT_4_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x144 2. "STATUS_PULSE_VPAC_OUT_4_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x144 1. "STATUS_PULSE_VPAC_OUT_4_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x144 0. "STATUS_PULSE_VPAC_OUT_4_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x148 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_2,Status Register 82" bitfld.long 0x148 3. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x148 2. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x148 1. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x148 0. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x14C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_3,Status Register 83" bitfld.long 0x14C 26. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x14C 25. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x14C 24. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x14C 22. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x14C 20. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x14C 19. "STATUS_PULSE_VPAC_OUT_4_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_4_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x14C 18. "STATUS_PULSE_VPAC_OUT_4_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_4_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x14C 17. "STATUS_PULSE_VPAC_OUT_4_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_4_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x14C 16. "STATUS_PULSE_VPAC_OUT_4_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_4_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x14C 15. "STATUS_PULSE_VPAC_OUT_4_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x14C 14. "STATUS_PULSE_VPAC_OUT_4_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x14C 13. "STATUS_PULSE_VPAC_OUT_4_TDONE_6,Status write 1 to set for pulse_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x14C 12. "STATUS_PULSE_VPAC_OUT_4_TDONE_5,Status write 1 to set for pulse_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x14C 11. "STATUS_PULSE_VPAC_OUT_4_TDONE_4,Status write 1 to set for pulse_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x14C 9. "STATUS_PULSE_VPAC_OUT_4_TDONE_2,Status write 1 to set for pulse_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x14C 7. "STATUS_PULSE_VPAC_OUT_4_TDONE_0,Status write 1 to set for pulse_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x14C 6. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x14C 5. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x14C 4. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x14C 3. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x14C 2. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x14C 1. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x14C 0. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x150 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_4,Status Register 84" bitfld.long 0x150 31. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x150 30. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x150 29. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x150 28. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x150 27. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x150 26. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x150 25. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x150 24. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x150 23. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x150 22. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x150 21. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x150 20. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x150 19. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x150 18. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x150 17. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x150 16. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x150 15. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x150 14. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x150 13. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x150 12. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x150 11. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x150 10. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x150 9. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x150 8. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x150 7. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x150 6. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x150 5. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x150 4. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x150 3. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x150 2. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x150 1. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x150 0. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x154 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_5,Status Register 85" bitfld.long 0x154 31. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_63,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_63" "0,1" newline bitfld.long 0x154 30. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_62,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_62" "0,1" newline bitfld.long 0x154 29. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_61,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_61" "0,1" newline bitfld.long 0x154 28. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_60,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_60" "0,1" newline bitfld.long 0x154 27. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_59,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_59" "0,1" newline bitfld.long 0x154 26. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_58,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_58" "0,1" newline bitfld.long 0x154 25. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_57,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_57" "0,1" newline bitfld.long 0x154 24. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_56,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_56" "0,1" newline bitfld.long 0x154 23. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_55,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_55" "0,1" newline bitfld.long 0x154 22. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_54,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_54" "0,1" newline bitfld.long 0x154 21. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_53,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_53" "0,1" newline bitfld.long 0x154 20. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_52,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_52" "0,1" newline bitfld.long 0x154 19. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_51,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_51" "0,1" newline bitfld.long 0x154 18. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_50,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_50" "0,1" newline bitfld.long 0x154 17. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_49,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_49" "0,1" newline bitfld.long 0x154 16. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_48,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_48" "0,1" newline bitfld.long 0x154 15. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_47,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_47" "0,1" newline bitfld.long 0x154 14. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_46,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_46" "0,1" newline bitfld.long 0x154 13. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_45,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_45" "0,1" newline bitfld.long 0x154 12. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_44,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_44" "0,1" newline bitfld.long 0x154 11. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_43,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_43" "0,1" newline bitfld.long 0x154 10. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_42,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_42" "0,1" newline bitfld.long 0x154 9. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_41,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_41" "0,1" newline bitfld.long 0x154 8. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_40,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_40" "0,1" newline bitfld.long 0x154 7. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_39,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_39" "0,1" newline bitfld.long 0x154 6. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_38,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_38" "0,1" newline bitfld.long 0x154 5. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_37,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_37" "0,1" newline bitfld.long 0x154 4. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_36,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_36" "0,1" newline bitfld.long 0x154 3. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_35,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_35" "0,1" newline bitfld.long 0x154 2. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_34,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_34" "0,1" newline bitfld.long 0x154 1. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_33,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_33" "0,1" newline bitfld.long 0x154 0. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_32,Status write 1 to set for pulse_vpac_out_4_en_utc0_complete_32" "0,1" line.long 0x158 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_6,Status Register 86" bitfld.long 0x158 0. "STATUS_PULSE_VPAC_OUT_4_UTC1_RSVD_UNUSED,Status write 1 to set for pulse_vpac_out_4_en_utc1_rsvd_unused" "0,1" line.long 0x15C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_4_7,Status Register 87" bitfld.long 0x15C 4. "STATUS_PULSE_VPAC_OUT_4_CTM_PULSE,Status write 1 to set for pulse_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x15C 2. "STATUS_PULSE_VPAC_OUT_4_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x15C 0. "STATUS_PULSE_VPAC_OUT_4_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_4_en_utc0_error" "0,1" line.long 0x160 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_0,Status Register 88" bitfld.long 0x160 27. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_DPC_STATS_READ_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x160 26. "STATUS_PULSE_VPAC_OUT_5_VISS0_CR_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x160 25. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_X_Y_POINTER,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x160 24. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_OUT_FR_START_EVT,Status write 1 to set for pulse_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x160 23. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_CAL_VP_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x160 22. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x160 21. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x160 20. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x160 19. "STATUS_PULSE_VPAC_OUT_5_VISS0_EE_SYNCOVF_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x160 18. "STATUS_PULSE_VPAC_OUT_5_VISS0_EE_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x160 17. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_HIST_READ_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x160 16. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_OUTIF_OVF_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x160 15. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x160 14. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCFA_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x160 13. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_VP_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x160 12. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_VSYNC_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x160 11. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_HSYNC_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x160 10. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_FILT_DONE,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x160 9. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_FILT_START,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x160 8. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x160 7. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_VBLANK_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x160 6. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_HBLANK_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x160 5. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_LINEMEM_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x160 4. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x160 3. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_H3A_PULSE,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x160 2. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_AF_PULSE,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x160 1. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_AEW_PULSE,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x160 0. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_CFG_ERR,Status write 1 to set for pulse_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0x164 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_1,Status Register 89" bitfld.long 0x164 8. "STATUS_PULSE_VPAC_OUT_5_LDC0_VBUSM_RD_ERR,Status write 1 to set for pulse_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x164 7. "STATUS_PULSE_VPAC_OUT_5_LDC0_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x164 6. "STATUS_PULSE_VPAC_OUT_5_LDC0_FR_DONE_EVT,Status write 1 to set for pulse_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x164 5. "STATUS_PULSE_VPAC_OUT_5_LDC0_INT_SZOVF,Status write 1 to set for pulse_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x164 4. "STATUS_PULSE_VPAC_OUT_5_LDC0_IFR_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x164 3. "STATUS_PULSE_VPAC_OUT_5_LDC0_MESH_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x164 2. "STATUS_PULSE_VPAC_OUT_5_LDC0_PIX_IBLK_MEMOVF,Status write 1 to set for pulse_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x164 1. "STATUS_PULSE_VPAC_OUT_5_LDC0_MESH_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x164 0. "STATUS_PULSE_VPAC_OUT_5_LDC0_PIX_IBLK_OUTOFBOUND,Status write 1 to set for pulse_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x168 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_2,Status Register 90" bitfld.long 0x168 3. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_SL2_WR_ERR,Status write 1 to set for pulse_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x168 2. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_SL2_RD_ERR,Status write 1 to set for pulse_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x168 1. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_1,Status write 1 to set for pulse_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x168 0. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_0,Status write 1 to set for pulse_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x16C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_3,Status Register 91" bitfld.long 0x16C 26. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_6,Status write 1 to set for pulse_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x16C 25. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_5,Status write 1 to set for pulse_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x16C 24. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_4,Status write 1 to set for pulse_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x16C 22. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_2,Status write 1 to set for pulse_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x16C 20. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_0,Status write 1 to set for pulse_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline rbitfld.long 0x16C 19. "STATUS_PULSE_VPAC_OUT_5_SPARE_PEND_1_LEVEL,Status for pulse_vpac_out_5_en_spare_pend_1_level" "0,1" newline rbitfld.long 0x16C 18. "STATUS_PULSE_VPAC_OUT_5_SPARE_PEND_1_PULSE,Status for pulse_vpac_out_5_en_spare_pend_1_pulse" "0,1" newline rbitfld.long 0x16C 17. "STATUS_PULSE_VPAC_OUT_5_SPARE_PEND_0_LEVEL,Status for pulse_vpac_out_5_en_spare_pend_0_level" "0,1" newline rbitfld.long 0x16C 16. "STATUS_PULSE_VPAC_OUT_5_SPARE_PEND_0_PULSE,Status for pulse_vpac_out_5_en_spare_pend_0_pulse" "0,1" newline bitfld.long 0x16C 15. "STATUS_PULSE_VPAC_OUT_5_SPARE_DEC_1,Status write 1 to set for pulse_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0x16C 14. "STATUS_PULSE_VPAC_OUT_5_SPARE_DEC_0,Status write 1 to set for pulse_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0x16C 13. "STATUS_PULSE_VPAC_OUT_5_TDONE_6,Status write 1 to set for pulse_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0x16C 12. "STATUS_PULSE_VPAC_OUT_5_TDONE_5,Status write 1 to set for pulse_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0x16C 11. "STATUS_PULSE_VPAC_OUT_5_TDONE_4,Status write 1 to set for pulse_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0x16C 9. "STATUS_PULSE_VPAC_OUT_5_TDONE_2,Status write 1 to set for pulse_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0x16C 7. "STATUS_PULSE_VPAC_OUT_5_TDONE_0,Status write 1 to set for pulse_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0x16C 6. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_6,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0x16C 5. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_5,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0x16C 4. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_4,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0x16C 3. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_3,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0x16C 2. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_2,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0x16C 1. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_1,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0x16C 0. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_0,Status write 1 to set for pulse_vpac_out_5_en_pipe_done_0" "0,1" line.long 0x170 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_4,Status Register 92" bitfld.long 0x170 31. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_31,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0x170 30. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_30,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0x170 29. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_29,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0x170 28. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_28,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0x170 27. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_27,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0x170 26. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_26,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0x170 25. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_25,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0x170 24. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_24,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0x170 23. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_23,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0x170 22. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_22,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0x170 21. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_21,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0x170 20. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_20,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0x170 19. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_19,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0x170 18. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_18,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0x170 17. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_17,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0x170 16. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_16,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0x170 15. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_15,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0x170 14. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_14,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0x170 13. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_13,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0x170 12. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_12,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0x170 11. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_11,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0x170 10. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_10,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0x170 9. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_9,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0x170 8. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_8,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0x170 7. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_7,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0x170 6. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_6,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0x170 5. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_5,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0x170 4. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_4,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0x170 3. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_3,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0x170 2. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_2,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0x170 1. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_1,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0x170 0. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_0,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0x174 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_5,Status Register 93" bitfld.long 0x174 31. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_63,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_63" "0,1" newline bitfld.long 0x174 30. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_62,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_62" "0,1" newline bitfld.long 0x174 29. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_61,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_61" "0,1" newline bitfld.long 0x174 28. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_60,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_60" "0,1" newline bitfld.long 0x174 27. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_59,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_59" "0,1" newline bitfld.long 0x174 26. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_58,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_58" "0,1" newline bitfld.long 0x174 25. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_57,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_57" "0,1" newline bitfld.long 0x174 24. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_56,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_56" "0,1" newline bitfld.long 0x174 23. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_55,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_55" "0,1" newline bitfld.long 0x174 22. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_54,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_54" "0,1" newline bitfld.long 0x174 21. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_53,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_53" "0,1" newline bitfld.long 0x174 20. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_52,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_52" "0,1" newline bitfld.long 0x174 19. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_51,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_51" "0,1" newline bitfld.long 0x174 18. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_50,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_50" "0,1" newline bitfld.long 0x174 17. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_49,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_49" "0,1" newline bitfld.long 0x174 16. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_48,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_48" "0,1" newline bitfld.long 0x174 15. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_47,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_47" "0,1" newline bitfld.long 0x174 14. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_46,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_46" "0,1" newline bitfld.long 0x174 13. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_45,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_45" "0,1" newline bitfld.long 0x174 12. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_44,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_44" "0,1" newline bitfld.long 0x174 11. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_43,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_43" "0,1" newline bitfld.long 0x174 10. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_42,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_42" "0,1" newline bitfld.long 0x174 9. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_41,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_41" "0,1" newline bitfld.long 0x174 8. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_40,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_40" "0,1" newline bitfld.long 0x174 7. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_39,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_39" "0,1" newline bitfld.long 0x174 6. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_38,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_38" "0,1" newline bitfld.long 0x174 5. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_37,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_37" "0,1" newline bitfld.long 0x174 4. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_36,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_36" "0,1" newline bitfld.long 0x174 3. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_35,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_35" "0,1" newline bitfld.long 0x174 2. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_34,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_34" "0,1" newline bitfld.long 0x174 1. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_33,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_33" "0,1" newline bitfld.long 0x174 0. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_32,Status write 1 to set for pulse_vpac_out_5_en_utc0_complete_32" "0,1" line.long 0x178 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_6,Status Register 94" bitfld.long 0x178 0. "STATUS_PULSE_VPAC_OUT_5_UTC1_RSVD_UNUSED,Status write 1 to set for pulse_vpac_out_5_en_utc1_rsvd_unused" "0,1" line.long 0x17C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_vpac_out_5_7,Status Register 95" bitfld.long 0x17C 4. "STATUS_PULSE_VPAC_OUT_5_CTM_PULSE,Status write 1 to set for pulse_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0x17C 2. "STATUS_PULSE_VPAC_OUT_5_UTC0_PROT_ERR,Status write 1 to set for pulse_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0x17C 0. "STATUS_PULSE_VPAC_OUT_5_UTC0_ERROR,Status write 1 to set for pulse_vpac_out_5_en_utc0_error" "0,1" group.long 0x700++0x17F line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_0,Status Clear Register 0" bitfld.long 0x0 27. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x0 26. "STATUS_LEVEL_VPAC_OUT_0_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x0 25. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x0 24. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x0 23. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x0 22. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x0 21. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x0 20. "STATUS_LEVEL_VPAC_OUT_0_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x0 19. "STATUS_LEVEL_VPAC_OUT_0_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x0 18. "STATUS_LEVEL_VPAC_OUT_0_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x0 17. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x0 16. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x0 15. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x0 14. "STATUS_LEVEL_VPAC_OUT_0_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x0 13. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x0 12. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x0 11. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x0 10. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x0 9. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x0 8. "STATUS_LEVEL_VPAC_OUT_0_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x0 7. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x0 6. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x0 5. "STATUS_LEVEL_VPAC_OUT_0_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x0 4. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x0 3. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x0 2. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x0 1. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x0 0. "STATUS_LEVEL_VPAC_OUT_0_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_1,Status Clear Register 1" bitfld.long 0x4 8. "STATUS_LEVEL_VPAC_OUT_0_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x4 7. "STATUS_LEVEL_VPAC_OUT_0_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x4 6. "STATUS_LEVEL_VPAC_OUT_0_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x4 5. "STATUS_LEVEL_VPAC_OUT_0_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x4 4. "STATUS_LEVEL_VPAC_OUT_0_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x4 3. "STATUS_LEVEL_VPAC_OUT_0_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x4 2. "STATUS_LEVEL_VPAC_OUT_0_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x4 1. "STATUS_LEVEL_VPAC_OUT_0_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x4 0. "STATUS_LEVEL_VPAC_OUT_0_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_2,Status Clear Register 2" bitfld.long 0x8 3. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x8 2. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x8 1. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x8 0. "STATUS_LEVEL_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_3,Status Clear Register 3" bitfld.long 0xC 26. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xC 25. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xC 24. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xC 22. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xC 20. "STATUS_LEVEL_VPAC_OUT_0_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xC 15. "STATUS_LEVEL_VPAC_OUT_0_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xC 14. "STATUS_LEVEL_VPAC_OUT_0_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xC 13. "STATUS_LEVEL_VPAC_OUT_0_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xC 12. "STATUS_LEVEL_VPAC_OUT_0_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xC 11. "STATUS_LEVEL_VPAC_OUT_0_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xC 9. "STATUS_LEVEL_VPAC_OUT_0_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xC 7. "STATUS_LEVEL_VPAC_OUT_0_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xC 6. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xC 5. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xC 4. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xC 3. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xC 2. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xC 1. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xC 0. "STATUS_LEVEL_VPAC_OUT_0_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_0_en_pipe_done_0" "0,1" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_4,Status Clear Register 4" bitfld.long 0x10 31. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0x10 30. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0x10 29. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0x10 28. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0x10 27. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0x10 26. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0x10 25. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0x10 24. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0x10 23. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0x10 22. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0x10 21. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0x10 20. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0x10 19. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0x10 18. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0x10 17. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0x10 16. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0x10 15. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0x10 14. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0x10 13. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0x10 12. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0x10 11. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0x10 10. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0x10 9. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0x10 8. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0x10 7. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0x10 6. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0x10 5. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0x10 4. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0x10 3. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0x10 2. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0x10 1. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0x10 0. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_5,Status Clear Register 5" bitfld.long 0x14 31. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_63" "0,1" newline bitfld.long 0x14 30. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_62" "0,1" newline bitfld.long 0x14 29. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_61" "0,1" newline bitfld.long 0x14 28. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_60" "0,1" newline bitfld.long 0x14 27. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_59" "0,1" newline bitfld.long 0x14 26. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_58" "0,1" newline bitfld.long 0x14 25. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_57" "0,1" newline bitfld.long 0x14 24. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_56" "0,1" newline bitfld.long 0x14 23. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_55" "0,1" newline bitfld.long 0x14 22. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_54" "0,1" newline bitfld.long 0x14 21. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_53" "0,1" newline bitfld.long 0x14 20. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_52" "0,1" newline bitfld.long 0x14 19. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_51" "0,1" newline bitfld.long 0x14 18. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_50" "0,1" newline bitfld.long 0x14 17. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_49" "0,1" newline bitfld.long 0x14 16. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_48" "0,1" newline bitfld.long 0x14 15. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_47" "0,1" newline bitfld.long 0x14 14. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_46" "0,1" newline bitfld.long 0x14 13. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_45" "0,1" newline bitfld.long 0x14 12. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_44" "0,1" newline bitfld.long 0x14 11. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_43" "0,1" newline bitfld.long 0x14 10. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_42" "0,1" newline bitfld.long 0x14 9. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_41" "0,1" newline bitfld.long 0x14 8. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_40" "0,1" newline bitfld.long 0x14 7. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_39" "0,1" newline bitfld.long 0x14 6. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_38" "0,1" newline bitfld.long 0x14 5. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_37" "0,1" newline bitfld.long 0x14 4. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_36" "0,1" newline bitfld.long 0x14 3. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_35" "0,1" newline bitfld.long 0x14 2. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_34" "0,1" newline bitfld.long 0x14 1. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_33" "0,1" newline bitfld.long 0x14 0. "STATUS_LEVEL_VPAC_OUT_0_UTC0_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_complete_32" "0,1" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_6,Status Clear Register 6" bitfld.long 0x18 0. "STATUS_LEVEL_VPAC_OUT_0_UTC1_RSVD_UNUSED_CLR,Status write 1 to clear for level_vpac_out_0_en_utc1_rsvd_unused" "0,1" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_0_7,Status Clear Register 7" bitfld.long 0x1C 4. "STATUS_LEVEL_VPAC_OUT_0_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0x1C 2. "STATUS_LEVEL_VPAC_OUT_0_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0x1C 0. "STATUS_LEVEL_VPAC_OUT_0_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_0_en_utc0_error" "0,1" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_0,Status Clear Register 8" bitfld.long 0x20 27. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x20 26. "STATUS_LEVEL_VPAC_OUT_1_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x20 25. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x20 24. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x20 23. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x20 22. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x20 21. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x20 20. "STATUS_LEVEL_VPAC_OUT_1_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x20 19. "STATUS_LEVEL_VPAC_OUT_1_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x20 18. "STATUS_LEVEL_VPAC_OUT_1_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x20 17. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x20 16. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x20 15. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x20 14. "STATUS_LEVEL_VPAC_OUT_1_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x20 13. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x20 12. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x20 11. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x20 10. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x20 9. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x20 8. "STATUS_LEVEL_VPAC_OUT_1_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x20 7. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x20 6. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x20 5. "STATUS_LEVEL_VPAC_OUT_1_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x20 4. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x20 3. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x20 2. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x20 1. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x20 0. "STATUS_LEVEL_VPAC_OUT_1_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_1,Status Clear Register 9" bitfld.long 0x24 8. "STATUS_LEVEL_VPAC_OUT_1_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x24 7. "STATUS_LEVEL_VPAC_OUT_1_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x24 6. "STATUS_LEVEL_VPAC_OUT_1_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x24 5. "STATUS_LEVEL_VPAC_OUT_1_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x24 4. "STATUS_LEVEL_VPAC_OUT_1_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x24 3. "STATUS_LEVEL_VPAC_OUT_1_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x24 2. "STATUS_LEVEL_VPAC_OUT_1_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x24 1. "STATUS_LEVEL_VPAC_OUT_1_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x24 0. "STATUS_LEVEL_VPAC_OUT_1_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_2,Status Clear Register 10" bitfld.long 0x28 3. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x28 2. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x28 1. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x28 0. "STATUS_LEVEL_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_3,Status Clear Register 11" bitfld.long 0x2C 26. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x2C 25. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x2C 24. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x2C 22. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x2C 20. "STATUS_LEVEL_VPAC_OUT_1_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x2C 15. "STATUS_LEVEL_VPAC_OUT_1_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0x2C 14. "STATUS_LEVEL_VPAC_OUT_1_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0x2C 13. "STATUS_LEVEL_VPAC_OUT_1_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0x2C 12. "STATUS_LEVEL_VPAC_OUT_1_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0x2C 11. "STATUS_LEVEL_VPAC_OUT_1_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0x2C 9. "STATUS_LEVEL_VPAC_OUT_1_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0x2C 7. "STATUS_LEVEL_VPAC_OUT_1_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0x2C 6. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0x2C 5. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0x2C 4. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0x2C 3. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0x2C 2. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0x2C 1. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0x2C 0. "STATUS_LEVEL_VPAC_OUT_1_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_1_en_pipe_done_0" "0,1" line.long 0x30 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_4,Status Clear Register 12" bitfld.long 0x30 31. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0x30 30. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0x30 29. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0x30 28. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0x30 27. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0x30 26. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0x30 25. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0x30 24. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0x30 23. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0x30 22. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0x30 21. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0x30 20. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0x30 19. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0x30 18. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0x30 17. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0x30 16. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0x30 15. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0x30 14. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0x30 13. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0x30 12. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0x30 11. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0x30 10. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0x30 9. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0x30 8. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0x30 7. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0x30 6. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0x30 5. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0x30 4. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0x30 3. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0x30 2. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0x30 1. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0x30 0. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_5,Status Clear Register 13" bitfld.long 0x34 31. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_63" "0,1" newline bitfld.long 0x34 30. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_62" "0,1" newline bitfld.long 0x34 29. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_61" "0,1" newline bitfld.long 0x34 28. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_60" "0,1" newline bitfld.long 0x34 27. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_59" "0,1" newline bitfld.long 0x34 26. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_58" "0,1" newline bitfld.long 0x34 25. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_57" "0,1" newline bitfld.long 0x34 24. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_56" "0,1" newline bitfld.long 0x34 23. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_55" "0,1" newline bitfld.long 0x34 22. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_54" "0,1" newline bitfld.long 0x34 21. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_53" "0,1" newline bitfld.long 0x34 20. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_52" "0,1" newline bitfld.long 0x34 19. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_51" "0,1" newline bitfld.long 0x34 18. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_50" "0,1" newline bitfld.long 0x34 17. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_49" "0,1" newline bitfld.long 0x34 16. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_48" "0,1" newline bitfld.long 0x34 15. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_47" "0,1" newline bitfld.long 0x34 14. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_46" "0,1" newline bitfld.long 0x34 13. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_45" "0,1" newline bitfld.long 0x34 12. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_44" "0,1" newline bitfld.long 0x34 11. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_43" "0,1" newline bitfld.long 0x34 10. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_42" "0,1" newline bitfld.long 0x34 9. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_41" "0,1" newline bitfld.long 0x34 8. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_40" "0,1" newline bitfld.long 0x34 7. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_39" "0,1" newline bitfld.long 0x34 6. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_38" "0,1" newline bitfld.long 0x34 5. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_37" "0,1" newline bitfld.long 0x34 4. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_36" "0,1" newline bitfld.long 0x34 3. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_35" "0,1" newline bitfld.long 0x34 2. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_34" "0,1" newline bitfld.long 0x34 1. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_33" "0,1" newline bitfld.long 0x34 0. "STATUS_LEVEL_VPAC_OUT_1_UTC0_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_complete_32" "0,1" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_6,Status Clear Register 14" bitfld.long 0x38 0. "STATUS_LEVEL_VPAC_OUT_1_UTC1_RSVD_UNUSED_CLR,Status write 1 to clear for level_vpac_out_1_en_utc1_rsvd_unused" "0,1" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_1_7,Status Clear Register 15" bitfld.long 0x3C 4. "STATUS_LEVEL_VPAC_OUT_1_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0x3C 2. "STATUS_LEVEL_VPAC_OUT_1_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0x3C 0. "STATUS_LEVEL_VPAC_OUT_1_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_1_en_utc0_error" "0,1" line.long 0x40 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_0,Status Clear Register 16" bitfld.long 0x40 27. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x40 26. "STATUS_LEVEL_VPAC_OUT_2_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x40 25. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x40 24. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x40 23. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x40 22. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x40 21. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x40 20. "STATUS_LEVEL_VPAC_OUT_2_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x40 19. "STATUS_LEVEL_VPAC_OUT_2_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x40 18. "STATUS_LEVEL_VPAC_OUT_2_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x40 17. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x40 16. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x40 15. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x40 14. "STATUS_LEVEL_VPAC_OUT_2_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x40 13. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x40 12. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x40 11. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x40 10. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x40 9. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x40 8. "STATUS_LEVEL_VPAC_OUT_2_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x40 7. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x40 6. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x40 5. "STATUS_LEVEL_VPAC_OUT_2_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x40 4. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x40 3. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x40 2. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x40 1. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x40 0. "STATUS_LEVEL_VPAC_OUT_2_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x44 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_1,Status Clear Register 17" bitfld.long 0x44 8. "STATUS_LEVEL_VPAC_OUT_2_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x44 7. "STATUS_LEVEL_VPAC_OUT_2_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x44 6. "STATUS_LEVEL_VPAC_OUT_2_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x44 5. "STATUS_LEVEL_VPAC_OUT_2_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x44 4. "STATUS_LEVEL_VPAC_OUT_2_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x44 3. "STATUS_LEVEL_VPAC_OUT_2_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x44 2. "STATUS_LEVEL_VPAC_OUT_2_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x44 1. "STATUS_LEVEL_VPAC_OUT_2_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x44 0. "STATUS_LEVEL_VPAC_OUT_2_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x48 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_2,Status Clear Register 18" bitfld.long 0x48 3. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x48 2. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x48 1. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x48 0. "STATUS_LEVEL_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x4C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_3,Status Clear Register 19" bitfld.long 0x4C 26. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x4C 25. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x4C 24. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x4C 22. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x4C 20. "STATUS_LEVEL_VPAC_OUT_2_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x4C 15. "STATUS_LEVEL_VPAC_OUT_2_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x4C 14. "STATUS_LEVEL_VPAC_OUT_2_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x4C 13. "STATUS_LEVEL_VPAC_OUT_2_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x4C 12. "STATUS_LEVEL_VPAC_OUT_2_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x4C 11. "STATUS_LEVEL_VPAC_OUT_2_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x4C 9. "STATUS_LEVEL_VPAC_OUT_2_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x4C 7. "STATUS_LEVEL_VPAC_OUT_2_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x4C 6. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x4C 5. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x4C 4. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x4C 3. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x4C 2. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x4C 1. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x4C 0. "STATUS_LEVEL_VPAC_OUT_2_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x50 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_4,Status Clear Register 20" bitfld.long 0x50 31. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x50 30. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x50 29. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x50 28. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x50 27. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x50 26. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x50 25. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x50 24. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x50 23. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x50 22. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x50 21. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x50 20. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x50 19. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x50 18. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x50 17. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x50 16. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x50 15. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x50 14. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x50 13. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x50 12. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x50 11. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x50 10. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x50 9. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x50 8. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x50 7. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x50 6. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x50 5. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x50 4. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x50 3. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x50 2. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x50 1. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x50 0. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x54 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_5,Status Clear Register 21" bitfld.long 0x54 31. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_63" "0,1" newline bitfld.long 0x54 30. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_62" "0,1" newline bitfld.long 0x54 29. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_61" "0,1" newline bitfld.long 0x54 28. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_60" "0,1" newline bitfld.long 0x54 27. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_59" "0,1" newline bitfld.long 0x54 26. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_58" "0,1" newline bitfld.long 0x54 25. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_57" "0,1" newline bitfld.long 0x54 24. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_56" "0,1" newline bitfld.long 0x54 23. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_55" "0,1" newline bitfld.long 0x54 22. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_54" "0,1" newline bitfld.long 0x54 21. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_53" "0,1" newline bitfld.long 0x54 20. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_52" "0,1" newline bitfld.long 0x54 19. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_51" "0,1" newline bitfld.long 0x54 18. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_50" "0,1" newline bitfld.long 0x54 17. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_49" "0,1" newline bitfld.long 0x54 16. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_48" "0,1" newline bitfld.long 0x54 15. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_47" "0,1" newline bitfld.long 0x54 14. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_46" "0,1" newline bitfld.long 0x54 13. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_45" "0,1" newline bitfld.long 0x54 12. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_44" "0,1" newline bitfld.long 0x54 11. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_43" "0,1" newline bitfld.long 0x54 10. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_42" "0,1" newline bitfld.long 0x54 9. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_41" "0,1" newline bitfld.long 0x54 8. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_40" "0,1" newline bitfld.long 0x54 7. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_39" "0,1" newline bitfld.long 0x54 6. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_38" "0,1" newline bitfld.long 0x54 5. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_37" "0,1" newline bitfld.long 0x54 4. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_36" "0,1" newline bitfld.long 0x54 3. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_35" "0,1" newline bitfld.long 0x54 2. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_34" "0,1" newline bitfld.long 0x54 1. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_33" "0,1" newline bitfld.long 0x54 0. "STATUS_LEVEL_VPAC_OUT_2_UTC0_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_complete_32" "0,1" line.long 0x58 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_6,Status Clear Register 22" bitfld.long 0x58 0. "STATUS_LEVEL_VPAC_OUT_2_UTC1_RSVD_UNUSED_CLR,Status write 1 to clear for level_vpac_out_2_en_utc1_rsvd_unused" "0,1" line.long 0x5C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_2_7,Status Clear Register 23" bitfld.long 0x5C 4. "STATUS_LEVEL_VPAC_OUT_2_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x5C 2. "STATUS_LEVEL_VPAC_OUT_2_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x5C 0. "STATUS_LEVEL_VPAC_OUT_2_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_2_en_utc0_error" "0,1" line.long 0x60 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_0,Status Clear Register 24" bitfld.long 0x60 27. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x60 26. "STATUS_LEVEL_VPAC_OUT_3_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x60 25. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x60 24. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x60 23. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x60 22. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x60 21. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x60 20. "STATUS_LEVEL_VPAC_OUT_3_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x60 19. "STATUS_LEVEL_VPAC_OUT_3_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x60 18. "STATUS_LEVEL_VPAC_OUT_3_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x60 17. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x60 16. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x60 15. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x60 14. "STATUS_LEVEL_VPAC_OUT_3_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x60 13. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x60 12. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x60 11. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x60 10. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x60 9. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x60 8. "STATUS_LEVEL_VPAC_OUT_3_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x60 7. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x60 6. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x60 5. "STATUS_LEVEL_VPAC_OUT_3_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x60 4. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x60 3. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x60 2. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x60 1. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x60 0. "STATUS_LEVEL_VPAC_OUT_3_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x64 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_1,Status Clear Register 25" bitfld.long 0x64 8. "STATUS_LEVEL_VPAC_OUT_3_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x64 7. "STATUS_LEVEL_VPAC_OUT_3_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x64 6. "STATUS_LEVEL_VPAC_OUT_3_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x64 5. "STATUS_LEVEL_VPAC_OUT_3_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x64 4. "STATUS_LEVEL_VPAC_OUT_3_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x64 3. "STATUS_LEVEL_VPAC_OUT_3_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x64 2. "STATUS_LEVEL_VPAC_OUT_3_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x64 1. "STATUS_LEVEL_VPAC_OUT_3_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x64 0. "STATUS_LEVEL_VPAC_OUT_3_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x68 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_2,Status Clear Register 26" bitfld.long 0x68 3. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x68 2. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x68 1. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x68 0. "STATUS_LEVEL_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x6C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_3,Status Clear Register 27" bitfld.long 0x6C 26. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x6C 25. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x6C 24. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x6C 22. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x6C 20. "STATUS_LEVEL_VPAC_OUT_3_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x6C 15. "STATUS_LEVEL_VPAC_OUT_3_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x6C 14. "STATUS_LEVEL_VPAC_OUT_3_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x6C 13. "STATUS_LEVEL_VPAC_OUT_3_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x6C 12. "STATUS_LEVEL_VPAC_OUT_3_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x6C 11. "STATUS_LEVEL_VPAC_OUT_3_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x6C 9. "STATUS_LEVEL_VPAC_OUT_3_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x6C 7. "STATUS_LEVEL_VPAC_OUT_3_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x6C 6. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x6C 5. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x6C 4. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x6C 3. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x6C 2. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x6C 1. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x6C 0. "STATUS_LEVEL_VPAC_OUT_3_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x70 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_4,Status Clear Register 28" bitfld.long 0x70 31. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x70 30. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x70 29. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x70 28. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x70 27. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x70 26. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x70 25. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x70 24. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x70 23. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x70 22. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x70 21. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x70 20. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x70 19. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x70 18. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x70 17. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x70 16. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x70 15. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x70 14. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x70 13. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x70 12. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x70 11. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x70 10. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x70 9. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x70 8. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x70 7. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x70 6. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x70 5. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x70 4. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x70 3. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x70 2. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x70 1. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x70 0. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x74 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_5,Status Clear Register 29" bitfld.long 0x74 31. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_63" "0,1" newline bitfld.long 0x74 30. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_62" "0,1" newline bitfld.long 0x74 29. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_61" "0,1" newline bitfld.long 0x74 28. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_60" "0,1" newline bitfld.long 0x74 27. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_59" "0,1" newline bitfld.long 0x74 26. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_58" "0,1" newline bitfld.long 0x74 25. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_57" "0,1" newline bitfld.long 0x74 24. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_56" "0,1" newline bitfld.long 0x74 23. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_55" "0,1" newline bitfld.long 0x74 22. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_54" "0,1" newline bitfld.long 0x74 21. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_53" "0,1" newline bitfld.long 0x74 20. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_52" "0,1" newline bitfld.long 0x74 19. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_51" "0,1" newline bitfld.long 0x74 18. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_50" "0,1" newline bitfld.long 0x74 17. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_49" "0,1" newline bitfld.long 0x74 16. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_48" "0,1" newline bitfld.long 0x74 15. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_47" "0,1" newline bitfld.long 0x74 14. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_46" "0,1" newline bitfld.long 0x74 13. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_45" "0,1" newline bitfld.long 0x74 12. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_44" "0,1" newline bitfld.long 0x74 11. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_43" "0,1" newline bitfld.long 0x74 10. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_42" "0,1" newline bitfld.long 0x74 9. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_41" "0,1" newline bitfld.long 0x74 8. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_40" "0,1" newline bitfld.long 0x74 7. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_39" "0,1" newline bitfld.long 0x74 6. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_38" "0,1" newline bitfld.long 0x74 5. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_37" "0,1" newline bitfld.long 0x74 4. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_36" "0,1" newline bitfld.long 0x74 3. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_35" "0,1" newline bitfld.long 0x74 2. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_34" "0,1" newline bitfld.long 0x74 1. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_33" "0,1" newline bitfld.long 0x74 0. "STATUS_LEVEL_VPAC_OUT_3_UTC0_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_complete_32" "0,1" line.long 0x78 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_6,Status Clear Register 30" bitfld.long 0x78 0. "STATUS_LEVEL_VPAC_OUT_3_UTC1_RSVD_UNUSED_CLR,Status write 1 to clear for level_vpac_out_3_en_utc1_rsvd_unused" "0,1" line.long 0x7C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_3_7,Status Clear Register 31" bitfld.long 0x7C 4. "STATUS_LEVEL_VPAC_OUT_3_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x7C 2. "STATUS_LEVEL_VPAC_OUT_3_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x7C 0. "STATUS_LEVEL_VPAC_OUT_3_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_3_en_utc0_error" "0,1" line.long 0x80 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_0,Status Clear Register 32" bitfld.long 0x80 27. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x80 26. "STATUS_LEVEL_VPAC_OUT_4_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x80 25. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x80 24. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x80 23. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x80 22. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x80 21. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x80 20. "STATUS_LEVEL_VPAC_OUT_4_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x80 19. "STATUS_LEVEL_VPAC_OUT_4_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x80 18. "STATUS_LEVEL_VPAC_OUT_4_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x80 17. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x80 16. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x80 15. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x80 14. "STATUS_LEVEL_VPAC_OUT_4_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x80 13. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x80 12. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x80 11. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x80 10. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x80 9. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x80 8. "STATUS_LEVEL_VPAC_OUT_4_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x80 7. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x80 6. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x80 5. "STATUS_LEVEL_VPAC_OUT_4_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x80 4. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x80 3. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x80 2. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x80 1. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x80 0. "STATUS_LEVEL_VPAC_OUT_4_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x84 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_1,Status Clear Register 33" bitfld.long 0x84 8. "STATUS_LEVEL_VPAC_OUT_4_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x84 7. "STATUS_LEVEL_VPAC_OUT_4_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x84 6. "STATUS_LEVEL_VPAC_OUT_4_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x84 5. "STATUS_LEVEL_VPAC_OUT_4_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x84 4. "STATUS_LEVEL_VPAC_OUT_4_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x84 3. "STATUS_LEVEL_VPAC_OUT_4_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x84 2. "STATUS_LEVEL_VPAC_OUT_4_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x84 1. "STATUS_LEVEL_VPAC_OUT_4_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x84 0. "STATUS_LEVEL_VPAC_OUT_4_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x88 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_2,Status Clear Register 34" bitfld.long 0x88 3. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x88 2. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x88 1. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x88 0. "STATUS_LEVEL_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x8C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_3,Status Clear Register 35" bitfld.long 0x8C 26. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x8C 25. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x8C 24. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x8C 22. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x8C 20. "STATUS_LEVEL_VPAC_OUT_4_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x8C 15. "STATUS_LEVEL_VPAC_OUT_4_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x8C 14. "STATUS_LEVEL_VPAC_OUT_4_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x8C 13. "STATUS_LEVEL_VPAC_OUT_4_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x8C 12. "STATUS_LEVEL_VPAC_OUT_4_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x8C 11. "STATUS_LEVEL_VPAC_OUT_4_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x8C 9. "STATUS_LEVEL_VPAC_OUT_4_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x8C 7. "STATUS_LEVEL_VPAC_OUT_4_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x8C 6. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x8C 5. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x8C 4. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x8C 3. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x8C 2. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x8C 1. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x8C 0. "STATUS_LEVEL_VPAC_OUT_4_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x90 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_4,Status Clear Register 36" bitfld.long 0x90 31. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x90 30. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x90 29. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x90 28. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x90 27. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x90 26. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x90 25. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x90 24. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x90 23. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x90 22. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x90 21. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x90 20. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x90 19. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x90 18. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x90 17. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x90 16. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x90 15. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x90 14. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x90 13. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x90 12. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x90 11. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x90 10. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x90 9. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x90 8. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x90 7. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x90 6. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x90 5. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x90 4. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x90 3. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x90 2. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x90 1. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x90 0. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x94 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_5,Status Clear Register 37" bitfld.long 0x94 31. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_63" "0,1" newline bitfld.long 0x94 30. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_62" "0,1" newline bitfld.long 0x94 29. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_61" "0,1" newline bitfld.long 0x94 28. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_60" "0,1" newline bitfld.long 0x94 27. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_59" "0,1" newline bitfld.long 0x94 26. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_58" "0,1" newline bitfld.long 0x94 25. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_57" "0,1" newline bitfld.long 0x94 24. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_56" "0,1" newline bitfld.long 0x94 23. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_55" "0,1" newline bitfld.long 0x94 22. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_54" "0,1" newline bitfld.long 0x94 21. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_53" "0,1" newline bitfld.long 0x94 20. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_52" "0,1" newline bitfld.long 0x94 19. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_51" "0,1" newline bitfld.long 0x94 18. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_50" "0,1" newline bitfld.long 0x94 17. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_49" "0,1" newline bitfld.long 0x94 16. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_48" "0,1" newline bitfld.long 0x94 15. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_47" "0,1" newline bitfld.long 0x94 14. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_46" "0,1" newline bitfld.long 0x94 13. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_45" "0,1" newline bitfld.long 0x94 12. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_44" "0,1" newline bitfld.long 0x94 11. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_43" "0,1" newline bitfld.long 0x94 10. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_42" "0,1" newline bitfld.long 0x94 9. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_41" "0,1" newline bitfld.long 0x94 8. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_40" "0,1" newline bitfld.long 0x94 7. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_39" "0,1" newline bitfld.long 0x94 6. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_38" "0,1" newline bitfld.long 0x94 5. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_37" "0,1" newline bitfld.long 0x94 4. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_36" "0,1" newline bitfld.long 0x94 3. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_35" "0,1" newline bitfld.long 0x94 2. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_34" "0,1" newline bitfld.long 0x94 1. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_33" "0,1" newline bitfld.long 0x94 0. "STATUS_LEVEL_VPAC_OUT_4_UTC0_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_complete_32" "0,1" line.long 0x98 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_6,Status Clear Register 38" bitfld.long 0x98 0. "STATUS_LEVEL_VPAC_OUT_4_UTC1_RSVD_UNUSED_CLR,Status write 1 to clear for level_vpac_out_4_en_utc1_rsvd_unused" "0,1" line.long 0x9C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_4_7,Status Clear Register 39" bitfld.long 0x9C 4. "STATUS_LEVEL_VPAC_OUT_4_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x9C 2. "STATUS_LEVEL_VPAC_OUT_4_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x9C 0. "STATUS_LEVEL_VPAC_OUT_4_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_4_en_utc0_error" "0,1" line.long 0xA0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_0,Status Clear Register 40" bitfld.long 0xA0 27. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0xA0 26. "STATUS_LEVEL_VPAC_OUT_5_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xA0 25. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xA0 24. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xA0 23. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xA0 22. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA0 21. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA0 20. "STATUS_LEVEL_VPAC_OUT_5_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xA0 19. "STATUS_LEVEL_VPAC_OUT_5_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xA0 18. "STATUS_LEVEL_VPAC_OUT_5_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xA0 17. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xA0 16. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xA0 15. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xA0 14. "STATUS_LEVEL_VPAC_OUT_5_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xA0 13. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xA0 12. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xA0 11. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xA0 10. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xA0 9. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xA0 8. "STATUS_LEVEL_VPAC_OUT_5_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xA0 7. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xA0 6. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xA0 5. "STATUS_LEVEL_VPAC_OUT_5_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xA0 4. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xA0 3. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xA0 2. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xA0 1. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xA0 0. "STATUS_LEVEL_VPAC_OUT_5_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0xA4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_1,Status Clear Register 41" bitfld.long 0xA4 8. "STATUS_LEVEL_VPAC_OUT_5_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xA4 7. "STATUS_LEVEL_VPAC_OUT_5_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xA4 6. "STATUS_LEVEL_VPAC_OUT_5_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xA4 5. "STATUS_LEVEL_VPAC_OUT_5_LDC0_INT_SZOVF_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xA4 4. "STATUS_LEVEL_VPAC_OUT_5_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xA4 3. "STATUS_LEVEL_VPAC_OUT_5_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xA4 2. "STATUS_LEVEL_VPAC_OUT_5_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xA4 1. "STATUS_LEVEL_VPAC_OUT_5_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xA4 0. "STATUS_LEVEL_VPAC_OUT_5_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for level_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xA8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_2,Status Clear Register 42" bitfld.long 0xA8 3. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xA8 2. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xA8 1. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for level_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xA8 0. "STATUS_LEVEL_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for level_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xAC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_3,Status Clear Register 43" bitfld.long 0xAC 26. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for level_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xAC 25. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for level_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xAC 24. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for level_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xAC 22. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for level_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xAC 20. "STATUS_LEVEL_VPAC_OUT_5_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for level_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xAC 15. "STATUS_LEVEL_VPAC_OUT_5_SPARE_DEC_1_CLR,Status write 1 to clear for level_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0xAC 14. "STATUS_LEVEL_VPAC_OUT_5_SPARE_DEC_0_CLR,Status write 1 to clear for level_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0xAC 13. "STATUS_LEVEL_VPAC_OUT_5_TDONE_6_CLR,Status write 1 to clear for level_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0xAC 12. "STATUS_LEVEL_VPAC_OUT_5_TDONE_5_CLR,Status write 1 to clear for level_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0xAC 11. "STATUS_LEVEL_VPAC_OUT_5_TDONE_4_CLR,Status write 1 to clear for level_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0xAC 9. "STATUS_LEVEL_VPAC_OUT_5_TDONE_2_CLR,Status write 1 to clear for level_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0xAC 7. "STATUS_LEVEL_VPAC_OUT_5_TDONE_0_CLR,Status write 1 to clear for level_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0xAC 6. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_6_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0xAC 5. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_5_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0xAC 4. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_4_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0xAC 3. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_3_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0xAC 2. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_2_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0xAC 1. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_1_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0xAC 0. "STATUS_LEVEL_VPAC_OUT_5_PIPE_DONE_0_CLR,Status write 1 to clear for level_vpac_out_5_en_pipe_done_0" "0,1" line.long 0xB0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_4,Status Clear Register 44" bitfld.long 0xB0 31. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_31_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0xB0 30. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_30_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0xB0 29. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_29_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0xB0 28. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_28_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0xB0 27. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_27_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0xB0 26. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_26_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0xB0 25. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_25_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0xB0 24. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_24_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0xB0 23. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_23_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0xB0 22. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_22_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0xB0 21. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_21_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0xB0 20. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_20_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0xB0 19. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_19_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0xB0 18. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_18_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0xB0 17. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_17_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0xB0 16. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_16_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0xB0 15. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_15_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0xB0 14. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_14_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0xB0 13. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_13_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0xB0 12. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_12_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0xB0 11. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_11_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0xB0 10. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_10_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0xB0 9. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_9_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0xB0 8. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_8_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0xB0 7. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_7_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0xB0 6. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_6_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0xB0 5. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_5_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0xB0 4. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_4_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0xB0 3. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_3_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0xB0 2. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_2_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0xB0 1. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_1_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0xB0 0. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_0_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0xB4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_5,Status Clear Register 45" bitfld.long 0xB4 31. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_63_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_63" "0,1" newline bitfld.long 0xB4 30. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_62_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_62" "0,1" newline bitfld.long 0xB4 29. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_61_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_61" "0,1" newline bitfld.long 0xB4 28. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_60_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_60" "0,1" newline bitfld.long 0xB4 27. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_59_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_59" "0,1" newline bitfld.long 0xB4 26. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_58_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_58" "0,1" newline bitfld.long 0xB4 25. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_57_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_57" "0,1" newline bitfld.long 0xB4 24. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_56_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_56" "0,1" newline bitfld.long 0xB4 23. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_55_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_55" "0,1" newline bitfld.long 0xB4 22. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_54_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_54" "0,1" newline bitfld.long 0xB4 21. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_53_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_53" "0,1" newline bitfld.long 0xB4 20. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_52_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_52" "0,1" newline bitfld.long 0xB4 19. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_51_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_51" "0,1" newline bitfld.long 0xB4 18. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_50_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_50" "0,1" newline bitfld.long 0xB4 17. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_49_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_49" "0,1" newline bitfld.long 0xB4 16. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_48_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_48" "0,1" newline bitfld.long 0xB4 15. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_47_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_47" "0,1" newline bitfld.long 0xB4 14. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_46_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_46" "0,1" newline bitfld.long 0xB4 13. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_45_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_45" "0,1" newline bitfld.long 0xB4 12. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_44_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_44" "0,1" newline bitfld.long 0xB4 11. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_43_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_43" "0,1" newline bitfld.long 0xB4 10. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_42_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_42" "0,1" newline bitfld.long 0xB4 9. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_41_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_41" "0,1" newline bitfld.long 0xB4 8. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_40_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_40" "0,1" newline bitfld.long 0xB4 7. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_39_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_39" "0,1" newline bitfld.long 0xB4 6. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_38_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_38" "0,1" newline bitfld.long 0xB4 5. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_37_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_37" "0,1" newline bitfld.long 0xB4 4. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_36_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_36" "0,1" newline bitfld.long 0xB4 3. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_35_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_35" "0,1" newline bitfld.long 0xB4 2. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_34_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_34" "0,1" newline bitfld.long 0xB4 1. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_33_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_33" "0,1" newline bitfld.long 0xB4 0. "STATUS_LEVEL_VPAC_OUT_5_UTC0_COMPLETE_32_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_complete_32" "0,1" line.long 0xB8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_6,Status Clear Register 46" bitfld.long 0xB8 0. "STATUS_LEVEL_VPAC_OUT_5_UTC1_RSVD_UNUSED_CLR,Status write 1 to clear for level_vpac_out_5_en_utc1_rsvd_unused" "0,1" line.long 0xBC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_vpac_out_5_7,Status Clear Register 47" bitfld.long 0xBC 4. "STATUS_LEVEL_VPAC_OUT_5_CTM_PULSE_CLR,Status write 1 to clear for level_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0xBC 2. "STATUS_LEVEL_VPAC_OUT_5_UTC0_PROT_ERR_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0xBC 0. "STATUS_LEVEL_VPAC_OUT_5_UTC0_ERROR_CLR,Status write 1 to clear for level_vpac_out_5_en_utc0_error" "0,1" line.long 0xC0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_0,Status Clear Register 48" bitfld.long 0xC0 27. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0xC0 26. "STATUS_PULSE_VPAC_OUT_0_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xC0 25. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xC0 24. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xC0 23. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xC0 22. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC0 21. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC0 20. "STATUS_PULSE_VPAC_OUT_0_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xC0 19. "STATUS_PULSE_VPAC_OUT_0_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xC0 18. "STATUS_PULSE_VPAC_OUT_0_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xC0 17. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xC0 16. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xC0 15. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xC0 14. "STATUS_PULSE_VPAC_OUT_0_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xC0 13. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xC0 12. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xC0 11. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xC0 10. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xC0 9. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xC0 8. "STATUS_PULSE_VPAC_OUT_0_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xC0 7. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xC0 6. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xC0 5. "STATUS_PULSE_VPAC_OUT_0_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xC0 4. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xC0 3. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xC0 2. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xC0 1. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xC0 0. "STATUS_PULSE_VPAC_OUT_0_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_viss0_rawfe_cfg_err" "0,1" line.long 0xC4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_1,Status Clear Register 49" bitfld.long 0xC4 8. "STATUS_PULSE_VPAC_OUT_0_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xC4 7. "STATUS_PULSE_VPAC_OUT_0_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xC4 6. "STATUS_PULSE_VPAC_OUT_0_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xC4 5. "STATUS_PULSE_VPAC_OUT_0_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xC4 4. "STATUS_PULSE_VPAC_OUT_0_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xC4 3. "STATUS_PULSE_VPAC_OUT_0_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xC4 2. "STATUS_PULSE_VPAC_OUT_0_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xC4 1. "STATUS_PULSE_VPAC_OUT_0_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xC4 0. "STATUS_PULSE_VPAC_OUT_0_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xC8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_2,Status Clear Register 50" bitfld.long 0xC8 3. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xC8 2. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xC8 1. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_0_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xC8 0. "STATUS_PULSE_VPAC_OUT_0_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xCC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_3,Status Clear Register 51" bitfld.long 0xCC 26. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_0_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xCC 25. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_0_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xCC 24. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_0_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xCC 22. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_0_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xCC 20. "STATUS_PULSE_VPAC_OUT_0_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xCC 15. "STATUS_PULSE_VPAC_OUT_0_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_0_en_spare_dec_1" "0,1" newline bitfld.long 0xCC 14. "STATUS_PULSE_VPAC_OUT_0_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_spare_dec_0" "0,1" newline bitfld.long 0xCC 13. "STATUS_PULSE_VPAC_OUT_0_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_0_en_tdone_6" "0,1" newline bitfld.long 0xCC 12. "STATUS_PULSE_VPAC_OUT_0_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_0_en_tdone_5" "0,1" newline bitfld.long 0xCC 11. "STATUS_PULSE_VPAC_OUT_0_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_0_en_tdone_4" "0,1" newline bitfld.long 0xCC 9. "STATUS_PULSE_VPAC_OUT_0_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_0_en_tdone_2" "0,1" newline bitfld.long 0xCC 7. "STATUS_PULSE_VPAC_OUT_0_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_tdone_0" "0,1" newline bitfld.long 0xCC 6. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_6" "0,1" newline bitfld.long 0xCC 5. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_5" "0,1" newline bitfld.long 0xCC 4. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_4" "0,1" newline bitfld.long 0xCC 3. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_3" "0,1" newline bitfld.long 0xCC 2. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_2" "0,1" newline bitfld.long 0xCC 1. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_1" "0,1" newline bitfld.long 0xCC 0. "STATUS_PULSE_VPAC_OUT_0_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_pipe_done_0" "0,1" line.long 0xD0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_4,Status Clear Register 52" bitfld.long 0xD0 31. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_31" "0,1" newline bitfld.long 0xD0 30. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_30" "0,1" newline bitfld.long 0xD0 29. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_29" "0,1" newline bitfld.long 0xD0 28. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_28" "0,1" newline bitfld.long 0xD0 27. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_27" "0,1" newline bitfld.long 0xD0 26. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_26" "0,1" newline bitfld.long 0xD0 25. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_25" "0,1" newline bitfld.long 0xD0 24. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_24" "0,1" newline bitfld.long 0xD0 23. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_23" "0,1" newline bitfld.long 0xD0 22. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_22" "0,1" newline bitfld.long 0xD0 21. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_21" "0,1" newline bitfld.long 0xD0 20. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_20" "0,1" newline bitfld.long 0xD0 19. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_19" "0,1" newline bitfld.long 0xD0 18. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_18" "0,1" newline bitfld.long 0xD0 17. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_17" "0,1" newline bitfld.long 0xD0 16. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_16" "0,1" newline bitfld.long 0xD0 15. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_15" "0,1" newline bitfld.long 0xD0 14. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_14" "0,1" newline bitfld.long 0xD0 13. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_13" "0,1" newline bitfld.long 0xD0 12. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_12" "0,1" newline bitfld.long 0xD0 11. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_11" "0,1" newline bitfld.long 0xD0 10. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_10" "0,1" newline bitfld.long 0xD0 9. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_9" "0,1" newline bitfld.long 0xD0 8. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_8" "0,1" newline bitfld.long 0xD0 7. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_7" "0,1" newline bitfld.long 0xD0 6. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_6" "0,1" newline bitfld.long 0xD0 5. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_5" "0,1" newline bitfld.long 0xD0 4. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_4" "0,1" newline bitfld.long 0xD0 3. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_3" "0,1" newline bitfld.long 0xD0 2. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_2" "0,1" newline bitfld.long 0xD0 1. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_1" "0,1" newline bitfld.long 0xD0 0. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_0" "0,1" line.long 0xD4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_5,Status Clear Register 53" bitfld.long 0xD4 31. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_63" "0,1" newline bitfld.long 0xD4 30. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_62" "0,1" newline bitfld.long 0xD4 29. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_61" "0,1" newline bitfld.long 0xD4 28. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_60" "0,1" newline bitfld.long 0xD4 27. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_59" "0,1" newline bitfld.long 0xD4 26. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_58" "0,1" newline bitfld.long 0xD4 25. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_57" "0,1" newline bitfld.long 0xD4 24. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_56" "0,1" newline bitfld.long 0xD4 23. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_55" "0,1" newline bitfld.long 0xD4 22. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_54" "0,1" newline bitfld.long 0xD4 21. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_53" "0,1" newline bitfld.long 0xD4 20. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_52" "0,1" newline bitfld.long 0xD4 19. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_51" "0,1" newline bitfld.long 0xD4 18. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_50" "0,1" newline bitfld.long 0xD4 17. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_49" "0,1" newline bitfld.long 0xD4 16. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_48" "0,1" newline bitfld.long 0xD4 15. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_47" "0,1" newline bitfld.long 0xD4 14. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_46" "0,1" newline bitfld.long 0xD4 13. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_45" "0,1" newline bitfld.long 0xD4 12. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_44" "0,1" newline bitfld.long 0xD4 11. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_43" "0,1" newline bitfld.long 0xD4 10. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_42" "0,1" newline bitfld.long 0xD4 9. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_41" "0,1" newline bitfld.long 0xD4 8. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_40" "0,1" newline bitfld.long 0xD4 7. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_39" "0,1" newline bitfld.long 0xD4 6. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_38" "0,1" newline bitfld.long 0xD4 5. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_37" "0,1" newline bitfld.long 0xD4 4. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_36" "0,1" newline bitfld.long 0xD4 3. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_35" "0,1" newline bitfld.long 0xD4 2. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_34" "0,1" newline bitfld.long 0xD4 1. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_33" "0,1" newline bitfld.long 0xD4 0. "STATUS_PULSE_VPAC_OUT_0_UTC0_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_complete_32" "0,1" line.long 0xD8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_6,Status Clear Register 54" bitfld.long 0xD8 0. "STATUS_PULSE_VPAC_OUT_0_UTC1_RSVD_UNUSED_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc1_rsvd_unused" "0,1" line.long 0xDC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_0_7,Status Clear Register 55" bitfld.long 0xDC 4. "STATUS_PULSE_VPAC_OUT_0_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_0_en_ctm_pulse" "0,1" newline bitfld.long 0xDC 2. "STATUS_PULSE_VPAC_OUT_0_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_prot_err" "0,1" newline bitfld.long 0xDC 0. "STATUS_PULSE_VPAC_OUT_0_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_0_en_utc0_error" "0,1" line.long 0xE0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_0,Status Clear Register 56" bitfld.long 0xE0 27. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0xE0 26. "STATUS_PULSE_VPAC_OUT_1_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0xE0 25. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0xE0 24. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0xE0 23. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0xE0 22. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE0 21. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE0 20. "STATUS_PULSE_VPAC_OUT_1_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0xE0 19. "STATUS_PULSE_VPAC_OUT_1_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0xE0 18. "STATUS_PULSE_VPAC_OUT_1_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0xE0 17. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0xE0 16. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0xE0 15. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0xE0 14. "STATUS_PULSE_VPAC_OUT_1_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0xE0 13. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0xE0 12. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0xE0 11. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0xE0 10. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0xE0 9. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0xE0 8. "STATUS_PULSE_VPAC_OUT_1_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0xE0 7. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0xE0 6. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0xE0 5. "STATUS_PULSE_VPAC_OUT_1_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0xE0 4. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0xE0 3. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0xE0 2. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0xE0 1. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0xE0 0. "STATUS_PULSE_VPAC_OUT_1_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_viss0_rawfe_cfg_err" "0,1" line.long 0xE4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_1,Status Clear Register 57" bitfld.long 0xE4 8. "STATUS_PULSE_VPAC_OUT_1_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0xE4 7. "STATUS_PULSE_VPAC_OUT_1_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0xE4 6. "STATUS_PULSE_VPAC_OUT_1_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0xE4 5. "STATUS_PULSE_VPAC_OUT_1_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_int_szovf" "0,1" newline bitfld.long 0xE4 4. "STATUS_PULSE_VPAC_OUT_1_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0xE4 3. "STATUS_PULSE_VPAC_OUT_1_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0xE4 2. "STATUS_PULSE_VPAC_OUT_1_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0xE4 1. "STATUS_PULSE_VPAC_OUT_1_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0xE4 0. "STATUS_PULSE_VPAC_OUT_1_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0xE8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_2,Status Clear Register 58" bitfld.long 0xE8 3. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0xE8 2. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0xE8 1. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_1_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0xE8 0. "STATUS_PULSE_VPAC_OUT_1_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_msc_lse_fr_done_evt_0" "0,1" line.long 0xEC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_3,Status Clear Register 59" bitfld.long 0xEC 26. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_1_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0xEC 25. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_1_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0xEC 24. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_1_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0xEC 22. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_1_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0xEC 20. "STATUS_PULSE_VPAC_OUT_1_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0xEC 15. "STATUS_PULSE_VPAC_OUT_1_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_1_en_spare_dec_1" "0,1" newline bitfld.long 0xEC 14. "STATUS_PULSE_VPAC_OUT_1_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_spare_dec_0" "0,1" newline bitfld.long 0xEC 13. "STATUS_PULSE_VPAC_OUT_1_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_1_en_tdone_6" "0,1" newline bitfld.long 0xEC 12. "STATUS_PULSE_VPAC_OUT_1_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_1_en_tdone_5" "0,1" newline bitfld.long 0xEC 11. "STATUS_PULSE_VPAC_OUT_1_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_1_en_tdone_4" "0,1" newline bitfld.long 0xEC 9. "STATUS_PULSE_VPAC_OUT_1_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_1_en_tdone_2" "0,1" newline bitfld.long 0xEC 7. "STATUS_PULSE_VPAC_OUT_1_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_tdone_0" "0,1" newline bitfld.long 0xEC 6. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_6" "0,1" newline bitfld.long 0xEC 5. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_5" "0,1" newline bitfld.long 0xEC 4. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_4" "0,1" newline bitfld.long 0xEC 3. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_3" "0,1" newline bitfld.long 0xEC 2. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_2" "0,1" newline bitfld.long 0xEC 1. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_1" "0,1" newline bitfld.long 0xEC 0. "STATUS_PULSE_VPAC_OUT_1_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_pipe_done_0" "0,1" line.long 0xF0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_4,Status Clear Register 60" bitfld.long 0xF0 31. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_31" "0,1" newline bitfld.long 0xF0 30. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_30" "0,1" newline bitfld.long 0xF0 29. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_29" "0,1" newline bitfld.long 0xF0 28. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_28" "0,1" newline bitfld.long 0xF0 27. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_27" "0,1" newline bitfld.long 0xF0 26. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_26" "0,1" newline bitfld.long 0xF0 25. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_25" "0,1" newline bitfld.long 0xF0 24. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_24" "0,1" newline bitfld.long 0xF0 23. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_23" "0,1" newline bitfld.long 0xF0 22. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_22" "0,1" newline bitfld.long 0xF0 21. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_21" "0,1" newline bitfld.long 0xF0 20. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_20" "0,1" newline bitfld.long 0xF0 19. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_19" "0,1" newline bitfld.long 0xF0 18. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_18" "0,1" newline bitfld.long 0xF0 17. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_17" "0,1" newline bitfld.long 0xF0 16. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_16" "0,1" newline bitfld.long 0xF0 15. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_15" "0,1" newline bitfld.long 0xF0 14. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_14" "0,1" newline bitfld.long 0xF0 13. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_13" "0,1" newline bitfld.long 0xF0 12. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_12" "0,1" newline bitfld.long 0xF0 11. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_11" "0,1" newline bitfld.long 0xF0 10. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_10" "0,1" newline bitfld.long 0xF0 9. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_9" "0,1" newline bitfld.long 0xF0 8. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_8" "0,1" newline bitfld.long 0xF0 7. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_7" "0,1" newline bitfld.long 0xF0 6. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_6" "0,1" newline bitfld.long 0xF0 5. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_5" "0,1" newline bitfld.long 0xF0 4. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_4" "0,1" newline bitfld.long 0xF0 3. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_3" "0,1" newline bitfld.long 0xF0 2. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_2" "0,1" newline bitfld.long 0xF0 1. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_1" "0,1" newline bitfld.long 0xF0 0. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_0" "0,1" line.long 0xF4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_5,Status Clear Register 61" bitfld.long 0xF4 31. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_63" "0,1" newline bitfld.long 0xF4 30. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_62" "0,1" newline bitfld.long 0xF4 29. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_61" "0,1" newline bitfld.long 0xF4 28. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_60" "0,1" newline bitfld.long 0xF4 27. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_59" "0,1" newline bitfld.long 0xF4 26. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_58" "0,1" newline bitfld.long 0xF4 25. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_57" "0,1" newline bitfld.long 0xF4 24. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_56" "0,1" newline bitfld.long 0xF4 23. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_55" "0,1" newline bitfld.long 0xF4 22. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_54" "0,1" newline bitfld.long 0xF4 21. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_53" "0,1" newline bitfld.long 0xF4 20. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_52" "0,1" newline bitfld.long 0xF4 19. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_51" "0,1" newline bitfld.long 0xF4 18. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_50" "0,1" newline bitfld.long 0xF4 17. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_49" "0,1" newline bitfld.long 0xF4 16. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_48" "0,1" newline bitfld.long 0xF4 15. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_47" "0,1" newline bitfld.long 0xF4 14. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_46" "0,1" newline bitfld.long 0xF4 13. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_45" "0,1" newline bitfld.long 0xF4 12. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_44" "0,1" newline bitfld.long 0xF4 11. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_43" "0,1" newline bitfld.long 0xF4 10. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_42" "0,1" newline bitfld.long 0xF4 9. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_41" "0,1" newline bitfld.long 0xF4 8. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_40" "0,1" newline bitfld.long 0xF4 7. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_39" "0,1" newline bitfld.long 0xF4 6. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_38" "0,1" newline bitfld.long 0xF4 5. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_37" "0,1" newline bitfld.long 0xF4 4. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_36" "0,1" newline bitfld.long 0xF4 3. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_35" "0,1" newline bitfld.long 0xF4 2. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_34" "0,1" newline bitfld.long 0xF4 1. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_33" "0,1" newline bitfld.long 0xF4 0. "STATUS_PULSE_VPAC_OUT_1_UTC0_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_complete_32" "0,1" line.long 0xF8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_6,Status Clear Register 62" bitfld.long 0xF8 0. "STATUS_PULSE_VPAC_OUT_1_UTC1_RSVD_UNUSED_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc1_rsvd_unused" "0,1" line.long 0xFC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_1_7,Status Clear Register 63" bitfld.long 0xFC 4. "STATUS_PULSE_VPAC_OUT_1_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_1_en_ctm_pulse" "0,1" newline bitfld.long 0xFC 2. "STATUS_PULSE_VPAC_OUT_1_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_prot_err" "0,1" newline bitfld.long 0xFC 0. "STATUS_PULSE_VPAC_OUT_1_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_1_en_utc0_error" "0,1" line.long 0x100 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_0,Status Clear Register 64" bitfld.long 0x100 27. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x100 26. "STATUS_PULSE_VPAC_OUT_2_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x100 25. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x100 24. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x100 23. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x100 22. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x100 21. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x100 20. "STATUS_PULSE_VPAC_OUT_2_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x100 19. "STATUS_PULSE_VPAC_OUT_2_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x100 18. "STATUS_PULSE_VPAC_OUT_2_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x100 17. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x100 16. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x100 15. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x100 14. "STATUS_PULSE_VPAC_OUT_2_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x100 13. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x100 12. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x100 11. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x100 10. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x100 9. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x100 8. "STATUS_PULSE_VPAC_OUT_2_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x100 7. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x100 6. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x100 5. "STATUS_PULSE_VPAC_OUT_2_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x100 4. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x100 3. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x100 2. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x100 1. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x100 0. "STATUS_PULSE_VPAC_OUT_2_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_viss0_rawfe_cfg_err" "0,1" line.long 0x104 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_1,Status Clear Register 65" bitfld.long 0x104 8. "STATUS_PULSE_VPAC_OUT_2_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x104 7. "STATUS_PULSE_VPAC_OUT_2_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x104 6. "STATUS_PULSE_VPAC_OUT_2_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x104 5. "STATUS_PULSE_VPAC_OUT_2_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x104 4. "STATUS_PULSE_VPAC_OUT_2_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x104 3. "STATUS_PULSE_VPAC_OUT_2_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x104 2. "STATUS_PULSE_VPAC_OUT_2_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x104 1. "STATUS_PULSE_VPAC_OUT_2_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x104 0. "STATUS_PULSE_VPAC_OUT_2_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x108 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_2,Status Clear Register 66" bitfld.long 0x108 3. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x108 2. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x108 1. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_2_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x108 0. "STATUS_PULSE_VPAC_OUT_2_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x10C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_3,Status Clear Register 67" bitfld.long 0x10C 26. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_2_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x10C 25. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_2_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x10C 24. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_2_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x10C 22. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_2_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x10C 20. "STATUS_PULSE_VPAC_OUT_2_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x10C 15. "STATUS_PULSE_VPAC_OUT_2_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_2_en_spare_dec_1" "0,1" newline bitfld.long 0x10C 14. "STATUS_PULSE_VPAC_OUT_2_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_spare_dec_0" "0,1" newline bitfld.long 0x10C 13. "STATUS_PULSE_VPAC_OUT_2_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_2_en_tdone_6" "0,1" newline bitfld.long 0x10C 12. "STATUS_PULSE_VPAC_OUT_2_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_2_en_tdone_5" "0,1" newline bitfld.long 0x10C 11. "STATUS_PULSE_VPAC_OUT_2_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_2_en_tdone_4" "0,1" newline bitfld.long 0x10C 9. "STATUS_PULSE_VPAC_OUT_2_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_2_en_tdone_2" "0,1" newline bitfld.long 0x10C 7. "STATUS_PULSE_VPAC_OUT_2_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_tdone_0" "0,1" newline bitfld.long 0x10C 6. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_6" "0,1" newline bitfld.long 0x10C 5. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_5" "0,1" newline bitfld.long 0x10C 4. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_4" "0,1" newline bitfld.long 0x10C 3. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_3" "0,1" newline bitfld.long 0x10C 2. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_2" "0,1" newline bitfld.long 0x10C 1. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_1" "0,1" newline bitfld.long 0x10C 0. "STATUS_PULSE_VPAC_OUT_2_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_pipe_done_0" "0,1" line.long 0x110 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_4,Status Clear Register 68" bitfld.long 0x110 31. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_31" "0,1" newline bitfld.long 0x110 30. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_30" "0,1" newline bitfld.long 0x110 29. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_29" "0,1" newline bitfld.long 0x110 28. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_28" "0,1" newline bitfld.long 0x110 27. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_27" "0,1" newline bitfld.long 0x110 26. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_26" "0,1" newline bitfld.long 0x110 25. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_25" "0,1" newline bitfld.long 0x110 24. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_24" "0,1" newline bitfld.long 0x110 23. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_23" "0,1" newline bitfld.long 0x110 22. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_22" "0,1" newline bitfld.long 0x110 21. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_21" "0,1" newline bitfld.long 0x110 20. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_20" "0,1" newline bitfld.long 0x110 19. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_19" "0,1" newline bitfld.long 0x110 18. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_18" "0,1" newline bitfld.long 0x110 17. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_17" "0,1" newline bitfld.long 0x110 16. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_16" "0,1" newline bitfld.long 0x110 15. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_15" "0,1" newline bitfld.long 0x110 14. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_14" "0,1" newline bitfld.long 0x110 13. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_13" "0,1" newline bitfld.long 0x110 12. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_12" "0,1" newline bitfld.long 0x110 11. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_11" "0,1" newline bitfld.long 0x110 10. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_10" "0,1" newline bitfld.long 0x110 9. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_9" "0,1" newline bitfld.long 0x110 8. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_8" "0,1" newline bitfld.long 0x110 7. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_7" "0,1" newline bitfld.long 0x110 6. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_6" "0,1" newline bitfld.long 0x110 5. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_5" "0,1" newline bitfld.long 0x110 4. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_4" "0,1" newline bitfld.long 0x110 3. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_3" "0,1" newline bitfld.long 0x110 2. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_2" "0,1" newline bitfld.long 0x110 1. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_1" "0,1" newline bitfld.long 0x110 0. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_0" "0,1" line.long 0x114 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_5,Status Clear Register 69" bitfld.long 0x114 31. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_63" "0,1" newline bitfld.long 0x114 30. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_62" "0,1" newline bitfld.long 0x114 29. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_61" "0,1" newline bitfld.long 0x114 28. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_60" "0,1" newline bitfld.long 0x114 27. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_59" "0,1" newline bitfld.long 0x114 26. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_58" "0,1" newline bitfld.long 0x114 25. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_57" "0,1" newline bitfld.long 0x114 24. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_56" "0,1" newline bitfld.long 0x114 23. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_55" "0,1" newline bitfld.long 0x114 22. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_54" "0,1" newline bitfld.long 0x114 21. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_53" "0,1" newline bitfld.long 0x114 20. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_52" "0,1" newline bitfld.long 0x114 19. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_51" "0,1" newline bitfld.long 0x114 18. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_50" "0,1" newline bitfld.long 0x114 17. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_49" "0,1" newline bitfld.long 0x114 16. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_48" "0,1" newline bitfld.long 0x114 15. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_47" "0,1" newline bitfld.long 0x114 14. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_46" "0,1" newline bitfld.long 0x114 13. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_45" "0,1" newline bitfld.long 0x114 12. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_44" "0,1" newline bitfld.long 0x114 11. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_43" "0,1" newline bitfld.long 0x114 10. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_42" "0,1" newline bitfld.long 0x114 9. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_41" "0,1" newline bitfld.long 0x114 8. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_40" "0,1" newline bitfld.long 0x114 7. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_39" "0,1" newline bitfld.long 0x114 6. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_38" "0,1" newline bitfld.long 0x114 5. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_37" "0,1" newline bitfld.long 0x114 4. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_36" "0,1" newline bitfld.long 0x114 3. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_35" "0,1" newline bitfld.long 0x114 2. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_34" "0,1" newline bitfld.long 0x114 1. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_33" "0,1" newline bitfld.long 0x114 0. "STATUS_PULSE_VPAC_OUT_2_UTC0_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_complete_32" "0,1" line.long 0x118 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_6,Status Clear Register 70" bitfld.long 0x118 0. "STATUS_PULSE_VPAC_OUT_2_UTC1_RSVD_UNUSED_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc1_rsvd_unused" "0,1" line.long 0x11C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_2_7,Status Clear Register 71" bitfld.long 0x11C 4. "STATUS_PULSE_VPAC_OUT_2_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_2_en_ctm_pulse" "0,1" newline bitfld.long 0x11C 2. "STATUS_PULSE_VPAC_OUT_2_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_prot_err" "0,1" newline bitfld.long 0x11C 0. "STATUS_PULSE_VPAC_OUT_2_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_2_en_utc0_error" "0,1" line.long 0x120 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_0,Status Clear Register 72" bitfld.long 0x120 27. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x120 26. "STATUS_PULSE_VPAC_OUT_3_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x120 25. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x120 24. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x120 23. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x120 22. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x120 21. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x120 20. "STATUS_PULSE_VPAC_OUT_3_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x120 19. "STATUS_PULSE_VPAC_OUT_3_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x120 18. "STATUS_PULSE_VPAC_OUT_3_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x120 17. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x120 16. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x120 15. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x120 14. "STATUS_PULSE_VPAC_OUT_3_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x120 13. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x120 12. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x120 11. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x120 10. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x120 9. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x120 8. "STATUS_PULSE_VPAC_OUT_3_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x120 7. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x120 6. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x120 5. "STATUS_PULSE_VPAC_OUT_3_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x120 4. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x120 3. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x120 2. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x120 1. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x120 0. "STATUS_PULSE_VPAC_OUT_3_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_viss0_rawfe_cfg_err" "0,1" line.long 0x124 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_1,Status Clear Register 73" bitfld.long 0x124 8. "STATUS_PULSE_VPAC_OUT_3_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x124 7. "STATUS_PULSE_VPAC_OUT_3_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x124 6. "STATUS_PULSE_VPAC_OUT_3_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x124 5. "STATUS_PULSE_VPAC_OUT_3_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x124 4. "STATUS_PULSE_VPAC_OUT_3_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x124 3. "STATUS_PULSE_VPAC_OUT_3_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x124 2. "STATUS_PULSE_VPAC_OUT_3_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x124 1. "STATUS_PULSE_VPAC_OUT_3_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x124 0. "STATUS_PULSE_VPAC_OUT_3_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x128 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_2,Status Clear Register 74" bitfld.long 0x128 3. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x128 2. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x128 1. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_3_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x128 0. "STATUS_PULSE_VPAC_OUT_3_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x12C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_3,Status Clear Register 75" bitfld.long 0x12C 26. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_3_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x12C 25. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_3_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x12C 24. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_3_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x12C 22. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_3_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x12C 20. "STATUS_PULSE_VPAC_OUT_3_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x12C 15. "STATUS_PULSE_VPAC_OUT_3_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_3_en_spare_dec_1" "0,1" newline bitfld.long 0x12C 14. "STATUS_PULSE_VPAC_OUT_3_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_spare_dec_0" "0,1" newline bitfld.long 0x12C 13. "STATUS_PULSE_VPAC_OUT_3_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_3_en_tdone_6" "0,1" newline bitfld.long 0x12C 12. "STATUS_PULSE_VPAC_OUT_3_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_3_en_tdone_5" "0,1" newline bitfld.long 0x12C 11. "STATUS_PULSE_VPAC_OUT_3_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_3_en_tdone_4" "0,1" newline bitfld.long 0x12C 9. "STATUS_PULSE_VPAC_OUT_3_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_3_en_tdone_2" "0,1" newline bitfld.long 0x12C 7. "STATUS_PULSE_VPAC_OUT_3_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_tdone_0" "0,1" newline bitfld.long 0x12C 6. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_6" "0,1" newline bitfld.long 0x12C 5. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_5" "0,1" newline bitfld.long 0x12C 4. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_4" "0,1" newline bitfld.long 0x12C 3. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_3" "0,1" newline bitfld.long 0x12C 2. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_2" "0,1" newline bitfld.long 0x12C 1. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_1" "0,1" newline bitfld.long 0x12C 0. "STATUS_PULSE_VPAC_OUT_3_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_pipe_done_0" "0,1" line.long 0x130 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_4,Status Clear Register 76" bitfld.long 0x130 31. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_31" "0,1" newline bitfld.long 0x130 30. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_30" "0,1" newline bitfld.long 0x130 29. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_29" "0,1" newline bitfld.long 0x130 28. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_28" "0,1" newline bitfld.long 0x130 27. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_27" "0,1" newline bitfld.long 0x130 26. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_26" "0,1" newline bitfld.long 0x130 25. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_25" "0,1" newline bitfld.long 0x130 24. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_24" "0,1" newline bitfld.long 0x130 23. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_23" "0,1" newline bitfld.long 0x130 22. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_22" "0,1" newline bitfld.long 0x130 21. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_21" "0,1" newline bitfld.long 0x130 20. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_20" "0,1" newline bitfld.long 0x130 19. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_19" "0,1" newline bitfld.long 0x130 18. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_18" "0,1" newline bitfld.long 0x130 17. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_17" "0,1" newline bitfld.long 0x130 16. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_16" "0,1" newline bitfld.long 0x130 15. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_15" "0,1" newline bitfld.long 0x130 14. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_14" "0,1" newline bitfld.long 0x130 13. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_13" "0,1" newline bitfld.long 0x130 12. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_12" "0,1" newline bitfld.long 0x130 11. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_11" "0,1" newline bitfld.long 0x130 10. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_10" "0,1" newline bitfld.long 0x130 9. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_9" "0,1" newline bitfld.long 0x130 8. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_8" "0,1" newline bitfld.long 0x130 7. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_7" "0,1" newline bitfld.long 0x130 6. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_6" "0,1" newline bitfld.long 0x130 5. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_5" "0,1" newline bitfld.long 0x130 4. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_4" "0,1" newline bitfld.long 0x130 3. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_3" "0,1" newline bitfld.long 0x130 2. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_2" "0,1" newline bitfld.long 0x130 1. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_1" "0,1" newline bitfld.long 0x130 0. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_0" "0,1" line.long 0x134 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_5,Status Clear Register 77" bitfld.long 0x134 31. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_63" "0,1" newline bitfld.long 0x134 30. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_62" "0,1" newline bitfld.long 0x134 29. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_61" "0,1" newline bitfld.long 0x134 28. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_60" "0,1" newline bitfld.long 0x134 27. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_59" "0,1" newline bitfld.long 0x134 26. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_58" "0,1" newline bitfld.long 0x134 25. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_57" "0,1" newline bitfld.long 0x134 24. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_56" "0,1" newline bitfld.long 0x134 23. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_55" "0,1" newline bitfld.long 0x134 22. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_54" "0,1" newline bitfld.long 0x134 21. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_53" "0,1" newline bitfld.long 0x134 20. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_52" "0,1" newline bitfld.long 0x134 19. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_51" "0,1" newline bitfld.long 0x134 18. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_50" "0,1" newline bitfld.long 0x134 17. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_49" "0,1" newline bitfld.long 0x134 16. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_48" "0,1" newline bitfld.long 0x134 15. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_47" "0,1" newline bitfld.long 0x134 14. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_46" "0,1" newline bitfld.long 0x134 13. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_45" "0,1" newline bitfld.long 0x134 12. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_44" "0,1" newline bitfld.long 0x134 11. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_43" "0,1" newline bitfld.long 0x134 10. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_42" "0,1" newline bitfld.long 0x134 9. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_41" "0,1" newline bitfld.long 0x134 8. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_40" "0,1" newline bitfld.long 0x134 7. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_39" "0,1" newline bitfld.long 0x134 6. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_38" "0,1" newline bitfld.long 0x134 5. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_37" "0,1" newline bitfld.long 0x134 4. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_36" "0,1" newline bitfld.long 0x134 3. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_35" "0,1" newline bitfld.long 0x134 2. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_34" "0,1" newline bitfld.long 0x134 1. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_33" "0,1" newline bitfld.long 0x134 0. "STATUS_PULSE_VPAC_OUT_3_UTC0_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_complete_32" "0,1" line.long 0x138 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_6,Status Clear Register 78" bitfld.long 0x138 0. "STATUS_PULSE_VPAC_OUT_3_UTC1_RSVD_UNUSED_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc1_rsvd_unused" "0,1" line.long 0x13C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_3_7,Status Clear Register 79" bitfld.long 0x13C 4. "STATUS_PULSE_VPAC_OUT_3_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_3_en_ctm_pulse" "0,1" newline bitfld.long 0x13C 2. "STATUS_PULSE_VPAC_OUT_3_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_prot_err" "0,1" newline bitfld.long 0x13C 0. "STATUS_PULSE_VPAC_OUT_3_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_3_en_utc0_error" "0,1" line.long 0x140 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_0,Status Clear Register 80" bitfld.long 0x140 27. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x140 26. "STATUS_PULSE_VPAC_OUT_4_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x140 25. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x140 24. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x140 23. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x140 22. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x140 21. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x140 20. "STATUS_PULSE_VPAC_OUT_4_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x140 19. "STATUS_PULSE_VPAC_OUT_4_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x140 18. "STATUS_PULSE_VPAC_OUT_4_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x140 17. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x140 16. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x140 15. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x140 14. "STATUS_PULSE_VPAC_OUT_4_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x140 13. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x140 12. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x140 11. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x140 10. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x140 9. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x140 8. "STATUS_PULSE_VPAC_OUT_4_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x140 7. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x140 6. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x140 5. "STATUS_PULSE_VPAC_OUT_4_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x140 4. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x140 3. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x140 2. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x140 1. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x140 0. "STATUS_PULSE_VPAC_OUT_4_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_viss0_rawfe_cfg_err" "0,1" line.long 0x144 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_1,Status Clear Register 81" bitfld.long 0x144 8. "STATUS_PULSE_VPAC_OUT_4_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x144 7. "STATUS_PULSE_VPAC_OUT_4_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x144 6. "STATUS_PULSE_VPAC_OUT_4_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x144 5. "STATUS_PULSE_VPAC_OUT_4_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x144 4. "STATUS_PULSE_VPAC_OUT_4_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x144 3. "STATUS_PULSE_VPAC_OUT_4_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x144 2. "STATUS_PULSE_VPAC_OUT_4_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x144 1. "STATUS_PULSE_VPAC_OUT_4_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x144 0. "STATUS_PULSE_VPAC_OUT_4_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x148 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_2,Status Clear Register 82" bitfld.long 0x148 3. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x148 2. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x148 1. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_4_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x148 0. "STATUS_PULSE_VPAC_OUT_4_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x14C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_3,Status Clear Register 83" bitfld.long 0x14C 26. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_4_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x14C 25. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_4_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x14C 24. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_4_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x14C 22. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_4_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x14C 20. "STATUS_PULSE_VPAC_OUT_4_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x14C 15. "STATUS_PULSE_VPAC_OUT_4_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_4_en_spare_dec_1" "0,1" newline bitfld.long 0x14C 14. "STATUS_PULSE_VPAC_OUT_4_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_spare_dec_0" "0,1" newline bitfld.long 0x14C 13. "STATUS_PULSE_VPAC_OUT_4_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_4_en_tdone_6" "0,1" newline bitfld.long 0x14C 12. "STATUS_PULSE_VPAC_OUT_4_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_4_en_tdone_5" "0,1" newline bitfld.long 0x14C 11. "STATUS_PULSE_VPAC_OUT_4_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_4_en_tdone_4" "0,1" newline bitfld.long 0x14C 9. "STATUS_PULSE_VPAC_OUT_4_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_4_en_tdone_2" "0,1" newline bitfld.long 0x14C 7. "STATUS_PULSE_VPAC_OUT_4_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_tdone_0" "0,1" newline bitfld.long 0x14C 6. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_6" "0,1" newline bitfld.long 0x14C 5. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_5" "0,1" newline bitfld.long 0x14C 4. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_4" "0,1" newline bitfld.long 0x14C 3. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_3" "0,1" newline bitfld.long 0x14C 2. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_2" "0,1" newline bitfld.long 0x14C 1. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_1" "0,1" newline bitfld.long 0x14C 0. "STATUS_PULSE_VPAC_OUT_4_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_pipe_done_0" "0,1" line.long 0x150 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_4,Status Clear Register 84" bitfld.long 0x150 31. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_31" "0,1" newline bitfld.long 0x150 30. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_30" "0,1" newline bitfld.long 0x150 29. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_29" "0,1" newline bitfld.long 0x150 28. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_28" "0,1" newline bitfld.long 0x150 27. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_27" "0,1" newline bitfld.long 0x150 26. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_26" "0,1" newline bitfld.long 0x150 25. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_25" "0,1" newline bitfld.long 0x150 24. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_24" "0,1" newline bitfld.long 0x150 23. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_23" "0,1" newline bitfld.long 0x150 22. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_22" "0,1" newline bitfld.long 0x150 21. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_21" "0,1" newline bitfld.long 0x150 20. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_20" "0,1" newline bitfld.long 0x150 19. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_19" "0,1" newline bitfld.long 0x150 18. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_18" "0,1" newline bitfld.long 0x150 17. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_17" "0,1" newline bitfld.long 0x150 16. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_16" "0,1" newline bitfld.long 0x150 15. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_15" "0,1" newline bitfld.long 0x150 14. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_14" "0,1" newline bitfld.long 0x150 13. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_13" "0,1" newline bitfld.long 0x150 12. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_12" "0,1" newline bitfld.long 0x150 11. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_11" "0,1" newline bitfld.long 0x150 10. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_10" "0,1" newline bitfld.long 0x150 9. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_9" "0,1" newline bitfld.long 0x150 8. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_8" "0,1" newline bitfld.long 0x150 7. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_7" "0,1" newline bitfld.long 0x150 6. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_6" "0,1" newline bitfld.long 0x150 5. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_5" "0,1" newline bitfld.long 0x150 4. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_4" "0,1" newline bitfld.long 0x150 3. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_3" "0,1" newline bitfld.long 0x150 2. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_2" "0,1" newline bitfld.long 0x150 1. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_1" "0,1" newline bitfld.long 0x150 0. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_0" "0,1" line.long 0x154 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_5,Status Clear Register 85" bitfld.long 0x154 31. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_63" "0,1" newline bitfld.long 0x154 30. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_62" "0,1" newline bitfld.long 0x154 29. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_61" "0,1" newline bitfld.long 0x154 28. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_60" "0,1" newline bitfld.long 0x154 27. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_59" "0,1" newline bitfld.long 0x154 26. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_58" "0,1" newline bitfld.long 0x154 25. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_57" "0,1" newline bitfld.long 0x154 24. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_56" "0,1" newline bitfld.long 0x154 23. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_55" "0,1" newline bitfld.long 0x154 22. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_54" "0,1" newline bitfld.long 0x154 21. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_53" "0,1" newline bitfld.long 0x154 20. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_52" "0,1" newline bitfld.long 0x154 19. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_51" "0,1" newline bitfld.long 0x154 18. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_50" "0,1" newline bitfld.long 0x154 17. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_49" "0,1" newline bitfld.long 0x154 16. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_48" "0,1" newline bitfld.long 0x154 15. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_47" "0,1" newline bitfld.long 0x154 14. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_46" "0,1" newline bitfld.long 0x154 13. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_45" "0,1" newline bitfld.long 0x154 12. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_44" "0,1" newline bitfld.long 0x154 11. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_43" "0,1" newline bitfld.long 0x154 10. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_42" "0,1" newline bitfld.long 0x154 9. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_41" "0,1" newline bitfld.long 0x154 8. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_40" "0,1" newline bitfld.long 0x154 7. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_39" "0,1" newline bitfld.long 0x154 6. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_38" "0,1" newline bitfld.long 0x154 5. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_37" "0,1" newline bitfld.long 0x154 4. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_36" "0,1" newline bitfld.long 0x154 3. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_35" "0,1" newline bitfld.long 0x154 2. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_34" "0,1" newline bitfld.long 0x154 1. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_33" "0,1" newline bitfld.long 0x154 0. "STATUS_PULSE_VPAC_OUT_4_UTC0_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_complete_32" "0,1" line.long 0x158 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_6,Status Clear Register 86" bitfld.long 0x158 0. "STATUS_PULSE_VPAC_OUT_4_UTC1_RSVD_UNUSED_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc1_rsvd_unused" "0,1" line.long 0x15C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_4_7,Status Clear Register 87" bitfld.long 0x15C 4. "STATUS_PULSE_VPAC_OUT_4_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_4_en_ctm_pulse" "0,1" newline bitfld.long 0x15C 2. "STATUS_PULSE_VPAC_OUT_4_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_prot_err" "0,1" newline bitfld.long 0x15C 0. "STATUS_PULSE_VPAC_OUT_4_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_4_en_utc0_error" "0,1" line.long 0x160 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_0,Status Clear Register 88" bitfld.long 0x160 27. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_DPC_STATS_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_dpc_stats_read_err" "0,1" newline bitfld.long 0x160 26. "STATUS_PULSE_VPAC_OUT_5_VISS0_CR_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_cr_cfg_err" "0,1" newline bitfld.long 0x160 25. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_X_Y_POINTER_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_x_y_pointer" "0,1" newline bitfld.long 0x160 24. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_OUT_FR_START_EVT_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_lse_out_fr_start_evt" "0,1" newline bitfld.long 0x160 23. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_CAL_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_lse_cal_vp_err" "0,1" newline bitfld.long 0x160 22. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_lse_sl2_wr_err" "0,1" newline bitfld.long 0x160 21. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_lse_sl2_rd_err" "0,1" newline bitfld.long 0x160 20. "STATUS_PULSE_VPAC_OUT_5_VISS0_LSE_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_lse_fr_done_evt" "0,1" newline bitfld.long 0x160 19. "STATUS_PULSE_VPAC_OUT_5_VISS0_EE_SYNCOVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_ee_syncovf_err" "0,1" newline bitfld.long 0x160 18. "STATUS_PULSE_VPAC_OUT_5_VISS0_EE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_ee_cfg_err" "0,1" newline bitfld.long 0x160 17. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_HIST_READ_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_fcc_hist_read_err" "0,1" newline bitfld.long 0x160 16. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_OUTIF_OVF_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_fcc_outif_ovf_err" "0,1" newline bitfld.long 0x160 15. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCC_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_fcc_cfg_err" "0,1" newline bitfld.long 0x160 14. "STATUS_PULSE_VPAC_OUT_5_VISS0_FCFA_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_fcfa_cfg_err" "0,1" newline bitfld.long 0x160 13. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_VP_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_vp_err" "0,1" newline bitfld.long 0x160 12. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_VSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_vsync_err" "0,1" newline bitfld.long 0x160 11. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_HSYNC_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_hsync_err" "0,1" newline bitfld.long 0x160 10. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_FILT_DONE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_filt_done" "0,1" newline bitfld.long 0x160 9. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_FILT_START_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_filt_start" "0,1" newline bitfld.long 0x160 8. "STATUS_PULSE_VPAC_OUT_5_VISS0_GLBCE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_glbce_cfg_err" "0,1" newline bitfld.long 0x160 7. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_VBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_nsf4v_vblank_err" "0,1" newline bitfld.long 0x160 6. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_HBLANK_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_nsf4v_hblank_err" "0,1" newline bitfld.long 0x160 5. "STATUS_PULSE_VPAC_OUT_5_VISS0_NSF4V_LINEMEM_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_nsf4v_linemem_cfg_err" "0,1" newline bitfld.long 0x160 4. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_H3A_BUF_OVRFLOW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_h3a_buf_ovrflow_pulse" "0,1" newline bitfld.long 0x160 3. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_H3A_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_h3a_pulse" "0,1" newline bitfld.long 0x160 2. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_AF_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_af_pulse" "0,1" newline bitfld.long 0x160 1. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_AEW_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_aew_pulse" "0,1" newline bitfld.long 0x160 0. "STATUS_PULSE_VPAC_OUT_5_VISS0_RAWFE_CFG_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_viss0_rawfe_cfg_err" "0,1" line.long 0x164 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_1,Status Clear Register 89" bitfld.long 0x164 8. "STATUS_PULSE_VPAC_OUT_5_LDC0_VBUSM_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_vbusm_rd_err" "0,1" newline bitfld.long 0x164 7. "STATUS_PULSE_VPAC_OUT_5_LDC0_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_sl2_wr_err" "0,1" newline bitfld.long 0x164 6. "STATUS_PULSE_VPAC_OUT_5_LDC0_FR_DONE_EVT_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_fr_done_evt" "0,1" newline bitfld.long 0x164 5. "STATUS_PULSE_VPAC_OUT_5_LDC0_INT_SZOVF_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_int_szovf" "0,1" newline bitfld.long 0x164 4. "STATUS_PULSE_VPAC_OUT_5_LDC0_IFR_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_ifr_outofbound" "0,1" newline bitfld.long 0x164 3. "STATUS_PULSE_VPAC_OUT_5_LDC0_MESH_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_mesh_iblk_memovf" "0,1" newline bitfld.long 0x164 2. "STATUS_PULSE_VPAC_OUT_5_LDC0_PIX_IBLK_MEMOVF_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_pix_iblk_memovf" "0,1" newline bitfld.long 0x164 1. "STATUS_PULSE_VPAC_OUT_5_LDC0_MESH_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_mesh_iblk_outofbound" "0,1" newline bitfld.long 0x164 0. "STATUS_PULSE_VPAC_OUT_5_LDC0_PIX_IBLK_OUTOFBOUND_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ldc0_pix_iblk_outofbound" "0,1" line.long 0x168 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_2,Status Clear Register 90" bitfld.long 0x168 3. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_SL2_WR_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_msc_lse_sl2_wr_err" "0,1" newline bitfld.long 0x168 2. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_SL2_RD_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_msc_lse_sl2_rd_err" "0,1" newline bitfld.long 0x168 1. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_1_CLR,Status write 1 to clear for pulse_vpac_out_5_en_msc_lse_fr_done_evt_1" "0,1" newline bitfld.long 0x168 0. "STATUS_PULSE_VPAC_OUT_5_MSC_LSE_FR_DONE_EVT_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_msc_lse_fr_done_evt_0" "0,1" line.long 0x16C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_3,Status Clear Register 91" bitfld.long 0x16C 26. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_6_CLR,Status write 1 to clear for pulse_vpac_out_5_en_watchdogtimer_err_6" "0,1" newline bitfld.long 0x16C 25. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_5_CLR,Status write 1 to clear for pulse_vpac_out_5_en_watchdogtimer_err_5" "0,1" newline bitfld.long 0x16C 24. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_4_CLR,Status write 1 to clear for pulse_vpac_out_5_en_watchdogtimer_err_4" "0,1" newline bitfld.long 0x16C 22. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_2_CLR,Status write 1 to clear for pulse_vpac_out_5_en_watchdogtimer_err_2" "0,1" newline bitfld.long 0x16C 20. "STATUS_PULSE_VPAC_OUT_5_WATCHDOGTIMER_ERR_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_watchdogtimer_err_0" "0,1" newline bitfld.long 0x16C 15. "STATUS_PULSE_VPAC_OUT_5_SPARE_DEC_1_CLR,Status write 1 to clear for pulse_vpac_out_5_en_spare_dec_1" "0,1" newline bitfld.long 0x16C 14. "STATUS_PULSE_VPAC_OUT_5_SPARE_DEC_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_spare_dec_0" "0,1" newline bitfld.long 0x16C 13. "STATUS_PULSE_VPAC_OUT_5_TDONE_6_CLR,Status write 1 to clear for pulse_vpac_out_5_en_tdone_6" "0,1" newline bitfld.long 0x16C 12. "STATUS_PULSE_VPAC_OUT_5_TDONE_5_CLR,Status write 1 to clear for pulse_vpac_out_5_en_tdone_5" "0,1" newline bitfld.long 0x16C 11. "STATUS_PULSE_VPAC_OUT_5_TDONE_4_CLR,Status write 1 to clear for pulse_vpac_out_5_en_tdone_4" "0,1" newline bitfld.long 0x16C 9. "STATUS_PULSE_VPAC_OUT_5_TDONE_2_CLR,Status write 1 to clear for pulse_vpac_out_5_en_tdone_2" "0,1" newline bitfld.long 0x16C 7. "STATUS_PULSE_VPAC_OUT_5_TDONE_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_tdone_0" "0,1" newline bitfld.long 0x16C 6. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_6_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_6" "0,1" newline bitfld.long 0x16C 5. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_5_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_5" "0,1" newline bitfld.long 0x16C 4. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_4_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_4" "0,1" newline bitfld.long 0x16C 3. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_3_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_3" "0,1" newline bitfld.long 0x16C 2. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_2_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_2" "0,1" newline bitfld.long 0x16C 1. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_1_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_1" "0,1" newline bitfld.long 0x16C 0. "STATUS_PULSE_VPAC_OUT_5_PIPE_DONE_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_pipe_done_0" "0,1" line.long 0x170 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_4,Status Clear Register 92" bitfld.long 0x170 31. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_31_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_31" "0,1" newline bitfld.long 0x170 30. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_30_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_30" "0,1" newline bitfld.long 0x170 29. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_29_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_29" "0,1" newline bitfld.long 0x170 28. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_28_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_28" "0,1" newline bitfld.long 0x170 27. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_27_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_27" "0,1" newline bitfld.long 0x170 26. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_26_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_26" "0,1" newline bitfld.long 0x170 25. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_25_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_25" "0,1" newline bitfld.long 0x170 24. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_24_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_24" "0,1" newline bitfld.long 0x170 23. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_23_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_23" "0,1" newline bitfld.long 0x170 22. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_22_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_22" "0,1" newline bitfld.long 0x170 21. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_21_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_21" "0,1" newline bitfld.long 0x170 20. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_20_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_20" "0,1" newline bitfld.long 0x170 19. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_19_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_19" "0,1" newline bitfld.long 0x170 18. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_18_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_18" "0,1" newline bitfld.long 0x170 17. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_17_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_17" "0,1" newline bitfld.long 0x170 16. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_16_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_16" "0,1" newline bitfld.long 0x170 15. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_15_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_15" "0,1" newline bitfld.long 0x170 14. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_14_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_14" "0,1" newline bitfld.long 0x170 13. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_13_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_13" "0,1" newline bitfld.long 0x170 12. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_12_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_12" "0,1" newline bitfld.long 0x170 11. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_11_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_11" "0,1" newline bitfld.long 0x170 10. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_10_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_10" "0,1" newline bitfld.long 0x170 9. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_9_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_9" "0,1" newline bitfld.long 0x170 8. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_8_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_8" "0,1" newline bitfld.long 0x170 7. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_7_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_7" "0,1" newline bitfld.long 0x170 6. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_6_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_6" "0,1" newline bitfld.long 0x170 5. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_5_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_5" "0,1" newline bitfld.long 0x170 4. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_4_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_4" "0,1" newline bitfld.long 0x170 3. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_3_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_3" "0,1" newline bitfld.long 0x170 2. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_2_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_2" "0,1" newline bitfld.long 0x170 1. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_1_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_1" "0,1" newline bitfld.long 0x170 0. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_0_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_0" "0,1" line.long 0x174 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_5,Status Clear Register 93" bitfld.long 0x174 31. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_63_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_63" "0,1" newline bitfld.long 0x174 30. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_62_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_62" "0,1" newline bitfld.long 0x174 29. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_61_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_61" "0,1" newline bitfld.long 0x174 28. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_60_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_60" "0,1" newline bitfld.long 0x174 27. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_59_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_59" "0,1" newline bitfld.long 0x174 26. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_58_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_58" "0,1" newline bitfld.long 0x174 25. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_57_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_57" "0,1" newline bitfld.long 0x174 24. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_56_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_56" "0,1" newline bitfld.long 0x174 23. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_55_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_55" "0,1" newline bitfld.long 0x174 22. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_54_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_54" "0,1" newline bitfld.long 0x174 21. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_53_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_53" "0,1" newline bitfld.long 0x174 20. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_52_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_52" "0,1" newline bitfld.long 0x174 19. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_51_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_51" "0,1" newline bitfld.long 0x174 18. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_50_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_50" "0,1" newline bitfld.long 0x174 17. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_49_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_49" "0,1" newline bitfld.long 0x174 16. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_48_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_48" "0,1" newline bitfld.long 0x174 15. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_47_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_47" "0,1" newline bitfld.long 0x174 14. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_46_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_46" "0,1" newline bitfld.long 0x174 13. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_45_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_45" "0,1" newline bitfld.long 0x174 12. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_44_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_44" "0,1" newline bitfld.long 0x174 11. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_43_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_43" "0,1" newline bitfld.long 0x174 10. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_42_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_42" "0,1" newline bitfld.long 0x174 9. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_41_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_41" "0,1" newline bitfld.long 0x174 8. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_40_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_40" "0,1" newline bitfld.long 0x174 7. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_39_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_39" "0,1" newline bitfld.long 0x174 6. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_38_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_38" "0,1" newline bitfld.long 0x174 5. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_37_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_37" "0,1" newline bitfld.long 0x174 4. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_36_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_36" "0,1" newline bitfld.long 0x174 3. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_35_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_35" "0,1" newline bitfld.long 0x174 2. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_34_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_34" "0,1" newline bitfld.long 0x174 1. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_33_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_33" "0,1" newline bitfld.long 0x174 0. "STATUS_PULSE_VPAC_OUT_5_UTC0_COMPLETE_32_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_complete_32" "0,1" line.long 0x178 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_6,Status Clear Register 94" bitfld.long 0x178 0. "STATUS_PULSE_VPAC_OUT_5_UTC1_RSVD_UNUSED_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc1_rsvd_unused" "0,1" line.long 0x17C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_vpac_out_5_7,Status Clear Register 95" bitfld.long 0x17C 4. "STATUS_PULSE_VPAC_OUT_5_CTM_PULSE_CLR,Status write 1 to clear for pulse_vpac_out_5_en_ctm_pulse" "0,1" newline bitfld.long 0x17C 2. "STATUS_PULSE_VPAC_OUT_5_UTC0_PROT_ERR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_prot_err" "0,1" newline bitfld.long 0x17C 0. "STATUS_PULSE_VPAC_OUT_5_UTC0_ERROR_CLR,Status write 1 to clear for pulse_vpac_out_5_en_utc0_error" "0,1" rgroup.long 0xA80++0x2F line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level_vpac_out_0,Interrupt Vector for level_vpac_out_0" hexmask.long 0x0 0.--31. 1. "INTR_VECTOR_LEVEL_VPAC_OUT_0,Interrupt Vector" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level_vpac_out_1,Interrupt Vector for level_vpac_out_1" hexmask.long 0x4 0.--31. 1. "INTR_VECTOR_LEVEL_VPAC_OUT_1,Interrupt Vector" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level_vpac_out_2,Interrupt Vector for level_vpac_out_2" hexmask.long 0x8 0.--31. 1. "INTR_VECTOR_LEVEL_VPAC_OUT_2,Interrupt Vector" line.long 0xC "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level_vpac_out_3,Interrupt Vector for level_vpac_out_3" hexmask.long 0xC 0.--31. 1. "INTR_VECTOR_LEVEL_VPAC_OUT_3,Interrupt Vector" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level_vpac_out_4,Interrupt Vector for level_vpac_out_4" hexmask.long 0x10 0.--31. 1. "INTR_VECTOR_LEVEL_VPAC_OUT_4,Interrupt Vector" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level_vpac_out_5,Interrupt Vector for level_vpac_out_5" hexmask.long 0x14 0.--31. 1. "INTR_VECTOR_LEVEL_VPAC_OUT_5,Interrupt Vector" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse_vpac_out_0,Interrupt Vector for pulse_vpac_out_0" hexmask.long 0x18 0.--31. 1. "INTR_VECTOR_PULSE_VPAC_OUT_0,Interrupt Vector" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse_vpac_out_1,Interrupt Vector for pulse_vpac_out_1" hexmask.long 0x1C 0.--31. 1. "INTR_VECTOR_PULSE_VPAC_OUT_1,Interrupt Vector" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse_vpac_out_2,Interrupt Vector for pulse_vpac_out_2" hexmask.long 0x20 0.--31. 1. "INTR_VECTOR_PULSE_VPAC_OUT_2,Interrupt Vector" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse_vpac_out_3,Interrupt Vector for pulse_vpac_out_3" hexmask.long 0x24 0.--31. 1. "INTR_VECTOR_PULSE_VPAC_OUT_3,Interrupt Vector" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse_vpac_out_4,Interrupt Vector for pulse_vpac_out_4" hexmask.long 0x28 0.--31. 1. "INTR_VECTOR_PULSE_VPAC_OUT_4,Interrupt Vector" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse_vpac_out_5,Interrupt Vector for pulse_vpac_out_5" hexmask.long 0x2C 0.--31. 1. "INTR_VECTOR_PULSE_VPAC_OUT_5,Interrupt Vector" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_CTSET2_WRAP_CFG_CTSET2_CFG" base ad:0x2C002000 rgroup.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTSETID,CTSET identification register" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old Scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,The value 10b designates this as Processor Business Unit IP" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNCTION,Function : Indicates a Debug IP (0x2nn) and 0x80 is the identifier for CT-SET" hexmask.long.byte 0x0 11.--15. 1. "RTL_VERSION,This field changes on bug fix and resets to '0' when either Minor Revision or Major Revision field changes" newline bitfld.long 0x0 8.--10. "MAJOR_REV,Major Revision. This field changes when there is a major feature change." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. 0 if non-custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR_REV,Minor Revision. This field changes when features are scaled up or down" group.long 0x10++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTSETSYSCFG,CTSET system configuration register" hexmask.long 0x0 4.--31. 1. "RESERVED1,Reserved returns 0" bitfld.long 0x0 2.--3. "IDLEMODE,Sets the Idle Mode for CTSET (0=Force Idle 1=No Idle 2=Smart Idle 3= Smart Idle wakeup)" "0: Force Idle,1: No Idle,2: Smart Idle,3: Smart Idle wakeup" newline rbitfld.long 0x0 1. "RESERVED,Reserved returns 0" "0,1" bitfld.long 0x0 0. "SOFTRESET,This will reset entire CTSET except the registers and the CFG interface. This bit is automatically cleared by hardware. Reads always return 0" "0,1" rgroup.long 0x14++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_SETSTR,CTSET status register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED1,Reserved returns 0" bitfld.long 0x0 8. "HWFIFOEMPTY,System Event Trace FIFO status 1 is empty 0 means captured data not yet exported" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved returns 0" bitfld.long 0x0 0. "RESETDONE,Reset status 0 means reset ongoing 1 indicates completed" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_DBGTIMELOW,The 32 low order bits of the debug time value supplied on the time input interface" hexmask.long 0x4 0.--31. 1. "DBGTIME,debug time" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_DBGTIMEHI,The 32 high order bits of the debug time value supplied on the time input interface" hexmask.long 0x8 0.--31. 1. "DBGTIME,debug time" group.long 0x24++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTSETCFG,The 32 low order bits of the debug time value supplied on the time input interface The 32 high order bits of the debug time value supplied on the time input interface. Reading DBGTIMEHI latches.." hexmask.long.byte 0x0 28.--31. 1. "CLAIM,Claim control and status. To program any bits other than 31 : 28 CTSET ownership must be claimed using bits 31 : 28." hexmask.long.tbyte 0x0 8.--27. 1. "RESERVED2,Reserved returns 0" newline bitfld.long 0x0 7. "SYSEVENTCAPTEN,When 1 the System event capture is enabled" "0,1" rbitfld.long 0x0 5.--6. "RESERVED1,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x0 4. "EVENTLEVEL,0 enables low level event detection 1 enables high level event detection" "0,1" bitfld.long 0x0 3. "MSGMODE,Message generated based on event detection 0 is sampling window 1 is event detection" "0,1" newline bitfld.long 0x0 2. "STOPCAPT,Stop capturing system events from external trigger detection" "0,1" bitfld.long 0x0 1. "STARTCAPT,Start capturing system events from external trigger detection" "0,1" newline rbitfld.long 0x0 0. "RESERVED,Reserved returns 0" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_SETSPLREG,System Event Sampling Window register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x4 0.--7. 1. "WINDOWSIZE,System events sampling window size expressed as CTSET cycles" group.long 0x30++0x23 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL1,System event detection enable register 1" bitfld.long 0x0 31. "EVENT32DETEN,Event(32) Detection Enable" "0,1" bitfld.long 0x0 30. "EVENT31DETEN,Event(31) Detection Enable" "0,1" newline bitfld.long 0x0 29. "EVENT30DETEN,Event(30) Detection Enable" "0,1" bitfld.long 0x0 28. "EVENT29DETEN,Event(29) Detection Enable" "0,1" newline bitfld.long 0x0 27. "EVENT28DETEN,Event(28) Detection Enable" "0,1" bitfld.long 0x0 26. "EVENT27DETEN,Event(27) Detection Enable" "0,1" newline bitfld.long 0x0 25. "EVENT26DETEN,Event(26) Detection Enable" "0,1" bitfld.long 0x0 24. "EVENT25DETEN,Event(25) Detection Enable" "0,1" newline bitfld.long 0x0 23. "EVENT24DETEN,Event(24) Detection Enable" "0,1" bitfld.long 0x0 22. "EVENT23DETEN,Event(23) Detection Enable" "0,1" newline bitfld.long 0x0 21. "EVENT22DETEN,Event(22) Detection Enable" "0,1" bitfld.long 0x0 20. "EVENT21DETEN,Event(21) Detection Enable" "0,1" newline bitfld.long 0x0 19. "EVENT20DETEN,Event(20) Detection Enable" "0,1" bitfld.long 0x0 18. "EVENT19DETEN,Event(19) Detection Enable" "0,1" newline bitfld.long 0x0 17. "EVENT18DETEN,Event(18) Detection Enable" "0,1" bitfld.long 0x0 16. "EVENT17DETEN,Event(17) Detection Enable" "0,1" newline bitfld.long 0x0 15. "EVENT16DETEN,Event(16) Detection Enable" "0,1" bitfld.long 0x0 14. "EVENT15DETEN,Event(15) Detection Enable" "0,1" newline bitfld.long 0x0 13. "EVENT14DETEN,Event(14) Detection Enable" "0,1" bitfld.long 0x0 12. "EVENT13DETEN,Event(13) Detection Enable" "0,1" newline bitfld.long 0x0 11. "EVENT12DETEN,Event(12) Detection Enable" "0,1" bitfld.long 0x0 10. "EVENT11DETEN,Event(11) Detection Enable" "0,1" newline bitfld.long 0x0 9. "EVENT10DETEN,Event(10) Detection Enable" "0,1" bitfld.long 0x0 8. "EVENT9DETEN,Event(9) Detection Enable" "0,1" newline bitfld.long 0x0 7. "EVENT8DETEN,Event(8) Detection Enable" "0,1" bitfld.long 0x0 6. "EVENT7DETEN,Event(7) Detection Enable" "0,1" newline bitfld.long 0x0 5. "EVENT6DETEN,Event(6) Detection Enable" "0,1" bitfld.long 0x0 4. "EVENT5DETEN,Event(5) Detection Enable" "0,1" newline bitfld.long 0x0 3. "EVENT4DETEN,Event(4) Detection Enable" "0,1" bitfld.long 0x0 2. "EVENT3DETEN,Event(3) Detection Enable" "0,1" newline bitfld.long 0x0 1. "EVENT2DETEN,Event(2) Detection Enable" "0,1" bitfld.long 0x0 0. "EVENT1DETEN,Event(1) Detection Enable" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL2,System event detection enable register 2 (if number of events > 32)" bitfld.long 0x4 31. "EVENT64DETEN,Event(64) Detection Enable" "0,1" bitfld.long 0x4 30. "EVENT63DETEN,Event(63) Detection Enable" "0,1" newline bitfld.long 0x4 29. "EVENT62DETEN,Event(62) Detection Enable" "0,1" bitfld.long 0x4 28. "EVENT61DETEN,Event(61) Detection Enable" "0,1" newline bitfld.long 0x4 27. "EVENT60DETEN,Event(60) Detection Enable" "0,1" bitfld.long 0x4 26. "EVENT59DETEN,Event(59) Detection Enable" "0,1" newline bitfld.long 0x4 25. "EVENT58DETEN,Event(58) Detection Enable" "0,1" bitfld.long 0x4 24. "EVENT57DETEN,Event(57) Detection Enable" "0,1" newline bitfld.long 0x4 23. "EVENT56DETEN,Event(56) Detection Enable" "0,1" bitfld.long 0x4 22. "EVENT55DETEN,Event(55) Detection Enable" "0,1" newline bitfld.long 0x4 21. "EVENT54DETEN,Event(54) Detection Enable" "0,1" bitfld.long 0x4 20. "EVENT53DETEN,Event(53) Detection Enable" "0,1" newline bitfld.long 0x4 19. "EVENT52DETEN,Event(52) Detection Enable" "0,1" bitfld.long 0x4 18. "EVENT51DETEN,Event(51) Detection Enable" "0,1" newline bitfld.long 0x4 17. "EVENT50DETEN,Event(50) Detection Enable" "0,1" bitfld.long 0x4 16. "EVENT49DETEN,Event(49) Detection Enable" "0,1" newline bitfld.long 0x4 15. "EVENT48DETEN,Event(48) Detection Enable" "0,1" bitfld.long 0x4 14. "EVENT47DETEN,Event(47) Detection Enable" "0,1" newline bitfld.long 0x4 13. "EVENT46DETEN,Event(46) Detection Enable" "0,1" bitfld.long 0x4 12. "EVENT45DETEN,Event(45) Detection Enable" "0,1" newline bitfld.long 0x4 11. "EVENT44DETEN,Event(44) Detection Enable" "0,1" bitfld.long 0x4 10. "EVENT43DETEN,Event(43) Detection Enable" "0,1" newline bitfld.long 0x4 9. "EVENT42DETEN,Event(42) Detection Enable" "0,1" bitfld.long 0x4 8. "EVENT41DETEN,Event(41) Detection Enable" "0,1" newline bitfld.long 0x4 7. "EVENT40DETEN,Event(40) Detection Enable" "0,1" bitfld.long 0x4 6. "EVENT39DETEN,Event(39) Detection Enable" "0,1" newline bitfld.long 0x4 5. "EVENT38DETEN,Event(38) Detection Enable" "0,1" bitfld.long 0x4 4. "EVENT37DETEN,Event(37) Detection Enable" "0,1" newline bitfld.long 0x4 3. "EVENT36DETEN,Event(36) Detection Enable" "0,1" bitfld.long 0x4 2. "EVENT35DETEN,Event(35) Detection Enable" "0,1" newline bitfld.long 0x4 1. "EVENT34DETEN,Event(34) Detection Enable" "0,1" bitfld.long 0x4 0. "EVENT33DETEN,Event(33) Detection Enable" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL3,System event detection enable register 3 (if number of events > 64)" bitfld.long 0x8 31. "EVENT96DETEN,Event(96) Detection Enable" "0,1" bitfld.long 0x8 30. "EVENT95DETEN,Event(95) Detection Enable" "0,1" newline bitfld.long 0x8 29. "EVENT94DETEN,Event(94) Detection Enable" "0,1" bitfld.long 0x8 28. "EVENT93DETEN,Event(93) Detection Enable" "0,1" newline bitfld.long 0x8 27. "EVENT92DETEN,Event(92) Detection Enable" "0,1" bitfld.long 0x8 26. "EVENT91DETEN,Event(91) Detection Enable" "0,1" newline bitfld.long 0x8 25. "EVENT90DETEN,Event(90) Detection Enable" "0,1" bitfld.long 0x8 24. "EVENT89DETEN,Event(89) Detection Enable" "0,1" newline bitfld.long 0x8 23. "EVENT88DETEN,Event(88) Detection Enable" "0,1" bitfld.long 0x8 22. "EVENT87DETEN,Event(87) Detection Enable" "0,1" newline bitfld.long 0x8 21. "EVENT86DETEN,Event(86) Detection Enable" "0,1" bitfld.long 0x8 20. "EVENT85DETEN,Event(85) Detection Enable" "0,1" newline bitfld.long 0x8 19. "EVENT84DETEN,Event(84) Detection Enable" "0,1" bitfld.long 0x8 18. "EVENT83DETEN,Event(83) Detection Enable" "0,1" newline bitfld.long 0x8 17. "EVENT82DETEN,Event(82) Detection Enable" "0,1" bitfld.long 0x8 16. "EVENT81DETEN,Event(81) Detection Enable" "0,1" newline bitfld.long 0x8 15. "EVENT80DETEN,Event(80) Detection Enable" "0,1" bitfld.long 0x8 14. "EVENT79DETEN,Event(79) Detection Enable" "0,1" newline bitfld.long 0x8 13. "EVENT78DETEN,Event(78) Detection Enable" "0,1" bitfld.long 0x8 12. "EVENT77DETEN,Event(77) Detection Enable" "0,1" newline bitfld.long 0x8 11. "EVENT76DETEN,Event(76) Detection Enable" "0,1" bitfld.long 0x8 10. "EVENT75DETEN,Event(75) Detection Enable" "0,1" newline bitfld.long 0x8 9. "EVENT74DETEN,Event(74) Detection Enable" "0,1" bitfld.long 0x8 8. "EVENT73DETEN,Event(73) Detection Enable" "0,1" newline bitfld.long 0x8 7. "EVENT72DETEN,Event(72) Detection Enable" "0,1" bitfld.long 0x8 6. "EVENT71DETEN,Event(71) Detection Enable" "0,1" newline bitfld.long 0x8 5. "EVENT70DETEN,Event(70) Detection Enable" "0,1" bitfld.long 0x8 4. "EVENT69DETEN,Event(69) Detection Enable" "0,1" newline bitfld.long 0x8 3. "EVENT68DETEN,Event(68) Detection Enable" "0,1" bitfld.long 0x8 2. "EVENT67DETEN,Event(67) Detection Enable" "0,1" newline bitfld.long 0x8 1. "EVENT66DETEN,Event(66) Detection Enable" "0,1" bitfld.long 0x8 0. "EVENT65DETEN,Event(65) Detection Enable" "0,1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL4,System event detection enable register 4 (if number of events > 96)" bitfld.long 0xC 31. "EVENT128DETEN,Event(128) Detection Enable" "0,1" bitfld.long 0xC 30. "EVENT127DETEN,Event(127) Detection Enable" "0,1" newline bitfld.long 0xC 29. "EVENT126DETEN,Event(126) Detection Enable" "0,1" bitfld.long 0xC 28. "EVENT125DETEN,Event(125) Detection Enable" "0,1" newline bitfld.long 0xC 27. "EVENT124DETEN,Event(124) Detection Enable" "0,1" bitfld.long 0xC 26. "EVENT123DETEN,Event(123) Detection Enable" "0,1" newline bitfld.long 0xC 25. "EVENT122DETEN,Event(122) Detection Enable" "0,1" bitfld.long 0xC 24. "EVENT121DETEN,Event(121) Detection Enable" "0,1" newline bitfld.long 0xC 23. "EVENT120DETEN,Event(120) Detection Enable" "0,1" bitfld.long 0xC 22. "EVENT119DETEN,Event(119) Detection Enable" "0,1" newline bitfld.long 0xC 21. "EVENT118DETEN,Event(118) Detection Enable" "0,1" bitfld.long 0xC 20. "EVENT117DETEN,Event(117) Detection Enable" "0,1" newline bitfld.long 0xC 19. "EVENT116DETEN,Event(116) Detection Enable" "0,1" bitfld.long 0xC 18. "EVENT115DETEN,Event(115) Detection Enable" "0,1" newline bitfld.long 0xC 17. "EVENT114DETEN,Event(114) Detection Enable" "0,1" bitfld.long 0xC 16. "EVENT113DETEN,Event(113) Detection Enable" "0,1" newline bitfld.long 0xC 15. "EVENT112DETEN,Event(112) Detection Enable" "0,1" bitfld.long 0xC 14. "EVENT111DETEN,Event(111) Detection Enable" "0,1" newline bitfld.long 0xC 13. "EVENT110DETEN,Event(110) Detection Enable" "0,1" bitfld.long 0xC 12. "EVENT109DETEN,Event(109) Detection Enable" "0,1" newline bitfld.long 0xC 11. "EVENT108DETEN,Event(108) Detection Enable" "0,1" bitfld.long 0xC 10. "EVENT107DETEN,Event(107) Detection Enable" "0,1" newline bitfld.long 0xC 9. "EVENT106DETEN,Event(106) Detection Enable" "0,1" bitfld.long 0xC 8. "EVENT105DETEN,Event(105) Detection Enable" "0,1" newline bitfld.long 0xC 7. "EVENT104DETEN,Event(104) Detection Enable" "0,1" bitfld.long 0xC 6. "EVENT103DETEN,Event(103) Detection Enable" "0,1" newline bitfld.long 0xC 5. "EVENT102DETEN,Event(102) Detection Enable" "0,1" bitfld.long 0xC 4. "EVENT101DETEN,Event(101) Detection Enable" "0,1" newline bitfld.long 0xC 3. "EVENT100DETEN,Event(100) Detection Enable" "0,1" bitfld.long 0xC 2. "EVENT99DETEN,Event(99) Detection Enable" "0,1" newline bitfld.long 0xC 1. "EVENT98DETEN,Event(98) Detection Enable" "0,1" bitfld.long 0xC 0. "EVENT97DETEN,Event(97) Detection Enable" "0,1" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL5,System event detection enable register 5 (if number of events > 128)" bitfld.long 0x10 31. "EVENT160DETEN,Event(160) Detection Enable" "0,1" bitfld.long 0x10 30. "EVENT159DETEN,Event(159) Detection Enable" "0,1" newline bitfld.long 0x10 29. "EVENT158DETEN,Event(158) Detection Enable" "0,1" bitfld.long 0x10 28. "EVENT157DETEN,Event(157) Detection Enable" "0,1" newline bitfld.long 0x10 27. "EVENT156DETEN,Event(156) Detection Enable" "0,1" bitfld.long 0x10 26. "EVENT155DETEN,Event(155) Detection Enable" "0,1" newline bitfld.long 0x10 25. "EVENT154DETEN,Event(154) Detection Enable" "0,1" bitfld.long 0x10 24. "EVENT153DETEN,Event(153) Detection Enable" "0,1" newline bitfld.long 0x10 23. "EVENT152DETEN,Event(152) Detection Enable" "0,1" bitfld.long 0x10 22. "EVENT151DETEN,Event(151) Detection Enable" "0,1" newline bitfld.long 0x10 21. "EVENT150DETEN,Event(150) Detection Enable" "0,1" bitfld.long 0x10 20. "EVENT149DETEN,Event(149) Detection Enable" "0,1" newline bitfld.long 0x10 19. "EVENT148DETEN,Event(148) Detection Enable" "0,1" bitfld.long 0x10 18. "EVENT147DETEN,Event(147) Detection Enable" "0,1" newline bitfld.long 0x10 17. "EVENT1468DETEN,Event(146) Detection Enable" "0,1" bitfld.long 0x10 16. "EVENT145DETEN,Event(145) Detection Enable" "0,1" newline bitfld.long 0x10 15. "EVENT144DETEN,Event(144) Detection Enable" "0,1" bitfld.long 0x10 14. "EVENT143DETEN,Event(143) Detection Enable" "0,1" newline bitfld.long 0x10 13. "EVENT142DETEN,Event(142) Detection Enable" "0,1" bitfld.long 0x10 12. "EVENT141DETEN,Event(141) Detection Enable" "0,1" newline bitfld.long 0x10 11. "EVENT140DETEN,Event(140) Detection Enable" "0,1" bitfld.long 0x10 10. "EVENT139DETEN,Event(139) Detection Enable" "0,1" newline bitfld.long 0x10 9. "EVENT138DETEN,Event(138) Detection Enable" "0,1" bitfld.long 0x10 8. "EVENT137DETEN,Event(137) Detection Enable" "0,1" newline bitfld.long 0x10 7. "EVENT136DETEN,Event(136) Detection Enable" "0,1" bitfld.long 0x10 6. "EVENT135DETEN,Event(135) Detection Enable" "0,1" newline bitfld.long 0x10 5. "EVENT134DETEN,Event(134) Detection Enable" "0,1" bitfld.long 0x10 4. "EVENT133DETEN,Event(133) Detection Enable" "0,1" newline bitfld.long 0x10 3. "EVENT132DETEN,Event(132) Detection Enable" "0,1" bitfld.long 0x10 2. "EVENT131DETEN,Event(131) Detection Enable" "0,1" newline bitfld.long 0x10 1. "EVENT130DETEN,Event(130) Detection Enable" "0,1" bitfld.long 0x10 0. "EVENT129DETEN,Event(129) Detection Enable" "0,1" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL6,System event detection enable register 6 (if number of events > 160)" bitfld.long 0x14 31. "EVENT192DETEN,Event(192) Detection Enable" "0,1" bitfld.long 0x14 30. "EVENT191DETEN,Event(191) Detection Enable" "0,1" newline bitfld.long 0x14 29. "EVENT190DETEN,Event(190) Detection Enable" "0,1" bitfld.long 0x14 28. "EVENT189DETEN,Event(189) Detection Enable" "0,1" newline bitfld.long 0x14 27. "EVENT188DETEN,Event(188) Detection Enable" "0,1" bitfld.long 0x14 26. "EVENT187DETEN,Event(187) Detection Enable" "0,1" newline bitfld.long 0x14 25. "EVENT186DETEN,Event(186) Detection Enable" "0,1" bitfld.long 0x14 24. "EVENT185DETEN,Event(185) Detection Enable" "0,1" newline bitfld.long 0x14 23. "EVENT184DETEN,Event(184) Detection Enable" "0,1" bitfld.long 0x14 22. "EVENT183DETEN,Event(183) Detection Enable" "0,1" newline bitfld.long 0x14 21. "EVENT182DETEN,Event(182) Detection Enable" "0,1" bitfld.long 0x14 20. "EVENT181DETEN,Event(181) Detection Enable" "0,1" newline bitfld.long 0x14 19. "EVENT180DETEN,Event(180) Detection Enable" "0,1" bitfld.long 0x14 18. "EVENT179DETEN,Event(179) Detection Enable" "0,1" newline bitfld.long 0x14 17. "EVENT178DETEN,Event(178) Detection Enable" "0,1" bitfld.long 0x14 16. "EVENT177DETEN,Event(177) Detection Enable" "0,1" newline bitfld.long 0x14 15. "EVENT176DETEN,Event(176) Detection Enable" "0,1" bitfld.long 0x14 14. "EVENT175DETEN,Event(175) Detection Enable" "0,1" newline bitfld.long 0x14 13. "EVENT174DETEN,Event(174) Detection Enable" "0,1" bitfld.long 0x14 12. "EVENT173DETEN,Event(173) Detection Enable" "0,1" newline bitfld.long 0x14 11. "EVENT172DETEN,Event(172) Detection Enable" "0,1" bitfld.long 0x14 10. "EVENT171DETEN,Event(171) Detection Enable" "0,1" newline bitfld.long 0x14 9. "EVENT170DETEN,Event(170) Detection Enable" "0,1" bitfld.long 0x14 8. "EVENT169DETEN,Event(169) Detection Enable" "0,1" newline bitfld.long 0x14 7. "EVENT168DETEN,Event(168) Detection Enable" "0,1" bitfld.long 0x14 6. "EVENT167DETEN,Event(167) Detection Enable" "0,1" newline bitfld.long 0x14 5. "EVENT166DETEN,Event(166) Detection Enable" "0,1" bitfld.long 0x14 4. "EVENT165DETEN,Event(165) Detection Enable" "0,1" newline bitfld.long 0x14 3. "EVENT164DETEN,Event(164) Detection Enable" "0,1" bitfld.long 0x14 2. "EVENT163DETEN,Event(163) Detection Enable" "0,1" newline bitfld.long 0x14 1. "EVENT162DETEN,Event(162) Detection Enable" "0,1" bitfld.long 0x14 0. "EVENT161DETEN,Event(161) Detection Enable" "0,1" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL7,System event detection enable register 7 (if number of events > 192)" bitfld.long 0x18 31. "EVENT224DETEN,Event(224) Detection Enable" "0,1" bitfld.long 0x18 30. "EVENT223DETEN,Event(223) Detection Enable" "0,1" newline bitfld.long 0x18 29. "EVENT222DETEN,Event(222) Detection Enable" "0,1" bitfld.long 0x18 28. "EVENT221DETEN,Event(221) Detection Enable" "0,1" newline bitfld.long 0x18 27. "EVENT220DETEN,Event(220) Detection Enable" "0,1" bitfld.long 0x18 26. "EVENT219DETEN,Event(219) Detection Enable" "0,1" newline bitfld.long 0x18 25. "EVENT218DETEN,Event(218) Detection Enable" "0,1" bitfld.long 0x18 24. "EVENT217DETEN,Event(217) Detection Enable" "0,1" newline bitfld.long 0x18 23. "EVENT216DETEN,Event(216) Detection Enable" "0,1" bitfld.long 0x18 22. "EVENT215DETEN,Event(215) Detection Enable" "0,1" newline bitfld.long 0x18 21. "EVENT214DETEN,Event(214) Detection Enable" "0,1" bitfld.long 0x18 20. "EVENT213DETEN,Event(213) Detection Enable" "0,1" newline bitfld.long 0x18 19. "EVENT212DETEN,Event(212) Detection Enable" "0,1" bitfld.long 0x18 18. "EVENT211DETEN,Event(211) Detection Enable" "0,1" newline bitfld.long 0x18 17. "EVENT210DETEN,Event(210) Detection Enable" "0,1" bitfld.long 0x18 16. "EVENT209DETEN,Event(209) Detection Enable" "0,1" newline bitfld.long 0x18 15. "EVENT208DETEN,Event(208) Detection Enable" "0,1" bitfld.long 0x18 14. "EVENT207DETEN,Event(207) Detection Enable" "0,1" newline bitfld.long 0x18 13. "EVENT206DETEN,Event(206) Detection Enable" "0,1" bitfld.long 0x18 12. "EVENT205DETEN,Event(205) Detection Enable" "0,1" newline bitfld.long 0x18 11. "EVENT204DETEN,Event(204) Detection Enable" "0,1" bitfld.long 0x18 10. "EVENT203DETEN,Event(203) Detection Enable" "0,1" newline bitfld.long 0x18 9. "EVENT202DETEN,Event(202) Detection Enable" "0,1" bitfld.long 0x18 8. "EVENT201DETEN,Event(201) Detection Enable" "0,1" newline bitfld.long 0x18 7. "EVENT200DETEN,Event(200) Detection Enable" "0,1" bitfld.long 0x18 6. "EVENT199DETEN,Event(199) Detection Enable" "0,1" newline bitfld.long 0x18 5. "EVENT198DETEN,Event(198) Detection Enable" "0,1" bitfld.long 0x18 4. "EVENT197DETEN,Event(197) Detection Enable" "0,1" newline bitfld.long 0x18 3. "EVENT196DETEN,Event(196) Detection Enable" "0,1" bitfld.long 0x18 2. "EVENT195DETEN,Event(195) Detection Enable" "0,1" newline bitfld.long 0x18 1. "EVENT194DETEN,Event(194) Detection Enable" "0,1" bitfld.long 0x18 0. "EVENT193DETEN,Event(193) Detection Enable" "0,1" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_SETEVTENBL8,System event detection enable register 8 (if number of events > 224)" bitfld.long 0x1C 31. "EVENT256DETEN,Event(256) Detection Enable" "0,1" bitfld.long 0x1C 30. "EVENT255DETEN,Event(255) Detection Enable" "0,1" newline bitfld.long 0x1C 29. "EVENT254DETEN,Event(254) Detection Enable" "0,1" bitfld.long 0x1C 28. "EVENT253DETEN,Event(253) Detection Enable" "0,1" newline bitfld.long 0x1C 27. "EVENT252DETEN,Event(252) Detection Enable" "0,1" bitfld.long 0x1C 26. "EVENT251DETEN,Event(251) Detection Enable" "0,1" newline bitfld.long 0x1C 25. "EVENT250DETEN,Event(250) Detection Enable" "0,1" bitfld.long 0x1C 24. "EVENT249DETEN,Event(249) Detection Enable" "0,1" newline bitfld.long 0x1C 23. "EVENT248DETEN,Event(248) Detection Enable" "0,1" bitfld.long 0x1C 22. "EVENT247DETEN,Event(247) Detection Enable" "0,1" newline bitfld.long 0x1C 21. "EVENT246DETEN,Event(246) Detection Enable" "0,1" bitfld.long 0x1C 20. "EVENT245DETEN,Event(245) Detection Enable" "0,1" newline bitfld.long 0x1C 19. "EVENT244DETEN,Event(244) Detection Enable" "0,1" bitfld.long 0x1C 18. "EVENT243DETEN,Event(243) Detection Enable" "0,1" newline bitfld.long 0x1C 17. "EVENT242DETEN,Event(242) Detection Enable" "0,1" bitfld.long 0x1C 16. "EVENT241DETEN,Event(241) Detection Enable" "0,1" newline bitfld.long 0x1C 15. "EVENT240DETEN,Event(240) Detection Enable" "0,1" bitfld.long 0x1C 14. "EVENT239DETEN,Event(239) Detection Enable" "0,1" newline bitfld.long 0x1C 13. "EVENT238DETEN,Event(238) Detection Enable" "0,1" bitfld.long 0x1C 12. "EVENT237DETEN,Event(237) Detection Enable" "0,1" newline bitfld.long 0x1C 11. "EVENT236DETEN,Event(236) Detection Enable" "0,1" bitfld.long 0x1C 10. "EVENT235DETEN,Event(235) Detection Enable" "0,1" newline bitfld.long 0x1C 9. "EVENT234DETEN,Event(234) Detection Enable" "0,1" bitfld.long 0x1C 8. "EVENT233DETEN,Event(233) Detection Enable" "0,1" newline bitfld.long 0x1C 7. "EVENT232DETEN,Event(232) Detection Enable" "0,1" bitfld.long 0x1C 6. "EVENT231DETEN,Event(231) Detection Enable" "0,1" newline bitfld.long 0x1C 5. "EVENT230DETEN,Event(230) Detection Enable" "0,1" bitfld.long 0x1C 4. "EVENT229DETEN,Event(229) Detection Enable" "0,1" newline bitfld.long 0x1C 3. "EVENT228DETEN,Event(228) Detection Enable" "0,1" bitfld.long 0x1C 2. "EVENT227DETEN,Event(227) Detection Enable" "0,1" newline bitfld.long 0x1C 1. "EVENT226DETEN,Event(226) Detection Enable" "0,1" bitfld.long 0x1C 0. "EVENT225DETEN,Event(225) Detection Enable" "0,1" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_SETMSTID,System Event Master ID" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x20 0.--7. 1. "MASTID,HW Master ID for System Event module. Software may overwrite the value at any time but this is only recommended for scenarios where top-level configuration errors result in a collision between HW master IDs" rgroup.long 0x800++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTL,Counter Timer Control" hexmask.long.byte 0x0 26.--31. 1. "NUMSTM,Number of counters that can export via STM" hexmask.long.byte 0x0 18.--25. 1. "NUMINPT,Number of event input signals" newline hexmask.long.byte 0x0 13.--17. 1. "NUMTIMR,Number of timers in the module" hexmask.long.byte 0x0 7.--12. 1. "NUMCNTR,Number of counters in the module" newline hexmask.long.byte 0x0 3.--6. 1. "REVID,Revision ID of CTSET" bitfld.long 0x0 1. "RESERVED,Reserved returns 0" "0,1" newline bitfld.long 0x0 0. "NUMCOREMD,Indicated the number of mode bus interfaces 0 is 2 CPU buses 1 is 4 buses" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTNUMDBG,Counter Timer Number Debug Event Register" hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x4 0.--2. "NUMEVT,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" group.long 0x808++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTUSERACCCTL,Counter Timer User Access Control. can only be written in priviledged mode" hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x0 2. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" newline bitfld.long 0x0 1. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x0 0. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" group.long 0x820++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTSTMCNTL,Counter Timer STM Control register" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x0 6.--11. 1. "NUMXPORT,The total number of counters designated for export" newline rbitfld.long 0x0 5. "XPORTACT,Indicates if a frame is currently being written to the STM." "0,1" bitfld.long 0x0 4. "CCMPORT,SW control of CCM message export" "0,1" newline bitfld.long 0x0 3. "CCMAVAIL,CTSET supports CCM export" "0,1" bitfld.long 0x0 2. "CSMXPORT,SW control of CSM message export" "0,1" newline bitfld.long 0x0 1. "SENDOVR,Send overflow data in CSM frame" "0,1" bitfld.long 0x0 0. "ENBL,CTSET STM global enable for counter/timer messages" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTSTMMSTID,Counter Timer STM Master ID register" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x4 0.--7. 1. "MASTID,HW Master ID for System Event module" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTSTMINTVL,Counter Timer STM Interval Register" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.word 0x8 0.--14. 1. "INTERVAL,Counter Timer Periodic export interval" line.long 0xC "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTSTMSEL0,Counter Timer STM Counter Select Register 0. This Selects Counter 0 to 31" hexmask.long 0xC 0.--31. 1. "COUNTSEL,The individual bit is this field indicate whether the corresponding counter value is included in the CSM message generated via the STM interface" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTSTMSEL1,Counter Timer STM Counter Select Register 1. This Selects Counter 32 to 63" hexmask.long 0x10 0.--31. 1. "COUNTSEL,The individual bit is this field indicate whether the corresponding counter value is included in the CSM message generated via the STM interface" group.long 0x840++0x3F line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR0,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x0 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR1,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x4 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR2,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x8 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0xC "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR3,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0xC 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR4,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x10 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR5,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x14 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR6,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x18 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR7,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x1C 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR8,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x20 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR9,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x24 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR10,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x28 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR11,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x2C 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x30 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR12,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x30 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR13,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x34 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR14,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x38 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTINTVLR15,These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated." hexmask.long 0x3C 0.--31. 1. "INTERVAL,Interval match value for the timers in the CTSET" group.long 0x8A0++0x1F line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL0,Timer Interval Register 0. Interval match value for timer 0 in CTSET Timer Interval Register 1. Interval match value for timer 1 in CTSET Timer Interval Register 2. Interval match value for.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x0 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL1,Counter Timer Debug Event Register 1" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x4 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL2,Counter Timer Debug Event Register 2" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x8 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0xC "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL3,Counter Timer Debug Event Register 3" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0xC 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL4,Counter Timer Debug Event Register 4" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x10 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL5,Counter Timer Debug Event Register5" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x14 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL6,Counter Timer Debug Event Register 6" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x18 0.--7. 1. "INPSEL,Counter Timer input selection" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTDBGSGL7,Counter Timer Debug Event Register 7" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x1C 0.--7. 1. "INPSEL,Counter Timer input selection" group.long 0x9F0++0x18F line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTGNBL0,Counter Timer Global Enable Register 0. This enables Counter 0 to 31" hexmask.long.byte 0x0 0.--7. 1. "ENABLE,The individual bit is this field enables the corresponding counter. Bits 30 and 31 will be high if global time stamp output interface is enabled" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTGNBL1,Counter Timer Global Enable Register 1. This enables Counter 32 to 63" hexmask.long.byte 0x4 0.--7. 1. "ENABLE,The individual bit is this field enables the corresponding counter" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTGRST0,Counter Timer Global Reset Register 0. This resets Counter 0 to 31" hexmask.long.byte 0x8 0.--7. 1. "RESET,The individual bit is this field resets the corresponding counter. These bits are self-clearing once a '1' is written after the counters are reset these bits are cleared. When Global Time Stamp output interface is enabled counter 31 and counter.." line.long 0xC "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTGRST1,Counter Timer Global Reset Register 0. This resets Counter 32 to 63" hexmask.long.byte 0xC 0.--7. 1. "RESET,The individual bit is this field resets the corresponding counter. These bits are self-clearing once a '1' is written after the counters are reset these bits are cleared." line.long 0x10 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR0,Counter Timer Control Register 0" hexmask.long.byte 0x10 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x10 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x10 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x10 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x10 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x10 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x10 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x10 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x10 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x10 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x10 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x10 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x10 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x10 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x10 1. "RESET,Counter reset control" "0,1" bitfld.long 0x10 0. "ENBL,Counter enable control" "0,1" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR1,Counter Timer Control Register 1" hexmask.long.byte 0x14 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x14 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x14 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x14 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x14 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x14 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x14 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x14 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x14 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x14 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x14 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x14 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x14 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x14 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x14 1. "RESET,Counter reset control" "0,1" bitfld.long 0x14 0. "ENBL,Counter enable control" "0,1" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR2,Counter Timer Control Register 2" hexmask.long.byte 0x18 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x18 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x18 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x18 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x18 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x18 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x18 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x18 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x18 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x18 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x18 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x18 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x18 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x18 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x18 1. "RESET,Counter reset control" "0,1" bitfld.long 0x18 0. "ENBL,Counter enable control" "0,1" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR3,Counter Timer Control Register 3" hexmask.long.byte 0x1C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x1C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x1C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x1C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x1C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x1C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x1C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x1C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x1C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x1C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x1C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x1C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x1C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x1C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x1C 1. "RESET,Counter reset control" "0,1" bitfld.long 0x1C 0. "ENBL,Counter enable control" "0,1" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR4,Counter Timer Control Register 4" hexmask.long.byte 0x20 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x20 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x20 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x20 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x20 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x20 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x20 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x20 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x20 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x20 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x20 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x20 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x20 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x20 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x20 1. "RESET,Counter reset control" "0,1" bitfld.long 0x20 0. "ENBL,Counter enable control" "0,1" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR5,Counter Timer Control Register 5" hexmask.long.byte 0x24 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x24 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x24 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x24 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x24 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x24 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x24 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x24 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x24 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x24 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x24 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x24 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x24 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x24 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x24 1. "RESET,Counter reset control" "0,1" bitfld.long 0x24 0. "ENBL,Counter enable control" "0,1" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR6,Counter Timer Control Register 6" hexmask.long.byte 0x28 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x28 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x28 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x28 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x28 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x28 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x28 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x28 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x28 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x28 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x28 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x28 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x28 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x28 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x28 1. "RESET,Counter reset control" "0,1" bitfld.long 0x28 0. "ENBL,Counter enable control" "0,1" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR7,Counter Timer Control Register 7" hexmask.long.byte 0x2C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x2C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x2C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x2C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x2C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x2C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x2C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x2C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x2C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x2C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x2C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x2C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x2C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x2C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x2C 1. "RESET,Counter reset control" "0,1" bitfld.long 0x2C 0. "ENBL,Counter enable control" "0,1" line.long 0x30 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR8,Counter Timer Control Register 8" hexmask.long.byte 0x30 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x30 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x30 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x30 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x30 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x30 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x30 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x30 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x30 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x30 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x30 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x30 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x30 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x30 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x30 1. "RESET,Counter reset control" "0,1" bitfld.long 0x30 0. "ENBL,Counter enable control" "0,1" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR9,Counter Timer Control Register 9" hexmask.long.byte 0x34 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x34 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x34 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x34 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x34 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x34 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x34 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x34 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x34 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x34 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x34 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x34 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x34 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x34 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x34 1. "RESET,Counter reset control" "0,1" bitfld.long 0x34 0. "ENBL,Counter enable control" "0,1" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR10,Counter Timer Control Register 10" hexmask.long.byte 0x38 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x38 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x38 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x38 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x38 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x38 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x38 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x38 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x38 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x38 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x38 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x38 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x38 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x38 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x38 1. "RESET,Counter reset control" "0,1" bitfld.long 0x38 0. "ENBL,Counter enable control" "0,1" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR11,Counter Timer Control Register 11" hexmask.long.byte 0x3C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x3C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x3C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x3C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x3C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x3C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x3C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x3C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x3C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x3C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x3C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x3C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x3C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x3C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x3C 1. "RESET,Counter reset control" "0,1" bitfld.long 0x3C 0. "ENBL,Counter enable control" "0,1" line.long 0x40 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR12,Counter Timer Control Register 12" hexmask.long.byte 0x40 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x40 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x40 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x40 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x40 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x40 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x40 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x40 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x40 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x40 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x40 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x40 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x40 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x40 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x40 1. "RESET,Counter reset control" "0,1" bitfld.long 0x40 0. "ENBL,Counter enable control" "0,1" line.long 0x44 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR13,Counter Timer Control Register 13" hexmask.long.byte 0x44 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x44 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x44 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x44 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x44 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x44 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x44 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x44 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x44 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x44 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x44 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x44 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x44 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x44 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x44 1. "RESET,Counter reset control" "0,1" bitfld.long 0x44 0. "ENBL,Counter enable control" "0,1" line.long 0x48 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR14,Counter Timer Control Register 14" hexmask.long.byte 0x48 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x48 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x48 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x48 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x48 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x48 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x48 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x48 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x48 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x48 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x48 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x48 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x48 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x48 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x48 1. "RESET,Counter reset control" "0,1" bitfld.long 0x48 0. "ENBL,Counter enable control" "0,1" line.long 0x4C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR15,Counter Timer Control Register 15" hexmask.long.byte 0x4C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x4C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x4C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x4C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x4C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x4C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x4C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x4C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x4C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x4C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x4C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x4C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x4C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x4C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x4C 1. "RESET,Counter reset control" "0,1" bitfld.long 0x4C 0. "ENBL,Counter enable control" "0,1" line.long 0x50 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR16,Counter Timer Control Register 16" hexmask.long.byte 0x50 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x50 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x50 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x50 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x50 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x50 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x50 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x50 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x50 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x50 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x50 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x50 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x50 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x50 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x50 1. "RESET,Counter reset control" "0,1" bitfld.long 0x50 0. "ENBL,Counter enable control" "0,1" line.long 0x54 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR17,Counter Timer Control Register 17" hexmask.long.byte 0x54 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x54 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x54 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x54 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x54 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x54 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x54 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x54 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x54 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x54 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x54 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x54 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x54 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x54 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x54 1. "RESET,Counter reset control" "0,1" bitfld.long 0x54 0. "ENBL,Counter enable control" "0,1" line.long 0x58 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR18,Counter Timer Control Register 18" hexmask.long.byte 0x58 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x58 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x58 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x58 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x58 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x58 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x58 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x58 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x58 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x58 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x58 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x58 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x58 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x58 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x58 1. "RESET,Counter reset control" "0,1" bitfld.long 0x58 0. "ENBL,Counter enable control" "0,1" line.long 0x5C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR19,Counter Timer Control Register 19" hexmask.long.byte 0x5C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x5C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x5C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x5C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x5C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x5C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x5C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x5C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x5C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x5C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x5C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x5C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x5C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x5C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x5C 1. "RESET,Counter reset control" "0,1" bitfld.long 0x5C 0. "ENBL,Counter enable control" "0,1" line.long 0x60 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR20,Counter Timer Control Register 20" hexmask.long.byte 0x60 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x60 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x60 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x60 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x60 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x60 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x60 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x60 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x60 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x60 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x60 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x60 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x60 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x60 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x60 1. "RESET,Counter reset control" "0,1" bitfld.long 0x60 0. "ENBL,Counter enable control" "0,1" line.long 0x64 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR21,Counter Timer Control Register 21" hexmask.long.byte 0x64 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x64 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x64 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x64 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x64 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x64 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x64 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x64 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x64 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x64 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x64 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x64 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x64 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x64 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x64 1. "RESET,Counter reset control" "0,1" bitfld.long 0x64 0. "ENBL,Counter enable control" "0,1" line.long 0x68 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR22,Counter Timer Control Register 22" hexmask.long.byte 0x68 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x68 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x68 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x68 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x68 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x68 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x68 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x68 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x68 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x68 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x68 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x68 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x68 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x68 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x68 1. "RESET,Counter reset control" "0,1" bitfld.long 0x68 0. "ENBL,Counter enable control" "0,1" line.long 0x6C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR23,Counter Timer Control Register 23" hexmask.long.byte 0x6C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x6C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x6C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x6C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x6C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x6C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x6C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x6C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x6C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x6C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x6C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x6C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x6C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x6C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x6C 1. "RESET,Counter reset control" "0,1" bitfld.long 0x6C 0. "ENBL,Counter enable control" "0,1" line.long 0x70 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR24,Counter Timer Control Register 24" hexmask.long.byte 0x70 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x70 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x70 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x70 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x70 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x70 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x70 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x70 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x70 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x70 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x70 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x70 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x70 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x70 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x70 1. "RESET,Counter reset control" "0,1" bitfld.long 0x70 0. "ENBL,Counter enable control" "0,1" line.long 0x74 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR25,Counter Timer Control Register 25" hexmask.long.byte 0x74 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x74 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x74 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x74 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x74 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x74 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x74 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x74 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x74 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x74 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x74 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x74 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x74 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x74 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x74 1. "RESET,Counter reset control" "0,1" bitfld.long 0x74 0. "ENBL,Counter enable control" "0,1" line.long 0x78 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR26,Counter Timer Control Register 26" hexmask.long.byte 0x78 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x78 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x78 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x78 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x78 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x78 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x78 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x78 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x78 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x78 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x78 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x78 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x78 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x78 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x78 1. "RESET,Counter reset control" "0,1" bitfld.long 0x78 0. "ENBL,Counter enable control" "0,1" line.long 0x7C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR27,Counter Timer Control Register 27" hexmask.long.byte 0x7C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x7C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x7C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x7C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x7C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x7C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x7C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x7C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x7C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x7C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x7C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x7C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x7C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x7C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x7C 1. "RESET,Counter reset control" "0,1" bitfld.long 0x7C 0. "ENBL,Counter enable control" "0,1" line.long 0x80 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR28,Counter Timer Control Register 28" hexmask.long.byte 0x80 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x80 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x80 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x80 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x80 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x80 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x80 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x80 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x80 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x80 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x80 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x80 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x80 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x80 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x80 1. "RESET,Counter reset control" "0,1" bitfld.long 0x80 0. "ENBL,Counter enable control" "0,1" line.long 0x84 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR29,Counter Timer Control Register 29" hexmask.long.byte 0x84 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x84 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x84 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x84 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x84 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x84 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x84 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x84 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x84 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x84 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x84 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x84 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x84 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x84 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x84 1. "RESET,Counter reset control" "0,1" bitfld.long 0x84 0. "ENBL,Counter enable control" "0,1" line.long 0x88 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR30,Counter Timer Control Register 30" hexmask.long.byte 0x88 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x88 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x88 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x88 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x88 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x88 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x88 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x88 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x88 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x88 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x88 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x88 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x88 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x88 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x88 1. "RESET,Counter reset control" "0,1" bitfld.long 0x88 0. "ENBL,Counter enable control" "0,1" line.long 0x8C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCR31,Counter Timer Control Register 31" hexmask.long.byte 0x8C 24.--31. 1. "WDRESET,WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" hexmask.long.byte 0x8C 16.--23. 1. "INPSEL,Counter Timer input selection. For WD mode it is the start event selector" newline bitfld.long 0x8C 14.--15. "MODESEL,Counter is in duration or occurrence mode. Only writable by debug accesses" "0,1,2,3" bitfld.long 0x8C 13. "FILTER,Use associated operating mode filter in CTMODEFILTERn" "0,1" newline bitfld.long 0x8C 12. "DBG_TRIG_STAT,Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x8C 11. "WDMODE,WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x8C 10. "RESTART,Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x8C 9. "DBG,Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" newline bitfld.long 0x8C 8. "INT,Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function" "0,1" bitfld.long 0x8C 7. "CHNSDW,Counter has a shadow register for chain reads. Only valid on counters with an even number index" "0,1" newline bitfld.long 0x8C 6. "OVRFLW,Counter is in duration or occurrence mode" "0,1" rbitfld.long 0x8C 4.--5. "RESERVED,Reserved returns 0" "0,1,2,3" newline bitfld.long 0x8C 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x8C 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" newline bitfld.long 0x8C 1. "RESET,Counter reset control" "0,1" bitfld.long 0x8C 0. "ENBL,Counter enable control" "0,1" line.long 0x90 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN0,Counter/Timer Ownership register 0" bitfld.long 0x90 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0x90 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0x90 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0x90 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x94 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN1,Counter/Timer Ownership register 1" bitfld.long 0x94 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0x94 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0x94 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0x94 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x98 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN2,Counter/Timer Ownership register 2" bitfld.long 0x98 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0x98 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0x98 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0x98 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x9C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN3,Counter/Timer Ownership register 3" bitfld.long 0x9C 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0x9C 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0x9C 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0x9C 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xA0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN4,Counter/Timer Ownership register 4" bitfld.long 0xA0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xA0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xA0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xA0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xA4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN5,Counter/Timer Ownership register 5" bitfld.long 0xA4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xA4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xA4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xA4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xA8 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN6,Counter/Timer Ownership register 6" bitfld.long 0xA8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xA8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xA8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xA8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xAC "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN7,Counter/Timer Ownership register 7" bitfld.long 0xAC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xAC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xAC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xAC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xB0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN8,Counter/Timer Ownership register 8" bitfld.long 0xB0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xB0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xB0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xB0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xB4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN9,Counter/Timer Ownership register 9" bitfld.long 0xB4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xB4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xB4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xB4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xB8 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN10,Counter/Timer Ownership register 10" bitfld.long 0xB8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xB8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xB8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xB8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xBC "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN11,Counter/Timer Ownership register 11" bitfld.long 0xBC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xBC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xBC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xBC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xC0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN12,Counter/Timer Ownership register 12" bitfld.long 0xC0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xC0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xC0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xC0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xC4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN13,Counter/Timer Ownership register 13" bitfld.long 0xC4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xC4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xC4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xC4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xC8 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN14,Counter/Timer Ownership register 14" bitfld.long 0xC8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xC8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xC8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xC8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xCC "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN15,Counter/Timer Ownership register 15" bitfld.long 0xCC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xCC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xCC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xCC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xD0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN16,Counter/Timer Ownership register 16" bitfld.long 0xD0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xD0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xD0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xD0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xD4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN17,Counter/Timer Ownership register 17" bitfld.long 0xD4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xD4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xD4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xD4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xD8 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN18,Counter/Timer Ownership register 18" bitfld.long 0xD8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xD8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xD8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xD8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xDC "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN19,Counter/Timer Ownership register 19" bitfld.long 0xDC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xDC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xDC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xDC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xE0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN20,Counter/Timer Ownership register 20" bitfld.long 0xE0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xE0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xE0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xE0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xE4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN21,Counter/Timer Ownership register 21" bitfld.long 0xE4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xE4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xE4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xE4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xE8 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN22,Counter/Timer Ownership register 22" bitfld.long 0xE8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xE8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xE8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xE8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xEC "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN23,Counter/Timer Ownership register2 3" bitfld.long 0xEC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xEC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xEC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xEC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xF0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN24,Counter/Timer Ownership register 24" bitfld.long 0xF0 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xF0 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xF0 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xF0 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xF4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN25,Counter/Timer Ownership register 25" bitfld.long 0xF4 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xF4 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xF4 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xF4 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xF8 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN26,Counter/Timer Ownership register 26" bitfld.long 0xF8 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xF8 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xF8 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xF8 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0xFC "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN27,Counter/Timer Ownership register 27" bitfld.long 0xFC 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0xFC 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0xFC 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0xFC 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x100 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN28,Counter/Timer Ownership register 28" bitfld.long 0x100 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0x100 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0x100 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0x100 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x104 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN29,Counter/Timer Ownership register 29" bitfld.long 0x104 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0x104 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0x104 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0x104 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x108 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN30,Counter/Timer Ownership register 30" bitfld.long 0x108 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0x108 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0x108 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0x108 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x10C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTOWN31,Counter/Timer Ownership register 31" bitfld.long 0x10C 30.--31. "OWNERSHIP,Counter/Timer Ownership Status. The Read encoding is (0=Available 1=Claimed 2=Enabled 3=Reserved). The write commands are (0=release 1=claim 2=enable 3=nop)" "0: release,1: claim,2: enable,3: nop" bitfld.long 0x10C 29. "DBG_OVERIDE,This bit indicates the debugger is Claiming the resource always reads back as 1" "0,1" newline rbitfld.long 0x10C 28. "CURRENT_OWNER,This value reflects the Counter/Timer ownership when the register is in a non-Available state 1=Ap owned 0=Dbg owned" "0: Dbg owned,1: Ap owned" hexmask.long 0x10C 0.--27. 1. "RESERVED,Reserved returns 0" line.long 0x110 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT0,Counter Timer 0 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x110 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x110 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x110 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x110 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x110 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x110 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x110 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x110 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x110 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x114 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT1,Counter Timer 1 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x114 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x114 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x114 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x114 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x114 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x114 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x114 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x114 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x114 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x118 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT2,Counter Timer 2 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x118 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x118 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x118 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x118 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x118 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x118 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x118 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x118 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x118 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x11C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT3,Counter Timer 3 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x11C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x11C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x11C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x11C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x11C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x11C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x11C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x11C 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x11C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x120 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT4,Counter Timer 4 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x120 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x120 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x120 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x120 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x120 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x120 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x120 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x120 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x120 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x124 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT5,Counter Timer 5 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x124 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x124 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x124 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x124 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x124 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x124 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x124 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x124 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x124 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x128 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT6,Counter Timer 6 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x128 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x128 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x128 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x128 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x128 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x128 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x128 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x128 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x128 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x12C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT7,Counter Timer 7 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x12C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x12C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x12C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x12C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x12C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x12C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x12C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x12C 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x12C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x130 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT8,Counter Timer 8 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x130 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x130 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x130 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x130 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x130 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x130 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x130 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x130 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x130 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x134 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT9,Counter Timer 9 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x134 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x134 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x134 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x134 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x134 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x134 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x134 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x134 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x134 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x138 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT10,Counter Timer 10 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x138 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x138 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x138 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x138 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x138 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x138 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x138 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x138 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x138 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x13C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT11,Counter Timer 11 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x13C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x13C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x13C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x13C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x13C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x13C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x13C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x13C 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x13C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x140 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT12,Counter Timer 12 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x140 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x140 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x140 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x140 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x140 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x140 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x140 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x140 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x140 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x144 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT13,Counter Timer 13 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x144 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x144 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x144 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x144 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x144 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x144 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x144 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x144 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x144 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x148 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT14,Counter Timer 14 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x148 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x148 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x148 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x148 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x148 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x148 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x148 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x148 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x148 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x14C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT15,Counter Timer 15 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x14C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x14C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x14C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x14C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x14C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x14C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x14C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x14C 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x14C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x150 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT16,Counter Timer 16 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x150 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x150 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x150 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x150 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x150 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x150 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x150 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x150 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x150 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x154 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT17,Counter Timer 17 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x154 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x154 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x154 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x154 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x154 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x154 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x154 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x154 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x154 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x158 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT18,Counter Timer 18 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x158 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x158 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x158 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x158 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x158 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x158 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x158 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x158 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x158 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x15C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT19,Counter Timer 19 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x15C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x15C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x15C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x15C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x15C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x15C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x15C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x15C 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x15C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x160 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT20,Counter Timer 20 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x160 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x160 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x160 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x160 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x160 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x160 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x160 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x160 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x160 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x164 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT21,Counter Timer 21 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x164 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x164 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x164 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x164 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x164 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x164 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x164 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x164 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x164 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x168 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT22,Counter Timer 22 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x168 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x168 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x168 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x168 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x168 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x168 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x168 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x168 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x168 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x16C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT23,Counter Timer 23 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x16C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x16C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x16C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x16C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x16C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x16C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x16C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x16C 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x16C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x170 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT24,Counter Timer 24 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x170 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x170 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x170 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x170 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x170 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x170 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x170 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x170 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x170 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x174 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT25,Counter Timer 25 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x174 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x174 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x174 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x174 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x174 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x174 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x174 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x174 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x174 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x178 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT26,Counter Timer 26 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x178 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x178 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x178 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x178 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x178 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x178 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x178 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x178 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x178 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x17C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT27,Counter Timer 27 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x17C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x17C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x17C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x17C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x17C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x17C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x17C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x17C 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x17C 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x180 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT28,Counter Timer 28 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x180 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x180 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x180 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x180 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x180 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x180 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x180 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x180 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x180 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x184 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT29,Counter Timer 29 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x184 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x184 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x184 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x184 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x184 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x184 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x184 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x184 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x184 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x188 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT30,Counter Timer 30 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x188 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x188 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x188 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x188 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x188 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x188 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x188 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x188 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x188 0. "FREE,Counter functions while system/core is halted" "0,1" line.long 0x18C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTFILT31,Counter Timer 31 Filter Register. These filters are only activated if the CTCRn : FILTER is set" hexmask.long.tbyte 0x18C 8.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x18C 7. "SECSUPER,Counter functions while system is in Secure-Supervisor mode" "0,1" newline bitfld.long 0x18C 6. "SECUSER,Counter functions while system is in Secure-User mode" "0,1" bitfld.long 0x18C 5. "RSUPER,Counter functions while system is in Root-Supervisor node" "0,1" newline bitfld.long 0x18C 4. "RUSER,Counter functions while system is in Root-User mode" "0,1" bitfld.long 0x18C 3. "NRSUPER,Counter functions while system is in Non-Root-Supervisor mode" "0,1" newline bitfld.long 0x18C 2. "NRUSER,Counter functions while system is in in Non-Root-User mode" "0,1" bitfld.long 0x18C 1. "IDLE,Counter functions while system/core is in idle" "0,1" newline bitfld.long 0x18C 0. "FREE,Counter functions while system/core is halted" "0,1" rgroup.long 0xB80++0x7F line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR0,Counter Timer Counter Register 0" hexmask.long 0x0 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR1,Counter Timer Counter Register 1" hexmask.long 0x4 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x8 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR2,Counter Timer Counter Register 2" hexmask.long 0x8 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0xC "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR3,Counter Timer Counter Register 3" hexmask.long 0xC 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x10 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR4,Counter Timer Counter Register 4" hexmask.long 0x10 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x14 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR5,Counter Timer Counter Register 5" hexmask.long 0x14 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x18 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR6,Counter Timer Counter Register 6" hexmask.long 0x18 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x1C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR7,Counter Timer Counter Register 7" hexmask.long 0x1C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x20 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR8,Counter Timer Counter Register 8" hexmask.long 0x20 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x24 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR9,Counter Timer Counter Register 9" hexmask.long 0x24 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x28 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR10,Counter Timer Counter Register 10" hexmask.long 0x28 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x2C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR11,Counter Timer Counter Register 11" hexmask.long 0x2C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x30 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR12,Counter Timer Counter Register 12" hexmask.long 0x30 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x34 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR13,Counter Timer Counter Register 13" hexmask.long 0x34 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x38 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR14,Counter Timer Counter Register 14" hexmask.long 0x38 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x3C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR15,Counter Timer Counter Register 15" hexmask.long 0x3C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x40 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR16,Counter Timer Counter Register 16" hexmask.long 0x40 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x44 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR17,Counter Timer Counter Register 17" hexmask.long 0x44 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x48 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR18,Counter Timer Counter Register 18" hexmask.long 0x48 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x4C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR19,Counter Timer Counter Register 19" hexmask.long 0x4C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x50 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR20,Counter Timer Counter Register 20" hexmask.long 0x50 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x54 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR21,Counter Timer Counter Register 21" hexmask.long 0x54 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x58 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR22,Counter Timer Counter Register 22" hexmask.long 0x58 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x5C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR23,Counter Timer Counter Register 23" hexmask.long 0x5C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x60 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR24,Counter Timer Counter Register 24" hexmask.long 0x60 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x64 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR25,Counter Timer Counter Register 25" hexmask.long 0x64 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x68 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR26,Counter Timer Counter Register 26" hexmask.long 0x68 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x6C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR27,Counter Timer Counter Register 27" hexmask.long 0x6C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x70 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR28,Counter Timer Counter Register 28" hexmask.long 0x70 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x74 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR29,Counter Timer Counter Register 29" hexmask.long 0x74 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x78 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR30,Counter Timer Counter Register 30" hexmask.long 0x78 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." line.long 0x7C "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTCNTR31,Counter Timer Counter Register 31" hexmask.long 0x7C 0.--31. 1. "COUNT,This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set the Counter will increment when the low order counter rolls.." group.long 0xC00++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CT_EOI,Counter Timer EOI Register. This register is the End of Interrupt used by SW to signal HW that an interrupt event service is complete and an interrupt can be rearmed. This register exists only if.." hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x0 0. "EOI,EOI value" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTIRQSTAT_RAW,Counter Timer IRQSTATUS RAW Register. This register indicates the raw status of the interrupt. It can be written by SW for testing. This register exists only if NUMTIMR > 0" hexmask.long 0x4 0.--31. 1. "TIM_INTN_IRQ,IRQSTATUS_RAW value. The individual bits is this field correspond to individual interrupts generated for each timer associated with Counter Timer Control Register (CTCRn : INT)." line.long 0x8 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTIRQSTAT,Counter Timer IRQSTATUS Register. This bit clears the interrupt event. SW can also read this bit to indicate that the interrupt is active and enabled. This register exists only if NUMTIMR > 0" hexmask.long 0x8 0.--31. 1. "TIM_INTN_IE,IRQSTATUS value. The individual bits is this field correspond to individual interrupts generated for each timer associated with Counter Timer Control Register (CTCRn : INT)." line.long 0xC "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTIRQENABLE_SET,Counter Timer IRQENABLE_SET Register. This register is to enable generation of Interrupt Event used by SW. This register exists only if NUMTIMR > 0" hexmask.long 0xC 0.--31. 1. "TIM_INTN_IES,IRQSET value. This bit sets the enable of the interrupt event. SW can also read this bit to determine if the interrupt is enabled. The individual bits is this field correspond to individual interrupts generated for each timer associated with.." line.long 0x10 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_CTIRQENABLE_CLR,Counter Timer IRQENABLE_CLR Register. This register is to disable generation of Interrupt Event used by SW. This register exists only if NUMTIMR > 0" hexmask.long 0x10 0.--31. 1. "TIM_INTN_IEC,IRQCLR value. This bit clears the enable of the interrupt event. SW can also read this bit to determine if the interrupt is enabled. The individual bits is this field correspond to individual interrupts generated for each timer associated.." group.long 0x1800++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_STPTCR,STP Trace Control Register" hexmask.long.byte 0x0 25.--31. 1. "RESERVED3,Reserved returns 0" rbitfld.long 0x0 24. "MOD_FIFOFULL,STPMI2ATB internal MID packet fifo is full" "0,1" newline rbitfld.long 0x0 23. "DATA_FIFOFULL,STPMI2ATB internal Data packet fifo is full" "0,1" hexmask.long.tbyte 0x0 6.--22. 1. "RESERVED2,Reserved returns 0" newline bitfld.long 0x0 5. "COMPEN,Compression of Data enable" "0,1" rbitfld.long 0x0 3.--4. "RESERVED1,Reserved returns 0" "0,1,2,3" newline rbitfld.long 0x0 2. "SYNCEN,The value 1 indicates STPASYNC is supported" "0,1" bitfld.long 0x0 1. "TSEN,Timestamp Enable. This bit is static and should not be changed dynamically. This should be changed before client is enabled." "0,1" newline rbitfld.long 0x0 0. "RESERVED,Reserved returns 0" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_STPTID,STP Trace ID Register" hexmask.long 0x4 7.--31. 1. "RESERVED,Reserved returns 0" hexmask.long.byte 0x4 0.--6. 1. "TRACEID,Trace ID value. Software may overwrite the value at any time but this is only recommended for scenarios where top-level configuration errors result in a collision between HW master IDs" group.long 0x1810++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_STPASYNC,STP Synchronization Control Register" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved returns 0" bitfld.long 0x0 12. "EXPMODE,Exponent mode A value of 1 sets count to 2 to the Nth where Nth is ((bits 11 : 8)+12). A value of 0 sets Count to N (bits 11 : 0)" "0,1" newline hexmask.long.word 0x0 0.--11. 1. "COUNT,The number of bytes between Synchronization packets" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_STPFFCR,STP Flush Control Register" hexmask.long 0x4 6.--31. 1. "RESERVED1,Reserved returns 0" bitfld.long 0x4 5. "FORCEFLUSH,Write a 1 to force a flush automatically clears after the operation is complete" "0,1" newline rbitfld.long 0x4 2.--4. "RESERVED,Reserved returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x4 1. "ASYNCPE,Async Priority Enable. 0 indicates ASYNC packet priority is lower than trace. 1 indicates priority escalates on second synchronization request" "0,1" newline bitfld.long 0x4 0. "AUTOFLUSH,Auto flush enable. When set on every complete data (ATDATA : WIDTH) in the fifo written data is exported out when ATREADY is asserted. This should be written before client IP enabled" "0,1" rgroup.long 0x1818++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__CTSET2_WRAP__CFG__CTSET2_CFG_STPFEAT1,STP Features 1 Register" hexmask.long.byte 0x0 27.--31. 1. "STP_RTLVER,RTL Version. Reset each time major or minor version is updated" bitfld.long 0x0 24.--26. "STP_MAJVER,Functional Major Version. This is the first version of STPMI2ATB" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 22.--23. "STP_CUSTVER,Custom Version (not used)" "0,1,2,3" hexmask.long.byte 0x0 17.--21. 1. "STP_MINVER,Functional Minor Version" newline hexmask.long.word 0x0 8.--16. 1. "RESERVED,Reserved returns 0" bitfld.long 0x0 4.--6. "VERSION,STP2.0 Time Stamp Value of 011 indicates Natural binary timestamp a value of 100 indicates gray binary timestamps" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "PROT,Protocol Revision. Value of 0001 indicates STP 2.0" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU" base ad:0x2C200000 rgroup.quad 0x0++0xF line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_dru_pid,Peripheral ID Register" bitfld.quad 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.quad 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.quad.word 0x0 16.--27. 1. "FUNC,Module ID" newline hexmask.quad.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.quad 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.quad 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.quad.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.quad 0x8 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_dru_capabilities,DRU Capabilities: Lists the capabilities of the channel for TR TYPE and formatting functions" bitfld.quad 0x8 48. "VCOMP,The DRU supports video compression mode" "0,1" bitfld.quad 0x8 47. "ACOMP,The DRU supports analytic compression mode" "0,1" hexmask.quad.byte 0x8 43.--46. 1. "SECTR,Maximum second TR function that is supported" newline hexmask.quad.byte 0x8 39.--42. 1. "DFMT,Maximum data reformatting function that is supported" hexmask.quad.byte 0x8 35.--38. 1. "ELTYPE,Maximum element type value that is supported" bitfld.quad 0x8 32.--34. "AMODE,The maximum AMODE that is supported. If AMODE is supported then DIR field must be supported for that AMODE." "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x8 20.--31. 1. "RSVD_CONF_SPEC,Reserved for Configuration Specific Features. This implementation has no configuration specific features." bitfld.quad 0x8 19. "GLOBAL_TRIG,Global Triggers 0 and 1 are supported" "0,1" bitfld.quad 0x8 18. "LOCAL_TRIG,Dedicated Local Trigger is supported" "0,1" newline bitfld.quad 0x8 17. "EOL,EOL Field is supported" "0,1" bitfld.quad 0x8 16. "TRSTATIC,STATIC Field is supported" "0,1" bitfld.quad 0x8 15. "TYPE15,Type 15 TR is supported" "0,1" newline bitfld.quad 0x8 14. "TYPE14,Type 14 TR is supported" "0,1" bitfld.quad 0x8 13. "TYPE13,Type 13 TR is supported" "0,1" bitfld.quad 0x8 12. "TYPE12,Type 12 TR is supported" "0,1" newline bitfld.quad 0x8 11. "TYPE11,Type 11 TR is supported" "0,1" bitfld.quad 0x8 10. "TYPE10,Type 10 TR is supported" "0,1" bitfld.quad 0x8 9. "TYPE9,Type 9 TR is supported" "0,1" newline bitfld.quad 0x8 8. "TYPE8,Type 8 TR is supported" "0,1" bitfld.quad 0x8 7. "TYPE7,Type 7 TR is supported" "0,1" bitfld.quad 0x8 6. "TYPE6,Type 6 TR is supported" "0,1" newline bitfld.quad 0x8 5. "TYPE5,Type 5 TR is supported" "0,1" bitfld.quad 0x8 4. "TYPE4,Type 4 TR is supported" "0,1" bitfld.quad 0x8 3. "TYPE3,Type 3 TR is supported" "0,1" newline bitfld.quad 0x8 2. "TYPE2,Type 2 TR is supported" "0,1" bitfld.quad 0x8 1. "TYPE1,Type 1 TR is supported" "0,1" bitfld.quad 0x8 0. "TYPE0,Type 0 TR is supported" "0,1" group.quad 0x40++0x7 line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_dru_pri_mask0,DRU Priority Masks: Enables locking a buffer to be used only by the priority queues" bitfld.quad 0x0 63. "MASK63,Buffer 63 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 62. "MASK62,Buffer 62 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 61. "MASK61,Buffer 61 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 60. "MASK60,Buffer 60 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 59. "MASK59,Buffer 59 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 58. "MASK58,Buffer 58 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 57. "MASK57,Buffer 57 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 56. "MASK56,Buffer 56 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 55. "MASK55,Buffer 55 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 54. "MASK54,Buffer 54 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 53. "MASK53,Buffer 53 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 52. "MASK52,Buffer 52 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 51. "MASK51,Buffer 51 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 50. "MASK50,Buffer 50 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 49. "MASK49,Buffer 49 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 48. "MASK48,Buffer 48 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 47. "MASK47,Buffer 47 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 46. "MASK46,Buffer 46 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 45. "MASK45,Buffer 45 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 44. "MASK44,Buffer 44 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 43. "MASK43,Buffer 43 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 42. "MASK42,Buffer 42 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 41. "MASK41,Buffer 41 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 40. "MASK40,Buffer 40 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 39. "MASK39,Buffer 39 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 38. "MASK38,Buffer 38 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 37. "MASK37,Buffer 37 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 36. "MASK36,Buffer 36 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 35. "MASK35,Buffer 35 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 34. "MASK34,Buffer 34 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 33. "MASK33,Buffer 33 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 32. "MASK32,Buffer 32 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 31. "MASK31,Buffer 31 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 30. "MASK30,Buffer 30 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 29. "MASK29,Buffer 29 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 28. "MASK28,Buffer 28 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 27. "MASK27,Buffer 27 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 26. "MASK26,Buffer 26 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 25. "MASK25,Buffer 25 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 24. "MASK24,Buffer 24 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 23. "MASK23,Buffer 23 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 22. "MASK22,Buffer 22 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 21. "MASK21,Buffer 21 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 20. "MASK20,Buffer 20 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 19. "MASK19,Buffer 19 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 18. "MASK18,Buffer 18 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 17. "MASK17,Buffer 17 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 16. "MASK16,Buffer 16 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 15. "MASK15,Buffer 15 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 14. "MASK14,Buffer 14 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 13. "MASK13,Buffer 13 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 12. "MASK12,Buffer 12 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 11. "MASK11,Buffer 11 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 10. "MASK10,Buffer 10 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 9. "MASK9,Buffer 9 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 8. "MASK8,Buffer 8 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 7. "MASK7,Buffer 7 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 6. "MASK6,Buffer 6 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 5. "MASK5,Buffer 5 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 4. "MASK4,Buffer 4 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 3. "MASK3,Buffer 3 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 2. "MASK2,Buffer 2 can only be used by the Priority queue if set to 1." "0,1" bitfld.quad 0x0 1. "MASK1,Buffer 1 can only be used by the Priority queue if set to 1." "0,1" newline bitfld.quad 0x0 0. "MASK0,Buffer 0 can only be used by the Priority queue if set to 1." "0,1" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE" base ad:0x2C2E0000 rgroup.quad 0x0++0x7 line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CAUSE_cause,Error Register cause for channels 0 to 15" bitfld.quad 0x0 63. "R_ERR15,Masked error bit for Tx channel n+15" "0,1" bitfld.quad 0x0 62. "R_PEND15,Masked completion ring pending bit for Rx channel n+15" "0,1" bitfld.quad 0x0 61. "T_ERR15,Masked error bit for Tx channel n+15" "0,1" bitfld.quad 0x0 60. "T_PEND15,Masked completion ring pending bit for Tx channel n+15" "0,1" bitfld.quad 0x0 59. "R_ERR14,Masked error bit for Tx channel n+14" "0,1" newline bitfld.quad 0x0 58. "R_PEND14,Masked completion ring pending bit for Rx channel n+14" "0,1" bitfld.quad 0x0 57. "T_ERR14,Masked error bit for Tx channel n+14" "0,1" bitfld.quad 0x0 56. "T_PEND14,Masked completion ring pending bit for Tx channel n+14" "0,1" bitfld.quad 0x0 55. "R_ERR13,Masked error bit for Tx channel n+13" "0,1" bitfld.quad 0x0 54. "R_PEND13,Masked completion ring pending bit for Rx channel n+13" "0,1" newline bitfld.quad 0x0 53. "T_ERR13,Masked error bit for Tx channel n+13" "0,1" bitfld.quad 0x0 52. "T_PEND13,Masked completion ring pending bit for Tx channel n+13" "0,1" bitfld.quad 0x0 51. "R_ERR12,Masked error bit for Tx channel n+12" "0,1" bitfld.quad 0x0 50. "R_PEND12,Masked completion ring pending bit for Rx channel n+12" "0,1" bitfld.quad 0x0 49. "T_ERR12,Masked error bit for Tx channel n+12" "0,1" newline bitfld.quad 0x0 48. "T_PEND12,Masked completion ring pending bit for Tx channel n+12" "0,1" bitfld.quad 0x0 47. "R_ERR11,Masked error bit for Tx channel n+11" "0,1" bitfld.quad 0x0 46. "R_PEND11,Masked completion ring pending bit for Rx channel n+11" "0,1" bitfld.quad 0x0 45. "T_ERR11,Masked error bit for Tx channel n+11" "0,1" bitfld.quad 0x0 44. "T_PEND11,Masked completion ring pending bit for Tx channel n+11" "0,1" newline bitfld.quad 0x0 43. "R_ERR10,Masked error bit for Tx channel n+10" "0,1" bitfld.quad 0x0 42. "R_PEND10,Masked completion ring pending bit for Rx channel n+10" "0,1" bitfld.quad 0x0 41. "T_ERR10,Masked error bit for Tx channel n+10" "0,1" bitfld.quad 0x0 40. "T_PEND10,Masked completion ring pending bit for Tx channel n+10" "0,1" bitfld.quad 0x0 39. "R_ERR9,Masked error bit for Tx channel n+9" "0,1" newline bitfld.quad 0x0 38. "R_PEND9,Masked completion ring pending bit for Rx channel n+9" "0,1" bitfld.quad 0x0 37. "T_ERR9,Masked error bit for Tx channel n+9" "0,1" bitfld.quad 0x0 36. "T_PEND9,Masked completion ring pending bit for Tx channel n+9" "0,1" bitfld.quad 0x0 35. "R_ERR8,Masked error bit for Tx channel n+8" "0,1" bitfld.quad 0x0 34. "R_PEND8,Masked completion ring pending bit for Rx channel n+8" "0,1" newline bitfld.quad 0x0 33. "T_ERR8,Masked error bit for Tx channel n+8" "0,1" bitfld.quad 0x0 32. "T_PEND8,Masked completion ring pending bit for Tx channel n+8" "0,1" bitfld.quad 0x0 31. "R_ERR7,Masked error bit for Tx channel n+7" "0,1" bitfld.quad 0x0 30. "R_PEND7,Masked completion ring pending bit for Rx channel n+7" "0,1" bitfld.quad 0x0 29. "T_ERR7,Masked error bit for Tx channel n+7" "0,1" newline bitfld.quad 0x0 28. "T_PEND7,Masked completion ring pending bit for Tx channel n+7" "0,1" bitfld.quad 0x0 27. "R_ERR6,Masked error bit for Tx channel n+6" "0,1" bitfld.quad 0x0 26. "R_PEND6,Masked completion ring pending bit for Rx channel n+6" "0,1" bitfld.quad 0x0 25. "T_ERR6,Masked error bit for Tx channel n+6" "0,1" bitfld.quad 0x0 24. "T_PEND6,Masked completion ring pending bit for Tx channel n+6" "0,1" newline bitfld.quad 0x0 23. "R_ERR5,Masked error bit for Tx channel n+5" "0,1" bitfld.quad 0x0 22. "R_PEND5,Masked completion ring pending bit for Rx channel n+5" "0,1" bitfld.quad 0x0 21. "T_ERR5,Masked error bit for Tx channel n+5" "0,1" bitfld.quad 0x0 20. "T_PEND5,Masked completion ring pending bit for Tx channel n+5" "0,1" bitfld.quad 0x0 19. "R_ERR4,Masked error bit for Tx channel n+4" "0,1" newline bitfld.quad 0x0 18. "R_PEND4,Masked completion ring pending bit for Rx channel n+4" "0,1" bitfld.quad 0x0 17. "T_ERR4,Masked error bit for Tx channel n+4" "0,1" bitfld.quad 0x0 16. "T_PEND4,Masked completion ring pending bit for Tx channel n+4" "0,1" bitfld.quad 0x0 15. "R_ERR3,Masked error bit for Tx channel n+3" "0,1" bitfld.quad 0x0 14. "R_PEND3,Masked completion ring pending bit for Rx channel n+3" "0,1" newline bitfld.quad 0x0 13. "T_ERR3,Masked error bit for Tx channel n+3" "0,1" bitfld.quad 0x0 12. "T_PEND3,Masked completion ring pending bit for Tx channel n+3" "0,1" bitfld.quad 0x0 11. "R_ERR2,Masked error bit for Tx channel n+2" "0,1" bitfld.quad 0x0 10. "R_PEND2,Masked completion ring pending bit for Rx channel n+2" "0,1" bitfld.quad 0x0 9. "T_ERR2,Masked error bit for Tx channel n+2" "0,1" newline bitfld.quad 0x0 8. "T_PEND2,Masked completion ring pending bit for Tx channel n+2" "0,1" bitfld.quad 0x0 7. "R_ERR1,Masked error bit for Tx channel n+1" "0,1" bitfld.quad 0x0 6. "R_PEND1,Masked completion ring pending bit for Rx channel n+1" "0,1" bitfld.quad 0x0 5. "T_ERR1,Masked error bit for Tx channel n+1" "0,1" bitfld.quad 0x0 4. "T_PEND1,Masked completion ring pending bit for Tx channel n+1" "0,1" newline bitfld.quad 0x0 3. "R_ERR0,Masked error bit for Tx channel n" "0,1" bitfld.quad 0x0 2. "R_PEND0,Masked completion ring pending bit for Rx channel n" "0,1" bitfld.quad 0x0 1. "T_ERR0,Masked error bit for Tx channel n" "0,1" bitfld.quad 0x0 0. "T_PEND0,Masked completion ring pending bit for Tx channel n" "0,1" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG" base ad:0x2C280000 rgroup.quad 0x0++0x7F line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_atomic_submit_curr_tr_word0_1,The first TR submission word" hexmask.quad.word 0x0 48.--63. 1. "ICNT1,Lines in a transfer" newline hexmask.quad.word 0x0 32.--47. 1. "ICNT0,Bytes in a transfer" newline hexmask.quad.long 0x0 0.--31. 1. "FLAGS,Flags for the operation and type of descriptor" line.quad 0x8 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_atomic_submit_curr_tr_word2_3,The second TR submission word" hexmask.quad 0x8 0.--47. 1. "SRC_ADDR,Source transfer address virtual or physical allowed" line.quad 0x10 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_atomic_submit_curr_tr_word4_5,The third TR submission word" hexmask.quad.word 0x10 48.--63. 1. "ICNT3,The size of the 4th loop in the TR transfer" newline hexmask.quad.word 0x10 32.--47. 1. "ICNT2,The size of the 3rd loop in the TR transfer" newline hexmask.quad.long 0x10 0.--31. 1. "DIM1,The first dimension width of the source data" line.quad 0x18 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_atomic_submit_curr_tr_word6_7,The fourth TR submission word" hexmask.quad.long 0x18 32.--63. 1. "DIM3,The third dimension width of the source data" newline hexmask.quad.long 0x18 0.--31. 1. "DIM2,The second dimension width of the source data" line.quad 0x20 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_atomic_submit_curr_tr_word8_9,The fifth TR submission word" hexmask.quad.long 0x20 32.--63. 1. "DDIM1,The first dimension width of the destination data" newline hexmask.quad.long 0x20 0.--31. 1. "FMTFLAGS,The data formatting flags to be used for the TR" line.quad 0x28 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_atomic_submit_curr_tr_word10_11,The sixth TR submission word" hexmask.quad 0x28 0.--47. 1. "DADDR,Destination transfer address virtual or physical allowed" line.quad 0x30 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_atomic_submit_curr_tr_word12_13,The seventh TR submission word" hexmask.quad.long 0x30 32.--63. 1. "DDIM3,The third dimension width of the destination data" newline hexmask.quad.long 0x30 0.--31. 1. "DDIM2,The second dimension width of the destination data" line.quad 0x38 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_atomic_submit_curr_tr_word14_15,The eight TR submission word" hexmask.quad.word 0x38 48.--63. 1. "DICNT3,The fourth count of the destination if different than the source" newline hexmask.quad.word 0x38 32.--47. 1. "DICNT2,The third count of the destination if different than the source" newline hexmask.quad.word 0x38 16.--31. 1. "DICNT1,The second innermost count of the destination if different than the source" newline hexmask.quad.word 0x38 0.--15. 1. "DICNT0,The innermost count of the destination if different than the source" line.quad 0x40 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_next_tr_word0_1,The first TR submission word" hexmask.quad.word 0x40 48.--63. 1. "ICNT1,Lines in a transfer" newline hexmask.quad.word 0x40 32.--47. 1. "ICNT0,Bytes in a transfer" newline hexmask.quad.long 0x40 0.--31. 1. "FLAGS,Flags for the operation and type of descriptor" line.quad 0x48 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_next_tr_word2_3,The second TR submission word" hexmask.quad 0x48 0.--47. 1. "SRC_ADDR,Source transfer address virtual or physical allowed" line.quad 0x50 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_next_tr_word4_5,The third TR submission word" hexmask.quad.word 0x50 48.--63. 1. "ICNT3,The size of the 4th loop in the TR transfer" newline hexmask.quad.word 0x50 32.--47. 1. "ICNT2,The size of the 3rd loop in the TR transfer" newline hexmask.quad.long 0x50 0.--31. 1. "DIM1,The first dimension width of the source data" line.quad 0x58 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_next_tr_word6_7,The fourth TR submission word" hexmask.quad.long 0x58 32.--63. 1. "DIM3,The third dimension width of the source data" newline hexmask.quad.long 0x58 0.--31. 1. "DIM2,The second dimension width of the source data" line.quad 0x60 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_next_tr_word8_9,The fifth TR submission word" hexmask.quad.long 0x60 32.--63. 1. "DDIM1,The first dimension width of the destination data" newline hexmask.quad.long 0x60 0.--31. 1. "FMTFLAGS,The data formatting flags to be used for the TR" line.quad 0x68 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_next_tr_word10_11,The sixth TR submission word" hexmask.quad 0x68 0.--47. 1. "DADDR,Destination transfer address virtual or physical allowed" line.quad 0x70 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_next_tr_word12_13,The seventh TR submission word" hexmask.quad.long 0x70 32.--63. 1. "DDIM3,The third dimension width of the destination data" newline hexmask.quad.long 0x70 0.--31. 1. "DDIM2,The second dimension width of the destination data" line.quad 0x78 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHATOMIC_DEBUG_next_tr_word14_15,The eight TR submission word" hexmask.quad.word 0x78 48.--63. 1. "DICNT3,The fourth count of the destination if different than the source" newline hexmask.quad.word 0x78 32.--47. 1. "DICNT2,The third count of the destination if different than the source" newline hexmask.quad.word 0x78 16.--31. 1. "DICNT1,The second innermost count of the destination if different than the source" newline hexmask.quad.word 0x78 0.--15. 1. "DICNT0,The innermost count of the destination if different than the source" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT" base ad:0x2C240000 group.quad 0x0++0x7 line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHNRT_cfg,Channel Configuration Register. The Channel Configuration Register is used to initialize static mode settings for the DMA Channel. The register may only be written when the chanel is.." bitfld.quad 0x0 31. "PAUSE_ON_ERR,Pause on Error. This field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW to.." "0: Channel will drop current work and move on,1: Channel will pause and wait for SW to.." newline bitfld.quad 0x0 19. "CHAN_TYPE_OWNER,This field controls how the TR is received by the UTC. If it is 0 then the SUBMISSION registers must be written to submit it. If it is a 1 then the TR will be received through PSIL." "0,1" newline rbitfld.quad 0x0 16.--18. "CHAN_TYPE,This field states the TR type that is being used it along with CHAN_TYPE_OWNER field make up the 4 bit CHAN_TYPE for a KS3 DMA UTC. The value of this is all zeroes. To reflect that the UTC DRU only does TRs through pass by value mechanisms." "0,1,2,3,4,5,6,7" group.quad 0x20++0x7 line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHNRT_choes0,The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event.." hexmask.quad.word 0x0 32.--47. 1. "RRING_EVT_NUM" newline hexmask.quad.word 0x0 16.--31. 1. "FRING_EVT_NUM" newline hexmask.quad.word 0x0 0.--15. 1. "EVT_NUM,This is the global event number to be generated." group.quad 0x40++0xF line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHNRT_chring_addr,The Ring Base Address Register contains the base address for the ring which is used to hand off pending work for the channel from the Host. The base address must be aligned.." hexmask.quad.byte 0x0 48.--51. 1. "ASEL,Ring base address select" newline hexmask.quad 0x0 0.--35. 1. "ADDR,Ring base address" line.quad 0x8 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHNRT_chring_size,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the.." rbitfld.quad 0x8 29.--31. "QMODE,Defines the mode for this ring or queue." "0,1,2,3,4,5,6,7" newline rbitfld.quad 0x8 24.--26. "RING_ELSIZE" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x8 0.--15. 1. "SIZE,Tx Ring element count. This field configures the size of the ring in elements." group.quad 0x60++0x7 line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHNRT_chst_sched,Channel Static Scheduler Config Register" bitfld.quad 0x0 0.--1. "QUEUE,This is the queue number that is written" "0,1,2,3" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHRT" base ad:0x2C260000 group.quad 0x0++0xF line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_ctl,The channel realtime control register contains real-time cotrol and status information for the DMA Channel. The fields in this regsiter can be changed while the channel is in.." bitfld.quad 0x0 31. "ENABLE,This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the.." "0: channel is disabled,1: channel is enabled This field will be cleared.." newline bitfld.quad 0x0 30. "TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete." "0,1" newline bitfld.quad 0x0 29. "PAUSE,Channel pause: Setting this bit will request the channel to pause processing at the next packet boundary. This is a more graceful method of halting processing than disabling the channel as it will not allow any current packets to underflow." "0,1" newline bitfld.quad 0x0 28. "FORCED_TEARDOWN,Channel forced teardown: Setting this bit will request the channel to be torn down forcefulyy. This field will clear after a channel teardown is complete." "0,1" line.quad 0x8 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_swtrig,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way." bitfld.quad 0x8 2. "LOCAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel. This will trigger LOCAL Event" "0,1" newline bitfld.quad 0x8 1. "GLOBAL_TRIGGER1,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel. This will trigger Global Event 1" "0,1" newline bitfld.quad 0x8 0. "GLOBAL_TRIGGER0,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel. This will trigger Global Event 0" "0,1" rgroup.quad 0x10++0xF line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_status_det,The channel status details" bitfld.quad 0x0 63. "CH_ACTIVE,The channel has some active work" "0,1" newline bitfld.quad 0x0 62. "WR_ACTIVE,The top TR has submitted a sub-TR to the write portion of the queue" "0,1" newline bitfld.quad 0x0 61. "RD_ACTIVE,The top TR has submitted a sub-TR to the read portion of the queue" "0,1" newline hexmask.quad.byte 0x0 24.--31. 1. "TR_IN_QUEUE_CNT,The number of TRs for the channel that are in the queue FIFO" newline hexmask.quad.byte 0x0 16.--23. 1. "TR_CNT,The number of TRs in the channel FIFO" newline hexmask.quad.byte 0x0 8.--15. 1. "CMD_ID,The last cmd_id given to the write queue" newline hexmask.quad.byte 0x0 4.--7. 1. "INFO,The info of the error that was received" newline hexmask.quad.byte 0x0 0.--3. 1. "STATUS_TYPE,The type of error that was received" line.quad 0x8 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_status_cnt,The channel count details" hexmask.quad.word 0x8 48.--63. 1. "ICNT3,The last icnt3 given to the write queue" newline hexmask.quad.word 0x8 32.--47. 1. "ICNT2,The last icnt2 given to the write queue" newline hexmask.quad.word 0x8 16.--31. 1. "ICNT1,The last icnt1 given to the write queue" newline hexmask.quad.word 0x8 0.--15. 1. "ICNT0,The last icnt0 given to the write queue" wgroup.quad 0x20++0x7 line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_ring_fwd_db,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field.." hexmask.quad.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.quad 0x28++0x7 line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_ring_fwd_occ,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed.." hexmask.quad.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." wgroup.quad 0x40++0x7 line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_ring_rvrs_db,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring. One or more entries as specified by the entry_cnt field.." bitfld.quad 0x0 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register. this bit is only valid on the reverse rings (rings consumed by the Host SW)" "0,1" newline hexmask.quad.byte 0x0 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ.." rgroup.quad 0x48++0x7 line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHRT_chrt_ring_rvrs_occ,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring. The contents of each of these registers are unary ORed.." bitfld.quad 0x0 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel. This bit is cleared anytime the tdown_ack bit is written as a 1 in the corresponding Ring N Doorbell Register. This bit is only valid on the reverse rings (rings.." "0,1" newline hexmask.quad.tbyte 0x0 0.--16. 1. "OCC,Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed." tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE" base ad:0x2C208000 group.quad 0x0++0x7 line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_QUEUE_cfg,Configuration Register for Queue 0" hexmask.quad.long 0x0 32.--63. 1. "RSVD,Reserved." hexmask.quad.byte 0x0 24.--31. 1. "REARB_WAIT,This is the number of commands that will be sent by other queues before allowing the queue to arbitrate again for the right to send commands. This is only started when a queue exhausted its consecutive trans count." newline hexmask.quad.byte 0x0 16.--23. 1. "CONSECUTIVE_TRANS,This is the number of consecutive transactions that will be sent before allowing another queue of equal level to arbitrate to send commands. This is the maximum number of commands that it can send. If the queue has any delays such as.." bitfld.quad 0x0 8.--10. "QOS,This configures the QOS for QUEUE0. This should only be set for fixed priority queues and the lower queue should have the lower QoS." "0,1,2,3,4,5,6,7" newline hexmask.quad.byte 0x0 4.--7. 1. "ORDERID,This configures the orderid for QUEUE0." bitfld.quad 0x0 0.--2. "PRI,This configures the priority for QUEUE0. This will be the priority that will be presented on the External bus for all commands from this queue." "0,1,2,3,4,5,6,7" rgroup.quad 0x40++0x7 line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_QUEUE_status,Status Register for Queue 0" hexmask.quad.word 0x0 27.--35. 1. "RD_TOTAL,This is the channel that the read half is currently working on." hexmask.quad.word 0x0 18.--26. 1. "RD_TOP,This is the channel that the read half is currently working on." newline hexmask.quad.word 0x0 9.--17. 1. "WR_TOTAL,This is the channel that the read half is currently working on." hexmask.quad.word 0x0 0.--8. 1. "WR_TOP,This is the channel that the write half is currently working on." tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_SET" base ad:0x2C204000 wgroup.quad 0x0++0x7 line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_SET_dru_shared_evt_set,DRU Shared Event Set Register" bitfld.quad 0x0 0. "PROT_ERR,Set the Prot Error event" "0,1" wgroup.quad 0x40++0x7 line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_SET_dru_comp_evt_set0,DRU Completion Event Set Register" bitfld.quad 0x0 63. "COMP_EVT63,Set the Completion Event for channel 63" "0,1" bitfld.quad 0x0 62. "COMP_EVT62,Set the Completion Event for channel 62" "0,1" bitfld.quad 0x0 61. "COMP_EVT61,Set the Completion Event for channel 61" "0,1" bitfld.quad 0x0 60. "COMP_EVT60,Set the Completion Event for channel 60" "0,1" newline bitfld.quad 0x0 59. "COMP_EVT59,Set the Completion Event for channel 59" "0,1" bitfld.quad 0x0 58. "COMP_EVT58,Set the Completion Event for channel 58" "0,1" bitfld.quad 0x0 57. "COMP_EVT57,Set the Completion Event for channel 57" "0,1" bitfld.quad 0x0 56. "COMP_EVT56,Set the Completion Event for channel 56" "0,1" newline bitfld.quad 0x0 55. "COMP_EVT55,Set the Completion Event for channel 55" "0,1" bitfld.quad 0x0 54. "COMP_EVT54,Set the Completion Event for channel 54" "0,1" bitfld.quad 0x0 53. "COMP_EVT53,Set the Completion Event for channel 53" "0,1" bitfld.quad 0x0 52. "COMP_EVT52,Set the Completion Event for channel 52" "0,1" newline bitfld.quad 0x0 51. "COMP_EVT51,Set the Completion Event for channel 51" "0,1" bitfld.quad 0x0 50. "COMP_EVT50,Set the Completion Event for channel 50" "0,1" bitfld.quad 0x0 49. "COMP_EVT49,Set the Completion Event for channel 49" "0,1" bitfld.quad 0x0 48. "COMP_EVT48,Set the Completion Event for channel 48" "0,1" newline bitfld.quad 0x0 47. "COMP_EVT47,Set the Completion Event for channel 47" "0,1" bitfld.quad 0x0 46. "COMP_EVT46,Set the Completion Event for channel 46" "0,1" bitfld.quad 0x0 45. "COMP_EVT45,Set the Completion Event for channel 45" "0,1" bitfld.quad 0x0 44. "COMP_EVT44,Set the Completion Event for channel 44" "0,1" newline bitfld.quad 0x0 43. "COMP_EVT43,Set the Completion Event for channel 43" "0,1" bitfld.quad 0x0 42. "COMP_EVT42,Set the Completion Event for channel 42" "0,1" bitfld.quad 0x0 41. "COMP_EVT41,Set the Completion Event for channel 41" "0,1" bitfld.quad 0x0 40. "COMP_EVT40,Set the Completion Event for channel 40" "0,1" newline bitfld.quad 0x0 39. "COMP_EVT39,Set the Completion Event for channel 39" "0,1" bitfld.quad 0x0 38. "COMP_EVT38,Set the Completion Event for channel 38" "0,1" bitfld.quad 0x0 37. "COMP_EVT37,Set the Completion Event for channel 37" "0,1" bitfld.quad 0x0 36. "COMP_EVT36,Set the Completion Event for channel 36" "0,1" newline bitfld.quad 0x0 35. "COMP_EVT35,Set the Completion Event for channel 35" "0,1" bitfld.quad 0x0 34. "COMP_EVT34,Set the Completion Event for channel 34" "0,1" bitfld.quad 0x0 33. "COMP_EVT33,Set the Completion Event for channel 33" "0,1" bitfld.quad 0x0 32. "COMP_EVT32,Set the Completion Event for channel 32" "0,1" newline bitfld.quad 0x0 31. "COMP_EVT31,Set the Completion Event for channel 31" "0,1" bitfld.quad 0x0 30. "COMP_EVT30,Set the Completion Event for channel 30" "0,1" bitfld.quad 0x0 29. "COMP_EVT29,Set the Completion Event for channel 29" "0,1" bitfld.quad 0x0 28. "COMP_EVT28,Set the Completion Event for channel 28" "0,1" newline bitfld.quad 0x0 27. "COMP_EVT27,Set the Completion Event for channel 27" "0,1" bitfld.quad 0x0 26. "COMP_EVT26,Set the Completion Event for channel 26" "0,1" bitfld.quad 0x0 25. "COMP_EVT25,Set the Completion Event for channel 25" "0,1" bitfld.quad 0x0 24. "COMP_EVT24,Set the Completion Event for channel 24" "0,1" newline bitfld.quad 0x0 23. "COMP_EVT23,Set the Completion Event for channel 23" "0,1" bitfld.quad 0x0 22. "COMP_EVT22,Set the Completion Event for channel 22" "0,1" bitfld.quad 0x0 21. "COMP_EVT21,Set the Completion Event for channel 21" "0,1" bitfld.quad 0x0 20. "COMP_EVT20,Set the Completion Event for channel 20" "0,1" newline bitfld.quad 0x0 19. "COMP_EVT19,Set the Completion Event for channel 19" "0,1" bitfld.quad 0x0 18. "COMP_EVT18,Set the Completion Event for channel 18" "0,1" bitfld.quad 0x0 17. "COMP_EVT17,Set the Completion Event for channel 17" "0,1" bitfld.quad 0x0 16. "COMP_EVT16,Set the Completion Event for channel 16" "0,1" newline bitfld.quad 0x0 15. "COMP_EVT15,Set the Completion Event for channel 15" "0,1" bitfld.quad 0x0 14. "COMP_EVT14,Set the Completion Event for channel 14" "0,1" bitfld.quad 0x0 13. "COMP_EVT13,Set the Completion Event for channel 13" "0,1" bitfld.quad 0x0 12. "COMP_EVT12,Set the Completion Event for channel 12" "0,1" newline bitfld.quad 0x0 11. "COMP_EVT11,Set the Completion Event for channel 11" "0,1" bitfld.quad 0x0 10. "COMP_EVT10,Set the Completion Event for channel 10" "0,1" bitfld.quad 0x0 9. "COMP_EVT9,Set the Completion Event for channel 9" "0,1" bitfld.quad 0x0 8. "COMP_EVT8,Set the Completion Event for channel 8" "0,1" newline bitfld.quad 0x0 7. "COMP_EVT7,Set the Completion Event for channel 7" "0,1" bitfld.quad 0x0 6. "COMP_EVT6,Set the Completion Event for channel 6" "0,1" bitfld.quad 0x0 5. "COMP_EVT5,Set the Completion Event for channel 5" "0,1" bitfld.quad 0x0 4. "COMP_EVT4,Set the Completion Event for channel 4" "0,1" newline bitfld.quad 0x0 3. "COMP_EVT3,Set the Completion Event for channel 3" "0,1" bitfld.quad 0x0 2. "COMP_EVT2,Set the Completion Event for channel 2" "0,1" bitfld.quad 0x0 1. "COMP_EVT1,Set the Completion Event for channel 1" "0,1" bitfld.quad 0x0 0. "COMP_EVT0,Set the Completion Event for channel 0" "0,1" wgroup.quad 0x80++0x7 line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_SET_dru_err_evt_set0,DRU Error Event Set Register" bitfld.quad 0x0 63. "ERR_EVT63,Set the Error Event for channel 63" "0,1" bitfld.quad 0x0 62. "ERR_EVT62,Set the Error Event for channel 62" "0,1" bitfld.quad 0x0 61. "ERR_EVT61,Set the Error Event for channel 61" "0,1" bitfld.quad 0x0 60. "ERR_EVT60,Set the Error Event for channel 60" "0,1" newline bitfld.quad 0x0 59. "ERR_EVT59,Set the Error Event for channel 59" "0,1" bitfld.quad 0x0 58. "ERR_EVT58,Set the Error Event for channel 58" "0,1" bitfld.quad 0x0 57. "ERR_EVT57,Set the Error Event for channel 57" "0,1" bitfld.quad 0x0 56. "ERR_EVT56,Set the Error Event for channel 56" "0,1" newline bitfld.quad 0x0 55. "ERR_EVT55,Set the Error Event for channel 55" "0,1" bitfld.quad 0x0 54. "ERR_EVT54,Set the Error Event for channel 54" "0,1" bitfld.quad 0x0 53. "ERR_EVT53,Set the Error Event for channel 53" "0,1" bitfld.quad 0x0 52. "ERR_EVT52,Set the Error Event for channel 52" "0,1" newline bitfld.quad 0x0 51. "ERR_EVT51,Set the Error Event for channel 51" "0,1" bitfld.quad 0x0 50. "ERR_EVT50,Set the Error Event for channel 50" "0,1" bitfld.quad 0x0 49. "ERR_EVT49,Set the Error Event for channel 49" "0,1" bitfld.quad 0x0 48. "ERR_EVT48,Set the Error Event for channel 48" "0,1" newline bitfld.quad 0x0 47. "ERR_EVT47,Set the Error Event for channel 47" "0,1" bitfld.quad 0x0 46. "ERR_EVT46,Set the Error Event for channel 46" "0,1" bitfld.quad 0x0 45. "ERR_EVT45,Set the Error Event for channel 45" "0,1" bitfld.quad 0x0 44. "ERR_EVT44,Set the Error Event for channel 44" "0,1" newline bitfld.quad 0x0 43. "ERR_EVT43,Set the Error Event for channel 43" "0,1" bitfld.quad 0x0 42. "ERR_EVT42,Set the Error Event for channel 42" "0,1" bitfld.quad 0x0 41. "ERR_EVT41,Set the Error Event for channel 41" "0,1" bitfld.quad 0x0 40. "ERR_EVT40,Set the Error Event for channel 40" "0,1" newline bitfld.quad 0x0 39. "ERR_EVT39,Set the Error Event for channel 39" "0,1" bitfld.quad 0x0 38. "ERR_EVT38,Set the Error Event for channel 38" "0,1" bitfld.quad 0x0 37. "ERR_EVT37,Set the Error Event for channel 37" "0,1" bitfld.quad 0x0 36. "ERR_EVT36,Set the Error Event for channel 36" "0,1" newline bitfld.quad 0x0 35. "ERR_EVT35,Set the Error Event for channel 35" "0,1" bitfld.quad 0x0 34. "ERR_EVT34,Set the Error Event for channel 34" "0,1" bitfld.quad 0x0 33. "ERR_EVT33,Set the Error Event for channel 33" "0,1" bitfld.quad 0x0 32. "ERR_EVT32,Set the Error Event for channel 32" "0,1" newline bitfld.quad 0x0 31. "ERR_EVT31,Set the Error Event for channel 31" "0,1" bitfld.quad 0x0 30. "ERR_EVT30,Set the Error Event for channel 30" "0,1" bitfld.quad 0x0 29. "ERR_EVT29,Set the Error Event for channel 29" "0,1" bitfld.quad 0x0 28. "ERR_EVT28,Set the Error Event for channel 28" "0,1" newline bitfld.quad 0x0 27. "ERR_EVT27,Set the Error Event for channel 27" "0,1" bitfld.quad 0x0 26. "ERR_EVT26,Set the Error Event for channel 26" "0,1" bitfld.quad 0x0 25. "ERR_EVT25,Set the Error Event for channel 25" "0,1" bitfld.quad 0x0 24. "ERR_EVT24,Set the Error Event for channel 24" "0,1" newline bitfld.quad 0x0 23. "ERR_EVT23,Set the Error Event for channel 23" "0,1" bitfld.quad 0x0 22. "ERR_EVT22,Set the Error Event for channel 22" "0,1" bitfld.quad 0x0 21. "ERR_EVT21,Set the Error Event for channel 21" "0,1" bitfld.quad 0x0 20. "ERR_EVT20,Set the Error Event for channel 20" "0,1" newline bitfld.quad 0x0 19. "ERR_EVT19,Set the Error Event for channel 19" "0,1" bitfld.quad 0x0 18. "ERR_EVT18,Set the Error Event for channel 18" "0,1" bitfld.quad 0x0 17. "ERR_EVT17,Set the Error Event for channel 17" "0,1" bitfld.quad 0x0 16. "ERR_EVT16,Set the Error Event for channel 16" "0,1" newline bitfld.quad 0x0 15. "ERR_EVT15,Set the Error Event for channel 15" "0,1" bitfld.quad 0x0 14. "ERR_EVT14,Set the Error Event for channel 14" "0,1" bitfld.quad 0x0 13. "ERR_EVT13,Set the Error Event for channel 13" "0,1" bitfld.quad 0x0 12. "ERR_EVT12,Set the Error Event for channel 12" "0,1" newline bitfld.quad 0x0 11. "ERR_EVT11,Set the Error Event for channel 11" "0,1" bitfld.quad 0x0 10. "ERR_EVT10,Set the Error Event for channel 10" "0,1" bitfld.quad 0x0 9. "ERR_EVT9,Set the Error Event for channel 9" "0,1" bitfld.quad 0x0 8. "ERR_EVT8,Set the Error Event for channel 8" "0,1" newline bitfld.quad 0x0 7. "ERR_EVT7,Set the Error Event for channel 7" "0,1" bitfld.quad 0x0 6. "ERR_EVT6,Set the Error Event for channel 6" "0,1" bitfld.quad 0x0 5. "ERR_EVT5,Set the Error Event for channel 5" "0,1" bitfld.quad 0x0 4. "ERR_EVT4,Set the Error Event for channel 4" "0,1" newline bitfld.quad 0x0 3. "ERR_EVT3,Set the Error Event for channel 3" "0,1" bitfld.quad 0x0 2. "ERR_EVT2,Set the Error Event for channel 2" "0,1" bitfld.quad 0x0 1. "ERR_EVT1,Set the Error Event for channel 1" "0,1" bitfld.quad 0x0 0. "ERR_EVT0,Set the Error Event for channel 0" "0,1" wgroup.quad 0xC0++0x7 line.quad 0x0 "IVPAC_TOP_0__CFG_SLV__DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_SET_dru_local_evt_set0,DRU Local Event Set Register" bitfld.quad 0x0 63. "COMP_EVT63,Set the Local Event for channel 63" "0,1" bitfld.quad 0x0 62. "COMP_EVT62,Set the Local Event for channel 62" "0,1" bitfld.quad 0x0 61. "COMP_EVT61,Set the Local Event for channel 61" "0,1" bitfld.quad 0x0 60. "COMP_EVT60,Set the Local Event for channel 60" "0,1" newline bitfld.quad 0x0 59. "COMP_EVT59,Set the Local Event for channel 59" "0,1" bitfld.quad 0x0 58. "COMP_EVT58,Set the Local Event for channel 58" "0,1" bitfld.quad 0x0 57. "COMP_EVT57,Set the Local Event for channel 57" "0,1" bitfld.quad 0x0 56. "COMP_EVT56,Set the Local Event for channel 56" "0,1" newline bitfld.quad 0x0 55. "COMP_EVT55,Set the Local Event for channel 55" "0,1" bitfld.quad 0x0 54. "COMP_EVT54,Set the Local Event for channel 54" "0,1" bitfld.quad 0x0 53. "COMP_EVT53,Set the Local Event for channel 53" "0,1" bitfld.quad 0x0 52. "COMP_EVT52,Set the Local Event for channel 52" "0,1" newline bitfld.quad 0x0 51. "COMP_EVT51,Set the Local Event for channel 51" "0,1" bitfld.quad 0x0 50. "COMP_EVT50,Set the Local Event for channel 50" "0,1" bitfld.quad 0x0 49. "COMP_EVT49,Set the Local Event for channel 49" "0,1" bitfld.quad 0x0 48. "COMP_EVT48,Set the Local Event for channel 48" "0,1" newline bitfld.quad 0x0 47. "COMP_EVT47,Set the Local Event for channel 47" "0,1" bitfld.quad 0x0 46. "COMP_EVT46,Set the Local Event for channel 46" "0,1" bitfld.quad 0x0 45. "COMP_EVT45,Set the Local Event for channel 45" "0,1" bitfld.quad 0x0 44. "COMP_EVT44,Set the Local Event for channel 44" "0,1" newline bitfld.quad 0x0 43. "COMP_EVT43,Set the Local Event for channel 43" "0,1" bitfld.quad 0x0 42. "COMP_EVT42,Set the Local Event for channel 42" "0,1" bitfld.quad 0x0 41. "COMP_EVT41,Set the Local Event for channel 41" "0,1" bitfld.quad 0x0 40. "COMP_EVT40,Set the Local Event for channel 40" "0,1" newline bitfld.quad 0x0 39. "COMP_EVT39,Set the Local Event for channel 39" "0,1" bitfld.quad 0x0 38. "COMP_EVT38,Set the Local Event for channel 38" "0,1" bitfld.quad 0x0 37. "COMP_EVT37,Set the Local Event for channel 37" "0,1" bitfld.quad 0x0 36. "COMP_EVT36,Set the Local Event for channel 36" "0,1" newline bitfld.quad 0x0 35. "COMP_EVT35,Set the Local Event for channel 35" "0,1" bitfld.quad 0x0 34. "COMP_EVT34,Set the Local Event for channel 34" "0,1" bitfld.quad 0x0 33. "COMP_EVT33,Set the Local Event for channel 33" "0,1" bitfld.quad 0x0 32. "COMP_EVT32,Set the Local Event for channel 32" "0,1" newline bitfld.quad 0x0 31. "COMP_EVT31,Set the Local Event for channel 31" "0,1" bitfld.quad 0x0 30. "COMP_EVT30,Set the Local Event for channel 30" "0,1" bitfld.quad 0x0 29. "COMP_EVT29,Set the Local Event for channel 29" "0,1" bitfld.quad 0x0 28. "COMP_EVT28,Set the Local Event for channel 28" "0,1" newline bitfld.quad 0x0 27. "COMP_EVT27,Set the Local Event for channel 27" "0,1" bitfld.quad 0x0 26. "COMP_EVT26,Set the Local Event for channel 26" "0,1" bitfld.quad 0x0 25. "COMP_EVT25,Set the Local Event for channel 25" "0,1" bitfld.quad 0x0 24. "COMP_EVT24,Set the Local Event for channel 24" "0,1" newline bitfld.quad 0x0 23. "COMP_EVT23,Set the Local Event for channel 23" "0,1" bitfld.quad 0x0 22. "COMP_EVT22,Set the Local Event for channel 22" "0,1" bitfld.quad 0x0 21. "COMP_EVT21,Set the Local Event for channel 21" "0,1" bitfld.quad 0x0 20. "COMP_EVT20,Set the Local Event for channel 20" "0,1" newline bitfld.quad 0x0 19. "COMP_EVT19,Set the Local Event for channel 19" "0,1" bitfld.quad 0x0 18. "COMP_EVT18,Set the Local Event for channel 18" "0,1" bitfld.quad 0x0 17. "COMP_EVT17,Set the Local Event for channel 17" "0,1" bitfld.quad 0x0 16. "COMP_EVT16,Set the Local Event for channel 16" "0,1" newline bitfld.quad 0x0 15. "COMP_EVT15,Set the Local Event for channel 15" "0,1" bitfld.quad 0x0 14. "COMP_EVT14,Set the Local Event for channel 14" "0,1" bitfld.quad 0x0 13. "COMP_EVT13,Set the Local Event for channel 13" "0,1" bitfld.quad 0x0 12. "COMP_EVT12,Set the Local Event for channel 12" "0,1" newline bitfld.quad 0x0 11. "COMP_EVT11,Set the Local Event for channel 11" "0,1" bitfld.quad 0x0 10. "COMP_EVT10,Set the Local Event for channel 10" "0,1" bitfld.quad 0x0 9. "COMP_EVT9,Set the Local Event for channel 9" "0,1" bitfld.quad 0x0 8. "COMP_EVT8,Set the Local Event for channel 8" "0,1" newline bitfld.quad 0x0 7. "COMP_EVT7,Set the Local Event for channel 7" "0,1" bitfld.quad 0x0 6. "COMP_EVT6,Set the Local Event for channel 6" "0,1" bitfld.quad 0x0 5. "COMP_EVT5,Set the Local Event for channel 5" "0,1" bitfld.quad 0x0 4. "COMP_EVT4,Set the Local Event for channel 4" "0,1" newline bitfld.quad 0x0 3. "COMP_EVT3,Set the Local Event for channel 3" "0,1" bitfld.quad 0x0 2. "COMP_EVT2,Set the Local Event for channel 2" "0,1" bitfld.quad 0x0 1. "COMP_EVT1,Set the Local Event for channel 1" "0,1" bitfld.quad 0x0 0. "COMP_EVT0,Set the Local Event for channel 0" "0,1" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_HTS_S_VBUSP" base ad:0x2C010000 group.long 0x0++0x1B line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_pipeline_control_0,Enable pipeline to activate all connected scheduler" bitfld.long 0x0 2.--4. "HW_EN_EVTSELECT,Hw triggered pipeline enable on internally generated hts_event[hw_en_evtselect]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1. "HW_EN,Hw event triggerred Pipeline 0 enable '1': activate pipeline to receive hw event as described in hw_en_evtselect and hts_event_gen.evt_select '0' : hw event based pipeline is not enabled" "0: hw event based pipeline is not enabled,1: activate pipeline to receive hw event as.." newline bitfld.long 0x0 0. "PIPE_EN,Pipeline 0 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0: pipeline is inactive,1: pipeline is active" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_pipeline_control_1,Enable pipeline to activate all connected scheduler" bitfld.long 0x4 2.--4. "HW_EN_EVTSELECT,Hw triggered pipeline enable on internally generated hts_event[hw_en_evtselect]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 1. "HW_EN,Hw event triggerred Pipeline 1 enable '1': activate pipeline to receive hw event as described in hw_en_evtselect and hts_event_gen.evt_select '0' : hw event based pipeline is not enabled" "0: hw event based pipeline is not enabled,1: activate pipeline to receive hw event as.." newline bitfld.long 0x4 0. "PIPE_EN,Pipeline 1 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0: pipeline is inactive,1: pipeline is active" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_pipeline_control_2,Enable pipeline to activate all connected scheduler" bitfld.long 0x8 2.--4. "HW_EN_EVTSELECT,Hw triggered pipeline enable on internally generated hts_event[hw_en_evtselect]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 1. "HW_EN,Hw event triggerred Pipeline 2 enable '1': activate pipeline to receive hw event as described in hw_en_evtselect and hts_event_gen.evt_select '0' : hw event based pipeline is not enabled" "0: hw event based pipeline is not enabled,1: activate pipeline to receive hw event as.." newline bitfld.long 0x8 0. "PIPE_EN,Pipeline 2 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0: pipeline is inactive,1: pipeline is active" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_pipeline_control_3,Enable pipeline to activate all connected scheduler" bitfld.long 0xC 2.--4. "HW_EN_EVTSELECT,Hw triggered pipeline enable on internally generated hts_event[hw_en_evtselect]" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 1. "HW_EN,Hw event triggerred Pipeline 3 enable '1': activate pipeline to receive hw event as described in hw_en_evtselect and hts_event_gen.evt_select '0' : hw event based pipeline is not enabled" "0: hw event based pipeline is not enabled,1: activate pipeline to receive hw event as.." newline bitfld.long 0xC 0. "PIPE_EN,Pipeline 3 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0: pipeline is inactive,1: pipeline is active" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_pipeline_control_4,Enable pipeline to activate all connected scheduler" bitfld.long 0x10 2.--4. "HW_EN_EVTSELECT,Hw triggered pipeline enable on internally generated hts_event[hw_en_evtselect]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 1. "HW_EN,Hw event triggerred Pipeline 4 enable '1': activate pipeline to receive hw event as described in hw_en_evtselect and hts_event_gen.evt_select '0' : hw event based pipeline is not enabled" "0: hw event based pipeline is not enabled,1: activate pipeline to receive hw event as.." newline bitfld.long 0x10 0. "PIPE_EN,Pipeline 4 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0: pipeline is inactive,1: pipeline is active" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_pipeline_control_5,Enable pipeline to activate all connected scheduler" bitfld.long 0x14 2.--4. "HW_EN_EVTSELECT,Hw triggered pipeline enable on internally generated hts_event[hw_en_evtselect]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 1. "HW_EN,Hw event triggerred Pipeline 5 enable '1': activate pipeline to receive hw event as described in hw_en_evtselect and hts_event_gen.evt_select '0' : hw event based pipeline is not enabled" "0: hw event based pipeline is not enabled,1: activate pipeline to receive hw event as.." newline bitfld.long 0x14 0. "PIPE_EN,Pipeline 5 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0: pipeline is inactive,1: pipeline is active" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_pipeline_control_6,Enable pipeline to activate all connected scheduler" bitfld.long 0x18 2.--4. "HW_EN_EVTSELECT,Hw triggered pipeline enable on internally generated hts_event[hw_en_evtselect]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 1. "HW_EN,Hw event triggerred Pipeline 6 enable '1': activate pipeline to receive hw event as described in hw_en_evtselect and hts_event_gen.evt_select '0' : hw event based pipeline is not enabled" "0: hw event based pipeline is not enabled,1: activate pipeline to receive hw event as.." newline bitfld.long 0x18 0. "PIPE_EN,Pipeline 6 enable writing '1' activate pipeline writing '0' during active pipeline is illegal and behavior is undefined read '1' -> pipeline is active read '0' -> pipeline is inactive" "0: pipeline is inactive,1: pipeline is active" rgroup.long 0x40++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_PID,HTS PID" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme. Spare bit to encode future schemes" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new FUNC number and hence PID should be assigned." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version. R as described in PDR with additional clarifications and definitions below. Must be easily ECO-able or controlled during fabrication. Ideally through a top level metal mask or e-fuse. This number is maintained/owned by IP design.." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision. X as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. X is part of IP numbering X.Y.R.Z. X changes ONLY when: (1) There is a major feature addition. An.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. 0 if non-custom." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision. Y as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. Y changes ONLY when: (1) Features are scaled (up or down). Flexibility exists in that this.." group.long 0x48++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_pipe_dbg_cntl,Pipeline Debug Control register is used by debug software to control pipeline debug behavior" rbitfld.long 0x0 17.--19. "DEBUG_STATE,Current state of Debug activity" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "ABORT_DEBUG,'1' -> Abort Debug activity on debug enabled pipelines '0' no impact" "?,1: Abort Debug activity on debug enabled pipelines" newline bitfld.long 0x0 6. "PIPE_DBG_DIS_6,'1' -> Pipeline6 doesn't respond to debug events '0' Pipeline5 respond to debug events" "?,1: Pipeline6 doesn't respond to debug events" newline bitfld.long 0x0 5. "PIPE_DBG_DIS_5,'1' -> Pipeline5 doesn't respond to debug events '0' Pipeline5 respond to debug events" "?,1: Pipeline5 doesn't respond to debug events" newline bitfld.long 0x0 4. "PIPE_DBG_DIS_4,'1' -> Pipeline4 doesn't respond to debug events '0' Pipeline4 respond to debug events" "?,1: Pipeline4 doesn't respond to debug events" newline bitfld.long 0x0 3. "PIPE_DBG_DIS_3,'1' -> Pipeline3 doesn't respond to debug events '0' Pipeline3 respond to debug events" "?,1: Pipeline3 doesn't respond to debug events" newline bitfld.long 0x0 2. "PIPE_DBG_DIS_2,'1' -> Pipeline2 doesn't respond to debug events '0' Pipeline2 respond to debug events" "?,1: Pipeline2 doesn't respond to debug events" newline bitfld.long 0x0 1. "PIPE_DBG_DIS_1,'1' -> Pipeline1 doesn't respond to debug events '0' Pipeline1 respond to debug events" "?,1: Pipeline1 doesn't respond to debug events" newline bitfld.long 0x0 0. "PIPE_DBG_DIS_0,'1' -> Pipeline0 doesn't respond to debug events '0' Pipeline0 respond to debug events" "?,1: Pipeline0 doesn't respond to debug events" rgroup.long 0x4C++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_dbg_cap,Debug Capability register is used by debug software to determine which optional debug modules are present and how many instances of each module exist." bitfld.long 0x0 30. "DBG_INT_STEP_SUP,Indicates that debug execution control can determine if single step blocks or allows interrupts. b0 No step/interrupt control b1 Step interrupt control via DBG_INT_STEP_IN" "0,1" newline bitfld.long 0x0 29. "DBG_WP_DATA_SUP,Indicates if the WP resources has corresponding data qualification. b0 - Not supported. b1 - Data qualifiers are supported." "0,1" newline bitfld.long 0x0 28. "DBG_OWN_SUP,Indicates if the HWA supports an module ownership. v2.0 and above. b0 - Not Supported. b1 - Ownership supported." "0,1" newline bitfld.long 0x0 27. "DBG_INDIRECT_SUP,Indicates if the HWA supports an indirect memory access port. v2.0 and above. b0 - Not Supported. b1 - Indirect port supported." "0,1" newline bitfld.long 0x0 26. "DBG_SWBP_SUP,Whether HWA Core supports SWBP or not. b0 - Not Supported. b1 - Supported." "0,1" newline bitfld.long 0x0 25. "DBQ_RESET_SUP,Whether HWA Core reset is supported or not which does not affect debug logic. b0 - Not Supported. b1 - Supported." "0,1" newline bitfld.long 0x0 24. "SYS_EXE_REQ,Whether HWA Core Execution status and control is supported. b0 - Not Supported. b1 - Supported." "0,1" newline bitfld.long 0x0 23. "TRIG_OUTPUT,b0 - Trigger Outputs are not supported. b1 - Trigger Outputs are supported." "0,1" newline bitfld.long 0x0 22. "TRIG_INPUT,b0 - Trigger Inputs are not supported. b1 - Trigger Inputs are supported." "0,1" newline bitfld.long 0x0 20.--21. "TRIG_CHNS,Number of Trigger Channels Supported. b00 ------ No channels supported. b01 ------ One channel supported. b10 ------ Two channels supported. Others ---- Reserved." "0,1,2,3" newline hexmask.long.byte 0x0 16.--19. 1. "NUM_CNTRS,The number of counter modules that exist. The registers supporting the counter modules must be implemented consecutively in the memory map." newline hexmask.long.byte 0x0 12.--15. 1. "NUM_WPS,The number of watchpoint modules that exist. The registers supporting the watchpoint modules must be implemented consecutively in the memory map" newline hexmask.long.byte 0x0 8.--11. 1. "NUM_BPS,The number of breakpoint modules that exist. The registers supporting the breakpoint modules must be implemented consecutively in the memory map." newline hexmask.long.byte 0x0 4.--7. 1. "REV_MAJ,Major Revision" newline hexmask.long.byte 0x0 0.--3. 1. "REV_MIN,Minor Revision" group.long 0x50++0x23 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_dbg_cntl,Debug Control register is used by debug software to control all of the basic debug functions." bitfld.long 0x0 26. "DBG_RESET_OCC,Sticky status bit to reflect reset has been generated" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "DBG_EMU0_CNTL,EMU0 output control. The cross trigger output control. The value in this field determines the behavior of the outputs generated on EMU0. NOTE: The effect of setting any non-zero value is ignored if the HWA Core is currently in HALTED.." newline rbitfld.long 0x0 12. "DBG_HALT_EMU0,Execution halted due to trigger in on EMU0 input Set to '1' when halt due to EMU0 input completes Set to '0' when execution resumes" "0,1" newline rbitfld.long 0x0 11. "DBG_HALT_USER,Execution halted due to register update of DBG_HALT Set to '1' when halt due to DBG_HALT update completes Set to '0' when execution resumes" "0,1" newline rbitfld.long 0x0 10. "DBG_HALT_STEP,Execution halted due to single step completion Set to '1' when the single step completes Set to '0' when execution resumes" "0,1" newline rbitfld.long 0x0 7. "DBG_EXE_STAT,The execution status of the module Set to '1' when halted due to debug event Set to '0' when execution resumes" "0,1" newline bitfld.long 0x0 5. "DBG_EMU0_EN,EMU0 input trigger enable Writing '1' enables halting on the falling edge of the EMU0 input Writing '0' disables halts via EMU0 input" "0,1" newline bitfld.long 0x0 2. "DBG_SINGLE_STEP_EN,Single Step Execution enable. When this bit is set the accelerator core shall be halted upon execution of a single instruction. This is after the accelerator core has left the halted state by clearing the DBG_HALT control bit." "0,1" newline bitfld.long 0x0 1. "DBG_RESTART,Debug Restart Status bit.This bit is normally set when the DBG_HALT bit transitions from '1' to '0' when the natural execution state is entered.It is a sticky bit. It may also be set when a synchronous run causes the accelerator to leave.." "0,1" newline bitfld.long 0x0 0. "DBG_HALT,Global debug run control. The bit will be read as being set upon entry to HALTED state due to halted state being entered because of SWBP HWBP HWWP EMU0 / 1 trigger or manual halt requested through this control. Writing '1' when read '0'.." "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_hts_event_gen0,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event0" hexmask.long.byte 0x4 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen0" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_hts_event_gen1,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event1" hexmask.long.byte 0x8 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_hts_event_gen2,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event2" hexmask.long.byte 0xC 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen2" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_hts_event_gen3,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event3" hexmask.long.byte 0x10 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen3" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_hts_event_gen4,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event4" hexmask.long.byte 0x14 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen4" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_hts_event_gen5,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event5" hexmask.long.byte 0x18 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen5" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_hts_event_gen6,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event6" hexmask.long.byte 0x1C 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen6" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_hts_event_gen7,select one of internal hts_event of width 34 out of 3'b0.pipeline_eop[6:0].1'b0.start_frame_evt.2'b0.hwa_eop[8:0].2'b0.hwa_init[8:0] bus as hts_event7" hexmask.long.byte 0x20 0.--5. 1. "EVT_SELECT,internal hts_event index for hts_event_gen7" group.long 0x100++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA0 Scheduler resources must not be read during halted state. '1'-> HWA0 Scheduler resources are readable during halted state" "0: HWA0 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA0 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA0 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further start. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value. when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count ; Note that tdone_count value is.." "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA0 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0: 64K,1: 128K" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA0 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0: Timer Inactive,1: Timer Active" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0: Disable watchdog timer,1: activate watchdog timer for 64K VPAC/DMPAC.." line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA0 sch '0' --> Disable" "?,1: Enable BW limiter function for HWA0 sch" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP.." hexmask.long.word 0x10 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA0 scheduler skip-enabled prod socket" newline hexmask.long.word 0x10 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA0 scheduler skip-enabled prod socket" group.long 0x120++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_cons0_control,Controlling consumer socket 0 for HWA0" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x128++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_cons1_control,Controlling consumer socket 1 for HWA0" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x130++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_cons2_control,Controlling consumer socket 2 for HWA0" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "?,1: Consumer socket 2 enable" group.long 0x138++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_cons3_control,Controlling consumer socket 3 for HWA0" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 3" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "?,1: Consumer socket 3 enable" group.long 0x140++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_cons4_control,Controlling consumer socket 4 for HWA0" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 4" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "?,1: Consumer socket 4 enable" group.long 0x148++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_cons5_control,Controlling consumer socket 5 for HWA0" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA0 cons socket 5" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 5 enable '0' Disable" "?,1: Consumer socket 5 enable" group.long 0x160++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod0_control,Controlling producer socket0 for HWA0" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "?,1: Producer socket 0 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod0_buf_control,Controlling producer socket0 buffer for HWA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod0_count,Defining count values for pre/post load for generating pend by HWA0 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_pa0_control,control register to manage pattern adapter on HWA0 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_pa0_prodcount,count values for HWA0 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x180++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod1_control,Controlling producer socket1 for HWA0" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "?,1: Producer socket 1 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod1_buf_control,Controlling producer socket1 buffer for HWA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod1_count,Defining count values for pre/post load for generating pend by HWA0 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_pa1_control,control register to manage pattern adapter on HWA0 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_pa1_prodcount,count values for HWA0 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x1A0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod2_control,Controlling producer socket2 for HWA0" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "?,1: Producer socket 2 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod2_buf_control,Controlling producer socket2 buffer for HWA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod2_count,Defining count values for pre/post load for generating pend by HWA0 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_pa2_control,control register to manage pattern adapter on HWA0 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_pa2_prodcount,count values for HWA0 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x1C0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod3_control,Controlling producer socket3 for HWA0" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "?,1: Producer socket 3 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod3_buf_control,Controlling producer socket3 buffer for HWA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod3_count,Defining count values for pre/post load for generating pend by HWA0 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_pa3_control,control register to manage pattern adapter on HWA0 prod socket3" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_pa3_prodcount,count values for HWA0 prod socket3" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x1E0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod4_control,Controlling producer socket4 for HWA0" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 4 skip enable '0' Disable" "?,1: Producer socket 4 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "?,1: block pend status at Producer socket 4" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "?,1: Producer socket 4 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod4_buf_control,Controlling producer socket4 buffer for HWA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod4_count,Defining count values for pre/post load for generating pend by HWA0 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x200++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod5_control,Controlling producer socket5 for HWA0" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 5. tdone_mask[mask_select] applies to prod_socket5. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 5 skip enable '0' Disable" "?,1: Producer socket 5 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 5 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 5 '0' Disable" "?,1: block pend status at Producer socket 5" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 5 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 5 enable '0' Disable" "?,1: Producer socket 5 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod5_buf_control,Controlling producer socket5 buffer for HWA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod5_count,Defining count values for pre/post load for generating pend by HWA0 prod5" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x220++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod6_control,Controlling producer socket6 for HWA0" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 6 skip enable '0' Disable" "?,1: Producer socket 6 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 6 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 6 '0' Disable" "?,1: block pend status at Producer socket 6" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 6 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA0 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 6 enable '0' Disable" "?,1: Producer socket 6 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod6_buf_control,Controlling producer socket6 buffer for HWA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA0_prod6_count,Defining count values for pre/post load for generating pend by HWA0 prod6" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x360++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA1 Scheduler resources must not be read during halted state. '1'-> HWA1 Scheduler resources are readable during halted state" "0: HWA1 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA1 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA1 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further start. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value. when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count ; Note that tdone_count value is.." "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA1 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0: 64K,1: 128K" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA1 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0: Timer Inactive,1: Timer Active" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0: Disable watchdog timer,1: activate watchdog timer for 64K VPAC/DMPAC.." line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA1 sch '0' --> Disable" "?,1: Enable BW limiter function for HWA1 sch" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP.." hexmask.long.word 0x10 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA1 scheduler skip-enabled prod socket" newline hexmask.long.word 0x10 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA1 scheduler skip-enabled prod socket" group.long 0x380++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_cons0_control,Controlling consumer socket 0 for HWA1" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x388++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_cons1_control,Controlling consumer socket 1 for HWA1" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x390++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_cons2_control,Controlling consumer socket 2 for HWA1" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "?,1: Consumer socket 2 enable" group.long 0x398++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_cons3_control,Controlling consumer socket 3 for HWA1" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 3" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "?,1: Consumer socket 3 enable" group.long 0x3A0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_cons4_control,Controlling consumer socket 4 for HWA1" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 4" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "?,1: Consumer socket 4 enable" group.long 0x3A8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_cons5_control,Controlling consumer socket 5 for HWA1" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA1 cons socket 5" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 5 enable '0' Disable" "?,1: Consumer socket 5 enable" group.long 0x3C0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod0_control,Controlling producer socket0 for HWA1" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "?,1: Producer socket 0 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod0_buf_control,Controlling producer socket0 buffer for HWA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod0_count,Defining count values for pre/post load for generating pend by HWA1 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_pa0_control,control register to manage pattern adapter on HWA1 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_pa0_prodcount,count values for HWA1 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x3E0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod1_control,Controlling producer socket1 for HWA1" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "?,1: Producer socket 1 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod1_buf_control,Controlling producer socket1 buffer for HWA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod1_count,Defining count values for pre/post load for generating pend by HWA1 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_pa1_control,control register to manage pattern adapter on HWA1 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_pa1_prodcount,count values for HWA1 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x400++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod2_control,Controlling producer socket2 for HWA1" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "?,1: Producer socket 2 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod2_buf_control,Controlling producer socket2 buffer for HWA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod2_count,Defining count values for pre/post load for generating pend by HWA1 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_pa2_control,control register to manage pattern adapter on HWA1 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_pa2_prodcount,count values for HWA1 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x420++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod3_control,Controlling producer socket3 for HWA1" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "?,1: Producer socket 3 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod3_buf_control,Controlling producer socket3 buffer for HWA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod3_count,Defining count values for pre/post load for generating pend by HWA1 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_pa3_control,control register to manage pattern adapter on HWA1 prod socket3" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_pa3_prodcount,count values for HWA1 prod socket3" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x440++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod4_control,Controlling producer socket4 for HWA1" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 4 skip enable '0' Disable" "?,1: Producer socket 4 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "?,1: block pend status at Producer socket 4" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "?,1: Producer socket 4 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod4_buf_control,Controlling producer socket4 buffer for HWA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod4_count,Defining count values for pre/post load for generating pend by HWA1 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x460++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod5_control,Controlling producer socket5 for HWA1" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 5. tdone_mask[mask_select] applies to prod_socket5. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 5 skip enable '0' Disable" "?,1: Producer socket 5 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 5 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 5 '0' Disable" "?,1: block pend status at Producer socket 5" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 5 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 5 enable '0' Disable" "?,1: Producer socket 5 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod5_buf_control,Controlling producer socket5 buffer for HWA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod5_count,Defining count values for pre/post load for generating pend by HWA1 prod5" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x480++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod6_control,Controlling producer socket6 for HWA1" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6. Valid value in range 0 - 6" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 6 skip enable '0' Disable" "?,1: Producer socket 6 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 6 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 6 '0' Disable" "?,1: block pend status at Producer socket 6" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 6 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA1 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 6 enable '0' Disable" "?,1: Producer socket 6 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod6_buf_control,Controlling producer socket6 buffer for HWA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA1_prod6_count,Defining count values for pre/post load for generating pend by HWA1 prod6" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x5C0++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_scheduler_control,Scheduler Control Register" bitfld.long 0x0 22. "EOR_EN,'1' -> LDC REGION/sub-frame feature enabled '0' LDC works in Frame mode only" "?,1: LDC REGION/sub-frame feature enabled" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA2 Scheduler resources must not be read during halted state. '1'-> HWA2 Scheduler resources are readable during halted state" "0: HWA2 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA2 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA2 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value . when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA2 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0: 64K,1: 128K" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA2 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0: Timer Inactive,1: Timer Active" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0: Disable watchdog timer,1: activate watchdog timer for 64K VPAC/DMPAC.." line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA2 sch '0' --> Disable" "?,1: Enable BW limiter function for HWA2 sch" group.long 0x5E0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_cons0_control,Controlling consumer socket 0 for HWA2" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA2 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x5E8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_cons1_control,Controlling consumer socket 1 for HWA2" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA2 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x5F0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_cons2_control,Controlling consumer socket 2 for HWA2" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA2 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "?,1: Consumer socket 2 enable" group.long 0x620++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod0_control,Controlling producer socket0 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 0 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (0+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior,1: Prod Socket 0 is used to trigger DMA channel to..,2: Prod Socket 0 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod0_buf_control,Controlling producer socket0 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod0_count,Defining count values for pre/post load for generating pend by HWA2 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_pa0_control,control register to manage pattern adapter on HWA2 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_pa0_prodcount,count values for HWA2 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x640++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod1_control,Controlling producer socket1 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 1 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (1+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior,1: Prod Socket 1 is used to trigger DMA channel to..,2: Prod Socket 1 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod1_buf_control,Controlling producer socket1 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod1_count,Defining count values for pre/post load for generating pend by HWA2 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_pa1_control,control register to manage pattern adapter on HWA2 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_pa1_prodcount,count values for HWA2 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x660++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod2_control,Controlling producer socket2 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 2 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (2+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior,1: Prod Socket 2 is used to trigger DMA channel to..,2: Prod Socket 2 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod2_buf_control,Controlling producer socket2 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod2_count,Defining count values for pre/post load for generating pend by HWA2 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_pa2_control,control register to manage pattern adapter on HWA2 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_pa2_prodcount,count values for HWA2 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x680++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod3_control,Controlling producer socket3 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 3 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (3+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior,1: Prod Socket 3 is used to trigger DMA channel to..,2: Prod Socket 3 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod3_buf_control,Controlling producer socket3 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod3_count,Defining count values for pre/post load for generating pend by HWA2 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_pa3_control,control register to manage pattern adapter on HWA2 prod socket3" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_pa3_prodcount,count values for HWA2 prod socket3" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x6A0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod4_control,Controlling producer socket4 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "?,1: block pend status at Producer socket 4" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "?,1: Producer socket 4 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod4_buf_control,Controlling producer socket4 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod4_count,Defining count values for pre/post load for generating pend by HWA2 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_pa4_control,control register to manage pattern adapter on HWA2 prod socket4" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_pa4_prodcount,count values for HWA2 prod socket4" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x6C0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod5_control,Controlling producer socket5 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 5. tdone_mask[mask_select] applies to prod_socket5. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 5 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 5 '0' Disable" "?,1: block pend status at Producer socket 5" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 5 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 5 enable '0' Disable" "?,1: Producer socket 5 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod5_buf_control,Controlling producer socket5 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod5_count,Defining count values for pre/post load for generating pend by HWA2 prod5" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_pa5_control,control register to manage pattern adapter on HWA2 prod socket5" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_pa5_prodcount,count values for HWA2 prod socket5" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x6E0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod6_control,Controlling producer socket6 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 6 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 6 '0' Disable" "?,1: block pend status at Producer socket 6" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 6 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 6 enable '0' Disable" "?,1: Producer socket 6 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod6_buf_control,Controlling producer socket6 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod6_count,Defining count values for pre/post load for generating pend by HWA2 prod6" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_pa6_control,control register to manage pattern adapter on HWA2 prod socket6" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_pa6_prodcount,count values for HWA2 prod socket6" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x700++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod7_control,Controlling producer socket7 for HWA2" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 7. tdone_mask[mask_select] applies to prod_socket7. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 7 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 7 '0' Disable" "?,1: block pend status at Producer socket 7" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 7 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA2 prod socket 7. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 7 enable '0' Disable" "?,1: Producer socket 7 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod7_buf_control,Controlling producer socket7 buffer for HWA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA2_prod7_count,Defining count values for pre/post load for generating pend by HWA2 prod7" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x820++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_scheduler_control,Scheduler Control Register" bitfld.long 0x0 22. "EOR_EN,'1' -> LDC REGION/sub-frame feature enabled '0' LDC works in Frame mode only" "?,1: LDC REGION/sub-frame feature enabled" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA3 Scheduler resources must not be read during halted state. '1'-> HWA3 Scheduler resources are readable during halted state" "0: HWA3 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA3 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA3 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value . when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA3 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0: 64K,1: 128K" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA3 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0: Timer Inactive,1: Timer Active" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0: Disable watchdog timer,1: activate watchdog timer for 64K VPAC/DMPAC.." line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA3 sch '0' --> Disable" "?,1: Enable BW limiter function for HWA3 sch" group.long 0x840++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_cons0_control,Controlling consumer socket 0 for HWA3" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA3 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x848++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_cons1_control,Controlling consumer socket 1 for HWA3" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA3 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x850++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_cons2_control,Controlling consumer socket 2 for HWA3" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA3 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "?,1: Consumer socket 2 enable" group.long 0x880++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod0_control,Controlling producer socket0 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 0 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (0+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior,1: Prod Socket 0 is used to trigger DMA channel to..,2: Prod Socket 0 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod0_buf_control,Controlling producer socket0 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod0_count,Defining count values for pre/post load for generating pend by HWA3 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_pa0_control,control register to manage pattern adapter on HWA3 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_pa0_prodcount,count values for HWA3 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x8A0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod1_control,Controlling producer socket1 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 1 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (1+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior,1: Prod Socket 1 is used to trigger DMA channel to..,2: Prod Socket 1 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod1_buf_control,Controlling producer socket1 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod1_count,Defining count values for pre/post load for generating pend by HWA3 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_pa1_control,control register to manage pattern adapter on HWA3 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_pa1_prodcount,count values for HWA3 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x8C0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod2_control,Controlling producer socket2 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 2 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (2+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior,1: Prod Socket 2 is used to trigger DMA channel to..,2: Prod Socket 2 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod2_buf_control,Controlling producer socket2 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod2_count,Defining count values for pre/post load for generating pend by HWA3 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_pa2_control,control register to manage pattern adapter on HWA3 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_pa2_prodcount,count values for HWA3 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x8E0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod3_control,Controlling producer socket3 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 4" newline bitfld.long 0x0 22.--23. "PARTIAL_BPR_TRIGMODE,0: Normal behavior; 1 : Prod Socket 3 is used to trigger DMA channel to transfer end of Row or End of Region Row buffer data for prod socket (3+2)%4. Useful when this Buffer is not completely filled at end of row and it enables.." "0: Normal behavior,1: Prod Socket 3 is used to trigger DMA channel to..,2: Prod Socket 3 is used to trigger DMA channel to..,?" newline hexmask.long.byte 0x0 18.--21. 1. "PARTIAL_BPR_COUNT,Remaining block count to complete configured BPR at End of Row or End of Region Row when LDC is configured in tdone_gen_mode='0'" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod3_buf_control,Controlling producer socket3 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod3_count,Defining count values for pre/post load for generating pend by HWA3 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_pa3_control,control register to manage pattern adapter on HWA3 prod socket3" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_pa3_prodcount,count values for HWA3 prod socket3" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x900++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod4_control,Controlling producer socket4 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "?,1: block pend status at Producer socket 4" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "?,1: Producer socket 4 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod4_buf_control,Controlling producer socket4 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod4_count,Defining count values for pre/post load for generating pend by HWA3 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_pa4_control,control register to manage pattern adapter on HWA3 prod socket4" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_pa4_prodcount,count values for HWA3 prod socket4" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x920++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod5_control,Controlling producer socket5 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 5. tdone_mask[mask_select] applies to prod_socket5. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 5 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 5 '0' Disable" "?,1: block pend status at Producer socket 5" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 5 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 5 enable '0' Disable" "?,1: Producer socket 5 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod5_buf_control,Controlling producer socket5 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod5_count,Defining count values for pre/post load for generating pend by HWA3 prod5" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_pa5_control,control register to manage pattern adapter on HWA3 prod socket5" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_pa5_prodcount,count values for HWA3 prod socket5" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x940++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod6_control,Controlling producer socket6 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 6 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 6 '0' Disable" "?,1: block pend status at Producer socket 6" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 6 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 6 enable '0' Disable" "?,1: Producer socket 6 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod6_buf_control,Controlling producer socket6 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod6_count,Defining count values for pre/post load for generating pend by HWA3 prod6" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_pa6_control,control register to manage pattern adapter on HWA3 prod socket6" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_pa6_prodcount,count values for HWA3 prod socket6" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x960++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod7_control,Controlling producer socket7 for HWA3" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 7. tdone_mask[mask_select] applies to prod_socket7. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 7 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 7 '0' Disable" "?,1: block pend status at Producer socket 7" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 7 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA3 prod socket 7. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 7 enable '0' Disable" "?,1: Producer socket 7 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod7_buf_control,Controlling producer socket7 buffer for HWA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA3_prod7_count,Defining count values for pre/post load for generating pend by HWA3 prod7" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xA80++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA4 Scheduler resources must not be read during halted state. '1'-> HWA4 Scheduler resources are readable during halted state" "0: HWA4 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA4 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA4 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value. when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA4 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0: 64K,1: 128K" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA4 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0: Timer Inactive,1: Timer Active" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0: Disable watchdog timer,1: activate watchdog timer for 64K VPAC/DMPAC.." line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA4 sch '0' --> Disable" "?,1: Enable BW limiter function for HWA4 sch" group.long 0xAA0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_cons0_control,Controlling consumer socket 0 for HWA4" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA4 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0xAA8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_cons1_control,Controlling consumer socket 1 for HWA4" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA4 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0xAB0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_cons2_control,Controlling consumer socket 2 for HWA4" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA4 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "?,1: Consumer socket 2 enable" group.long 0xAE0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod0_control,Controlling producer socket0 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod0_buf_control,Controlling producer socket0 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod0_count,Defining count values for pre/post load for generating pend by HWA4 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_pa0_control,control register to manage pattern adapter on HWA4 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_pa0_prodcount,count values for HWA4 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0xB00++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod1_control,Controlling producer socket1 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod1_buf_control,Controlling producer socket1 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod1_count,Defining count values for pre/post load for generating pend by HWA4 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_pa1_control,control register to manage pattern adapter on HWA4 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_pa1_prodcount,count values for HWA4 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0xB20++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod2_control,Controlling producer socket2 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod2_buf_control,Controlling producer socket2 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod2_count,Defining count values for pre/post load for generating pend by HWA4 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xB40++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod3_control,Controlling producer socket3 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod3_buf_control,Controlling producer socket3 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod3_count,Defining count values for pre/post load for generating pend by HWA4 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xB60++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod4_control,Controlling producer socket4 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "?,1: block pend status at Producer socket 4" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "?,1: Producer socket 4 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod4_buf_control,Controlling producer socket4 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod4_count,Defining count values for pre/post load for generating pend by HWA4 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xB80++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod5_control,Controlling producer socket5 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 5. tdone_mask[mask_select] applies to prod_socket5. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 5 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 5 '0' Disable" "?,1: block pend status at Producer socket 5" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 5 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 5 enable '0' Disable" "?,1: Producer socket 5 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod5_buf_control,Controlling producer socket5 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod5_count,Defining count values for pre/post load for generating pend by HWA4 prod5" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xBA0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod6_control,Controlling producer socket6 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 6 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 6 '0' Disable" "?,1: block pend status at Producer socket 6" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 6 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 6 enable '0' Disable" "?,1: Producer socket 6 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod6_buf_control,Controlling producer socket6 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod6_count,Defining count values for pre/post load for generating pend by HWA4 prod6" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xBC0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod7_control,Controlling producer socket7 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 7. tdone_mask[mask_select] applies to prod_socket7. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 7 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 7 '0' Disable" "?,1: block pend status at Producer socket 7" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 7 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 7. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 7 enable '0' Disable" "?,1: Producer socket 7 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod7_buf_control,Controlling producer socket7 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod7_count,Defining count values for pre/post load for generating pend by HWA4 prod7" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xBE0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod8_control,Controlling producer socket8 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 8. tdone_mask[mask_select] applies to prod_socket8. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 8 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 8 '0' Disable" "?,1: block pend status at Producer socket 8" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 8 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 8. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 8 enable '0' Disable" "?,1: Producer socket 8 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod8_buf_control,Controlling producer socket8 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod8_count,Defining count values for pre/post load for generating pend by HWA4 prod8" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xC00++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod9_control,Controlling producer socket9 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 9. tdone_mask[mask_select] applies to prod_socket9. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 9 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 9 '0' Disable" "?,1: block pend status at Producer socket 9" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 9 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 9. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 9 enable '0' Disable" "?,1: Producer socket 9 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod9_buf_control,Controlling producer socket9 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod9_count,Defining count values for pre/post load for generating pend by HWA4 prod9" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xC20++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod10_control,Controlling producer socket10 for HWA4" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 10. tdone_mask[mask_select] applies to prod_socket10. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 10 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 10 '0' Disable" "?,1: block pend status at Producer socket 10" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 10 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA4 prod socket 10. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 10 enable '0' Disable" "?,1: Producer socket 10 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod10_buf_control,Controlling producer socket10 buffer for HWA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA4_prod10_count,Defining count values for pre/post load for generating pend by HWA4 prod10" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xCE0++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA5 Scheduler resources must not be read during halted state. '1'-> HWA5 Scheduler resources are readable during halted state" "0: HWA5 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA5 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA5 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value. when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA5 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0: 64K,1: 128K" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA5 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0: Timer Inactive,1: Timer Active" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0: Disable watchdog timer,1: activate watchdog timer for 64K VPAC/DMPAC.." line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA5 sch '0' --> Disable" "?,1: Enable BW limiter function for HWA5 sch" group.long 0xD00++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_cons0_control,Controlling consumer socket 0 for HWA5" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA5 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0xD08++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_cons1_control,Controlling consumer socket 1 for HWA5" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA5 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0xD10++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_cons2_control,Controlling consumer socket 2 for HWA5" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA5 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "?,1: Consumer socket 2 enable" group.long 0xD40++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod0_control,Controlling producer socket0 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod0_buf_control,Controlling producer socket0 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod0_count,Defining count values for pre/post load for generating pend by HWA5 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_pa0_control,control register to manage pattern adapter on HWA5 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_pa0_prodcount,count values for HWA5 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0xD60++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod1_control,Controlling producer socket1 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod1_buf_control,Controlling producer socket1 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod1_count,Defining count values for pre/post load for generating pend by HWA5 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_pa1_control,control register to manage pattern adapter on HWA5 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_pa1_prodcount,count values for HWA5 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0xD80++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod2_control,Controlling producer socket2 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod2_buf_control,Controlling producer socket2 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod2_count,Defining count values for pre/post load for generating pend by HWA5 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xDA0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod3_control,Controlling producer socket3 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod3_buf_control,Controlling producer socket3 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod3_count,Defining count values for pre/post load for generating pend by HWA5 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xDC0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod4_control,Controlling producer socket4 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "?,1: block pend status at Producer socket 4" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "?,1: Producer socket 4 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod4_buf_control,Controlling producer socket4 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod4_count,Defining count values for pre/post load for generating pend by HWA5 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xDE0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod5_control,Controlling producer socket5 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 5. tdone_mask[mask_select] applies to prod_socket5. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 5 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 5 '0' Disable" "?,1: block pend status at Producer socket 5" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 5 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 5. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 5 enable '0' Disable" "?,1: Producer socket 5 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod5_buf_control,Controlling producer socket5 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod5_count,Defining count values for pre/post load for generating pend by HWA5 prod5" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xE00++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod6_control,Controlling producer socket6 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 6. tdone_mask[mask_select] applies to prod_socket6. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 6 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 6 '0' Disable" "?,1: block pend status at Producer socket 6" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 6 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 6. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 6 enable '0' Disable" "?,1: Producer socket 6 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod6_buf_control,Controlling producer socket6 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod6_count,Defining count values for pre/post load for generating pend by HWA5 prod6" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xE20++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod7_control,Controlling producer socket7 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 7. tdone_mask[mask_select] applies to prod_socket7. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 7 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 7 '0' Disable" "?,1: block pend status at Producer socket 7" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 7 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 7. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 7 enable '0' Disable" "?,1: Producer socket 7 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod7_buf_control,Controlling producer socket7 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod7_count,Defining count values for pre/post load for generating pend by HWA5 prod7" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xE40++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod8_control,Controlling producer socket8 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 8. tdone_mask[mask_select] applies to prod_socket8. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 8 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 8 '0' Disable" "?,1: block pend status at Producer socket 8" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 8 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 8. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 8 enable '0' Disable" "?,1: Producer socket 8 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod8_buf_control,Controlling producer socket8 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod8_count,Defining count values for pre/post load for generating pend by HWA5 prod8" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xE60++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod9_control,Controlling producer socket9 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 9. tdone_mask[mask_select] applies to prod_socket9. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 9 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 9 '0' Disable" "?,1: block pend status at Producer socket 9" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 9 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 9. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 9 enable '0' Disable" "?,1: Producer socket 9 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod9_buf_control,Controlling producer socket9 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod9_count,Defining count values for pre/post load for generating pend by HWA5 prod9" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xE80++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod10_control,Controlling producer socket10 for HWA5" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 10. tdone_mask[mask_select] applies to prod_socket10. Valid value in range 0 - 10" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 10 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 10 '0' Disable" "?,1: block pend status at Producer socket 10" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 10 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA5 prod socket 10. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 10 enable '0' Disable" "?,1: Producer socket 10 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod10_buf_control,Controlling producer socket10 buffer for HWA5" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA5_prod10_count,Defining count values for pre/post load for generating pend by HWA5 prod10" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0xF40++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA6_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA6 Scheduler resources must not be read during halted state. '1'-> HWA6 Scheduler resources are readable during halted state" "0: HWA6 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA6 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA6 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA6_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value . when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA6_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA6 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0: 64K,1: 128K" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA6 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0: Timer Inactive,1: Timer Active" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0: Disable watchdog timer,1: activate watchdog timer for 64K VPAC/DMPAC.." line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA6_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA6 sch '0' --> Disable" "?,1: Enable BW limiter function for HWA6 sch" group.long 0xF60++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA6_cons0_control,Controlling consumer socket 0 for HWA6" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA6 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0xF68++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA6_cons1_control,Controlling consumer socket 1 for HWA6" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA6 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0xFA0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA6_prod0_control,Controlling producer socket0 for HWA6" bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA6 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA6_prod0_buf_control,Controlling producer socket0 buffer for HWA6" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA6_prod0_count,Defining count values for pre/post load for generating pend by HWA6 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA6_pa0_control,control register to manage pattern adapter on HWA6 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA6_pa0_prodcount,count values for HWA6 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0xFC0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA6_prod1_control,Controlling producer socket1 for HWA6" bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA6 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA6_prod1_buf_control,Controlling producer socket1 buffer for HWA6" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA6_prod1_count,Defining count values for pre/post load for generating pend by HWA6 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x11A0++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA7 Scheduler resources must not be read during halted state. '1'-> HWA7 Scheduler resources are readable during halted state" "0: HWA7 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA7 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA7 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further start. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value . when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA7 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0: 64K,1: 128K" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA7 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0: Timer Inactive,1: Timer Active" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0: Disable watchdog timer,1: activate watchdog timer for 64K VPAC/DMPAC.." line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA7 sch '0' --> Disable" "?,1: Enable BW limiter function for HWA7 sch" group.long 0x11C0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_cons0_control,Controlling consumer socket 0 for HWA7" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x11C8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_cons1_control,Controlling consumer socket 1 for HWA7" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x11D0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_cons2_control,Controlling consumer socket 2 for HWA7" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "?,1: Consumer socket 2 enable" group.long 0x11D8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_cons3_control,Controlling consumer socket 3 for HWA7" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 3" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "?,1: Consumer socket 3 enable" group.long 0x11E0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_cons4_control,Controlling consumer socket 4 for HWA7" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA7 cons socket 4" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "?,1: Consumer socket 4 enable" group.long 0x1200++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_prod0_control,Controlling producer socket0 for HWA7" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_prod0_buf_control,Controlling producer socket0 buffer for HWA7" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_prod0_count,Defining count values for pre/post load for generating pend by HWA7 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_pa0_control,control register to manage pattern adapter on HWA7 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_pa0_prodcount,count values for HWA7 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x1220++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_prod1_control,Controlling producer socket1 for HWA7" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_prod1_buf_control,Controlling producer socket1 buffer for HWA7" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_prod1_count,Defining count values for pre/post load for generating pend by HWA7 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_pa1_control,control register to manage pattern adapter on HWA7 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_pa1_prodcount,count values for HWA7 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x1240++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_prod2_control,Controlling producer socket2 for HWA7" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_prod2_buf_control,Controlling producer socket2 buffer for HWA7" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_prod2_count,Defining count values for pre/post load for generating pend by HWA7 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_pa2_control,control register to manage pattern adapter on HWA7 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_pa2_prodcount,count values for HWA7 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x1260++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_prod3_control,Controlling producer socket3 for HWA7" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_prod3_buf_control,Controlling producer socket3 buffer for HWA7" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_prod3_count,Defining count values for pre/post load for generating pend by HWA7 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_pa3_control,control register to manage pattern adapter on HWA7 prod socket3" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_pa3_prodcount,count values for HWA7 prod socket3" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x1280++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_prod4_control,Controlling producer socket4 for HWA7" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "?,1: block pend status at Producer socket 4" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA7 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "?,1: Producer socket 4 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_prod4_buf_control,Controlling producer socket4 buffer for HWA7" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA7_prod4_count,Defining count values for pre/post load for generating pend by HWA7 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x1400++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_scheduler_control,Scheduler Control Register" bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA8 Scheduler resources must not be read during halted state. '1'-> HWA8 Scheduler resources are readable during halted state" "0: HWA8 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA8 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA8 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further start. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value . when enabled it triggers tdone_intr when (tdone_count==hop_thread_count) '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_WDTimer,Watchdog timer control register" hexmask.long.tbyte 0x8 8.--24. 1. "WDTIMER_COUNT,Current value of HWA8 Scheduler watchdog timer count" newline bitfld.long 0x8 2. "WDTIMER_MODE,Watchdog timeout count '1' -> 128K '0' -> 64K" "0: 64K,1: 128K" newline rbitfld.long 0x8 1. "WDTIMER_STATUS,HWA8 Scheduler watchdog timer status '1' -> Timer Active '0' -> Timer Inactive (count is stable)" "0: Timer Inactive,1: Timer Active" newline bitfld.long 0x8 0. "WDTIMER_EN,'1' -> activate watchdog timer for 64K VPAC/DMPAC cycles between task start and task done '0' -> Disable watchdog timer" "0: Disable watchdog timer,1: activate watchdog timer for 64K VPAC/DMPAC.." line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_BW_limiter,Scheduler BW Control Register. Processing unit level BW control. Use DMA to eliminate peak system BW within processing units line/Block" hexmask.long.word 0xC 8.--22. 1. "BW_CYCLE_COUNT,Average Cycle count between successive Task Start" newline hexmask.long.byte 0xC 1.--4. 1. "BW_TOKEN_COUNT,Max Token count to create average BW" newline bitfld.long 0xC 0. "BW_LIMITER_EN,'1' -> Enable BW limiter function for HWA8 sch '0' --> Disable" "?,1: Enable BW limiter function for HWA8 sch" group.long 0x1420++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_cons0_control,Controlling consumer socket 0 for HWA8" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x1428++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_cons1_control,Controlling consumer socket 1 for HWA8" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x1430++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_cons2_control,Controlling consumer socket 2 for HWA8" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 2" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 2 enable '0' Disable" "?,1: Consumer socket 2 enable" group.long 0x1438++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_cons3_control,Controlling consumer socket 3 for HWA8" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 3" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 3 enable '0' Disable" "?,1: Consumer socket 3 enable" group.long 0x1440++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_cons4_control,Controlling consumer socket 4 for HWA8" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA8 cons socket 4" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 4 enable '0' Disable" "?,1: Consumer socket 4 enable" group.long 0x1460++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_prod0_control,Controlling producer socket0 for HWA8" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 0. tdone_mask[mask_select] applies to prod_socket0. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_prod0_buf_control,Controlling producer socket0 buffer for HWA8" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_prod0_count,Defining count values for pre/post load for generating pend by HWA8 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_pa0_control,control register to manage pattern adapter on HWA8 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_pa0_prodcount,count values for HWA8 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x1480++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_prod1_control,Controlling producer socket1 for HWA8" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 1. tdone_mask[mask_select] applies to prod_socket1. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_prod1_buf_control,Controlling producer socket1 buffer for HWA8" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_prod1_count,Defining count values for pre/post load for generating pend by HWA8 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_pa1_control,control register to manage pattern adapter on HWA8 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_pa1_prodcount,count values for HWA8 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x14A0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_prod2_control,Controlling producer socket2 for HWA8" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 2. tdone_mask[mask_select] applies to prod_socket2. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_prod2_buf_control,Controlling producer socket2 buffer for HWA8" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_prod2_count,Defining count values for pre/post load for generating pend by HWA8 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_pa2_control,control register to manage pattern adapter on HWA8 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_pa2_prodcount,count values for HWA8 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x14C0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_prod3_control,Controlling producer socket3 for HWA8" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 3. tdone_mask[mask_select] applies to prod_socket3. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_prod3_buf_control,Controlling producer socket3 buffer for HWA8" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_prod3_count,Defining count values for pre/post load for generating pend by HWA8 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_pa3_control,control register to manage pattern adapter on HWA8 prod socket3" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_pa3_prodcount,count values for HWA8 prod socket3" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x14E0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_prod4_control,Controlling producer socket4 for HWA8" hexmask.long.byte 0x0 24.--27. 1. "MASK_SELECT,define which tdone_mask apply to prod socket 4. tdone_mask[mask_select] applies to prod_socket4. Valid value in range 0 - 4" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 4 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 4 '0' Disable" "?,1: block pend status at Producer socket 4" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 4 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA8 prod socket 4. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 4 enable '0' Disable" "?,1: Producer socket 4 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_prod4_buf_control,Controlling producer socket4 buffer for HWA8" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA8_prod4_count,Defining count values for pre/post load for generating pend by HWA8 prod4" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x1D80++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_scheduler_control,Scheduler Control Register" bitfld.long 0x0 25. "CHANNEL_LINK_EN,'1' -> Trigger dma_channel_no for chanel_count_set0.count0 times --> Trigger dma_channel_no+1 for chanel_count_set0.count1 times --> Trigger dma_channel_no+2 for chanel_count_set1.count0 times .. repeat till either total count reaches HOP.." "?,1: Trigger dma_channel_no for chanel_count_set0" newline bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "?,1: task skip enable" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "?,1: loop back start onto done in same cycle w/o.." newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA12" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA12 Scheduler resources must not be read during halted state. '1'-> HWA12 Scheduler resources are readable during halted state" "0: HWA12 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA12 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA12 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x1D90++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP.." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA12 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA12 scheduler skip-enabled prod socket" group.long 0x1DA0++0x17 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_channel_count_set0,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x0 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+1 HWA12_channel_count_set0.count1 times before linking to next HWA12_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x0 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+0 HWA12_channel_count_set0.count0 times before linking to count1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_channel_count_set1,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x4 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+3 HWA12_channel_count_set1.count1 times before linking to next HWA12_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x4 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+2 HWA12_channel_count_set1.count0 times before linking to count1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_channel_count_set2,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x8 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+5 HWA12_channel_count_set2.count1 times before linking to next HWA12_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x8 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+4 HWA12_channel_count_set2.count0 times before linking to count1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_channel_count_set3,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0xC 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+7 HWA12_channel_count_set3.count1 times before linking to next HWA12_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0xC 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+6 HWA12_channel_count_set3.count0 times before linking to count1" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_channel_count_set4,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x10 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+9 HWA12_channel_count_set4.count1 times before linking to next HWA12_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x10 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+8 HWA12_channel_count_set4.count0 times before linking to count1" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_channel_count_set5,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x14 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+11 HWA12_channel_count_set5.count1 times before linking to next HWA12_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x14 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+10 HWA12_channel_count_set5.count0 times before linking to count1" group.long 0x1DE0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_cons0_control,Controlling consumer socket 0 for HWA12" bitfld.long 0x0 31. "EHWA_PROD,'1' -> spare consumer is connected to external host producer '0' --> no external host producer" "?,1: spare consumer is connected to external host.." newline bitfld.long 0x0 30. "SET_PEND,writing '1' sets pend on consumer socket" "0,1" newline hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA12 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x1DE8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_cons1_control,Controlling consumer socket 1 for HWA12" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA12 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x1E20++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_prod0_control,Controlling producer socket0 for HWA12" bitfld.long 0x0 31. "EHWA_CONS,'1' -> spare consumer is connected to external host consumer '0' --> no external host consumer" "?,1: spare consumer is connected to external host.." newline bitfld.long 0x0 30. "PROD_DEC,writing '1' decrement prod count value" "0,1" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "?,1: Producer socket 0 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_prod0_buf_control,Controlling producer socket0 buffer for HWA12" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_prod0_count,Defining count values for pre/post load for generating pend by HWA12 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_pa0_control,control register to manage pattern adapter on HWA12 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_pa0_prodcount,count values for HWA12 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x1E40++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_prod1_control,Controlling producer socket1 for HWA12" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "?,1: Producer socket 1 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_prod1_buf_control,Controlling producer socket1 buffer for HWA12" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_prod1_count,Defining count values for pre/post load for generating pend by HWA12 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_pa1_control,control register to manage pattern adapter on HWA12 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_pa1_prodcount,count values for HWA12 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x1E60++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_prod2_control,Controlling producer socket2 for HWA12" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "?,1: Producer socket 2 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_prod2_buf_control,Controlling producer socket2 buffer for HWA12" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_prod2_count,Defining count values for pre/post load for generating pend by HWA12 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_pa2_control,control register to manage pattern adapter on HWA12 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_pa2_prodcount,count values for HWA12 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x1E80++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_prod3_control,Controlling producer socket3 for HWA12" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "?,1: Producer socket 3 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA12 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_prod3_buf_control,Controlling producer socket3 buffer for HWA12" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA12_prod3_count,Defining count values for pre/post load for generating pend by HWA12 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x2020++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_scheduler_control,Scheduler Control Register" bitfld.long 0x0 25. "CHANNEL_LINK_EN,'1' -> Trigger dma_channel_no for chanel_count_set0.count0 times --> Trigger dma_channel_no+1 for chanel_count_set0.count1 times --> Trigger dma_channel_no+2 for chanel_count_set1.count0 times .. repeat till either total count reaches HOP.." "?,1: Trigger dma_channel_no for chanel_count_set0" newline bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "?,1: task skip enable" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "?,1: loop back start onto done in same cycle w/o.." newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA13" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA13 Scheduler resources must not be read during halted state. '1'-> HWA13 Scheduler resources are readable during halted state" "0: HWA13 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA13 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA13 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x2030++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP.." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA13 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA13 scheduler skip-enabled prod socket" group.long 0x2040++0x17 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_channel_count_set0,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x0 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+1 HWA13_channel_count_set0.count1 times before linking to next HWA13_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x0 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+0 HWA13_channel_count_set0.count0 times before linking to count1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_channel_count_set1,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x4 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+3 HWA13_channel_count_set1.count1 times before linking to next HWA13_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x4 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+2 HWA13_channel_count_set1.count0 times before linking to count1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_channel_count_set2,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x8 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+5 HWA13_channel_count_set2.count1 times before linking to next HWA13_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x8 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+4 HWA13_channel_count_set2.count0 times before linking to count1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_channel_count_set3,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0xC 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+7 HWA13_channel_count_set3.count1 times before linking to next HWA13_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0xC 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+6 HWA13_channel_count_set3.count0 times before linking to count1" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_channel_count_set4,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x10 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+9 HWA13_channel_count_set4.count1 times before linking to next HWA13_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x10 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+8 HWA13_channel_count_set4.count0 times before linking to count1" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_channel_count_set5,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x14 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+11 HWA13_channel_count_set5.count1 times before linking to next HWA13_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x14 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+10 HWA13_channel_count_set5.count0 times before linking to count1" group.long 0x2080++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_cons0_control,Controlling consumer socket 0 for HWA13" bitfld.long 0x0 31. "EHWA_PROD,'1' -> spare consumer is connected to external host producer '0' --> no external host producer" "?,1: spare consumer is connected to external host.." newline bitfld.long 0x0 30. "SET_PEND,writing '1' sets pend on consumer socket" "0,1" newline hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA13 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x2088++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_cons1_control,Controlling consumer socket 1 for HWA13" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA13 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x20C0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_prod0_control,Controlling producer socket0 for HWA13" bitfld.long 0x0 31. "EHWA_CONS,'1' -> spare consumer is connected to external host consumer '0' --> no external host consumer" "?,1: spare consumer is connected to external host.." newline bitfld.long 0x0 30. "PROD_DEC,writing '1' decrement prod count value" "0,1" newline bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "?,1: Producer socket 0 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_prod0_buf_control,Controlling producer socket0 buffer for HWA13" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_prod0_count,Defining count values for pre/post load for generating pend by HWA13 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_pa0_control,control register to manage pattern adapter on HWA13 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_pa0_prodcount,count values for HWA13 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x20E0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_prod1_control,Controlling producer socket1 for HWA13" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "?,1: Producer socket 1 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_prod1_buf_control,Controlling producer socket1 buffer for HWA13" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_prod1_count,Defining count values for pre/post load for generating pend by HWA13 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_pa1_control,control register to manage pattern adapter on HWA13 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_pa1_prodcount,count values for HWA13 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x2100++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_prod2_control,Controlling producer socket2 for HWA13" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "?,1: Producer socket 2 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_prod2_buf_control,Controlling producer socket2 buffer for HWA13" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_prod2_count,Defining count values for pre/post load for generating pend by HWA13 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_pa2_control,control register to manage pattern adapter on HWA13 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_pa2_prodcount,count values for HWA13 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x2120++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_prod3_control,Controlling producer socket3 for HWA13" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "?,1: Producer socket 3 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA13 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_prod3_buf_control,Controlling producer socket3 buffer for HWA13" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA13_prod3_count,Defining count values for pre/post load for generating pend by HWA13 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x22C0++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_scheduler_control,Scheduler Control Register" bitfld.long 0x0 25. "CHANNEL_LINK_EN,'1' -> Trigger dma_channel_no for chanel_count_set0.count0 times --> Trigger dma_channel_no+1 for chanel_count_set0.count1 times --> Trigger dma_channel_no+2 for chanel_count_set1.count0 times .. repeat till either total count reaches HOP.." "?,1: Trigger dma_channel_no for chanel_count_set0" newline bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "?,1: task skip enable" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "?,1: loop back start onto done in same cycle w/o.." newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA14" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA14 Scheduler resources must not be read during halted state. '1'-> HWA14 Scheduler resources are readable during halted state" "0: HWA14 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA14 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA14 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x22D0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP.." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA14 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA14 scheduler skip-enabled prod socket" group.long 0x22E0++0x17 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_channel_count_set0,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x0 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+1 HWA14_channel_count_set0.count1 times before linking to next HWA14_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x0 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+0 HWA14_channel_count_set0.count0 times before linking to count1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_channel_count_set1,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x4 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+3 HWA14_channel_count_set1.count1 times before linking to next HWA14_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x4 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+2 HWA14_channel_count_set1.count0 times before linking to count1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_channel_count_set2,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x8 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+5 HWA14_channel_count_set2.count1 times before linking to next HWA14_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x8 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+4 HWA14_channel_count_set2.count0 times before linking to count1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_channel_count_set3,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0xC 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+7 HWA14_channel_count_set3.count1 times before linking to next HWA14_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0xC 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+6 HWA14_channel_count_set3.count0 times before linking to count1" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_channel_count_set4,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x10 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+9 HWA14_channel_count_set4.count1 times before linking to next HWA14_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x10 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+8 HWA14_channel_count_set4.count0 times before linking to count1" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_channel_count_set5,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x14 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+11 HWA14_channel_count_set5.count1 times before linking to next HWA14_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x14 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+10 HWA14_channel_count_set5.count0 times before linking to count1" group.long 0x2320++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_cons0_control,Controlling consumer socket 0 for HWA14" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA14 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x2328++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_cons1_control,Controlling consumer socket 1 for HWA14" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA14 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x2360++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_prod0_control,Controlling producer socket0 for HWA14" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "?,1: Producer socket 0 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_prod0_buf_control,Controlling producer socket0 buffer for HWA14" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_prod0_count,Defining count values for pre/post load for generating pend by HWA14 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_pa0_control,control register to manage pattern adapter on HWA14 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_pa0_prodcount,count values for HWA14 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x2380++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_prod1_control,Controlling producer socket1 for HWA14" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "?,1: Producer socket 1 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_prod1_buf_control,Controlling producer socket1 buffer for HWA14" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_prod1_count,Defining count values for pre/post load for generating pend by HWA14 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_pa1_control,control register to manage pattern adapter on HWA14 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_pa1_prodcount,count values for HWA14 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x23A0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_prod2_control,Controlling producer socket2 for HWA14" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "?,1: Producer socket 2 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_prod2_buf_control,Controlling producer socket2 buffer for HWA14" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_prod2_count,Defining count values for pre/post load for generating pend by HWA14 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_pa2_control,control register to manage pattern adapter on HWA14 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_pa2_prodcount,count values for HWA14 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x23C0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_prod3_control,Controlling producer socket3 for HWA14" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "?,1: Producer socket 3 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA14 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_prod3_buf_control,Controlling producer socket3 buffer for HWA14" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA14_prod3_count,Defining count values for pre/post load for generating pend by HWA14 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x2560++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_scheduler_control,Scheduler Control Register" bitfld.long 0x0 25. "CHANNEL_LINK_EN,'1' -> Trigger dma_channel_no for chanel_count_set0.count0 times --> Trigger dma_channel_no+1 for chanel_count_set0.count1 times --> Trigger dma_channel_no+2 for chanel_count_set1.count0 times .. repeat till either total count reaches HOP.." "?,1: Trigger dma_channel_no for chanel_count_set0" newline bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "?,1: task skip enable" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "?,1: loop back start onto done in same cycle w/o.." newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA15" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA15 Scheduler resources must not be read during halted state. '1'-> HWA15 Scheduler resources are readable during halted state" "0: HWA15 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA15 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA15 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x2570++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP.." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA15 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA15 scheduler skip-enabled prod socket" group.long 0x2580++0x17 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_channel_count_set0,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x0 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+1 HWA15_channel_count_set0.count1 times before linking to next HWA15_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x0 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+0 HWA15_channel_count_set0.count0 times before linking to count1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_channel_count_set1,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x4 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+3 HWA15_channel_count_set1.count1 times before linking to next HWA15_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x4 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+2 HWA15_channel_count_set1.count0 times before linking to count1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_channel_count_set2,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x8 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+5 HWA15_channel_count_set2.count1 times before linking to next HWA15_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x8 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+4 HWA15_channel_count_set2.count0 times before linking to count1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_channel_count_set3,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0xC 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+7 HWA15_channel_count_set3.count1 times before linking to next HWA15_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0xC 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+6 HWA15_channel_count_set3.count0 times before linking to count1" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_channel_count_set4,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x10 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+9 HWA15_channel_count_set4.count1 times before linking to next HWA15_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x10 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+8 HWA15_channel_count_set4.count0 times before linking to count1" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_channel_count_set5,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x14 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+11 HWA15_channel_count_set5.count1 times before linking to next HWA15_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x14 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+10 HWA15_channel_count_set5.count0 times before linking to count1" group.long 0x25C0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_cons0_control,Controlling consumer socket 0 for HWA15" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA15 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x25C8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_cons1_control,Controlling consumer socket 1 for HWA15" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA15 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x2600++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_prod0_control,Controlling producer socket0 for HWA15" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "?,1: Producer socket 0 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_prod0_buf_control,Controlling producer socket0 buffer for HWA15" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_prod0_count,Defining count values for pre/post load for generating pend by HWA15 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_pa0_control,control register to manage pattern adapter on HWA15 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_pa0_prodcount,count values for HWA15 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x2620++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_prod1_control,Controlling producer socket1 for HWA15" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "?,1: Producer socket 1 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_prod1_buf_control,Controlling producer socket1 buffer for HWA15" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_prod1_count,Defining count values for pre/post load for generating pend by HWA15 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_pa1_control,control register to manage pattern adapter on HWA15 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_pa1_prodcount,count values for HWA15 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x2640++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_prod2_control,Controlling producer socket2 for HWA15" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "?,1: Producer socket 2 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_prod2_buf_control,Controlling producer socket2 buffer for HWA15" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_prod2_count,Defining count values for pre/post load for generating pend by HWA15 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_pa2_control,control register to manage pattern adapter on HWA15 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_pa2_prodcount,count values for HWA15 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x2660++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_prod3_control,Controlling producer socket3 for HWA15" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "?,1: Producer socket 3 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA15 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_prod3_buf_control,Controlling producer socket3 buffer for HWA15" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA15_prod3_count,Defining count values for pre/post load for generating pend by HWA15 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x2800++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_scheduler_control,Scheduler Control Register" bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "?,1: task skip enable" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "?,1: loop back start onto done in same cycle w/o.." newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA16" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA16 Scheduler resources must not be read during halted state. '1'-> HWA16 Scheduler resources are readable during halted state" "0: HWA16 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA16 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA16 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x2810++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP.." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA16 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA16 scheduler skip-enabled prod socket" group.long 0x2860++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_cons0_control,Controlling consumer socket 0 for HWA16" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA16 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x2868++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_cons1_control,Controlling consumer socket 1 for HWA16" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA16 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x28A0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_prod0_control,Controlling producer socket0 for HWA16" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "?,1: Producer socket 0 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_prod0_buf_control,Controlling producer socket0 buffer for HWA16" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_prod0_count,Defining count values for pre/post load for generating pend by HWA16 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_pa0_control,control register to manage pattern adapter on HWA16 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_pa0_prodcount,count values for HWA16 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x28C0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_prod1_control,Controlling producer socket1 for HWA16" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "?,1: Producer socket 1 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_prod1_buf_control,Controlling producer socket1 buffer for HWA16" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_prod1_count,Defining count values for pre/post load for generating pend by HWA16 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_pa1_control,control register to manage pattern adapter on HWA16 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_pa1_prodcount,count values for HWA16 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x28E0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_prod2_control,Controlling producer socket2 for HWA16" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "?,1: Producer socket 2 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_prod2_buf_control,Controlling producer socket2 buffer for HWA16" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_prod2_count,Defining count values for pre/post load for generating pend by HWA16 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_pa2_control,control register to manage pattern adapter on HWA16 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_pa2_prodcount,count values for HWA16 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x2900++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_prod3_control,Controlling producer socket3 for HWA16" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "?,1: Producer socket 3 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA16 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_prod3_buf_control,Controlling producer socket3 buffer for HWA16" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA16_prod3_count,Defining count values for pre/post load for generating pend by HWA16 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x2AA0++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_scheduler_control,Scheduler Control Register" bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "?,1: task skip enable" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "?,1: loop back start onto done in same cycle w/o.." newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA17" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA17 Scheduler resources must not be read during halted state. '1'-> HWA17 Scheduler resources are readable during halted state" "0: HWA17 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA17 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA17 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x2AB0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP.." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA17 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA17 scheduler skip-enabled prod socket" group.long 0x2B00++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_cons0_control,Controlling consumer socket 0 for HWA17" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA17 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x2B08++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_cons1_control,Controlling consumer socket 1 for HWA17" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA17 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x2B40++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_prod0_control,Controlling producer socket0 for HWA17" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "?,1: Producer socket 0 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_prod0_buf_control,Controlling producer socket0 buffer for HWA17" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_prod0_count,Defining count values for pre/post load for generating pend by HWA17 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_pa0_control,control register to manage pattern adapter on HWA17 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_pa0_prodcount,count values for HWA17 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x2B60++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_prod1_control,Controlling producer socket1 for HWA17" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "?,1: Producer socket 1 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_prod1_buf_control,Controlling producer socket1 buffer for HWA17" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_prod1_count,Defining count values for pre/post load for generating pend by HWA17 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_pa1_control,control register to manage pattern adapter on HWA17 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_pa1_prodcount,count values for HWA17 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x2B80++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_prod2_control,Controlling producer socket2 for HWA17" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "?,1: Producer socket 2 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_prod2_buf_control,Controlling producer socket2 buffer for HWA17" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_prod2_count,Defining count values for pre/post load for generating pend by HWA17 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_pa2_control,control register to manage pattern adapter on HWA17 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_pa2_prodcount,count values for HWA17 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x2BA0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_prod3_control,Controlling producer socket3 for HWA17" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "?,1: Producer socket 3 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA17 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_prod3_buf_control,Controlling producer socket3 buffer for HWA17" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA17_prod3_count,Defining count values for pre/post load for generating pend by HWA17 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x2D40++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_scheduler_control,Scheduler Control Register" bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "?,1: task skip enable" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "?,1: loop back start onto done in same cycle w/o.." newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA18" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA18 Scheduler resources must not be read during halted state. '1'-> HWA18 Scheduler resources are readable during halted state" "0: HWA18 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA18 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA18 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x2D50++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP.." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA18 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA18 scheduler skip-enabled prod socket" group.long 0x2DA0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_cons0_control,Controlling consumer socket 0 for HWA18" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA18 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x2DA8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_cons1_control,Controlling consumer socket 1 for HWA18" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA18 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x2DE0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_prod0_control,Controlling producer socket0 for HWA18" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "?,1: Producer socket 0 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_prod0_buf_control,Controlling producer socket0 buffer for HWA18" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_prod0_count,Defining count values for pre/post load for generating pend by HWA18 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_pa0_control,control register to manage pattern adapter on HWA18 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_pa0_prodcount,count values for HWA18 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x2E00++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_prod1_control,Controlling producer socket1 for HWA18" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "?,1: Producer socket 1 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_prod1_buf_control,Controlling producer socket1 buffer for HWA18" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_prod1_count,Defining count values for pre/post load for generating pend by HWA18 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_pa1_control,control register to manage pattern adapter on HWA18 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_pa1_prodcount,count values for HWA18 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x2E20++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_prod2_control,Controlling producer socket2 for HWA18" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "?,1: Producer socket 2 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_prod2_buf_control,Controlling producer socket2 buffer for HWA18" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_prod2_count,Defining count values for pre/post load for generating pend by HWA18 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_pa2_control,control register to manage pattern adapter on HWA18 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_pa2_prodcount,count values for HWA18 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x2E40++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_prod3_control,Controlling producer socket3 for HWA18" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "?,1: Producer socket 3 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA18 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_prod3_buf_control,Controlling producer socket3 buffer for HWA18" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA18_prod3_count,Defining count values for pre/post load for generating pend by HWA18 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x2FE0++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_scheduler_control,Scheduler Control Register" bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "?,1: task skip enable" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "?,1: loop back start onto done in same cycle w/o.." newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA19" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA19 Scheduler resources must not be read during halted state. '1'-> HWA19 Scheduler resources are readable during halted state" "0: HWA19 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA19 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA19 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x2FF0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP.." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA19 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA19 scheduler skip-enabled prod socket" group.long 0x3040++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_cons0_control,Controlling consumer socket 0 for HWA19" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA19 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x3048++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_cons1_control,Controlling consumer socket 1 for HWA19" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA19 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x3080++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_prod0_control,Controlling producer socket0 for HWA19" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "?,1: Producer socket 0 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_prod0_buf_control,Controlling producer socket0 buffer for HWA19" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_prod0_count,Defining count values for pre/post load for generating pend by HWA19 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_pa0_control,control register to manage pattern adapter on HWA19 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_pa0_prodcount,count values for HWA19 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x30A0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_prod1_control,Controlling producer socket1 for HWA19" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "?,1: Producer socket 1 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_prod1_buf_control,Controlling producer socket1 buffer for HWA19" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_prod1_count,Defining count values for pre/post load for generating pend by HWA19 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_pa1_control,control register to manage pattern adapter on HWA19 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_pa1_prodcount,count values for HWA19 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x30C0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_prod2_control,Controlling producer socket2 for HWA19" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "?,1: Producer socket 2 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_prod2_buf_control,Controlling producer socket2 buffer for HWA19" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_prod2_count,Defining count values for pre/post load for generating pend by HWA19 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_pa2_control,control register to manage pattern adapter on HWA19 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_pa2_prodcount,count values for HWA19 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x30E0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_prod3_control,Controlling producer socket3 for HWA19" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "?,1: Producer socket 3 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA19 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_prod3_buf_control,Controlling producer socket3 buffer for HWA19" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA19_prod3_count,Defining count values for pre/post load for generating pend by HWA19 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x3280++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_scheduler_control,Scheduler Control Register" bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "?,1: task skip enable" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "?,1: loop back start onto done in same cycle w/o.." newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA20" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA20 Scheduler resources must not be read during halted state. '1'-> HWA20 Scheduler resources are readable during halted state" "0: HWA20 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA20 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA20 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x3290++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP.." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA20 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA20 scheduler skip-enabled prod socket" group.long 0x32E0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_cons0_control,Controlling consumer socket 0 for HWA20" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA20 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x32E8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_cons1_control,Controlling consumer socket 1 for HWA20" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA20 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x3320++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_prod0_control,Controlling producer socket0 for HWA20" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "?,1: Producer socket 0 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA20 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_prod0_buf_control,Controlling producer socket0 buffer for HWA20" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_prod0_count,Defining count values for pre/post load for generating pend by HWA20 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_pa0_control,control register to manage pattern adapter on HWA20 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_pa0_prodcount,count values for HWA20 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x3340++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_prod1_control,Controlling producer socket1 for HWA20" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "?,1: Producer socket 1 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA20 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_prod1_buf_control,Controlling producer socket1 buffer for HWA20" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_prod1_count,Defining count values for pre/post load for generating pend by HWA20 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_pa1_control,control register to manage pattern adapter on HWA20 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_pa1_prodcount,count values for HWA20 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x3360++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_prod2_control,Controlling producer socket2 for HWA20" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "?,1: Producer socket 2 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA20 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_prod2_buf_control,Controlling producer socket2 buffer for HWA20" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_prod2_count,Defining count values for pre/post load for generating pend by HWA20 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_pa2_control,control register to manage pattern adapter on HWA20 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_pa2_prodcount,count values for HWA20 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x3380++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_prod3_control,Controlling producer socket3 for HWA20" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "?,1: Producer socket 3 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA20 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_prod3_buf_control,Controlling producer socket3 buffer for HWA20" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA20_prod3_count,Defining count values for pre/post load for generating pend by HWA20 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x3520++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_scheduler_control,Scheduler Control Register" bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "?,1: task skip enable" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "?,1: loop back start onto done in same cycle w/o.." newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA21" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA21 Scheduler resources must not be read during halted state. '1'-> HWA21 Scheduler resources are readable during halted state" "0: HWA21 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA21 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA21 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x3530++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP.." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA21 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA21 scheduler skip-enabled prod socket" group.long 0x3580++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_cons0_control,Controlling consumer socket 0 for HWA21" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA21 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x3588++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_cons1_control,Controlling consumer socket 1 for HWA21" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA21 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x35C0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_prod0_control,Controlling producer socket0 for HWA21" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "?,1: Producer socket 0 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA21 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_prod0_buf_control,Controlling producer socket0 buffer for HWA21" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_prod0_count,Defining count values for pre/post load for generating pend by HWA21 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_pa0_control,control register to manage pattern adapter on HWA21 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_pa0_prodcount,count values for HWA21 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x35E0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_prod1_control,Controlling producer socket1 for HWA21" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "?,1: Producer socket 1 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA21 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_prod1_buf_control,Controlling producer socket1 buffer for HWA21" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_prod1_count,Defining count values for pre/post load for generating pend by HWA21 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_pa1_control,control register to manage pattern adapter on HWA21 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_pa1_prodcount,count values for HWA21 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x3600++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_prod2_control,Controlling producer socket2 for HWA21" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "?,1: Producer socket 2 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA21 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_prod2_buf_control,Controlling producer socket2 buffer for HWA21" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_prod2_count,Defining count values for pre/post load for generating pend by HWA21 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_pa2_control,control register to manage pattern adapter on HWA21 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_pa2_prodcount,count values for HWA21 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x3620++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_prod3_control,Controlling producer socket3 for HWA21" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "?,1: Producer socket 3 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA21 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_prod3_buf_control,Controlling producer socket3 buffer for HWA21" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA21_prod3_count,Defining count values for pre/post load for generating pend by HWA21 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x4240++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_scheduler_control,Scheduler Control Register" bitfld.long 0x0 25. "CHANNEL_LINK_EN,'1' -> Trigger dma_channel_no for chanel_count_set0.count0 times --> Trigger dma_channel_no+1 for chanel_count_set0.count1 times --> Trigger dma_channel_no+2 for chanel_count_set1.count0 times .. repeat till either total count reaches HOP.." "?,1: Trigger dma_channel_no for chanel_count_set0" newline bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "?,1: task skip enable" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "?,1: loop back start onto done in same cycle w/o.." newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA26" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA26 Scheduler resources must not be read during halted state. '1'-> HWA26 Scheduler resources are readable during halted state" "0: HWA26 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA26 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA26 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x4250++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP.." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA26 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA26 scheduler skip-enabled prod socket" group.long 0x4260++0x17 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_channel_count_set0,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x0 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+1 HWA26_channel_count_set0.count1 times before linking to next HWA26_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x0 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+0 HWA26_channel_count_set0.count0 times before linking to count1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_channel_count_set1,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x4 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+3 HWA26_channel_count_set1.count1 times before linking to next HWA26_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x4 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+2 HWA26_channel_count_set1.count0 times before linking to count1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_channel_count_set2,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x8 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+5 HWA26_channel_count_set2.count1 times before linking to next HWA26_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x8 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+4 HWA26_channel_count_set2.count0 times before linking to count1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_channel_count_set3,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0xC 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+7 HWA26_channel_count_set3.count1 times before linking to next HWA26_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0xC 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+6 HWA26_channel_count_set3.count0 times before linking to count1" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_channel_count_set4,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x10 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+9 HWA26_channel_count_set4.count1 times before linking to next HWA26_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x10 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+8 HWA26_channel_count_set4.count0 times before linking to count1" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_channel_count_set5,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x14 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+11 HWA26_channel_count_set5.count1 times before linking to next HWA26_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x14 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+10 HWA26_channel_count_set5.count0 times before linking to count1" group.long 0x42A0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_cons0_control,Controlling consumer socket 0 for HWA26" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA26 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x42A8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_cons1_control,Controlling consumer socket 1 for HWA26" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA26 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x42E0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_prod0_control,Controlling producer socket0 for HWA26" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "?,1: Producer socket 0 skip enable" newline bitfld.long 0x0 16. "DYNAMIC_TH_EN,'1' -> Dynamic Thresholding Enabled for Producer socket 0 '0' Disable Dynamic Thresholding" "?,1: Dynamic Thresholding Enabled for Producer socket 0" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA26 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_prod0_buf_control,Controlling producer socket0 buffer for HWA26" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_prod0_count,Defining count values for pre/post load for generating pend by HWA26 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_pa0_control,control register to manage pattern adapter on HWA26 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_pa0_prodcount,count values for HWA26 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x4300++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_prod1_control,Controlling producer socket1 for HWA26" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "?,1: Producer socket 1 skip enable" newline bitfld.long 0x0 16. "DYNAMIC_TH_EN,'1' -> Dynamic Thresholding Enabled for Producer socket 1 '0' Disable Dynamic Thresholding" "?,1: Dynamic Thresholding Enabled for Producer socket 1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA26 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_prod1_buf_control,Controlling producer socket1 buffer for HWA26" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_prod1_count,Defining count values for pre/post load for generating pend by HWA26 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_pa1_control,control register to manage pattern adapter on HWA26 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_pa1_prodcount,count values for HWA26 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x4320++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_prod2_control,Controlling producer socket2 for HWA26" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "?,1: Producer socket 2 skip enable" newline bitfld.long 0x0 16. "DYNAMIC_TH_EN,'1' -> Dynamic Thresholding Enabled for Producer socket 2 '0' Disable Dynamic Thresholding" "?,1: Dynamic Thresholding Enabled for Producer socket 2" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA26 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_prod2_buf_control,Controlling producer socket2 buffer for HWA26" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_prod2_count,Defining count values for pre/post load for generating pend by HWA26 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_pa2_control,control register to manage pattern adapter on HWA26 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_pa2_prodcount,count values for HWA26 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x4340++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_prod3_control,Controlling producer socket3 for HWA26" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "?,1: Producer socket 3 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA26 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_prod3_buf_control,Controlling producer socket3 buffer for HWA26" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_prod3_count,Defining count values for pre/post load for generating pend by HWA26 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x44E0++0x1FF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold0,csmaxcount and count_dec value for Row No 0. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 0 when dynamic threshold feature is enabled" newline hexmask.long.word 0x0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 0 when dynamic threshold feature is enabled" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold1,csmaxcount and count_dec value for Row No 1. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 1 when dynamic threshold feature is enabled" newline hexmask.long.word 0x4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 1 when dynamic threshold feature is enabled" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold2,csmaxcount and count_dec value for Row No 2. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 2 when dynamic threshold feature is enabled" newline hexmask.long.word 0x8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 2 when dynamic threshold feature is enabled" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold3,csmaxcount and count_dec value for Row No 3. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 3 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 3 when dynamic threshold feature is enabled" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold4,csmaxcount and count_dec value for Row No 4. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x10 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 4 when dynamic threshold feature is enabled" newline hexmask.long.word 0x10 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 4 when dynamic threshold feature is enabled" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold5,csmaxcount and count_dec value for Row No 5. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x14 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 5 when dynamic threshold feature is enabled" newline hexmask.long.word 0x14 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 5 when dynamic threshold feature is enabled" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold6,csmaxcount and count_dec value for Row No 6. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x18 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 6 when dynamic threshold feature is enabled" newline hexmask.long.word 0x18 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 6 when dynamic threshold feature is enabled" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold7,csmaxcount and count_dec value for Row No 7. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 7 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 7 when dynamic threshold feature is enabled" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold8,csmaxcount and count_dec value for Row No 8. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x20 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 8 when dynamic threshold feature is enabled" newline hexmask.long.word 0x20 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 8 when dynamic threshold feature is enabled" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold9,csmaxcount and count_dec value for Row No 9. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x24 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 9 when dynamic threshold feature is enabled" newline hexmask.long.word 0x24 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 9 when dynamic threshold feature is enabled" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold10,csmaxcount and count_dec value for Row No 10. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x28 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 10 when dynamic threshold feature is enabled" newline hexmask.long.word 0x28 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 10 when dynamic threshold feature is enabled" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold11,csmaxcount and count_dec value for Row No 11. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x2C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 11 when dynamic threshold feature is enabled" newline hexmask.long.word 0x2C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 11 when dynamic threshold feature is enabled" line.long 0x30 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold12,csmaxcount and count_dec value for Row No 12. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x30 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 12 when dynamic threshold feature is enabled" newline hexmask.long.word 0x30 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 12 when dynamic threshold feature is enabled" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold13,csmaxcount and count_dec value for Row No 13. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x34 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 13 when dynamic threshold feature is enabled" newline hexmask.long.word 0x34 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 13 when dynamic threshold feature is enabled" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold14,csmaxcount and count_dec value for Row No 14. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x38 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 14 when dynamic threshold feature is enabled" newline hexmask.long.word 0x38 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 14 when dynamic threshold feature is enabled" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold15,csmaxcount and count_dec value for Row No 15. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x3C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 15 when dynamic threshold feature is enabled" newline hexmask.long.word 0x3C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 15 when dynamic threshold feature is enabled" line.long 0x40 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold16,csmaxcount and count_dec value for Row No 16. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x40 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 16 when dynamic threshold feature is enabled" newline hexmask.long.word 0x40 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 16 when dynamic threshold feature is enabled" line.long 0x44 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold17,csmaxcount and count_dec value for Row No 17. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x44 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 17 when dynamic threshold feature is enabled" newline hexmask.long.word 0x44 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 17 when dynamic threshold feature is enabled" line.long 0x48 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold18,csmaxcount and count_dec value for Row No 18. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x48 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 18 when dynamic threshold feature is enabled" newline hexmask.long.word 0x48 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 18 when dynamic threshold feature is enabled" line.long 0x4C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold19,csmaxcount and count_dec value for Row No 19. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x4C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 19 when dynamic threshold feature is enabled" newline hexmask.long.word 0x4C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 19 when dynamic threshold feature is enabled" line.long 0x50 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold20,csmaxcount and count_dec value for Row No 20. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x50 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 20 when dynamic threshold feature is enabled" newline hexmask.long.word 0x50 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 20 when dynamic threshold feature is enabled" line.long 0x54 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold21,csmaxcount and count_dec value for Row No 21. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x54 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 21 when dynamic threshold feature is enabled" newline hexmask.long.word 0x54 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 21 when dynamic threshold feature is enabled" line.long 0x58 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold22,csmaxcount and count_dec value for Row No 22. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x58 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 22 when dynamic threshold feature is enabled" newline hexmask.long.word 0x58 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 22 when dynamic threshold feature is enabled" line.long 0x5C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold23,csmaxcount and count_dec value for Row No 23. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x5C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 23 when dynamic threshold feature is enabled" newline hexmask.long.word 0x5C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 23 when dynamic threshold feature is enabled" line.long 0x60 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold24,csmaxcount and count_dec value for Row No 24. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x60 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 24 when dynamic threshold feature is enabled" newline hexmask.long.word 0x60 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 24 when dynamic threshold feature is enabled" line.long 0x64 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold25,csmaxcount and count_dec value for Row No 25. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x64 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 25 when dynamic threshold feature is enabled" newline hexmask.long.word 0x64 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 25 when dynamic threshold feature is enabled" line.long 0x68 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold26,csmaxcount and count_dec value for Row No 26. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x68 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 26 when dynamic threshold feature is enabled" newline hexmask.long.word 0x68 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 26 when dynamic threshold feature is enabled" line.long 0x6C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold27,csmaxcount and count_dec value for Row No 27. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x6C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 27 when dynamic threshold feature is enabled" newline hexmask.long.word 0x6C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 27 when dynamic threshold feature is enabled" line.long 0x70 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold28,csmaxcount and count_dec value for Row No 28. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x70 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 28 when dynamic threshold feature is enabled" newline hexmask.long.word 0x70 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 28 when dynamic threshold feature is enabled" line.long 0x74 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold29,csmaxcount and count_dec value for Row No 29. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x74 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 29 when dynamic threshold feature is enabled" newline hexmask.long.word 0x74 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 29 when dynamic threshold feature is enabled" line.long 0x78 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold30,csmaxcount and count_dec value for Row No 30. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x78 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 30 when dynamic threshold feature is enabled" newline hexmask.long.word 0x78 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 30 when dynamic threshold feature is enabled" line.long 0x7C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold31,csmaxcount and count_dec value for Row No 31. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x7C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 31 when dynamic threshold feature is enabled" newline hexmask.long.word 0x7C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 31 when dynamic threshold feature is enabled" line.long 0x80 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold32,csmaxcount and count_dec value for Row No 32. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x80 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 32 when dynamic threshold feature is enabled" newline hexmask.long.word 0x80 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 32 when dynamic threshold feature is enabled" line.long 0x84 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold33,csmaxcount and count_dec value for Row No 33. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x84 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 33 when dynamic threshold feature is enabled" newline hexmask.long.word 0x84 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 33 when dynamic threshold feature is enabled" line.long 0x88 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold34,csmaxcount and count_dec value for Row No 34. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x88 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 34 when dynamic threshold feature is enabled" newline hexmask.long.word 0x88 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 34 when dynamic threshold feature is enabled" line.long 0x8C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold35,csmaxcount and count_dec value for Row No 35. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x8C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 35 when dynamic threshold feature is enabled" newline hexmask.long.word 0x8C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 35 when dynamic threshold feature is enabled" line.long 0x90 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold36,csmaxcount and count_dec value for Row No 36. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x90 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 36 when dynamic threshold feature is enabled" newline hexmask.long.word 0x90 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 36 when dynamic threshold feature is enabled" line.long 0x94 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold37,csmaxcount and count_dec value for Row No 37. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x94 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 37 when dynamic threshold feature is enabled" newline hexmask.long.word 0x94 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 37 when dynamic threshold feature is enabled" line.long 0x98 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold38,csmaxcount and count_dec value for Row No 38. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x98 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 38 when dynamic threshold feature is enabled" newline hexmask.long.word 0x98 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 38 when dynamic threshold feature is enabled" line.long 0x9C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold39,csmaxcount and count_dec value for Row No 39. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x9C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 39 when dynamic threshold feature is enabled" newline hexmask.long.word 0x9C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 39 when dynamic threshold feature is enabled" line.long 0xA0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold40,csmaxcount and count_dec value for Row No 40. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xA0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 40 when dynamic threshold feature is enabled" newline hexmask.long.word 0xA0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 40 when dynamic threshold feature is enabled" line.long 0xA4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold41,csmaxcount and count_dec value for Row No 41. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xA4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 41 when dynamic threshold feature is enabled" newline hexmask.long.word 0xA4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 41 when dynamic threshold feature is enabled" line.long 0xA8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold42,csmaxcount and count_dec value for Row No 42. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xA8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 42 when dynamic threshold feature is enabled" newline hexmask.long.word 0xA8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 42 when dynamic threshold feature is enabled" line.long 0xAC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold43,csmaxcount and count_dec value for Row No 43. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xAC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 43 when dynamic threshold feature is enabled" newline hexmask.long.word 0xAC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 43 when dynamic threshold feature is enabled" line.long 0xB0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold44,csmaxcount and count_dec value for Row No 44. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xB0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 44 when dynamic threshold feature is enabled" newline hexmask.long.word 0xB0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 44 when dynamic threshold feature is enabled" line.long 0xB4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold45,csmaxcount and count_dec value for Row No 45. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xB4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 45 when dynamic threshold feature is enabled" newline hexmask.long.word 0xB4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 45 when dynamic threshold feature is enabled" line.long 0xB8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold46,csmaxcount and count_dec value for Row No 46. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xB8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 46 when dynamic threshold feature is enabled" newline hexmask.long.word 0xB8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 46 when dynamic threshold feature is enabled" line.long 0xBC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold47,csmaxcount and count_dec value for Row No 47. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xBC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 47 when dynamic threshold feature is enabled" newline hexmask.long.word 0xBC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 47 when dynamic threshold feature is enabled" line.long 0xC0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold48,csmaxcount and count_dec value for Row No 48. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 48 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 48 when dynamic threshold feature is enabled" line.long 0xC4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold49,csmaxcount and count_dec value for Row No 49. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 49 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 49 when dynamic threshold feature is enabled" line.long 0xC8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold50,csmaxcount and count_dec value for Row No 50. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 50 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 50 when dynamic threshold feature is enabled" line.long 0xCC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold51,csmaxcount and count_dec value for Row No 51. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xCC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 51 when dynamic threshold feature is enabled" newline hexmask.long.word 0xCC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 51 when dynamic threshold feature is enabled" line.long 0xD0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold52,csmaxcount and count_dec value for Row No 52. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xD0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 52 when dynamic threshold feature is enabled" newline hexmask.long.word 0xD0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 52 when dynamic threshold feature is enabled" line.long 0xD4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold53,csmaxcount and count_dec value for Row No 53. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xD4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 53 when dynamic threshold feature is enabled" newline hexmask.long.word 0xD4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 53 when dynamic threshold feature is enabled" line.long 0xD8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold54,csmaxcount and count_dec value for Row No 54. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xD8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 54 when dynamic threshold feature is enabled" newline hexmask.long.word 0xD8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 54 when dynamic threshold feature is enabled" line.long 0xDC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold55,csmaxcount and count_dec value for Row No 55. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xDC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 55 when dynamic threshold feature is enabled" newline hexmask.long.word 0xDC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 55 when dynamic threshold feature is enabled" line.long 0xE0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold56,csmaxcount and count_dec value for Row No 56. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xE0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 56 when dynamic threshold feature is enabled" newline hexmask.long.word 0xE0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 56 when dynamic threshold feature is enabled" line.long 0xE4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold57,csmaxcount and count_dec value for Row No 57. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xE4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 57 when dynamic threshold feature is enabled" newline hexmask.long.word 0xE4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 57 when dynamic threshold feature is enabled" line.long 0xE8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold58,csmaxcount and count_dec value for Row No 58. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xE8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 58 when dynamic threshold feature is enabled" newline hexmask.long.word 0xE8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 58 when dynamic threshold feature is enabled" line.long 0xEC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold59,csmaxcount and count_dec value for Row No 59. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xEC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 59 when dynamic threshold feature is enabled" newline hexmask.long.word 0xEC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 59 when dynamic threshold feature is enabled" line.long 0xF0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold60,csmaxcount and count_dec value for Row No 60. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xF0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 60 when dynamic threshold feature is enabled" newline hexmask.long.word 0xF0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 60 when dynamic threshold feature is enabled" line.long 0xF4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold61,csmaxcount and count_dec value for Row No 61. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xF4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 61 when dynamic threshold feature is enabled" newline hexmask.long.word 0xF4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 61 when dynamic threshold feature is enabled" line.long 0xF8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold62,csmaxcount and count_dec value for Row No 62. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xF8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 62 when dynamic threshold feature is enabled" newline hexmask.long.word 0xF8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 62 when dynamic threshold feature is enabled" line.long 0xFC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold63,csmaxcount and count_dec value for Row No 63. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xFC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 63 when dynamic threshold feature is enabled" newline hexmask.long.word 0xFC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 63 when dynamic threshold feature is enabled" line.long 0x100 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold64,csmaxcount and count_dec value for Row No 64. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x100 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 64 when dynamic threshold feature is enabled" newline hexmask.long.word 0x100 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 64 when dynamic threshold feature is enabled" line.long 0x104 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold65,csmaxcount and count_dec value for Row No 65. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x104 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 65 when dynamic threshold feature is enabled" newline hexmask.long.word 0x104 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 65 when dynamic threshold feature is enabled" line.long 0x108 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold66,csmaxcount and count_dec value for Row No 66. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x108 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 66 when dynamic threshold feature is enabled" newline hexmask.long.word 0x108 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 66 when dynamic threshold feature is enabled" line.long 0x10C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold67,csmaxcount and count_dec value for Row No 67. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x10C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 67 when dynamic threshold feature is enabled" newline hexmask.long.word 0x10C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 67 when dynamic threshold feature is enabled" line.long 0x110 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold68,csmaxcount and count_dec value for Row No 68. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x110 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 68 when dynamic threshold feature is enabled" newline hexmask.long.word 0x110 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 68 when dynamic threshold feature is enabled" line.long 0x114 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold69,csmaxcount and count_dec value for Row No 69. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x114 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 69 when dynamic threshold feature is enabled" newline hexmask.long.word 0x114 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 69 when dynamic threshold feature is enabled" line.long 0x118 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold70,csmaxcount and count_dec value for Row No 70. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x118 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 70 when dynamic threshold feature is enabled" newline hexmask.long.word 0x118 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 70 when dynamic threshold feature is enabled" line.long 0x11C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold71,csmaxcount and count_dec value for Row No 71. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x11C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 71 when dynamic threshold feature is enabled" newline hexmask.long.word 0x11C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 71 when dynamic threshold feature is enabled" line.long 0x120 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold72,csmaxcount and count_dec value for Row No 72. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x120 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 72 when dynamic threshold feature is enabled" newline hexmask.long.word 0x120 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 72 when dynamic threshold feature is enabled" line.long 0x124 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold73,csmaxcount and count_dec value for Row No 73. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x124 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 73 when dynamic threshold feature is enabled" newline hexmask.long.word 0x124 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 73 when dynamic threshold feature is enabled" line.long 0x128 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold74,csmaxcount and count_dec value for Row No 74. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x128 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 74 when dynamic threshold feature is enabled" newline hexmask.long.word 0x128 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 74 when dynamic threshold feature is enabled" line.long 0x12C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold75,csmaxcount and count_dec value for Row No 75. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x12C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 75 when dynamic threshold feature is enabled" newline hexmask.long.word 0x12C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 75 when dynamic threshold feature is enabled" line.long 0x130 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold76,csmaxcount and count_dec value for Row No 76. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x130 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 76 when dynamic threshold feature is enabled" newline hexmask.long.word 0x130 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 76 when dynamic threshold feature is enabled" line.long 0x134 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold77,csmaxcount and count_dec value for Row No 77. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x134 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 77 when dynamic threshold feature is enabled" newline hexmask.long.word 0x134 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 77 when dynamic threshold feature is enabled" line.long 0x138 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold78,csmaxcount and count_dec value for Row No 78. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x138 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 78 when dynamic threshold feature is enabled" newline hexmask.long.word 0x138 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 78 when dynamic threshold feature is enabled" line.long 0x13C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold79,csmaxcount and count_dec value for Row No 79. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x13C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 79 when dynamic threshold feature is enabled" newline hexmask.long.word 0x13C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 79 when dynamic threshold feature is enabled" line.long 0x140 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold80,csmaxcount and count_dec value for Row No 80. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x140 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 80 when dynamic threshold feature is enabled" newline hexmask.long.word 0x140 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 80 when dynamic threshold feature is enabled" line.long 0x144 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold81,csmaxcount and count_dec value for Row No 81. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x144 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 81 when dynamic threshold feature is enabled" newline hexmask.long.word 0x144 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 81 when dynamic threshold feature is enabled" line.long 0x148 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold82,csmaxcount and count_dec value for Row No 82. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x148 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 82 when dynamic threshold feature is enabled" newline hexmask.long.word 0x148 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 82 when dynamic threshold feature is enabled" line.long 0x14C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold83,csmaxcount and count_dec value for Row No 83. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x14C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 83 when dynamic threshold feature is enabled" newline hexmask.long.word 0x14C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 83 when dynamic threshold feature is enabled" line.long 0x150 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold84,csmaxcount and count_dec value for Row No 84. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x150 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 84 when dynamic threshold feature is enabled" newline hexmask.long.word 0x150 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 84 when dynamic threshold feature is enabled" line.long 0x154 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold85,csmaxcount and count_dec value for Row No 85. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x154 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 85 when dynamic threshold feature is enabled" newline hexmask.long.word 0x154 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 85 when dynamic threshold feature is enabled" line.long 0x158 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold86,csmaxcount and count_dec value for Row No 86. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x158 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 86 when dynamic threshold feature is enabled" newline hexmask.long.word 0x158 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 86 when dynamic threshold feature is enabled" line.long 0x15C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold87,csmaxcount and count_dec value for Row No 87. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x15C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 87 when dynamic threshold feature is enabled" newline hexmask.long.word 0x15C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 87 when dynamic threshold feature is enabled" line.long 0x160 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold88,csmaxcount and count_dec value for Row No 88. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x160 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 88 when dynamic threshold feature is enabled" newline hexmask.long.word 0x160 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 88 when dynamic threshold feature is enabled" line.long 0x164 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold89,csmaxcount and count_dec value for Row No 89. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x164 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 89 when dynamic threshold feature is enabled" newline hexmask.long.word 0x164 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 89 when dynamic threshold feature is enabled" line.long 0x168 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold90,csmaxcount and count_dec value for Row No 90. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x168 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 90 when dynamic threshold feature is enabled" newline hexmask.long.word 0x168 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 90 when dynamic threshold feature is enabled" line.long 0x16C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold91,csmaxcount and count_dec value for Row No 91. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x16C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 91 when dynamic threshold feature is enabled" newline hexmask.long.word 0x16C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 91 when dynamic threshold feature is enabled" line.long 0x170 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold92,csmaxcount and count_dec value for Row No 92. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x170 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 92 when dynamic threshold feature is enabled" newline hexmask.long.word 0x170 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 92 when dynamic threshold feature is enabled" line.long 0x174 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold93,csmaxcount and count_dec value for Row No 93. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x174 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 93 when dynamic threshold feature is enabled" newline hexmask.long.word 0x174 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 93 when dynamic threshold feature is enabled" line.long 0x178 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold94,csmaxcount and count_dec value for Row No 94. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x178 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 94 when dynamic threshold feature is enabled" newline hexmask.long.word 0x178 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 94 when dynamic threshold feature is enabled" line.long 0x17C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold95,csmaxcount and count_dec value for Row No 95. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x17C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 95 when dynamic threshold feature is enabled" newline hexmask.long.word 0x17C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 95 when dynamic threshold feature is enabled" line.long 0x180 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold96,csmaxcount and count_dec value for Row No 96. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x180 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 96 when dynamic threshold feature is enabled" newline hexmask.long.word 0x180 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 96 when dynamic threshold feature is enabled" line.long 0x184 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold97,csmaxcount and count_dec value for Row No 97. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x184 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 97 when dynamic threshold feature is enabled" newline hexmask.long.word 0x184 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 97 when dynamic threshold feature is enabled" line.long 0x188 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold98,csmaxcount and count_dec value for Row No 98. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x188 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 98 when dynamic threshold feature is enabled" newline hexmask.long.word 0x188 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 98 when dynamic threshold feature is enabled" line.long 0x18C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold99,csmaxcount and count_dec value for Row No 99. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x18C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 99 when dynamic threshold feature is enabled" newline hexmask.long.word 0x18C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 99 when dynamic threshold feature is enabled" line.long 0x190 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold100,csmaxcount and count_dec value for Row No 100. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x190 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 100 when dynamic threshold feature is enabled" newline hexmask.long.word 0x190 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 100 when dynamic threshold feature is enabled" line.long 0x194 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold101,csmaxcount and count_dec value for Row No 101. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x194 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 101 when dynamic threshold feature is enabled" newline hexmask.long.word 0x194 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 101 when dynamic threshold feature is enabled" line.long 0x198 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold102,csmaxcount and count_dec value for Row No 102. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x198 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 102 when dynamic threshold feature is enabled" newline hexmask.long.word 0x198 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 102 when dynamic threshold feature is enabled" line.long 0x19C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold103,csmaxcount and count_dec value for Row No 103. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x19C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 103 when dynamic threshold feature is enabled" newline hexmask.long.word 0x19C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 103 when dynamic threshold feature is enabled" line.long 0x1A0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold104,csmaxcount and count_dec value for Row No 104. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1A0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 104 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1A0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 104 when dynamic threshold feature is enabled" line.long 0x1A4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold105,csmaxcount and count_dec value for Row No 105. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1A4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 105 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1A4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 105 when dynamic threshold feature is enabled" line.long 0x1A8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold106,csmaxcount and count_dec value for Row No 106. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1A8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 106 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1A8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 106 when dynamic threshold feature is enabled" line.long 0x1AC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold107,csmaxcount and count_dec value for Row No 107. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1AC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 107 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1AC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 107 when dynamic threshold feature is enabled" line.long 0x1B0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold108,csmaxcount and count_dec value for Row No 108. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1B0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 108 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1B0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 108 when dynamic threshold feature is enabled" line.long 0x1B4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold109,csmaxcount and count_dec value for Row No 109. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1B4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 109 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1B4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 109 when dynamic threshold feature is enabled" line.long 0x1B8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold110,csmaxcount and count_dec value for Row No 110. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1B8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 110 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1B8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 110 when dynamic threshold feature is enabled" line.long 0x1BC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold111,csmaxcount and count_dec value for Row No 111. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1BC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 111 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1BC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 111 when dynamic threshold feature is enabled" line.long 0x1C0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold112,csmaxcount and count_dec value for Row No 112. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 112 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 112 when dynamic threshold feature is enabled" line.long 0x1C4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold113,csmaxcount and count_dec value for Row No 113. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 113 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 113 when dynamic threshold feature is enabled" line.long 0x1C8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold114,csmaxcount and count_dec value for Row No 114. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 114 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 114 when dynamic threshold feature is enabled" line.long 0x1CC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold115,csmaxcount and count_dec value for Row No 115. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1CC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 115 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1CC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 115 when dynamic threshold feature is enabled" line.long 0x1D0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold116,csmaxcount and count_dec value for Row No 116. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1D0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 116 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1D0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 116 when dynamic threshold feature is enabled" line.long 0x1D4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold117,csmaxcount and count_dec value for Row No 117. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1D4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 117 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1D4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 117 when dynamic threshold feature is enabled" line.long 0x1D8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold118,csmaxcount and count_dec value for Row No 118. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1D8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 118 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1D8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 118 when dynamic threshold feature is enabled" line.long 0x1DC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold119,csmaxcount and count_dec value for Row No 119. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1DC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 119 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1DC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 119 when dynamic threshold feature is enabled" line.long 0x1E0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold120,csmaxcount and count_dec value for Row No 120. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1E0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 120 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1E0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 120 when dynamic threshold feature is enabled" line.long 0x1E4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold121,csmaxcount and count_dec value for Row No 121. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1E4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 121 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1E4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 121 when dynamic threshold feature is enabled" line.long 0x1E8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold122,csmaxcount and count_dec value for Row No 122. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1E8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 122 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1E8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 122 when dynamic threshold feature is enabled" line.long 0x1EC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold123,csmaxcount and count_dec value for Row No 123. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1EC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 123 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1EC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 123 when dynamic threshold feature is enabled" line.long 0x1F0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold124,csmaxcount and count_dec value for Row No 124. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1F0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 124 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1F0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 124 when dynamic threshold feature is enabled" line.long 0x1F4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold125,csmaxcount and count_dec value for Row No 125. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1F4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 125 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1F4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 125 when dynamic threshold feature is enabled" line.long 0x1F8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold126,csmaxcount and count_dec value for Row No 126. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1F8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 126 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1F8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 126 when dynamic threshold feature is enabled" line.long 0x1FC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA26_dynamic_threshold127,csmaxcount and count_dec value for Row No 127. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1FC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 127 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1FC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 127 when dynamic threshold feature is enabled" group.long 0x4780++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_scheduler_control,Scheduler Control Register" bitfld.long 0x0 25. "CHANNEL_LINK_EN,'1' -> Trigger dma_channel_no for chanel_count_set0.count0 times --> Trigger dma_channel_no+1 for chanel_count_set0.count1 times --> Trigger dma_channel_no+2 for chanel_count_set1.count0 times .. repeat till either total count reaches HOP.." "?,1: Trigger dma_channel_no for chanel_count_set0" newline bitfld.long 0x0 24. "SKIP_TASK_EN,'1' -> task skip enable '0' Disable" "?,1: task skip enable" newline bitfld.long 0x0 23. "START_LOOP_BACK,'1' -> loop back start onto done in same cycle w/o asserting external channel start '0' No loop back" "?,1: loop back start onto done in same cycle w/o.." newline hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for HWA27" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> HWA27 Scheduler resources must not be read during halted state. '1'-> HWA27 Scheduler resources are readable during halted state" "0: HWA27 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of HWA27 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of HWA27 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x4790++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_skip_control,Scheduler Skip Control Register. If enabled in specific prod socket. tdones within skip_top and skip_bot is included in pend generation. tdone_count_en bit in HOP needs to be set to use SKIP.." hexmask.long.word 0x0 16.--28. 1. "SKIP_BOT,skip/ignore tdone from tdone_count=skip_bot till eop in HWA27 scheduler skip-enabled prod socket" newline hexmask.long.word 0x0 0.--12. 1. "SKIP_TOP,skip/ignore tdone from tdone_count=0 till tdone_count=skip_top value in HWA27 scheduler skip-enabled prod socket" group.long 0x47A0++0x17 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_channel_count_set0,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x0 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+1 HWA27_channel_count_set0.count1 times before linking to next HWA27_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x0 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+0 HWA27_channel_count_set0.count0 times before linking to count1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_channel_count_set1,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x4 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+3 HWA27_channel_count_set1.count1 times before linking to next HWA27_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x4 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+2 HWA27_channel_count_set1.count0 times before linking to count1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_channel_count_set2,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x8 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+5 HWA27_channel_count_set2.count1 times before linking to next HWA27_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x8 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+4 HWA27_channel_count_set2.count0 times before linking to count1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_channel_count_set3,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0xC 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+7 HWA27_channel_count_set3.count1 times before linking to next HWA27_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0xC 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+6 HWA27_channel_count_set3.count0 times before linking to count1" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_channel_count_set4,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x10 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+9 HWA27_channel_count_set4.count1 times before linking to next HWA27_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x10 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+8 HWA27_channel_count_set4.count0 times before linking to count1" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_channel_count_set5,Scheduler channel count. If enabled in specific pare scheduler configured channel number is triggered for set0.count0 followed by set0.count1 before linking to set1 parameters" hexmask.long.word 0x14 16.--28. 1. "COUNT1,When channel_link_en is set trigger dma_channel_no+11 HWA27_channel_count_set5.count1 times before linking to next HWA27_channel_count_set. set5 links to set0 if total trigger count exceeds hop_count" newline hexmask.long.word 0x14 0.--12. 1. "COUNT0,When channel_link_en is set trigger dma_channel_no+10 HWA27_channel_count_set5.count0 times before linking to count1" group.long 0x47E0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_cons0_control,Controlling consumer socket 0 for HWA27" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA27 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x47E8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_cons1_control,Controlling consumer socket 1 for HWA27" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for HWA27 cons socket 1" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 1 enable '0' Disable" "?,1: Consumer socket 1 enable" group.long 0x4820++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_prod0_control,Controlling producer socket0 for HWA27" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 0 skip enable '0' Disable" "?,1: Producer socket 0 skip enable" newline bitfld.long 0x0 16. "DYNAMIC_TH_EN,'1' -> Dynamic Thresholding Enabled for Producer socket 0 '0' Disable Dynamic Thresholding" "?,1: Dynamic Thresholding Enabled for Producer socket 0" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 0 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 0 '0' Disable" "?,1: block pend status at Producer socket 0" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 0 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA27 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_prod0_buf_control,Controlling producer socket0 buffer for HWA27" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_prod0_count,Defining count values for pre/post load for generating pend by HWA27 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_pa0_control,control register to manage pattern adapter on HWA27 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_pa0_prodcount,count values for HWA27 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x4840++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_prod1_control,Controlling producer socket1 for HWA27" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 1 skip enable '0' Disable" "?,1: Producer socket 1 skip enable" newline bitfld.long 0x0 16. "DYNAMIC_TH_EN,'1' -> Dynamic Thresholding Enabled for Producer socket 1 '0' Disable Dynamic Thresholding" "?,1: Dynamic Thresholding Enabled for Producer socket 1" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 1 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 1 '0' Disable" "?,1: block pend status at Producer socket 1" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 1 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA27 prod socket 1. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 1 enable '0' Disable" "?,1: Producer socket 1 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_prod1_buf_control,Controlling producer socket1 buffer for HWA27" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_prod1_count,Defining count values for pre/post load for generating pend by HWA27 prod1" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_pa1_control,control register to manage pattern adapter on HWA27 prod socket1" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_pa1_prodcount,count values for HWA27 prod socket1" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x4860++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_prod2_control,Controlling producer socket2 for HWA27" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 2 skip enable '0' Disable" "?,1: Producer socket 2 skip enable" newline bitfld.long 0x0 16. "DYNAMIC_TH_EN,'1' -> Dynamic Thresholding Enabled for Producer socket 2 '0' Disable Dynamic Thresholding" "?,1: Dynamic Thresholding Enabled for Producer socket 2" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 2 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 2 '0' Disable" "?,1: block pend status at Producer socket 2" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 2 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA27 prod socket 2. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 2 enable '0' Disable" "?,1: Producer socket 2 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_prod2_buf_control,Controlling producer socket2 buffer for HWA27" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_prod2_count,Defining count values for pre/post load for generating pend by HWA27 prod2" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_pa2_control,control register to manage pattern adapter on HWA27 prod socket2" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_pa2_prodcount,count values for HWA27 prod socket2" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x4880++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_prod3_control,Controlling producer socket3 for HWA27" bitfld.long 0x0 17. "SKIP_PEND_EN,'1' -> Producer socket 3 skip enable '0' Disable" "?,1: Producer socket 3 skip enable" newline bitfld.long 0x0 15. "BLOCK_PEND_EN,'1' -> block pend at the end of hwa eop enabled at Producer socket 3 '0' Disable" "?,1: block pend at the end of hwa eop enabled at.." newline bitfld.long 0x0 14. "BLOCK_PEND_STATUS,'1' -> block pend status at Producer socket 3 '0' Disable" "?,1: block pend status at Producer socket 3" newline bitfld.long 0x0 11.--13. "BLOCK_PEND_CLRSELECT,hts_event_gen[block_pend_clrselect] will be used to clear blocked pend in super pipeline" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 10. "BLOCK_PEND_AUTOCLR_EN,'1' -> Enable clearing block pend status at Producer socket 3 by hts_event_gen[block_pend_clrselect] '0' Disable" "?,1: Enable clearing block pend status at Producer.." newline hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for HWA27 prod socket 3. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 3 enable '0' Disable" "?,1: Producer socket 3 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_prod3_buf_control,Controlling producer socket3 buffer for HWA27" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_prod3_count,Defining count values for pre/post load for generating pend by HWA27 prod3" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x4A20++0x1FF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold0,csmaxcount and count_dec value for Row No 0. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 0 when dynamic threshold feature is enabled" newline hexmask.long.word 0x0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 0 when dynamic threshold feature is enabled" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold1,csmaxcount and count_dec value for Row No 1. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 1 when dynamic threshold feature is enabled" newline hexmask.long.word 0x4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 1 when dynamic threshold feature is enabled" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold2,csmaxcount and count_dec value for Row No 2. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 2 when dynamic threshold feature is enabled" newline hexmask.long.word 0x8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 2 when dynamic threshold feature is enabled" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold3,csmaxcount and count_dec value for Row No 3. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 3 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 3 when dynamic threshold feature is enabled" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold4,csmaxcount and count_dec value for Row No 4. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x10 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 4 when dynamic threshold feature is enabled" newline hexmask.long.word 0x10 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 4 when dynamic threshold feature is enabled" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold5,csmaxcount and count_dec value for Row No 5. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x14 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 5 when dynamic threshold feature is enabled" newline hexmask.long.word 0x14 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 5 when dynamic threshold feature is enabled" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold6,csmaxcount and count_dec value for Row No 6. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x18 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 6 when dynamic threshold feature is enabled" newline hexmask.long.word 0x18 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 6 when dynamic threshold feature is enabled" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold7,csmaxcount and count_dec value for Row No 7. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 7 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 7 when dynamic threshold feature is enabled" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold8,csmaxcount and count_dec value for Row No 8. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x20 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 8 when dynamic threshold feature is enabled" newline hexmask.long.word 0x20 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 8 when dynamic threshold feature is enabled" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold9,csmaxcount and count_dec value for Row No 9. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x24 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 9 when dynamic threshold feature is enabled" newline hexmask.long.word 0x24 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 9 when dynamic threshold feature is enabled" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold10,csmaxcount and count_dec value for Row No 10. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x28 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 10 when dynamic threshold feature is enabled" newline hexmask.long.word 0x28 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 10 when dynamic threshold feature is enabled" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold11,csmaxcount and count_dec value for Row No 11. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x2C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 11 when dynamic threshold feature is enabled" newline hexmask.long.word 0x2C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 11 when dynamic threshold feature is enabled" line.long 0x30 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold12,csmaxcount and count_dec value for Row No 12. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x30 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 12 when dynamic threshold feature is enabled" newline hexmask.long.word 0x30 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 12 when dynamic threshold feature is enabled" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold13,csmaxcount and count_dec value for Row No 13. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x34 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 13 when dynamic threshold feature is enabled" newline hexmask.long.word 0x34 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 13 when dynamic threshold feature is enabled" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold14,csmaxcount and count_dec value for Row No 14. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x38 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 14 when dynamic threshold feature is enabled" newline hexmask.long.word 0x38 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 14 when dynamic threshold feature is enabled" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold15,csmaxcount and count_dec value for Row No 15. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x3C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 15 when dynamic threshold feature is enabled" newline hexmask.long.word 0x3C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 15 when dynamic threshold feature is enabled" line.long 0x40 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold16,csmaxcount and count_dec value for Row No 16. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x40 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 16 when dynamic threshold feature is enabled" newline hexmask.long.word 0x40 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 16 when dynamic threshold feature is enabled" line.long 0x44 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold17,csmaxcount and count_dec value for Row No 17. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x44 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 17 when dynamic threshold feature is enabled" newline hexmask.long.word 0x44 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 17 when dynamic threshold feature is enabled" line.long 0x48 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold18,csmaxcount and count_dec value for Row No 18. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x48 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 18 when dynamic threshold feature is enabled" newline hexmask.long.word 0x48 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 18 when dynamic threshold feature is enabled" line.long 0x4C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold19,csmaxcount and count_dec value for Row No 19. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x4C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 19 when dynamic threshold feature is enabled" newline hexmask.long.word 0x4C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 19 when dynamic threshold feature is enabled" line.long 0x50 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold20,csmaxcount and count_dec value for Row No 20. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x50 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 20 when dynamic threshold feature is enabled" newline hexmask.long.word 0x50 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 20 when dynamic threshold feature is enabled" line.long 0x54 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold21,csmaxcount and count_dec value for Row No 21. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x54 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 21 when dynamic threshold feature is enabled" newline hexmask.long.word 0x54 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 21 when dynamic threshold feature is enabled" line.long 0x58 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold22,csmaxcount and count_dec value for Row No 22. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x58 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 22 when dynamic threshold feature is enabled" newline hexmask.long.word 0x58 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 22 when dynamic threshold feature is enabled" line.long 0x5C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold23,csmaxcount and count_dec value for Row No 23. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x5C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 23 when dynamic threshold feature is enabled" newline hexmask.long.word 0x5C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 23 when dynamic threshold feature is enabled" line.long 0x60 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold24,csmaxcount and count_dec value for Row No 24. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x60 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 24 when dynamic threshold feature is enabled" newline hexmask.long.word 0x60 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 24 when dynamic threshold feature is enabled" line.long 0x64 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold25,csmaxcount and count_dec value for Row No 25. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x64 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 25 when dynamic threshold feature is enabled" newline hexmask.long.word 0x64 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 25 when dynamic threshold feature is enabled" line.long 0x68 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold26,csmaxcount and count_dec value for Row No 26. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x68 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 26 when dynamic threshold feature is enabled" newline hexmask.long.word 0x68 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 26 when dynamic threshold feature is enabled" line.long 0x6C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold27,csmaxcount and count_dec value for Row No 27. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x6C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 27 when dynamic threshold feature is enabled" newline hexmask.long.word 0x6C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 27 when dynamic threshold feature is enabled" line.long 0x70 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold28,csmaxcount and count_dec value for Row No 28. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x70 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 28 when dynamic threshold feature is enabled" newline hexmask.long.word 0x70 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 28 when dynamic threshold feature is enabled" line.long 0x74 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold29,csmaxcount and count_dec value for Row No 29. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x74 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 29 when dynamic threshold feature is enabled" newline hexmask.long.word 0x74 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 29 when dynamic threshold feature is enabled" line.long 0x78 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold30,csmaxcount and count_dec value for Row No 30. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x78 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 30 when dynamic threshold feature is enabled" newline hexmask.long.word 0x78 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 30 when dynamic threshold feature is enabled" line.long 0x7C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold31,csmaxcount and count_dec value for Row No 31. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x7C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 31 when dynamic threshold feature is enabled" newline hexmask.long.word 0x7C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 31 when dynamic threshold feature is enabled" line.long 0x80 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold32,csmaxcount and count_dec value for Row No 32. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x80 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 32 when dynamic threshold feature is enabled" newline hexmask.long.word 0x80 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 32 when dynamic threshold feature is enabled" line.long 0x84 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold33,csmaxcount and count_dec value for Row No 33. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x84 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 33 when dynamic threshold feature is enabled" newline hexmask.long.word 0x84 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 33 when dynamic threshold feature is enabled" line.long 0x88 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold34,csmaxcount and count_dec value for Row No 34. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x88 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 34 when dynamic threshold feature is enabled" newline hexmask.long.word 0x88 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 34 when dynamic threshold feature is enabled" line.long 0x8C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold35,csmaxcount and count_dec value for Row No 35. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x8C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 35 when dynamic threshold feature is enabled" newline hexmask.long.word 0x8C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 35 when dynamic threshold feature is enabled" line.long 0x90 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold36,csmaxcount and count_dec value for Row No 36. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x90 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 36 when dynamic threshold feature is enabled" newline hexmask.long.word 0x90 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 36 when dynamic threshold feature is enabled" line.long 0x94 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold37,csmaxcount and count_dec value for Row No 37. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x94 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 37 when dynamic threshold feature is enabled" newline hexmask.long.word 0x94 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 37 when dynamic threshold feature is enabled" line.long 0x98 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold38,csmaxcount and count_dec value for Row No 38. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x98 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 38 when dynamic threshold feature is enabled" newline hexmask.long.word 0x98 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 38 when dynamic threshold feature is enabled" line.long 0x9C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold39,csmaxcount and count_dec value for Row No 39. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x9C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 39 when dynamic threshold feature is enabled" newline hexmask.long.word 0x9C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 39 when dynamic threshold feature is enabled" line.long 0xA0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold40,csmaxcount and count_dec value for Row No 40. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xA0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 40 when dynamic threshold feature is enabled" newline hexmask.long.word 0xA0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 40 when dynamic threshold feature is enabled" line.long 0xA4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold41,csmaxcount and count_dec value for Row No 41. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xA4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 41 when dynamic threshold feature is enabled" newline hexmask.long.word 0xA4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 41 when dynamic threshold feature is enabled" line.long 0xA8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold42,csmaxcount and count_dec value for Row No 42. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xA8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 42 when dynamic threshold feature is enabled" newline hexmask.long.word 0xA8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 42 when dynamic threshold feature is enabled" line.long 0xAC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold43,csmaxcount and count_dec value for Row No 43. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xAC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 43 when dynamic threshold feature is enabled" newline hexmask.long.word 0xAC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 43 when dynamic threshold feature is enabled" line.long 0xB0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold44,csmaxcount and count_dec value for Row No 44. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xB0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 44 when dynamic threshold feature is enabled" newline hexmask.long.word 0xB0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 44 when dynamic threshold feature is enabled" line.long 0xB4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold45,csmaxcount and count_dec value for Row No 45. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xB4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 45 when dynamic threshold feature is enabled" newline hexmask.long.word 0xB4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 45 when dynamic threshold feature is enabled" line.long 0xB8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold46,csmaxcount and count_dec value for Row No 46. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xB8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 46 when dynamic threshold feature is enabled" newline hexmask.long.word 0xB8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 46 when dynamic threshold feature is enabled" line.long 0xBC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold47,csmaxcount and count_dec value for Row No 47. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xBC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 47 when dynamic threshold feature is enabled" newline hexmask.long.word 0xBC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 47 when dynamic threshold feature is enabled" line.long 0xC0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold48,csmaxcount and count_dec value for Row No 48. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 48 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 48 when dynamic threshold feature is enabled" line.long 0xC4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold49,csmaxcount and count_dec value for Row No 49. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 49 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 49 when dynamic threshold feature is enabled" line.long 0xC8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold50,csmaxcount and count_dec value for Row No 50. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xC8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 50 when dynamic threshold feature is enabled" newline hexmask.long.word 0xC8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 50 when dynamic threshold feature is enabled" line.long 0xCC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold51,csmaxcount and count_dec value for Row No 51. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xCC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 51 when dynamic threshold feature is enabled" newline hexmask.long.word 0xCC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 51 when dynamic threshold feature is enabled" line.long 0xD0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold52,csmaxcount and count_dec value for Row No 52. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xD0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 52 when dynamic threshold feature is enabled" newline hexmask.long.word 0xD0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 52 when dynamic threshold feature is enabled" line.long 0xD4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold53,csmaxcount and count_dec value for Row No 53. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xD4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 53 when dynamic threshold feature is enabled" newline hexmask.long.word 0xD4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 53 when dynamic threshold feature is enabled" line.long 0xD8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold54,csmaxcount and count_dec value for Row No 54. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xD8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 54 when dynamic threshold feature is enabled" newline hexmask.long.word 0xD8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 54 when dynamic threshold feature is enabled" line.long 0xDC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold55,csmaxcount and count_dec value for Row No 55. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xDC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 55 when dynamic threshold feature is enabled" newline hexmask.long.word 0xDC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 55 when dynamic threshold feature is enabled" line.long 0xE0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold56,csmaxcount and count_dec value for Row No 56. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xE0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 56 when dynamic threshold feature is enabled" newline hexmask.long.word 0xE0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 56 when dynamic threshold feature is enabled" line.long 0xE4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold57,csmaxcount and count_dec value for Row No 57. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xE4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 57 when dynamic threshold feature is enabled" newline hexmask.long.word 0xE4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 57 when dynamic threshold feature is enabled" line.long 0xE8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold58,csmaxcount and count_dec value for Row No 58. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xE8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 58 when dynamic threshold feature is enabled" newline hexmask.long.word 0xE8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 58 when dynamic threshold feature is enabled" line.long 0xEC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold59,csmaxcount and count_dec value for Row No 59. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xEC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 59 when dynamic threshold feature is enabled" newline hexmask.long.word 0xEC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 59 when dynamic threshold feature is enabled" line.long 0xF0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold60,csmaxcount and count_dec value for Row No 60. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xF0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 60 when dynamic threshold feature is enabled" newline hexmask.long.word 0xF0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 60 when dynamic threshold feature is enabled" line.long 0xF4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold61,csmaxcount and count_dec value for Row No 61. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xF4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 61 when dynamic threshold feature is enabled" newline hexmask.long.word 0xF4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 61 when dynamic threshold feature is enabled" line.long 0xF8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold62,csmaxcount and count_dec value for Row No 62. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xF8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 62 when dynamic threshold feature is enabled" newline hexmask.long.word 0xF8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 62 when dynamic threshold feature is enabled" line.long 0xFC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold63,csmaxcount and count_dec value for Row No 63. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0xFC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 63 when dynamic threshold feature is enabled" newline hexmask.long.word 0xFC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 63 when dynamic threshold feature is enabled" line.long 0x100 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold64,csmaxcount and count_dec value for Row No 64. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x100 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 64 when dynamic threshold feature is enabled" newline hexmask.long.word 0x100 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 64 when dynamic threshold feature is enabled" line.long 0x104 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold65,csmaxcount and count_dec value for Row No 65. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x104 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 65 when dynamic threshold feature is enabled" newline hexmask.long.word 0x104 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 65 when dynamic threshold feature is enabled" line.long 0x108 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold66,csmaxcount and count_dec value for Row No 66. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x108 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 66 when dynamic threshold feature is enabled" newline hexmask.long.word 0x108 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 66 when dynamic threshold feature is enabled" line.long 0x10C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold67,csmaxcount and count_dec value for Row No 67. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x10C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 67 when dynamic threshold feature is enabled" newline hexmask.long.word 0x10C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 67 when dynamic threshold feature is enabled" line.long 0x110 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold68,csmaxcount and count_dec value for Row No 68. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x110 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 68 when dynamic threshold feature is enabled" newline hexmask.long.word 0x110 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 68 when dynamic threshold feature is enabled" line.long 0x114 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold69,csmaxcount and count_dec value for Row No 69. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x114 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 69 when dynamic threshold feature is enabled" newline hexmask.long.word 0x114 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 69 when dynamic threshold feature is enabled" line.long 0x118 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold70,csmaxcount and count_dec value for Row No 70. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x118 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 70 when dynamic threshold feature is enabled" newline hexmask.long.word 0x118 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 70 when dynamic threshold feature is enabled" line.long 0x11C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold71,csmaxcount and count_dec value for Row No 71. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x11C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 71 when dynamic threshold feature is enabled" newline hexmask.long.word 0x11C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 71 when dynamic threshold feature is enabled" line.long 0x120 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold72,csmaxcount and count_dec value for Row No 72. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x120 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 72 when dynamic threshold feature is enabled" newline hexmask.long.word 0x120 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 72 when dynamic threshold feature is enabled" line.long 0x124 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold73,csmaxcount and count_dec value for Row No 73. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x124 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 73 when dynamic threshold feature is enabled" newline hexmask.long.word 0x124 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 73 when dynamic threshold feature is enabled" line.long 0x128 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold74,csmaxcount and count_dec value for Row No 74. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x128 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 74 when dynamic threshold feature is enabled" newline hexmask.long.word 0x128 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 74 when dynamic threshold feature is enabled" line.long 0x12C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold75,csmaxcount and count_dec value for Row No 75. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x12C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 75 when dynamic threshold feature is enabled" newline hexmask.long.word 0x12C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 75 when dynamic threshold feature is enabled" line.long 0x130 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold76,csmaxcount and count_dec value for Row No 76. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x130 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 76 when dynamic threshold feature is enabled" newline hexmask.long.word 0x130 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 76 when dynamic threshold feature is enabled" line.long 0x134 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold77,csmaxcount and count_dec value for Row No 77. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x134 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 77 when dynamic threshold feature is enabled" newline hexmask.long.word 0x134 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 77 when dynamic threshold feature is enabled" line.long 0x138 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold78,csmaxcount and count_dec value for Row No 78. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x138 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 78 when dynamic threshold feature is enabled" newline hexmask.long.word 0x138 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 78 when dynamic threshold feature is enabled" line.long 0x13C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold79,csmaxcount and count_dec value for Row No 79. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x13C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 79 when dynamic threshold feature is enabled" newline hexmask.long.word 0x13C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 79 when dynamic threshold feature is enabled" line.long 0x140 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold80,csmaxcount and count_dec value for Row No 80. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x140 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 80 when dynamic threshold feature is enabled" newline hexmask.long.word 0x140 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 80 when dynamic threshold feature is enabled" line.long 0x144 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold81,csmaxcount and count_dec value for Row No 81. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x144 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 81 when dynamic threshold feature is enabled" newline hexmask.long.word 0x144 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 81 when dynamic threshold feature is enabled" line.long 0x148 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold82,csmaxcount and count_dec value for Row No 82. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x148 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 82 when dynamic threshold feature is enabled" newline hexmask.long.word 0x148 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 82 when dynamic threshold feature is enabled" line.long 0x14C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold83,csmaxcount and count_dec value for Row No 83. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x14C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 83 when dynamic threshold feature is enabled" newline hexmask.long.word 0x14C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 83 when dynamic threshold feature is enabled" line.long 0x150 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold84,csmaxcount and count_dec value for Row No 84. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x150 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 84 when dynamic threshold feature is enabled" newline hexmask.long.word 0x150 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 84 when dynamic threshold feature is enabled" line.long 0x154 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold85,csmaxcount and count_dec value for Row No 85. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x154 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 85 when dynamic threshold feature is enabled" newline hexmask.long.word 0x154 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 85 when dynamic threshold feature is enabled" line.long 0x158 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold86,csmaxcount and count_dec value for Row No 86. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x158 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 86 when dynamic threshold feature is enabled" newline hexmask.long.word 0x158 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 86 when dynamic threshold feature is enabled" line.long 0x15C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold87,csmaxcount and count_dec value for Row No 87. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x15C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 87 when dynamic threshold feature is enabled" newline hexmask.long.word 0x15C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 87 when dynamic threshold feature is enabled" line.long 0x160 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold88,csmaxcount and count_dec value for Row No 88. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x160 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 88 when dynamic threshold feature is enabled" newline hexmask.long.word 0x160 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 88 when dynamic threshold feature is enabled" line.long 0x164 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold89,csmaxcount and count_dec value for Row No 89. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x164 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 89 when dynamic threshold feature is enabled" newline hexmask.long.word 0x164 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 89 when dynamic threshold feature is enabled" line.long 0x168 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold90,csmaxcount and count_dec value for Row No 90. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x168 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 90 when dynamic threshold feature is enabled" newline hexmask.long.word 0x168 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 90 when dynamic threshold feature is enabled" line.long 0x16C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold91,csmaxcount and count_dec value for Row No 91. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x16C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 91 when dynamic threshold feature is enabled" newline hexmask.long.word 0x16C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 91 when dynamic threshold feature is enabled" line.long 0x170 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold92,csmaxcount and count_dec value for Row No 92. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x170 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 92 when dynamic threshold feature is enabled" newline hexmask.long.word 0x170 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 92 when dynamic threshold feature is enabled" line.long 0x174 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold93,csmaxcount and count_dec value for Row No 93. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x174 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 93 when dynamic threshold feature is enabled" newline hexmask.long.word 0x174 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 93 when dynamic threshold feature is enabled" line.long 0x178 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold94,csmaxcount and count_dec value for Row No 94. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x178 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 94 when dynamic threshold feature is enabled" newline hexmask.long.word 0x178 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 94 when dynamic threshold feature is enabled" line.long 0x17C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold95,csmaxcount and count_dec value for Row No 95. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x17C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 95 when dynamic threshold feature is enabled" newline hexmask.long.word 0x17C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 95 when dynamic threshold feature is enabled" line.long 0x180 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold96,csmaxcount and count_dec value for Row No 96. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x180 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 96 when dynamic threshold feature is enabled" newline hexmask.long.word 0x180 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 96 when dynamic threshold feature is enabled" line.long 0x184 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold97,csmaxcount and count_dec value for Row No 97. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x184 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 97 when dynamic threshold feature is enabled" newline hexmask.long.word 0x184 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 97 when dynamic threshold feature is enabled" line.long 0x188 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold98,csmaxcount and count_dec value for Row No 98. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x188 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 98 when dynamic threshold feature is enabled" newline hexmask.long.word 0x188 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 98 when dynamic threshold feature is enabled" line.long 0x18C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold99,csmaxcount and count_dec value for Row No 99. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x18C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 99 when dynamic threshold feature is enabled" newline hexmask.long.word 0x18C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 99 when dynamic threshold feature is enabled" line.long 0x190 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold100,csmaxcount and count_dec value for Row No 100. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x190 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 100 when dynamic threshold feature is enabled" newline hexmask.long.word 0x190 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 100 when dynamic threshold feature is enabled" line.long 0x194 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold101,csmaxcount and count_dec value for Row No 101. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x194 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 101 when dynamic threshold feature is enabled" newline hexmask.long.word 0x194 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 101 when dynamic threshold feature is enabled" line.long 0x198 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold102,csmaxcount and count_dec value for Row No 102. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x198 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 102 when dynamic threshold feature is enabled" newline hexmask.long.word 0x198 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 102 when dynamic threshold feature is enabled" line.long 0x19C "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold103,csmaxcount and count_dec value for Row No 103. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x19C 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 103 when dynamic threshold feature is enabled" newline hexmask.long.word 0x19C 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 103 when dynamic threshold feature is enabled" line.long 0x1A0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold104,csmaxcount and count_dec value for Row No 104. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1A0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 104 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1A0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 104 when dynamic threshold feature is enabled" line.long 0x1A4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold105,csmaxcount and count_dec value for Row No 105. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1A4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 105 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1A4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 105 when dynamic threshold feature is enabled" line.long 0x1A8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold106,csmaxcount and count_dec value for Row No 106. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1A8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 106 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1A8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 106 when dynamic threshold feature is enabled" line.long 0x1AC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold107,csmaxcount and count_dec value for Row No 107. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1AC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 107 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1AC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 107 when dynamic threshold feature is enabled" line.long 0x1B0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold108,csmaxcount and count_dec value for Row No 108. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1B0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 108 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1B0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 108 when dynamic threshold feature is enabled" line.long 0x1B4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold109,csmaxcount and count_dec value for Row No 109. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1B4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 109 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1B4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 109 when dynamic threshold feature is enabled" line.long 0x1B8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold110,csmaxcount and count_dec value for Row No 110. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1B8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 110 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1B8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 110 when dynamic threshold feature is enabled" line.long 0x1BC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold111,csmaxcount and count_dec value for Row No 111. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1BC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 111 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1BC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 111 when dynamic threshold feature is enabled" line.long 0x1C0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold112,csmaxcount and count_dec value for Row No 112. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 112 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 112 when dynamic threshold feature is enabled" line.long 0x1C4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold113,csmaxcount and count_dec value for Row No 113. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 113 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 113 when dynamic threshold feature is enabled" line.long 0x1C8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold114,csmaxcount and count_dec value for Row No 114. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1C8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 114 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1C8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 114 when dynamic threshold feature is enabled" line.long 0x1CC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold115,csmaxcount and count_dec value for Row No 115. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1CC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 115 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1CC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 115 when dynamic threshold feature is enabled" line.long 0x1D0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold116,csmaxcount and count_dec value for Row No 116. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1D0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 116 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1D0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 116 when dynamic threshold feature is enabled" line.long 0x1D4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold117,csmaxcount and count_dec value for Row No 117. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1D4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 117 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1D4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 117 when dynamic threshold feature is enabled" line.long 0x1D8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold118,csmaxcount and count_dec value for Row No 118. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1D8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 118 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1D8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 118 when dynamic threshold feature is enabled" line.long 0x1DC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold119,csmaxcount and count_dec value for Row No 119. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1DC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 119 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1DC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 119 when dynamic threshold feature is enabled" line.long 0x1E0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold120,csmaxcount and count_dec value for Row No 120. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1E0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 120 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1E0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 120 when dynamic threshold feature is enabled" line.long 0x1E4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold121,csmaxcount and count_dec value for Row No 121. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1E4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 121 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1E4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 121 when dynamic threshold feature is enabled" line.long 0x1E8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold122,csmaxcount and count_dec value for Row No 122. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1E8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 122 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1E8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 122 when dynamic threshold feature is enabled" line.long 0x1EC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold123,csmaxcount and count_dec value for Row No 123. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1EC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 123 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1EC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 123 when dynamic threshold feature is enabled" line.long 0x1F0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold124,csmaxcount and count_dec value for Row No 124. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1F0 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 124 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1F0 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 124 when dynamic threshold feature is enabled" line.long 0x1F4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold125,csmaxcount and count_dec value for Row No 125. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1F4 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 125 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1F4 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 125 when dynamic threshold feature is enabled" line.long 0x1F8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold126,csmaxcount and count_dec value for Row No 126. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1F8 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 126 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1F8 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 126 when dynamic threshold feature is enabled" line.long 0x1FC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_HWA27_dynamic_threshold127,csmaxcount and count_dec value for Row No 127. Only used alongwith Pattern Adapter feature. i.e. PA need to be enabled for this feature" hexmask.long.byte 0x1FC 16.--23. 1. "DYN_COUNT_DEC,Prod count dec after pattern adaptation of Row No 127 when dynamic threshold feature is enabled" newline hexmask.long.word 0x1FC 0.--9. 1. "DYN_CS_MAXCOUNT,Source count for pattern adaptation of Row No 127 when dynamic threshold feature is enabled" group.long 0x5740++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA0_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA0" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA0 Scheduler resources must not be read during halted state. '1'-> DMA0 Scheduler resources are readable during halted state" "0: DMA0 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA0 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA0 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA0_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x5760++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA0_prod0_control,Controlling producer socket0 for DMA0" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA0 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA0_prod0_buf_control,Controlling producer socket0 buffer for DMA0" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA0_prod0_count,Defining count values for pre/post load for generating pend by DMA0 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x5780++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA1_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA1" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA1 Scheduler resources must not be read during halted state. '1'-> DMA1 Scheduler resources are readable during halted state" "0: DMA1 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA1 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA1 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA1_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x57A0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA1_prod0_control,Controlling producer socket0 for DMA1" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA1 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA1_prod0_buf_control,Controlling producer socket0 buffer for DMA1" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA1_prod0_count,Defining count values for pre/post load for generating pend by DMA1 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x57C0++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA2_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA2" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA2 Scheduler resources must not be read during halted state. '1'-> DMA2 Scheduler resources are readable during halted state" "0: DMA2 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA2 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA2 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA2_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x57E0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA2_prod0_control,Controlling producer socket0 for DMA2" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA2 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA2_prod0_buf_control,Controlling producer socket0 buffer for DMA2" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA2_prod0_count,Defining count values for pre/post load for generating pend by DMA2 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x5800++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA3_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA3" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA3 Scheduler resources must not be read during halted state. '1'-> DMA3 Scheduler resources are readable during halted state" "0: DMA3 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA3 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA3 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA3_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x5820++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA3_prod0_control,Controlling producer socket0 for DMA3" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA3 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA3_prod0_buf_control,Controlling producer socket0 buffer for DMA3" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA3_prod0_count,Defining count values for pre/post load for generating pend by DMA3 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x5840++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA4_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA4" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA4 Scheduler resources must not be read during halted state. '1'-> DMA4 Scheduler resources are readable during halted state" "0: DMA4 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA4 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA4 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA4_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x5860++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA4_prod0_control,Controlling producer socket0 for DMA4" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA4 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA4_prod0_buf_control,Controlling producer socket0 buffer for DMA4" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA4_prod0_count,Defining count values for pre/post load for generating pend by DMA4 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x5940++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA8_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA8" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA8 Scheduler resources must not be read during halted state. '1'-> DMA8 Scheduler resources are readable during halted state" "0: DMA8 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA8 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA8 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA8_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x5960++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA8_prod0_control,Controlling producer socket0 for DMA8" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA8 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA8_prod0_buf_control,Controlling producer socket0 buffer for DMA8" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA8_prod0_count,Defining count values for pre/post load for generating pend by DMA8 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA8_pa0_control,control register to manage pattern adapter on DMA8 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA8_pa0_prodcount,count values for HWA8 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x5980++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA9_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA9" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA9 Scheduler resources must not be read during halted state. '1'-> DMA9 Scheduler resources are readable during halted state" "0: DMA9 Scheduler resources must not be read during..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA9 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA9 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA9_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x59A0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA9_prod0_control,Controlling producer socket0 for DMA9" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA9 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA9_prod0_buf_control,Controlling producer socket0 buffer for DMA9" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA9_prod0_count,Defining count values for pre/post load for generating pend by DMA9 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA9_pa0_control,control register to manage pattern adapter on DMA9 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA9_pa0_prodcount,count values for HWA9 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x59C0++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA10_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA10" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA10 Scheduler resources must not be read during halted state. '1'-> DMA10 Scheduler resources are readable during halted state" "0: DMA10 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA10 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA10 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA10_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x59E0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA10_prod0_control,Controlling producer socket0 for DMA10" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA10 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA10_prod0_buf_control,Controlling producer socket0 buffer for DMA10" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA10_prod0_count,Defining count values for pre/post load for generating pend by DMA10 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA10_pa0_control,control register to manage pattern adapter on DMA10 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA10_pa0_prodcount,count values for HWA10 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x5F40++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA32_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA32" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA32 Scheduler resources must not be read during halted state. '1'-> DMA32 Scheduler resources are readable during halted state" "0: DMA32 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA32 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA32 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA32_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x5F60++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA32_prod0_control,Controlling producer socket0 for DMA32" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA32 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA32_prod0_buf_control,Controlling producer socket0 buffer for DMA32" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA32_prod0_count,Defining count values for pre/post load for generating pend by DMA32 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA32_pa0_control,control register to manage pattern adapter on DMA32 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA32_pa0_prodcount,count values for HWA32 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x5F80++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA33_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA33" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA33 Scheduler resources must not be read during halted state. '1'-> DMA33 Scheduler resources are readable during halted state" "0: DMA33 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA33 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA33 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA33_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x5FA0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA33_prod0_control,Controlling producer socket0 for DMA33" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA33 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA33_prod0_buf_control,Controlling producer socket0 buffer for DMA33" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA33_prod0_count,Defining count values for pre/post load for generating pend by DMA33 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA33_pa0_control,control register to manage pattern adapter on DMA33 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA33_pa0_prodcount,count values for HWA33 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x6140++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA40_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA40" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA40 Scheduler resources must not be read during halted state. '1'-> DMA40 Scheduler resources are readable during halted state" "0: DMA40 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA40 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA40 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA40_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x6160++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA40_prod0_control,Controlling producer socket0 for DMA40" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA40 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA40_prod0_buf_control,Controlling producer socket0 buffer for DMA40" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA40_prod0_count,Defining count values for pre/post load for generating pend by DMA40 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA40_pa0_control,control register to manage pattern adapter on DMA40 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA40_pa0_prodcount,count values for HWA40 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x6180++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA41_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA41" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA41 Scheduler resources must not be read during halted state. '1'-> DMA41 Scheduler resources are readable during halted state" "0: DMA41 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA41 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA41 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA41_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x61A0++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA41_prod0_control,Controlling producer socket0 for DMA41" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA41 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA41_prod0_buf_control,Controlling producer socket0 buffer for DMA41" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA41_prod0_count,Defining count values for pre/post load for generating pend by DMA41 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" line.long 0xC "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA41_pa0_control,control register to manage pattern adapter on DMA41 prod socket0" hexmask.long.word 0xC 13.--22. 1. "PA_PS_MAXCOUNT,destination count for pattern adaptation (N) M --> N" newline hexmask.long.word 0xC 3.--12. 1. "PA_CS_MAXCOUNT,source count for pattern adaptation (M) M --> N" newline bitfld.long 0xC 2. "PA_BUF_CNTL,'1' -> Apply threshold count_preload and count_postload on pattern adapter count (use this only when pa_enable='1') '0' -> Apply threshold count_preload and count_postload on prod count (same behavior as if no pattern adapter. Note when.." "0: Apply threshold,1: Apply threshold" newline bitfld.long 0xC 1. "PA_DEC_CNTL,'1' -> post pattern adaptation decrement ps count by count_dec '0' -> post pattern adaptation decrement ps count by pa_cs_maxcount" "0: post pattern adaptation,1: post pattern adaptation" newline bitfld.long 0xC 0. "PA_ENABLE,'1' -> pa enable '0' -> disable" "0: disable,1: pa enable" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA41_pa0_prodcount,count values for HWA41 prod socket0" hexmask.long.word 0x10 6.--15. 1. "PA_PSCOUNT,current count value of pa prod count" newline hexmask.long.byte 0x10 0.--5. 1. "PA_COUNT_DEC,Decrement count value of pa_prod_count after pattern adapter prod count reaches threshold" group.long 0x6340++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA48_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA48" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA48 Scheduler resources must not be read during halted state. '1'-> DMA48 Scheduler resources are readable during halted state" "0: DMA48 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA48 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA48 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA48_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x6360++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA48_prod0_control,Controlling producer socket0 for DMA48" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA48 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA48_prod0_buf_control,Controlling producer socket0 buffer for DMA48" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA48_prod0_count,Defining count values for pre/post load for generating pend by DMA48 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x6540++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA56_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA56" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA56 Scheduler resources must not be read during halted state. '1'-> DMA56 Scheduler resources are readable during halted state" "0: DMA56 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA56 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA56 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA56_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x6560++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA56_prod0_control,Controlling producer socket0 for DMA56" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA56 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA56_prod0_buf_control,Controlling producer socket0 buffer for DMA56" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA56_prod0_count,Defining count values for pre/post load for generating pend by DMA56 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x6580++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA57_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA57" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA57 Scheduler resources must not be read during halted state. '1'-> DMA57 Scheduler resources are readable during halted state" "0: DMA57 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA57 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA57 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA57_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x65A0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA57_prod0_control,Controlling producer socket0 for DMA57" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA57 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA57_prod0_buf_control,Controlling producer socket0 buffer for DMA57" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA57_prod0_count,Defining count values for pre/post load for generating pend by DMA57 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x65C0++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA58_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA58" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA58 Scheduler resources must not be read during halted state. '1'-> DMA58 Scheduler resources are readable during halted state" "0: DMA58 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA58 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA58 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA58_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x65E0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA58_prod0_control,Controlling producer socket0 for DMA58" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA58 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA58_prod0_buf_control,Controlling producer socket0 buffer for DMA58" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA58_prod0_count,Defining count values for pre/post load for generating pend by DMA58 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x6600++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA59_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA59" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA59 Scheduler resources must not be read during halted state. '1'-> DMA59 Scheduler resources are readable during halted state" "0: DMA59 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA59 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA59 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA59_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x6620++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA59_prod0_control,Controlling producer socket0 for DMA59" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA59 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA59_prod0_buf_control,Controlling producer socket0 buffer for DMA59" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA59_prod0_count,Defining count values for pre/post load for generating pend by DMA59 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x6740++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA64_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA64" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA64 Scheduler resources must not be read during halted state. '1'-> DMA64 Scheduler resources are readable during halted state" "0: DMA64 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA64 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA64 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA64_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x6760++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA64_prod0_control,Controlling producer socket0 for DMA64" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA64 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA64_prod0_buf_control,Controlling producer socket0 buffer for DMA64" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA64_prod0_count,Defining count values for pre/post load for generating pend by DMA64 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x6780++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA65_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA65" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA65 Scheduler resources must not be read during halted state. '1'-> DMA65 Scheduler resources are readable during halted state" "0: DMA65 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA65 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA65 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA65_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x67A0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA65_prod0_control,Controlling producer socket0 for DMA65" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA65 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA65_prod0_buf_control,Controlling producer socket0 buffer for DMA65" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA65_prod0_count,Defining count values for pre/post load for generating pend by DMA65 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x67C0++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA66_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA66" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA66 Scheduler resources must not be read during halted state. '1'-> DMA66 Scheduler resources are readable during halted state" "0: DMA66 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA66 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA66 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA66_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x67E0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA66_prod0_control,Controlling producer socket0 for DMA66" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA66 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA66_prod0_buf_control,Controlling producer socket0 buffer for DMA66" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA66_prod0_count,Defining count values for pre/post load for generating pend by DMA66 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x6800++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA67_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA67" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA67 Scheduler resources must not be read during halted state. '1'-> DMA67 Scheduler resources are readable during halted state" "0: DMA67 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA67 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA67 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA67_HOP,Scheduler HOP Control Register. Help in detecting eop within scheduler. Once configured. it counts task/channel starts and stops issuing further starts. Specifically useful for Head of pipe dma scheduler ." hexmask.long.word 0x4 17.--29. 1. "TDONE_COUNT,current tdone count value" newline bitfld.long 0x4 16. "TDONE_COUNT_EN,'1' -> Count tdone(Not impacted due to individual channel mask). Current tdone count available as read value '0' -> No count" "0: No count,1: Count tdone" newline hexmask.long.word 0x4 1.--13. 1. "HOP_THREAD_COUNT,Number of Task count for Head of pipe" newline bitfld.long 0x4 0. "HOP,'1' -> Head of Pipe producer Sch '0' -> No hop" "0: No hop,1: Head of Pipe producer Sch" group.long 0x6820++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA67_prod0_control,Controlling producer socket0 for DMA67" hexmask.long.byte 0x0 1.--8. 1. "CONS_SELECT,consumer select for DMA67 prod socket 0. Used in decrementing count of producer buffer" newline bitfld.long 0x0 0. "PROD_EN,'1' -> Producer socket 0 enable '0' Disable" "?,1: Producer socket 0 enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA67_prod0_buf_control,Controlling producer socket0 buffer for DMA67" hexmask.long.byte 0x4 23.--30. 1. "COUNT_DEC,Count decrement value for prod count" newline hexmask.long.word 0x4 13.--22. 1. "THRESHOLD,Count threshold to generate pend for consumer" newline hexmask.long.word 0x4 0.--12. 1. "DEPTH,Maximum number of producer buffer count" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA67_prod0_count,Defining count values for pre/post load for generating pend by DMA67 prod0" hexmask.long.word 0x8 19.--31. 1. "COUNT,current count value" newline hexmask.long.word 0x8 10.--18. 1. "COUNT_POSTLOAD,count postload after producer max thread count reached" newline hexmask.long.word 0x8 0.--8. 1. "COUNT_PRELOAD,count preload after scheduler start/init" group.long 0x9340++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA240_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA240" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA240 Scheduler resources must not be read during halted state. '1'-> DMA240 Scheduler resources are readable during halted state" "0: DMA240 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA240 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA240 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9360++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA240_cons0_control,Controlling consumer socket 0 for DMA240" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA240 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9368++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA241_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA241" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA241 Scheduler resources must not be read during halted state. '1'-> DMA241 Scheduler resources are readable during halted state" "0: DMA241 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA241 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA241 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9388++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA241_cons0_control,Controlling consumer socket 0 for DMA241" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA241 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9390++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA242_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA242" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA242 Scheduler resources must not be read during halted state. '1'-> DMA242 Scheduler resources are readable during halted state" "0: DMA242 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA242 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA242 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x93B0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA242_cons0_control,Controlling consumer socket 0 for DMA242" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA242 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x93B8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA243_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA243" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA243 Scheduler resources must not be read during halted state. '1'-> DMA243 Scheduler resources are readable during halted state" "0: DMA243 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA243 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA243 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x93D8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA243_cons0_control,Controlling consumer socket 0 for DMA243" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA243 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x93E0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA244_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA244" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA244 Scheduler resources must not be read during halted state. '1'-> DMA244 Scheduler resources are readable during halted state" "0: DMA244 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA244 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA244 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9400++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA244_cons0_control,Controlling consumer socket 0 for DMA244" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA244 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9408++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA245_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA245" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA245 Scheduler resources must not be read during halted state. '1'-> DMA245 Scheduler resources are readable during halted state" "0: DMA245 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA245 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA245 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9428++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA245_cons0_control,Controlling consumer socket 0 for DMA245" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA245 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x95C0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA256_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA256" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA256 Scheduler resources must not be read during halted state. '1'-> DMA256 Scheduler resources are readable during halted state" "0: DMA256 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA256 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA256 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x95E0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA256_cons0_control,Controlling consumer socket 0 for DMA256" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA256 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x95E8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA257_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA257" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA257 Scheduler resources must not be read during halted state. '1'-> DMA257 Scheduler resources are readable during halted state" "0: DMA257 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA257 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA257 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9608++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA257_cons0_control,Controlling consumer socket 0 for DMA257" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA257 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9610++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA258_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA258" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA258 Scheduler resources must not be read during halted state. '1'-> DMA258 Scheduler resources are readable during halted state" "0: DMA258 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA258 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA258 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9630++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA258_cons0_control,Controlling consumer socket 0 for DMA258" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA258 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9638++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA259_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA259" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA259 Scheduler resources must not be read during halted state. '1'-> DMA259 Scheduler resources are readable during halted state" "0: DMA259 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA259 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA259 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9658++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA259_cons0_control,Controlling consumer socket 0 for DMA259" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA259 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9660++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA260_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA260" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA260 Scheduler resources must not be read during halted state. '1'-> DMA260 Scheduler resources are readable during halted state" "0: DMA260 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA260 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA260 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9680++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA260_cons0_control,Controlling consumer socket 0 for DMA260" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA260 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9688++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA261_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA261" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA261 Scheduler resources must not be read during halted state. '1'-> DMA261 Scheduler resources are readable during halted state" "0: DMA261 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA261 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA261 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x96A8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA261_cons0_control,Controlling consumer socket 0 for DMA261" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA261 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9840++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA272_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA272" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA272 Scheduler resources must not be read during halted state. '1'-> DMA272 Scheduler resources are readable during halted state" "0: DMA272 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA272 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA272 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9860++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA272_cons0_control,Controlling consumer socket 0 for DMA272" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA272 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9868++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA273_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA273" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA273 Scheduler resources must not be read during halted state. '1'-> DMA273 Scheduler resources are readable during halted state" "0: DMA273 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA273 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA273 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9888++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA273_cons0_control,Controlling consumer socket 0 for DMA273" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA273 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9890++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA274_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA274" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA274 Scheduler resources must not be read during halted state. '1'-> DMA274 Scheduler resources are readable during halted state" "0: DMA274 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA274 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA274 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x98B0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA274_cons0_control,Controlling consumer socket 0 for DMA274" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA274 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x98B8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA275_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA275" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA275 Scheduler resources must not be read during halted state. '1'-> DMA275 Scheduler resources are readable during halted state" "0: DMA275 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA275 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA275 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x98D8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA275_cons0_control,Controlling consumer socket 0 for DMA275" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA275 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9AC0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA288_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA288" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA288 Scheduler resources must not be read during halted state. '1'-> DMA288 Scheduler resources are readable during halted state" "0: DMA288 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA288 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA288 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9AE0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA288_cons0_control,Controlling consumer socket 0 for DMA288" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA288 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9AE8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA289_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA289" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA289 Scheduler resources must not be read during halted state. '1'-> DMA289 Scheduler resources are readable during halted state" "0: DMA289 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA289 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA289 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9B08++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA289_cons0_control,Controlling consumer socket 0 for DMA289" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA289 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9B10++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA290_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA290" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA290 Scheduler resources must not be read during halted state. '1'-> DMA290 Scheduler resources are readable during halted state" "0: DMA290 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA290 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA290 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9B30++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA290_cons0_control,Controlling consumer socket 0 for DMA290" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA290 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9B38++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA291_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA291" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA291 Scheduler resources must not be read during halted state. '1'-> DMA291 Scheduler resources are readable during halted state" "0: DMA291 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA291 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA291 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9B58++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA291_cons0_control,Controlling consumer socket 0 for DMA291" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA291 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9D40++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA304_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA304" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA304 Scheduler resources must not be read during halted state. '1'-> DMA304 Scheduler resources are readable during halted state" "0: DMA304 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA304 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA304 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9D60++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA304_cons0_control,Controlling consumer socket 0 for DMA304" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA304 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9D68++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA305_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA305" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA305 Scheduler resources must not be read during halted state. '1'-> DMA305 Scheduler resources are readable during halted state" "0: DMA305 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA305 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA305 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9D88++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA305_cons0_control,Controlling consumer socket 0 for DMA305" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA305 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9D90++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA306_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA306" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA306 Scheduler resources must not be read during halted state. '1'-> DMA306 Scheduler resources are readable during halted state" "0: DMA306 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA306 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA306 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9DB0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA306_cons0_control,Controlling consumer socket 0 for DMA306" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA306 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9DB8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA307_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA307" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA307 Scheduler resources must not be read during halted state. '1'-> DMA307 Scheduler resources are readable during halted state" "0: DMA307 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA307 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA307 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9DD8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA307_cons0_control,Controlling consumer socket 0 for DMA307" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA307 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9DE0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA308_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA308" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA308 Scheduler resources must not be read during halted state. '1'-> DMA308 Scheduler resources are readable during halted state" "0: DMA308 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA308 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA308 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9E00++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA308_cons0_control,Controlling consumer socket 0 for DMA308" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA308 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9E08++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA309_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA309" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA309 Scheduler resources must not be read during halted state. '1'-> DMA309 Scheduler resources are readable during halted state" "0: DMA309 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA309 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA309 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9E28++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA309_cons0_control,Controlling consumer socket 0 for DMA309" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA309 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9E30++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA310_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA310" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA310 Scheduler resources must not be read during halted state. '1'-> DMA310 Scheduler resources are readable during halted state" "0: DMA310 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA310 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA310 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9E50++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA310_cons0_control,Controlling consumer socket 0 for DMA310" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA310 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9E58++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA311_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA311" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA311 Scheduler resources must not be read during halted state. '1'-> DMA311 Scheduler resources are readable during halted state" "0: DMA311 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA311 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA311 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9E78++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA311_cons0_control,Controlling consumer socket 0 for DMA311" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA311 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9E80++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA312_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA312" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA312 Scheduler resources must not be read during halted state. '1'-> DMA312 Scheduler resources are readable during halted state" "0: DMA312 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA312 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA312 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9EA0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA312_cons0_control,Controlling consumer socket 0 for DMA312" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA312 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0x9EA8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA313_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA313" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA313 Scheduler resources must not be read during halted state. '1'-> DMA313 Scheduler resources are readable during halted state" "0: DMA313 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA313 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA313 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0x9EC8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA313_cons0_control,Controlling consumer socket 0 for DMA313" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA313 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0xA240++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA336_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA336" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA336 Scheduler resources must not be read during halted state. '1'-> DMA336 Scheduler resources are readable during halted state" "0: DMA336 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA336 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA336 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0xA260++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA336_cons0_control,Controlling consumer socket 0 for DMA336" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA336 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0xA4C0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA352_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA352" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA352 Scheduler resources must not be read during halted state. '1'-> DMA352 Scheduler resources are readable during halted state" "0: DMA352 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA352 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA352 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0xA4E0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA352_cons0_control,Controlling consumer socket 0 for DMA352" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA352 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0xA4E8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA353_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA353" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA353 Scheduler resources must not be read during halted state. '1'-> DMA353 Scheduler resources are readable during halted state" "0: DMA353 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA353 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA353 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0xA508++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA353_cons0_control,Controlling consumer socket 0 for DMA353" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA353 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0xA510++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA354_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA354" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA354 Scheduler resources must not be read during halted state. '1'-> DMA354 Scheduler resources are readable during halted state" "0: DMA354 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA354 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA354 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0xA530++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA354_cons0_control,Controlling consumer socket 0 for DMA354" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA354 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0xA538++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA355_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA355" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA355 Scheduler resources must not be read during halted state. '1'-> DMA355 Scheduler resources are readable during halted state" "0: DMA355 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA355 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA355 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0xA558++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA355_cons0_control,Controlling consumer socket 0 for DMA355" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA355 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0xA740++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA368_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA368" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA368 Scheduler resources must not be read during halted state. '1'-> DMA368 Scheduler resources are readable during halted state" "0: DMA368 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA368 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA368 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0xA760++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA368_cons0_control,Controlling consumer socket 0 for DMA368" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA368 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0xA768++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA369_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA369" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA369 Scheduler resources must not be read during halted state. '1'-> DMA369 Scheduler resources are readable during halted state" "0: DMA369 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA369 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA369 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0xA788++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA369_cons0_control,Controlling consumer socket 0 for DMA369" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA369 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0xA790++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA370_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA370" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA370 Scheduler resources must not be read during halted state. '1'-> DMA370 Scheduler resources are readable during halted state" "0: DMA370 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA370 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA370 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0xA7B0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA370_cons0_control,Controlling consumer socket 0 for DMA370" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA370 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" group.long 0xA7B8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA371_scheduler_control,Scheduler Control Register" hexmask.long.byte 0x0 13.--20. 1. "DMA_CHANNEL_NO,DMA channel number for thread scheduler for DMA371" newline bitfld.long 0x0 12. "DEBUG_RDY,'0' -> DMA371 Scheduler resources must not be read during halted state. '1'-> DMA371 Scheduler resources are readable during halted state" "0: DMA371 Scheduler resources must not be read..,?" newline hexmask.long.byte 0x0 7.--10. 1. "STATE,Current state of DMA371 Scheduler" newline bitfld.long 0x0 6. "PAUSE,'1' -> pause/suspend scheduler '0' -> resume scheduler" "0: resume scheduler,1: pause/suspend scheduler" newline bitfld.long 0x0 5. "STRM_EN,'1' -> Streaming input enable '0' No streaming input" "?,1: Streaming input enable" newline bitfld.long 0x0 1.--3. "PIPELINE_NUM,Pipeline Number of DMA371 Scheduler" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "SCH_EN,scheduler enable; write '1' to enable scheduler" "0,1" group.long 0xA7D8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__HTS__S_VBUSP__REGS_DMA371_cons0_control,Controlling consumer socket 0 for DMA371" hexmask.long.word 0x0 1.--9. 1. "PROD_SELECT,producer select for DMA371 cons socket 0" newline bitfld.long 0x0 0. "CONS_EN,'1' -> Consumer socket 0 enable '0' Disable" "?,1: Consumer socket 0 enable" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_CBCR_VBUSPI_CBCR_MEM" base ad:0x2C030000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MEMCFG_LOOP__CBCR_VBUSPI__CBCR_MEM_RAM,cbcr memory" hexmask.long.tbyte 0x0 0.--23. 1. "MEM,Memory location" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_MESH_VBUSPI_MESH_MEM" base ad:0x2C022000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MEMCFG_LOOP__MESH_VBUSPI__MESH_MEM_RAM,mesh memory" hexmask.long 0x0 0.--31. 1. "MEM,Memory location" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_Y_VBUSPI_Y_MEM" base ad:0x2C028000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MEMCFG_LOOP__Y_VBUSPI__Y_MEM_RAM,y memory" hexmask.long.tbyte 0x0 0.--23. 1. "MEM,Memory location" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP" base ad:0x2C020000 rgroup.long 0x0++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_REVISION_REG,LDC PID" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme. Spare bit to encode future schemes" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new FUNC number and hence PID should be assigned." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version. R as described in PDR with additional clarifications and definitions below. Must be easily ECO-able or controlled during fabrication. Ideally through a top level metal mask or e-fuse. This number is maintained/owned by IP design.." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision. X as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. X is part of IP numbering X.Y.R.Z. X changes ONLY when: (1) There is a major feature addition. An.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. 0 if non-custom." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision. Y as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. Y changes ONLY when: (1) Features are scaled (up or down). Flexibility exists in that this.." line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_PRIVATE_MEMSIZE,Memory size mentioned is for both ping and pong combined." hexmask.long.byte 0x4 16.--23. 1. "MESH,Mesh Private pixel memory size in KBytes" newline hexmask.long.byte 0x4 8.--15. 1. "CHROMA,Chroma Private pixel memory size in KBytes" newline hexmask.long.byte 0x4 0.--7. 1. "LUMA,Luma Private pixel memory size in KBytes" group.long 0x8++0x8B line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_CTRL,Control Register to Enable/Disable and select modes of operation" bitfld.long 0x0 24. "HYBD_ADDREN,Hybrid addressing scheme Enable. Enabled when part of the data stored in circular buffer and rest in Linear addressing buffers. When enabled IP_CIRCEN should be high and can only be enabled in frame mode." "0,1" newline bitfld.long 0x0 17.--18. "CH_IP_DFMT,Chroma Input pixel data format. Valid only independent chroma channel control is enbaled (CH_CHANCTRL_EN=1). 0: 8-bit format 1: 12-bit packed format 2: 12-bit unpacked format 3: Reserved" "0: 8-bit format,1: 12-bit packed format,2: 12-bit unpacked format,3: Reserved" newline bitfld.long 0x0 16. "CH_CHANCTRL_EN,Enable for Independent Chroma Channel parameters. Can be enabled only when chroma data is in separate buffer. When enabled Chroma channel parameters - Input Data Format/Line Offset/Circular buffer size/hybrid addressing parameters should.." "0,1" newline bitfld.long 0x0 14. "REGMODE_EN,Enables for Frame division into multiple regions. Needs to be enabled only when more than one region per frame. 0 - Disable 1 - Enable When enabled LDC provides option to configure independent block size parameters for each region" "0,1" newline bitfld.long 0x0 13. "OP_DATAMODE,Output Pixel Data Mode; Used when input is YUV422* mode. 0: YUV422 mode 1: convert to YUV420 output data;" "0: YUV422 mode,1: convert to YUV420 output data" newline bitfld.long 0x0 12. "IP_HTS_ROWSYNC,Enables control of Input Fetch with HTS at Block Row level. 0 - Disable 1 - Enable When enabled input fetch of first block in row is gated with corresponding HTS Tstart number. This allows synchronization between VISS and LDC or/and.." "0,1" newline bitfld.long 0x0 11. "IP_CIRCEN,Enables circular addressing mode on input pixel fetch. Can only be enabled in Frame mode. 0 - Disable circular addressing for input data. 1 - Enable circular addressing." "0,1" newline bitfld.long 0x0 10. "ALIGN_12BIT,Alignment of 12-bit pixel in 16-bit unpacked data format on input pixel data. Common for both Luma and Chroma channels. 0 - LSB Aligned 1 - MSB Aligned" "0,1" newline bitfld.long 0x0 9. "PWARPEN,Perspective warp transform Enable. Set to 1 to enable use of PWARP_GH.G and PWARP_GH.H" "0,1" newline bitfld.long 0x0 7.--8. "IP_DFMT,Input Pixel Data Format 0: 8-bit format 1: 12-bit packed format 2: 12-bit unpacked format 3: Reserved" "0: 8-bit format,1: 12-bit packed format,2: 12-bit unpacked format,3: Reserved" newline hexmask.long.byte 0x0 3.--6. 1. "IP_DATAMODE,Input Pixel Data Mode 0: YUV422 UYVY Interleaved data 1: YUV420_Y Luma Data Only 2: YUV420 Data 3: YUV420_UV Chroma Data Only. 4: YUV422_SP Semi-Planar Data. 5: Y1_Y2 - 2 independent channel data at full resolution in separate.." newline rbitfld.long 0x0 2. "BUSY,Idle/Busy Status 0: Idle 1: Busy Set on hts_init when LDC_EN is high cleared on Frame completion" "0: Idle,1: Busy Set on hts_init when LDC_EN is high" newline bitfld.long 0x0 1. "LDMAPEN,Distortion Back Mapping Enable. 1: Enabled 0: Disabled" "0: Disabled,1: Enabled" newline bitfld.long 0x0 0. "LDC_EN,Write 1 to enable LDC function. Auto cleared by HW at the end of Frame in OneShoft mode. In continuous mode needs to cleared by SW at the end to enter Idle condition" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_CFG,LDC Configuration register." bitfld.long 0x4 6. "YINT_TYP,Interpolation type for Y data. 0: bicubic 1: bilinear" "0: bicubic,1: bilinear" newline bitfld.long 0x4 2. "CNTU_MODE,Continuous mode enable. When enabled LDC HW won't disable at the end of frame and will start frame processing on hts_init. 0: One Shot mode (default) - LDC enable is cleared at the end of frame 1: Continous mode - LDC will continue to be.." "0: One Shot mode,1: Continous mode" newline bitfld.long 0x4 1. "CLKCG_OVERIDE,Clock gating override control for memory clock gating for Pbist config testing" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_MESHTABLE_CFG,Defines the down-sampling factors used for the mesh offset tables" bitfld.long 0x8 0.--2. "M,Mesh table down-sampling factor (by 2^M in both horizontal and Vertical). 0: 1 - no down-sampling 1: 2 - 2x down-sampling 2: 4 3: 8 4: 16 5: 32 6: 64 7:128" "0: 1,1: 2,2: 4,3: 8,4: 16,5: 32,6: 64,7: 128" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_MESH_FRSZ,Mesh data mapping is available for this Frame size. Actual number of mesh data entires depend Mesh Frame size and Mesh sampling factor. This Frame size is independent from.." hexmask.long.word 0xC 16.--29. 1. "H,Mesh Frame height in Lines" newline hexmask.long.word 0xC 0.--13. 1. "W,Mesh Frame Width" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_COMPUTE_FRSZ,H corresponds to the total number of lines to process. W corresponds to the number of pixels to process in each line. This parameters must be loaded as actual pixel counts. NOT.." hexmask.long.word 0x10 16.--29. 1. "H,Output Frame height in Lines. Must be even" newline hexmask.long.word 0x10 0.--13. 1. "W,Output Frame Width. Must be even" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_INITXY,LDC Initial Output Co-ordinate to process" hexmask.long.word 0x14 16.--28. 1. "INITY,Output starting Y-coordinate. must be even" newline hexmask.long.word 0x14 0.--12. 1. "INITX,Output starting X-coordinate. must be even" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_INPUT_FRSZ,Defines the total input frame size" hexmask.long.word 0x18 16.--29. 1. "H,Input Frame height in Lines. Must be even" newline hexmask.long.word 0x18 0.--13. 1. "W,Input Frame Width in Pixels. Must be even" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_OUT_BLKSZ,LDC Output Block parameter registers. These parameters represent actual pixel counts. NOT pixel counts - 1. OBW must be greater than 0 and less than or equal to frame width.." hexmask.long.byte 0x1C 16.--19. 1. "PIXPAD,Pixel pad" newline hexmask.long.byte 0x1C 8.--15. 1. "OBH,Output block height must be >0 and even" newline hexmask.long.byte 0x1C 0.--7. 1. "OBW,Output block width must be >0 and multiple of 8" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_AFF_AB,LDC Affine Transwarp A/B" hexmask.long.word 0x20 16.--31. 1. "B,Affine transwarp B (S16Q12)" newline hexmask.long.word 0x20 0.--15. 1. "A,Affine transwarp A (S16Q12)" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_AFF_CD,LDC Affine Transwarp C/D" hexmask.long.word 0x24 16.--31. 1. "D,Affine transwarp D (S16Q12)" newline hexmask.long.word 0x24 0.--15. 1. "C,Affine transwarp C (S16Q3)" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_AFF_EF,LDC Affine Transwarp E/F" hexmask.long.word 0x28 16.--31. 1. "F,Affine transwarp F (S16Q3)" newline hexmask.long.word 0x28 0.--15. 1. "E,Affine transwarp E (S16Q12)" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_PWARP_GH,LDC Perspective Transformation Parameters. G and H" hexmask.long.word 0x2C 16.--31. 1. "H,Perspective Transformation H (S16Q23)" newline hexmask.long.word 0x2C 0.--15. 1. "G,Perspective Transformation H (S16Q23)" line.long 0x30 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_MESH_BASE_H,Higher 16-bit of Mesh Table Base Address" hexmask.long.word 0x30 0.--15. 1. "ADDR,Higher 16-bit of Read Base address for mesh offset table" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_MESH_BASE_L,Lower 32-bit of Mesh Table Base Address" hexmask.long 0x34 0.--31. 1. "ADDR,Lower 32-bit of Read Base address for mesh offset table. Must be 16-byte aligned so four LSB are coded to 0" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_MESH_OFST,Defines the stride between rows for the Mesh table in bytes." hexmask.long.word 0x38 0.--15. 1. "OFST,LDC Mesh table line offset must be 16-byte aligned so four LSB are coded to 0" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_RD_BASE_H,Higher 16-bit of Input Frame Base Address" hexmask.long.word 0x3C 0.--15. 1. "ADDR,Higher 16-bit of Input Frame Base Address" line.long 0x40 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_RD_BASE_L,Lower 32-bit of Input Frame Base Address" hexmask.long 0x40 0.--31. 1. "ADDR,Lower 32-bit of Read Base address of Input Frame Base Address. Must be 16-byte aligned so four LSB are coded to 0" line.long 0x44 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_RD_420C_BASE_H,Higher 16-bit of Input Frame 420C Base Address" hexmask.long.word 0x44 0.--15. 1. "ADDR,Higher 16-bit of Input Frame Chroma Base Address in YUV420" line.long 0x48 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_RD_420C_BASE_L,Lower 32-bit of Input Frame Chroma Base Address in YUV420" hexmask.long 0x48 0.--31. 1. "ADDR,Lower 32-bit of Read Base address of Input Frame Chroma Base Address in YUV420. Must be 16-byte aligned so four LSB are coded to 0" line.long 0x4C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_RD_OFST,Define stride between lines in the Input Frame in bytes and circular buffer height" hexmask.long.word 0x4C 16.--29. 1. "MOD,Sets the circular buffer size if circular buffering mode is used. The circular buffer is sized in terms of number of lines and has to be multiple of 2" newline hexmask.long.word 0x4C 0.--15. 1. "OFST,Read frame line offset must be 16-byte aligned so internally [3:0] bits are hard-wired zero. OFST is common for Luma and Chroma in YUV420 mode" line.long 0x50 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_CH_RD_OFST,Define Chroma stride between lines in the Input Frame in bytes and chroma circular buffer height. Used when CH_CHANCTRL_EN is enabled" hexmask.long.word 0x50 16.--29. 1. "MOD,Sets the circular buffer size if circular buffering mode is used. The circular buffer is sized in terms of number of chroma lines" newline hexmask.long.word 0x50 0.--15. 1. "OFST,Read frame line offset must be 16-byte aligned so internally [3:0] bits are hard-wired zero." line.long 0x54 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_VBUSMR_CFG,Control VBUSM Read Interface" hexmask.long.word 0x54 16.--27. 1. "BW_CTRL,Limits the mean bandwidth (computed over one block) that the LDC module can request for read from system memory. 0: The BW limiter is bypassed 1~4095: maximum number of bytes per 256 cycles. Examples: 1 : 1.17 MBytes/s @ 300 MHz 4095 :.." newline hexmask.long.byte 0x54 3.--7. 1. "TAG_CNT,Limits the maximum number of outstanding LDC requests to TAG_CNT+1" newline bitfld.long 0x54 1.--2. "MAX_BURSTLEN,Limits the maximum burst length that could be used by LDC. Each burst is of 16 bytes. HW also breaks the command at max burst size boundary. For K3 devices it is best to keep burst size of 8 which command size of 128 bytes. 0: 16 1: 8.." "0: 16,1: 8,2: 4,3: 2" line.long 0x58 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_COREOUT_CHANCFG,LDC Core to LSE output channel enable control" bitfld.long 0x58 3. "CH3_EN,Enable for LDC Core to LSE Channel_3 connection used for Chroma Dual output. Expected to be enabled in Y1_Y2Y3 Data mode" "0,1" newline bitfld.long 0x58 2. "CH2_EN,Enable for LDC Core to LSE Channel_2 connection used for Luma Dual output. Should be disabled in Y1_Y2Y3 Data mode" "0,1" newline bitfld.long 0x58 1. "RSRV_CH1,Primary Chroma channel (LSE Channel_1) enable extracted from output data mode" "0,1" newline bitfld.long 0x58 0. "RSRV_CH0,Primary Luuma channel (LSE Channel_0) enable extracted from output data mode" "0,1" line.long 0x5C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_DUALOUT_CFG,Configuration for Dual Luma and Chroma channels and LUT" hexmask.long.byte 0x5C 21.--24. 1. "COUT_BITDPTH,Chroma Output Data Bit depth. Output clipped at 2^COUT_BITDPTH -1. Valid values 12-8" newline hexmask.long.byte 0x5C 17.--20. 1. "CIN_BITDPTH,Chroma Input Data Bit depth. Should same as YIN_BITDPTH. Valid values 12 to 8" newline bitfld.long 0x5C 16. "CLUT_EN,Chroma LUT mapping enable. If disabled data is sent as it is bypassing LUT mapping. Expected to be disabled in Y1_Y2Y3 Data mode" "0,1" newline hexmask.long.byte 0x5C 5.--8. 1. "YOUT_BITDPTH,Luma Output Data Bit depth. Output clipped at 2^YOUT_BITDPTH -1. Valid values 12-8" newline hexmask.long.byte 0x5C 1.--4. 1. "YIN_BITDPTH,Luma Input Data Bit depth. Valid values 12 to 8" newline bitfld.long 0x5C 0. "YLUT_EN,Luma LUT mapping enable. If disabled data is sent as it is bypassing LUT mapping" "0,1" line.long 0x60 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_IBUF_PIX_START,Expected to be used when Circular buffer is enabled. SW needs to make sure that all required pixel data is after this start pixel. Base address and Off Set needs to align with.." hexmask.long.word 0x60 16.--28. 1. "STARTY,Vertical pixel start position. Must be Even and should be programmed as '0' when hybrid addressing mode is enabled" newline hexmask.long.word 0x60 0.--12. 1. "STARTX,Horizontal pixel start position. Must be align to 16-byte base address" line.long 0x64 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CBUFF_PARAM,Valid when HYBD_ADDREN is enabled. Frame data from Start to end line is stored in Circular buffer and rest of the data in stored in linear buffer(s)" hexmask.long.word 0x64 16.--28. 1. "STARTLINE,Start line of the frame which is stored in the circular buffer. Must be even" newline hexmask.long.word 0x64 0.--12. 1. "ENDLINE,End line of the frame which is stored in the circular buffer. Must be Odd" line.long 0x68 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CBUFF_BA_H,Higher 16-bit of circular buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long.word 0x68 0.--15. 1. "ADDR,Higher 16-bit of circular buffer base address in hydrid addressing mode" line.long 0x6C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CBUFF_BA_L,Lower 32-bit of circular buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long 0x6C 0.--31. 1. "ADDR,Lower 32-bit of circular buffer base address in hydrid addressing mode. Must be 16-byte aligned so four LSB are coded to 0" line.long 0x70 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_BUFF2_BA_H,Higher 16-bit of second linear buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long.word 0x70 0.--15. 1. "ADDR,Higher 16-bit of second linear buffer base address in hydrid addressing mode" line.long 0x74 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_BUFF2_BA_L,Lower 32-bit of second linear buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long 0x74 0.--31. 1. "ADDR,Lower 32-bit of second linear buffer base address in hydrid addressing mode. Must be 16-byte aligned so four LSB are coded to 0" line.long 0x78 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CHCBUFF_PARAM,Valid when both CH_CHANCTRL_EN and HYBD_ADDREN are enabled. Frame data from Start to end line is stored in Circular buffer and rest of the data in stored in linear buffers." hexmask.long.word 0x78 16.--28. 1. "STARTLINE,Start line of the frame which is stored in the circular buffer. Must be even" newline hexmask.long.word 0x78 0.--12. 1. "ENDLINE,End line of the frame which is stored in the circular buffer. Must be odd" line.long 0x7C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CHCBUFF_BA_H,Higher 16-bit of chroma circular buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long.word 0x7C 0.--15. 1. "ADDR,Higher 16-bit of circular buffer base address in hydrid addressing mode" line.long 0x80 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CHCBUFF_BA_L,Lower 32-bit of chroma circular buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long 0x80 0.--31. 1. "ADDR,Lower 32-bit of circular buffer base address in hydrid addressing mode. Must be 16-byte aligned so four LSB are coded to 0" line.long 0x84 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CHBUFF2_BA_H,Higher 16-bit of second linear chroma buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long.word 0x84 0.--15. 1. "ADDR,Higher 16-bit of second linear buffer base address in hydrid addressing mode" line.long 0x88 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_HYBD_CHBUFF2_BA_L,Lower 32-bit of second linear chroma buffer base address in hydrid addressing mode. Valid when HYBD_ADDREN is enabled." hexmask.long 0x88 0.--31. 1. "ADDR,Lower 32-bit of second linear buffer base address in hydrid addressing mode. Must be 16-byte aligned so four LSB are coded to 0" group.long 0xE0++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_REGN_W12_SZ,Horizontal slice width for Region division" hexmask.long.word 0x0 16.--29. 1. "W2,Width of second horizontal slice. (Minimum of 8 and must be even)" newline hexmask.long.word 0x0 0.--13. 1. "W1,Width of first horizontal slice. (Minimum of 8 and must be even)" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_REGN_W3_SZ,Horizontal slice width for Region division" hexmask.long.word 0x4 0.--13. 1. "W3,Width of third horizontal slice. (Minimum of 8 and must be even)" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_REGN_H12_SZ,vertical slice height for Region division" hexmask.long.word 0x8 16.--29. 1. "H2,Height of second vertical slice. (must be even)" newline hexmask.long.word 0x8 0.--13. 1. "H1,Height of first vertical slice. (must be even)" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_REGN_H3_SZ,Vertical slice height for Region division" hexmask.long.word 0xC 0.--13. 1. "H3,Height of third vertical slice. (must be even)" group.long 0x200++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_ERR_STATUS,Control VBUSM Read Interface" bitfld.long 0x0 8.--10. "VBUSMR_ERR,VBUSM Read I/F Last Error Status. Write '1' to clear works independently for each bit." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "INT_SZOVF,Internal operation has overflown the HW supported block or frame sizes. Should be fixed" "0,1" newline bitfld.long 0x0 4. "M_IBLK_MEMOVF,Mesh block storage requirement is more than internal memory available. Should be fixed" "0,1" newline bitfld.long 0x0 3. "P_IBLK_MEMOVF,Input pixel block storage requirement is more than internal memory available. Should be fixed" "0,1" newline bitfld.long 0x0 2. "IFRAME_OUTB,Either Mesh data or Input pixel data required is going out of valid frame available" "0,1" newline bitfld.long 0x0 1. "M_IBLK_OUTB,Mesh Input Block out of Bound. Mesh data required for block is not available in the prefetched internal memory. Should be fine." "0,1" newline bitfld.long 0x0 0. "P_IBLK_OUTB,Pixel Input Block out of Bound. Pixel data required for block is not available in the prefetched internal memory. PIX_PAD is not enough" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_DEBUG_CTRL,Control the memory access selection" bitfld.long 0x4 0. "CFG_MEMACC_SEL,VBUSP Configuration access control. 0 - VBUSP can access Ping memories 1 - VBUSP can access pong memories All private memories Mesh Luma Chroma will share same.." "0,1" rgroup.long 0x208++0x17 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_DEBUG_STATUS,LDC Debug Status Register" bitfld.long 0x0 24. "PROC_STATUS,Block Processing status. 0 - Block Processing is ongoing 1 - Either block processing is completed or not started" "0,1" newline bitfld.long 0x0 16.--18. "FETCH_RESPSTATE,VBUSM Fetch Response state machine 3'd0 = ST_RESP_IDLE.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--12. 1. "FETCH_REQSTATE,VBUSM Fetch Request state machine 5'b00_000 = ST_REQ_IDLE.." newline hexmask.long.byte 0x0 0.--3. 1. "CTRL_STATE,Main Control State machine 4'd0 = STATE_IDLE.." line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_FR_PDFTCH,Pixel bytes fetched by VBUSM Read Interface. It is updated on every command issued and cleared at the beginning frame fetch. Reading at the end of the frame will provide total.." hexmask.long 0x4 0.--31. 1. "PBYTES,Pixel bytes fetched for current Frame. Reading at the end of frame will provide pixel data fetched for entire frame" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_FR_MDFTCH,Mesh bytes fetched by VBUSM Read Interface. It is updated on every command issued and cleared at the beginning frame fetch. Reading at the end of the frame will provide total number.." hexmask.long 0x8 0.--31. 1. "MBYTES,Mesh bytes fetched for current Frame. Reading at the end of frame will provide Mesh data fetched for entire frame" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_PIXMEMOVF_BLK,Starting co-ordinates of first output block for which input pixel buffer overflowed" hexmask.long.word 0xC 16.--28. 1. "Y,Start Y Co-ordinate" newline hexmask.long.word 0xC 0.--12. 1. "X,Start X Co-ordinate" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_MESHMEMOVF_BLK,Starting co-ordinates of first output block for which input mesh buffer overflowed" hexmask.long.word 0x10 16.--28. 1. "Y,Start Y Co-ordinate" newline hexmask.long.word 0x10 0.--12. 1. "X,Start X Co-ordinate" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_OUTOFBOUND_BLK,Starting co-ordinates of first output block for which PIX_PAD is not enough" hexmask.long.word 0x14 16.--28. 1. "Y,Start Y Co-ordinate" newline hexmask.long.word 0x14 0.--12. 1. "X,Start X Co-ordinate" group.long 0x100++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_CTRL,Region Control Register" bitfld.long 0x0 0. "ENABLE,Enable for processing of this region. This is can be used to selectively disable processing of some regions (default enabled). 1 - Process the region i.e. no skipping 0 - Don't process the region" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__MMR__VBUSP__REGS_OUT_BLKSZ,Block size and Pixel Pad config" hexmask.long.byte 0x4 16.--19. 1. "PIXPAD,Pixel pad" newline hexmask.long.byte 0x4 8.--15. 1. "OBH,Output block height must be >0 and even. Should be less than or equal to corresponding region height" newline hexmask.long.byte 0x4 0.--7. 1. "OBW,Output block width must be >0 and multiple of 8. Should be less than or equal to corresponding region width" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALC_LUTCFG_DUALC_LUT" base ad:0x2C021000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__PIXWRINTF__DUALC_LUTCFG__DUALC_LUT_LUT,dualc width conversion LUT" hexmask.long.word 0x0 16.--27. 1. "LUT_1,Bank-1" hexmask.long.word 0x0 0.--11. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALY_LUTCFG_DUALY_LUT" base ad:0x2C020800 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__PIXWRINTF__DUALY_LUTCFG__DUALY_LUT_LUT,dualy width conversion LUT" hexmask.long.word 0x0 16.--27. 1. "LUT_1,Bank-1" hexmask.long.word 0x0 0.--11. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_LDC0_S_VBUSP_VPAC_LDC_LSE_CFG_VP" base ad:0x2C020400 rgroup.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_status_param,The STATUS_PARAM register returns the LSE compile configuration parameters." bitfld.long 0x0 30.--31. "BYPASS_CH,Number of available input channel selection for loopback mode" "0,1,2,3" newline bitfld.long 0x0 29. "OUT_SKIP_EN,Output Auto-Skip Enable" "0,1" newline bitfld.long 0x0 28. "CORE_OUT_2D,1D or 2D output addressing mode(2D if 1)" "0,1" newline hexmask.long.byte 0x0 23.--27. 1. "CORE_OUT_DW,Core Output Channel Data Width" newline bitfld.long 0x0 22. "LINE_SKIP_EN,Source Line Inc by 2 Supported (if 1)" "0,1" newline bitfld.long 0x0 21. "BIT_AOFFSET,Source nibble offset address Supported (if 1)" "0,1" newline bitfld.long 0x0 20. "HV_INSERT,H/VBLANK Insertion Supported (if 1)" "0,1" newline bitfld.long 0x0 17.--19. "PIX_MX_HT,Core_Input Pixel Matrix Height" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--16. 1. "CORE_DW,Core Input Data Bus Width" newline bitfld.long 0x0 10.--11. "SL2_OUT_H3A_CH,Number of SL2 H3A Output Channels" "0,1,2,3" newline hexmask.long.byte 0x0 6.--9. 1. "SL2_OUT_CH,Number of SL2 Output Channels" newline bitfld.long 0x0 3.--5. "SL2_IN_CH_THR,Number of Input Channels per thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "VPORT_THR,Number of VPORT input enabled" "0,1" newline bitfld.long 0x0 0.--1. "NTHR,Number of threads supported" "0,1,2,3" group.long 0x4++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_status_error,The STATUS_ERROR register returns the LSE error status." hexmask.long.byte 0x0 8.--14. 1. "VM_WR_ERR,VBUSM I/F Last Write Error Status [14:11] Write Channel Number [10:8] VBUSM write error status" rgroup.long 0x8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_status_idle_mode,The STATUS_IDLE_MODE register returns IDLE status of LSE VBUSM port and in/output channels - 0: IDLE 1: ACTIVE" hexmask.long.byte 0x0 12.--15. 1. "LSE_OUT_CHAN,Output Channel[3:0] Status" newline bitfld.long 0x0 1. "VM_WR_PORT,SL2 vbusm I/F Write Port Status" "0,1" group.long 0xC++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_cfg_lse,The CFG_LSE register configures the LSE general hardware modes." bitfld.long 0x0 8. "PSA_EN,Test mode Output Channel Signature Generation Enable 0: Disable (default) 1: Enable When enabled LSE generates a unique CRC signature for each output channel's frame data at frame completion." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 4. "VM_ARB_FIXED_MODE,VBUSM Arbitration Fixed Mode select 0: Round-Robin Arbitration (default) 1: Fixed-mode Arbitration" "0: Round-Robin Arbitration,1: Fixed-mode Arbitration" group.long 0x13C++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_dst_common_cfg,The DST_COMMON_CFG register captures common configuration for the output channels" hexmask.long.byte 0x0 0.--5. 1. "ROUNDING_OFFSET,output channel rounding offset value. Default value to be considered 6'h08" rgroup.long 0x140++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_psa_signature,The PSA_SIGNATURE register returns the captured PSA signature value of the last frame data of output channel [a]." hexmask.long 0x0 0.--31. 1. "VALUE,32-bit CRC signature value" rgroup.long 0x1E0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_dbg,The DBG register returns the current status of internal FSM - TI internal use only." hexmask.long 0x0 0.--31. 1. "STATUS,Debug status" group.long 0x50++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_buf_cfg,The DST_BUF_CFG register configures the output buffer channel ." rbitfld.long 0x0 31. "CH_DISABLED,Channel Disable Status (read-only) 0: (Default) Chanel is enabled for Y UV or YUV422 data transfer to SL2 memory. All configurations associated with this DST_BUF[a] are valid. 1: Channel is disabled for SL2 data transfer (because the.." "0: (Default,1: Channel is disabled for SL2 data transfer" newline bitfld.long 0x0 29. "YUV422_INTLV_ORDER,YUV422 Interleaving Order Selection 0: UYVY 1: YUYV Only Applicable if this output channel is YUV422 output capable LUMA channel. Otherwise setting has no effect." "0: UYVY,1: YUYV Only Applicable if this output channel is.." newline bitfld.long 0x0 28. "YUV422_OUT_EN,YUV422 Interleaved Output Merge Enable 0: Disable 1: Enable When enabled this channel interleaves data from the associated chroma data output channel to output YUV422 interleaved data to the SL2 memory. Only Applicable if this output.." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 10. "ENABLE_SIGNED_ACCLERATOR_DATA,Specify the acclerator data to be signed or unsigned 0: Unsigned data (By default) 1: Signed Data" "0: Unsigned data,1: Signed Data" newline bitfld.long 0x0 9. "ENABLE_OUTPUT_PIXEL_ROUNDING,enable acclerator pixel output rounding 0: Disable rounding logic 1: Enable rounding logic" "0: Disable rounding logic,1: Enable rounding logic" newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Output Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Output Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Output pixel container size must be same or larger than output pixel width. If yuv422_out_en is set pix_fmt_cntrsz must be 0." "0: 8-bit,1: 12-bit,2: 16-bit,3: reserved Output pixel container size must be.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Output Pixel Width Sel 0: 8-bit 1: 12-bit 2: reserved 3: 16-bit The width defines the bit-depth of the pixel data to be stored in the pixel container." "0: 8-bit,1: 12-bit,2: reserved,3: 16-bit The width defines the bit-depth of the.." line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_buf_attr0,The DST_BUF_ATTR0 register configures the attributes of the output SL2 buffer ." hexmask.long.word 0x4 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0x4 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0x4 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_buf_attr1,The DST_BUF_ATTR1 register configures the 2D Block attributes of the output SL2 buffer ." hexmask.long.word 0x8 16.--25. 1. "CBUF_BPR_CHAN,Circular Buffer - 2D blocks per row defined by cbuf_stride (selected when bpr_sel_mode=0)" newline bitfld.long 0x8 2. "TDONE_GEN_MODE,HTS Tdone Generation Mode for 2D transfer 0: Generate Tdone on every 2D block completion 1: Generate Tdone only at the end of CBUF_BPR Must be common across all DST channels and Must be set to 0 when BPR settings for enabled output.." "0: Generate Tdone on every 2D block completion,1: Generate Tdone only at the end of CBUF_BPR Must.." newline bitfld.long 0x8 1. "BPR_SEL_MODE,CBUF BPR Selection mode 0: Use cbuf_bpr_chan (applied to all regions) for this output channel 1: Use the common multi-region BPR parameters" "0: Use cbuf_bpr_chan,1: Use the common multi-region BPR parameters" newline bitfld.long 0x8 0. "CBUF_VWRAP_EN,CBUF Vertical Wrap Enable 0: Disable (for Memory to Memory data transfer mode) 1: Enable (for In-Line Rasterization Mode)" "0: Disable,1: Enable" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_buf_ba,The DST_BUF_BA register configures the base address of the output SL2 circular buffer ." bitfld.long 0xC 31. "ENABLE,Output Channel Enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline hexmask.long.tbyte 0xC 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0xC 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" group.long 0x100++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_LDC0__S_VBUSP__VPAC_LDC_LSE__CFG_VP__REGS_row,The COMMON_CFG_ROW registers configure the common CBUF_BPR values for regions of all output channels." hexmask.long.word 0x0 20.--29. 1. "BPR0,Region [a 0] CBUF_BPR value" newline hexmask.long.word 0x0 10.--19. 1. "BPR1,Region [a 1] CBUF_BPR value" newline hexmask.long.word 0x0 0.--9. 1. "BPR2,Region [a 2] CBUF_BPR value" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_MSC_CFG_VP_CFG_VP" base ad:0x2C0C0000 rgroup.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_revision,The REVISION Register contains the major and minor revisions for the VPAC MSC HWA module." bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme. Spare bit to encode future schemes" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new FUNC number and hence PID should be assigned." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version. R as described in PDR with additional clarifications and definitions below. Must be easily ECO-able or controlled during fabrication. Ideally through a top level metal mask or e-fuse. This number is maintained/owned by IP design.." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision. X as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. X is part of IP numbering X.Y.R.Z. X changes ONLY when: (1) There is a major feature addition." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. 0 if non-c ustom." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision. Y as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owne r. Y changes ONLY when: (1) Features are scaled (up or down). Flexibility exists in that this.." group.long 0x4++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_control,The CONTROL Register allows the CPU to control various aspects of the module." bitfld.long 0x0 0. "MSC_ENABLE,MSC Core Enable: Enables the MSC HWA. (Must be enabled even when MSC is strictly in the loopback-only mode. Individual resizing filter is enabled only when the output buffer associated with the filter is enabled in the LSE configuration.) 0:.." "0: Disable,1: Enable" group.long 0x10++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_cfg,The FILT[a]_CFG register configures the modes of FILTER channel [a]." bitfld.long 0x0 22. "SIGNED_DATA,Integer type of input and output frame data: 0 : Unsigned 12-bit (default) 1 : Signed 12-bit" "0: Unsigned 12-bit,1: Signed 12-bit" newline hexmask.long.byte 0x0 18.--21. 1. "COEF_SHIFT,Coef Shift Size: configures the precision of the 10-bit signed filter coefficients (valid Shift range: 5~9) : 5: Shift by 5 (5-bit fraction) 6: Shift by 6 (6-bit fraction) 7: Shift by 7 (7-bit fraction) 8: Shift by 8 (8-bit.." newline bitfld.long 0x0 17. "UV_MODE,Source data interleave format: 0 - non-interleaved (Y data) 1 - interleaved (UV data)" "0,1" newline bitfld.long 0x0 16. "SAT_MODE,Filter Output Saturation Mode 0 - [0..4095] clipping 1 - [-2048.. 2047] clip followed by +2048 This is used only when signed_data=0 (unsigned data type)." "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "SP_VS_COEF_SEL,Single Phase Vertical Filter Coef Selection (sp_vs_coef_src = 0) 0000 : Use Dedicated SP coef-0 0001 : Use Dedicated SP coef-1 (sp_hs_coef_src = 1) N : Use (N+16)th entry of 5-tap/32-phase filter coef set 0 (N = 0..15)" newline bitfld.long 0x0 11. "SP_VS_COEF_SRC,Single Phase Vertical Filter Coef Source Selection 0 : Use one of two dedicated single phase coeffs 1 : Use the custom single phase coeff table (5-tap/32-phase Filter coef set 0) If set to 1 5-tap/32-phase filter coef set-0 is to.." "0: Use one of two dedicated single phase coeffs,1: Use the custom single phase coeff table" newline hexmask.long.byte 0x0 7.--10. 1. "SP_HS_COEF_SEL,Single Phase Horizontal Filter Coef Selection (sp_hs_coef_src = 0) 0000 : Use Dedicated SP coef-0 0001 : Use Dedicated SP coef-1 (sp_hs_coef_src = 1) N : Use Nth entry of 5-tap/32-phase filter coef set 0 (N = 0..15)" newline bitfld.long 0x0 6. "SP_HS_COEF_SRC,Single Phase Horizontal Filter Coef Source Selection 0 : Use one of two dedicated single phase coeffs 1 : Use the custom single phase coeff table (5-tap/32-phase Filter coef set 0) If set to 1 5-tap/32-phase filter coef set-0 is.." "0: Use one of two dedicated single phase coeffs,1: Use the custom single phase coeff table" newline bitfld.long 0x0 4.--5. "VS_COEF_SEL,Multi-phase Vertical Coef Selection (Phase_mode=0) 00 : 5-tap/32-phase Filter coef sets 0 & 1 10 : 5-tap/32-phase Filter Coef sets 2 & 3 (Phase_mode=1) 00 : 5-tap/32-phase Filter coef set 0 01 : 5-tap/32-phase Filter coef set 1.." "0: 5-tap/32-phase Filter coef set 0,1: 5-tap/32-phase Filter coef set 1,?,?" newline bitfld.long 0x0 2.--3. "HS_COEF_SEL,Multi-phase Horizontal Coef Selection (Phase_mode=0) 00 : 5-tap/32-phase Filter coef sets 0 & 1 10 : 5-tap/32-phase Filter Coef sets 2 & 3 (Phase_mode=1) 00 : 5-tap/32-phase Filter coef set 0 01 : 5-tap/32-phase Filter coef set 1.." "0: 5-tap/32-phase Filter coef set 0,1: 5-tap/32-phase Filter coef set 1,?,?" newline bitfld.long 0x0 1. "PHASE_MODE,Filter Phase mode selection 0 - 64 phases 1 - 32 phases" "0,1" newline bitfld.long 0x0 0. "FILTER_MODE,Filter Mode 0 : Single Phase Filter (e.g. Gaussian Filter for Pyramid generation) 1: Multi-phase Scaling Filter" "0: Single Phase Filter,1: Multi-phase Scaling Filter" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_src_roi,The FILT[a]_SRC_ROI register configures the input ROI position within the input super frame for FILTER channel [a]. Set to 0 if ROI is full-size." hexmask.long.word 0x4 16.--28. 1. "Y_OFFSET,Source Y offset" newline hexmask.long.word 0x4 0.--12. 1. "X_OFFSET,Source X offset (Must be an even # when FILT_CFG.uv_mode=1)" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_out_size,The FILT[a]_OUT_SIZE configures the output size for FILTER channel [a]." hexmask.long.word 0x8 16.--28. 1. "HEIGHT,Output Height" newline hexmask.long.word 0x8 0.--12. 1. "WIDTH,Output Width" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_firinc,The FILT[a]_FIRINC register configures the FIRINC attributes of FILTER channel [a]." hexmask.long.word 0xC 16.--30. 1. "VS,FIRINC of VS filter" newline hexmask.long.word 0xC 0.--14. 1. "HS,FIRINC of HS filter" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_acc_init,The FILT[a]_ACC_INIT register configures the FIRINC attributes of FILTER channel [a]." hexmask.long.word 0x10 16.--27. 1. "VS,ACC_INIT of VS filter" newline hexmask.long.word 0x10 0.--11. 1. "HS,ACC_INIT of HS filter" group.long 0x180++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_c210,Single Phase Coef Set[a] coefficients C2/C1/C0" hexmask.long.word 0x0 20.--29. 1. "FIR_C2,Signed coefficient C2" newline hexmask.long.word 0x0 10.--19. 1. "FIR_C1,Signed coefficient C1" newline hexmask.long.word 0x0 0.--9. 1. "FIR_C0,Signed coefficient C0" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_c43,Single Phase Coef Set[a] coefficients C4/C3" hexmask.long.word 0x4 10.--19. 1. "FIR_C4,Signed coefficient C4" newline hexmask.long.word 0x4 0.--9. 1. "FIR_C3,Signed coefficient C3" group.long 0x200++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_c210,Multi Phase Coef Set[a] Phase[b] coefficients C2/C1/C0" hexmask.long.word 0x0 20.--29. 1. "FIR_C2,Signed coefficient C2" newline hexmask.long.word 0x0 10.--19. 1. "FIR_C1,Signed coefficient C1" newline hexmask.long.word 0x0 0.--9. 1. "FIR_C0,Signed coefficient C0" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__CFG__VP__REGS_c43,Multi Phase Coef Set[a] Phase[b] coefficients C4/C3" hexmask.long.word 0x4 10.--19. 1. "FIR_C4,Signed coefficient C4" newline hexmask.long.word 0x4 0.--9. 1. "FIR_C3,Signed coefficient C3" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_MSC_CFG_VP_LSE_CFG_VP" base ad:0x2C0C0800 rgroup.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_status_param,The STATUS_PARAM register returns the LSE compile configuration parameters." bitfld.long 0x0 30.--31. "BYPASS_CH,Number of available input channel selection for loopback mode" "0,1,2,3" newline bitfld.long 0x0 29. "OUT_SKIP_EN,Output Auto-Skip Enable" "0,1" newline bitfld.long 0x0 28. "CORE_OUT_2D,1D or 2D output addressing mode(2D if 1)" "0,1" newline hexmask.long.byte 0x0 23.--27. 1. "CORE_OUT_DW,Core Output Channel Data Width" newline bitfld.long 0x0 22. "LINE_SKIP_EN,Source Line Inc by 2 Supported (if 1)" "0,1" newline bitfld.long 0x0 21. "BIT_AOFFSET,Source nibble offset address Supported (if 1)" "0,1" newline bitfld.long 0x0 20. "HV_INSERT,H/VBLANK Insertion Supported (if 1)" "0,1" newline bitfld.long 0x0 17.--19. "PIX_MX_HT,Core_Input Pixel Matrix Height" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--16. 1. "CORE_DW,Core Input Data Bus Width" newline bitfld.long 0x0 10.--11. "SL2_OUT_H3A_CH,Number of SL2 H3A Output Channels" "0,1,2,3" newline hexmask.long.byte 0x0 6.--9. 1. "SL2_OUT_CH,Number of SL2 Output Channels" newline bitfld.long 0x0 3.--5. "SL2_IN_CH_THR,Number of Input Channels per thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "VPORT_THR,Number of VPORT input enabled" "0,1" newline bitfld.long 0x0 0.--1. "NTHR,Number of threads supported" "0,1,2,3" group.long 0x4++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_status_error,The STATUS_ERROR register returns the LSE error status." hexmask.long.byte 0x0 8.--14. 1. "VM_WR_ERR,VBUSM I/F Last Write Error Status [14:11] Write Channel Number [10:8] VBUSM write error status" newline hexmask.long.byte 0x0 0.--4. 1. "VM_RD_ERR,VBUSM I/F Last Read Error Status [4:3] Read Channel Number [2:0] VBUSM read error status" rgroup.long 0x8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_status_idle_mode,The STATUS_IDLE_MODE register returns IDLE status of LSE VBUSM port and in/output channels - 0: IDLE 1: ACTIVE" hexmask.long.word 0x0 12.--21. 1. "LSE_OUT_CHAN,Output Channel[9:0] Status" newline hexmask.long.byte 0x0 4.--7. 1. "LSE_IN_CHAN,Input Channel[3:0] Status" newline bitfld.long 0x0 1. "VM_WR_PORT,SL2 vbusm I/F Write Port Status" "0,1" newline bitfld.long 0x0 0. "VM_RD_PORT,SL2 vbusm I/F Read Port Status" "0,1" group.long 0xC++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_cfg_lse,The CFG_LSE register configures the LSE general hardware modes." bitfld.long 0x0 8. "PSA_EN,Test mode Output Channel Signature Generation Enable 0: Disable (default) 1: Enable When enabled LSE generates a unique CRC signature for each output channel's frame data at frame completion." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 4. "VM_ARB_FIXED_MODE,VBUSM Arbitration Fixed Mode select 0: Round-Robin Arbitration (default) 1: Fixed-mode Arbitration" "0: Round-Robin Arbitration,1: Fixed-mode Arbitration" newline bitfld.long 0x0 1. "LOOPBACK_CORE_EN,Functional path (data to HWA core) enable during loopback mode 0: Disable 1: Enable When enabled the loopback-enabled input channel is used also for CORE data input. Otherwise it is strictly used for the loopback path." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 0. "LOOPBACK_EN,LSE loopback mode enable 0: Disable 1: Enable When enabled the second thread's input channel data (middle tap data) is looped back out to the last (#9) output channel." "0: Disable,1: Enable When enabled" group.long 0x13C++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_dst_common_cfg,The DST_COMMON_CFG register captures common configuration for the output channels" hexmask.long.byte 0x0 0.--5. 1. "ROUNDING_OFFSET,output channel rounding offset value. Default value to be considered 6'h08" rgroup.long 0x140++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_psa_signature,The PSA_SIGNATURE register returns the captured PSA signature value of the last frame data of output channel [a]." hexmask.long 0x0 0.--31. 1. "VALUE,32-bit CRC signature value" group.long 0x170++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_src0_cfg1,The src0_cfg1 register configures the input channels for the processing thread [a]" bitfld.long 0x0 6. "SKIP_SL2_READS,When set skips SL2 reads from the channel and channel0 read_data is redirected to the current channel" "0,1" newline bitfld.long 0x0 5. "ENABLE_CHAN_SPECIFIC_PARAMS,Enables channel specific SRC_CFG and FRAME_SIZE parameters. 0 : Current channel config parameters are derived from chan0 MMR's. 1 : Current channel config parameters are derived from channel specific MMR's" "0: Current channel config parameters are derived..,1: Current channel config parameters are derived.." newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Input pixel container size must be same or larger than input pixel width." "0: 8-bit,1: 12-bit,2: 16-bit,3: reserved Input pixel container size must be same.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Input Pixel Width Sel 0: 8-bit 1: 12-bit 2: 14-bit 3: 16-bit The width defines the bit-depth of the pixel data to be extracted from the pixel container." "0: 8-bit,1: 12-bit,2: 14-bit,3: 16-bit The width defines the bit-depth of the.." line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_src0_frame_size1,The src0_frame_size1 register configures the frame size of all input buffers for the processing thread [a]." hexmask.long.word 0x4 0.--12. 1. "WIDTH,SL2 - Source Buffer Width (number of pixels)" group.long 0x190++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_src1_cfg1,The src1_cfg1 register configures the input channels for the processing thread [a]" bitfld.long 0x0 6. "SKIP_SL2_READS,When set skips SL2 reads from the channel and channel0 read_data is redirected to the current channel" "0,1" newline bitfld.long 0x0 5. "ENABLE_CHAN_SPECIFIC_PARAMS,Enables channel specific SRC_CFG and FRAME_SIZE parameters. 0 : Current channel config parameters are derived from chan0 MMR's. 1 : Current channel config parameters are derived from channel specific MMR's" "0: Current channel config parameters are derived..,1: Current channel config parameters are derived.." newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Input pixel container size must be same or larger than input pixel width." "0: 8-bit,1: 12-bit,2: 16-bit,3: reserved Input pixel container size must be same.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Input Pixel Width Sel 0: 8-bit 1: 12-bit 2: 14-bit 3: 16-bit The width defines the bit-depth of the pixel data to be extracted from the pixel container." "0: 8-bit,1: 12-bit,2: 14-bit,3: 16-bit The width defines the bit-depth of the.." line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_src1_frame_size1,The src1_frame_size1 register configures the frame size of all input buffers for the processing thread [a]." hexmask.long.word 0x4 0.--12. 1. "WIDTH,SL2 - Source Buffer Width (number of pixels)" rgroup.long 0x1E0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_dbg,The DBG register returns the current status of internal FSM - TI internal use only." hexmask.long 0x0 0.--31. 1. "STATUS,Debug status" group.long 0x10++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_cfg,The SRC[a]_CFG register configures the input channels for the processing thread [a]" bitfld.long 0x0 19.--21. "KERN_TPAD_SZ,Input kernel top padding lines valid=0..2 for msc" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "KERN_BPAD_SZ,Input kernel bottom padding lines valid=0..2 for msc" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--15. 1. "KERN_LN_OFFSET,Input kernel starting line position valid=0..4 for msc" newline hexmask.long.byte 0x0 8.--11. 1. "KERN_SZ_HEIGHT,Actual number of input kernel lines (height) valid=1..5 for msc" newline bitfld.long 0x0 7. "SRC_LN_INC_2,Source Line address Increment by 2 enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Input pixel container size must be same or larger than input pixel width." "0: 8-bit,1: 12-bit,2: 16-bit,3: reserved Input pixel container size must be same.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Input Pixel Width Sel 0: 8-bit 1: 12-bit 2: 14-bit 3: 16-bit The width defines the bit-depth of the pixel data to be extracted from the pixel container." "0: 8-bit,1: 12-bit,2: 14-bit,3: 16-bit The width defines the bit-depth of the.." group.long 0x18++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_frame_size,The SRC[a]_FRAME_SIZE register configures the frame size of all input buffers for the processing thread [a]." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,SL2 - Source Buffer Height (number of lines)" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,SL2 - Source Buffer Width (number of pixels)" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_buf_attr,The SRC[a]_BUF_ATTR register configures the common attributes of all SL2 source buffers for the processing thread [a]." hexmask.long.byte 0x4 25.--31. 1. "START_NIB_OFFSET,Buffer Line start offset within the first SL2 data word - in half-byte (nibble) resolution" newline hexmask.long.word 0x4 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0x4 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0x4 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_buf_ba,The SRC[a]_BUF_BA[b] register configures the base address of the SL2 source buffer [b] for the processing thread [a]." bitfld.long 0x8 31. "ENABLE,Input Buffer Enable 0: Disable 1: Enable When the processing thread is enabled at least one of the input buffer must be enabled" "0: Disable,1: Enable When the processing thread is enabled" newline bitfld.long 0x8 30. "SKIP_ODD_LINE_PROC,This bit when set skips odd line processing" "0,1" newline bitfld.long 0x8 29. "SKIP_ALTERNATE_LINE_PROC,This bit when enabled skips processing of lines. This is used in YUV420 MSC scalar processing Y and UV pixels on the single HTS thread" "0,1" newline bitfld.long 0x8 28. "ENABLE_INTERLEAVED_PIXEL_EXTRACTION,This bit when set enable interleaved pixel extraction. usecases : YUV422 scenarios" "0,1" newline bitfld.long 0x8 27. "EXTRACT_INTERLEAVED_ODD_PIXELS,This bit is valid when enable_interleaved_pixel_extraction is set. 1 : Odd pixels extracted 0 : Even pixels extracted" "0: Even pixels extracted,1: Odd pixels extracted" newline hexmask.long.tbyte 0x8 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x8 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" group.long 0x50++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_buf_cfg,The DST[a]_BUF_CFG register configures the output buffer channel [a]." rbitfld.long 0x0 31. "CH_DISABLED,Channel Disable Status (read-only) 0: (Default) Chanel is enabled for Y UV or YUV422 data transfer to SL2 memory. All configurations associated with this DST_BUF[a] are valid. 1: Channel is disabled for SL2 data transfer (because the.." "0: (Default,1: Channel is disabled for SL2 data transfer" newline bitfld.long 0x0 29. "YUV422_INTLV_ORDER,YUV422 Interleaving Order Selection 0: UYVY 1: YUYV Only Applicable if this output channel is YUV422 output capable LUMA channel. Otherwise setting has no effect." "0: UYVY,1: YUYV Only Applicable if this output channel is.." newline bitfld.long 0x0 28. "YUV422_OUT_EN,YUV422 Interleaved Output Merge Enable 0: Disable 1: Enable When enabled this channel interleaves data from the associated chroma data output channel to output YUV422 interleaved data to the SL2 memory. Only Applicable if this output.." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 10. "ENABLE_SIGNED_ACCLERATOR_DATA,Specify the acclerator data to be signed or unsigned 0: Unsigned data (By default) 1: Signed Data" "0: Unsigned data,1: Signed Data" newline bitfld.long 0x0 9. "ENABLE_OUTPUT_PIXEL_ROUNDING,enable acclerator pixel output rounding 0: Disable rounding logic 1: Enable rounding logic" "0: Disable rounding logic,1: Enable rounding logic" newline bitfld.long 0x0 8. "CHAN_THREAD_MAP,Output Channel - channel mapping per each thread 0: Mapped to channel-0 1: Mapped to channel-1" "0: Mapped to channel-0,1: Mapped to channel-1" newline bitfld.long 0x0 7. "THREAD_MAP,Output Channel - thread mapping 0: Mapped to Thread-0 1: Mapped to Thread-1" "0: Mapped to Thread-0,1: Mapped to Thread-1" newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Output Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Output Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Output pixel container size must be same or larger than output pixel width. If yuv422_out_en is set pix_fmt_cntrsz must be 0." "0: 8-bit,1: 12-bit,2: 16-bit,3: reserved Output pixel container size must be.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Output Pixel Width Sel 0: 8-bit 1: 12-bit 2: reserved 3: 16-bit The width defines the bit-depth of the pixel data to be stored in the pixel container." "0: 8-bit,1: 12-bit,2: reserved,3: 16-bit The width defines the bit-depth of the.." line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_buf_attr0,The DST[a]_BUF_ATTR0 register configures the attributes of the output SL2 buffer [a]." hexmask.long.word 0x4 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0x4 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0x4 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" group.long 0x5C++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_MSC__CFG_VP__LSE__CFG_VP__REGS_buf_ba,The DST[a]_BUF_BA register configures the base address of the output SL2 circular buffer [a]." bitfld.long 0x0 31. "ENABLE,Output Channel Enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline bitfld.long 0x0 30. "SKIP_ODD_LINE_PROC,This bit when set skips odd line processing" "0,1" newline bitfld.long 0x0 29. "SKIP_ALTERNATE_LINE_PROC,This bit when enabled skips processing of lines. This is used in YUV420 MSC scalar processing Y and UV pixels on the single HTS thread" "0,1" newline hexmask.long.tbyte 0x0 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x0 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_CFG_GLBCE" base ad:0x2C103800 group.long 0x0++0xAF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_CFG,GLBCE Configuration Registers" bitfld.long 0x0 0. "SWRST,Reserved for this version for HW. This bit initiate software reset process" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_MODE,GLBCE Mode Control register" bitfld.long 0x4 0. "OST,One shot mode or continuous mode One shot mode turns itself off after each frame Note that this bit only controls the enable signal and does not revert the statistics to the default status To revert the cache content to the default status you.." "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_CONTROL0,GLBCE Control Register 0 (control_0)" rbitfld.long 0x8 4. "CCTL,Color Control [CCTL] - Enabling this processing will result in more accurate colors processing The color correction algorithm is required on gamma corrected sources It reduces the saturation in dark areas when they are being amplified and saturates.." "0,1" newline bitfld.long 0x8 3. "MB,Max Bayer Type- Use this bit to select the algorithm used for calculating intensity 0b: Algorithm 1 1b: Algorithm 2 [Recommended]" "0,1" newline rbitfld.long 0x8 1.--2. "RESERVED0,These bits are read only Controls the storage of image sensor RAW data in memory This bit is loaded with the timing of the internal VD signal: it becomes active starting at the lead of the VD signal that comes after 1 is written in this bit" "0,1,2,3" newline bitfld.long 0x8 0. "ONOFF,GLBCE On/Off - This bit turns GLBCE processing ON and OFF When GLBCE is OFF the video data passes to the output without any changes Disabling GLBCE using this bit is equivalent to setting the Strength parameter to 0 Many internal modules run in.." "0,1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_CONTROL1,Connected to iridix_control1 parameter in GLBCE Core" hexmask.long.byte 0xC 0.--7. 1. "CONTROL1,Connected Control1 port" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_BLACK_LEVEL,Black Level Register (black_level)" hexmask.long.word 0x10 0.--15. 1. "VAL,The value stored in Black Level Port will be used as zero level for GLBCE processing in all unsigned data channels Data below Black level will not be processed and stay unchanged" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WHITE_LEVEL,White Level Register (white_level)" hexmask.long.word 0x14 0.--15. 1. "VAL,The value stored in White Level Port will be used as white level for GLBCE processing in all unsigned data channels Data above White level will not be processed and stay unchanged" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_VARIANCE,Affects the sensitivity of the transform to different areas of the image. and can be increased in order to emphasize small regions (e.g. faces)." hexmask.long.byte 0x18 4.--7. 1. "VARIANCEINTENSITY,Variance Intensity - Sets the degree of sensitivity in the luminance domain Maximum Variance is 0xF and minimum Variance is 0x0" newline hexmask.long.byte 0x18 0.--3. 1. "VARIANCESPACE,Variance Space - Sets the degree of spatial sensitivity of the algorithm As this parameter is made smaller the algorithm focuses on smaller regions within the image Maximum Variance is 0xF and minimum Variance is 0x0" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LIMIT_AMPL,The parameters" hexmask.long.byte 0x1C 4.--7. 1. "BRIGHTAMPLIFICATIONLIMIT,Bright amplification limit - The resultant tone curve cannot be lower than bright amplification limit line controlled by the bright amplification limit parameter See Chapter 4 of the spec document for more explanation Maximum.." newline hexmask.long.byte 0x1C 0.--3. 1. "DARKAMPLIFICATIONLIMIT,Dark amplification limit - The resultant tone curve cannot be higher than dark amplification limit line controlled by the dark amplification limit parameter See Chapter 4 of the spec for more explanation Maximum limit is 0xF when.." line.long 0x20 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_DITHER,Dithering Register (dither)" bitfld.long 0x20 0.--2. "DITHER,000b: No dithering 001b: One least significant bit of the output signal is dithered 010b: Two bits are dithered 011b: Three bits are dithered 100b: Four bits are dithered All other values : Four bits are dithered" "0,1,2,3,4,5,6,7" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_SLOPE_MAX,Slope Max Limit Register (slope_max)" hexmask.long.byte 0x24 0.--7. 1. "SLOPEMAXLIMIT,Slope Max Limit - Slope Max Limit is used to restrict the slope of the tone-curve generated by GLBCE When Slope Max Limit parameter is set to 0xFF the tone curve slope generated by GLBCE is not limited [maximum slope 15] When this value.." line.long 0x28 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_SLOPE_MIN,Slope Min Limit Register (slope_min)" hexmask.long.byte 0x28 0.--7. 1. "SLOPEMINLIMIT,Slope Min Limit - Slope Min Limit is used to restrict the slope of the tone-curve generated by GLBCE When Slope Min Limit parameter is set to 0x00 the tone curve slope generated by GLBCE is not limited When this value is set to FF GLBCE.." line.long 0x2C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_00,Asymmetry Function LUT" hexmask.long.word 0x2C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x30 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_01,Asymmetry Function LUT" hexmask.long.word 0x30 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_02,Asymmetry Function LUT" hexmask.long.word 0x34 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_03,Asymmetry Function LUT" hexmask.long.word 0x38 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_04,Asymmetry Function LUT" hexmask.long.word 0x3C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x40 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_05,Asymmetry Function LUT" hexmask.long.word 0x40 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x44 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_06,Asymmetry Function LUT" hexmask.long.word 0x44 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x48 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_07,Asymmetry Function LUT" hexmask.long.word 0x48 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x4C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_08,Asymmetry Function LUT" hexmask.long.word 0x4C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x50 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_09,Asymmetry Function LUT" hexmask.long.word 0x50 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x54 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_10,Asymmetry Function LUT" hexmask.long.word 0x54 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x58 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_11,Asymmetry Function LUT" hexmask.long.word 0x58 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x5C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_12,Asymmetry Function LUT" hexmask.long.word 0x5C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x60 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_13,Asymmetry Function LUT" hexmask.long.word 0x60 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x64 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_14,Asymmetry Function LUT" hexmask.long.word 0x64 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x68 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_15,Asymmetry Function LUT" hexmask.long.word 0x68 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x6C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_16,Asymmetry Function LUT" hexmask.long.word 0x6C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x70 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_17,Asymmetry Function LUT" hexmask.long.word 0x70 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x74 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_18,Asymmetry Function LUT" hexmask.long.word 0x74 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x78 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_19,Asymmetry Function LUT" hexmask.long.word 0x78 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x7C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_20,Asymmetry Function LUT" hexmask.long.word 0x7C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x80 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_21,Asymmetry Function LUT" hexmask.long.word 0x80 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x84 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_22,Asymmetry Function LUT" hexmask.long.word 0x84 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x88 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_23,Asymmetry Function LUT" hexmask.long.word 0x88 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x8C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_24,Asymmetry Function LUT" hexmask.long.word 0x8C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x90 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_25,Asymmetry Function LUT" hexmask.long.word 0x90 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x94 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_26,Asymmetry Function LUT" hexmask.long.word 0x94 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x98 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_27,Asymmetry Function LUT" hexmask.long.word 0x98 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0x9C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_28,Asymmetry Function LUT" hexmask.long.word 0x9C 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0xA0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_29,Asymmetry Function LUT" hexmask.long.word 0xA0 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0xA4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_30,Asymmetry Function LUT" hexmask.long.word 0xA4 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0xA8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_31,Asymmetry Function LUT" hexmask.long.word 0xA8 0.--15. 1. "VAL,Asymmetry LUT Entry" line.long 0xAC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_LUT_FI_32,Asymmetry Function LUT" hexmask.long.word 0xAC 0.--15. 1. "VAL,Asymmetry LUT Entry" rgroup.long 0xB0++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FORMAT_CONTROL_REG0,Data format port specifies the input data format so that the GLBCE core can process the different input data formats. This register is reserved for.." bitfld.long 0x0 0.--1. "DATAFORMAT,This value is reserved The color format is always RGB and this value should be fixed 0" "0,1,2,3" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FORMAT_CONTROL_REG1,Control Reg1" bitfld.long 0x4 7. "AUTOSIZE,This value is read only. GLBCE in this HW version never use Auto-size mode" "0,1" newline bitfld.long 0x4 6. "AUTOPOS,This value is read only. GLBCE in this HW version always runs in Auto Position mode" "0,1" newline bitfld.long 0x4 4.--5. "FCMODE,Field Correction Mode" "0,1,2,3" newline bitfld.long 0x4 1. "VSPOL,Vertical Sync Polarity This value is read only The SWITCH block always convert the polarity to rising edge active" "0,1" newline bitfld.long 0x4 0. "HSPOL,Horizontal Sync Polarity This value is read only The SWITCH block always convert the polarity to rising edge active" "0,1" group.long 0xB8++0x623 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FRAME_WIDTH,Frame Width is the number of pixels in an active line. This port is used only in non-automatic mode." hexmask.long.word 0x0 0.--15. 1. "VAL,Frame Width. minimum of 480" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FRAME_HEIGHT,Frame Height is the number of active lines in one field." hexmask.long.word 0x4 0.--15. 1. "VAL,Frame Height. minimum of 240" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_STRENGTH_IR,Strength (Strength of GLBCE) - This Port sets processing Strength. Minimum value is 0. maximum is 255." hexmask.long.byte 0x8 0.--7. 1. "VAL,0x00: Video data will not be processed at all and will go to the output unchanged 0xFF: Maximum strength" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_PERCEPT_EN,Enable for GLBCE Perceptual LUT function" bitfld.long 0xC 1. "FWD_EN,Forward Perceptual LUT enable" "0,1" newline bitfld.long 0xC 0. "REV_EN,Reverse Perceptual LUT enable[" "0,1" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_00,Reverse Perceptual LUT" hexmask.long.word 0x10 0.--15. 1. "VAL,LUT Value" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_01,Reverse Perceptual LUT" hexmask.long.word 0x14 0.--15. 1. "VAL,LUT Value" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_02,Reverse Perceptual LUT" hexmask.long.word 0x18 0.--15. 1. "VAL,LUT Value" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_03,Reverse Perceptual LUT" hexmask.long.word 0x1C 0.--15. 1. "VAL,LUT Value" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_04,Reverse Perceptual LUT" hexmask.long.word 0x20 0.--15. 1. "VAL,LUT Value" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_05,Reverse Perceptual LUT" hexmask.long.word 0x24 0.--15. 1. "VAL,LUT Value" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_06,Reverse Perceptual LUT" hexmask.long.word 0x28 0.--15. 1. "VAL,LUT Value" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_07,Reverse Perceptual LUT" hexmask.long.word 0x2C 0.--15. 1. "VAL,LUT Value" line.long 0x30 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_08,Reverse Perceptual LUT" hexmask.long.word 0x30 0.--15. 1. "VAL,LUT Value" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_09,Reverse Perceptual LUT" hexmask.long.word 0x34 0.--15. 1. "VAL,LUT Value" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_10,Reverse Perceptual LUT" hexmask.long.word 0x38 0.--15. 1. "VAL,LUT Value" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_11,Reverse Perceptual LUT" hexmask.long.word 0x3C 0.--15. 1. "VAL,LUT Value" line.long 0x40 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_12,Reverse Perceptual LUT" hexmask.long.word 0x40 0.--15. 1. "VAL,LUT Value" line.long 0x44 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_13,Reverse Perceptual LUT" hexmask.long.word 0x44 0.--15. 1. "VAL,LUT Value" line.long 0x48 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_14,Reverse Perceptual LUT" hexmask.long.word 0x48 0.--15. 1. "VAL,LUT Value" line.long 0x4C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_15,Reverse Perceptual LUT" hexmask.long.word 0x4C 0.--15. 1. "VAL,LUT Value" line.long 0x50 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_16,Reverse Perceptual LUT" hexmask.long.word 0x50 0.--15. 1. "VAL,LUT Value" line.long 0x54 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_17,Reverse Perceptual LUT" hexmask.long.word 0x54 0.--15. 1. "VAL,LUT Value" line.long 0x58 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_18,Reverse Perceptual LUT" hexmask.long.word 0x58 0.--15. 1. "VAL,LUT Value" line.long 0x5C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_19,Reverse Perceptual LUT" hexmask.long.word 0x5C 0.--15. 1. "VAL,LUT Value" line.long 0x60 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_20,Reverse Perceptual LUT" hexmask.long.word 0x60 0.--15. 1. "VAL,LUT Value" line.long 0x64 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_21,Reverse Perceptual LUT" hexmask.long.word 0x64 0.--15. 1. "VAL,LUT Value" line.long 0x68 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_22,Reverse Perceptual LUT" hexmask.long.word 0x68 0.--15. 1. "VAL,LUT Value" line.long 0x6C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_23,Reverse Perceptual LUT" hexmask.long.word 0x6C 0.--15. 1. "VAL,LUT Value" line.long 0x70 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_24,Reverse Perceptual LUT" hexmask.long.word 0x70 0.--15. 1. "VAL,LUT Value" line.long 0x74 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_25,Reverse Perceptual LUT" hexmask.long.word 0x74 0.--15. 1. "VAL,LUT Value" line.long 0x78 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_26,Reverse Perceptual LUT" hexmask.long.word 0x78 0.--15. 1. "VAL,LUT Value" line.long 0x7C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_27,Reverse Perceptual LUT" hexmask.long.word 0x7C 0.--15. 1. "VAL,LUT Value" line.long 0x80 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_28,Reverse Perceptual LUT" hexmask.long.word 0x80 0.--15. 1. "VAL,LUT Value" line.long 0x84 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_29,Reverse Perceptual LUT" hexmask.long.word 0x84 0.--15. 1. "VAL,LUT Value" line.long 0x88 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_30,Reverse Perceptual LUT" hexmask.long.word 0x88 0.--15. 1. "VAL,LUT Value" line.long 0x8C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_31,Reverse Perceptual LUT" hexmask.long.word 0x8C 0.--15. 1. "VAL,LUT Value" line.long 0x90 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_32,Reverse Perceptual LUT" hexmask.long.word 0x90 0.--15. 1. "VAL,LUT Value" line.long 0x94 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_33,Reverse Perceptual LUT" hexmask.long.word 0x94 0.--15. 1. "VAL,LUT Value" line.long 0x98 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_34,Reverse Perceptual LUT" hexmask.long.word 0x98 0.--15. 1. "VAL,LUT Value" line.long 0x9C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_35,Reverse Perceptual LUT" hexmask.long.word 0x9C 0.--15. 1. "VAL,LUT Value" line.long 0xA0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_36,Reverse Perceptual LUT" hexmask.long.word 0xA0 0.--15. 1. "VAL,LUT Value" line.long 0xA4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_37,Reverse Perceptual LUT" hexmask.long.word 0xA4 0.--15. 1. "VAL,LUT Value" line.long 0xA8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_38,Reverse Perceptual LUT" hexmask.long.word 0xA8 0.--15. 1. "VAL,LUT Value" line.long 0xAC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_39,Reverse Perceptual LUT" hexmask.long.word 0xAC 0.--15. 1. "VAL,LUT Value" line.long 0xB0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_40,Reverse Perceptual LUT" hexmask.long.word 0xB0 0.--15. 1. "VAL,LUT Value" line.long 0xB4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_41,Reverse Perceptual LUT" hexmask.long.word 0xB4 0.--15. 1. "VAL,LUT Value" line.long 0xB8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_42,Reverse Perceptual LUT" hexmask.long.word 0xB8 0.--15. 1. "VAL,LUT Value" line.long 0xBC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_43,Reverse Perceptual LUT" hexmask.long.word 0xBC 0.--15. 1. "VAL,LUT Value" line.long 0xC0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_44,Reverse Perceptual LUT" hexmask.long.word 0xC0 0.--15. 1. "VAL,LUT Value" line.long 0xC4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_45,Reverse Perceptual LUT" hexmask.long.word 0xC4 0.--15. 1. "VAL,LUT Value" line.long 0xC8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_46,Reverse Perceptual LUT" hexmask.long.word 0xC8 0.--15. 1. "VAL,LUT Value" line.long 0xCC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_47,Reverse Perceptual LUT" hexmask.long.word 0xCC 0.--15. 1. "VAL,LUT Value" line.long 0xD0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_48,Reverse Perceptual LUT" hexmask.long.word 0xD0 0.--15. 1. "VAL,LUT Value" line.long 0xD4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_49,Reverse Perceptual LUT" hexmask.long.word 0xD4 0.--15. 1. "VAL,LUT Value" line.long 0xD8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_50,Reverse Perceptual LUT" hexmask.long.word 0xD8 0.--15. 1. "VAL,LUT Value" line.long 0xDC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_51,Reverse Perceptual LUT" hexmask.long.word 0xDC 0.--15. 1. "VAL,LUT Value" line.long 0xE0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_52,Reverse Perceptual LUT" hexmask.long.word 0xE0 0.--15. 1. "VAL,LUT Value" line.long 0xE4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_53,Reverse Perceptual LUT" hexmask.long.word 0xE4 0.--15. 1. "VAL,LUT Value" line.long 0xE8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_54,Reverse Perceptual LUT" hexmask.long.word 0xE8 0.--15. 1. "VAL,LUT Value" line.long 0xEC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_55,Reverse Perceptual LUT" hexmask.long.word 0xEC 0.--15. 1. "VAL,LUT Value" line.long 0xF0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_56,Reverse Perceptual LUT" hexmask.long.word 0xF0 0.--15. 1. "VAL,LUT Value" line.long 0xF4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_57,Reverse Perceptual LUT" hexmask.long.word 0xF4 0.--15. 1. "VAL,LUT Value" line.long 0xF8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_58,Reverse Perceptual LUT" hexmask.long.word 0xF8 0.--15. 1. "VAL,LUT Value" line.long 0xFC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_59,Reverse Perceptual LUT" hexmask.long.word 0xFC 0.--15. 1. "VAL,LUT Value" line.long 0x100 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_60,Reverse Perceptual LUT" hexmask.long.word 0x100 0.--15. 1. "VAL,LUT Value" line.long 0x104 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_61,Reverse Perceptual LUT" hexmask.long.word 0x104 0.--15. 1. "VAL,LUT Value" line.long 0x108 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_62,Reverse Perceptual LUT" hexmask.long.word 0x108 0.--15. 1. "VAL,LUT Value" line.long 0x10C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_63,Reverse Perceptual LUT" hexmask.long.word 0x10C 0.--15. 1. "VAL,LUT Value" line.long 0x110 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_REV_PERCEPT_LUT_64,Reverse Perceptual LUT" hexmask.long.word 0x110 0.--15. 1. "VAL,LUT Value" line.long 0x114 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_00,Forward Perception LUT" hexmask.long.word 0x114 0.--15. 1. "VAL,LUT Value" line.long 0x118 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_01,Forward Perception LUT" hexmask.long.word 0x118 0.--15. 1. "VAL,LUT Value" line.long 0x11C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_02,Forward Perception LUT" hexmask.long.word 0x11C 0.--15. 1. "VAL,LUT Value" line.long 0x120 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_03,Forward Perception LUT" hexmask.long.word 0x120 0.--15. 1. "VAL,LUT Value" line.long 0x124 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_04,Forward Perception LUT" hexmask.long.word 0x124 0.--15. 1. "VAL,LUT Value" line.long 0x128 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_05,Forward Perception LUT" hexmask.long.word 0x128 0.--15. 1. "VAL,LUT Value" line.long 0x12C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_06,Forward Perception LUT" hexmask.long.word 0x12C 0.--15. 1. "VAL,LUT Value" line.long 0x130 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_07,Forward Perception LUT" hexmask.long.word 0x130 0.--15. 1. "VAL,LUT Value" line.long 0x134 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_08,Forward Perception LUT" hexmask.long.word 0x134 0.--15. 1. "VAL,LUT Value" line.long 0x138 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_09,Forward Perception LUT" hexmask.long.word 0x138 0.--15. 1. "VAL,LUT Value" line.long 0x13C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_10,Forward Perception LUT" hexmask.long.word 0x13C 0.--15. 1. "VAL,LUT Value" line.long 0x140 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_11,Forward Perception LUT" hexmask.long.word 0x140 0.--15. 1. "VAL,LUT Value" line.long 0x144 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_12,Forward Perception LUT" hexmask.long.word 0x144 0.--15. 1. "VAL,LUT Value" line.long 0x148 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_13,Forward Perception LUT" hexmask.long.word 0x148 0.--15. 1. "VAL,LUT Value" line.long 0x14C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_14,Forward Perception LUT" hexmask.long.word 0x14C 0.--15. 1. "VAL,LUT Value" line.long 0x150 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_15,Forward Perception LUT" hexmask.long.word 0x150 0.--15. 1. "VAL,LUT Value" line.long 0x154 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_16,Forward Perception LUT" hexmask.long.word 0x154 0.--15. 1. "VAL,LUT Value" line.long 0x158 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_17,Forward Perception LUT" hexmask.long.word 0x158 0.--15. 1. "VAL,LUT Value" line.long 0x15C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_18,Forward Perception LUT" hexmask.long.word 0x15C 0.--15. 1. "VAL,LUT Value" line.long 0x160 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_19,Forward Perception LUT" hexmask.long.word 0x160 0.--15. 1. "VAL,LUT Value" line.long 0x164 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_20,Forward Perception LUT" hexmask.long.word 0x164 0.--15. 1. "VAL,LUT Value" line.long 0x168 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_21,Forward Perception LUT" hexmask.long.word 0x168 0.--15. 1. "VAL,LUT Value" line.long 0x16C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_22,Forward Perception LUT" hexmask.long.word 0x16C 0.--15. 1. "VAL,LUT Value" line.long 0x170 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_23,Forward Perception LUT" hexmask.long.word 0x170 0.--15. 1. "VAL,LUT Value" line.long 0x174 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_24,Forward Perception LUT" hexmask.long.word 0x174 0.--15. 1. "VAL,LUT Value" line.long 0x178 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_25,Forward Perception LUT" hexmask.long.word 0x178 0.--15. 1. "VAL,LUT Value" line.long 0x17C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_26,Forward Perception LUT" hexmask.long.word 0x17C 0.--15. 1. "VAL,LUT Value" line.long 0x180 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_27,Forward Perception LUT" hexmask.long.word 0x180 0.--15. 1. "VAL,LUT Value" line.long 0x184 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_28,Forward Perception LUT" hexmask.long.word 0x184 0.--15. 1. "VAL,LUT Value" line.long 0x188 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_29,Forward Perception LUT" hexmask.long.word 0x188 0.--15. 1. "VAL,LUT Value" line.long 0x18C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_30,Forward Perception LUT" hexmask.long.word 0x18C 0.--15. 1. "VAL,LUT Value" line.long 0x190 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_31,Forward Perception LUT" hexmask.long.word 0x190 0.--15. 1. "VAL,LUT Value" line.long 0x194 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_32,Forward Perception LUT" hexmask.long.word 0x194 0.--15. 1. "VAL,LUT Value" line.long 0x198 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_33,Forward Perception LUT" hexmask.long.word 0x198 0.--15. 1. "VAL,LUT Value" line.long 0x19C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_34,Forward Perception LUT" hexmask.long.word 0x19C 0.--15. 1. "VAL,LUT Value" line.long 0x1A0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_35,Forward Perception LUT" hexmask.long.word 0x1A0 0.--15. 1. "VAL,LUT Value" line.long 0x1A4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_36,Forward Perception LUT" hexmask.long.word 0x1A4 0.--15. 1. "VAL,LUT Value" line.long 0x1A8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_37,Forward Perception LUT" hexmask.long.word 0x1A8 0.--15. 1. "VAL,LUT Value" line.long 0x1AC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_38,Forward Perception LUT" hexmask.long.word 0x1AC 0.--15. 1. "VAL,LUT Value" line.long 0x1B0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_39,Forward Perception LUT" hexmask.long.word 0x1B0 0.--15. 1. "VAL,LUT Value" line.long 0x1B4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_40,Forward Perception LUT" hexmask.long.word 0x1B4 0.--15. 1. "VAL,LUT Value" line.long 0x1B8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_41,Forward Perception LUT" hexmask.long.word 0x1B8 0.--15. 1. "VAL,LUT Value" line.long 0x1BC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_42,Forward Perception LUT" hexmask.long.word 0x1BC 0.--15. 1. "VAL,LUT Value" line.long 0x1C0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_43,Forward Perception LUT" hexmask.long.word 0x1C0 0.--15. 1. "VAL,LUT Value" line.long 0x1C4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_44,Forward Perception LUT" hexmask.long.word 0x1C4 0.--15. 1. "VAL,LUT Value" line.long 0x1C8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_45,Forward Perception LUT" hexmask.long.word 0x1C8 0.--15. 1. "VAL,LUT Value" line.long 0x1CC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_46,Forward Perception LUT" hexmask.long.word 0x1CC 0.--15. 1. "VAL,LUT Value" line.long 0x1D0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_47,Forward Perception LUT" hexmask.long.word 0x1D0 0.--15. 1. "VAL,LUT Value" line.long 0x1D4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_48,Forward Perception LUT" hexmask.long.word 0x1D4 0.--15. 1. "VAL,LUT Value" line.long 0x1D8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_49,Forward Perception LUT" hexmask.long.word 0x1D8 0.--15. 1. "VAL,LUT Value" line.long 0x1DC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_50,Forward Perception LUT" hexmask.long.word 0x1DC 0.--15. 1. "VAL,LUT Value" line.long 0x1E0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_51,Forward Perception LUT" hexmask.long.word 0x1E0 0.--15. 1. "VAL,LUT Value" line.long 0x1E4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_52,Forward Perception LUT" hexmask.long.word 0x1E4 0.--15. 1. "VAL,LUT Value" line.long 0x1E8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_53,Forward Perception LUT" hexmask.long.word 0x1E8 0.--15. 1. "VAL,LUT Value" line.long 0x1EC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_54,Forward Perception LUT" hexmask.long.word 0x1EC 0.--15. 1. "VAL,LUT Value" line.long 0x1F0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_55,Forward Perception LUT" hexmask.long.word 0x1F0 0.--15. 1. "VAL,LUT Value" line.long 0x1F4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_56,Forward Perception LUT" hexmask.long.word 0x1F4 0.--15. 1. "VAL,LUT Value" line.long 0x1F8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_57,Forward Perception LUT" hexmask.long.word 0x1F8 0.--15. 1. "VAL,LUT Value" line.long 0x1FC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_58,Forward Perception LUT" hexmask.long.word 0x1FC 0.--15. 1. "VAL,LUT Value" line.long 0x200 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_59,Forward Perception LUT" hexmask.long.word 0x200 0.--15. 1. "VAL,LUT Value" line.long 0x204 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_60,Forward Perception LUT" hexmask.long.word 0x204 0.--15. 1. "VAL,LUT Value" line.long 0x208 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_61,Forward Perception LUT" hexmask.long.word 0x208 0.--15. 1. "VAL,LUT Value" line.long 0x20C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_62,Forward Perception LUT" hexmask.long.word 0x20C 0.--15. 1. "VAL,LUT Value" line.long 0x210 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_63,Forward Perception LUT" hexmask.long.word 0x210 0.--15. 1. "VAL,LUT Value" line.long 0x214 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_FWD_PERCEPT_LUT_64,Forward Perception LUT" hexmask.long.word 0x214 0.--15. 1. "VAL,LUT Value" line.long 0x218 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_EN,WDR Gamma LUT Enable" bitfld.long 0x218 0. "EN,Frontend WDR LUT enable" "0,1" line.long 0x21C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_00,Frontend WDR LUT" hexmask.long.word 0x21C 0.--15. 1. "VAL,LUT Value" line.long 0x220 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_01,Frontend WDR LUT" hexmask.long.word 0x220 0.--15. 1. "VAL,LUT Value" line.long 0x224 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_02,Frontend WDR LUT" hexmask.long.word 0x224 0.--15. 1. "VAL,LUT Value" line.long 0x228 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_03,Frontend WDR LUT" hexmask.long.word 0x228 0.--15. 1. "VAL,LUT Value" line.long 0x22C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_04,Frontend WDR LUT" hexmask.long.word 0x22C 0.--15. 1. "VAL,LUT Value" line.long 0x230 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_05,Frontend WDR LUT" hexmask.long.word 0x230 0.--15. 1. "VAL,LUT Value" line.long 0x234 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_06,Frontend WDR LUT" hexmask.long.word 0x234 0.--15. 1. "VAL,LUT Value" line.long 0x238 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_07,Frontend WDR LUT" hexmask.long.word 0x238 0.--15. 1. "VAL,LUT Value" line.long 0x23C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_08,Frontend WDR LUT" hexmask.long.word 0x23C 0.--15. 1. "VAL,LUT Value" line.long 0x240 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_09,Frontend WDR LUT" hexmask.long.word 0x240 0.--15. 1. "VAL,LUT Value" line.long 0x244 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_10,Frontend WDR LUT" hexmask.long.word 0x244 0.--15. 1. "VAL,LUT Value" line.long 0x248 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_11,Frontend WDR LUT" hexmask.long.word 0x248 0.--15. 1. "VAL,LUT Value" line.long 0x24C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_12,Frontend WDR LUT" hexmask.long.word 0x24C 0.--15. 1. "VAL,LUT Value" line.long 0x250 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_13,Frontend WDR LUT" hexmask.long.word 0x250 0.--15. 1. "VAL,LUT Value" line.long 0x254 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_14,Frontend WDR LUT" hexmask.long.word 0x254 0.--15. 1. "VAL,LUT Value" line.long 0x258 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_15,Frontend WDR LUT" hexmask.long.word 0x258 0.--15. 1. "VAL,LUT Value" line.long 0x25C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_16,Frontend WDR LUT" hexmask.long.word 0x25C 0.--15. 1. "VAL,LUT Value" line.long 0x260 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_17,Frontend WDR LUT" hexmask.long.word 0x260 0.--15. 1. "VAL,LUT Value" line.long 0x264 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_18,Frontend WDR LUT" hexmask.long.word 0x264 0.--15. 1. "VAL,LUT Value" line.long 0x268 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_19,Frontend WDR LUT" hexmask.long.word 0x268 0.--15. 1. "VAL,LUT Value" line.long 0x26C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_20,Frontend WDR LUT" hexmask.long.word 0x26C 0.--15. 1. "VAL,LUT Value" line.long 0x270 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_21,Frontend WDR LUT" hexmask.long.word 0x270 0.--15. 1. "VAL,LUT Value" line.long 0x274 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_22,Frontend WDR LUT" hexmask.long.word 0x274 0.--15. 1. "VAL,LUT Value" line.long 0x278 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_23,Frontend WDR LUT" hexmask.long.word 0x278 0.--15. 1. "VAL,LUT Value" line.long 0x27C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_24,Frontend WDR LUT" hexmask.long.word 0x27C 0.--15. 1. "VAL,LUT Value" line.long 0x280 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_25,Frontend WDR LUT" hexmask.long.word 0x280 0.--15. 1. "VAL,LUT Value" line.long 0x284 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_26,Frontend WDR LUT" hexmask.long.word 0x284 0.--15. 1. "VAL,LUT Value" line.long 0x288 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_27,Frontend WDR LUT" hexmask.long.word 0x288 0.--15. 1. "VAL,LUT Value" line.long 0x28C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_28,Frontend WDR LUT" hexmask.long.word 0x28C 0.--15. 1. "VAL,LUT Value" line.long 0x290 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_29,Frontend WDR LUT" hexmask.long.word 0x290 0.--15. 1. "VAL,LUT Value" line.long 0x294 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_30,Frontend WDR LUT" hexmask.long.word 0x294 0.--15. 1. "VAL,LUT Value" line.long 0x298 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_31,Frontend WDR LUT" hexmask.long.word 0x298 0.--15. 1. "VAL,LUT Value" line.long 0x29C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_32,Frontend WDR LUT" hexmask.long.word 0x29C 0.--15. 1. "VAL,LUT Value" line.long 0x2A0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_33,Frontend WDR LUT" hexmask.long.word 0x2A0 0.--15. 1. "VAL,LUT Value" line.long 0x2A4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_34,Frontend WDR LUT" hexmask.long.word 0x2A4 0.--15. 1. "VAL,LUT Value" line.long 0x2A8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_35,Frontend WDR LUT" hexmask.long.word 0x2A8 0.--15. 1. "VAL,LUT Value" line.long 0x2AC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_36,Frontend WDR LUT" hexmask.long.word 0x2AC 0.--15. 1. "VAL,LUT Value" line.long 0x2B0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_37,Frontend WDR LUT" hexmask.long.word 0x2B0 0.--15. 1. "VAL,LUT Value" line.long 0x2B4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_38,Frontend WDR LUT" hexmask.long.word 0x2B4 0.--15. 1. "VAL,LUT Value" line.long 0x2B8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_39,Frontend WDR LUT" hexmask.long.word 0x2B8 0.--15. 1. "VAL,LUT Value" line.long 0x2BC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_40,Frontend WDR LUT" hexmask.long.word 0x2BC 0.--15. 1. "VAL,LUT Value" line.long 0x2C0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_41,Frontend WDR LUT" hexmask.long.word 0x2C0 0.--15. 1. "VAL,LUT Value" line.long 0x2C4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_42,Frontend WDR LUT" hexmask.long.word 0x2C4 0.--15. 1. "VAL,LUT Value" line.long 0x2C8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_43,Frontend WDR LUT" hexmask.long.word 0x2C8 0.--15. 1. "VAL,LUT Value" line.long 0x2CC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_44,Frontend WDR LUT" hexmask.long.word 0x2CC 0.--15. 1. "VAL,LUT Value" line.long 0x2D0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_45,Frontend WDR LUT" hexmask.long.word 0x2D0 0.--15. 1. "VAL,LUT Value" line.long 0x2D4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_46,Frontend WDR LUT" hexmask.long.word 0x2D4 0.--15. 1. "VAL,LUT Value" line.long 0x2D8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_47,Frontend WDR LUT" hexmask.long.word 0x2D8 0.--15. 1. "VAL,LUT Value" line.long 0x2DC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_48,Frontend WDR LUT" hexmask.long.word 0x2DC 0.--15. 1. "VAL,LUT Value" line.long 0x2E0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_49,Frontend WDR LUT" hexmask.long.word 0x2E0 0.--15. 1. "VAL,LUT Value" line.long 0x2E4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_50,Frontend WDR LUT" hexmask.long.word 0x2E4 0.--15. 1. "VAL,LUT Value" line.long 0x2E8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_51,Frontend WDR LUT" hexmask.long.word 0x2E8 0.--15. 1. "VAL,LUT Value" line.long 0x2EC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_52,Frontend WDR LUT" hexmask.long.word 0x2EC 0.--15. 1. "VAL,LUT Value" line.long 0x2F0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_53,Frontend WDR LUT" hexmask.long.word 0x2F0 0.--15. 1. "VAL,LUT Value" line.long 0x2F4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_54,Frontend WDR LUT" hexmask.long.word 0x2F4 0.--15. 1. "VAL,LUT Value" line.long 0x2F8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_55,Frontend WDR LUT" hexmask.long.word 0x2F8 0.--15. 1. "VAL,LUT Value" line.long 0x2FC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_56,Frontend WDR LUT" hexmask.long.word 0x2FC 0.--15. 1. "VAL,LUT Value" line.long 0x300 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_57,Frontend WDR LUT" hexmask.long.word 0x300 0.--15. 1. "VAL,LUT Value" line.long 0x304 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_58,Frontend WDR LUT" hexmask.long.word 0x304 0.--15. 1. "VAL,LUT Value" line.long 0x308 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_59,Frontend WDR LUT" hexmask.long.word 0x308 0.--15. 1. "VAL,LUT Value" line.long 0x30C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_60,Frontend WDR LUT" hexmask.long.word 0x30C 0.--15. 1. "VAL,LUT Value" line.long 0x310 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_61,Frontend WDR LUT" hexmask.long.word 0x310 0.--15. 1. "VAL,LUT Value" line.long 0x314 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_62,Frontend WDR LUT" hexmask.long.word 0x314 0.--15. 1. "VAL,LUT Value" line.long 0x318 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_63,Frontend WDR LUT" hexmask.long.word 0x318 0.--15. 1. "VAL,LUT Value" line.long 0x31C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_64,Frontend WDR LUT" hexmask.long.word 0x31C 0.--15. 1. "VAL,LUT Value" line.long 0x320 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_65,Frontend WDR LUT" hexmask.long.word 0x320 0.--15. 1. "VAL,LUT Value" line.long 0x324 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_66,Frontend WDR LUT" hexmask.long.word 0x324 0.--15. 1. "VAL,LUT Value" line.long 0x328 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_67,Frontend WDR LUT" hexmask.long.word 0x328 0.--15. 1. "VAL,LUT Value" line.long 0x32C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_68,Frontend WDR LUT" hexmask.long.word 0x32C 0.--15. 1. "VAL,LUT Value" line.long 0x330 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_69,Frontend WDR LUT" hexmask.long.word 0x330 0.--15. 1. "VAL,LUT Value" line.long 0x334 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_70,Frontend WDR LUT" hexmask.long.word 0x334 0.--15. 1. "VAL,LUT Value" line.long 0x338 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_71,Frontend WDR LUT" hexmask.long.word 0x338 0.--15. 1. "VAL,LUT Value" line.long 0x33C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_72,Frontend WDR LUT" hexmask.long.word 0x33C 0.--15. 1. "VAL,LUT Value" line.long 0x340 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_73,Frontend WDR LUT" hexmask.long.word 0x340 0.--15. 1. "VAL,LUT Value" line.long 0x344 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_74,Frontend WDR LUT" hexmask.long.word 0x344 0.--15. 1. "VAL,LUT Value" line.long 0x348 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_75,Frontend WDR LUT" hexmask.long.word 0x348 0.--15. 1. "VAL,LUT Value" line.long 0x34C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_76,Frontend WDR LUT" hexmask.long.word 0x34C 0.--15. 1. "VAL,LUT Value" line.long 0x350 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_77,Frontend WDR LUT" hexmask.long.word 0x350 0.--15. 1. "VAL,LUT Value" line.long 0x354 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_78,Frontend WDR LUT" hexmask.long.word 0x354 0.--15. 1. "VAL,LUT Value" line.long 0x358 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_79,Frontend WDR LUT" hexmask.long.word 0x358 0.--15. 1. "VAL,LUT Value" line.long 0x35C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_80,Frontend WDR LUT" hexmask.long.word 0x35C 0.--15. 1. "VAL,LUT Value" line.long 0x360 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_81,Frontend WDR LUT" hexmask.long.word 0x360 0.--15. 1. "VAL,LUT Value" line.long 0x364 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_82,Frontend WDR LUT" hexmask.long.word 0x364 0.--15. 1. "VAL,LUT Value" line.long 0x368 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_83,Frontend WDR LUT" hexmask.long.word 0x368 0.--15. 1. "VAL,LUT Value" line.long 0x36C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_84,Frontend WDR LUT" hexmask.long.word 0x36C 0.--15. 1. "VAL,LUT Value" line.long 0x370 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_85,Frontend WDR LUT" hexmask.long.word 0x370 0.--15. 1. "VAL,LUT Value" line.long 0x374 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_86,Frontend WDR LUT" hexmask.long.word 0x374 0.--15. 1. "VAL,LUT Value" line.long 0x378 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_87,Frontend WDR LUT" hexmask.long.word 0x378 0.--15. 1. "VAL,LUT Value" line.long 0x37C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_88,Frontend WDR LUT" hexmask.long.word 0x37C 0.--15. 1. "VAL,LUT Value" line.long 0x380 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_89,Frontend WDR LUT" hexmask.long.word 0x380 0.--15. 1. "VAL,LUT Value" line.long 0x384 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_90,Frontend WDR LUT" hexmask.long.word 0x384 0.--15. 1. "VAL,LUT Value" line.long 0x388 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_91,Frontend WDR LUT" hexmask.long.word 0x388 0.--15. 1. "VAL,LUT Value" line.long 0x38C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_92,Frontend WDR LUT" hexmask.long.word 0x38C 0.--15. 1. "VAL,LUT Value" line.long 0x390 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_93,Frontend WDR LUT" hexmask.long.word 0x390 0.--15. 1. "VAL,LUT Value" line.long 0x394 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_94,Frontend WDR LUT" hexmask.long.word 0x394 0.--15. 1. "VAL,LUT Value" line.long 0x398 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_95,Frontend WDR LUT" hexmask.long.word 0x398 0.--15. 1. "VAL,LUT Value" line.long 0x39C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_96,Frontend WDR LUT" hexmask.long.word 0x39C 0.--15. 1. "VAL,LUT Value" line.long 0x3A0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_97,Frontend WDR LUT" hexmask.long.word 0x3A0 0.--15. 1. "VAL,LUT Value" line.long 0x3A4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_98,Frontend WDR LUT" hexmask.long.word 0x3A4 0.--15. 1. "VAL,LUT Value" line.long 0x3A8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_99,Frontend WDR LUT" hexmask.long.word 0x3A8 0.--15. 1. "VAL,LUT Value" line.long 0x3AC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_100,Frontend WDR LUT" hexmask.long.word 0x3AC 0.--15. 1. "VAL,LUT Value" line.long 0x3B0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_101,Frontend WDR LUT" hexmask.long.word 0x3B0 0.--15. 1. "VAL,LUT Value" line.long 0x3B4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_102,Frontend WDR LUT" hexmask.long.word 0x3B4 0.--15. 1. "VAL,LUT Value" line.long 0x3B8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_103,Frontend WDR LUT" hexmask.long.word 0x3B8 0.--15. 1. "VAL,LUT Value" line.long 0x3BC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_104,Frontend WDR LUT" hexmask.long.word 0x3BC 0.--15. 1. "VAL,LUT Value" line.long 0x3C0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_105,Frontend WDR LUT" hexmask.long.word 0x3C0 0.--15. 1. "VAL,LUT Value" line.long 0x3C4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_106,Frontend WDR LUT" hexmask.long.word 0x3C4 0.--15. 1. "VAL,LUT Value" line.long 0x3C8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_107,Frontend WDR LUT" hexmask.long.word 0x3C8 0.--15. 1. "VAL,LUT Value" line.long 0x3CC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_108,Frontend WDR LUT" hexmask.long.word 0x3CC 0.--15. 1. "VAL,LUT Value" line.long 0x3D0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_109,Frontend WDR LUT" hexmask.long.word 0x3D0 0.--15. 1. "VAL,LUT Value" line.long 0x3D4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_110,Frontend WDR LUT" hexmask.long.word 0x3D4 0.--15. 1. "VAL,LUT Value" line.long 0x3D8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_111,Frontend WDR LUT" hexmask.long.word 0x3D8 0.--15. 1. "VAL,LUT Value" line.long 0x3DC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_112,Frontend WDR LUT" hexmask.long.word 0x3DC 0.--15. 1. "VAL,LUT Value" line.long 0x3E0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_113,Frontend WDR LUT" hexmask.long.word 0x3E0 0.--15. 1. "VAL,LUT Value" line.long 0x3E4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_114,Frontend WDR LUT" hexmask.long.word 0x3E4 0.--15. 1. "VAL,LUT Value" line.long 0x3E8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_115,Frontend WDR LUT" hexmask.long.word 0x3E8 0.--15. 1. "VAL,LUT Value" line.long 0x3EC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_116,Frontend WDR LUT" hexmask.long.word 0x3EC 0.--15. 1. "VAL,LUT Value" line.long 0x3F0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_117,Frontend WDR LUT" hexmask.long.word 0x3F0 0.--15. 1. "VAL,LUT Value" line.long 0x3F4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_118,Frontend WDR LUT" hexmask.long.word 0x3F4 0.--15. 1. "VAL,LUT Value" line.long 0x3F8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_119,Frontend WDR LUT" hexmask.long.word 0x3F8 0.--15. 1. "VAL,LUT Value" line.long 0x3FC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_120,Frontend WDR LUT" hexmask.long.word 0x3FC 0.--15. 1. "VAL,LUT Value" line.long 0x400 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_121,Frontend WDR LUT" hexmask.long.word 0x400 0.--15. 1. "VAL,LUT Value" line.long 0x404 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_122,Frontend WDR LUT" hexmask.long.word 0x404 0.--15. 1. "VAL,LUT Value" line.long 0x408 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_123,Frontend WDR LUT" hexmask.long.word 0x408 0.--15. 1. "VAL,LUT Value" line.long 0x40C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_124,Frontend WDR LUT" hexmask.long.word 0x40C 0.--15. 1. "VAL,LUT Value" line.long 0x410 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_125,Frontend WDR LUT" hexmask.long.word 0x410 0.--15. 1. "VAL,LUT Value" line.long 0x414 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_126,Frontend WDR LUT" hexmask.long.word 0x414 0.--15. 1. "VAL,LUT Value" line.long 0x418 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_127,Frontend WDR LUT" hexmask.long.word 0x418 0.--15. 1. "VAL,LUT Value" line.long 0x41C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_128,Frontend WDR LUT" hexmask.long.word 0x41C 0.--15. 1. "VAL,LUT Value" line.long 0x420 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_129,Frontend WDR LUT" hexmask.long.word 0x420 0.--15. 1. "VAL,LUT Value" line.long 0x424 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_130,Frontend WDR LUT" hexmask.long.word 0x424 0.--15. 1. "VAL,LUT Value" line.long 0x428 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_131,Frontend WDR LUT" hexmask.long.word 0x428 0.--15. 1. "VAL,LUT Value" line.long 0x42C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_132,Frontend WDR LUT" hexmask.long.word 0x42C 0.--15. 1. "VAL,LUT Value" line.long 0x430 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_133,Frontend WDR LUT" hexmask.long.word 0x430 0.--15. 1. "VAL,LUT Value" line.long 0x434 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_134,Frontend WDR LUT" hexmask.long.word 0x434 0.--15. 1. "VAL,LUT Value" line.long 0x438 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_135,Frontend WDR LUT" hexmask.long.word 0x438 0.--15. 1. "VAL,LUT Value" line.long 0x43C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_136,Frontend WDR LUT" hexmask.long.word 0x43C 0.--15. 1. "VAL,LUT Value" line.long 0x440 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_137,Frontend WDR LUT" hexmask.long.word 0x440 0.--15. 1. "VAL,LUT Value" line.long 0x444 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_138,Frontend WDR LUT" hexmask.long.word 0x444 0.--15. 1. "VAL,LUT Value" line.long 0x448 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_139,Frontend WDR LUT" hexmask.long.word 0x448 0.--15. 1. "VAL,LUT Value" line.long 0x44C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_140,Frontend WDR LUT" hexmask.long.word 0x44C 0.--15. 1. "VAL,LUT Value" line.long 0x450 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_141,Frontend WDR LUT" hexmask.long.word 0x450 0.--15. 1. "VAL,LUT Value" line.long 0x454 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_142,Frontend WDR LUT" hexmask.long.word 0x454 0.--15. 1. "VAL,LUT Value" line.long 0x458 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_143,Frontend WDR LUT" hexmask.long.word 0x458 0.--15. 1. "VAL,LUT Value" line.long 0x45C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_144,Frontend WDR LUT" hexmask.long.word 0x45C 0.--15. 1. "VAL,LUT Value" line.long 0x460 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_145,Frontend WDR LUT" hexmask.long.word 0x460 0.--15. 1. "VAL,LUT Value" line.long 0x464 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_146,Frontend WDR LUT" hexmask.long.word 0x464 0.--15. 1. "VAL,LUT Value" line.long 0x468 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_147,Frontend WDR LUT" hexmask.long.word 0x468 0.--15. 1. "VAL,LUT Value" line.long 0x46C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_148,Frontend WDR LUT" hexmask.long.word 0x46C 0.--15. 1. "VAL,LUT Value" line.long 0x470 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_149,Frontend WDR LUT" hexmask.long.word 0x470 0.--15. 1. "VAL,LUT Value" line.long 0x474 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_150,Frontend WDR LUT" hexmask.long.word 0x474 0.--15. 1. "VAL,LUT Value" line.long 0x478 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_151,Frontend WDR LUT" hexmask.long.word 0x478 0.--15. 1. "VAL,LUT Value" line.long 0x47C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_152,Frontend WDR LUT" hexmask.long.word 0x47C 0.--15. 1. "VAL,LUT Value" line.long 0x480 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_153,Frontend WDR LUT" hexmask.long.word 0x480 0.--15. 1. "VAL,LUT Value" line.long 0x484 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_154,Frontend WDR LUT" hexmask.long.word 0x484 0.--15. 1. "VAL,LUT Value" line.long 0x488 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_155,Frontend WDR LUT" hexmask.long.word 0x488 0.--15. 1. "VAL,LUT Value" line.long 0x48C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_156,Frontend WDR LUT" hexmask.long.word 0x48C 0.--15. 1. "VAL,LUT Value" line.long 0x490 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_157,Frontend WDR LUT" hexmask.long.word 0x490 0.--15. 1. "VAL,LUT Value" line.long 0x494 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_158,Frontend WDR LUT" hexmask.long.word 0x494 0.--15. 1. "VAL,LUT Value" line.long 0x498 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_159,Frontend WDR LUT" hexmask.long.word 0x498 0.--15. 1. "VAL,LUT Value" line.long 0x49C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_160,Frontend WDR LUT" hexmask.long.word 0x49C 0.--15. 1. "VAL,LUT Value" line.long 0x4A0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_161,Frontend WDR LUT" hexmask.long.word 0x4A0 0.--15. 1. "VAL,LUT Value" line.long 0x4A4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_162,Frontend WDR LUT" hexmask.long.word 0x4A4 0.--15. 1. "VAL,LUT Value" line.long 0x4A8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_163,Frontend WDR LUT" hexmask.long.word 0x4A8 0.--15. 1. "VAL,LUT Value" line.long 0x4AC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_164,Frontend WDR LUT" hexmask.long.word 0x4AC 0.--15. 1. "VAL,LUT Value" line.long 0x4B0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_165,Frontend WDR LUT" hexmask.long.word 0x4B0 0.--15. 1. "VAL,LUT Value" line.long 0x4B4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_166,Frontend WDR LUT" hexmask.long.word 0x4B4 0.--15. 1. "VAL,LUT Value" line.long 0x4B8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_167,Frontend WDR LUT" hexmask.long.word 0x4B8 0.--15. 1. "VAL,LUT Value" line.long 0x4BC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_168,Frontend WDR LUT" hexmask.long.word 0x4BC 0.--15. 1. "VAL,LUT Value" line.long 0x4C0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_169,Frontend WDR LUT" hexmask.long.word 0x4C0 0.--15. 1. "VAL,LUT Value" line.long 0x4C4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_170,Frontend WDR LUT" hexmask.long.word 0x4C4 0.--15. 1. "VAL,LUT Value" line.long 0x4C8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_171,Frontend WDR LUT" hexmask.long.word 0x4C8 0.--15. 1. "VAL,LUT Value" line.long 0x4CC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_172,Frontend WDR LUT" hexmask.long.word 0x4CC 0.--15. 1. "VAL,LUT Value" line.long 0x4D0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_173,Frontend WDR LUT" hexmask.long.word 0x4D0 0.--15. 1. "VAL,LUT Value" line.long 0x4D4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_174,Frontend WDR LUT" hexmask.long.word 0x4D4 0.--15. 1. "VAL,LUT Value" line.long 0x4D8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_175,Frontend WDR LUT" hexmask.long.word 0x4D8 0.--15. 1. "VAL,LUT Value" line.long 0x4DC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_176,Frontend WDR LUT" hexmask.long.word 0x4DC 0.--15. 1. "VAL,LUT Value" line.long 0x4E0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_177,Frontend WDR LUT" hexmask.long.word 0x4E0 0.--15. 1. "VAL,LUT Value" line.long 0x4E4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_178,Frontend WDR LUT" hexmask.long.word 0x4E4 0.--15. 1. "VAL,LUT Value" line.long 0x4E8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_179,Frontend WDR LUT" hexmask.long.word 0x4E8 0.--15. 1. "VAL,LUT Value" line.long 0x4EC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_180,Frontend WDR LUT" hexmask.long.word 0x4EC 0.--15. 1. "VAL,LUT Value" line.long 0x4F0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_181,Frontend WDR LUT" hexmask.long.word 0x4F0 0.--15. 1. "VAL,LUT Value" line.long 0x4F4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_182,Frontend WDR LUT" hexmask.long.word 0x4F4 0.--15. 1. "VAL,LUT Value" line.long 0x4F8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_183,Frontend WDR LUT" hexmask.long.word 0x4F8 0.--15. 1. "VAL,LUT Value" line.long 0x4FC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_184,Frontend WDR LUT" hexmask.long.word 0x4FC 0.--15. 1. "VAL,LUT Value" line.long 0x500 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_185,Frontend WDR LUT" hexmask.long.word 0x500 0.--15. 1. "VAL,LUT Value" line.long 0x504 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_186,Frontend WDR LUT" hexmask.long.word 0x504 0.--15. 1. "VAL,LUT Value" line.long 0x508 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_187,Frontend WDR LUT" hexmask.long.word 0x508 0.--15. 1. "VAL,LUT Value" line.long 0x50C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_188,Frontend WDR LUT" hexmask.long.word 0x50C 0.--15. 1. "VAL,LUT Value" line.long 0x510 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_189,Frontend WDR LUT" hexmask.long.word 0x510 0.--15. 1. "VAL,LUT Value" line.long 0x514 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_190,Frontend WDR LUT" hexmask.long.word 0x514 0.--15. 1. "VAL,LUT Value" line.long 0x518 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_191,Frontend WDR LUT" hexmask.long.word 0x518 0.--15. 1. "VAL,LUT Value" line.long 0x51C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_192,Frontend WDR LUT" hexmask.long.word 0x51C 0.--15. 1. "VAL,LUT Value" line.long 0x520 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_193,Frontend WDR LUT" hexmask.long.word 0x520 0.--15. 1. "VAL,LUT Value" line.long 0x524 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_194,Frontend WDR LUT" hexmask.long.word 0x524 0.--15. 1. "VAL,LUT Value" line.long 0x528 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_195,Frontend WDR LUT" hexmask.long.word 0x528 0.--15. 1. "VAL,LUT Value" line.long 0x52C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_196,Frontend WDR LUT" hexmask.long.word 0x52C 0.--15. 1. "VAL,LUT Value" line.long 0x530 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_197,Frontend WDR LUT" hexmask.long.word 0x530 0.--15. 1. "VAL,LUT Value" line.long 0x534 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_198,Frontend WDR LUT" hexmask.long.word 0x534 0.--15. 1. "VAL,LUT Value" line.long 0x538 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_199,Frontend WDR LUT" hexmask.long.word 0x538 0.--15. 1. "VAL,LUT Value" line.long 0x53C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_200,Frontend WDR LUT" hexmask.long.word 0x53C 0.--15. 1. "VAL,LUT Value" line.long 0x540 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_201,Frontend WDR LUT" hexmask.long.word 0x540 0.--15. 1. "VAL,LUT Value" line.long 0x544 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_202,Frontend WDR LUT" hexmask.long.word 0x544 0.--15. 1. "VAL,LUT Value" line.long 0x548 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_203,Frontend WDR LUT" hexmask.long.word 0x548 0.--15. 1. "VAL,LUT Value" line.long 0x54C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_204,Frontend WDR LUT" hexmask.long.word 0x54C 0.--15. 1. "VAL,LUT Value" line.long 0x550 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_205,Frontend WDR LUT" hexmask.long.word 0x550 0.--15. 1. "VAL,LUT Value" line.long 0x554 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_206,Frontend WDR LUT" hexmask.long.word 0x554 0.--15. 1. "VAL,LUT Value" line.long 0x558 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_207,Frontend WDR LUT" hexmask.long.word 0x558 0.--15. 1. "VAL,LUT Value" line.long 0x55C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_208,Frontend WDR LUT" hexmask.long.word 0x55C 0.--15. 1. "VAL,LUT Value" line.long 0x560 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_209,Frontend WDR LUT" hexmask.long.word 0x560 0.--15. 1. "VAL,LUT Value" line.long 0x564 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_210,Frontend WDR LUT" hexmask.long.word 0x564 0.--15. 1. "VAL,LUT Value" line.long 0x568 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_211,Frontend WDR LUT" hexmask.long.word 0x568 0.--15. 1. "VAL,LUT Value" line.long 0x56C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_212,Frontend WDR LUT" hexmask.long.word 0x56C 0.--15. 1. "VAL,LUT Value" line.long 0x570 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_213,Frontend WDR LUT" hexmask.long.word 0x570 0.--15. 1. "VAL,LUT Value" line.long 0x574 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_214,Frontend WDR LUT" hexmask.long.word 0x574 0.--15. 1. "VAL,LUT Value" line.long 0x578 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_215,Frontend WDR LUT" hexmask.long.word 0x578 0.--15. 1. "VAL,LUT Value" line.long 0x57C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_216,Frontend WDR LUT" hexmask.long.word 0x57C 0.--15. 1. "VAL,LUT Value" line.long 0x580 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_217,Frontend WDR LUT" hexmask.long.word 0x580 0.--15. 1. "VAL,LUT Value" line.long 0x584 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_218,Frontend WDR LUT" hexmask.long.word 0x584 0.--15. 1. "VAL,LUT Value" line.long 0x588 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_219,Frontend WDR LUT" hexmask.long.word 0x588 0.--15. 1. "VAL,LUT Value" line.long 0x58C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_220,Frontend WDR LUT" hexmask.long.word 0x58C 0.--15. 1. "VAL,LUT Value" line.long 0x590 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_221,Frontend WDR LUT" hexmask.long.word 0x590 0.--15. 1. "VAL,LUT Value" line.long 0x594 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_222,Frontend WDR LUT" hexmask.long.word 0x594 0.--15. 1. "VAL,LUT Value" line.long 0x598 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_223,Frontend WDR LUT" hexmask.long.word 0x598 0.--15. 1. "VAL,LUT Value" line.long 0x59C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_224,Frontend WDR LUT" hexmask.long.word 0x59C 0.--15. 1. "VAL,LUT Value" line.long 0x5A0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_225,Frontend WDR LUT" hexmask.long.word 0x5A0 0.--15. 1. "VAL,LUT Value" line.long 0x5A4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_226,Frontend WDR LUT" hexmask.long.word 0x5A4 0.--15. 1. "VAL,LUT Value" line.long 0x5A8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_227,Frontend WDR LUT" hexmask.long.word 0x5A8 0.--15. 1. "VAL,LUT Value" line.long 0x5AC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_228,Frontend WDR LUT" hexmask.long.word 0x5AC 0.--15. 1. "VAL,LUT Value" line.long 0x5B0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_229,Frontend WDR LUT" hexmask.long.word 0x5B0 0.--15. 1. "VAL,LUT Value" line.long 0x5B4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_230,Frontend WDR LUT" hexmask.long.word 0x5B4 0.--15. 1. "VAL,LUT Value" line.long 0x5B8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_231,Frontend WDR LUT" hexmask.long.word 0x5B8 0.--15. 1. "VAL,LUT Value" line.long 0x5BC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_232,Frontend WDR LUT" hexmask.long.word 0x5BC 0.--15. 1. "VAL,LUT Value" line.long 0x5C0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_233,Frontend WDR LUT" hexmask.long.word 0x5C0 0.--15. 1. "VAL,LUT Value" line.long 0x5C4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_234,Frontend WDR LUT" hexmask.long.word 0x5C4 0.--15. 1. "VAL,LUT Value" line.long 0x5C8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_235,Frontend WDR LUT" hexmask.long.word 0x5C8 0.--15. 1. "VAL,LUT Value" line.long 0x5CC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_236,Frontend WDR LUT" hexmask.long.word 0x5CC 0.--15. 1. "VAL,LUT Value" line.long 0x5D0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_237,Frontend WDR LUT" hexmask.long.word 0x5D0 0.--15. 1. "VAL,LUT Value" line.long 0x5D4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_238,Frontend WDR LUT" hexmask.long.word 0x5D4 0.--15. 1. "VAL,LUT Value" line.long 0x5D8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_239,Frontend WDR LUT" hexmask.long.word 0x5D8 0.--15. 1. "VAL,LUT Value" line.long 0x5DC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_240,Frontend WDR LUT" hexmask.long.word 0x5DC 0.--15. 1. "VAL,LUT Value" line.long 0x5E0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_241,Frontend WDR LUT" hexmask.long.word 0x5E0 0.--15. 1. "VAL,LUT Value" line.long 0x5E4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_242,Frontend WDR LUT" hexmask.long.word 0x5E4 0.--15. 1. "VAL,LUT Value" line.long 0x5E8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_243,Frontend WDR LUT" hexmask.long.word 0x5E8 0.--15. 1. "VAL,LUT Value" line.long 0x5EC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_244,Frontend WDR LUT" hexmask.long.word 0x5EC 0.--15. 1. "VAL,LUT Value" line.long 0x5F0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_245,Frontend WDR LUT" hexmask.long.word 0x5F0 0.--15. 1. "VAL,LUT Value" line.long 0x5F4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_246,Frontend WDR LUT" hexmask.long.word 0x5F4 0.--15. 1. "VAL,LUT Value" line.long 0x5F8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_247,Frontend WDR LUT" hexmask.long.word 0x5F8 0.--15. 1. "VAL,LUT Value" line.long 0x5FC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_248,Frontend WDR LUT" hexmask.long.word 0x5FC 0.--15. 1. "VAL,LUT Value" line.long 0x600 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_249,Frontend WDR LUT" hexmask.long.word 0x600 0.--15. 1. "VAL,LUT Value" line.long 0x604 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_250,Frontend WDR LUT" hexmask.long.word 0x604 0.--15. 1. "VAL,LUT Value" line.long 0x608 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_251,Frontend WDR LUT" hexmask.long.word 0x608 0.--15. 1. "VAL,LUT Value" line.long 0x60C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_252,Frontend WDR LUT" hexmask.long.word 0x60C 0.--15. 1. "VAL,LUT Value" line.long 0x610 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_253,Frontend WDR LUT" hexmask.long.word 0x610 0.--15. 1. "VAL,LUT Value" line.long 0x614 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_254,Frontend WDR LUT" hexmask.long.word 0x614 0.--15. 1. "VAL,LUT Value" line.long 0x618 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_255,Frontend WDR LUT" hexmask.long.word 0x618 0.--15. 1. "VAL,LUT Value" line.long 0x61C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_WDR_GAMMA_LUT_256,Frontend WDR LUT" hexmask.long.word 0x61C 0.--15. 1. "VAL,LUT Value" line.long 0x620 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_TILE_OUT_POS,Tile processing signals" hexmask.long.word 0x620 16.--31. 1. "TOP,Tile Top position" newline hexmask.long.word 0x620 0.--15. 1. "LEFT,Tile Left position" group.long 0x6E0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_TILE_OUT_SIZE,Tile processing signals" hexmask.long.word 0x0 16.--31. 1. "HEIGHT,Tile Height" newline hexmask.long.word 0x0 0.--15. 1. "WIDTH,Tile Width" group.long 0x6E8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_TILE_CONTROL,Tile Processing Control register" bitfld.long 0x0 4. "LAST,Last time" "0,1" newline bitfld.long 0x0 3. "COLLECTION_DISABLE,Statistics collection disable" "0,1" newline bitfld.long 0x0 2. "UPDATE_DSABLE,Statistics update disable" "0,1" newline bitfld.long 0x0 0. "ENABLE,Tile processing Enable" "0,1" rgroup.long 0x6EC++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__CFG__GLBCE_REGS_GLBCE_OUTPUT_FLAGS,Tile status register" hexmask.long.word 0x0 0.--15. 1. "TILE_STATUS,Tile Status" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_STATMEM_CFG_GLBCE_STATMEM" base ad:0x2C104000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__K3_GLBCE_TOP__STATMEM_CFG__GLBCE_STATMEM_statmem,odd and even banks are combined for one 32-bit access" hexmask.long.word 0x0 16.--31. 1. "ODD,Odd bank" hexmask.long.word 0x0 0.--15. 1. "EVEN,Even bank" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP" base ad:0x2C100000 rgroup.long 0x0++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_REVISION_REG,VISS PID" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme. Spare bit to encode future schemes" "0,1,2,3" newline bitfld.long 0x0 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new FUNC number and hence PID should be assigned." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version. R as described in PDR with additional clarifications and definitions below. Must be easily ECO-able or controlled during fabrication. Ideally through a top level metal mask or e-fuse. This number is maintained/owned by IP design.." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision. X as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. X is part of IP numbering X.Y.R.Z. X changes ONLY when: (1) There is a major feature addition. An.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. 0 if non-custom." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision. Y as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. Y changes ONLY when: (1) Features are scaled (up or down). Flexibility exists in that this.." line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_VISS_FUSE_STATUS,Register captures the Fuse control status. Shouldn't be captured into TRM" bitfld.long 0x4 1. "NIKON_DISABLE,Availability of NIKON specific feature HW in H3A. '0' -> Nikon features are available '1' -> Nikon features are not available" "0: Nikon features are available,1: Nikon features are not available" newline bitfld.long 0x4 0. "GLBCE_DISABLE,Availability GLBCE HW. '0' -> GLBCE function HW is available '1' -> GLBCE function HW is not available" "0: GLBCE function HW is available,1: GLBCE function HW is not available" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_VISS_LINEMEM_SIZE,Captures the no. of pixels per line supported by the VISS" hexmask.long.word 0x8 0.--13. 1. "LINEMEM_SZ,No. of pixels per line supported by the VISS HWAs Memories" group.long 0xC++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_SYSCONFIG,system Configuration" bitfld.long 0x0 1. "CLKCG_OVERIDE,Reserved for this HW version" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_VISS_CNTL,VISS top control" bitfld.long 0x4 3. "PCID_EN,'1' -> PCID is ON '0' -> PCID is off i.e. bypass PCID. Read the bit status for completion of write. Even when '0' Configuration access to PCID will be successful." "0: PCID is off i,1: PCID is ON" newline bitfld.long 0x4 2. "CAC_EN,'1' -> CAC is ON '0' -> CAC is off i.e. bypass CAC. Read the bit status for completion of write. Even when '0' Configuration access to CAC will be successful." "0: CAC is off i,1: CAC is ON" newline bitfld.long 0x4 1. "NSF4V_EN,'1' -> NSF4V is ON '0' -> NSF4V is off i.e. bypass NSF4V. Read the bit status for completion of write. Even when '0' Configuration access to NSF4V will be successful." "0: NSF4V is off i,1: NSF4V is ON" newline bitfld.long 0x4 0. "GLBCE_EN,'1' -> GLBCE is ON '0' -> GLBCE is off i.e. bypass GLBCE. Read the bit status for completion of write. When '0' Configuration access to GLBCE End points (MMR Statastics memory ) will result in Error response." "0: GLBCE is off i,1: GLBCE is ON" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_FREEPCLK_CFG,Register to control and configure Free running pixel clock to whole VISS pipe line" hexmask.long.word 0x8 16.--28. 1. "CNTVAL,Number of free pixel clocks to be provided" newline rbitfld.long 0x8 1. "PCLKFREE_STATE,Status of Free running pixel clock state. 0 - Free running pixel Clock is not being provided currently 1 - Free running pixel Clock is getting provided" "0,1" newline bitfld.long 0x8 0. "PCLKFREE_EN,Enable to provide Free running pixel clocks at the end of frame for VISS data pipe line. Needs to be enabled before end of a frame to provide free running pixel clock after that particular frame" "0,1" group.long 0x40++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_FCP2_CNTL,FCP2 Input Control register" hexmask.long.byte 0x0 16.--23. 1. "IN_PIPEDLY,No. of pixel clock pipe delay on FCP2 input Vport. Used for matching with horizontal delay upto FCP Input" newline bitfld.long 0x0 1.--2. "IN_SEL,Input path to FCP2. 0 - RFE output 1 - NSF4V output 2 - GLBCE output 3 - CAC output" "0,1,2,3" newline bitfld.long 0x0 0. "PIXCLK_EN,Enable for FCP2 Pixel clock. 0 - FCP2 Pixel clock gated 1 - Pixel clock is enabled for FCP2" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_LSEOUT_MUX_CNTL,LSE Outout channel mux contro. IR output[11:0] selection should be used when IR output width <= 12. When IR data width is greater than 12-bit. it should split & LSB..." bitfld.long 0x4 16.--17. "S8SEL,LSE[4] - S8 output channel driver. 0 - FCP S8 Channel 1 - Reserved 2 - PCID IR Channel output[11:0] (IR data width is 8-12bit range) Others - In valid" "0,1,2,3" newline bitfld.long 0x4 12.--14. "UV8SEL,LSE[3] - UV8 output channel driver. 0 - Reserved 1 - Reserved 2 - FCP UV8 Channel 3 - Reserved 4 - PCID IR Channel output[11:0] (IR data width is 8-12bit range) 5 - PCID IR Channel output[7:0] (when IR data width > 12) Others - In.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "Y8SEL,LSE[2] - Y8 output channel driver. 0 - Reserved 1 - Reserved 2 - FCP Y8 Channel 3 - Reserved 4 - PCID IR Channel output[11:0] (IR data width is 8-12bit range) 5 - PCID IR Channel output[15:8] (when IR data width > 12) Others - In.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "UV12SEL,LSE[1] - UV12 output channel driver. 0 - FCP UV12 Channel 1 - Reserved 2 - Reserved 3 - Reserved 4 - PCID IR Channel output[11:0] (IR data width is 8-12bit range) 5 - PCID IR Channel output[7:0] (when IR data width > 12) Others -.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "Y12SEL,LSE[0] - Y12 output channel driver. 0 - FCP Y12 Channel 1 - Reserved 2 - Reserved 3 - Reserved 4 - PCID IR Channel output[11:0] (IR data width is 8-12bit range) 5 - PCID IR Channel output[15:8] (when IR data width > 12) Others -.." "0,1,2,3,4,5,6,7" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_IROUT_CNTL,Control register for IR Output path delay synchronization with rest of the pipe line" hexmask.long.word 0x8 16.--24. 1. "PIPEDLY,No. of pixel clock pipe delay on PCID IR Output channel. Max allowed value is 274. Used for matching horizontal delay VISS bayer pipe line" newline hexmask.long.byte 0x8 8.--12. 1. "DWIDTH,IR Output Data width. Valid ranges are 8-16" group.long 0x70++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_VISS_INT_STAT,Set on internal interutp event and clr by SW" bitfld.long 0x0 0. "IROUT_OVF_ERR,Status/Clear for Overflow on IR output write infrace. Set on Overflow condition on IR output interface" "0,1" group.long 0x80++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_VISS_DBG_CTL,Enable for VISS debug staus capture" bitfld.long 0x0 2. "IROUT_STALL_EN,Enable to Capture Stall on IR output write infrace" "0,1" newline bitfld.long 0x0 1. "PRTL_WR_EN,Enable to Capture Partial Write to any VISS end point" "0,1" newline bitfld.long 0x0 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_VISS_DBG_STAT,Set/Clear for VISS debug status" bitfld.long 0x4 2. "IROUT_STALL,Status/Clear for Stall on IR output write infrace. Set on stall IR output interface" "0,1" newline bitfld.long 0x4 1. "PRTL_WR,Status/Clear for Partial Write to any VISS end point. Set on Partial Write at VISS_Top input Cfg interface" "0,1" group.long 0x100++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_GLBCECONFIG,GLBCE Configuration" bitfld.long 0x0 0. "GLBCE_PCLKFREE,'1'-> GLBCE pclk is free running '0' -> GLBCE pclk is gated pixel clock" "0: GLBCE pclk is gated pixel clock,?" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_GLBCE_VPSYNCDLY,Delay of GLBCE Core. used to regenerate VS/VE VPORT signals" hexmask.long.byte 0x4 8.--15. 1. "V_DLY,Line delay between GLBCE.VS_In to GLBCE.VS_Out" newline hexmask.long.byte 0x4 0.--7. 1. "H_DLY,Cycle delay between GLBCE.HS_In to GLBCE.HS_Out minus 1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_GLBCE_INT_STAT,Set on internal interutp event and clr by SW" bitfld.long 0x8 6. "VSYNC_ERR,status/clear for GLBCE VSYNC Delay programmation error. Set Delayed sync signals doesn't match with sync signal generated from GLBCE Core" "0,1" newline bitfld.long 0x8 5. "HSYNC_ERR,status/clear for GLBCE HSYNC Delay programmation error. Set Delayed sync signals doesn't match with sync signal generated from GLBCE Core" "0,1" newline bitfld.long 0x8 4. "VP_ERR,status/clear for GLBCE Input frame start error. Set Input frame is started while filtering is going on" "0,1" newline bitfld.long 0x8 3. "FILT_DONE,status/clear for GLBCE Filtering Done event. Set when GLBCE Filtering is completed." "0,1" newline bitfld.long 0x8 2. "FILT_START,status/clear for GLBCE Filtering Start event. Set when GLBCE Filtering starts" "0,1" newline bitfld.long 0x8 1. "STATMEM_CFG_ERR,status/clear for statastics memory configuration error. Set when access happen to statastics memory in the middle of processing" "0,1" newline bitfld.long 0x8 0. "MMR_CFG_ERR,status/clear for mmr configuration error. Set when writes happen to non-shadowed registers in the middle of processing" "0,1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_GLBCE_DBG_CTL,Enable for GLBCE debug events" bitfld.long 0xC 4. "EOF_EN,Enable for EOF at GLBCE output" "0,1" newline bitfld.long 0xC 3. "EOL_EN,Enable for EOL at GLBCE output" "0,1" newline bitfld.long 0xC 2. "SOF_EN,Enable for SOF at GLBCE input" "0,1" newline bitfld.long 0xC 1. "SOL_EN,Enable for SOL at GLBCE input" "0,1" newline bitfld.long 0xC 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_GLBCE_DBG_STAT,Set/Clear for GLBCE debug events" bitfld.long 0x10 4. "EOF,Status/Clear for EOF at GLBCE output. Set on EOF at GLBCE output" "0,1" newline bitfld.long 0x10 3. "EOL,Status/Clear for EOL at GLBCE output. Set on EOL at GLBCE output" "0,1" newline bitfld.long 0x10 2. "SOF,Status/Clear for SOF at GLBCE input. Set on SOF at GLBCE input" "0,1" newline bitfld.long 0x10 1. "SOL,Status/Clear for SOL at GLBCE input. Set on SOL at GLBCE input" "0,1" group.long 0x180++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_NSF4V_INT_STAT,Set on internal interutp event and clr by SW" bitfld.long 0x0 4. "VBLANK_ERR,status/clear for Vorizontal Blanking Error. Set when Vertical Blanking too short between frames" "0,1" newline bitfld.long 0x0 3. "HBLANK_ERR,status/clear for Horizontal Blanking Error. Set when Horzontal Blanking too short between lines" "0,1" newline bitfld.long 0x0 2. "RAWHIST_CFG_ERR,status/clear for RawHistogram Read incomplete. Set when SW starts reading Raw Histogram data (read from location '0') but didn't complete (read from '127' location) before end of next frame" "0,1" newline bitfld.long 0x0 1. "LUT_CFG_ERR,status/clear for Histogram LUT memory configuration error. Set VBUSP access of RAM while NSF data path using LUT for functional purpose" "0,1" newline bitfld.long 0x0 0. "LINEMEM_CFG_ERR,status/clear for Line mem configuration error. Set when VBUSP diagnostic read access of RAM while NSF data path using RAM for functional purpose" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_NSF4V_DBG_CTL,Enable for NSF4V debug events" bitfld.long 0x4 4. "EOF_EN,Enable for EOF at NSF4V output" "0,1" newline bitfld.long 0x4 3. "EOL_EN,Enable for EOL at NSF4V output" "0,1" newline bitfld.long 0x4 2. "SOF_EN,Enable for SOF at NSF4V input" "0,1" newline bitfld.long 0x4 1. "SOL_EN,Enable for SOL at NSF4V input" "0,1" newline bitfld.long 0x4 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_NSF4V_DBG_STAT,Set/Clear for NSF4V debug events" bitfld.long 0x8 4. "EOF,Status/Clear for EOF at NSF4V output. Set on EOF at NSF4V output" "0,1" newline bitfld.long 0x8 3. "EOL,Status/Clear for EOL at NSF4V output. Set on EOL at NSF4V output" "0,1" newline bitfld.long 0x8 2. "SOF,Status/Clear for SOF at NSF4V input. Set on SOF at NSF4V input" "0,1" newline bitfld.long 0x8 1. "SOL,Status/Clear for SOL at NSF4V input. Set on SOL at NSF4V input" "0,1" group.long 0x1A0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_DBGEVT_CTL,Control to map internal events" bitfld.long 0x0 4.--5. "SEL3,Mux select for GLBCE CAC PCID VPORT events. 0 - Select GLBCE events 1 - Select CAC events 2. Select PCID events Common mux control for SOL SOF EOL and EOF events between the GLBCE and CAC. For PCID output events IR VPORT is exported" "0,1,2,3" newline bitfld.long 0x0 2.--3. "SEL2,Mux select for CFA SOFs and FCP2 fcc_eop event. 0 - FCP.cfa_sof_event 1 - reserved 2 - reserved 3. Invalid" "0,1,2,3" newline bitfld.long 0x0 0.--1. "SEL1,Mux select for CFA SOLs FCP2 fcc_stall and IR output write stall event. 0 - FCP.cfa_sol_event 1 - reserved 2 - reserved 3. PCID IR output write Stall" "0,1,2,3" group.long 0x1C0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__MMR__CFG__VISS_TOP_REGS_TEST_CNTL,Control register for TEST. Shouldn't be used in functional mode" bitfld.long 0x0 0. "GATED_MEM_CLKF,Control to force functional clock to H3A and CAC line memory for Pbist Config test. '1' - Free running functional clock is supplied to H3A line memory '0' - Gated Pixel clock is supplied in functional operation" "0,1" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_CORE_LUT_CFG_LUT_MEM" base ad:0x2C182000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__CORE__LUT_CFG__LUT_MEM_lut,Only full 32-bit access it allowed for ECC reasons" hexmask.long.byte 0x0 24.--31. 1. "ODD_DY,Vertical Displacement for Odd Line" hexmask.long.byte 0x0 16.--23. 1. "ODD_DX,Horizontal Displacement for Odd Line" hexmask.long.byte 0x0 8.--15. 1. "EVEN_DY,Vertical Displacement for Even Line starting with '0'" hexmask.long.byte 0x0 0.--7. 1. "EVEN_DX,Horizontal Displacement for Even Line starting with '0'" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_LINEMEM_CFG_LINE_MEM" base ad:0x2C184000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP____LINEMEM_CFG__LINE_MEM_MEM,Only full 32-bit access it allowed" hexmask.long 0x0 0.--31. 1. "PIXD,No Byte or Word Access. Only full 32-bit access it allowed" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_MMRCFG_CAC" base ad:0x2C180000 group.long 0x4++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__MMR__MMRCFG__CAC_REGS_CTRL,Control Register to Enable/Disable and select modes of operation" hexmask.long.byte 0x0 8.--11. 1. "COLOR_EN,Enable for CAC processing in 2x2 pixel grid. bit[0] - row[0]col[0] bit[1] - row[0]col[1] bit[2] - row[1]col[0] bit[3] - row[1]col[1]. One pixel should be enabled in each row of 2x2. 10 or 01 combinations are allowed in each row." line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__MMR__MMRCFG__CAC_REGS_FRAMESZ,Actual frame size is configured value + 1" hexmask.long.word 0x4 16.--28. 1. "HEIGHT,Number of Lines per frame. Actual Frame height is HEIGHT +1. Actual frame height should minimum of 32 and multiple of 2" hexmask.long.word 0x4 0.--12. 1. "WIDTH,Number of pixels per line. Actual Frame width is WIDTH +1. Actual frame width should minimum of 64 and multiple of 2" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__MMR__MMRCFG__CAC_REGS_BLOCKSZ,Size of Block and each block will have 2 LUT entries with displacement value" hexmask.long.byte 0x8 0.--7. 1. "SIZE,Height and Width of Subsampled Block. Each block will have 2 displacement entries for SIZExSIZE block ; one for even line and other for odd line. Minimum of 8 and maximum of 128. Should be multiple of 4" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__MMR__MMRCFG__CAC_REGS_BLOCKCNT,LUT Grid size. Should cover frame size plus 1 for interpolation. VCNT * HCNT <= 2048" hexmask.long.word 0xC 16.--25. 1. "VCNT,LUT Grid heighti i.e. no. of blocks in vertical direction. (VCNT-1)* BLOCKSZ.SIZE >= frame_height and max value is 512" hexmask.long.word 0xC 0.--9. 1. "HCNT,LUT Grid width i.e. no. of blocks in horizontal direction. (HCNT-1)* BLOCKSZ.SIZE >= frame_width and max value is 512" group.long 0x80++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__MMR__MMRCFG__CAC_REGS_INT_STAT,Set on internal interupt event and clr by SW" bitfld.long 0x0 0. "LUT_CFG_ERR,status/clear for mmr configuration error. Set when Config access happen to LUT memory in the middle of processing" "0,1" group.long 0x100++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__MMR__MMRCFG__CAC_REGS_DBG_CTL,Control the memory access selection" hexmask.long.byte 0x0 8.--11. 1. "LINEMEM_SEL,0-6: CAC corrected line memory. i.e. EnLine0..6 7-9: Bypassed pixel Line memory. i.e. BypLine0..2" bitfld.long 0x0 4. "EOF_EN,Enable for EOF at CAC output" "0,1" bitfld.long 0x0 3. "EOL_EN,Enable for EOL at CAC output" "0,1" newline bitfld.long 0x0 2. "SOF_EN,Enable for SOF at CAC input" "0,1" bitfld.long 0x0 1. "SOL_EN,Enable for SOL at CAC input" "0,1" bitfld.long 0x0 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_CAC__S_VBUSP__MMR__MMRCFG__CAC_REGS_DBG_STAT,Set/Clear for CAC debug events" bitfld.long 0x4 4. "EOF,Status/Clear for EOF at CAC output. Set on EOF at CAC output" "0,1" bitfld.long 0x4 3. "EOL,Status/Clear for EOL at CAC output. Set on EOL at CAC output" "0,1" bitfld.long 0x4 2. "SOF,Status/Clear for SOF at CAC input. Set on SOF at CAC input" "0,1" newline bitfld.long 0x4 1. "SOL,Status/Clear for SOL at CAC input. Set on SOL at CAC input" "0,1" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_CFA_VBUSP_FLEXCFA" base ad:0x2C108000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_LUT,The LUT table contains the information used to reduce the pixle width to 12 from 13-16" hexmask.long.word 0x0 16.--31. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." newline hexmask.long.word 0x0 0.--15. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." group.long 0x1004++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CFG_0,The Control Register controls the input width and height of the module." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,Height of the input image" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,Width of the input image" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CFG_1,The Control Register identifies the bit width of the input image" bitfld.long 0x4 11. "BYPASS_CORE3,Setting the ~ibypass_core3 bit will bypass filtering operation output = input" "0,1" newline bitfld.long 0x4 10. "BYPASS_CORE2,Setting the ~ibypass_core2 bit will bypass filtering operation output = input" "0,1" newline bitfld.long 0x4 9. "BYPASS_CORE1,Setting the ~ibypass_core1 bit will bypass filtering operation output = input" "0,1" newline bitfld.long 0x4 8. "BYPASS_CORE0,Setting the ~ibypass_core0 bit will bypass filtering operation output = input" "0,1" newline bitfld.long 0x4 6. "EN16BITMODE,0->legacy mode 1->Enhanced 16 bit CFA mode enabled when LUT is disabled" "0,1" newline bitfld.long 0x4 5. "LUT_ENABLE,0->Use shift(bitwidth-12) 1->Use LUT" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "BITWIDTH,BitWidth of the input image values greater than 16 will be treated as 16 and values less than 12 will be treated as 12." group.long 0x1D8C++0x47 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_GRAD_CFG,Gradient configuration for all 4 cores" bitfld.long 0x0 25.--26. "BLENDMODECORE3,Core-3 Blend (0:Input-0 1: Input0/1 2: Input 0/1/2 3 : Adaptive Input0/1/2 )" "0: Input-0,1: Input0/1,2: Input 0/1/2,3: Adaptive Input0/1/2" newline bitfld.long 0x0 24. "BITMASKSELCORE3,Core-3 Bitmask Select (0: Set-0 1: Set-1)" "0: Set-0,1: Set-1" newline bitfld.long 0x0 17.--18. "BLENDMODECORE2,Core-2 Blend (0:Input-0 1: Input0/1 2: Input 0/1/2 3 : Adaptive Input0/1/2 )" "0: Input-0,1: Input0/1,2: Input 0/1/2,3: Adaptive Input0/1/2" newline bitfld.long 0x0 16. "BITMASKSELCORE2,Core-2 Bitmask Select (0: Set-0 1: Set-1)" "0: Set-0,1: Set-1" newline bitfld.long 0x0 9.--10. "BLENDMODECORE1,Core-1 Blend (0:Input-0 1: Input0/1 2: Input 0/1/2 3 : Adaptive Input0/1/2 )" "0: Input-0,1: Input0/1,2: Input 0/1/2,3: Adaptive Input0/1/2" newline bitfld.long 0x0 8. "BITMASKSELCORE1,Core-1 Bitmask Select (0: Set-0 1: Set-1)" "0: Set-0,1: Set-1" newline bitfld.long 0x0 1.--2. "BLENDMODECORE0,Core-0 Blend (0:Input-0 1: Input0/1 2: Input 0/1/2 3 : Adaptive Input0/1/2 )" "0: Input-0,1: Input0/1,2: Input 0/1/2,3: Adaptive Input0/1/2" newline bitfld.long 0x0 0. "BITMASKSELCORE0,Core-0 Bitmask Select (0: Set-0 1: Set-1)" "0: Set-0,1: Set-1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_GRAD_HZ,Gradient Bitfield selector. Set-0 for Horizontal" hexmask.long.byte 0x4 24.--31. 1. "PHASE3,Bitfield selector for Phase-3" newline hexmask.long.byte 0x4 16.--23. 1. "PHASE2,Bitfield selector for Phase-2" newline hexmask.long.byte 0x4 8.--15. 1. "PHASE1,Bitfield selector for Phase-1" newline hexmask.long.byte 0x4 0.--7. 1. "PHASE0,Bitfield selector for Phase-0" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_GRAD_VT,Gradient Bitfield selector. Set-0 for Vertical" hexmask.long.byte 0x8 24.--31. 1. "PHASE3,Bitfield selector for Phase-3" newline hexmask.long.byte 0x8 16.--23. 1. "PHASE2,Bitfield selector for Phase-2" newline hexmask.long.byte 0x8 8.--15. 1. "PHASE1,Bitfield selector for Phase-1" newline hexmask.long.byte 0x8 0.--7. 1. "PHASE0,Bitfield selector for Phase-0" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_INTENSITY0,Intensity Bitfield selector and shift for phase0/1" hexmask.long.byte 0xC 28.--31. 1. "SHIFT_PH1,Intensity shift for Phase-1" newline hexmask.long.byte 0xC 16.--19. 1. "BITFIELD_PH1,Intensity Bitfield selector for Phase-1" newline hexmask.long.byte 0xC 12.--15. 1. "SHIFT_PH0,Intensity shift for Phase-0" newline hexmask.long.byte 0xC 0.--3. 1. "BITFIELD_PH0,Intensity Bitfield selector for Phase-0" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_INTENSITY1,Intensity Bitfield selector and shift for phase2/3" hexmask.long.byte 0x10 28.--31. 1. "SHIFT_PH3,Intensity shift for Phase-3" newline hexmask.long.byte 0x10 16.--19. 1. "BITFIELD_PH3,Intensity Bitfield selector for Phase-3" newline hexmask.long.byte 0x10 12.--15. 1. "SHIFT_PH2,Intensity shift for Phase-2" newline hexmask.long.byte 0x10 0.--3. 1. "BITFIELD_PH2,Intensity Bitfield selector for Phase-2" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_GRAD_HZ,Gradient Bitfield selector. Set-1 for Horizontal" hexmask.long.byte 0x14 24.--31. 1. "PHASE3,Bitfield selector for Phase-3" newline hexmask.long.byte 0x14 16.--23. 1. "PHASE2,Bitfield selector for Phase-2" newline hexmask.long.byte 0x14 8.--15. 1. "PHASE1,Bitfield selector for Phase-1" newline hexmask.long.byte 0x14 0.--7. 1. "PHASE0,Bitfield selector for Phase-0" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_GRAD_VT,Gradient Bitfield selector. Set-1 for Vertical" hexmask.long.byte 0x18 24.--31. 1. "PHASE3,Bitfield selector for Phase-3" newline hexmask.long.byte 0x18 16.--23. 1. "PHASE2,Bitfield selector for Phase-2" newline hexmask.long.byte 0x18 8.--15. 1. "PHASE1,Bitfield selector for Phase-1" newline hexmask.long.byte 0x18 0.--7. 1. "PHASE0,Bitfield selector for Phase-0" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_INTENSITY0,Intensity Bitfield selector and shift for phase0/1" hexmask.long.byte 0x1C 28.--31. 1. "SHIFT_PH1,Intensity shift for Phase-1" newline hexmask.long.byte 0x1C 16.--19. 1. "BITFIELD_PH1,Intensity Bitfield selector for Phase-1" newline hexmask.long.byte 0x1C 12.--15. 1. "SHIFT_PH0,Intensity shift for Phase-0" newline hexmask.long.byte 0x1C 0.--3. 1. "BITFIELD_PH0,Intensity Bitfield selector for Phase-0" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_INTENSITY1,Intensity Bitfield selector and shift for phase2/3" hexmask.long.byte 0x20 28.--31. 1. "SHIFT_PH3,Intensity shift for Phase-3" newline hexmask.long.byte 0x20 16.--19. 1. "BITFIELD_PH3,Intensity Bitfield selector for Phase-3" newline hexmask.long.byte 0x20 12.--15. 1. "SHIFT_PH2,Intensity shift for Phase-2" newline hexmask.long.byte 0x20 0.--3. 1. "BITFIELD_PH2,Intensity Bitfield selector for Phase-2" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_THR0_1,Set0 Thr0_1 for H/V Grad difference" hexmask.long.word 0x24 16.--31. 1. "THR_1,H/V Grad diff Threshold_1" newline hexmask.long.word 0x24 0.--15. 1. "THR_0,H/V Grad diff Threshold_0" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_THR2_3,Set0 Thr2_3 for H/V Grad difference" hexmask.long.word 0x28 16.--31. 1. "THR_3,H/V Grad diff Threshold_3" newline hexmask.long.word 0x28 0.--15. 1. "THR_2,H/V Grad diff Threshold_2" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_THR4_5,Set0 Thr4_5 for H/V Grad difference" hexmask.long.word 0x2C 16.--31. 1. "THR_5,H/V Grad diff Threshold_5" newline hexmask.long.word 0x2C 0.--15. 1. "THR_4,H/V Grad diff Threshold_4" line.long 0x30 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET0_THR6,Set0 Thr6 for H/V Grad difference" hexmask.long.word 0x30 0.--15. 1. "THR_6,H/V Grad diff Threshold_6" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_THR0_1,Set1 Thr0_1 for H/V Grad difference" hexmask.long.word 0x34 16.--31. 1. "THR_1,H/V Grad diff Threshold_1" newline hexmask.long.word 0x34 0.--15. 1. "THR_0,H/V Grad diff Threshold_0" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_THR2_3,Set1 Thr2_3 for H/V Grad difference" hexmask.long.word 0x38 16.--31. 1. "THR_3,H/V Grad diff Threshold_3" newline hexmask.long.word 0x38 0.--15. 1. "THR_2,H/V Grad diff Threshold_2" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_THR4_5,Set1 Thr4_5 for H/V Grad difference" hexmask.long.word 0x3C 16.--31. 1. "THR_5,H/V Grad diff Threshold_5" newline hexmask.long.word 0x3C 0.--15. 1. "THR_4,H/V Grad diff Threshold_4" line.long 0x40 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_SET1_THR6,Set1 Thr6 for H/V Grad difference" hexmask.long.word 0x40 0.--15. 1. "THR_6,H/V Grad diff Threshold_6" line.long 0x44 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_INT_STATUS,Status/clear register for flexcfa interrupts" bitfld.long 0x44 4. "CLUT_CFG_ERR,status/clear for error on CLUT cfg set when software accesses CLUT during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x44 3. "DLUT_CFG_ERR,status/clear for error on DLUT cfg set when software accesses DLUT during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x44 2. "CFA_MMR_ERR,status/clear for error writes to the FIR Filter MMRs during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x44 1. "CFA_PIX_ERR,status/clear for error on line array set when software accesses pixel array during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x44 0. "LUT_CFG_ERR,status/clear for error on LUT cfg set when software accesses LUT during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" group.long 0x2000++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_DEBUG_CTL,Enable for different debug events" bitfld.long 0x0 2. "SOF_EN,Enable for sof event" "0,1" newline bitfld.long 0x0 1. "SOL_EN,Enable for sol event" "0,1" newline bitfld.long 0x0 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_DEBUG_STATUS,Set/Clear for debug events" bitfld.long 0x4 2. "SOF_EVENT,Status/Clear for sof event write '1' to clear" "0,1" newline bitfld.long 0x4 1. "SOL_EVENT,Status/Clear for sol event write '1' to clear" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_LINE_SEL,Selector for which line memory is read or written" bitfld.long 0x8 0.--2. "LINE_SELECTOR,Selects which line is read or written from the line memory array. The current line is updated at Start-Of-Line so if the memory is read during a line that is being written the data for the current_line will contain the new data for this.." "0: current line written,1: current line,2: current line,3: current line,4: current line,?,?,?" group.long 0x2010++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_DANDC_COM_CTRL,This register handles the general conrtrol bits for the DLUT CCM and CLUT blocks that preceed the CC module in the FCP." bitfld.long 0x0 27. "DISFIR3,Disables the FIR filter for C3 to save power" "0,1" newline bitfld.long 0x0 26. "DISFIR2,Disables the FIR filter for C2 to save power" "0,1" newline bitfld.long 0x0 25. "DISFIR1,Disables the FIR filter for C1 to save power" "0,1" newline bitfld.long 0x0 24. "DISFIR0,Disables the FIR filter for C0 to save power" "0,1" newline bitfld.long 0x0 10. "CMPDLUTEN,Enables the CLUT" "0,1" newline bitfld.long 0x0 9. "CCMEN,Enables the CCM" "0,1" newline bitfld.long 0x0 8. "DCMPDLUTEN,Enables the DLUT" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "LINEARBITWIDTH,Defines the DLUT output bit width the CCM clipping bit width and the CLUT input bit width valid values are 12-24. Values less than 12 12 will be used values greater than 24 24 will be used. Useful combinations are 12/16/20/24" group.long 0x2040++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH0_ICH1_0,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x0 16.--27. 1. "CCM_OCH0_ICH1,Defines the 12 bit signed wieght for the C0 output channel from the C1 input channel" newline hexmask.long.word 0x0 0.--11. 1. "CCM_OCH0_ICH0,Defines the 12 bit signed wieght for the C0 output channel from the C0 input channel" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH0_ICH3_2,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x4 16.--27. 1. "CCM_OCH0_ICH3,Defines the 12 bit signed wieght for the C0 output channel from the C3 input channel" newline hexmask.long.word 0x4 0.--11. 1. "CCM_OCH0_ICH2,Defines the 12 bit signed wieght for the C0 output channel from the C2 input channel" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH0_OFFSET,Defines the 26 bit signed S26Q24 offset for CCM" hexmask.long 0x8 0.--25. 1. "CCM_OCH0_OFFSET,Defines the 26 bit signed offset for the C0 output channel" group.long 0x2050++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH1_ICH1_0,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x0 16.--27. 1. "CCM_OCH1_ICH1,Defines the 12 bit signed wieght for the C1 output channel from the C1 input channel" newline hexmask.long.word 0x0 0.--11. 1. "CCM_OCH1_ICH0,Defines the 12 bit signed wieght for the C1 output channel from the C0 input channel" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH1_ICH3_2,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x4 16.--27. 1. "CCM_OCH1_ICH3,Defines the 12 bit signed wieght for the C1 output channel from the C3 input channel" newline hexmask.long.word 0x4 0.--11. 1. "CCM_OCH1_ICH2,Defines the 12 bit signed wieght for the C1 output channel from the C2 input channel" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH1_OFFSET,Defines the 26 bit signed S26Q24 offset for CCM" hexmask.long 0x8 0.--25. 1. "CCM_OCH1_OFFSET,Defines the 26 bit signed offset for the C1 output channel" group.long 0x2060++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH2_ICH1_0,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x0 16.--27. 1. "CCM_OCH2_ICH1,Defines the 12 bit signed wieght for the C2 output channel from the C1 input channel" newline hexmask.long.word 0x0 0.--11. 1. "CCM_OCH2_ICH0,Defines the 12 bit signed wieght for the C2 output channel from the C0 input channel" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH2_ICH3_2,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x4 16.--27. 1. "CCM_OCH2_ICH3,Defines the 12 bit signed wieght for the C2 output channel from the C3 input channel" newline hexmask.long.word 0x4 0.--11. 1. "CCM_OCH2_ICH2,Defines the 12 bit signed wieght for the C2 output channel from the C2 input channel" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH2_OFFSET,Defines the 26 bit signed S26Q24 offset for CCM" hexmask.long 0x8 0.--25. 1. "CCM_OCH2_OFFSET,Defines the 26 bit signed offset for the C2 output channel" group.long 0x2070++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH3_ICH1_0,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x0 16.--27. 1. "CCM_OCH3_ICH1,Defines the 12 bit signed wieght for the C3 output channel from the C1 input channel" newline hexmask.long.word 0x0 0.--11. 1. "CCM_OCH3_ICH0,Defines the 12 bit signed wieght for the C3 output channel from the C0 input channel" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH3_ICH3_2,Defines the 12 bit signed S12Q8 wieght for CCM" hexmask.long.word 0x4 16.--27. 1. "CCM_OCH3_ICH3,Defines the 12 bit signed wieght for the C3 output channel from the C3 input channel" newline hexmask.long.word 0x4 0.--11. 1. "CCM_OCH3_ICH2,Defines the 12 bit signed wieght for the C3 output channel from the C2 input channel" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CCM_OCH3_OFFSET,Defines the 26 bit signed S26Q24 offset for CCM" hexmask.long 0x8 0.--25. 1. "CCM_OCH3_OFFSET,Defines the 26 bit signed offset for the C3 output channel" group.long 0x2080++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_FIR_SCALES_1_0,Defines the FIR output scaler for FIR filters 1 and 0" hexmask.long.word 0x0 16.--29. 1. "FIR_SCALER1,Defines the U14Q8 scaler for FIR filter 1" newline hexmask.long.word 0x0 0.--13. 1. "FIR_SCALER0,Defines the U14Q8 scaler for FIR filter 0" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_FIR_SCALES_3_2,Defines the FIR output scaler for FIR filters 3 and 2" hexmask.long.word 0x4 16.--29. 1. "FIR_SCALER3,Defines the U14Q8 scaler for FIR filter 3" newline hexmask.long.word 0x4 0.--13. 1. "FIR_SCALER2,Defines the U14Q8 scaler for FIR filter 2" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_FIR_OFFSETS_1_0,Defines the FIR output offset for FIR filters 1 and 0" hexmask.long.word 0x8 16.--31. 1. "FIR_OFFSET1,Defines the U16 offset for FIR filter 1" newline hexmask.long.word 0x8 0.--15. 1. "FIR_OFFSET0,Defines the U16 offset for FIR filter 0" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_FIR_OFFSETS_3_2,Defines the FIR output offset for FIR filters 3 and 2" hexmask.long.word 0xC 16.--31. 1. "FIR_OFFSET3,Defines the U16 offset for FIR filter 3" newline hexmask.long.word 0xC 0.--15. 1. "FIR_OFFSET2,Defines the U16 offset for FIR filter 2" group.long 0x2C00++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CLUT0,The LUT table contains the information used to reduce the pixle width to 24 from 12" hexmask.long.word 0x0 16.--27. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." newline hexmask.long.word 0x0 0.--11. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." group.long 0x3100++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CLUT1,The LUT table contains the information used to reduce the pixle width to 24 from 12" hexmask.long.word 0x0 16.--27. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." newline hexmask.long.word 0x0 0.--11. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." group.long 0x3600++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CLUT2,The LUT table contains the information used to reduce the pixle width to 24 from 12" hexmask.long.word 0x0 16.--27. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." newline hexmask.long.word 0x0 0.--11. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." group.long 0x3B00++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_CLUT3,The LUT table contains the information used to reduce the pixle width to 24 from 12" hexmask.long.word 0x0 16.--27. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." newline hexmask.long.word 0x0 0.--11. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." group.long 0x4000++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_PIXEL_RAM,The pixel RAM contains the array of 16 bit pixels stored and used by the CFA logic. Pixels are 16 bit aligned. Pixels can only be written two at a time." hexmask.long.word 0x0 16.--31. 1. "PIXEL_HI,The 16 bit pixel data for the selected line upper pixel 'n+1'" newline hexmask.long.word 0x0 0.--15. 1. "PIXEL_LO,The 16 bit pixel data for the selected line lower pixel 'n'" group.long 0x100C++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_REGS_coef,Coefficients for a=core. b=dir. c=phase. d=row. column=e*2+1 and e*2" hexmask.long.word 0x0 16.--24. 1. "COEF_1,Coefficient - e*2+1" newline hexmask.long.word 0x0 0.--8. 1. "COEF_0,Coefficient - e*2" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_CFA_VBUSP_FLEXCFA_DLUTS" base ad:0x2C158000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_DLUTS_DLUT0,The LUT table contains the information used to expand the pixel width from 16 to 24" hexmask.long.tbyte 0x0 0.--23. 1. "LUT_ENTRY,The lower LUT entry" group.long 0x1000++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_DLUTS_DLUT1,The LUT table contains the information used to expand the pixel width from 16 to 24" hexmask.long.tbyte 0x0 0.--23. 1. "LUT_ENTRY,The lower LUT entry" group.long 0x2000++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_DLUTS_DLUT2,The LUT table contains the information used to expand the pixel width from 16 to 24" hexmask.long.tbyte 0x0 0.--23. 1. "LUT_ENTRY,The lower LUT entry" group.long 0x3000++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__CFA_VBUSP__FLEXCFA_DLUTS_DLUT3,The LUT table contains the information used to expand the pixel width from 16 to 24" hexmask.long.tbyte 0x0 0.--23. 1. "LUT_ENTRY,The lower LUT entry" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_EE_VBUSP_FLEXEE" base ad:0x2C150000 group.long 0x0++0x1B line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_EE_CFG_0,The Control Register controls the input width and height of the module." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,Height of the input image" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,Width of the input image" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_EE_CFG_1,The CEE route config Register controls the routing of trafic through and around the EE." bitfld.long 0x4 28. "YUV12_CL_ALIGN,Enables the alignment of the Chroma and Luma for the yuv12 stream. The aligner can align the Chroma and Luma +-19 pixel clocks. 1: Enable alignment. 0: Pass Chroma and Luma as they arrive." "0: Pass Chroma and Luma as they arrive,1: Enable alignment" newline bitfld.long 0x4 24. "YUV8_CL_ALIGN,Enables the alignment of the Chroma and Luma for the yuv8 stream. The aligner can align the Chroma and Luma +-19 pixel clocks. 1: Enable alignment. 0: Pass Chroma and Luma as they arrive." "0: Pass Chroma and Luma as they arrive,1: Enable alignment" newline bitfld.long 0x4 22. "EE_FE_MUX_SEL,Selects which data stream to pass through the EE block. 0: Selects the yuv12 stream. 1: selects the yuv8 stream." "0: Selects the yuv12 stream,1: selects the yuv8 stream" newline bitfld.long 0x4 18.--19. "SHIFTLEFT_NUM,Sects the amount to shift left the incoming pixel to the EE block. 0: No Shift. 1: Shift by 2. 2: Shift by 4. 3: Reserved for future expansion." "0: No Shift,1: Shift by 2,2: Shift by 4,3: Reserved for future expansion" newline bitfld.long 0x4 16.--17. "SHIFTRIGHT_NUM,Sects the amount to shift right the outgoing pixel from the EE block. 0: No Shift. 1: Shift by 2. 2: Shift by 4. 3: Reserved for future expansion." "0: No Shift,1: Shift by 2,2: Shift by 4,3: Reserved for future expansion" newline bitfld.long 0x4 12. "LLSE12_MUX_SEL,Selects Luma stream for the yuv12 output. 0: Bypass EE block. 1: Use EE Luma Output." "0: Bypass EE block,1: Use EE Luma Output" newline bitfld.long 0x4 8. "CLSE12_MUX_SEL,Selects Chroma stream for the yuv12 output. 0: Bypass EE block. 1: Use EE Chroma Output." "0: Bypass EE block,1: Use EE Chroma Output" newline bitfld.long 0x4 4. "LLSE8_MUX_SEL,Selects Luma stream for the yuv8 output. 0: Bypass EE block. 1: Use EE Luma Output." "0: Bypass EE block,1: Use EE Luma Output" newline bitfld.long 0x4 0. "CLSE8_MUX_SEL,Selects Chroma stream for the yuv8 output. 0: Bypass EE block. 1: Use EE Chroma Output." "0: Bypass EE block,1: Use EE Chroma Output" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_EE_ENABLE,The EE Enable register control the internal bypass of the EE block." bitfld.long 0x8 0. "YEE_ENABLE,The EE Enable register control the internal bypass of the EE block." "0,1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_SHIFT,The YEE Shift register controls the down shift length of high pass filter (HPF) in edge enhancer" hexmask.long.byte 0xC 0.--5. 1. "YEE_SHIFT,The down shift length of high pass filter (HPF) in edge enhancer takes the output of the 5x5 HPF and shifts it by the selected amount. Only values 0-31 are valid." line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R0_C0,The YEE Coefficient Row 0 Column 0 defines the Multiplier coefficient in HPF" hexmask.long.word 0x10 0.--9. 1. "YEE_COEF_R0_C0,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x14 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R0_C1,The YEE Coefficient Row 0 Column 1 defines the Multiplier coefficient in HPF" hexmask.long.word 0x14 0.--9. 1. "YEE_COEF_R0_C1,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x18 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R0_C2,The YEE Coefficient Row 0 Column 2 defines the Multiplier coefficient in HPF" hexmask.long.word 0x18 0.--9. 1. "YEE_COEF_R0_C2,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." group.long 0x20++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R1_C0,The YEE Coefficient Row 1 Column 0 defines the Multiplier coefficient in HPF" hexmask.long.word 0x0 0.--9. 1. "YEE_COEF_R1_C0,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R1_C1,The YEE Coefficient Row 1 Column 1 defines the Multiplier coefficient in HPF" hexmask.long.word 0x4 0.--9. 1. "YEE_COEF_R1_C1,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R1_C2,The YEE Coefficient Row 1 Column 2 defines the Multiplier coefficient in HPF" hexmask.long.word 0x8 0.--9. 1. "YEE_COEF_R1_C2,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." group.long 0x30++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R2_C0,The YEE Coefficient Row 2 Column 0 defines the Multiplier coefficient in HPF" hexmask.long.word 0x0 0.--9. 1. "YEE_COEF_R2_C0,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R2_C1,The YEE Coefficient Row 2 Column 1 defines the Multiplier coefficient in HPF" hexmask.long.word 0x4 0.--9. 1. "YEE_COEF_R2_C1,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_COEF_R2_C2,The YEE Coefficient Row 2 Column 2 defines the Multiplier coefficient in HPF" hexmask.long.word 0x8 0.--9. 1. "YEE_COEF_R2_C2,The Multiplier coefficient for the given row/col is used in the HPF and can range from -512 to 511." group.long 0x40++0x1F line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_E_THR,The Edge Enhancer lower threshold before referring to LUT." hexmask.long.word 0x0 0.--9. 1. "YEE_E_THR,The yee_e_thr is the Shrink Threshold before the LUT scaled by 16x." line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YEE_MERGESEL,The Merge selects the output that is added to the target pixel." bitfld.long 0x4 0. "YEE_MERGESEL,The yee_mergesel selects either the sum of the LUT and edge sharpener output of the max of the absolute values from both. 0: selects the SUM. 1: elects the absolute value max." "0: selects the SUM,1: elects the absolute value max" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YES_E_HAL,The Halo selects Halo reduction mode." bitfld.long 0x8 0. "YES_E_HAL,The yes_e_hal selects whether the 3x3 gradients is used to clip the target pixel. 0: Halo reduction off. 1: Halo reduction on." "0: Halo reduction off,1: Halo reduction on" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YES_G_GAIN,The Edge sharpener. gain value on gradient" hexmask.long.byte 0xC 0.--7. 1. "YES_G_GAIN,Sets the Gradient Gain value" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YES_E_GAIN,The Edge sharpener gain" hexmask.long.word 0x10 0.--11. 1. "YES_E_GAIN,Sets the Edge sharpener Band-pass filter gain" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YES_E_THR1,The Edge sharpener HPF value lower limit" hexmask.long.word 0x14 0.--15. 1. "YES_E_THR1,Sets the Edge sharpener HPF value lower limit shrink threshold" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YES_E_THR2,The Edge sharpener HPF value upper limit (after 6 bit right shift)" hexmask.long.word 0x18 0.--9. 1. "YES_E_THR2,Sets the Edge sharpener HPF value upper limit (after 6 bit right shift) clip threshold" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_YES_G_OFT,The Edge sharpener. offset value on gradient" hexmask.long.word 0x1C 0.--9. 1. "YES_G_OFT,Sets the Edge sharpener offset value on gradient" group.long 0x100++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_INT_STATUS,Status/clear register for flexee interrupts" bitfld.long 0x0 3. "EE_HZ_ALIGN8,status/clear for EE horizontal aligner yuv8 overflow error indicates that the luma and chroma line starts were not within hardware synchronization limits. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x0 2. "EE_HZ_ALIGN12,status/clear for EE horizontal aligner yuv12 overflow error indicates that the luma and chroma line starts were not within hardware synchronization limits. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x0 1. "EE_PIX_ERR,status/clear for error on line array set when software accesses EE pixel array during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" newline bitfld.long 0x0 0. "EELUT_CFG_ERR,status/clear for error on EE LUT cfg set when software accesses EE LUT during active frame causing potential frame corruption. Write 1 to clear write 0 has no effect." "0,1" group.long 0x1008++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_LINE_SEL,Selector for which line memory is read or written" bitfld.long 0x0 0.--2. "LINE_SELECTOR,Selects which line is read or written from the line memory array. The current line is updated at Start-Of-Line so if the memory is read during a line that is being written the data for the current_line will contain the new data for this.." "0: current line written,1: current line,2: current line,3: current line,4: current side band line,5: current side band line,?,?" group.long 0x2000++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_EELUT_RAM,The host will program the EE LUT RAM so that the pixels are translated from 14 bit to 12 bit using LUT entries." hexmask.long.word 0x0 16.--28. 1. "EELUT_ENTRY_HI,The lower EE LUT entry n+1." newline hexmask.long.word 0x0 0.--12. 1. "EELUT_ENTRY_LO,The lower EE LUT entry n+0." group.long 0x4000++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__EE_VBUSP__FLEXEE_REGS_PIXEL_RAM,The pixel RAM contains the array of 12 bit pixels stored and used by the CFA logic. Pixels are 16 bit aligned. Pixels can only be written two at a time." hexmask.long.word 0x0 16.--27. 1. "PIXEL_HI,The 12 bit pixel data for the selected line upper pixel 'n+1'" newline hexmask.long.word 0x0 0.--11. 1. "PIXEL_LO,The 12 bit pixel data for the selected line lower pixel 'n'" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC" base ad:0x2C110000 group.long 0x0++0x6B line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CFG_0,The Control Register controls the input width and height of the module." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,Height of the input image" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,Width of the input image" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CFG_1,Configuration Register for top level data flow" bitfld.long 0x4 27. "CHROMA_MODE,Mux for 422/420 (0:420 Chroma 1: 422 Chroma)" "0: 420 Chroma,1: 422 Chroma" newline bitfld.long 0x4 26. "MUXRGBHSV_MUX_V,Mux for V calculation (0:Select non WB corrected data 1: Select WB corrected data)" "0: Select non WB corrected data,1: Select WB corrected data" newline bitfld.long 0x4 25. "MUXRGBHSV_H2,Mux for S/V calculation (0:Select B 1: Select Max(RGB))" "0: Select B,1: Select Max" newline bitfld.long 0x4 24. "MUXRGBHSV_H1,Mux for S/V calculation (0:Select R 1: Select Min(RGB))" "0: Select R,1: Select Min" newline bitfld.long 0x4 18.--19. "S8B8OUTEN,'0': Disable All '1': S8 enable 2:B8 enable 3:C4 enable" "0: Disable All,1: S8 enable,2: B8 enable,3: C4 enable" newline bitfld.long 0x4 16.--17. "C8G8OUTEN,'0': Disable All '1': C8 enable 2:G8 enable 3:C3 enable" "0: Disable All,1: C8 enable,2: G8 enable,3: C3 enable" newline bitfld.long 0x4 14.--15. "Y8R8OUTEN,'0': Disable all '1': Y8 enable 2:R8 enable 3:C2 enable" "0: Disable all,1: Y8 enable,2: R8 enable,3: C2 enable" newline bitfld.long 0x4 12.--13. "C12OUTEN,'0': Disable all '1': C12 enable '2': C1 enable" "0: Disable all,1: C12 enable,2: C1 enable,?" newline bitfld.long 0x4 11. "Y12OUTEN,'0': Disable Y12 output '1': Enable Y12 output" "0: Disable Y12 output,1: Enable Y12 output" newline bitfld.long 0x4 6. "MUXRGBHSV,Input Select for RGBHSV (0:In after Contrast 1: In before Contrast)" "0: In after Contrast,1: In before Contrast" newline bitfld.long 0x4 4.--5. "MUXY8_OUT,Mux for Y-8 Output (0:MuxC1_4 1:RGB2YUV 2:RGB2HSV)" "0: MuxC1_4,1: RGB2YUV,2: RGB2HSV,?" newline bitfld.long 0x4 2.--3. "MUXY12_OUT,Mux for Y-12 Output (0:MuxC1_4 1:RGB2YUV 2:RGB2HSV 3:C1 enable)" "0: MuxC1_4,1: RGB2YUV,2: RGB2HSV,3: C1 enable" newline bitfld.long 0x4 0.--1. "MUXC1_4,Mux for selecting C input (0:C0 1:C1 2:C2 3:C3)" "0: C0,1: C1,2: C2,3: C3" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CFG_2,Configuration Register-2" hexmask.long.byte 0x8 13.--16. 1. "Y8INBITWIDTH,Bitwidth of input to 12to8 module (Y8) for shift(Program as 12 or lower)" newline hexmask.long.byte 0x8 9.--12. 1. "CONTRASTBITCLIP,Clip Value set as 2^ContrastBitClip -1" newline bitfld.long 0x8 8. "CONTRASTEN,0:Disable 1: Enable Contrast" "0: Disable,1: Enable Contrast" newline bitfld.long 0x8 6. "HSVSATMODE,0:Max(RGB) - Min(RGB) 1:Sum(RGB) - Min(RGB)" "0: Max,1: Sum" newline bitfld.long 0x8 4.--5. "HSVSATDIVMODE,0:One 1:Max(RGB) 2: 4095 -V 3:Sum(RGB)" "0: One,1: Max,2: 4095 -V,3: Sum" newline bitfld.long 0x8 3. "SATLUTEN,'1':Use LUT '0':Use shift" "0: Use shift,1: Use LUT" newline bitfld.long 0x8 2. "RGB8LUTEN,'1':Use LUT '0':Use shift" "0: Use shift,1: Use LUT" newline bitfld.long 0x8 1. "Y8LUTEN,'1':Use LUT '0':Use shift" "0: Use shift,1: Use LUT" newline bitfld.long 0x8 0. "C8LUTEN,'1':Use LUT '0':Use shift" "0: Use shift,1: Use LUT" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CFG_Hist_1,Configuration-1 Register for histogram" hexmask.long.word 0xC 16.--28. 1. "HISTSTARTY,Y Start for Histogram ROI should be >= 1" newline bitfld.long 0xC 14. "BANK,bank select for Histogram" "0,1" newline hexmask.long.word 0xC 1.--13. 1. "HISTSTARTX,X Start for Histogram ROI should be even" newline bitfld.long 0xC 0. "HISTEN,Enable bit for histogram" "0,1" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CFG_Hist_2,Configuration-2 Register for histogram" hexmask.long.word 0x10 16.--28. 1. "HISTSIZEY,Y Size (Height) for Histogram ROI" newline bitfld.long 0x10 13.--15. "HISTMODE,Histogram Mode 0:Col-0(R) 1:Col-1(G) 2:Col-2(B) 3:MuxC1_4 4:(R+2G+B)/4 5:Col-0(R)" "0: Col-0,1: Col-1,2: Col-2,3: MuxC1_4,4: (R+2G+B,5: Col-0,?,?" newline hexmask.long.word 0x10 0.--12. 1. "HISTSIZEX,X Size (Width) for Histogram ROI should be > 256 & even" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_W0_0_1,CCM Weights for Row0" hexmask.long.word 0x14 16.--27. 1. "W_1,Weight W_01 : (S12 b)" newline hexmask.long.word 0x14 0.--11. 1. "W_0,Weight W_00 : (S12 b)" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_W0_2_3,CCM Weights for Row0" hexmask.long.word 0x18 16.--27. 1. "W_3,Weight W_03 : (S12 b)" newline hexmask.long.word 0x18 0.--11. 1. "W_2,Weight W_02 : (S12 b)" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_OFFSET_0,CCM OFFSET for Row0" hexmask.long.word 0x1C 0.--12. 1. "OFFSET_0,OFFSET_0 : (S13 b)" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_W1_0_1,CCM Weights for Row1" hexmask.long.word 0x20 16.--27. 1. "W_1,Weight W_11 : (S12 b)" newline hexmask.long.word 0x20 0.--11. 1. "W_0,Weight W_10 : (S12 b)" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_W1_2_3,CCM Weights for Row1" hexmask.long.word 0x24 16.--27. 1. "W_3,Weight W_13 : (S12 b)" newline hexmask.long.word 0x24 0.--11. 1. "W_2,Weight W_12 : (S12 b)" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_OFFSET_1,CCM OFFSET for Row1" hexmask.long.word 0x28 0.--12. 1. "OFFSET_1,OFFSET_1 : (S13 b)" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_W2_0_1,CCM Weights for Row2" hexmask.long.word 0x2C 16.--27. 1. "W_1,Weight W_21 : (S12 b)" newline hexmask.long.word 0x2C 0.--11. 1. "W_0,Weight W_20 : (S12 b)" line.long 0x30 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_W2_2_3,CCM Weights for Row2" hexmask.long.word 0x30 16.--27. 1. "W_3,Weight W_23 : (S12 b)" newline hexmask.long.word 0x30 0.--11. 1. "W_2,Weight W_22 : (S12 b)" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_CCM_OFFSET_2,CCM OFFSET for Row2" hexmask.long.word 0x34 0.--12. 1. "OFFSET_2,OFFSET_2 : (S13 b)" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W01,Weight/Offset for Row0" hexmask.long.word 0x38 16.--27. 1. "W_02,Weight W_02 : (S12 b)" newline hexmask.long.word 0x38 0.--11. 1. "W_01,Weight W_01 : (S12 b)" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W02,Weight/Offset for Row0" hexmask.long.word 0x3C 16.--28. 1. "OFFSET_0,Offset_0 : (S13b)" newline hexmask.long.word 0x3C 0.--11. 1. "W_03,Weight W_03 : (S12 b)" line.long 0x40 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W11,Weight/Offset for Row1" hexmask.long.word 0x40 16.--27. 1. "W_12,Weight W_12 : (S12 b)" newline hexmask.long.word 0x40 0.--11. 1. "W_11,Weight W_11 : (S12 b)" line.long 0x44 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W12,Weight/Offset for Row1" hexmask.long.word 0x44 16.--28. 1. "OFFSET_1,Offset_1 : (S13b)" newline hexmask.long.word 0x44 0.--11. 1. "W_13,Weight W_13 : (S12 b)" line.long 0x48 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W21,Weight/Offset for Row2" hexmask.long.word 0x48 16.--27. 1. "W_22,Weight W_22 : (S12 b)" newline hexmask.long.word 0x48 0.--11. 1. "W_21,Weight W_21 : (S12 b)" line.long 0x4C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBYUV_W22,Weight/Offset for Row2" hexmask.long.word 0x4C 16.--28. 1. "OFFSET_2,Offset_2 : (S13b)" newline hexmask.long.word 0x4C 0.--11. 1. "W_23,Weight W_23 : (S12 b)" line.long 0x50 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBHSV_W0,Weights 11/12 for V calculation" hexmask.long.word 0x50 16.--27. 1. "W12,Weight W12 (Signed 12b)" newline hexmask.long.word 0x50 0.--11. 1. "W11,Weight W11 (Signed 12b)" line.long 0x54 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBHSV_W1,Weights13 and Offset_1 for V Calculation" hexmask.long.word 0x54 16.--28. 1. "OFFSET_1,Offset_1 (Signed 13b)" newline hexmask.long.word 0x54 0.--11. 1. "W13,Weight W13 (Signed 12b)" line.long 0x58 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBHSV_WB_LINLOGTHR_1,Dynamic WB Thr limit" hexmask.long.word 0x58 16.--27. 1. "THR_1,THR_1 / G-Channel Thr (U 12b)" newline hexmask.long.word 0x58 0.--11. 1. "THR_0,THR_0 / R-Channel Thr (U 12b)" line.long 0x5C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBHSV_WB_LINLOGTHR_2,Dynamic WB Thr limit and SatMinThr" hexmask.long.word 0x5C 16.--27. 1. "SATMINTHR,Thr for comparing Min(RGB) limit" newline hexmask.long.word 0x5C 0.--11. 1. "THR_2,THR_2 / B-Channel Thr (U 12b)" line.long 0x60 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBHSV_OFF1,WB Offset for Saturation" hexmask.long.word 0x60 16.--27. 1. "OFFSET_2,Offset_2 (U 12b)" newline hexmask.long.word 0x60 0.--11. 1. "OFFSET_1,Offset-1 (U 12b)" line.long 0x64 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_RGBHSV_OFF2,WB Offsets for Saturation" hexmask.long.word 0x64 0.--11. 1. "OFFSET_3,Offset-3 (U 12b)" line.long 0x68 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_FLEXCC_INT_STATUS,Status/clear register for flexcc interrupts" bitfld.long 0x68 11. "HIST_READ_ERR,status/clear for histogram memory set when mem access has occurred to the first location but not to the last location during active frame implying that full histogram was not read . Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 10. "LUT_12TO82_CFG_ERR,status/clear for 12to8_2_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 9. "LUT_12TO81_CFG_ERR,status/clear for 12to8_1_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 8. "LUT_12TO80_CFG_ERR,status/clear for 12to8_0_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 7. "CONTRAST2_CFG_ERR,status/clear for contrast2_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 6. "CONTRAST1_CFG_ERR,status/clear for contrast1_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 5. "CONTRAST0_CFG_ERR,status/clear for contrast0_lut cfg err set when mem access occurs during active line when the LUT is enabled causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 4. "OVERFLOW_IF_S8B8,status/clear for overflow on s8b8 i/f set when fifo overflows causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 3. "OVERFLOW_IF_C8G8,status/clear for overflow on c8g8 i/f set when fifo overflows causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 2. "OVERFLOW_IF_Y8R8,status/clear for overflow on y8r8 i/f set when fifo overflows causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 1. "OVERFLOW_IF_UV12,status/clear for overflow on uv12 i/f set when fifo overflows causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" newline bitfld.long 0x68 0. "OVERFLOW_IF_Y12,status/clear for overflow on y12 i/f set when fifo overflows causing frame corruption. Write 1 to clear write 0 has no effect" "0,1" group.long 0x100++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_DEBUG_CTL,Enable for different debug events" bitfld.long 0x0 12. "FLEXCC_EOP_EN,Enable for flexcc eop" "0,1" newline bitfld.long 0x0 11. "EOF_IF_S8B8_EN,Enable for eof on s8b8" "0,1" newline bitfld.long 0x0 10. "EOL_IF_S8B8_EN,Enable for eol on s8b8" "0,1" newline bitfld.long 0x0 9. "EOF_IF_C8G8_EN,Enable for eof on c8g8" "0,1" newline bitfld.long 0x0 8. "EOL_IF_C8G8_EN,Enable for eol on c8g8" "0,1" newline bitfld.long 0x0 7. "EOF_IF_Y8R8_EN,Enable for eof on y8r8" "0,1" newline bitfld.long 0x0 6. "EOL_IF_Y8R8_EN,Enable for eol on y8r8" "0,1" newline bitfld.long 0x0 5. "EOF_IF_UV12_EN,Enable for eof on uv12" "0,1" newline bitfld.long 0x0 4. "EOL_IF_UV12_EN,Enable for eol on uv12" "0,1" newline bitfld.long 0x0 3. "EOF_IF_Y12_EN,Enable for eof on y12" "0,1" newline bitfld.long 0x0 2. "EOL_IF_Y12_EN,Enable for eol on y12" "0,1" newline bitfld.long 0x0 1. "STALL_EN,Enable for stall event" "0,1" newline bitfld.long 0x0 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_DEBUG_STATUS,Set/Clear for debug events" bitfld.long 0x4 12. "FLEXCC_EOP_EVENT,Status/Clear for flexcc eop write '1' to clear" "0,1" newline bitfld.long 0x4 11. "EOF_IF_S8B8_EVENT,Status/Clear for eof on s8b8 write '1' to clear" "0,1" newline bitfld.long 0x4 10. "EOL_IF_S8B8_EVENT,Status/Clear for eol on s8b8 write '1' to clear" "0,1" newline bitfld.long 0x4 9. "EOF_IF_C8G8_EVENT,Status/Clear for eof on c8g8 write '1' to clear" "0,1" newline bitfld.long 0x4 8. "EOL_IF_C8G8_EVENT,Status/Clear for eol on c8g8 write '1' to clear" "0,1" newline bitfld.long 0x4 7. "EOF_IF_Y8R8_EVENT,Status/Clear for eof on y8r8 write '1' to clear" "0,1" newline bitfld.long 0x4 6. "EOL_IF_Y8R8_EVENT,Status/Clear for eol on y8r8 write '1' to clear" "0,1" newline bitfld.long 0x4 5. "EOF_IF_UV12_EVENT,Status/Clear for eof on uv12 write '1' to clear" "0,1" newline bitfld.long 0x4 4. "EOL_IF_UV12_EVENT,Status/Clear for eol on uv12 write '1' to clear" "0,1" newline bitfld.long 0x4 3. "EOF_IF_Y12_EVENT,Status/Clear for eof on y12 write '1' to clear" "0,1" newline bitfld.long 0x4 2. "EOL_IF_Y12_EVENT,Status/Clear for eol on y12 write '1' to clear" "0,1" newline bitfld.long 0x4 1. "STALL_EVENT,Status/Clear for stall event write '1' to clear" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_REGS_DEBUG_RAW,Set/Clear for debug RAW mode" bitfld.long 0x8 0. "DBG_RAW_MODE,Enable debug RAW mode takes input from RAWFE and delivers to FlexCC as C1={raw[11:0]} C2={4'd0 raw[7:0]} C3={4'd0 raw[15:8]} c4={8'd0 raw[15:12]}" "0,1" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_C8G8" base ad:0x2C112800 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_C8G8_LUT_C8G8,Memory for 12to8 LUT" hexmask.long.byte 0x0 16.--23. 1. "LUT_1,Bank-1" hexmask.long.byte 0x0 0.--7. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC1" base ad:0x2C110800 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_CONTRASTC1_LUT_contrastC1,Memory for contrast C1" hexmask.long.word 0x0 16.--27. 1. "LUT_1,Bank-1" hexmask.long.word 0x0 0.--11. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC2" base ad:0x2C111000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_CONTRASTC2_LUT_contrastC2,Memory for contrast C1" hexmask.long.word 0x0 16.--27. 1. "LUT_1,Bank-1" hexmask.long.word 0x0 0.--11. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC3" base ad:0x2C111800 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_CONTRASTC3_LUT_contrastC3,Memory for contrast C1" hexmask.long.word 0x0 16.--27. 1. "LUT_1,Bank-1" hexmask.long.word 0x0 0.--11. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_HIST" base ad:0x2C113800 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_HIST_HIST,Memory for Histogram" hexmask.long.tbyte 0x0 0.--19. 1. "HIST_VAL,Bank-0" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_LINE" base ad:0x2C118000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_LINE_LINE_MEM,Memory for 2 lines of yuv444to420" hexmask.long.word 0x0 16.--27. 1. "LINE_1,Line-1" hexmask.long.word 0x0 0.--11. 1. "LINE_0,Line-0" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_S8B8" base ad:0x2C113000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_S8B8_LUT_S8B8,Memory for 12to8 LUT" hexmask.long.byte 0x0 16.--23. 1. "LUT_1,Bank-1" hexmask.long.byte 0x0 0.--7. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_Y8R8" base ad:0x2C112000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_FCP__FCC_VBUSP__FLEXCC_Y8R8_LUT_Y8R8,Memory for 12to8 LUT" hexmask.long.byte 0x0 16.--23. 1. "LUT_1,Bank-1" hexmask.long.byte 0x0 0.--7. 1. "LUT_0,Bank-0" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MEM_MMRRAM_VBUSP_MMR_RAM" base ad:0x2C144000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MEM_MMR__MMRRAM_VBUSP__MMR_RAM_DBG_MEM,Warning: reading or writing this MMR during operation will corrupt processing resulting in bad output data and will result in error interrupt firing." hexmask.long 0x0 0.--31. 1. "DATA,Adr range selects which RAM address to index. (Wr or rd beyond populated RAM adr result in non productive cycles and rd returns zero)" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MMR_VBUSP_NSF4VCORE" base ad:0x2C140000 group.long 0x4++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_dbg,Diagnostic Register Control" hexmask.long.byte 0x0 0.--5. 1. "RAM_MUX_CFG,Diagnostic Rd Wr access to Embedded RAM Selector Mux. This bit controls the mux select or which RAM and which section of that RAM are assessed via the VBUSP read of RAM. (This MMR is not shadowed)" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_ctrl,All modes are set here" bitfld.long 0x4 12. "LSCC_EN_CFG,enable Lens Shading Correction Compensation. When disabled implments a unity gain" "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "LSCC_SETSEL_CFG,bit per BAYER color component indicating which of two sets of 16 segment PWL Curve to use for LSCC. 0: use set0 1: use set1" newline bitfld.long 0x4 4. "TN_MODE_CFG,single bit controlling T_n calculation 0: use u_mode bits to indicate which LL2 to average and which bits to keep independent without averaging 1: independent no averaging" "0: use u_mode bits to indicate which LL2 to average..,1: independent no averaging" newline hexmask.long.byte 0x4 0.--3. 1. "U_MODE_CFG,bit per BAYER color component indicating Decomp sub component 0: average with others 1: independent color component do not average for calculation of U Suppress. bit[0]:color 0 at (v=0 h=0) bit[1]:color 1 at (v=0 h=1) bit[2]:color 2.." line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_dim,Input Output Frame dimensions in units of pixels. Same value for input and output" hexmask.long.word 0x8 16.--28. 1. "IH_CFG,(U13) input height in units of pixels minus 1." newline hexmask.long.word 0x8 0.--12. 1. "IW_CFG,(U13) input width in units of pixels minus 1. Max usable value determined by populated line buffer RAM size" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_LSCC,Lens Shading Correction Compensation. First control register" hexmask.long.word 0xC 20.--28. 1. "GMAX_CFG,(U4.5) LSCC maximum gain. Any calculated value is clipped to this max value" newline hexmask.long.byte 0xC 16.--19. 1. "T_CFG,(U4) LSCC radius dynamic range select. T is the right shift amount prior to MSB clip." newline hexmask.long.byte 0xC 8.--15. 1. "KV_CFG,(U2.6) LSCC horizontal or Y Gain for elliptical lens" newline hexmask.long.byte 0xC 0.--7. 1. "KH_CFG,(U2.6) LSCC vertical or X Gain for elliptical lens" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_LSCC_cent,Lens Shading Correction Compensation. Programmable Center of frame" hexmask.long.word 0x10 16.--29. 1. "Y_CFG,(S14) Vertical (Y) position of lens center. Negative value supports the case where processed frame starts after the center. HW supports center config with below constraint. if (Y_cfg < 0) # negative DIM.ih_cfg + abs(Y_cfg) < 8K else #.." newline hexmask.long.word 0x10 0.--13. 1. "X_CFG,(S14) Horizontal (X) position of lens center. Negative value supports the case where processed frame starts after the center. HW supports center config with below constraint. if (X_cfg < 0) # negative DIM.iw_cfg + abs(X_cfg) < 8K else #.." group.long 0x1C++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_Tn_Scale,Tn scaling factor multiplied by all 4 color components Tn after 12 segment PWL. Different scaling factor per level" hexmask.long.byte 0x0 16.--23. 1. "TN3_CFG,(U3.5) Level3. Sub-bands 7 8 9" newline hexmask.long.byte 0x0 8.--15. 1. "TN2_CFG,(U3.5) Level2. Sub-bands 4 5 6" newline hexmask.long.byte 0x0 0.--7. 1. "TN1_CFG,(U3.5) Level1. Sub-bands 0 1 2" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_U_knee,U suppression curve knee. Same knee value for all 9 levels x 4 color components." hexmask.long.byte 0x4 0.--5. 1. "U_KNEE_CFG,(U0.6) U Suppress curve knee. X (LL2) value which separates constant suppression of 1.0 from linear suppression." line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_WhiteBal0,White Balance Gain (Part0). Separate Gain for each of 4 colors" hexmask.long.word 0x8 16.--28. 1. "GAIN1_CFG,(U4.9) Gain for color 1" newline hexmask.long.word 0x8 0.--12. 1. "GAIN0_CFG,(U4.9) Gain for color 0" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_WhiteBal1,White Balance Gain (Part1). Separate Gain for each of 4 colors" hexmask.long.word 0xC 16.--28. 1. "GAIN3_CFG,(U4.9) Gain for color 3" newline hexmask.long.word 0xC 0.--12. 1. "GAIN2_CFG,(U4.9) Gain for color 2" group.long 0x3F0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_DWB_CNTL,Dynamic White Balance Control Register" bitfld.long 0x0 0. "DWB_EN,Dynamic White Balance Enable" "0,1" group.long 0x5F0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_Hist_Ctrl,Has control parameters related to Raw Domain Histogram" hexmask.long.byte 0x0 16.--23. 1. "ROI_EN,Enable for ROIs. Each bit corresponds to one ROI. bit[x] to ROI[x]. Use lower index regions if less than 8 regions are needed." newline hexmask.long.byte 0x0 9.--13. 1. "INBITWDTH,BitWidth of the input image values greater than 16 will be treated as 16 and values less than 12 will be treated as 12" newline bitfld.long 0x0 8. "LUT_EN,0->Use shift(bitwidth-12) 1->Use LUT" "0,1" newline bitfld.long 0x0 5. "BANK,Bank attached to Histogram HW Datapath. Shadowed and internal control is updated outisde of active frame 0 -> HW access Bank0 & Cfg MMR access Bank1 1 -> HW access Bank1 & Cfg MMR access Bank0." "0: HW access Bank0 & Cfg MMR access Bank1,1: HW access Bank1 & Cfg MMR access Bank0" newline hexmask.long.byte 0x0 1.--4. 1. "PHASESEL,Histogram Phase select enable; one bit for each color channel. Up to 2 bits can be enabled; only bit can be enabled per line. bit[0]:color 0 at (v=0 h=0) bit[1]:color 1 at (v=0 h=1) bit[2]:color 2 at (v=1 h=0) bit[3]:color 3 at (v=1 h=1)" newline bitfld.long 0x0 0. "HIST_EN,Raw domain Histogram Enable. When enbaled minimum frame width has to be 128" "0,1" group.long 0x500++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_dwb_wght01,Weights to calculate intensity" hexmask.long.word 0x0 16.--24. 1. "W1,U9Q8 Weight1" newline hexmask.long.word 0x0 0.--8. 1. "W0,U9Q8 Weight0" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_dwb_wght23,Weights to calculate intensity" hexmask.long.word 0x4 16.--24. 1. "W3,U9Q8 Weight3" newline hexmask.long.word 0x4 0.--8. 1. "W2,U9Q8 Weight2" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_dwb_wght45,Weights to calculate intensity" hexmask.long.word 0x8 16.--24. 1. "W5,U9Q8 Weight5" newline hexmask.long.word 0x8 0.--8. 1. "W4,U9Q8 Weight4" group.long 0x600++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_Start,Start Pixel location for the region" hexmask.long.word 0x0 16.--28. 1. "STARTY,Valid line start Vertically. Needs to be even. Minimum is 2 and should be greater than previous region EndY" newline hexmask.long.word 0x0 0.--12. 1. "STARTX,Valid pixel start Horizontally. Has to be even" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_End,End Pixel location for the region" hexmask.long.word 0x4 16.--28. 1. "ENDY,Valid line end Vertically. Min region height is 8 and region height has to be even" newline hexmask.long.word 0x4 0.--12. 1. "ENDX,Valid pixel end Horizontally. Min region width is 8 and region width has to be even" group.long 0x60++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_tn0,T_n 12 segment piecewise linear curve Part0 (4 color x 12 segment)" hexmask.long.word 0x0 16.--30. 1. "Y_CFG,(U15) Y (U) value. T_n resulting value from lookup. Starting point from which SLOPE will linearly calculate between X Y points" newline hexmask.long.word 0x0 0.--15. 1. "X_CFG,(U16) X (LL2) value. LL2 averaged input value into lookup rounded down to nearest X value. (X0 programmed value is unused and defaults to a value of 0 in hardware implementation)" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_tn1,T_n 12 segment piecewise linear curve Part1 (4 color x 12 segment)" hexmask.long.word 0x4 0.--15. 1. "S_CFG,(S5.11) S value. Slope value used calculated linear interpolation between X Y points" group.long 0x200++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_lsccCurve0,LSCC 16 segment piecewise linear curve Part0 (2 set x 16 segment)" hexmask.long.word 0x0 16.--24. 1. "Y_CFG,(U15.0) Y (U) value. LSCC Gain resulting value from lookup. Starting point from which SLOPE will linearly calculate between X Y points" newline hexmask.long.word 0x0 0.--15. 1. "X_CFG,(U16) X (normalized radius from center) value. Input rounded down to nearest X value. (X0 programmed value is unused and defaults to a value of 0 in hardware implementation)" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_lsccCurve1,LSCC 16 segment piecewise linear curve Part1 (2 set x 16 segment)" hexmask.long.word 0x4 0.--15. 1. "S_CFG,(S5.11) S value. Slope value used calculated linear interpolation between X Y points" group.long 0x400++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_dwbCurve0,Dynamic WB 8 segment piecewise linear curve Part0. 4 color x 8 segment" hexmask.long.word 0x0 16.--27. 1. "Y_CFG,U12Q8 Y Reference value from the segment. Starting point from which SLOPE will linearly calculate between X Y points" newline hexmask.long.word 0x0 0.--15. 1. "X_CFG,U16 X Intesity value. X0 programmed value is unused and defaults to a value of 0 in hardware implementation" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__MMR__MMR_VBUSP__NSF4VCORE_REG_dwbCurve1,Dynamic WB 8 segment piecewise linear curve Part1 (4 color x 8 segment)" hexmask.long.word 0x4 0.--15. 1. "S_CFG,S16Q12 Slope value for the segment. Slope value used calculated linear interpolation between X Y points" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_RAWHIST_HISTDATA_VBUSP_RAWHIST" base ad:0x2C140800 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__RAWHIST__HISTDATA_VBUSP__RAWHIST_HIST,Memory for Histogram" hexmask.long.tbyte 0x0 0.--21. 1. "HIST_VAL,Histogram Data" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_RAWHIST_HISTLUT_VBUSP_RAWHIST_LUT" base ad:0x2C141000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_NSF4V__CFG__RAWHIST__HISTLUT_VBUSP__RAWHIST_LUT_HIST_LUT,LUT to convert from 16-bit to 12-bit" hexmask.long.word 0x0 16.--27. 1. "LUT_1,Entry 2*n+1 in Bank-1" hexmask.long.word 0x0 0.--11. 1. "LUT_0,Entry 2*n in Bank-0" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_PCID_S_VBUSP_CFG_LINEMEM_CFG_LINE_MEM" base ad:0x2C18C000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__CFG_LINEMEM__LINEMEM_CFG__LINE_MEM_MEM,Only full 32-bit access it allowed" hexmask.long 0x0 0.--31. 1. "PIXD,No Byte or Word Access. Only full 32-bit access it allowed. When IrSubtraction factor line memory is seleted only LSB 18-bit are valid" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_PCID_S_VBUSP_IR_REMAPLUT_LUT_CFG_IRREMAP_LUT" base ad:0x2C188800 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__IR_REMAPLUT__LUT_CFG__IRREMAP_LUT_LUT,Only full 32-bit access it allowed" hexmask.long.word 0x0 16.--31. 1. "LUT_ENTRY_HI,The upper LUT entry n+1." hexmask.long.word 0x0 0.--15. 1. "LUT_ENTRY_LO,The lower LUT entry n+0." tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_PCID_S_VBUSP_MMRCFG_PCID" base ad:0x2C188000 group.long 0x4++0x2F line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__MMR__MMRCFG__PCID_REGS_CTRL,Control Register to Enable/Disable and select modes of operation" bitfld.long 0x0 12.--14. "CFAFORMAT,Position of RED in first 4x2 window of 4x4 pixel RGBIR pixel pattern. configure such that RED pixel will be at [row%2]*4+col%4 in 4x4 RGBIR pixel pattern" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "IRREMAPLUTEN,Enable for IR Remap LUT. 0 : Disable IR remap LUT. IR data sent directly 1 : Enable IR Remap LUT function" "0: Disable IR remap LUT,1: Enable IR Remap LUT function" newline bitfld.long 0x0 6. "BAYEROUTSEL,Control to select Bayer or IR to output on Bayer output channel. 0 : IR Subtracted bayer is sent 1: Pre Remap Lut IR is sent" "0: IR Subtracted bayer is sent,1: Pre Remap Lut IR is sent" newline bitfld.long 0x0 5. "IRSUBTRACTFILTEN,Control for smoothening filtering of IR Subtraction Factor. 0 : smoothening Filter is disabled 1 : smoothening Filter is enabled Valid when IRSubtractEn is set" "0: smoothening Filter is disabled,1: smoothening Filter is enabled Valid when.." newline bitfld.long 0x0 4. "IRSUBTRACTEN,Control for IR Subtraction from Bayer output. 0 : IR subtraction from Bayer is disabled 1 : IR subtraction from Bayer is enabled" "0: IR subtraction from Bayer is disabled,1: IR subtraction from Bayer is enabled" newline bitfld.long 0x0 3. "RBINTPATIR,Output color on IR pixels. 0 : Interpolate B at IR positions and R at B locations 1: Interpolate R at IR positions and B at R locations" "0: Interpolate B at IR positions and R at B locations,1: Interpolate R at IR positions and B at R locations" newline bitfld.long 0x0 2. "RBIRINTPMETHOD,Interpolation method used for RB and IR upsampling interpolation. 0 : Constant Hue 1 : Color Difference" "0: Constant Hue,1: Color Difference" newline bitfld.long 0x0 1. "IROUTEN,Control to output IR Output Channel by PCID block. 0 : Disable 1 : Enable Note that IR needs to calculated internally for IR subtraction" "0: Disable,1: Enable Note that IR needs to calculated.." newline bitfld.long 0x0 0. "BAYEROUTEN,Control to output data on Bayer Output Channel by PCID block. 0 : Disable 1 : Enable" "0: Disable,1: Enable" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__MMR__MMRCFG__PCID_REGS_FRAMESZ,Actual frame size is configured value + 1" hexmask.long.word 0x4 16.--28. 1. "HEIGHT,Number of Lines per frame. Actual Frame height is HEIGHT +1. Actual frame height should minimum of 32 and multiple of 4. Max width supported is 8188" newline hexmask.long.word 0x4 0.--12. 1. "WIDTH,Number of pixels per line. Actual Frame width is WIDTH +1. Actual frame width should minimum of 64 and multiple of 4. Max width supported by logic is 8192 and limited by line memory size of 2688" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__MMR__MMRCFG__PCID_REGS_RBIrIntPCFG1,Threshold Configuration for R/B/Ir interpoaltion processing" hexmask.long.word 0x8 16.--31. 1. "T2,T2 Threshold in U16 format." newline hexmask.long.word 0x8 0.--15. 1. "T1,T1 Threshold in U16 format. Recommandated T1 < T2 < T3" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__MMR__MMRCFG__PCID_REGS_RBIrIntPCFG2,Threshold Configuration for R/B/Ir interpoaltion processing" hexmask.long.word 0xC 0.--15. 1. "T3,T3 Threshold in U16 format." line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__MMR__MMRCFG__PCID_REGS_RBIrColorDiffCFG,Portion of green high frequency component mixed with interpolated R/B/Ir" hexmask.long.word 0x10 16.--24. 1. "GHFXFERFACTORIR,Portion of green high frequency component mixed with interpolated Ir values in color difference IR interpolation method in U9Q8 format. Max value supported is 256" newline hexmask.long.word 0x10 0.--8. 1. "GHFXFERFACTOR,Portion of green high frequency component mixed with interpolated R/B values in color difference R/B interpolation Method in U9Q8 format. Max value supported is 256" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__MMR__MMRCFG__PCID_REGS_IRSubCFG1,IR Subtraction Configuration1 Register" hexmask.long.word 0x14 0.--15. 1. "CUTOFFTH,Threshold for Ir subtraction in U16 format. When R/G/B pixel values at a locations in the input are above this threshold no IR subtraction is performed (i.e. Ir subtraction factor == 0)" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__MMR__MMRCFG__PCID_REGS_IRSubCFG2,IR Subtraction Configuration1 Register" hexmask.long.word 0x18 16.--24. 1. "TRANSITIONRANGEINV,Reciprocal of TransitionRange in U9Q8 format (i.e. 8-bit of decimal with 1-bit of integer). SW driver needs to generate this from TransitionRange to avoid HW divider" newline hexmask.long.byte 0x18 0.--7. 1. "TRANSITIONRANGE,Range of gray levels just below IRSubCFG1.Thrshld where Ir subtraction factor linearly changes from 1 at IRSubCFG1.Thrshld - IRSubCFG2.TransitionRange and 0 above IRSubCFG1.Thrshld. Is in U8 format" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__MMR__MMRCFG__PCID_REGS_IRSubDistScaleLUT0,City Block Distance based IR Subtraction Scale factor LUT. Scales are used in Pre smoothing filter factor calculation" hexmask.long.word 0x1C 16.--24. 1. "D1SCALE,L1 norm of City Block Distance 1 Scale Filter. Max value supported is 256" newline hexmask.long.word 0x1C 0.--8. 1. "D0SCALE,L1 norm of City Block Distance 0 Scale Filter. Max value supported is 256" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__MMR__MMRCFG__PCID_REGS_IRSubDistScaleLUT1,Distance based IR Subtraction Scale factor LUT. Scales are used in Pre smoothing filter factor calculation" hexmask.long.word 0x20 16.--24. 1. "D3SCALE,L1 norm of City Block Distance 3 Scale Filter. Max value supported is 256" newline hexmask.long.word 0x20 0.--8. 1. "D2SCALE,L1 norm of City Block Distance 2 Scale Filter. Max value supported is 256" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__MMR__MMRCFG__PCID_REGS_IRSubDistScaleLUT2,Distance based IR Subtraction Scale factor LUT. Scales are used in Pre smoothing filter factor calculation" hexmask.long.word 0x24 0.--8. 1. "D4SCALE,L1 norm of City Block Distance 4 Scale Filter. Max value supported is 256" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__MMR__MMRCFG__PCID_REGS_IRSubScale0,IR Subtraction Factor after smoothening Factor Filter" hexmask.long.word 0x28 16.--24. 1. "SUBFACTSCALE01,Ir Subtraction factor scale for [0][1] co-ordinates in Bayer 2x2 pattern. Represented in U9Q8 format and Max value supported is 511" newline hexmask.long.word 0x28 0.--8. 1. "SUBFACTSCALE00,Ir Subtraction factor scale for [0][0] co-ordinates in Bayer 2x2 pattern. Represented in U9Q8 format and Max value supported is 511" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__MMR__MMRCFG__PCID_REGS_IRSubScale1,IR Subtraction Factor after smoothening Factor Filter" hexmask.long.word 0x2C 16.--24. 1. "SUBFACTSCALE11,Ir Subtraction factor scale for [1][1] co-ordinates in Bayer 2x2 pattern. Represented in U9Q8 format and Max value supported is 511" newline hexmask.long.word 0x2C 0.--8. 1. "SUBFACTSCALE10,Ir Subtraction factor scale for [1][0] co-ordinates in Bayer 2x2 pattern. Represented in U9Q8 format and Max value supported is 511" group.long 0x80++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__MMR__MMRCFG__PCID_REGS_INT_STAT,Set on internal interupt event and clr by SW" bitfld.long 0x0 0. "LUT_CFG_ERR,status/clear for mmr configuration error. Set when Config access happen to LUT memory in the middle of processing" "0,1" group.long 0x100++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__MMR__MMRCFG__PCID_REGS_DBG_CTL,Control the memory access selection" hexmask.long.byte 0x0 8.--12. 1. "LINEMEM_SEL,Select Line memory to do MMR access. 0 - 7 : Input Line buffer (32-bit max_line_width/2 entries) 8 - 12 : Up-Sampled new green pixel Line memory (32-bit max_line_width/4 entries) 13 - 17 : IR Subtraction Factor Line memory (18-bit.." newline bitfld.long 0x0 6. "IR_EOF_EN,Enable for EOF at PCID IR output channel" "0,1" newline bitfld.long 0x0 5. "IR_EOL_EN,Enable for EOL at PCID IR output channel" "0,1" newline bitfld.long 0x0 4. "BAYER_EOF_EN,Enable for EOF at PCID Bayer output channel" "0,1" newline bitfld.long 0x0 3. "BAYER_EOL_EN,Enable for EOL at PCID Bayer output channel" "0,1" newline bitfld.long 0x0 2. "SOF_EN,Enable for SOF at PCID input" "0,1" newline bitfld.long 0x0 1. "SOL_EN,Enable for SOL at PCID input" "0,1" newline bitfld.long 0x0 0. "DBG_EN,Enable debug features set to '0' to disable all debug events" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_PCID__S_VBUSP__MMR__MMRCFG__PCID_REGS_DBG_STAT,Set/Clear for PCID debug events and corresponding event capture is enabled in DBG_CTL register" bitfld.long 0x4 6. "IR_EOF,Status/Clear for EOF at PCID IR output channel. Set on EOF at PCID IR output channel" "0,1" newline bitfld.long 0x4 5. "IR_EOL,Status/Clear for EOL at PCID IR output channel. Set on EOL at PCID IR output channel" "0,1" newline bitfld.long 0x4 4. "BAYER_EOF,Status/Clear for EOF at PCID Bayer output channel. Set on EOF at PCID Bayer output channel" "0,1" newline bitfld.long 0x4 3. "BAYER_EOL,Status/Clear for EOL at PCID Bayer output channel. Set on EOL at PCID Bayer output channel" "0,1" newline bitfld.long 0x4 2. "SOF,Status/Clear for SOF at PCID input. Set on SOF at PCID input" "0,1" newline bitfld.long 0x4 1. "SOL,Status/Clear for SOL at PCID input. Set on SOL at PCID input" "0,1" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_DPC_LRAM_RAWFE_DPC_LRAM" base ad:0x2C124000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__DPC__LRAM__RAWFE_DPC_LRAM_ram1,Input image line storage." hexmask.long 0x0 0.--31. 1. "DATA,pixel storage" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_DPC_RAM_RAWFE_DPC_LUT_RAM" base ad:0x2C123000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__DPC__RAM__RAWFE_DPC_LUT_RAM_ram1,Input image width and height." tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_DPC_STATRAM_RAWFE_DPC_STATRAM" base ad:0x2C136000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__DPC__STATRAM__RAWFE_DPC_STATRAM_ram1,DPC stats RAM." hexmask.long 0x0 0.--31. 1. "DATA,dpc stats (6'd0 y-cordination x-cordination)" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_LUT_RAM_RAWFE_H3A_LUT_RAM" base ad:0x2C122800 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_LUT__RAM__RAWFE_H3A_LUT_RAM_ram1,Input image width and height." tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_ARAM_RAWFE_H3A_ARAM" base ad:0x2C130000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__ARAM__RAWFE_H3A_ARAM_ram1,Input image width and height." tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_CFG_RAWFE_H3A_CFG" base ad:0x2C120400 rgroup.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_PID,Peripheral Revision and Class Information" bitfld.long 0x0 30.--31. "SCHEME,PID scheme type" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,PID func revision" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,PID rtl revision" newline bitfld.long 0x0 8.--10. "MAJOR,PID major revision" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,PID minor revision" group.long 0x4++0x7B line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_PCR,Peripheral Control Register" hexmask.long.word 0x0 22.--31. 1. "AVE2LMT,AE/AWB Saturation Limit This is the value that all sub sampled pixels in the AE/AWB engine are compared to If the data is greater or equal to this data then the block is considered saturated" newline bitfld.long 0x0 21. "OVF,H3A module overflow status bit If the H3A module overflows it will keep sending data The software can read this status bit during vertical blanking period to ensure that no overflow happened while writing out the data to SDRAM There is also an.." "0,1" newline bitfld.long 0x0 20. "AF_VF_EN,AF Vertical Focus Enable" "0,1" newline bitfld.long 0x0 19. "AEW_MED_EN,AE/AWB Median filter Enable If the median filter is enabled then the 1st 2 and last 2 pixels in the frame are not filtered" "0,1" newline rbitfld.long 0x0 18. "BUSYAEAWB,Busy bit for AE/AWB" "0,1" newline bitfld.long 0x0 17. "AEW_ALAW_EN,AE/AWB A-law Enable" "0,1" newline bitfld.long 0x0 16. "AEW_EN,AE/AWB enable" "0,1" newline rbitfld.long 0x0 15. "BUSYAF,Busy bit for AF" "0,1" newline bitfld.long 0x0 14. "FVMODE,Focus Value Accumulation Mode" "0,1" newline bitfld.long 0x0 11.--13. "RGBPOS,Red Green and blue pixel location in the AF windows RGBPOS[0]: GR and GB as Bayer pattern RGBPOS[1]: RG and GB as Bayer pattern RGBPOS[2]: GR and BG as Bayer pattern RGBPOS[3]: RG and BG as Bayer pattern RGBPOS[4]: GG and RB as custom pattern.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--10. 1. "MED_TH,Median filter threshold" newline bitfld.long 0x0 2. "AF_MED_EN,Auto Focus Median filter Enable If the median filter is enabled then the 1st 2 and last 2 pixels in the frame are not in the valid region Therefore the paxel start/end and IIR filter start positions should not be set within the 1st and last 2.." "0,1" newline bitfld.long 0x0 1. "AF_ALAW_EN,AF A-law table enable" "0,1" newline bitfld.long 0x0 0. "AF_EN,AF enable" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFPAX1,Setup for the AF Engine Paxel Configuration" hexmask.long.byte 0x4 16.--23. 1. "PAXW,AF Engine Paxel Width The width of the paxel is the value of this register plus 1 multiplied by 2 The minimum width is 16 pixels if pixel clock is or less of the vpss clock If pixel clock is equal to vpss clock the minimum width is 32 pixels * This.." newline hexmask.long.byte 0x4 0.--7. 1. "PAXH,AF Engine Paxel Height The height of the paxel is the value of this register plus 1 multiplied by 2 with a final value of 2-256 [even] * This value is shadowed and latched on the rising edge of VSYNC" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFPAX2,Setup for the AF Engine Paxel Configuration" hexmask.long.byte 0x8 17.--20. 1. "AFINCH,AF Engine Column Increments Number of columns to increment in a paxel plus 1 multiplied by 2 Thus the number of columns that can be skipped between two processed line pairs is 2-32 [even] The starting two columns in a paxel are first processed.." newline hexmask.long.byte 0x8 13.--16. 1. "AFINCV,AF Engine Line Increments Number of lines to increment in a Paxel plus 1 multiplied by 2 Incrementing the line in a paxel is always done on a line pair due to the fact that the RGB pattern falls in two lines If all the lines are to be processed .." newline hexmask.long.byte 0x8 6.--12. 1. "PAXVC,AF Engine Vertical Paxel Count The number of paxels in the vertical direction plus 1 The maximum number of vertical paxels in a frame should not exceed 128 The value should be set to ensure that the bandwidth requirements and buffer size are not.." newline hexmask.long.byte 0x8 0.--5. 1. "PAXHC,AF Engine Horizontal Paxel Count The number of paxels in the horizontal direction plus 1 It is illegal to set a number that is greater than 35 [total of 36 paxels in the horizontal direction] The minimum number of paxels should be 2 [valid range.." line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFPAXSTART,Start Position for AF Engine Paxels" hexmask.long.word 0xC 16.--27. 1. "PAXSH,AF Engine Paxel Horizontal start position Range: 2-4094 PAXSH must be equal to or greater than [IIRSH + 2] This value must be even if Vertical mode is not enabled If Vertical mode is enabled then the lower bit of PAXSH and IIRSH must be equal *.." newline hexmask.long.word 0xC 0.--11. 1. "PAXSV,AF Engine Paxel Vertical start position Range: 0-4095 Sets the vertical line for the first paxel This value must be greater then or equal to 8 if the vertical mode is enabled * This value is shadowed and latched on the rising edge of VSYNC" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFIIRSH,Start Position for IIRSH" hexmask.long.word 0x10 0.--11. 1. "IIRSH,AF Engine IIR Horizontal Start Position Range from 0-4094 When the horizontal position of a line equals this value the shift registers are cleared on the next pixel This value must be even if Vertical mode is not enabled If vertical mode is enabled.." line.long 0x14 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFBUFST,SDRAM destination address for AF engine statistics" hexmask.long 0x14 5.--31. 1. "AFBUFST,SDRAM destination address for AF engine statistics The SDRAM destination address for the AF statistics The 6 LSBs are ignored address shall be on a 64-byte boundary This field can be altered even when the AF is busy Change will take place only.." line.long 0x18 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF010,IIR filter coefficient data for SET 0." hexmask.long.word 0x18 16.--27. 1. "COEFF1,AF Engine IIR filter Coefficient #1 [Set 0] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x18 0.--11. 1. "COEFF0,AF Engine IIR filter Coefficient #0 [Set 0] The range is signed -32 <= value <= 31 +63/64" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF032,IIR filter coefficient data for SET 0." hexmask.long.word 0x1C 16.--27. 1. "COEFF3,AF Engine IIR filter Coefficient #3 [Set 0] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x1C 0.--11. 1. "COEFF2,AF Engine IIR filter Coefficient #2 [Set 0] The range is signed -32 <= value <= 31 +63/64" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF054,IIR filter coefficient data for SET 0." hexmask.long.word 0x20 16.--27. 1. "COEFF5,AF Engine IIR filter Coefficient #5 [Set 0] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x20 0.--11. 1. "COEFF4,AF Engine IIR filter Coefficient #4 [Set 0] The range is signed -32 <= value <= 31 +63/64" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF076,IIR filter coefficient data for SET 0." hexmask.long.word 0x24 16.--27. 1. "COEFF7,AF Engine IIR filter Coefficient #7 [Set 0] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x24 0.--11. 1. "COEFF6,AF Engine IIR filter Coefficient #6 [Set 0] The range is signed -32 <= value <= 31 +63/64" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF098,IIR filter coefficient data for SET 0." hexmask.long.word 0x28 16.--27. 1. "COEFF9,AF Engine IIR filter Coefficient #9 [Set 0] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x28 0.--11. 1. "COEFF8,AF Engine IIR filter Coefficient #8 [Set 0] The range is signed -32 <= value <= 31 +63/64" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF0010,IIR filter coefficient data for SET 0." hexmask.long.word 0x2C 0.--11. 1. "COEFF10,AF Engine IIR filter Coefficient #10 [Set 0] The range is signed -32 <= value <= 31 +63/64" line.long 0x30 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF110,IIR filter coefficient data for SET 1." hexmask.long.word 0x30 16.--27. 1. "COEFF1,AF Engine IIR filter Coefficient #1 [Set 1] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x30 0.--11. 1. "COEFF0,AF Engine IIR filter Coefficient #0 [Set 1] The range is signed -32 <= value <= 31 +63/64" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF132,IIR filter coefficient data for SET 1." hexmask.long.word 0x34 16.--27. 1. "COEFF3,AF Engine IIR filter Coefficient #3 [Set 1] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x34 0.--11. 1. "COEFF2,AF Engine IIR filter Coefficient #2 [Set 1] The range is signed -32 <= value <= 31 +63/64" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF154,IIR filter coefficient data for SET 1." hexmask.long.word 0x38 16.--27. 1. "COEFF5,AF Engine IIR filter Coefficient #5 [Set 1] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x38 0.--11. 1. "COEFF4,AF Engine IIR filter Coefficient #4 [Set 1] The range is signed -32 <= value <= 31 +63/64" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF176,IIR filter coefficient data for SET 1." hexmask.long.word 0x3C 16.--27. 1. "COEFF7,AF Engine IIR filter Coefficient #7 [Set 1] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x3C 0.--11. 1. "COEFF6,AF Engine IIR filter Coefficient #6 [Set 1] The range is signed -32 <= value <= 31 +63/64" line.long 0x40 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF198,IIR filter coefficient data for SET 1." hexmask.long.word 0x40 16.--27. 1. "COEFF9,AF Engine IIR filter Coefficient #9 [Set 1] The range is signed -32 <= value <= 31 +63/64" newline hexmask.long.word 0x40 0.--11. 1. "COEFF8,AF Engine IIR filter Coefficient #8 [Set 1] The range is signed -32 <= value <= 31 +63/64" line.long 0x44 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AFCOEF1010,IIR filter coefficient data for SET 1." hexmask.long.word 0x44 0.--11. 1. "COEFF10,AF Engine IIR filter Coefficient #10 [Set 1] The range is signed -32 <= value <= 31 +63/64" line.long 0x48 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AEWWIN1,Configuration for AE/AWB Windows." hexmask.long.byte 0x48 24.--31. 1. "WINH,AE/AWB Engine Window Height This specifies the window height in an even number of pixels the window height is the value plus 1 multiplied by 2 The final value can be from 2-512 [even] * This value is shadowed and latched on the rising edge of VSYNC" newline hexmask.long.byte 0x48 13.--20. 1. "WINW,AE/AWB Engine Window Width This specifies the window width in an even number of pixels the window width is the value plus 1 multiplied by 2 The minimum width is expected to be 8 pixels * This value is shadowed and latched on the rising edge of VSYNC" newline hexmask.long.byte 0x48 6.--12. 1. "WINVC,AE/AWB Engine Vertical Window Count The number of windows in the vertical direction plus 1 The maximum number of vertical windows in a frame should not exceed 128 The value should be set to ensure that the bandwidth requirements and buffer size are.." newline hexmask.long.byte 0x48 0.--5. 1. "WINHC,AE/AWB Engine Horizontal Window Count The number of horizontal windows plus 1 The maximum number of horizontal windows is 35 plus 1 [36] The minimum number of windows should be 2 [valid range for the field is 1-35] * This value is shadowed and.." line.long 0x4C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AEWINSTART,Start position for AE/AWB Windows." hexmask.long.word 0x4C 16.--27. 1. "WINSV,AE/AWB Engine Vertical Window Start Position Sets the first line for the first window Range 0-4095 * This value is shadowed and latched on the rising edge of VSYNC" newline hexmask.long.word 0x4C 0.--11. 1. "WINSH,AE/AWB Engine Horizontal Window Start Position Sets the horizontal position for the first window on each line Range 0-4095 * This value is shadowed and latched on the rising edge of VSYNC" line.long 0x50 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AEWINBLK,Start position and height for black line of AE/AWB Windows" hexmask.long.word 0x50 16.--27. 1. "WINSV,AE/AWB Engine Vertical Window Start Position for single black line of windows Sets the first line for the single black line of windows * This value is shadowed and latched on the rising edge of VSYNC Range 0-4095 Note that the horizontal start and.." newline hexmask.long.byte 0x50 0.--6. 1. "WINH,AE/AWB Engine Window Height for the single black line of windows This specifies the window height in an even number of pixels the window height is the value plus 1 multiplied by 2 The final value can be from 2-256 [even] * This value is shadowed.." line.long 0x54 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AEWSUBWIN,Configuration for subsample data in AE/AWB window." hexmask.long.byte 0x54 8.--11. 1. "AEWINCV,AE/AWB Engine Vertical Sampling Point Increment Sets vertical distance between sub-samples within a window plus 1 multiplied by 2 The final range is 2-32 * This value is shadowed and latched on the rising edge of VSYNC" newline hexmask.long.byte 0x54 0.--3. 1. "AEWINCH,AE/AWB Engine Horizontal Sampling Point Increment Sets horizontal distance between sub-samples within a window plus 1 multiplied by 2 The final range is 2-32 * This value is shadowed and latched on the rising edge of VSYNC" line.long 0x58 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AEWBUFST,SDRAM destination address for AE/AWB engine statistics" hexmask.long 0x58 5.--31. 1. "AEWBUFST,SDRAM destination address for AE/AWB engine statistics The start location in SDRAM for the AE/AWB statistics The 6 LSB are ignored address should be on a 64-byte boundary This field can be altered even when the AE/AWB is busy Change will take.." line.long 0x5C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_AEWCFG,Configuration for AE/AWB" bitfld.long 0x5C 8.--9. "AEFMT,AE/AWB output format 0 = sum of squares 1 = min/max 2 = sum only; no sum of squares or min/max * This value is shadowed and latched on the rising edge of VSYNC" "0: sum of squares,1: min/max,2: sum only,?" newline hexmask.long.byte 0x5C 0.--3. 1. "SUMSHFT,AE/AWB engine shift value for the accumulation of pixel values This bitfield sets the right shift value which is applied on the result of the pixel accumulation before it is stored in the packet The accumulation takes place on 26 bits which is.." line.long 0x60 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_LINE_START,Line Framing Logic Register" hexmask.long.word 0x60 16.--31. 1. "SLV,Start Line Vertical Specifies how many lines after the VD rising edge the real frame starts" newline hexmask.long.word 0x60 0.--15. 1. "LINE_START,Line Start The framing module uses the LINE_START bitfield to find the position of the first pixel to place into the line buffer Range: 0-65535" line.long 0x64 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_VFV_CFG1,Vertical focus value configuration 1." hexmask.long.byte 0x64 24.--31. 1. "VCOEF1_3,Vertical FV FIR 1 coefficient 3" newline hexmask.long.byte 0x64 16.--23. 1. "VCOEF1_2,Vertical FV FIR 1 coefficient 2" newline hexmask.long.byte 0x64 8.--15. 1. "VCOEF1_1,Vertical FV FIR 1 coefficient 1" newline hexmask.long.byte 0x64 0.--7. 1. "VCOEF1_0,Vertical FV FIR 1 coefficient 0" line.long 0x68 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_VFV_CFG2,Vertical focus value configuration 2." hexmask.long.word 0x68 16.--31. 1. "VTHR1,Threshold for vertical FV FIR 1" newline hexmask.long.byte 0x68 0.--7. 1. "VCOEF1_4,Vertical FV FIR 1 coefficient 4" line.long 0x6C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_VFV_CFG3,Vertical focus value configuration 4." hexmask.long.byte 0x6C 24.--31. 1. "VCOEF2_3,Vertical FV FIR 2 coefficient 3" newline hexmask.long.byte 0x6C 16.--23. 1. "VCOEF2_2,Vertical FV FIR 2 coefficient 2" newline hexmask.long.byte 0x6C 8.--15. 1. "VCOEF2_1,Vertical FV FIR 2 coefficient 1" newline hexmask.long.byte 0x6C 0.--7. 1. "VCOEF2_0,Vertical FV FIR 2 coefficient 0" line.long 0x70 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_VFV_CFG4,Vertical focus value configuration 4." hexmask.long.word 0x70 16.--31. 1. "VTHR2,Threshold for vertical FV FIR 2" newline hexmask.long.byte 0x70 0.--7. 1. "VCOEF2_4,Vertical FV FIR 2 coefficient 4" line.long 0x74 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_HVF_THR,Horizontal Focus Value Threshold" hexmask.long.word 0x74 16.--31. 1. "HTHR2,Threshold for horizontal FV IIR 2" newline hexmask.long.word 0x74 0.--15. 1. "HTHR1,Threshold for horizontal FV IIR 1" line.long 0x78 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__CFG__RAWFE_H3A_CFG_H3A_ADVANCED,advanced setting register. NOT FOR TRM" hexmask.long.word 0x78 16.--31. 1. "ID,Below information should not be in TRM To access the other bitfields [AF_MODE/AEW_MODE] certain value should be written to this ID field first First the ID is written to this field Second the AF_MODE or/and AEW_MODE is written" newline bitfld.long 0x78 4. "AEW_MODE,This bit should not be included in TRM This bit is accesible only if ID is set to 0xDC00 AE/AWB engine custom mode [AVE2 mode] select" "0,1" newline bitfld.long 0x78 0. "AF_MODE,AF engine mode Below information should not be included in TRM The effect of this bit changes based on the ID value If other value than 0xCA00 or 0xDC00 is set to ID this field has no effect" "0,1" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_LRAM_RAWFE_H3A_LRAM" base ad:0x2C132000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__H3A_WRAP__LRAM__RAWFE_H3A_LRAM_ram1,Input image width and height." tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LSC_RAM_RAWFE_LSC_LUT_RAM" base ad:0x2C128000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__LSC__RAM__RAWFE_LSC_LUT_RAM_ram1,Input image width and height." tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT1_RAM_RAWFE_PWL_LUT1_RAM" base ad:0x2C121800 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__LUT1__RAM__RAWFE_PWL_LUT1_RAM_ram1,Input image width and height." tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT2_RAM_RAWFE_PWL_LUT2_RAM" base ad:0x2C121000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__LUT2__RAM__RAWFE_PWL_LUT2_RAM_ram1,Input image width and height." tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT3_RAM_RAWFE_PWL_LUT3_RAM" base ad:0x2C120800 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__LUT3__RAM__RAWFE_PWL_LUT3_RAM_ram1,Input image width and height." tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_MMR_S_VBUSP_RAWFE_CFG" base ad:0x2C120000 group.long 0x0++0x19B line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_IMAGE_CFG,Input image width and height." hexmask.long.word 0x0 16.--28. 1. "HEIGHT,image height" newline hexmask.long.word 0x0 0.--12. 1. "WIDTH,image width" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_SHADOW_CFG,shadow configuration" bitfld.long 0x4 0. "LUT3_SHDW_EN,use LUT2 ram as LUT table for LUT3 processing" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_MASK_SH,Long frame PWL mask and shift values" hexmask.long.byte 0x8 16.--19. 1. "SHIFT,number of right shift" newline hexmask.long.word 0x8 0.--15. 1. "MASK,mask bit pattern" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_EN,Long frame PWL enable" bitfld.long 0xC 0. "ENABLE,enable" "0,1" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_THRX12,Long frame PWL threshold X1 and X2 - Unsigned" hexmask.long.word 0x10 16.--31. 1. "THR_X2,threshold X2" newline hexmask.long.word 0x10 0.--15. 1. "THR_X1,threshold X1" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_THRX3,Long frame PWL threshold X3 - Unsigned" hexmask.long.word 0x14 0.--15. 1. "THR_X3,threshold X3" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_THRY1,Long frame PWL threshold Y1 - Unsigned" hexmask.long.tbyte 0x18 0.--23. 1. "THR_Y1,threshold Y1" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_THRY2,Long frame PWL threshold Y2 - Unsigned" hexmask.long.tbyte 0x1C 0.--23. 1. "THR_Y2,threshold Y2" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_THRY3,Long frame PWL threshold Y3 - Unsigned" hexmask.long.tbyte 0x20 0.--23. 1. "THR_Y3,threshold Y3" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_SLP12,Long frame PWL slope 1 and 2 - Unsigned" hexmask.long.word 0x24 16.--31. 1. "SLOPE_2,slope 2" newline hexmask.long.word 0x24 0.--15. 1. "SLOPE_1,slope 1" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_SLP34,Long frame PWL slope 3 and 4 - Unsigned" hexmask.long.word 0x28 16.--31. 1. "SLOPE_4,slope 4" newline hexmask.long.word 0x28 0.--15. 1. "SLOPE_3,slope 3" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_SLPSH_CLIP,Long frame PWL slope shift and clip" hexmask.long.tbyte 0x2C 8.--31. 1. "CLIP,clip value" newline hexmask.long.byte 0x2C 0.--7. 1. "SLOPE_SHIFT,shift value for slope must not exceed decimal 31." line.long 0x30 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_OFF1,Long frame Offset 1" hexmask.long.byte 0x30 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x30 0.--23. 1. "OFST00,S24 Offset at pixel 00" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_OFF2,Long frame Offset 2" hexmask.long.byte 0x34 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x34 0.--23. 1. "OFST01,S24 Offset at pixel 01" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_OFF3,Long frame Offset 3" hexmask.long.byte 0x38 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x38 0.--23. 1. "OFST10,S24 Offset at pixel 10" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_OFF4,Long frame Offset 4" hexmask.long.byte 0x3C 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x3C 0.--23. 1. "OFST11,S24 Offset at pixel 11" line.long 0x40 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_WB_gain12,Long Frame white balance gain 1 and 2" hexmask.long.word 0x40 16.--28. 1. "WB_GAIN01,U13Q9 WB gain at pixel 01" newline hexmask.long.word 0x40 0.--12. 1. "WB_GAIN00,U13Q9 WB gain at pixel 00" line.long 0x44 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_WB_gain34,Long Frame white balance gain 3 and 4" hexmask.long.word 0x44 16.--28. 1. "WB_GAIN11,U13Q9 WB gain at pixel 11" newline hexmask.long.word 0x44 0.--12. 1. "WB_GAIN10,U13Q9 WB gain at pixel 10" line.long 0x48 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_LUT,Long frame PWL LUT configuration" hexmask.long.byte 0x48 1.--5. 1. "LUT_BITS,LUT input bit depth up to 24" newline bitfld.long 0x48 0. "LUT_EN,enable LUT based compression" "0,1" line.long 0x4C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL1_LUTCLIP,Long frame PWL LUT output clip value" hexmask.long.word 0x4C 0.--15. 1. "LUTCLIP,LUT clip value" line.long 0x50 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_MASK_SH,Short frame PWL mask and shift values" hexmask.long.byte 0x50 16.--19. 1. "SHIFT,number of right shift" newline hexmask.long.word 0x50 0.--15. 1. "MASK,mask bit pattern" line.long 0x54 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_EN,Short frame PWL enable" bitfld.long 0x54 0. "ENABLE,enable" "0,1" line.long 0x58 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_THRX12,Short frame PWL threshold X1 and X2 - Unsigned" hexmask.long.word 0x58 16.--31. 1. "THR_X2,threshold X2" newline hexmask.long.word 0x58 0.--15. 1. "THR_X1,threshold X1" line.long 0x5C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_THRX3,Short frame PWL threshold X3 - Unsigned" hexmask.long.word 0x5C 0.--15. 1. "THR_X3,threshold X3" line.long 0x60 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_THRY1,Short frame PWL threshold Y1 - Unsigned" hexmask.long.tbyte 0x60 0.--23. 1. "THR_Y1,threshold Y1" line.long 0x64 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_THRY2,Short frame PWL threshold Y2 - Unsigned" hexmask.long.tbyte 0x64 0.--23. 1. "THR_Y2,threshold Y2" line.long 0x68 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_THRY3,Short frame PWL threshold Y3 - Unsigned" hexmask.long.tbyte 0x68 0.--23. 1. "THR_Y3,threshold Y3" line.long 0x6C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_SLP12,Short frame PWL slope 1 and 2 - Unsigned" hexmask.long.word 0x6C 16.--31. 1. "SLOPE_2,slope 2" newline hexmask.long.word 0x6C 0.--15. 1. "SLOPE_1,slope 1" line.long 0x70 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_SLP34,Short frame PWL slope 3 and 4 - Unsigned" hexmask.long.word 0x70 16.--31. 1. "SLOPE_4,slope 4" newline hexmask.long.word 0x70 0.--15. 1. "SLOPE_3,slope 3" line.long 0x74 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_SLPSH_CLIP,Short frame PWL slope shift and clip" hexmask.long.tbyte 0x74 8.--31. 1. "CLIP,clip value" newline hexmask.long.byte 0x74 0.--7. 1. "SLOPE_SHIFT,shift value for slope must not exceed decimal 31" line.long 0x78 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_LUT,Short frame PWL LUT configuration" hexmask.long.byte 0x78 1.--5. 1. "LUT_BITS,LUT input bit depth up to 24" newline bitfld.long 0x78 0. "LUT_EN,enable LUT based compression" "0,1" line.long 0x7C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_LUTCLIP,Short frame PWL LUT output clip value" hexmask.long.word 0x7C 0.--15. 1. "LUTCLIP,LUT clip value" line.long 0x80 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_OFF1,Short frame WB Offset 1" hexmask.long.byte 0x80 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x80 0.--23. 1. "OFST00,S24 WB Offset at pixel 00" line.long 0x84 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_OFF2,Short frame Offset 2" hexmask.long.byte 0x84 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x84 0.--23. 1. "OFST01,S24 Offset at pixel 01" line.long 0x88 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_OFF3,Short frame Offset 3" hexmask.long.byte 0x88 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x88 0.--23. 1. "OFST10,S24 Offset at pixel 10" line.long 0x8C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_OFF4,Short frame Offset 4" hexmask.long.byte 0x8C 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0x8C 0.--23. 1. "OFST11,S24 Offset at pixel 11" line.long 0x90 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_WB_gain12,Short Frame white balance gain 1 and 2" hexmask.long.word 0x90 16.--28. 1. "WB_GAIN01,U13Q9 WB gain at pixel 01" newline hexmask.long.word 0x90 0.--12. 1. "WB_GAIN00,U13Q9 WB gain at pixel 00" line.long 0x94 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL2_WB_gain34,Short Frame white balance gain 3 and 4" hexmask.long.word 0x94 16.--28. 1. "WB_GAIN11,U13Q9 WB gain at pixel 11" newline hexmask.long.word 0x94 0.--12. 1. "WB_GAIN10,U13Q9 WB gain at pixel 10" line.long 0x98 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_MASK_SH,Very short frame PWL mask and shift values" hexmask.long.byte 0x98 16.--19. 1. "SHIFT,number of right shift" newline hexmask.long.word 0x98 0.--15. 1. "MASK,mask bit pattern" line.long 0x9C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_EN,Very short frame PWL enable" bitfld.long 0x9C 0. "ENABLE,enable" "0,1" line.long 0xA0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_THRX12,Very short frame PWL threshold X1 and X2 - Unsigned" hexmask.long.word 0xA0 16.--31. 1. "THR_X2,threshold X2" newline hexmask.long.word 0xA0 0.--15. 1. "THR_X1,threshold X1" line.long 0xA4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_THRX3,Very short frame PWL threshold X3 - Unsigned" hexmask.long.word 0xA4 0.--15. 1. "THR_X3,threshold X3" line.long 0xA8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_THRY1,Very short frame PWL threshold Y1 - Unsigned" hexmask.long.tbyte 0xA8 0.--23. 1. "THR_Y1,threshold Y1" line.long 0xAC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_THRY2,Very short frame PWL threshold Y2 - Unsigned" hexmask.long.tbyte 0xAC 0.--23. 1. "THR_Y2,threshold Y2" line.long 0xB0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_THRY3,Very short frame PWL threshold Y3 - Unsigned" hexmask.long.tbyte 0xB0 0.--23. 1. "THR_Y3,threshold Y3" line.long 0xB4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_SLP12,Very short frame PWL slope 1 and 2 - Unsigned" hexmask.long.word 0xB4 16.--31. 1. "SLOPE_2,slope 2" newline hexmask.long.word 0xB4 0.--15. 1. "SLOPE_1,slope 1" line.long 0xB8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_SLP34,Very short frame PWL slope 3 and 4 - Unsigned" hexmask.long.word 0xB8 16.--31. 1. "SLOPE_4,slope 4" newline hexmask.long.word 0xB8 0.--15. 1. "SLOPE_3,slope 3" line.long 0xBC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_SLPSH_CLIP,Very short frame PWL slope shift and clip" hexmask.long.tbyte 0xBC 8.--31. 1. "CLIP,clip value" newline hexmask.long.byte 0xBC 0.--7. 1. "SLOPE_SHIFT,shift value for slope must not exceed decimal 31" line.long 0xC0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_LUT,Very short frame PWL LUT configuration" hexmask.long.byte 0xC0 1.--5. 1. "LUT_BITS,LUT input bit depth up to 24" newline bitfld.long 0xC0 0. "LUT_EN,enable LUT based compression" "0,1" line.long 0xC4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_LUTCLIP,Very short frame PWL LUT output clip value" hexmask.long.word 0xC4 0.--15. 1. "LUTCLIP,LUT clip value" line.long 0xC8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_OFF1,Very Short frame Offset 1" hexmask.long.byte 0xC8 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0xC8 0.--23. 1. "OFST00,S24 Offset at pixel 00" line.long 0xCC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_OFF2,Very Short frame Offset 2" hexmask.long.byte 0xCC 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0xCC 0.--23. 1. "OFST01,S24 Offset at pixel 01" line.long 0xD0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_OFF3,Very Short frame Offset 3" hexmask.long.byte 0xD0 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0xD0 0.--23. 1. "OFST10,S24 Offset at pixel 10" line.long 0xD4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_OFF4,Very Short frame Offset 4" hexmask.long.byte 0xD4 24.--31. 1. "RSVD,reserved" newline hexmask.long.tbyte 0xD4 0.--23. 1. "OFST11,S24 Offset at pixel 11" line.long 0xD8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_WB_gain12,Very Short Frame white balance gain 1 and 2" hexmask.long.word 0xD8 16.--28. 1. "WB_GAIN01,U13Q9 WB gain at pixel 01" newline hexmask.long.word 0xD8 0.--12. 1. "WB_GAIN00,U13Q9 WB gain at pixel 00" line.long 0xDC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_PWL3_WB_gain34,Very Short Frame white balance gain 3 and 4" hexmask.long.word 0xDC 16.--28. 1. "WB_GAIN11,U13Q9 WB gain at pixel 11" newline hexmask.long.word 0xDC 0.--12. 1. "WB_GAIN10,U13Q9 WB gain at pixel 10" line.long 0xE0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_CFG,First stage WDR merge configuration" bitfld.long 0xE0 14. "CFG_WGT_SEL,Select source for weight calculation (0:long 1: short)" "0: long,1: short" newline hexmask.long.byte 0xE0 10.--13. 1. "CFG_SBIT,U4 short exposure image bit shift" newline hexmask.long.byte 0xE0 6.--9. 1. "CFG_LBIT,U4 long exposure image bit shift" newline hexmask.long.byte 0xE0 1.--5. 1. "CFG_DST,U5 down shift value after WDR merge" newline bitfld.long 0xE0 0. "CFG_EN,enable" "0,1" line.long 0xE4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_GAIN,First stage WDR merge gain" hexmask.long.word 0xE4 16.--31. 1. "GSHORT,U16Q15 gain for long frame" newline hexmask.long.word 0xE4 0.--15. 1. "GLONG,U16Q15 gain for short frame" line.long 0xE8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_LBLK12,First stage WDR merge black level 1 and 2 for long frame" hexmask.long.word 0xE8 16.--27. 1. "LBK01,U12 black level for long frame at pixel 01" newline hexmask.long.word 0xE8 0.--11. 1. "LBK00,U12 black level for long frame at pixel 00" line.long 0xEC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_LBLK34,First stage WDR merge black level 3 and 4 for long frame" hexmask.long.word 0xEC 16.--27. 1. "LBK11,U12 black level for long frame at pixel 11" newline hexmask.long.word 0xEC 0.--11. 1. "LBK10,U12 black level for long frame at pixel 10" line.long 0xF0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_SBLK12,First stage WDR merge black level 1 and 2 for short frame" hexmask.long.word 0xF0 16.--27. 1. "SBK01,U12 black level for short frame at pixel 01" newline hexmask.long.word 0xF0 0.--11. 1. "SBK00,U12 black level for short frame at pixel 00" line.long 0xF4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_SBLK34,First stage WDR merge black level 3 and 4 for short frame" hexmask.long.word 0xF4 16.--27. 1. "SBK11,U12 black level for short frame at pixel 11" newline hexmask.long.word 0xF4 0.--11. 1. "SBK10,U12 black level for short frame at pixel 10" line.long 0xF8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_LWB12,First stage WDR merge WB gain 1 and 2 for long frame" hexmask.long.word 0xF8 16.--28. 1. "WB01,U13Q9 WB gain for long frame at pixel 01" newline hexmask.long.word 0xF8 0.--12. 1. "WB00,U13Q9 WB gain for long frame at pixel 00" line.long 0xFC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_LWB34,First stage WDR merge WB gain 3 and 4 for long frame" hexmask.long.word 0xFC 16.--28. 1. "WB11,U13Q9 WB gain for long frame at pixel 11" newline hexmask.long.word 0xFC 0.--12. 1. "WB10,U13Q9 WB gain for long frame at pixel 10" line.long 0x100 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_SWB12,First stage WDR merge WB gain 1 and 2 for short frame" hexmask.long.word 0x100 16.--28. 1. "WB01,U13Q9 WB gain for short frame at pixel 01" newline hexmask.long.word 0x100 0.--12. 1. "WB00,U13Q9 WB gain for short frame at pixel 00" line.long 0x104 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_SWB34,First stage WDR merge WB gain 3 and 4 for short frame" hexmask.long.word 0x104 16.--28. 1. "WB11,U13Q9 WB gain for short frame at pixel 11" newline hexmask.long.word 0x104 0.--12. 1. "WB10,U13Q9 WB gain for short frame at pixel 10" line.long 0x108 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_WDRTHR_BF,First stage WDR merge parameter WDRTHR and BF" hexmask.long.word 0x108 16.--31. 1. "BF,S16 bf parameter for merge" newline hexmask.long.word 0x108 0.--15. 1. "WDRTHR,U16 WDR threshold for merge" line.long 0x10C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_AF,First stage WDR merge parameter AF" hexmask.long.byte 0x10C 16.--21. 1. "AFE,U6 af_e parameter for merge" newline hexmask.long.word 0x10C 0.--15. 1. "AFM,S16 af_m parameter for merge" line.long 0x110 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_MA,First stage WDR merge parameter MA" hexmask.long.word 0x110 16.--31. 1. "MAS,U16 slope for merge MA filter" newline hexmask.long.word 0x110 0.--15. 1. "MAD,U16 lower threshold for merge MA filter" line.long 0x114 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG1_CLIP_SFT,First stage WDR merge clip value and shift before weight block" bitfld.long 0x114 20.--22. "WTSFT,U3 shift before weight block" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x114 0.--19. 1. "CLIP,U20 output clip value. It is a software restriction to always ensure that the clipped value is a 16-bit number for first wdr stage." line.long 0x118 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_CFG,Second stage WDR merge configuration" bitfld.long 0x118 14. "CFG_WGT_SEL,Select source for weight calculation (0:long 1: short)" "0: long,1: short" newline hexmask.long.byte 0x118 10.--13. 1. "CFG_SBIT,U4 short exposure image bit shift" newline hexmask.long.byte 0x118 6.--9. 1. "CFG_LBIT,U4 long exposure image bit shift" newline hexmask.long.byte 0x118 1.--5. 1. "CFG_DST,U5 down shift value after WDR merge" newline bitfld.long 0x118 0. "CFG_EN,enable" "0,1" line.long 0x11C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_GAIN,Second stage WDR merge gain" hexmask.long.word 0x11C 16.--31. 1. "GSHORT,U16Q15 gain for long frame" newline hexmask.long.word 0x11C 0.--15. 1. "GLONG,U16Q15 gain for short frame" line.long 0x120 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_LBLK12,Second stage WDR merge black level 1 and 2 for long frame" hexmask.long.word 0x120 16.--27. 1. "LBK01,U12 black level for long frame at pixel 01" newline hexmask.long.word 0x120 0.--11. 1. "LBK00,U12 black level for long frame at pixel 00" line.long 0x124 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_LBLK34,Second stage WDR merge black level 3 and 4 for long frame" hexmask.long.word 0x124 16.--27. 1. "LBK11,U12 black level for long frame at pixel 11" newline hexmask.long.word 0x124 0.--11. 1. "LBK10,U12 black level for long frame at pixel 10" line.long 0x128 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_SBLK12,Second stage WDR merge black level 1 and 2 for short frame" hexmask.long.word 0x128 16.--27. 1. "SBK01,U12 black level for short frame at pixel 01" newline hexmask.long.word 0x128 0.--11. 1. "SBK00,U12 black level for short frame at pixel 00" line.long 0x12C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_SBLK34,Second stage WDR merge black level 3 and 4 for short frame" hexmask.long.word 0x12C 16.--27. 1. "SBK11,U12 black level for short frame at pixel 11" newline hexmask.long.word 0x12C 0.--11. 1. "SBK10,U12 black level for short frame at pixel 10" line.long 0x130 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_LWB12,Second stage WDR merge WB gain 1 and 2 for long frame" hexmask.long.word 0x130 16.--28. 1. "WB01,U13Q9 WB gain for long frame at pixel 01" newline hexmask.long.word 0x130 0.--12. 1. "WB00,U13Q9 WB gain for long frame at pixel 00" line.long 0x134 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_LWB34,Second stage WDR merge WB gain 3 and 4 for long frame" hexmask.long.word 0x134 16.--28. 1. "WB11,U13Q9 WB gain for long frame at pixel 11" newline hexmask.long.word 0x134 0.--12. 1. "WB10,U13Q9 WB gain for long frame at pixel 10" line.long 0x138 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_SWB12,Second stage WDR merge WB gain 1 and 2 for short frame" hexmask.long.word 0x138 16.--28. 1. "WB01,U13Q9 WB gain for short frame at pixel 01" newline hexmask.long.word 0x138 0.--12. 1. "WB00,U13Q9 WB gain for short frame at pixel 00" line.long 0x13C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_SWB34,Second stage WDR merge WB gain 3 and 4 for short frame" hexmask.long.word 0x13C 16.--28. 1. "WB11,U13Q9 WB gain for short frame at pixel 11" newline hexmask.long.word 0x13C 0.--12. 1. "WB10,U13Q9 WB gain for short frame at pixel 10" line.long 0x140 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_WDRTHR_BF,Second stage WDR merge parameter WDRTHR and BF" hexmask.long.word 0x140 16.--31. 1. "BF,S16 bf parameter for merge" newline hexmask.long.word 0x140 0.--15. 1. "WDRTHR,U16 WDR threshold for merge" line.long 0x144 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_AF,Second stage WDR merge parameter AF" hexmask.long.byte 0x144 16.--21. 1. "AFE,U6 af_e parameter for merge" newline hexmask.long.word 0x144 0.--15. 1. "AFM,S16 af_m parameter for merge" line.long 0x148 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_MA,Second stage WDR merge parameter MA" hexmask.long.word 0x148 16.--31. 1. "MAS,U16 slope for merge MA filter" newline hexmask.long.word 0x148 0.--15. 1. "MAD,U16 lower threshold for merge MA filter" line.long 0x14C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WDRMRG2_CLIP_SFT,Second stage WDR merge clip value and shift before weight block" bitfld.long 0x14C 20.--22. "WTSFT,U3 shift before weight block" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x14C 0.--19. 1. "CLIP,U20 output clip value" line.long 0x150 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_MRGLUT_CFG,Merge LUT configuration" hexmask.long.word 0x150 16.--31. 1. "CLIP,U16 LUT output clip" newline hexmask.long.byte 0x150 1.--5. 1. "BITS,U5 LUT input bit depth up to 24" newline bitfld.long 0x150 0. "EN,LUT enable" "0,1" line.long 0x154 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_LUTDPC_CFG,LUTDPC configuration" hexmask.long.byte 0x154 2.--9. 1. "SIZE,U8 number of LUT entires - 1" newline bitfld.long 0x154 1. "SEL,replace with black (0) or white (1)" "0,1" newline bitfld.long 0x154 0. "EN,LUTDPC enable" "0,1" line.long 0x158 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_EN,OTFDPC enable" hexmask.long.byte 0x158 4.--7. 1. "LUT_MAP,OTF DPC THREHOLD LUT SELECTION MAPPING for 4 color channels. 0:red 1: green 2: blue 3: IR. When LUT_MAP[i]=1 LUT2 threshold will be used for the color i when LUT_MAP[i]=0 LUT1 threshold will be used for the color i." newline bitfld.long 0x158 3. "DETECT_ONLY,OTF DPC DETECTION ONLY CFG. 0: both detection and correction 1: only detection but not correction" "0: both detection and correction,1: only detection but not correction" newline bitfld.long 0x158 1.--2. "STATS_CFG,OTF DPC STATS UPDATE CFG 0: no update 1: update to lower 1024 entries 2: update to higher 1024 entries 3: reserved" "0: no update,1: update to lower 1024 entries,2: update to higher 1024 entries,3: reserved" newline bitfld.long 0x158 0. "EN,OTF DPC enable. 0: disable OTF DPC (none of the other fields in OTFDPC_EN is used) 1: enable OTF DPC" "0: disable OTF DPC,1: enable OTF DPC" line.long 0x15C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP1,OTFDPC threshold and slope 1" hexmask.long.word 0x15C 16.--27. 1. "SLP1,S12Q8 slope at x-position 1" newline hexmask.long.word 0x15C 0.--15. 1. "THR1,U16 threshold at x-position 1" line.long 0x160 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP2,OTFDPC threshold and slope 2" hexmask.long.word 0x160 16.--27. 1. "SLP1,S12Q8 slope at x-position 2" newline hexmask.long.word 0x160 0.--15. 1. "THR1,U16 threshold at x-position 2" line.long 0x164 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP3,OTFDPC threshold and slope 3" hexmask.long.word 0x164 16.--27. 1. "SLP1,S12Q8 slope at x-position 3" newline hexmask.long.word 0x164 0.--15. 1. "THR1,U16 threshold at x-position 3" line.long 0x168 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP4,OTFDPC threshold and slope 4" hexmask.long.word 0x168 16.--27. 1. "SLP1,S12Q8 slope at x-position 4" newline hexmask.long.word 0x168 0.--15. 1. "THR1,U16 threshold at x-position 4" line.long 0x16C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP5,OTFDPC threshold and slope 5" hexmask.long.word 0x16C 16.--27. 1. "SLP1,S12Q8 slope at x-position 5" newline hexmask.long.word 0x16C 0.--15. 1. "THR1,U16 threshold at x-position 5" line.long 0x170 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP6,OTFDPC threshold and slope 6" hexmask.long.word 0x170 16.--27. 1. "SLP1,S12Q8 slope at x-position 6" newline hexmask.long.word 0x170 0.--15. 1. "THR1,U16 threshold at x-position 6" line.long 0x174 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP7,OTFDPC threshold and slope 7" hexmask.long.word 0x174 16.--27. 1. "SLP1,S12Q8 slope at x-position 7" newline hexmask.long.word 0x174 0.--15. 1. "THR1,U16 threshold at x-position 7" line.long 0x178 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRSLP8,OTFDPC threshold and slope 8" hexmask.long.word 0x178 16.--27. 1. "SLP1,S12Q8 slope at x-position 8" newline hexmask.long.word 0x178 0.--15. 1. "THR1,U16 threshold at x-position 8" line.long 0x17C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_LSC_CFG,LSC configuration" bitfld.long 0x17C 16. "DISABLE_LUT_CFG_ERR,Enable/disable lut_cfg_err interrupt. 0: lut_cfg_err interrupt is enabled 1: lut_cfg_err interrupt is disabled to allow SW to reconfig currently unused upper or lower 4 channels of LUT for dual 4 channel support." "0: lut_cfg_err interrupt is enabled,1: lut_cfg_err interrupt is disabled to allow SW to.." newline bitfld.long 0x17C 10.--11. "CHN_MODE,LSC color channel mode 0: legacy 4 channel mode 1: new 4 channel mode (LUT is specified for grid corner for all colors) 2: 8 channel mode 3: reserved" "0: legacy 4 channel mode,1: new 4 channel mode,2: 8 channel mode,3: reserved" newline bitfld.long 0x17C 7.--9. "GAIN_FORMAT,LSC LUT gain format 0:Q8 1:Q8+1 2:Q7 3:Q7+1 4:Q6 5:Q6+1 6:Q5 7:Q5+1" "0: Q8,1: Q8+1,2: Q7,3: Q7+1,4: Q6,5: Q6+1,6: Q5,7: Q5+1" newline bitfld.long 0x17C 4.--6. "MODE_N,vertical LSC LUT downsampling 3:8x 4:16x 5:32x 6:64x 7:128x" "?,?,?,3: 8x,4: 16x,5: 32x,6: 64x,7: 128x" newline bitfld.long 0x17C 1.--3. "MODE_M,horizontal LSC LUT downsampling 3:8x 4:16x 5:32x 6:64x 7:128x" "?,?,?,3: 8x,4: 16x,5: 32x,6: 64x,7: 128x" newline bitfld.long 0x17C 0. "EN,LSC enable" "0,1" line.long 0x180 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WB2_offset12,WB2 white balance offset 1 and 2" hexmask.long.word 0x180 16.--31. 1. "WB_OFST01,S16 WB offset at pixel 01" newline hexmask.long.word 0x180 0.--15. 1. "WB_OFST00,S16 WB offset at pixel 00" line.long 0x184 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WB2_offset34,WB2 white balance offset 3 and 4" hexmask.long.word 0x184 16.--31. 1. "WB_OFST11,S16 WB offset at pixel 11" newline hexmask.long.word 0x184 0.--15. 1. "WB_OFST10,S16 WB offset at pixel 10" line.long 0x188 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WB2_gain12,WB2 white balance gain 1 and 2" hexmask.long.word 0x188 16.--28. 1. "WB_GAIN01,U13Q9 WB gain at pixel 01" newline hexmask.long.word 0x188 0.--12. 1. "WB_GAIN00,U13Q9 WB gain at pixel 00" line.long 0x18C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_WB2_gain34,WB2 white balance gain 3 and 4" hexmask.long.word 0x18C 16.--28. 1. "WB_GAIN11,U13Q9 WB gain at pixel 11" newline hexmask.long.word 0x18C 0.--12. 1. "WB_GAIN10,U13Q9 WB gain at pixel 10" line.long 0x190 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_H3AMUX_CFG,H3A MUX configuration" bitfld.long 0x190 8. "PCIDSEL,H3A input PCID selection 0: RAWFE selection 1: PCID selection" "0: RAWFE selection,1: PCID selection" newline hexmask.long.byte 0x190 2.--5. 1. "SHIFT,U8 number of right shift from 0 to 14" newline bitfld.long 0x190 0.--1. "SEL,H3A input selection 0: long frame 1: short frame 2: very short frame 3: LSC output" "0: long frame,1: short frame,2: very short frame,3: LSC output" line.long 0x194 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_H3ALUT_CFG,H3A LUT configuration" hexmask.long.word 0x194 16.--25. 1. "CLIP,U10 LUT output clip value" newline hexmask.long.byte 0x194 1.--5. 1. "BITS,U5 LUT input bit depth up to 24" newline bitfld.long 0x194 0. "EN,LUT enable" "0,1" line.long 0x198 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_RAWFE_INT_STAT,status/clear register for rawfe interrupts" bitfld.long 0x198 10. "DPC_STATS_READ_ERR,status/clear for DPC stats read error. This is set when reading by SW to DPC stats is started but the last valid stats entry is not read by the end of next frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 9. "LSC_CFG_ERR,status/clear for lsc config error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 8. "DPC_LINE_CFG_ERR,status/clear for dpc line config error. This is set when a write occurs in the middle of frame processing or read that would contend for memory access by HW. This results in data corruption for the frame. When a read to a dpc line memory.." "0,1" newline bitfld.long 0x198 7. "DPC_LUT_CFG_ERR,status/clear for dpc lut configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 6. "H3A_ACCM_CFG_ERR,status/clear for h3a accum configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 5. "H3A_LINE_CFG_ERR,status/clear for h3a line configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 4. "H3A_LUT_CFG_ERR,status/clear for h3a lut configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 3. "WDR_LUT_CFG_ERR,status/clear for wdr lut configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 2. "LUT3_CFG_ERR,status/clear for lut3 configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 1. "LUT2_CFG_ERR,status/clear for lut2 configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x198 0. "LUT1_CFG_ERR,status/clear for lut1 configuration error. This is set when a write or read occurs in the middle of frame processing. This results in data corruption for the frame. write 1 to clear event status write of 0 has no affect" "0,1" group.long 0x200++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_DBG_CTL,debug event and control register" bitfld.long 0x0 12.--14. "DPC_LINE_SEL,select for which dpc line ram to read on debug interface" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "PIPE_ADV_EN_EVENT,enable for pixal pipe line advanced" "0,1" newline bitfld.long 0x0 10. "DPC_OTF_CORR_EN_EVENT,enable for dpc otf corrected a pixel" "0,1" newline bitfld.long 0x0 9. "LSE_INTF_STALL_EN_EVENT,enable for lse slave port stalled by rawfe" "0,1" newline bitfld.long 0x0 8. "LSE_MST_STALL_EN_EVENT,enable for lse maaster port stalled on H3A out I/F" "0,1" newline bitfld.long 0x0 7. "LSE_SLV_STALL_EN_EVENT,enable for lse not sending data in frame on pixel I/F" "0,1" newline bitfld.long 0x0 6. "HE_EN_EVENT,enable for horizantal end" "0,1" newline bitfld.long 0x0 5. "HS_EN_EVENT,enable for horizantal start" "0,1" newline bitfld.long 0x0 4. "VE_EN_EVENT,enable for verticle end" "0,1" newline bitfld.long 0x0 3. "VS_EN_EVENT,enable for verticle start" "0,1" newline bitfld.long 0x0 2. "X_Y_EN_EVENT,enable for x y position match event; Only generates event no halt" "0,1" newline bitfld.long 0x0 1. "X_Y_EN_HALT,enable for x y position match halt; Halts Pipe clear this bit to resume. Only way to resume is to clear this bit back to 0. You would need to clear the status bit after clearing this bit." "0,1" newline bitfld.long 0x0 0. "DBG_EN,Enable debug features set to '0' to disable all events" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_DBG_HWBP,x.y event for event matching" hexmask.long.word 0x4 16.--28. 1. "Y_POS,pixel y position. Can not use 0 as a valid position." newline hexmask.long.word 0x4 0.--12. 1. "X_POS,pixel x position. Can not use 0 as a valid position." line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_DBG_STAT1,status/clear register for debug events" bitfld.long 0x8 11. "PIPE_ADV_EVENT,status/clear for pixal pipe line advanced" "0,1" newline bitfld.long 0x8 10. "DPC_OTF_CORR_EVENT,status/clear for dpc otf corrected a pixel. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 9. "LSE_INTF_STALL_EVENT,status/clear for lse slave port stalled by rawfe. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 8. "LSE_MST_STALL_EVENT,status/clear for lse maaster port stalled. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 7. "LSE_SLV_STALL_EVENT,status/clear for lse not sending data in frame. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 6. "HE_EVENT,status/clear for horizantal end. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 5. "HS_EVENT,status/clear for horizantal start. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 4. "VE_EVENT,status/clear for verticle end. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 3. "VS_EVENT,status/clear for verticle start. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 2. "X_Y_EVENT,status/clear for x y position match event. write 1 to clear event status write of 0 has no affect" "0,1" newline bitfld.long 0x8 1. "X_Y_HALT,status/clear for x y position match halt. write 1 to clear event status write of 0 has no affect" "0,1" rgroup.long 0x20C++0xB line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_DBG_STAT2,current x.y position in frame" hexmask.long.word 0x0 16.--28. 1. "Y_POS,current y position" newline hexmask.long.word 0x0 0.--12. 1. "X_POS,current x position" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_DBG_STAT3,internal state status" hexmask.long 0x4 2.--31. 1. "DPC_MIRROR_STAT,dpc mirror status" newline bitfld.long 0x4 0.--1. "DPC_LINE_RAM_CTL,ram control for understanding the phase of DPC line rams circular buffer for debug reads (limited to line ram 0-3 for legacy mode use only)" "0,1,2,3" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_DBG_STAT4,internal state status" hexmask.long 0x8 0.--31. 1. "LSC_DBG_STAT,lsc state machine" group.long 0x220++0x43 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_CFA_CFG,CFA cfg register" bitfld.long 0x0 2.--4. "PHASE,CFA color phase specifies first red pixel position in first 4x2 pixel array in a frame" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--1. "MODE,CFA pattern mode 0: Legacy 2x2 RGB 1:Enhanced 2x2 RGB 2: 4x4 RGBIR 3: reserved" "0: Legacy 2x2 RGB,1: Enhanced 2x2 RGB,2: 4x4 RGBIR,3: reserved" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRX12,OTFDPC threshold 1 and 2 x-position" hexmask.long.word 0x4 16.--31. 1. "THRX2,U16 threshold 2 x-position. THRX2 > THRX1" newline hexmask.long.word 0x4 0.--15. 1. "THRX1,U16 threshold 1 x-position. THRX1 should be only set to 0." line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRX34,OTFDPC threshold 3 and 4 x-position" hexmask.long.word 0x8 16.--31. 1. "THRX4,U16 threshold 4 x-position. THRX4 > THRX3" newline hexmask.long.word 0x8 0.--15. 1. "THRX3,U16 threshold 3 x-position. THRX3 > THRX2" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRX56,OTFDPC threshold 5 and 6 x-position" hexmask.long.word 0xC 16.--31. 1. "THRX6,U16 threshold 6 x-position. THRX6 > THRX5" newline hexmask.long.word 0xC 0.--15. 1. "THRX5,U16 threshold 5 x-position. THRX5 > THRX4" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_THRX78,OTFDPC threshold 7 and 8 x-position" hexmask.long.word 0x10 16.--31. 1. "THRX8,U16 threshold 8 x-position. THRX8 > THRX7" newline hexmask.long.word 0x10 0.--15. 1. "THRX7,U16 threshold 7 x-position. THRX7 > THRX6" line.long 0x14 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_LUT2_THRSLP1,OTFDPC LUT2 threshold and slope 1" hexmask.long.word 0x14 16.--27. 1. "SLP1,S12Q8 slope" newline hexmask.long.word 0x14 0.--15. 1. "THR1,U16 threshold" line.long 0x18 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_LUT2_THRSLP2,OTFDPC LUT2 threshold and slope 2" hexmask.long.word 0x18 16.--27. 1. "SLP1,S12Q8 slope" newline hexmask.long.word 0x18 0.--15. 1. "THR1,U16 threshold" line.long 0x1C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_LUT2_THRSLP3,OTFDPC LUT2 threshold and slope 3" hexmask.long.word 0x1C 16.--27. 1. "SLP1,S12Q8 slope" newline hexmask.long.word 0x1C 0.--15. 1. "THR1,U16 threshold" line.long 0x20 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_LUT2_THRSLP4,OTFDPC LUT2 threshold and slope 4" hexmask.long.word 0x20 16.--27. 1. "SLP1,S12Q8 slope" newline hexmask.long.word 0x20 0.--15. 1. "THR1,U16 threshold" line.long 0x24 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_LUT2_THRSLP5,OTFDPC LUT2 threshold and slope 5" hexmask.long.word 0x24 16.--27. 1. "SLP1,S12Q8 slope" newline hexmask.long.word 0x24 0.--15. 1. "THR1,U16 threshold" line.long 0x28 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_LUT2_THRSLP6,OTFDPC LUT2 threshold and slope 6" hexmask.long.word 0x28 16.--27. 1. "SLP1,S12Q8 slope" newline hexmask.long.word 0x28 0.--15. 1. "THR1,U16 threshold" line.long 0x2C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_LUT2_THRSLP7,OTFDPC LUT2 threshold and slope 7" hexmask.long.word 0x2C 16.--27. 1. "SLP1,S12Q8 slope" newline hexmask.long.word 0x2C 0.--15. 1. "THR1,U16 threshold" line.long 0x30 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_LUT2_THRSLP8,OTFDPC LUT2 threshold and slope 8" hexmask.long.word 0x30 16.--27. 1. "SLP1,S12Q8 slope" newline hexmask.long.word 0x30 0.--15. 1. "THR1,U16 threshold" line.long 0x34 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_LUT2_THRX12,OTFDPC LUT2 threshold 1 and 2 x-position" hexmask.long.word 0x34 16.--31. 1. "THRX2,U16 threshold 2 x-position. THRX2 > ThRX1" newline hexmask.long.word 0x34 0.--15. 1. "THRX1,U16 threshold 1 x-position. THRX1 should always be set to 0" line.long 0x38 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_LUT2_THRX34,OTFDPC LUT2 threshold 3 and 4 x-position" hexmask.long.word 0x38 16.--31. 1. "THRX4,U16 threshold 4 x-position. THRX4 > ThRX3" newline hexmask.long.word 0x38 0.--15. 1. "THRX3,U16 threshold 3 x-position. THRX3 > ThRX2" line.long 0x3C "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_LUT2_THRX56,OTFDPC LUT2 threshold 5 and 6 x-position" hexmask.long.word 0x3C 16.--31. 1. "THRX6,U16 threshold 6 x-position. THRX6 > ThRX5" newline hexmask.long.word 0x3C 0.--15. 1. "THRX5,U16 threshold 5 x-position. THRX5 > ThRX4" line.long 0x40 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_LUT2_THRX78,OTFDPC LUT2 threshold 7 and 8 x-position" hexmask.long.word 0x40 16.--31. 1. "THRX8,U16 threshold 8 x-position. THRX8 > ThRX7" newline hexmask.long.word 0x40 0.--15. 1. "THRX7,U16 threshold 7 x-position. THRX7 > ThRX6" rgroup.long 0x264++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_OTFDPC_COUNT,OTFDPC detected defect pixel count" hexmask.long.word 0x0 0.--15. 1. "COUNT,U16 OTF detected defect pixel count. Saturated to 65535" group.long 0x268++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_LSC_LUT_MAP07,LSC LUT MAP 0 to 7 define which LUT to use for the first 8 color channels in 4x4 pattern. Color channel 0 corresponds to the first pixel in a 4x4" bitfld.long 0x0 21.--23. "MAP7,U3 LSC LUT MAP for color channel 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "MAP6,U3 LSC LUT MAP for color channel 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15.--17. "MAP5,U3 LSC LUT MAP for color channel 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "MAP4,U3 LSC LUT MAP for color channel 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 9.--11. "MAP3,U3 LSC LUT MAP for color channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "MAP2,U3 LSC LUT MAP for color channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "MAP1,U3 LSC LUT MAP for color channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "MAP0,U3 LSC LUT MAP for color channel 0" "0,1,2,3,4,5,6,7" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__MMR__S_VBUSP__RAWFE_CFG_LSC_LUT_MAP815,LSC LUT MAP 8 to 15 define which LUT to use for the 2nd 8 color channels in 4x4 pattern. Color channel 8 corresponds to the 8th pixel in a 4x4" bitfld.long 0x4 21.--23. "MAP15,U3 LSC LUT MAP for color channel 15" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "MAP14,U3 LSC LUT MAP for color channel 14" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15.--17. "MAP13,U3 LSC LUT MAP for color channel 13" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--14. "MAP12,U3 LSC LUT MAP for color channel 12" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 9.--11. "MAP11,U3 LSC LUT MAP for color channel 11" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--8. "MAP10,U3 LSC LUT MAP for color channel 10" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3.--5. "MAP9,U3 LSC LUT MAP for color channel 9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "MAP8,U3 LSC LUT MAP for color channel 8" "0,1,2,3,4,5,6,7" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_WDR_LUT_RAM_RAWFE_WDR_LUT_RAM" base ad:0x2C122000 group.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VISS_RAWFE__CFG__WDR_LUT__RAM__RAWFE_WDR_LUT_RAM_ram1,Input image width and height." tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_PAR_VPAC_VISS0_S_VBUSP_VPAC_VISS_LSE_CFG_VP" base ad:0x2C100400 rgroup.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_status_param,The STATUS_PARAM register returns the LSE compile configuration parameters." bitfld.long 0x0 30.--31. "BYPASS_CH,Number of available input channel selection for loopback mode" "0,1,2,3" newline bitfld.long 0x0 29. "OUT_SKIP_EN,Output Auto-Skip Enable" "0,1" newline bitfld.long 0x0 28. "CORE_OUT_2D,1D or 2D output addressing mode(2D if 1)" "0,1" newline hexmask.long.byte 0x0 23.--27. 1. "CORE_OUT_DW,Core Output Channel Data Width" newline bitfld.long 0x0 22. "LINE_SKIP_EN,Source Line Inc by 2 Supported (if 1)" "0,1" newline bitfld.long 0x0 21. "BIT_AOFFSET,Source nibble offset address Supported (if 1)" "0,1" newline bitfld.long 0x0 20. "HV_INSERT,H/VBLANK Insertion Supported (if 1)" "0,1" newline bitfld.long 0x0 17.--19. "PIX_MX_HT,Core_Input Pixel Matrix Height" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--16. 1. "CORE_DW,Core Input Data Bus Width" newline bitfld.long 0x0 10.--11. "SL2_OUT_H3A_CH,Number of SL2 H3A Output Channels" "0,1,2,3" newline hexmask.long.byte 0x0 6.--9. 1. "SL2_OUT_CH,Number of SL2 Output Channels" newline bitfld.long 0x0 3.--5. "SL2_IN_CH_THR,Number of Input Channels per thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "VPORT_THR,Number of VPORT input enabled" "0,1" newline bitfld.long 0x0 0.--1. "NTHR,Number of threads supported" "0,1,2,3" group.long 0x4++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_status_error,The STATUS_ERROR register returns the LSE error status." hexmask.long.word 0x0 16.--26. 1. "VPORT_IN_ERR,VPORT_CAL Input Error Status Protocol Errors [26] VS without HS [25] VE without HE [24] VS-VS (missing VE) Error [23] HS-HS (missing HE) Error [22] HE-HE (missing HS) Error [21] VE-VE (missing VS) Error Frame Size Errors [20].." newline hexmask.long.byte 0x0 8.--14. 1. "VM_WR_ERR,VBUSM I/F Last Write Error Status [14:11] Write Channel Number [10:8] VBUSM write error status" newline hexmask.long.byte 0x0 0.--4. 1. "VM_RD_ERR,VBUSM I/F Last Read Error Status [4:3] Read Channel Number [2:0] VBUSM read error status" rgroup.long 0x8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_status_idle_mode,The STATUS_IDLE_MODE register returns IDLE status of LSE VBUSM port and in/output channels - 0: IDLE 1: ACTIVE" bitfld.long 0x0 24. "LSE_OUT_H3A_CHAN,Output H3A Channel Status" "0,1" newline hexmask.long.byte 0x0 12.--16. 1. "LSE_OUT_CHAN,Output Channel[4:0] Status" newline bitfld.long 0x0 11. "VPORT_IN_CHAN,CAL I/F Vport Input Cahnnel Status" "0,1" newline bitfld.long 0x0 4.--6. "LSE_IN_CHAN,Input Channel[2:0] Status" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1. "VM_WR_PORT,SL2 vbusm I/F Write Port Status" "0,1" newline bitfld.long 0x0 0. "VM_RD_PORT,SL2 vbusm I/F Read Port Status" "0,1" group.long 0xC++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_cfg_lse,The CFG_LSE register configures the LSE general hardware modes." bitfld.long 0x0 8. "PSA_EN,Test mode Output Channel Signature Generation Enable 0: Disable (default) 1: Enable When enabled LSE generates a unique CRC signature for each output channel's frame data at frame completion." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 5. "IN_CH_SYNC_MODE,Input Channel Transfer Sync Mode (applicable only for VISS) 0: Line Mode 1: Frame Mode (default) When set to 0 (Line Mode) LSE waits for a HTS_TSTART on every line reads from SL2. When set to 1 (Frame Mode) LSE waits for the.." "0: Line Mode,1: Frame Mode" newline bitfld.long 0x0 4. "VM_ARB_FIXED_MODE,VBUSM Arbitration Fixed Mode select 0: Round-Robin Arbitration (default) 1: Fixed-mode Arbitration" "0: Round-Robin Arbitration,1: Fixed-mode Arbitration" newline bitfld.long 0x0 2.--3. "LOOPBACK_IN_CH_SEL,Loopback Input Channel Select (applicable only for VISS) 0: Ch0/CAL_Vport_In 1: Ch1 2: Ch2" "0: Ch0/CAL_Vport_In,1: Ch1,2: Ch2,?" newline bitfld.long 0x0 1. "LOOPBACK_CORE_EN,Functional path (data to HWA core) enable during loopback mode 0: Disable 1: Enable When enabled the loopback-enabled input channel is used also for CORE data input. Otherwise it is strictly used for the loopback path." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 0. "LOOPBACK_EN,LSE loopback mode enable 0: Disable 1: Enable When enabled selected input channel data is looped back out to the last (#4) output channel." "0: Disable,1: Enable When enabled" group.long 0x13C++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_dst_common_cfg,The DST_COMMON_CFG register captures common configuration for the output channels" hexmask.long.byte 0x0 0.--5. 1. "ROUNDING_OFFSET,output channel rounding offset value. Default value to be considered 6'h08" rgroup.long 0x140++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_psa_signature,The PSA_SIGNATURE register returns the captured PSA signature value of the last frame data of output channel [a]." hexmask.long 0x0 0.--31. 1. "VALUE,32-bit CRC signature value" rgroup.long 0x1E0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_dbg,The DBG register returns the current status of internal FSM - TI internal use only." hexmask.long 0x0 0.--31. 1. "STATUS,Debug status" group.long 0x10++0x13 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_cfg,The SRC_CFG register configures the input channels for the processing thread" hexmask.long.word 0x0 22.--31. 1. "VP_HBLNK_CNT,Number of HBlank Pixels to insert between active lines for internal vport interface to core. (Max=1023) Must be set to 0 if hblank insertion is not needed by HWA_CORE Else must be at least 2 (2 or more hblank cycles)" newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Input Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Input Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Input pixel container size must be same or larger than input pixel width." "0: 8-bit,1: 12-bit,2: 16-bit,3: reserved Input pixel container size must be same.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Input Pixel Width Sel 0: 8-bit 1: 12-bit 2: 14-bit 3: 16-bit The width defines the bit-depth of the pixel data to be extracted from the pixel container." "0: 8-bit,1: 12-bit,2: 14-bit,3: 16-bit The width defines the bit-depth of the.." line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_vpin_cfg,The SRC_VPIN_CFG register configures the VPORT input channel for the processing thread" bitfld.long 0x4 4. "VP_PROTOCOL_CHK,Vport Input Data Protocol Check Enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline bitfld.long 0x4 2.--3. "VPORT_PW,Vport Pixel Data Width Sel 0: 8-bit 1: 12-bit 2: 14-bit 3: 16-bit Vport Pixels are always LSB aligned in 16-bit halfword" "0: 8-bit,1: 12-bit,2: 14-bit,3: 16-bit Vport Pixels are always LSB aligned in.." newline bitfld.long 0x4 1. "VPORT_TWO_PIXEL,Number of pixels per vport cycles 0: 1 pixels 1: 2 pixels" "0: 1 pixels,1: 2 pixels" newline bitfld.long 0x4 0. "VPORT_EN,vport_en 0: Disable 1: Enable When Enabled external VPORT input data is selected instead of SRC channel 0 of this thread" "0: Disable,1: Enable When Enabled" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_frame_size,The SRC_FRAME_SIZE register configures the frame size of all input buffers for the processing thread ." hexmask.long.word 0x8 16.--28. 1. "HEIGHT,SL2 - Source Buffer Height (number of lines)" newline hexmask.long.word 0x8 0.--12. 1. "WIDTH,SL2 - Source Buffer Width (number of pixels)" line.long 0xC "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_buf_attr,The SRC_BUF_ATTR register configures the common attributes of all SL2 source buffers for the processing thread ." hexmask.long.word 0xC 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0xC 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0xC 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" line.long 0x10 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_buf_ba,The SRC_BUF_BA[b] register configures the base address of the SL2 source buffer [b] for the processing thread ." bitfld.long 0x10 31. "ENABLE,Input Buffer Enable 0: Disable 1: Enable When the processing thread is enabled at least one of the input buffer must be enabled" "0: Disable,1: Enable When the processing thread is enabled" newline hexmask.long.tbyte 0x10 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x10 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" group.long 0x50++0x7 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_buf_cfg,The DST_BUF_CFG register configures the output buffer channel ." rbitfld.long 0x0 31. "CH_DISABLED,Channel Disable Status (read-only) 0: (Default) Chanel is enabled for Y UV or YUV422 data transfer to SL2 memory. All configurations associated with this DST_BUF[a] are valid. 1: Channel is disabled for SL2 data transfer (because the.." "0: (Default,1: Channel is disabled for SL2 data transfer" newline bitfld.long 0x0 29. "YUV422_INTLV_ORDER,YUV422 Interleaving Order Selection 0: UYVY 1: YUYV Only Applicable if this output channel is YUV422 output capable LUMA channel. Otherwise setting has no effect." "0: UYVY,1: YUYV Only Applicable if this output channel is.." newline bitfld.long 0x0 28. "YUV422_OUT_EN,YUV422 Interleaved Output Merge Enable 0: Disable 1: Enable When enabled this channel interleaves data from the associated chroma data output channel to output YUV422 interleaved data to the SL2 memory. Only Applicable if this output.." "0: Disable,1: Enable When enabled" newline bitfld.long 0x0 10. "ENABLE_SIGNED_ACCLERATOR_DATA,Specify the acclerator data to be signed or unsigned 0: Unsigned data (By default) 1: Signed Data" "0: Unsigned data,1: Signed Data" newline bitfld.long 0x0 9. "ENABLE_OUTPUT_PIXEL_ROUNDING,enable acclerator pixel output rounding 0: Disable rounding logic 1: Enable rounding logic" "0: Disable rounding logic,1: Enable rounding logic" newline bitfld.long 0x0 4. "PIX_FMT_ALIGN,Output Pixel Container Alignment 0: LSB-aligned 1: MSB-aligned" "0: LSB-aligned,1: MSB-aligned" newline bitfld.long 0x0 2.--3. "PIX_FMT_CNTRSZ,Output Pixel Container Size Sel 0: 8-bit 1: 12-bit 2: 16-bit 3: reserved Output pixel container size must be same or larger than output pixel width. If yuv422_out_en is set pix_fmt_cntrsz must be 0." "0: 8-bit,1: 12-bit,2: 16-bit,3: reserved Output pixel container size must be.." newline bitfld.long 0x0 0.--1. "PIX_FMT_PW,Output Pixel Width Sel 0: 8-bit 1: 12-bit 2: reserved 3: 16-bit The width defines the bit-depth of the pixel data to be stored in the pixel container." "0: 8-bit,1: 12-bit,2: reserved,3: 16-bit The width defines the bit-depth of the.." line.long 0x4 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_buf_attr0,The DST_BUF_ATTR0 register configures the attributes of the output SL2 buffer ." hexmask.long.byte 0x4 25.--31. 1. "LOUT_SKIP_INIT,Line Out Initial Skip Count - The number of initial HTS tstart/tdone cycles with no output from the core on this output channel. The LSE will auto-generate the channel done status during these cycles." newline hexmask.long.word 0x4 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of line buffers)" newline hexmask.long.word 0x4 6.--15. 1. "BUF_STRIDE,Buffer Stride Size [15:6] (64 byte multiple) stride size" newline hexmask.long.byte 0x4 0.--5. 1. "BUF_STRIDE_6_LSB,Buffer Stride Size [5:0] - 6 LSB bits of buffer stride size should always be 0. Writes have no effect. Always read as 0" group.long 0x5C++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_buf_ba,The DST_BUF_BA register configures the base address of the output SL2 circular buffer ." bitfld.long 0x0 31. "ENABLE,Output Channel Enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline hexmask.long.tbyte 0x0 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x0 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" group.long 0xF0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_buf_attr,The H3A_BUF_ATTR register configures the attributes of the H3A output SL2 buffer." hexmask.long.word 0x0 16.--24. 1. "CBUF_SIZE,SL2 Circular Buffer Size (number of H3A Line buffers)" newline hexmask.long.word 0x0 6.--15. 1. "H3A_LN_SIZE,H3A Output Done Line Size [15:0] Size of H3A output line size in bytes for HTS Done generation (64 byte multiple) This is equivalent to Buf_Stride." newline hexmask.long.byte 0x0 0.--5. 1. "H3A_LN_SIZE_6_LSB,H3A Output Done Line Size [5:0] - 6 LSB bits should always be 0. Writes have no effect. Always read as 0" group.long 0xF8++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__PAR_VPAC_VISS0__S_VBUSP__VPAC_VISS_LSE__CFG_VP__REGS_buf_ba,The H3A_BUF_BA register configures the base address of the H3A output SL2 circular buffer." bitfld.long 0x0 31. "ENABLE,Output H3A Buffer Enable 0: Disable 1: Enable" "0: Disable,1: Enable" newline hexmask.long.tbyte 0x0 6.--23. 1. "ADDR,Base Address[23:6] - (64 Byte aligned) byte address" newline hexmask.long.byte 0x0 0.--5. 1. "ADDR_6_LSB,Base Address[5:0] - 6 LSB bits of address should always be 0. Writes have no effect. Always read as 0" tree.end tree "VPAC0_COMMON_0_IVPAC_TOP_0_CFG_SLV_VPAC_REGS_VPAC_REGS_CFG_IP_MMRS" base ad:0x2C000000 rgroup.long 0x0++0x3 line.long 0x0 "IVPAC_TOP_0__CFG_SLV__VPAC_REGS__VPAC_REGS_CFG__IP_MMRS_PID,VPAC PID" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and new scheme. Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU indicator DSPS ==> 0x0 WTBU ==> 0x1 Processors ==> 0x2" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family. If there is no level of software compatibility a new FUNC number and hence PID should be assigned." hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version. R as described in PDR with additional clarifications and definitions below. Must be easily ECO-able or controlled during fabrication. Ideally through a top level metal mask or e-fuse. This number is maintained/owned by IP design.." newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision. X as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. X is part of IP numbering X.Y.R.Z. X changes ONLY when: (1) There is a major feature addition. An.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers. 0 if non-custom." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision. Y as described in PDR with additional clarifications/definitions below. This number is owned/maintained by IP specification owner. Y changes ONLY when: (1) Features are scaled (up or down). Flexibility exists in that this.." group.long 0x4++0xF line.long 0x0 "IVPAC_TOP_0__CFG_SLV__VPAC_REGS__VPAC_REGS_CFG__IP_MMRS_ENABLE,VPAC accelerators Enable; used in clock gating accelerator when disabled. NOT SUPPORTED IN current VERSION" bitfld.long 0x0 5. "NF_ENABLE,'1' --> nf is enabled '0' --> nf is disabled" "0,1" bitfld.long 0x0 4. "MSC_ENABLE,'1' --> msc is enabled '0' --> msc is disabled" "0,1" newline bitfld.long 0x0 2. "LDC0_ENABLE,'1' --> ldc0 is enabled '0' --> ldc0 is disabled" "0,1" bitfld.long 0x0 0. "VISS0_ENABLE,'1' --> viss0 is enabled '0' --> viss0 is disabled" "0,1" line.long 0x4 "IVPAC_TOP_0__CFG_SLV__VPAC_REGS__VPAC_REGS_CFG__IP_MMRS_CG_ENABLE_OVERRIDE,Register to override the dynamic auto clock gating done in VPAC to reduce power.By default these bits are 0. it should be set to 1 only when we encounter some silicon bug." bitfld.long 0x4 31. "VPAC_SL2_MSRAM_CG_NOGATE,'1' --> No clock gating in SL2 MSRAM '0' --> auto clock gating enabled. Not to be used in this version of HW" "0,1" bitfld.long 0x4 30. "VPAC_SL2_CBASS_CG_NOGATE,'1' --> No clock gating in SL2 MSRAM '0' --> auto clock gating enabled." "0,1" newline bitfld.long 0x4 29. "VPAC_DMASCR_CG_NOGATE,'1' --> No clock gating in SL2 MSRAM '0' --> auto clock gating enabled." "0,1" bitfld.long 0x4 28. "VPAC_ASYNC_DATAMST1M2M_CG_NOGATE,'1' --> No clock gating in data_mst1 async m2m '0' --> auto clock gating enabled" "0,1" newline bitfld.long 0x4 27. "VPAC_ASYNC_DATAMST0M2M_CG_NOGATE,'1' --> No clock gating in data_mst0 async m2m '0' --> auto clock gating enabled" "0,1" bitfld.long 0x4 26. "VPAC_ASYNC_MEMSLVM2M_CG_NOGATE,'1' --> No clock gating in mem_slv async m2m '0' --> auto clock gating enabled" "0,1" newline bitfld.long 0x4 25. "VPAC_ASYNC_LDCM2M_CG_NOGATE,'1' --> No clock gating in ldc_mst async m2m '0' --> auto clock gating enabled" "0,1" bitfld.long 0x4 24. "VPAC_ASYNC_FWMCBASS_CG_NOGATE,'1' --> No clock gating in vpac fw vbusm async cbass '0' --> auto clock gating enabled." "0,1" newline bitfld.long 0x4 23. "VPAC_ASYNC_FWPCBASS_CG_NOGATE,'1' --> No clock gating in vpac fw vbusp async cbass '0' --> auto clock gating enabled." "0,1" bitfld.long 0x4 22. "VPAC_ASYNC_CFGCBASS_CG_NOGATE,'1' --> No clock gating in vpac config async cbass '0' --> auto clock gating enabled" "0,1" newline bitfld.long 0x4 21. "VPAC_MEMSLVM2M_CG_NOGATE,'1' --> No clock gating in memslv rd reassembly m2m '0' --> auto clock gating enabled" "0,1" bitfld.long 0x4 20. "VPAC_UTC1RDM2M_CG_NOGATE,'1' --> No clock gating in utc1 rd reassembly m2m '0' --> auto clock gating enabled." "0,1" newline bitfld.long 0x4 19. "VPAC_UTC0RDM2M_CG_NOGATE,'1' --> No clock gating in utc0 rd reassembly m2m '0' --> auto clock gating enabled." "0,1" bitfld.long 0x4 18. "VPAC_CFGCBASS_CG_NOGATE,'1' --> No clock gating in vpac config cbass '0' --> auto clock gating enabled" "0,1" newline bitfld.long 0x4 17. "VISS0_CBASS_CG_NOGATE,'1' --> No clock gating in viss cbass '0' --> auto clock gating enabled" "0,1" bitfld.long 0x4 16. "HTS_CG_OVERRIDE,'1' --> clock gating override '0' --> No clock gating override" "0,1" newline bitfld.long 0x4 4. "MSC_CG_OVERRIDE,'1' --> clock gating override '0' --> No clock gating override" "0,1" bitfld.long 0x4 2. "LDC0_CG_OVERRIDE,'1' --> clock gating override '0' --> No clock gating override" "0,1" newline bitfld.long 0x4 0. "VISS0_CG_OVERRIDE,'1' --> clock gating override '0' --> No clock gating override" "0,1" line.long 0x8 "IVPAC_TOP_0__CFG_SLV__VPAC_REGS__VPAC_REGS_CFG__IP_MMRS_VPAC_CTRL,Register to control and do event selection for VPAC module" bitfld.long 0x8 4. "CTSET_DMA_SOC_DBG,select config for CTSET[206:175] '0' --> select UTC utc_ctset_intr[31:0] '1' --> Select ldc0_rd NRT_ext RT_ext master ports (sreq rreq creq stall valid creq)" "0,1" bitfld.long 0x8 3. "CTSET_UTC_SL2_DBG,select config for CTSET[254:239] '0' --> select ext_ctset_event[15:0] '1' --> Select NRT_wr NRT_rd RT_wr RT_rd master ports (sreq rreq creq stall valid creq)" "0,1" newline bitfld.long 0x8 2. "CTSET_HWA_SL2_DBG,select config for CTSET[142:111] '0' --> Select UTC utc_channel_start[31:0] '1' --> Select nf msc ldc0 viss0 master ports (sreq rreq creq stall valid creq)" "0,1" bitfld.long 0x8 1. "CTSET_RT_UTC_OUT,select config for CTSET[238:207] '0' --> Select UTC utc_ctset_intr[63:32] '1' --> Select UTC utc_ctset_intr[31:0]" "0,1" newline bitfld.long 0x8 0. "CTSET_RT_UTC_IN,select config for CTSET[174:143] '0' --> Select UTC utc_channel_start[63:32] '1' --> 32'b0" "0,1" line.long 0xC "IVPAC_TOP_0__CFG_SLV__VPAC_REGS__VPAC_REGS_CFG__IP_MMRS_VPAC_TEST_CTRL,Register to control testing config" bitfld.long 0xC 1. "UTC1_CFG_PBIST_OVERRIDE,'1' --> Config pbist mode: forces UTC1 interface to allow free running clock to RAM during config PBIST '0' --> FUNC mode" "0,1" bitfld.long 0xC 0. "UTC0_CFG_PBIST_OVERRIDE,'1' --> Config pbist mode: forces UTC0 interface to allow free running clock to RAM during config PBIST '0' --> FUNC mode" "0,1" tree.end tree.end tree.end endif tree "WKUP" base ad:0x0 sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-MCU")) tree "WKUP_PSC0" base ad:0x4000000 rgroup.long 0x0++0x3 line.long 0x0 "VBUS_PID,The peripheral identification register is a constant register that contains the ID and ID revision number for that module. The PID stores version information used to identify the module. All bits within this register are read-only (writes have.." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release" bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" rgroup.long 0x10++0x7 line.long 0x0 "VBUS_GBLCTL,This register contains global control to PSC." hexmask.long.byte 0x0 8.--15. 1. "IO_ANA_CTL,General purpose IO/Analog PowerDown control. Directly drives io_ana_pdctl_po[7:0] outputs." line.long 0x4 "VBUS_GBLSTAT,This register shows the PSC global status." hexmask.long.word 0x4 16.--27. 1. "EF_SMRFLEX,Smart reflex class0 bits" bitfld.long 0x4 0. "OVRIDE,PSC Override Status" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "VBUS_INTEVAL,This register has no storage. Read from this register returns 0." bitfld.long 0x0 19. "GOSET,GOSTAT Interrupt Set" "0,1" bitfld.long 0x0 18. "EPCSET,External Power Control Interrupt Set" "0,1" bitfld.long 0x0 17. "ERRSET,Combined Interrupt Set" "0,1" newline bitfld.long 0x0 2. "EPCEV,External Power Control Interrupt Set" "0,1" bitfld.long 0x0 1. "ERREV,Re_evaluate Error Interrupt" "0,1" bitfld.long 0x0 0. "ALLEV,Re_evaluate combined PSC interrupt" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "VBUS_MERRPR,This register records pending error conditions for all modules. Each bit represents one module (index 0 for modules 0-31. index 1 for modules 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "M,Records pending error conditions. Each bit n represents a module." group.long 0x50++0x3 line.long 0x0 "VBUS_MERRCR,This register has no storage. Read from this register returns 0. Each bit represents one module (index 0 for modules 0-31. index 1 for modules 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "M,Write of 1 clears the corresponding MERRPR bit." rgroup.long 0x60++0x3 line.long 0x0 "VBUS_PERRPR,This register records pending error conditions for each power domain. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "P,Power Domain n Error Condition. Each bit n represents a power domain." group.long 0x68++0x3 line.long 0x0 "VBUS_PERRCR,This register has no storage. Read from this register returns 0. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "P,Write of 1 clears the corresponding PERRPR bit." rgroup.long 0x70++0x3 line.long 0x0 "VBUS_EPCPR,This register records pending external power control conditions. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "EPC,External Power Control Intervention Request for Power Domain n" group.long 0x78++0x3 line.long 0x0 "VBUS_EPCCR,This register has no storage. Read from this register returns 0. Each bit represents one domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "EPC,Write of 1 clears the corresponding EPCPR bit" rgroup.long 0x100++0x3 line.long 0x0 "VBUS_RAILSTAT,This register is a read-only and shows the current rail requestor whose request is being granted and the current value of the counter associated with this requestor." hexmask.long.byte 0x0 24.--28. 1. "RAILNUM,Indicates Current Rail Requestor being processed by GPSC" hexmask.long.byte 0x0 0.--7. 1. "RAILCNT,Indicates the current rail counter value" group.long 0x104++0x7 line.long 0x0 "VBUS_RAILCTL,This register is user programmable. It holds the counter values for rail counter. User can select one of the two counter values to be used for each power domain (see RAILSEL register)." hexmask.long.byte 0x0 8.--15. 1. "RAILCTR1,Rail Counter Value 1" hexmask.long.byte 0x0 0.--7. 1. "RAILCTR0,Rail Counter Value 0" line.long 0x4 "VBUS_RAILSEL,User can use this register to select the counter value (RAILCTL) for each power domain." hexmask.long 0x4 0.--31. 1. "P,Rail Counter Select for Power Domain" group.long 0x120++0x3 line.long 0x0 "VBUS_PTCMD,This is a pseudo-command register with no actual storage. Reads return 0. One bit for each power domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "GO,Power Domain n GO Transition" rgroup.long 0x128++0x3 line.long 0x0 "VBUS_PTSTAT,This is a status register. One bit for each power domain (index 0 for domains 0-31. index 1 for domains 32-63. etc.)." hexmask.long 0x0 0.--31. 1. "GOSTAT,Power Domain n Transition Command Status" rgroup.long 0x200++0x3 line.long 0x0 "VBUS_PDSTAT,This is a status register. One register per power domain. Each register contains the status for the given power domain." bitfld.long 0x0 11. "EMUIHB,Emulation Alters Domain State" "0,1" bitfld.long 0x0 10. "PWRBAD,Power Bad error" "0,1" bitfld.long 0x0 9. "PORDONE,POR Done Input Status" "0,1" newline bitfld.long 0x0 8. "PORZ,PORz output actual status" "0,1" hexmask.long.byte 0x0 0.--4. 1. "STATE,Current Power Domain State" group.long 0x300++0x3 line.long 0x0 "VBUS_PDCTL,This is a control register. One register per power domain." bitfld.long 0x0 31. "FORCE,Force Bit" "0,1" bitfld.long 0x0 29. "PWRSW,Power shorting Switch Control" "0,1" bitfld.long 0x0 28. "ISO,Isolation Cell control" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "WAKECNT,RAM wake count delay value" bitfld.long 0x0 12.--14. "PDMODE,Power Down mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. "EMUIHBIE,Emulation alters domain state" "0,1" newline bitfld.long 0x0 8. "EPCGOOD,External Power Control Power Good Indication" "0,1" bitfld.long 0x0 0. "NEXT,User_Desired Next Power Domain State" "0,1" rgroup.long 0x400++0x3 line.long 0x0 "VBUS_PDCFG,This is a status register. It shows PSC settings for easy debug." bitfld.long 0x0 3. "ICEPICK,Icepick support" "0,1" bitfld.long 0x0 1. "MEMSLPKWK,Memory sleep-wake domain" "0,1" bitfld.long 0x0 0. "ALWAYSON,Always on power domain" "0,1" rgroup.long 0x600++0x3 line.long 0x0 "VBUS_MDCFG,This is a constant register showing some PSC settings for easy debug. This register is read only." hexmask.long.byte 0x0 16.--20. 1. "PWRDOM,Indicates which power domain this module belongs to" bitfld.long 0x0 15. "AUTOONLY,0: This LPSC supports all modes 1: This LPSC supports Enable AutoSleep or AutoWake only" "0: This LPSC supports all modes,1: This LPSC supports Enable" bitfld.long 0x0 14. "RESETISO,0: This LPSC does not support Reset Isolation 1: This LPSC supports Reset Isolation" "0: This LPSC does not support Reset Isolation,1: This LPSC supports Reset Isolation" newline bitfld.long 0x0 13. "NEXTLOCK,0: MDCTL.NEXT field is writable 1: MDCTL.NEXT field is locked" "0: MDCTL,1: MDCTL" bitfld.long 0x0 12. "ASYNC,Async Lpsc" "0,1" bitfld.long 0x0 11. "ICEPICK,IcePick support" "0,1" newline bitfld.long 0x0 10. "PERMDIS,Permanently disable" "0,1" bitfld.long 0x0 9. "PLLHANDSHAKE,RTL parameter PLL_HANDSHAKE" "0,1" bitfld.long 0x0 6.--8. "NUMSCRDISBALE,Number of PWR_SCR_DISABLE interfaces required on LPSC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--5. "NUMCLKEN,Number of PWR_CLK_EN interfaces required on LPSC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "NUMCLK,Number of PWR_CLKSTOP interfaces required on LPSC" "0,1,2,3,4,5,6,7" rgroup.long 0x800++0x3 line.long 0x0 "VBUS_MDSTAT,This register shows the status of each module. Requires one register per module on the device." bitfld.long 0x0 17. "EMUIHB,Emulation Alters Module State. Inhibits Module Inactive or Force Module Active." "0,1" bitfld.long 0x0 16. "EMURST,Emulation Alters Reset" "0,1" bitfld.long 0x0 12. "MCKOUT,Actual modclk output to module" "0,1" newline bitfld.long 0x0 11. "MRSTDONE,Module reset initialization done status" "0,1" bitfld.long 0x0 10. "MRSTZ,Module reset actual status" "0,1" bitfld.long 0x0 9. "LRSTDONE,Module local reset initialization done status" "0,1" newline bitfld.long 0x0 8. "LRSTZ,Module local reset actual status" "0,1" hexmask.long.byte 0x0 0.--5. 1. "STATE,These bits indicate the current module state" group.long 0xA00++0x3 line.long 0x0 "VBUS_MDCTL,This register provides specific control for the individual module. One register per module on the device." bitfld.long 0x0 31. "FORCE,Force Bit" "0,1" bitfld.long 0x0 12. "RESETISO,Reset Isolation" "0,1" bitfld.long 0x0 11. "BLKCHIP1RST,Block Chip_1_Reset" "0,1" newline bitfld.long 0x0 10. "EMUIHBIE,Emulation Alters Module State. Inhibits Module Inactive or Force Module Active." "0,1" bitfld.long 0x0 9. "EMURSTIE,Emulation Alter Reset Interrupt Enable" "0,1" bitfld.long 0x0 8. "LRSTZ,Module local reset control" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "NEXT,Module Next State" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-MCU")) tree "WKUP_PLL0_CFG" base ad:0x4040000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_pll0_PID" bitfld.long 0x0 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit - Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE,Module functional identifier" hexmask.long.byte 0x0 11.--15. 1. "MISC,Misc revision number" bitfld.long 0x0 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,custom revision number" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number" rgroup.long 0x8++0x3 line.long 0x0 "CFG_pll0_CFG" hexmask.long.word 0x0 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock" bitfld.long 0x0 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved" "0,1,2,3" bitfld.long 0x0 8. "SSM_WVTBL,Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present" "0,1" bitfld.long 0x0 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL" "0,1,2,3" group.long 0x10++0x7 line.long 0x0 "CFG_pll0_LOCKKEY0" hexmask.long 0x0 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers" rbitfld.long 0x0 0. "UNLOCKED,Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing." "0,1" line.long 0x4 "CFG_pll0_LOCKKEY1" hexmask.long 0x4 0.--31. 1. "LOCKKEY1_VAL,Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers" group.long 0x20++0x3 line.long 0x0 "CFG_pll0_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the.." "0,1" bitfld.long 0x0 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 -.." "0,1" bitfld.long 0x0 15. "PLL_EN,PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled" "0,1" bitfld.long 0x0 8. "INTL_BYP_EN,PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock" "0,1" bitfld.long 0x0 5. "CLK_4PH_EN,Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2 FOUT3 FOUT4 clocks are enabled." "0,1" newline bitfld.long 0x0 4. "CLK_POSTDIV_EN,Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV 4-phase and synchronous clocks are enabled." "0,1" bitfld.long 0x0 1. "DSM_EN,Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode)" "0,1" bitfld.long 0x0 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer.." "0,1" rgroup.long 0x24++0x3 line.long 0x0 "CFG_pll0_STAT" bitfld.long 0x0 0. "LOCK,PLL lock status. Software should wait for lock to be asserted before clearing the PLL_CTRL_bypass_en bit 1'b0 - PLL is not locked 1'b1 - PLL is locked" "0,1" group.long 0x30++0xB line.long 0x0 "CFG_pll0_FREQ_CTRL0" hexmask.long.word 0x0 0.--11. 1. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 -.." line.long 0x4 "CFG_pll0_FREQ_CTRL1" hexmask.long.tbyte 0x4 0.--23. 1. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209.." line.long 0x8 "CFG_pll0_DIV_CTRL" bitfld.long 0x8 24.--26. "POST_DIV2,Secondary post divider. Supports values of 1-7" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "POST_DIV1,Primary post divider. To ensure correct operation post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--5. 1. "REF_DIV,Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63" group.long 0x40++0x7 line.long 0x0 "CFG_pll0_SS_CTRL" bitfld.long 0x0 31. "BYPASS_EN,Bypass the SS modulator. 1'b0 - Spread spectrum modulation is enabled 1'b1 - SSMOD is bypassed. No modulation of PLL frequency" "0,1" hexmask.long.byte 0x0 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address. Indicates the maximum number of address bits used to access the external wave table. These bits are not used if PLL_CFG_ssm_wvtbl = 0" bitfld.long 0x0 15. "RESET,SSM reset. When set to 1 the SSM modulator is in reset" "0,1" bitfld.long 0x0 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance 1'b0 - Center spread 1'b1 - Down spread" "0,1" bitfld.long 0x0 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved): 1'b0 - Use 128 point triangle wave table 1'b1 - Use external wave table" "0,1" line.long 0x4 "CFG_pll0_SS_SPREAD" hexmask.long.byte 0x4 16.--19. 1. "MOD_DIV,Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-63" hexmask.long.byte 0x4 0.--4. 1. "SPREAD,Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1%" group.long 0x60++0x3 line.long 0x0 "CFG_pll0_CAL_CTRL" bitfld.long 0x0 31. "CAL_EN,Calibration enable to actively adjust for input skew 1'b0 - Disabled. Static phase offset determined by analog matching only 1'b1 - Enabled. Static phase offset adjusted by phase sensing at input" "0,1" bitfld.long 0x0 20. "FAST_CAL,Fast calibration enabled 1'b0 - Normal operation 1'b1 - Used for initial calibration if initial value is not already known" "0,1" bitfld.long 0x0 16.--18. "CAL_CNT,Calibration loop programmable counter. Selects the number of PFD edges to wait after each calibration step defined by 2**cal_cnt" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "CAL_BYP,Calibration bypass 1'b0 - Use the calibration output to set the phase correction 1'b1 - Use the cal_in input value to set the phase correction" "0,1" hexmask.long.word 0x0 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration. When cal_byp is 1'b1 this is the override value for calibration. Value is a signed integer with positive values delaying the faster path reset and.." rgroup.long 0x64++0x3 line.long 0x0 "CFG_pll0_CAL_STAT" bitfld.long 0x0 31. "CAL_LOCK,Reserved for future use" "0,1" hexmask.long.byte 0x0 16.--19. 1. "LOCK_CNT,Reserved for future use" hexmask.long.word 0x0 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0. If cal_byp = 1'b1 it is a buffer version of cal_in[11:0]. Can be used to read the phase calibration state to for later use as an override value to bypass skew calibration" group.long 0x80++0x1B line.long 0x0 "CFG_pll0_HSDIV_CTRL0" bitfld.long 0x0 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x0 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x0 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x0 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x4 "CFG_pll0_HSDIV_CTRL1" bitfld.long 0x4 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x4 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x4 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x8 "CFG_pll0_HSDIV_CTRL2" bitfld.long 0x8 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x8 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x8 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x8 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0xC "CFG_pll0_HSDIV_CTRL3" bitfld.long 0xC 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0xC 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0xC 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0xC 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x10 "CFG_pll0_HSDIV_CTRL4" bitfld.long 0x10 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x10 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x10 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x10 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x14 "CFG_pll0_HSDIV_CTRL5" bitfld.long 0x14 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x14 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x14 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x14 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" line.long 0x18 "CFG_pll0_HSDIV_CTRL6" bitfld.long 0x18 31. "RESET,SSM reset. When set to 1 the SSM modulator is in resetl" "0,1" bitfld.long 0x18 15. "CLKOUT_EN,CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1" "0,1" bitfld.long 0x18 8. "SYNC_DIS,Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous" "0,1" hexmask.long.byte 0x18 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-MCU")) tree "WKUP_PADCFG_CTRL0_CFG0" base ad:0x4080000 rgroup.long 0x0++0xB line.long 0x0 "CFG0_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16" hexmask.long.byte 0x0 11.--15. 1. "PID_MISC" newline bitfld.long 0x0 8.--10. "PID_MAJOR" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "PID_CUSTOM" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR" line.long 0x4 "CFG0_MMR_CFG0" hexmask.long.word 0x4 16.--31. 1. "MMR_CFG0_CFG_REV,Major configuration release" hexmask.long.word 0x4 0.--15. 1. "MMR_CFG0_SPEC_REV,Minor spec-only revision. Doesn't change RTL release" line.long 0x8 "CFG0_MMR_CFG1" bitfld.long 0x8 31. "MMR_CFG1_PROXY_EN,Proxy addressing enabled" "0,1" hexmask.long.byte 0x8 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions" group.long 0x1008++0x1B line.long 0x0 "CFG0_LOCK0_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK0_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" line.long 0x8 "CFG0_intr_raw_status" bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "CFG0_intr_enabled_status_clear" bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "CFG0_intr_enable" bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "CFG0_intr_enable_clear" bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "CFG0_eoi" hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0xB line.long 0x0 "CFG0_fault_address" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." line.long 0x4 "CFG0_fault_type_status" bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.." line.long 0x8 "CFG0_fault_attr_status" hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID." hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID." wgroup.long 0x1030++0x3 line.long 0x0 "CFG0_fault_clear" bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" rgroup.long 0x1100++0x3 line.long 0x0 "CFG0_CLAIMREG_P0_R0_READONLY" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0_READONLY,Claim bits for Partition 0" rgroup.long 0x2000++0xB line.long 0x0 "CFG0_PID_PROXY" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16_PROXY" hexmask.long.byte 0x0 11.--15. 1. "PID_MISC_PROXY" newline bitfld.long 0x0 8.--10. "PID_MAJOR_PROXY" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "PID_CUSTOM_PROXY" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR_PROXY" line.long 0x4 "CFG0_MMR_CFG0_PROXY" hexmask.long.word 0x4 16.--31. 1. "MMR_CFG0_CFG_REV_PROXY,Major configuration release" hexmask.long.word 0x4 0.--15. 1. "MMR_CFG0_SPEC_REV_PROXY,Minor spec-only revision. Doesn't change RTL release" line.long 0x8 "CFG0_MMR_CFG1_PROXY" bitfld.long 0x8 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing enabled" "0,1" hexmask.long.byte 0x8 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions" group.long 0x3008++0x1B line.long 0x0 "CFG0_LOCK0_KICK0_PROXY" hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK0_KICK1_PROXY" hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1_PROXY,- KICK1 component" line.long 0x8 "CFG0_intr_raw_status_PROXY" bitfld.long 0x8 3. "PROXY_ERR_PROXY,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x8 2. "KICK_ERR_PROXY,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR_PROXY,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_PROXY,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "CFG0_intr_enabled_status_clear_PROXY" bitfld.long 0xC 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0xC 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "ENABLED_PROT_ERR_PROXY,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "CFG0_intr_enable_PROXY" bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "CFG0_intr_enable_clear_PROXY" bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "CFG0_eoi_PROXY" hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x3024++0xB line.long 0x0 "CFG0_fault_address_PROXY" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR_PROXY,Fault Address." line.long 0x4 "CFG0_fault_type_status_PROXY" bitfld.long 0x4 6. "FAULT_NS_PROXY,Non-secure access." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE_PROXY,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv =.." line.long 0x8 "CFG0_fault_attr_status_PROXY" hexmask.long.word 0x8 20.--31. 1. "FAULT_XID_PROXY,XID." hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID." wgroup.long 0x3030++0x3 line.long 0x0 "CFG0_fault_clear_PROXY" bitfld.long 0x0 0. "FAULT_CLR_PROXY,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" group.long 0x3100++0x3 line.long 0x0 "CFG0_CLAIMREG_P0_R0" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0,Claim bits for Partition 0" group.long 0x4000++0x87 line.long 0x0 "CFG0_PADCONFIG0" bitfld.long 0x0 31. "PADCONFIG0_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x0 30. "PADCONFIG0_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x0 29. "PADCONFIG0_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x0 28. "PADCONFIG0_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x0 27. "PADCONFIG0_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x0 26. "PADCONFIG0_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x0 25. "PADCONFIG0_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x0 24. "PADCONFIG0_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x0 23. "PADCONFIG0_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x0 22. "PADCONFIG0_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x0 21. "PADCONFIG0_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x0 19.--20. "PADCONFIG0_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "PADCONFIG0_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x0 17. "PADCONFIG0_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x0 16. "PADCONFIG0_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x0 15. "PADCONFIG0_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x0 14. "PADCONFIG0_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x0 11.--13. "PADCONFIG0_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "PADCONFIG0_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x0 7. "PADCONFIG0_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG0_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x4 "CFG0_PADCONFIG1" bitfld.long 0x4 31. "PADCONFIG1_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x4 30. "PADCONFIG1_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x4 29. "PADCONFIG1_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x4 28. "PADCONFIG1_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x4 27. "PADCONFIG1_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x4 26. "PADCONFIG1_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x4 25. "PADCONFIG1_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x4 24. "PADCONFIG1_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x4 23. "PADCONFIG1_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x4 22. "PADCONFIG1_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x4 21. "PADCONFIG1_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x4 19.--20. "PADCONFIG1_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "PADCONFIG1_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x4 17. "PADCONFIG1_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x4 16. "PADCONFIG1_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x4 15. "PADCONFIG1_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x4 14. "PADCONFIG1_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x4 11.--13. "PADCONFIG1_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "PADCONFIG1_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x4 7. "PADCONFIG1_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG1_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x8 "CFG0_PADCONFIG2" bitfld.long 0x8 31. "PADCONFIG2_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x8 30. "PADCONFIG2_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x8 29. "PADCONFIG2_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x8 28. "PADCONFIG2_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x8 27. "PADCONFIG2_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x8 26. "PADCONFIG2_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x8 25. "PADCONFIG2_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x8 24. "PADCONFIG2_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x8 23. "PADCONFIG2_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x8 22. "PADCONFIG2_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x8 21. "PADCONFIG2_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x8 19.--20. "PADCONFIG2_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "PADCONFIG2_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x8 17. "PADCONFIG2_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x8 16. "PADCONFIG2_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x8 15. "PADCONFIG2_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x8 14. "PADCONFIG2_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x8 11.--13. "PADCONFIG2_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "PADCONFIG2_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x8 7. "PADCONFIG2_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG2_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0xC "CFG0_PADCONFIG3" bitfld.long 0xC 31. "PADCONFIG3_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xC 30. "PADCONFIG3_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xC 29. "PADCONFIG3_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xC 28. "PADCONFIG3_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xC 27. "PADCONFIG3_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xC 26. "PADCONFIG3_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xC 25. "PADCONFIG3_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xC 24. "PADCONFIG3_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xC 23. "PADCONFIG3_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xC 22. "PADCONFIG3_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xC 21. "PADCONFIG3_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xC 19.--20. "PADCONFIG3_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "PADCONFIG3_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xC 17. "PADCONFIG3_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xC 16. "PADCONFIG3_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xC 15. "PADCONFIG3_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xC 14. "PADCONFIG3_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xC 11.--13. "PADCONFIG3_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "PADCONFIG3_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xC 7. "PADCONFIG3_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG3_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x10 "CFG0_PADCONFIG4" bitfld.long 0x10 31. "PADCONFIG4_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x10 30. "PADCONFIG4_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x10 29. "PADCONFIG4_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x10 28. "PADCONFIG4_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x10 27. "PADCONFIG4_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x10 26. "PADCONFIG4_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x10 25. "PADCONFIG4_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x10 24. "PADCONFIG4_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x10 23. "PADCONFIG4_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x10 22. "PADCONFIG4_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x10 21. "PADCONFIG4_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x10 15. "PADCONFIG4_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x10 14. "PADCONFIG4_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "PADCONFIG4_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x10 7. "PADCONFIG4_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG4_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x14 "CFG0_PADCONFIG5" bitfld.long 0x14 31. "PADCONFIG5_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x14 30. "PADCONFIG5_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x14 29. "PADCONFIG5_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x14 28. "PADCONFIG5_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x14 27. "PADCONFIG5_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x14 26. "PADCONFIG5_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x14 25. "PADCONFIG5_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x14 24. "PADCONFIG5_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x14 23. "PADCONFIG5_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x14 22. "PADCONFIG5_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x14 21. "PADCONFIG5_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x14 15. "PADCONFIG5_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x14 14. "PADCONFIG5_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "PADCONFIG5_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x14 7. "PADCONFIG5_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG5_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x18 "CFG0_PADCONFIG6" bitfld.long 0x18 31. "PADCONFIG6_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x18 30. "PADCONFIG6_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x18 29. "PADCONFIG6_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x18 28. "PADCONFIG6_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x18 27. "PADCONFIG6_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x18 26. "PADCONFIG6_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x18 25. "PADCONFIG6_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x18 24. "PADCONFIG6_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x18 23. "PADCONFIG6_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x18 22. "PADCONFIG6_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x18 21. "PADCONFIG6_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x18 15. "PADCONFIG6_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x18 14. "PADCONFIG6_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "PADCONFIG6_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x18 7. "PADCONFIG6_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG6_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x1C "CFG0_PADCONFIG7" bitfld.long 0x1C 31. "PADCONFIG7_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1C 30. "PADCONFIG7_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1C 29. "PADCONFIG7_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1C 28. "PADCONFIG7_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1C 27. "PADCONFIG7_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1C 26. "PADCONFIG7_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1C 25. "PADCONFIG7_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1C 24. "PADCONFIG7_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1C 23. "PADCONFIG7_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1C 22. "PADCONFIG7_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1C 15. "PADCONFIG7_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1C 14. "PADCONFIG7_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "PADCONFIG7_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1C 7. "PADCONFIG7_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG7_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x20 "CFG0_PADCONFIG8" bitfld.long 0x20 31. "PADCONFIG8_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x20 30. "PADCONFIG8_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x20 29. "PADCONFIG8_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x20 28. "PADCONFIG8_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x20 27. "PADCONFIG8_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x20 26. "PADCONFIG8_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x20 25. "PADCONFIG8_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x20 24. "PADCONFIG8_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x20 23. "PADCONFIG8_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x20 22. "PADCONFIG8_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x20 21. "PADCONFIG8_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x20 15. "PADCONFIG8_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x20 14. "PADCONFIG8_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 8. "PADCONFIG8_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x20 7. "PADCONFIG8_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG8_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x24 "CFG0_PADCONFIG9" bitfld.long 0x24 31. "PADCONFIG9_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x24 30. "PADCONFIG9_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x24 29. "PADCONFIG9_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x24 28. "PADCONFIG9_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x24 27. "PADCONFIG9_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x24 26. "PADCONFIG9_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x24 25. "PADCONFIG9_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x24 24. "PADCONFIG9_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x24 23. "PADCONFIG9_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x24 22. "PADCONFIG9_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x24 21. "PADCONFIG9_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x24 15. "PADCONFIG9_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x24 14. "PADCONFIG9_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "PADCONFIG9_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x24 7. "PADCONFIG9_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG9_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x28 "CFG0_PADCONFIG10" bitfld.long 0x28 31. "PADCONFIG10_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x28 30. "PADCONFIG10_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x28 29. "PADCONFIG10_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x28 28. "PADCONFIG10_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x28 27. "PADCONFIG10_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x28 26. "PADCONFIG10_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x28 25. "PADCONFIG10_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x28 24. "PADCONFIG10_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x28 23. "PADCONFIG10_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x28 22. "PADCONFIG10_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x28 21. "PADCONFIG10_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x28 15. "PADCONFIG10_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x28 14. "PADCONFIG10_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8. "PADCONFIG10_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x28 7. "PADCONFIG10_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG10_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x2C "CFG0_PADCONFIG11" bitfld.long 0x2C 31. "PADCONFIG11_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x2C 30. "PADCONFIG11_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x2C 29. "PADCONFIG11_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x2C 28. "PADCONFIG11_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x2C 27. "PADCONFIG11_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x2C 26. "PADCONFIG11_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x2C 25. "PADCONFIG11_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x2C 24. "PADCONFIG11_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x2C 23. "PADCONFIG11_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x2C 22. "PADCONFIG11_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x2C 15. "PADCONFIG11_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x2C 14. "PADCONFIG11_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 8. "PADCONFIG11_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x2C 7. "PADCONFIG11_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x2C 0.--3. 1. "PADCONFIG11_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x30 "CFG0_PADCONFIG12" bitfld.long 0x30 31. "PADCONFIG12_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x30 30. "PADCONFIG12_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x30 29. "PADCONFIG12_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x30 28. "PADCONFIG12_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x30 27. "PADCONFIG12_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x30 26. "PADCONFIG12_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x30 25. "PADCONFIG12_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x30 24. "PADCONFIG12_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x30 23. "PADCONFIG12_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x30 22. "PADCONFIG12_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x30 21. "PADCONFIG12_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x30 15. "PADCONFIG12_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x30 14. "PADCONFIG12_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 8. "PADCONFIG12_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x30 7. "PADCONFIG12_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PADCONFIG12_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x34 "CFG0_PADCONFIG13" bitfld.long 0x34 31. "PADCONFIG13_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x34 30. "PADCONFIG13_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x34 29. "PADCONFIG13_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x34 28. "PADCONFIG13_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x34 27. "PADCONFIG13_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x34 26. "PADCONFIG13_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x34 25. "PADCONFIG13_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x34 24. "PADCONFIG13_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x34 23. "PADCONFIG13_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x34 22. "PADCONFIG13_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x34 21. "PADCONFIG13_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x34 15. "PADCONFIG13_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x34 14. "PADCONFIG13_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 8. "PADCONFIG13_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x34 7. "PADCONFIG13_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x34 0.--3. 1. "PADCONFIG13_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x38 "CFG0_PADCONFIG14" bitfld.long 0x38 31. "PADCONFIG14_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x38 30. "PADCONFIG14_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x38 29. "PADCONFIG14_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x38 28. "PADCONFIG14_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x38 27. "PADCONFIG14_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x38 26. "PADCONFIG14_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x38 25. "PADCONFIG14_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x38 24. "PADCONFIG14_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x38 23. "PADCONFIG14_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x38 22. "PADCONFIG14_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x38 21. "PADCONFIG14_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x38 15. "PADCONFIG14_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x38 14. "PADCONFIG14_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 8. "PADCONFIG14_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x38 7. "PADCONFIG14_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x38 0.--3. 1. "PADCONFIG14_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x3C "CFG0_PADCONFIG15" bitfld.long 0x3C 31. "PADCONFIG15_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x3C 30. "PADCONFIG15_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x3C 29. "PADCONFIG15_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x3C 28. "PADCONFIG15_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x3C 27. "PADCONFIG15_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x3C 26. "PADCONFIG15_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x3C 25. "PADCONFIG15_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x3C 24. "PADCONFIG15_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x3C 23. "PADCONFIG15_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x3C 22. "PADCONFIG15_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x3C 15. "PADCONFIG15_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x3C 14. "PADCONFIG15_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x3C 8. "PADCONFIG15_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x3C 7. "PADCONFIG15_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x3C 0.--3. 1. "PADCONFIG15_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x40 "CFG0_PADCONFIG16" bitfld.long 0x40 31. "PADCONFIG16_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x40 30. "PADCONFIG16_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x40 29. "PADCONFIG16_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x40 28. "PADCONFIG16_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x40 27. "PADCONFIG16_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x40 26. "PADCONFIG16_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x40 25. "PADCONFIG16_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x40 24. "PADCONFIG16_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x40 23. "PADCONFIG16_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x40 22. "PADCONFIG16_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x40 21. "PADCONFIG16_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x40 15. "PADCONFIG16_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x40 14. "PADCONFIG16_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 8. "PADCONFIG16_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x40 7. "PADCONFIG16_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "PADCONFIG16_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x44 "CFG0_PADCONFIG17" bitfld.long 0x44 31. "PADCONFIG17_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x44 30. "PADCONFIG17_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x44 29. "PADCONFIG17_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x44 28. "PADCONFIG17_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x44 27. "PADCONFIG17_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x44 26. "PADCONFIG17_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x44 25. "PADCONFIG17_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x44 24. "PADCONFIG17_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x44 23. "PADCONFIG17_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x44 22. "PADCONFIG17_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x44 21. "PADCONFIG17_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x44 15. "PADCONFIG17_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x44 14. "PADCONFIG17_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x44 8. "PADCONFIG17_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x44 7. "PADCONFIG17_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x44 0.--3. 1. "PADCONFIG17_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x48 "CFG0_PADCONFIG18" bitfld.long 0x48 31. "PADCONFIG18_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x48 30. "PADCONFIG18_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x48 29. "PADCONFIG18_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x48 28. "PADCONFIG18_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x48 27. "PADCONFIG18_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x48 26. "PADCONFIG18_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x48 25. "PADCONFIG18_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x48 24. "PADCONFIG18_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x48 23. "PADCONFIG18_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x48 22. "PADCONFIG18_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x48 21. "PADCONFIG18_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x48 15. "PADCONFIG18_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x48 14. "PADCONFIG18_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 8. "PADCONFIG18_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x48 7. "PADCONFIG18_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x48 0.--3. 1. "PADCONFIG18_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x4C "CFG0_PADCONFIG19" bitfld.long 0x4C 31. "PADCONFIG19_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x4C 30. "PADCONFIG19_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x4C 29. "PADCONFIG19_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x4C 28. "PADCONFIG19_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x4C 27. "PADCONFIG19_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x4C 26. "PADCONFIG19_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x4C 25. "PADCONFIG19_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x4C 24. "PADCONFIG19_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x4C 23. "PADCONFIG19_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x4C 22. "PADCONFIG19_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x4C 15. "PADCONFIG19_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x4C 14. "PADCONFIG19_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4C 8. "PADCONFIG19_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x4C 7. "PADCONFIG19_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x4C 0.--3. 1. "PADCONFIG19_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x50 "CFG0_PADCONFIG20" bitfld.long 0x50 31. "PADCONFIG20_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x50 30. "PADCONFIG20_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x50 29. "PADCONFIG20_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x50 28. "PADCONFIG20_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x50 27. "PADCONFIG20_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x50 26. "PADCONFIG20_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x50 25. "PADCONFIG20_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x50 24. "PADCONFIG20_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x50 23. "PADCONFIG20_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x50 22. "PADCONFIG20_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x50 21. "PADCONFIG20_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x50 15. "PADCONFIG20_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x50 14. "PADCONFIG20_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 8. "PADCONFIG20_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x50 7. "PADCONFIG20_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x50 0.--3. 1. "PADCONFIG20_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x54 "CFG0_PADCONFIG21" bitfld.long 0x54 31. "PADCONFIG21_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x54 30. "PADCONFIG21_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x54 29. "PADCONFIG21_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x54 28. "PADCONFIG21_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x54 27. "PADCONFIG21_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x54 26. "PADCONFIG21_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x54 25. "PADCONFIG21_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x54 24. "PADCONFIG21_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x54 23. "PADCONFIG21_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x54 22. "PADCONFIG21_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x54 21. "PADCONFIG21_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x54 15. "PADCONFIG21_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x54 14. "PADCONFIG21_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x54 8. "PADCONFIG21_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x54 7. "PADCONFIG21_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x54 0.--3. 1. "PADCONFIG21_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x58 "CFG0_PADCONFIG22" bitfld.long 0x58 31. "PADCONFIG22_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x58 30. "PADCONFIG22_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x58 29. "PADCONFIG22_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x58 28. "PADCONFIG22_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x58 27. "PADCONFIG22_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x58 26. "PADCONFIG22_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x58 25. "PADCONFIG22_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x58 24. "PADCONFIG22_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x58 23. "PADCONFIG22_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x58 22. "PADCONFIG22_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x58 21. "PADCONFIG22_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x58 15. "PADCONFIG22_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x58 14. "PADCONFIG22_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 8. "PADCONFIG22_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x58 7. "PADCONFIG22_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x58 0.--3. 1. "PADCONFIG22_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x5C "CFG0_PADCONFIG23" bitfld.long 0x5C 31. "PADCONFIG23_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x5C 30. "PADCONFIG23_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x5C 29. "PADCONFIG23_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x5C 28. "PADCONFIG23_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x5C 27. "PADCONFIG23_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x5C 26. "PADCONFIG23_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x5C 25. "PADCONFIG23_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x5C 24. "PADCONFIG23_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x5C 23. "PADCONFIG23_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x5C 22. "PADCONFIG23_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x5C 15. "PADCONFIG23_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x5C 14. "PADCONFIG23_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x5C 8. "PADCONFIG23_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x5C 7. "PADCONFIG23_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x5C 0.--3. 1. "PADCONFIG23_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x60 "CFG0_PADCONFIG24" bitfld.long 0x60 31. "PADCONFIG24_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x60 30. "PADCONFIG24_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x60 29. "PADCONFIG24_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x60 28. "PADCONFIG24_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x60 27. "PADCONFIG24_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x60 26. "PADCONFIG24_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x60 25. "PADCONFIG24_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x60 24. "PADCONFIG24_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x60 23. "PADCONFIG24_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x60 22. "PADCONFIG24_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x60 21. "PADCONFIG24_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x60 15. "PADCONFIG24_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x60 14. "PADCONFIG24_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 8. "PADCONFIG24_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x60 7. "PADCONFIG24_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "PADCONFIG24_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x64 "CFG0_PADCONFIG25" bitfld.long 0x64 31. "PADCONFIG25_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x64 30. "PADCONFIG25_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x64 29. "PADCONFIG25_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x64 28. "PADCONFIG25_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x64 27. "PADCONFIG25_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x64 26. "PADCONFIG25_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x64 25. "PADCONFIG25_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x64 24. "PADCONFIG25_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x64 23. "PADCONFIG25_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x64 22. "PADCONFIG25_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x64 21. "PADCONFIG25_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x64 15. "PADCONFIG25_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x64 14. "PADCONFIG25_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x64 8. "PADCONFIG25_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x64 7. "PADCONFIG25_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x64 0.--3. 1. "PADCONFIG25_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x68 "CFG0_PADCONFIG26" bitfld.long 0x68 31. "PADCONFIG26_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x68 30. "PADCONFIG26_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x68 29. "PADCONFIG26_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x68 28. "PADCONFIG26_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x68 27. "PADCONFIG26_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x68 26. "PADCONFIG26_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x68 25. "PADCONFIG26_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x68 24. "PADCONFIG26_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x68 23. "PADCONFIG26_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x68 22. "PADCONFIG26_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x68 21. "PADCONFIG26_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x68 15. "PADCONFIG26_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x68 14. "PADCONFIG26_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 8. "PADCONFIG26_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x68 7. "PADCONFIG26_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x68 0.--3. 1. "PADCONFIG26_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x6C "CFG0_PADCONFIG27" bitfld.long 0x6C 31. "PADCONFIG27_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x6C 30. "PADCONFIG27_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x6C 29. "PADCONFIG27_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x6C 28. "PADCONFIG27_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x6C 27. "PADCONFIG27_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x6C 26. "PADCONFIG27_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x6C 25. "PADCONFIG27_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x6C 24. "PADCONFIG27_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x6C 23. "PADCONFIG27_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x6C 22. "PADCONFIG27_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x6C 15. "PADCONFIG27_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x6C 14. "PADCONFIG27_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x6C 8. "PADCONFIG27_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x6C 7. "PADCONFIG27_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x6C 0.--3. 1. "PADCONFIG27_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x70 "CFG0_PADCONFIG28" bitfld.long 0x70 31. "PADCONFIG28_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x70 30. "PADCONFIG28_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x70 29. "PADCONFIG28_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x70 28. "PADCONFIG28_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x70 27. "PADCONFIG28_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x70 26. "PADCONFIG28_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x70 25. "PADCONFIG28_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x70 24. "PADCONFIG28_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x70 23. "PADCONFIG28_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x70 22. "PADCONFIG28_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x70 21. "PADCONFIG28_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x70 15. "PADCONFIG28_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x70 14. "PADCONFIG28_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 8. "PADCONFIG28_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x70 7. "PADCONFIG28_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x70 0.--3. 1. "PADCONFIG28_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x74 "CFG0_PADCONFIG29" bitfld.long 0x74 31. "PADCONFIG29_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x74 30. "PADCONFIG29_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x74 29. "PADCONFIG29_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x74 28. "PADCONFIG29_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x74 27. "PADCONFIG29_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x74 26. "PADCONFIG29_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x74 25. "PADCONFIG29_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x74 24. "PADCONFIG29_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x74 23. "PADCONFIG29_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x74 22. "PADCONFIG29_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x74 21. "PADCONFIG29_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x74 15. "PADCONFIG29_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x74 14. "PADCONFIG29_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x74 8. "PADCONFIG29_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x74 7. "PADCONFIG29_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x74 0.--3. 1. "PADCONFIG29_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x78 "CFG0_PADCONFIG30" bitfld.long 0x78 31. "PADCONFIG30_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x78 30. "PADCONFIG30_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x78 29. "PADCONFIG30_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x78 28. "PADCONFIG30_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x78 27. "PADCONFIG30_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x78 26. "PADCONFIG30_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x78 25. "PADCONFIG30_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x78 24. "PADCONFIG30_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x78 23. "PADCONFIG30_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x78 22. "PADCONFIG30_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x78 21. "PADCONFIG30_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x78 15. "PADCONFIG30_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x78 14. "PADCONFIG30_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 8. "PADCONFIG30_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x78 7. "PADCONFIG30_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x78 0.--3. 1. "PADCONFIG30_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x7C "CFG0_PADCONFIG31" bitfld.long 0x7C 31. "PADCONFIG31_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x7C 30. "PADCONFIG31_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x7C 29. "PADCONFIG31_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x7C 28. "PADCONFIG31_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x7C 27. "PADCONFIG31_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x7C 26. "PADCONFIG31_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x7C 25. "PADCONFIG31_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x7C 24. "PADCONFIG31_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x7C 23. "PADCONFIG31_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x7C 22. "PADCONFIG31_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x7C 15. "PADCONFIG31_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x7C 14. "PADCONFIG31_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x7C 8. "PADCONFIG31_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x7C 7. "PADCONFIG31_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x7C 0.--3. 1. "PADCONFIG31_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x80 "CFG0_PADCONFIG32" bitfld.long 0x80 31. "PADCONFIG32_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x80 30. "PADCONFIG32_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x80 29. "PADCONFIG32_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x80 28. "PADCONFIG32_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x80 27. "PADCONFIG32_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x80 26. "PADCONFIG32_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x80 25. "PADCONFIG32_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x80 24. "PADCONFIG32_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x80 23. "PADCONFIG32_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x80 22. "PADCONFIG32_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x80 21. "PADCONFIG32_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x80 15. "PADCONFIG32_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x80 14. "PADCONFIG32_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 8. "PADCONFIG32_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x80 7. "PADCONFIG32_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "PADCONFIG32_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." line.long 0x84 "CFG0_PADCONFIG33" bitfld.long 0x84 31. "PADCONFIG33_LOCK,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x84 30. "PADCONFIG33_WKUP_EVT,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x84 29. "PADCONFIG33_WKUP_EN,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x84 28. "PADCONFIG33_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x84 27. "PADCONFIG33_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x84 26. "PADCONFIG33_DSOUT_VAL,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x84 25. "PADCONFIG33_DSOUT_DIS,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x84 24. "PADCONFIG33_DS_EN,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x84 23. "PADCONFIG33_ISO_BYP,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x84 22. "PADCONFIG33_ISO_OVR,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x84 21. "PADCONFIG33_TX_DIS,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x84 19.--20. "PADCONFIG33_DRV_STR,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x84 18. "PADCONFIG33_RXACTIVE,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x84 17. "PADCONFIG33_PULLTYPESEL,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x84 16. "PADCONFIG33_PULLUDEN,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x84 15. "PADCONFIG33_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x84 14. "PADCONFIG33_ST_EN,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x84 11.--13. "PADCONFIG33_DEBOUNCE_SEL,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x84 8. "PADCONFIG33_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x84 7. "PADCONFIG33_WK_LVL_EN,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained." "0,1" newline hexmask.long.byte 0x84 0.--3. 1. "PADCONFIG33_MUXMODE,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 - Mux.." group.long 0x5008++0x7 line.long 0x0 "CFG0_LOCK1_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK1_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1,- KICK1 component" rgroup.long 0x5100++0x7 line.long 0x0 "CFG0_CLAIMREG_P1_R0_READONLY" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0_READONLY,Claim bits for Partition 1" line.long 0x4 "CFG0_CLAIMREG_P1_R1_READONLY" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1_READONLY,Claim bits for Partition 1" group.long 0x6000++0x87 line.long 0x0 "CFG0_PADCONFIG0_PROXY" bitfld.long 0x0 31. "PADCONFIG0_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x0 30. "PADCONFIG0_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x0 29. "PADCONFIG0_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x0 28. "PADCONFIG0_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x0 27. "PADCONFIG0_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x0 26. "PADCONFIG0_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x0 25. "PADCONFIG0_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x0 24. "PADCONFIG0_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x0 23. "PADCONFIG0_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x0 22. "PADCONFIG0_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x0 21. "PADCONFIG0_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x0 19.--20. "PADCONFIG0_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x0 18. "PADCONFIG0_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x0 17. "PADCONFIG0_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x0 16. "PADCONFIG0_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x0 15. "PADCONFIG0_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x0 14. "PADCONFIG0_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x0 11.--13. "PADCONFIG0_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "PADCONFIG0_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x0 7. "PADCONFIG0_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PADCONFIG0_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x4 "CFG0_PADCONFIG1_PROXY" bitfld.long 0x4 31. "PADCONFIG1_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x4 30. "PADCONFIG1_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x4 29. "PADCONFIG1_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x4 28. "PADCONFIG1_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x4 27. "PADCONFIG1_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x4 26. "PADCONFIG1_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x4 25. "PADCONFIG1_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x4 24. "PADCONFIG1_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x4 23. "PADCONFIG1_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x4 22. "PADCONFIG1_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x4 21. "PADCONFIG1_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x4 19.--20. "PADCONFIG1_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4 18. "PADCONFIG1_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x4 17. "PADCONFIG1_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x4 16. "PADCONFIG1_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x4 15. "PADCONFIG1_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x4 14. "PADCONFIG1_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x4 11.--13. "PADCONFIG1_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "PADCONFIG1_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x4 7. "PADCONFIG1_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "PADCONFIG1_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x8 "CFG0_PADCONFIG2_PROXY" bitfld.long 0x8 31. "PADCONFIG2_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x8 30. "PADCONFIG2_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x8 29. "PADCONFIG2_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x8 28. "PADCONFIG2_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x8 27. "PADCONFIG2_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x8 26. "PADCONFIG2_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x8 25. "PADCONFIG2_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x8 24. "PADCONFIG2_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x8 23. "PADCONFIG2_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x8 22. "PADCONFIG2_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x8 21. "PADCONFIG2_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x8 19.--20. "PADCONFIG2_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x8 18. "PADCONFIG2_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x8 17. "PADCONFIG2_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x8 16. "PADCONFIG2_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x8 15. "PADCONFIG2_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x8 14. "PADCONFIG2_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x8 11.--13. "PADCONFIG2_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "PADCONFIG2_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x8 7. "PADCONFIG2_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PADCONFIG2_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0xC "CFG0_PADCONFIG3_PROXY" bitfld.long 0xC 31. "PADCONFIG3_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0xC 30. "PADCONFIG3_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0xC 29. "PADCONFIG3_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0xC 28. "PADCONFIG3_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0xC 27. "PADCONFIG3_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0xC 26. "PADCONFIG3_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0xC 25. "PADCONFIG3_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0xC 24. "PADCONFIG3_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0xC 23. "PADCONFIG3_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0xC 22. "PADCONFIG3_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0xC 21. "PADCONFIG3_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0xC 19.--20. "PADCONFIG3_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0xC 18. "PADCONFIG3_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0xC 17. "PADCONFIG3_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0xC 16. "PADCONFIG3_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0xC 15. "PADCONFIG3_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0xC 14. "PADCONFIG3_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0xC 11.--13. "PADCONFIG3_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "PADCONFIG3_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0xC 7. "PADCONFIG3_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "PADCONFIG3_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x10 "CFG0_PADCONFIG4_PROXY" bitfld.long 0x10 31. "PADCONFIG4_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x10 30. "PADCONFIG4_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x10 29. "PADCONFIG4_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x10 28. "PADCONFIG4_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x10 27. "PADCONFIG4_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x10 26. "PADCONFIG4_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x10 25. "PADCONFIG4_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x10 24. "PADCONFIG4_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x10 23. "PADCONFIG4_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x10 22. "PADCONFIG4_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x10 21. "PADCONFIG4_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x10 15. "PADCONFIG4_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x10 14. "PADCONFIG4_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "PADCONFIG4_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x10 7. "PADCONFIG4_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "PADCONFIG4_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x14 "CFG0_PADCONFIG5_PROXY" bitfld.long 0x14 31. "PADCONFIG5_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x14 30. "PADCONFIG5_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x14 29. "PADCONFIG5_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x14 28. "PADCONFIG5_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x14 27. "PADCONFIG5_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x14 26. "PADCONFIG5_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x14 25. "PADCONFIG5_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x14 24. "PADCONFIG5_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x14 23. "PADCONFIG5_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x14 22. "PADCONFIG5_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x14 21. "PADCONFIG5_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x14 15. "PADCONFIG5_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x14 14. "PADCONFIG5_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "PADCONFIG5_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x14 7. "PADCONFIG5_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "PADCONFIG5_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x18 "CFG0_PADCONFIG6_PROXY" bitfld.long 0x18 31. "PADCONFIG6_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x18 30. "PADCONFIG6_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x18 29. "PADCONFIG6_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x18 28. "PADCONFIG6_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x18 27. "PADCONFIG6_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x18 26. "PADCONFIG6_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x18 25. "PADCONFIG6_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x18 24. "PADCONFIG6_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x18 23. "PADCONFIG6_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x18 22. "PADCONFIG6_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x18 21. "PADCONFIG6_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x18 15. "PADCONFIG6_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x18 14. "PADCONFIG6_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8. "PADCONFIG6_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x18 7. "PADCONFIG6_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x18 0.--3. 1. "PADCONFIG6_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x1C "CFG0_PADCONFIG7_PROXY" bitfld.long 0x1C 31. "PADCONFIG7_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x1C 30. "PADCONFIG7_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x1C 29. "PADCONFIG7_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x1C 28. "PADCONFIG7_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x1C 27. "PADCONFIG7_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x1C 26. "PADCONFIG7_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x1C 25. "PADCONFIG7_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x1C 24. "PADCONFIG7_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x1C 23. "PADCONFIG7_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x1C 22. "PADCONFIG7_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x1C 15. "PADCONFIG7_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x1C 14. "PADCONFIG7_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "PADCONFIG7_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x1C 7. "PADCONFIG7_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x1C 0.--3. 1. "PADCONFIG7_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x20 "CFG0_PADCONFIG8_PROXY" bitfld.long 0x20 31. "PADCONFIG8_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x20 30. "PADCONFIG8_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x20 29. "PADCONFIG8_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x20 28. "PADCONFIG8_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x20 27. "PADCONFIG8_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x20 26. "PADCONFIG8_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x20 25. "PADCONFIG8_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x20 24. "PADCONFIG8_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x20 23. "PADCONFIG8_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x20 22. "PADCONFIG8_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x20 21. "PADCONFIG8_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x20 15. "PADCONFIG8_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x20 14. "PADCONFIG8_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 8. "PADCONFIG8_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x20 7. "PADCONFIG8_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "PADCONFIG8_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x24 "CFG0_PADCONFIG9_PROXY" bitfld.long 0x24 31. "PADCONFIG9_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x24 30. "PADCONFIG9_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x24 29. "PADCONFIG9_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x24 28. "PADCONFIG9_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x24 27. "PADCONFIG9_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x24 26. "PADCONFIG9_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x24 25. "PADCONFIG9_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x24 24. "PADCONFIG9_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x24 23. "PADCONFIG9_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x24 22. "PADCONFIG9_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x24 21. "PADCONFIG9_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x24 15. "PADCONFIG9_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x24 14. "PADCONFIG9_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8. "PADCONFIG9_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x24 7. "PADCONFIG9_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x24 0.--3. 1. "PADCONFIG9_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x28 "CFG0_PADCONFIG10_PROXY" bitfld.long 0x28 31. "PADCONFIG10_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x28 30. "PADCONFIG10_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x28 29. "PADCONFIG10_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x28 28. "PADCONFIG10_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x28 27. "PADCONFIG10_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x28 26. "PADCONFIG10_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x28 25. "PADCONFIG10_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x28 24. "PADCONFIG10_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x28 23. "PADCONFIG10_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x28 22. "PADCONFIG10_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x28 21. "PADCONFIG10_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x28 15. "PADCONFIG10_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x28 14. "PADCONFIG10_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 8. "PADCONFIG10_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x28 7. "PADCONFIG10_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PADCONFIG10_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x2C "CFG0_PADCONFIG11_PROXY" bitfld.long 0x2C 31. "PADCONFIG11_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x2C 30. "PADCONFIG11_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x2C 29. "PADCONFIG11_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x2C 28. "PADCONFIG11_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x2C 27. "PADCONFIG11_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x2C 26. "PADCONFIG11_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x2C 25. "PADCONFIG11_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x2C 24. "PADCONFIG11_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x2C 23. "PADCONFIG11_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x2C 22. "PADCONFIG11_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x2C 15. "PADCONFIG11_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x2C 14. "PADCONFIG11_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 8. "PADCONFIG11_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x2C 7. "PADCONFIG11_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x2C 0.--3. 1. "PADCONFIG11_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x30 "CFG0_PADCONFIG12_PROXY" bitfld.long 0x30 31. "PADCONFIG12_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x30 30. "PADCONFIG12_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x30 29. "PADCONFIG12_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x30 28. "PADCONFIG12_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x30 27. "PADCONFIG12_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x30 26. "PADCONFIG12_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x30 25. "PADCONFIG12_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x30 24. "PADCONFIG12_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x30 23. "PADCONFIG12_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x30 22. "PADCONFIG12_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x30 21. "PADCONFIG12_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x30 15. "PADCONFIG12_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x30 14. "PADCONFIG12_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 8. "PADCONFIG12_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x30 7. "PADCONFIG12_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PADCONFIG12_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x34 "CFG0_PADCONFIG13_PROXY" bitfld.long 0x34 31. "PADCONFIG13_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x34 30. "PADCONFIG13_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x34 29. "PADCONFIG13_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x34 28. "PADCONFIG13_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x34 27. "PADCONFIG13_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x34 26. "PADCONFIG13_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x34 25. "PADCONFIG13_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x34 24. "PADCONFIG13_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x34 23. "PADCONFIG13_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x34 22. "PADCONFIG13_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x34 21. "PADCONFIG13_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x34 15. "PADCONFIG13_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x34 14. "PADCONFIG13_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 8. "PADCONFIG13_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x34 7. "PADCONFIG13_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x34 0.--3. 1. "PADCONFIG13_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x38 "CFG0_PADCONFIG14_PROXY" bitfld.long 0x38 31. "PADCONFIG14_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x38 30. "PADCONFIG14_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x38 29. "PADCONFIG14_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x38 28. "PADCONFIG14_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x38 27. "PADCONFIG14_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x38 26. "PADCONFIG14_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x38 25. "PADCONFIG14_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x38 24. "PADCONFIG14_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x38 23. "PADCONFIG14_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x38 22. "PADCONFIG14_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x38 21. "PADCONFIG14_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x38 15. "PADCONFIG14_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x38 14. "PADCONFIG14_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 8. "PADCONFIG14_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x38 7. "PADCONFIG14_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x38 0.--3. 1. "PADCONFIG14_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x3C "CFG0_PADCONFIG15_PROXY" bitfld.long 0x3C 31. "PADCONFIG15_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x3C 30. "PADCONFIG15_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x3C 29. "PADCONFIG15_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x3C 28. "PADCONFIG15_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x3C 27. "PADCONFIG15_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x3C 26. "PADCONFIG15_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x3C 25. "PADCONFIG15_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x3C 24. "PADCONFIG15_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x3C 23. "PADCONFIG15_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x3C 22. "PADCONFIG15_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x3C 15. "PADCONFIG15_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x3C 14. "PADCONFIG15_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x3C 8. "PADCONFIG15_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x3C 7. "PADCONFIG15_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x3C 0.--3. 1. "PADCONFIG15_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x40 "CFG0_PADCONFIG16_PROXY" bitfld.long 0x40 31. "PADCONFIG16_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x40 30. "PADCONFIG16_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x40 29. "PADCONFIG16_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x40 28. "PADCONFIG16_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x40 27. "PADCONFIG16_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x40 26. "PADCONFIG16_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x40 25. "PADCONFIG16_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x40 24. "PADCONFIG16_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x40 23. "PADCONFIG16_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x40 22. "PADCONFIG16_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x40 21. "PADCONFIG16_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x40 15. "PADCONFIG16_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x40 14. "PADCONFIG16_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 8. "PADCONFIG16_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x40 7. "PADCONFIG16_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "PADCONFIG16_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x44 "CFG0_PADCONFIG17_PROXY" bitfld.long 0x44 31. "PADCONFIG17_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x44 30. "PADCONFIG17_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x44 29. "PADCONFIG17_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x44 28. "PADCONFIG17_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x44 27. "PADCONFIG17_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x44 26. "PADCONFIG17_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x44 25. "PADCONFIG17_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x44 24. "PADCONFIG17_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x44 23. "PADCONFIG17_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x44 22. "PADCONFIG17_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x44 21. "PADCONFIG17_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x44 15. "PADCONFIG17_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x44 14. "PADCONFIG17_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x44 8. "PADCONFIG17_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x44 7. "PADCONFIG17_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x44 0.--3. 1. "PADCONFIG17_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x48 "CFG0_PADCONFIG18_PROXY" bitfld.long 0x48 31. "PADCONFIG18_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x48 30. "PADCONFIG18_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x48 29. "PADCONFIG18_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x48 28. "PADCONFIG18_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x48 27. "PADCONFIG18_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x48 26. "PADCONFIG18_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x48 25. "PADCONFIG18_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x48 24. "PADCONFIG18_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x48 23. "PADCONFIG18_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x48 22. "PADCONFIG18_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x48 21. "PADCONFIG18_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x48 15. "PADCONFIG18_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x48 14. "PADCONFIG18_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x48 8. "PADCONFIG18_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x48 7. "PADCONFIG18_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x48 0.--3. 1. "PADCONFIG18_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x4C "CFG0_PADCONFIG19_PROXY" bitfld.long 0x4C 31. "PADCONFIG19_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x4C 30. "PADCONFIG19_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x4C 29. "PADCONFIG19_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x4C 28. "PADCONFIG19_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x4C 27. "PADCONFIG19_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x4C 26. "PADCONFIG19_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x4C 25. "PADCONFIG19_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x4C 24. "PADCONFIG19_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x4C 23. "PADCONFIG19_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x4C 22. "PADCONFIG19_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x4C 15. "PADCONFIG19_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x4C 14. "PADCONFIG19_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4C 8. "PADCONFIG19_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x4C 7. "PADCONFIG19_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x4C 0.--3. 1. "PADCONFIG19_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x50 "CFG0_PADCONFIG20_PROXY" bitfld.long 0x50 31. "PADCONFIG20_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x50 30. "PADCONFIG20_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x50 29. "PADCONFIG20_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x50 28. "PADCONFIG20_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x50 27. "PADCONFIG20_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x50 26. "PADCONFIG20_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x50 25. "PADCONFIG20_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x50 24. "PADCONFIG20_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x50 23. "PADCONFIG20_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x50 22. "PADCONFIG20_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x50 21. "PADCONFIG20_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x50 15. "PADCONFIG20_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x50 14. "PADCONFIG20_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 8. "PADCONFIG20_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x50 7. "PADCONFIG20_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x50 0.--3. 1. "PADCONFIG20_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x54 "CFG0_PADCONFIG21_PROXY" bitfld.long 0x54 31. "PADCONFIG21_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x54 30. "PADCONFIG21_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x54 29. "PADCONFIG21_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x54 28. "PADCONFIG21_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x54 27. "PADCONFIG21_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x54 26. "PADCONFIG21_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x54 25. "PADCONFIG21_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x54 24. "PADCONFIG21_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x54 23. "PADCONFIG21_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x54 22. "PADCONFIG21_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x54 21. "PADCONFIG21_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x54 15. "PADCONFIG21_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x54 14. "PADCONFIG21_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x54 8. "PADCONFIG21_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x54 7. "PADCONFIG21_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x54 0.--3. 1. "PADCONFIG21_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x58 "CFG0_PADCONFIG22_PROXY" bitfld.long 0x58 31. "PADCONFIG22_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x58 30. "PADCONFIG22_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x58 29. "PADCONFIG22_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x58 28. "PADCONFIG22_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x58 27. "PADCONFIG22_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x58 26. "PADCONFIG22_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x58 25. "PADCONFIG22_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x58 24. "PADCONFIG22_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x58 23. "PADCONFIG22_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x58 22. "PADCONFIG22_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x58 21. "PADCONFIG22_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x58 15. "PADCONFIG22_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x58 14. "PADCONFIG22_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 8. "PADCONFIG22_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x58 7. "PADCONFIG22_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x58 0.--3. 1. "PADCONFIG22_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x5C "CFG0_PADCONFIG23_PROXY" bitfld.long 0x5C 31. "PADCONFIG23_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x5C 30. "PADCONFIG23_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x5C 29. "PADCONFIG23_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x5C 28. "PADCONFIG23_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x5C 27. "PADCONFIG23_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x5C 26. "PADCONFIG23_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x5C 25. "PADCONFIG23_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x5C 24. "PADCONFIG23_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x5C 23. "PADCONFIG23_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x5C 22. "PADCONFIG23_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x5C 15. "PADCONFIG23_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x5C 14. "PADCONFIG23_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x5C 8. "PADCONFIG23_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x5C 7. "PADCONFIG23_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x5C 0.--3. 1. "PADCONFIG23_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x60 "CFG0_PADCONFIG24_PROXY" bitfld.long 0x60 31. "PADCONFIG24_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x60 30. "PADCONFIG24_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x60 29. "PADCONFIG24_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x60 28. "PADCONFIG24_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x60 27. "PADCONFIG24_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x60 26. "PADCONFIG24_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x60 25. "PADCONFIG24_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x60 24. "PADCONFIG24_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x60 23. "PADCONFIG24_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x60 22. "PADCONFIG24_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x60 21. "PADCONFIG24_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x60 15. "PADCONFIG24_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x60 14. "PADCONFIG24_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 8. "PADCONFIG24_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x60 7. "PADCONFIG24_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "PADCONFIG24_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x64 "CFG0_PADCONFIG25_PROXY" bitfld.long 0x64 31. "PADCONFIG25_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x64 30. "PADCONFIG25_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x64 29. "PADCONFIG25_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x64 28. "PADCONFIG25_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x64 27. "PADCONFIG25_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x64 26. "PADCONFIG25_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x64 25. "PADCONFIG25_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x64 24. "PADCONFIG25_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x64 23. "PADCONFIG25_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x64 22. "PADCONFIG25_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x64 21. "PADCONFIG25_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x64 15. "PADCONFIG25_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x64 14. "PADCONFIG25_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x64 8. "PADCONFIG25_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x64 7. "PADCONFIG25_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x64 0.--3. 1. "PADCONFIG25_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x68 "CFG0_PADCONFIG26_PROXY" bitfld.long 0x68 31. "PADCONFIG26_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x68 30. "PADCONFIG26_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x68 29. "PADCONFIG26_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x68 28. "PADCONFIG26_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x68 27. "PADCONFIG26_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x68 26. "PADCONFIG26_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x68 25. "PADCONFIG26_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x68 24. "PADCONFIG26_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x68 23. "PADCONFIG26_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x68 22. "PADCONFIG26_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x68 21. "PADCONFIG26_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x68 15. "PADCONFIG26_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x68 14. "PADCONFIG26_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 8. "PADCONFIG26_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x68 7. "PADCONFIG26_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x68 0.--3. 1. "PADCONFIG26_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x6C "CFG0_PADCONFIG27_PROXY" bitfld.long 0x6C 31. "PADCONFIG27_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x6C 30. "PADCONFIG27_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x6C 29. "PADCONFIG27_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x6C 28. "PADCONFIG27_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x6C 27. "PADCONFIG27_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x6C 26. "PADCONFIG27_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x6C 25. "PADCONFIG27_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x6C 24. "PADCONFIG27_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x6C 23. "PADCONFIG27_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x6C 22. "PADCONFIG27_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x6C 15. "PADCONFIG27_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x6C 14. "PADCONFIG27_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x6C 8. "PADCONFIG27_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x6C 7. "PADCONFIG27_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x6C 0.--3. 1. "PADCONFIG27_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x70 "CFG0_PADCONFIG28_PROXY" bitfld.long 0x70 31. "PADCONFIG28_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x70 30. "PADCONFIG28_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x70 29. "PADCONFIG28_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x70 28. "PADCONFIG28_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x70 27. "PADCONFIG28_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x70 26. "PADCONFIG28_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x70 25. "PADCONFIG28_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x70 24. "PADCONFIG28_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x70 23. "PADCONFIG28_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x70 22. "PADCONFIG28_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x70 21. "PADCONFIG28_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x70 15. "PADCONFIG28_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x70 14. "PADCONFIG28_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 8. "PADCONFIG28_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x70 7. "PADCONFIG28_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x70 0.--3. 1. "PADCONFIG28_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x74 "CFG0_PADCONFIG29_PROXY" bitfld.long 0x74 31. "PADCONFIG29_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x74 30. "PADCONFIG29_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x74 29. "PADCONFIG29_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x74 28. "PADCONFIG29_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x74 27. "PADCONFIG29_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x74 26. "PADCONFIG29_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x74 25. "PADCONFIG29_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x74 24. "PADCONFIG29_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x74 23. "PADCONFIG29_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x74 22. "PADCONFIG29_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x74 21. "PADCONFIG29_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x74 15. "PADCONFIG29_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x74 14. "PADCONFIG29_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x74 8. "PADCONFIG29_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x74 7. "PADCONFIG29_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x74 0.--3. 1. "PADCONFIG29_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x78 "CFG0_PADCONFIG30_PROXY" bitfld.long 0x78 31. "PADCONFIG30_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x78 30. "PADCONFIG30_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x78 29. "PADCONFIG30_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x78 28. "PADCONFIG30_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x78 27. "PADCONFIG30_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x78 26. "PADCONFIG30_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x78 25. "PADCONFIG30_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x78 24. "PADCONFIG30_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x78 23. "PADCONFIG30_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x78 22. "PADCONFIG30_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x78 21. "PADCONFIG30_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x78 15. "PADCONFIG30_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x78 14. "PADCONFIG30_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x78 8. "PADCONFIG30_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x78 7. "PADCONFIG30_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x78 0.--3. 1. "PADCONFIG30_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x7C "CFG0_PADCONFIG31_PROXY" bitfld.long 0x7C 31. "PADCONFIG31_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x7C 30. "PADCONFIG31_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x7C 29. "PADCONFIG31_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x7C 28. "PADCONFIG31_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x7C 27. "PADCONFIG31_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x7C 26. "PADCONFIG31_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x7C 25. "PADCONFIG31_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x7C 24. "PADCONFIG31_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x7C 23. "PADCONFIG31_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x7C 22. "PADCONFIG31_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x7C 15. "PADCONFIG31_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x7C 14. "PADCONFIG31_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x7C 8. "PADCONFIG31_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x7C 7. "PADCONFIG31_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x7C 0.--3. 1. "PADCONFIG31_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x80 "CFG0_PADCONFIG32_PROXY" bitfld.long 0x80 31. "PADCONFIG32_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x80 30. "PADCONFIG32_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x80 29. "PADCONFIG32_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x80 28. "PADCONFIG32_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x80 27. "PADCONFIG32_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x80 26. "PADCONFIG32_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x80 25. "PADCONFIG32_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x80 24. "PADCONFIG32_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x80 23. "PADCONFIG32_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x80 22. "PADCONFIG32_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x80 21. "PADCONFIG32_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x80 15. "PADCONFIG32_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x80 14. "PADCONFIG32_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x80 8. "PADCONFIG32_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x80 7. "PADCONFIG32_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "PADCONFIG32_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." line.long 0x84 "CFG0_PADCONFIG33_PROXY" bitfld.long 0x84 31. "PADCONFIG33_LOCK_PROXY,Lock 0 - Padconfig register is unlocked 1 - Padconfig register is locked from further writes" "0,1" rbitfld.long 0x84 30. "PADCONFIG33_WKUP_EVT_PROXY,Wakeup event status 0 - No wake event on pin 1 - Wake event occurred on pin" "0,1" newline bitfld.long 0x84 29. "PADCONFIG33_WKUP_EN_PROXY,Wakeup enable 0 - Wakeup operation disabled 1 - Wakeup operation enabled" "0,1" bitfld.long 0x84 28. "PADCONFIG33_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection 0 - Offmode pulldown selected 1 - Offmode pullup selected" "0,1" newline bitfld.long 0x84 27. "PADCONFIG33_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low) 0 - Pullup / pulldown is enabled 1 - Pullup / pulldown is disabled" "0,1" bitfld.long 0x84 26. "PADCONFIG33_DSOUT_VAL_PROXY,Deep Sleep output value 0 - Output value is 0 1 - Output value is 1" "0,1" newline bitfld.long 0x84 25. "PADCONFIG33_DSOUT_DIS_PROXY,Deep Sleep output disable 0 - Output enabled 1 - Output disabled" "0,1" bitfld.long 0x84 24. "PADCONFIG33_DS_EN_PROXY,Deep Sleep override control 0 - IO keeps its previous state when Deep Sleep mode is active 1 - IO state is forced to OFF mode value when Deep Sleep mode is active" "0,1" newline bitfld.long 0x84 23. "PADCONFIG33_ISO_BYP_PROXY,Isolation Bypass 0 - IO isolation is preserved 1 - IO isolation is bypassed" "0,1" bitfld.long 0x84 22. "PADCONFIG33_ISO_OVR_PROXY,Isolation Override 0 - IO isolation is preserved 1 - IO isolation is overridden" "0,1" newline bitfld.long 0x84 21. "PADCONFIG33_TX_DIS_PROXY,Driver Disable 0 - Driver is enabled 1 - Driver is disabled" "0,1" bitfld.long 0x84 19.--20. "PADCONFIG33_DRV_STR_PROXY,Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)" "0,1,2,3" newline bitfld.long 0x84 18. "PADCONFIG33_RXACTIVE_PROXY,Input enable for the Pad 0 - Receiver disabled 1 - Receiver enabled" "0,1" bitfld.long 0x84 17. "PADCONFIG33_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection 0 - Pulldown selected 1 - Pullup selected" "0,1" newline bitfld.long 0x84 16. "PADCONFIG33_PULLUDEN_PROXY,Pad Pullup / Pulldown enable. This is an active low signal. 0 - Pullup / Pulldown enabled 1 - Pullup / Pulldown disabled" "0,1" bitfld.long 0x84 15. "PADCONFIG33_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding WKUP DM gating 0 - Deep Sleep pad controls are gated by the WKUP DM 1 - Activate Deep Sleep pad controls (override WKUP DM gating logic)" "0,1" newline bitfld.long 0x84 14. "PADCONFIG33_ST_EN_PROXY,Receiver Schmitt Trigger enable 0 - Schmitt trigger input disabled 1 - Schmitt trigger input enabled" "0,1" bitfld.long 0x84 11.--13. "PADCONFIG33_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad." "0,1,2,3,4,5,6,7" newline bitfld.long 0x84 8. "PADCONFIG33_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1. 0 - Low. A low (0) value on the pin causes a wakeup 1 - High. A high (1) value on the pin causes a wakeup" "0,1" bitfld.long 0x84 7. "PADCONFIG33_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable 0 - Disabled. Wakeup is triggered by change of the pin input value 1 - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be.." "0,1" newline hexmask.long.byte 0x84 0.--3. 1. "PADCONFIG33_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved): 4'b0000 - Mux Mode 0 4'b0001 - Mux Mode 1 4'b0010 - Mux Mode 2 4'b0011 - Mux Mode 3 4'b0100 - Mux Mode 4 4'b0101 - Mux Mode 5 4'b0110 - Mux Mode 6 4'b0111 -.." group.long 0x7008++0x7 line.long 0x0 "CFG0_LOCK1_KICK0_PROXY" hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK1_KICK1_PROXY" hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1_PROXY,- KICK1 component" group.long 0x7100++0x7 line.long 0x0 "CFG0_CLAIMREG_P1_R0" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0,Claim bits for Partition 1" line.long 0x4 "CFG0_CLAIMREG_P1_R1" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1,Claim bits for Partition 1" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-MCU")) tree "WKUP_ESM0_CFG" base ad:0x4100000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_PID,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "CFG_INFO,The Info Register gives the configuration Inforrmation of this ESM." bitfld.long 0x4 31. "LAST_RESET,Indicates the Source of the last Reset" "0,1" hexmask.long.byte 0x4 8.--15. 1. "PULSE_GROUPS,Number of Pulse Error Groups" hexmask.long.byte 0x4 0.--7. 1. "GROUPS,Total number of Error Groups" group.long 0x8++0x3 line.long 0x0 "CFG_EN,The Global Enable Register has the master interrupt mask" hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Enable" wgroup.long 0xC++0x3 line.long 0x0 "CFG_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables" hexmask.long.byte 0x0 0.--3. 1. "KEY,Global Soft Reset" group.long 0x10++0xF line.long 0x0 "CFG_ERR_RAW,Raw Status/Set Register for Configuration Errors" bitfld.long 0x0 0.--2. "STS,This is the raw status for config errors" "0,1,2,3,4,5,6,7" line.long 0x4 "CFG_ERR_STS,Config Error Enable and Clear Register" bitfld.long 0x4 0.--2. "MSK,This is the masked status/clear for config errors" "0,1,2,3,4,5,6,7" line.long 0x8 "CFG_ERR_EN_SET,Config Error Enable Set Register" bitfld.long 0x8 0.--2. "MSK,This is the mask enable set for config errors" "0,1,2,3,4,5,6,7" line.long 0xC "CFG_ERR_EN_CLR,Config Error Interrupt Enabled Clear register" bitfld.long 0xC 0.--2. "MSK,This is the mask enable clear for config errors" "0,1,2,3,4,5,6,7" rgroup.long 0x20++0xF line.long 0x0 "CFG_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt" hexmask.long.word 0x0 16.--31. 1. "PLS,This is the highest priority outstanding low priority pulse interrupt" hexmask.long.word 0x0 0.--15. 1. "LVL,This is the highest priority outstanding low priority level interrupt" line.long 0x4 "CFG_HI_PRI,Shows which is the highest priority outstanding high priority interrupt" hexmask.long.word 0x4 16.--31. 1. "PLS,This is the highest priority outstanding high priority pulse interrupt" hexmask.long.word 0x4 0.--15. 1. "LVL,This is the highest priority outstanding high priority level interrupt" line.long 0x8 "CFG_LOW,Shows which groups have oustanding low priority interrupts" hexmask.long 0x8 0.--31. 1. "STS,This is the raw status for config errors" line.long 0xC "CFG_HI,Shows which groups have oustanding high priority interrupts" hexmask.long 0xC 0.--31. 1. "STS,This is the raw status for config errors" wgroup.long 0x30++0x3 line.long 0x0 "CFG_EOI,End of Interrupt Register" hexmask.long.word 0x0 0.--10. 1. "KEY,This is the interrupt being serviced" group.long 0x40++0x3 line.long 0x0 "CFG_PIN_CTRL,This register controls the error_pin_n output" hexmask.long.byte 0x0 4.--7. 1. "PWM_EN,PWM enable" hexmask.long.byte 0x0 0.--3. 1. "KEY,Pin Control Key" rgroup.long 0x44++0x7 line.long 0x0 "CFG_PIN_STS,This register reflects the status of the error_pin_n output" bitfld.long 0x0 0. "VAL,Value of the error_pin_n" "0,1" line.long 0x4 "CFG_PIN_CNTR,This register shows the current value of the error pin counter" hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Current Counter Value" group.long 0x4C++0x3 line.long 0x0 "CFG_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" rgroup.long 0x50++0x3 line.long 0x0 "CFG_PWMH_PIN_CNTR,This register shows the current value of the error pin PWM high counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value" group.long 0x54++0x3 line.long 0x0 "CFG_PWMH_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM High Counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" rgroup.long 0x58++0x3 line.long 0x0 "CFG_PWML_PIN_CNTR,This register shows the current value of the error pin PWM low counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value" group.long 0x5C++0x3 line.long 0x0 "CFG_PWML_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM Low Counter" hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-MCU")) tree "WKUP_MCU_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG" base ad:0x4210000 rgroup.long 0x0++0x3 line.long 0x0 "INTR_ROUTER_CFG_PID,Identification register" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.byte 0x0 0.--4. 1. "MUX_CNTL,Mux control for interrupt N" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-MCU")) tree "WKUP_CTRL_MMR1_CFG0" base ad:0x4500000 rgroup.long 0x0++0x3 line.long 0x0 "CFG0_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16" newline hexmask.long.byte 0x0 11.--15. 1. "PID_MISC" newline bitfld.long 0x0 8.--10. "PID_MAJOR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR" rgroup.long 0x8++0x3 line.long 0x0 "CFG0_MMR_CFG1" bitfld.long 0x0 31. "MMR_CFG1_PROXY_EN,Proxy addressing activated" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions" group.long 0x100++0x3 line.long 0x0 "CFG0_IPC_SET0" hexmask.long 0x0 4.--31. 1. "IPC_SET0_IPC_SRC_SET,Read returns current value Write: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x0 0. "IPC_SET0_IPC_SET,Read returns 0 Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0,1" group.long 0x180++0x3 line.long 0x0 "CFG0_IPC_CLR0" hexmask.long 0x0 4.--31. 1. "IPC_CLR0_IPC_SRC_CLR,Read returns current value Write: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x0 0. "IPC_CLR0_IPC_CLR,Read returns current value Write: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0,1" rgroup.long 0x270++0x3 line.long 0x0 "CFG0_CBA_ERR_STAT" bitfld.long 0x0 24. "CBA_ERR_STAT_WKUP_SAFE_CBA_ERR,Access Error from Wkup Safe CBASS" "0,1" newline bitfld.long 0x0 20. "CBA_ERR_STAT_MCU_CBA_ERR,Access Error from MCU CBASS" "0,1" rgroup.long 0x280++0x3 line.long 0x0 "CFG0_ACCESS_ERR_STAT" bitfld.long 0x0 9. "ACCESS_ERR_STAT_ACCESS_ERR_IN9,Access Error Detected in MCU PadCfg MMR" "0,1" newline bitfld.long 0x0 8. "ACCESS_ERR_STAT_ACCESS_ERR_IN8,Access Error Detected in MCU Ctrl MMR" "0,1" newline bitfld.long 0x0 4. "ACCESS_ERR_STAT_ACCESS_ERR_IN4,Access Error Detected in MAIN PadCfg MMR" "0,1" newline bitfld.long 0x0 3. "ACCESS_ERR_STAT_ACCESS_ERR_IN3,Access Error Detected in MAIN Ctrl MMR" "0,1" newline bitfld.long 0x0 0. "ACCESS_ERR_STAT_ACCESS_ERR_IN0,Access Error Detected in WKUP Ctrl MMR" "0,1" group.long 0x1008++0x1B line.long 0x0 "CFG0_LOCK0_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK0_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" line.long 0x8 "CFG0_intr_raw_status" bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "CFG0_intr_enabled_status_clear" bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "CFG0_intr_enable" bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "CFG0_intr_enable_clear" bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "CFG0_eoi" hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0xB line.long 0x0 "CFG0_fault_address" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." line.long 0x4 "CFG0_fault_type_status" bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.." line.long 0x8 "CFG0_fault_attr_status" hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID." newline hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID." wgroup.long 0x1030++0x3 line.long 0x0 "CFG0_fault_clear" bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" rgroup.long 0x1100++0x17 line.long 0x0 "CFG0_CLAIMREG_P0_R0_READONLY" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0_READONLY,Claim bits for Partition 0" line.long 0x4 "CFG0_CLAIMREG_P0_R1_READONLY" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P0_R1_READONLY,Claim bits for Partition 0" line.long 0x8 "CFG0_CLAIMREG_P0_R2_READONLY" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P0_R2_READONLY,Claim bits for Partition 0" line.long 0xC "CFG0_CLAIMREG_P0_R3_READONLY" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P0_R3_READONLY,Claim bits for Partition 0" line.long 0x10 "CFG0_CLAIMREG_P0_R4_READONLY" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P0_R4_READONLY,Claim bits for Partition 0" line.long 0x14 "CFG0_CLAIMREG_P0_R5_READONLY" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P0_R5_READONLY,Claim bits for Partition 0" rgroup.long 0x2000++0x3 line.long 0x0 "CFG0_PID_PROXY" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16_PROXY" newline hexmask.long.byte 0x0 11.--15. 1. "PID_MISC_PROXY" newline bitfld.long 0x0 8.--10. "PID_MAJOR_PROXY" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM_PROXY" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR_PROXY" rgroup.long 0x2008++0x3 line.long 0x0 "CFG0_MMR_CFG1_PROXY" bitfld.long 0x0 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing activated" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions" group.long 0x2100++0x3 line.long 0x0 "CFG0_IPC_SET0_PROXY" hexmask.long 0x0 4.--31. 1. "IPC_SET0_IPC_SRC_SET_PROXY,Read returns current value Write: 0 - No effect 1 - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register" newline bitfld.long 0x0 0. "IPC_SET0_IPC_SET_PROXY,Read returns 0 Write: 0 - No effect 1 - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register" "0,1" group.long 0x2180++0x3 line.long 0x0 "CFG0_IPC_CLR0_PROXY" hexmask.long 0x0 4.--31. 1. "IPC_CLR0_IPC_SRC_CLR_PROXY,Read returns current value Write: 0 - No effect 1 - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register" newline bitfld.long 0x0 0. "IPC_CLR0_IPC_CLR_PROXY,Read returns current value Write: 0 - No effect 1 - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register" "0,1" rgroup.long 0x2270++0x3 line.long 0x0 "CFG0_CBA_ERR_STAT_PROXY" bitfld.long 0x0 24. "CBA_ERR_STAT_WKUP_SAFE_CBA_ERR_PROXY,Access Error from Wkup Safe CBASS" "0,1" newline bitfld.long 0x0 20. "CBA_ERR_STAT_MCU_CBA_ERR_PROXY,Access Error from MCU CBASS" "0,1" rgroup.long 0x2280++0x3 line.long 0x0 "CFG0_ACCESS_ERR_STAT_PROXY" bitfld.long 0x0 9. "ACCESS_ERR_STAT_ACCESS_ERR_IN9_PROXY,Access Error Detected in MCU PadCfg MMR" "0,1" newline bitfld.long 0x0 8. "ACCESS_ERR_STAT_ACCESS_ERR_IN8_PROXY,Access Error Detected in MCU Ctrl MMR" "0,1" newline bitfld.long 0x0 4. "ACCESS_ERR_STAT_ACCESS_ERR_IN4_PROXY,Access Error Detected in MAIN PadCfg MMR" "0,1" newline bitfld.long 0x0 3. "ACCESS_ERR_STAT_ACCESS_ERR_IN3_PROXY,Access Error Detected in MAIN Ctrl MMR" "0,1" newline bitfld.long 0x0 0. "ACCESS_ERR_STAT_ACCESS_ERR_IN0_PROXY,Access Error Detected in WKUP Ctrl MMR" "0,1" group.long 0x3008++0x1B line.long 0x0 "CFG0_LOCK0_KICK0_PROXY" hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK0_KICK1_PROXY" hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1_PROXY,- KICK1 component" line.long 0x8 "CFG0_intr_raw_status_PROXY" bitfld.long 0x8 3. "PROXY_ERR_PROXY,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 2. "KICK_ERR_PROXY,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 1. "ADDR_ERR_PROXY,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0x8 0. "PROT_ERR_PROXY,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0xC "CFG0_intr_enabled_status_clear_PROXY" bitfld.long 0xC 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.long 0xC 0. "ENABLED_PROT_ERR_PROXY,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x10 "CFG0_intr_enable_PROXY" bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0x14 "CFG0_intr_enable_clear_PROXY" bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x18 "CFG0_eoi_PROXY" hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x3024++0xB line.long 0x0 "CFG0_fault_address_PROXY" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR_PROXY,Fault Address." line.long 0x4 "CFG0_fault_type_status_PROXY" bitfld.long 0x4 6. "FAULT_NS_PROXY,Non-secure access." "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE_PROXY,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv =.." line.long 0x8 "CFG0_fault_attr_status_PROXY" hexmask.long.word 0x8 20.--31. 1. "FAULT_XID_PROXY,XID." newline hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID." newline hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID." wgroup.long 0x3030++0x3 line.long 0x0 "CFG0_fault_clear_PROXY" bitfld.long 0x0 0. "FAULT_CLR_PROXY,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" group.long 0x3100++0x17 line.long 0x0 "CFG0_CLAIMREG_P0_R0" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P0_R0,Claim bits for Partition 0" line.long 0x4 "CFG0_CLAIMREG_P0_R1" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P0_R1,Claim bits for Partition 0" line.long 0x8 "CFG0_CLAIMREG_P0_R2" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P0_R2,Claim bits for Partition 0" line.long 0xC "CFG0_CLAIMREG_P0_R3" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P0_R3,Claim bits for Partition 0" line.long 0x10 "CFG0_CLAIMREG_P0_R4" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P0_R4,Claim bits for Partition 0" line.long 0x14 "CFG0_CLAIMREG_P0_R5" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P0_R5,Claim bits for Partition 0" group.long 0x4020++0x3 line.long 0x0 "CFG0_MCU_GPIO_CTRL" bitfld.long 0x0 0. "MCU_GPIO_CTRL_WAKEN,Activates MCU_GPIO wakeup event operation by controling the MCU_GPIO LPSC clockstop_ack behavior. Field values (Others are reserved): 1'b0 - No MCU_GPIO wakeup support. MCU_GPIO vbus clock is gated on clkstop_ack from MCU_GPIO to.." "0,1" group.long 0x4084++0x17 line.long 0x0 "CFG0_DBOUNCE_CFG1" hexmask.long.byte 0x0 0.--5. 1. "DBOUNCE_CFG1_DB_CFG,Configures the debounce period used for I/Os with debounce_sel1 activated. See the AM62xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=745&filtertitle=2719&filteritem=14547)" line.long 0x4 "CFG0_DBOUNCE_CFG2" hexmask.long.byte 0x4 0.--5. 1. "DBOUNCE_CFG2_DB_CFG,Configures the debounce period used for I/Os with debounce_sel2 activated. See the AM62xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=745&filtertitle=2719&filteritem=14547)" line.long 0x8 "CFG0_DBOUNCE_CFG3" hexmask.long.byte 0x8 0.--5. 1. "DBOUNCE_CFG3_DB_CFG,Configures the debounce period used for I/Os with debounce_sel3 activated. See the AM62xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=745&filtertitle=2719&filteritem=14547)" line.long 0xC "CFG0_DBOUNCE_CFG4" hexmask.long.byte 0xC 0.--5. 1. "DBOUNCE_CFG4_DB_CFG,Configures the debounce period used for I/Os with debounce_sel4 activated. See the AM62xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=745&filtertitle=2719&filteritem=14547)" line.long 0x10 "CFG0_DBOUNCE_CFG5" hexmask.long.byte 0x10 0.--5. 1. "DBOUNCE_CFG5_DB_CFG,Configures the debounce period used for I/Os with debounce_sel5 activated. See the AM62xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=745&filtertitle=2719&filteritem=14547)" line.long 0x14 "CFG0_DBOUNCE_CFG6" hexmask.long.byte 0x14 0.--5. 1. "DBOUNCE_CFG6_DB_CFG,Configures the debounce period used for I/Os with debounce_sel6 activated. See the AM62xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=745&filtertitle=2719&filteritem=14547)" rgroup.long 0x40A0++0x3 line.long 0x0 "CFG0_TEMP_DIODE_TRIM" hexmask.long.word 0x0 0.--13. 1. "TEMP_DIODE_TRIM_TRIM,Sets the diode non-ideality factor (n) starting from 100th place decimal and going down" rgroup.long 0x40B0++0x3 line.long 0x0 "CFG0_IO_VOLTAGE_STAT" bitfld.long 0x0 17. "IO_VOLTAGE_STAT_GPMC,Indicates the voltage for the GPMC I/O group (VDDSHV3) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 16. "IO_VOLTAGE_STAT_GEMAC,Indicates the voltage for the GEMAC I/O group (VDDSHV2) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 11. "IO_VOLTAGE_STAT_MMC2,Indicates the voltage for the MMC2 I/O group (VDDSHV6) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 10. "IO_VOLTAGE_STAT_MMC1,Indicates the voltage for the MMC1 I/O group (VDDSHV5) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 9. "IO_VOLTAGE_STAT_MMC0,Indicates the voltage for the MMC0 I/O group (VDDSHV4) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 8. "IO_VOLTAGE_STAT_GENERAL,Indicates the voltage for the General I/O group (VDDSHV0) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 2. "IO_VOLTAGE_STAT_CANUART,Indicates the voltage for the CANUART I/O group (VDDSHV_WKUP) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 1. "IO_VOLTAGE_STAT_FLASH,Indicates the voltage for the Flash I/O group (VDDSHV1) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 0. "IO_VOLTAGE_STAT_WKUP_MCU,Indicates the voltage for the WKUP_MCU I/O group (VDDSHV_MCU) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" group.long 0x4204++0x3 line.long 0x0 "CFG0_MCU_TIMER1_CTRL" bitfld.long 0x0 8. "MCU_TIMER1_CTRL_CASCADE_EN,Activates cascading of TIMER1 to TIMER0" "0,1" group.long 0x420C++0x3 line.long 0x0 "CFG0_MCU_TIMER3_CTRL" bitfld.long 0x0 8. "MCU_TIMER3_CTRL_CASCADE_EN,Activates cascading of TIMER3 to TIMER2" "0,1" group.long 0x42E0++0x3 line.long 0x0 "CFG0_MCU_I2C0_CTRL" bitfld.long 0x0 0. "MCU_I2C0_CTRL_HS_MCS_EN,HS Mode controller current source activate. When set activates the current-source pull-up on the SCL output. Only one controller on the I2C bus should activate SCL current sourcing." "0,1" group.long 0x4604++0x7 line.long 0x0 "CFG0_WKUP_MTOG_CTRL0" rbitfld.long 0x0 31. "WKUP_MTOG_CTRL0_IDLE_STAT,Idle Status" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "WKUP_MTOG_CTRL0_FORCE_TIMEOUT,Force Timout This is a fault tolerant bitfield. Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and.." newline bitfld.long 0x0 15. "WKUP_MTOG_CTRL0_TIMEOUT_EN,Timeout Activate 1'b0 - Deactivate the gasket. Clear the interrupt and reset the counter 1'b1 - Activate the timeout gasket functions" "0,1" newline bitfld.long 0x0 0.--2. "WKUP_MTOG_CTRL0_TIMEOUT_VAL,Gasket Timeout Value Selects the number of clock cycles before the interface is considered to have timed out" "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_WKUP_MTOG_CTRL1" rbitfld.long 0x4 31. "WKUP_MTOG_CTRL1_IDLE_STAT,Idle Status" "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "WKUP_MTOG_CTRL1_FORCE_TIMEOUT,Force Timout This is a fault tolerant bitfield. Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout and.." newline bitfld.long 0x4 15. "WKUP_MTOG_CTRL1_TIMEOUT_EN,Timeout Activate 1'b0 - Deactivate the gasket. Clear the interrupt and reset the counter 1'b1 - Activate the timeout gasket functions" "0,1" newline bitfld.long 0x4 0.--2. "WKUP_MTOG_CTRL1_TIMEOUT_VAL,Gasket Timeout Value Selects the number of clock cycles before the interface is considered to have timed out" "0,1,2,3,4,5,6,7" rgroup.long 0x4610++0x3 line.long 0x0 "CFG0_TOG_STAT" bitfld.long 0x0 15. "TOG_STAT_SLV_TOG_STAT,Error Status of Target Timeout Gaskets Field values (others are reserved): 1'b0 - No Error 1'b1 - Error from mcu2dm timeout gasket MCU_TIMEOUT0" "0,1" newline bitfld.long 0x0 0.--1. "TOG_STAT_MST_TOG_STAT,Error Status of Target Timeout Gaskets Field values (others are reserved): 2'b00 - No Error 2'b01 - Error from dm2mcu WKUP_TIMEOUT1 gasket 2'b10 - Error from dm2ws WKUP_TIMEOUT0 gasket 2'b11 - Error from both dm2mcu and dm2ws.." "0,1,2,3" group.long 0x5008++0x7 line.long 0x0 "CFG0_LOCK1_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK1_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1,- KICK1 component" rgroup.long 0x5100++0x33 line.long 0x0 "CFG0_CLAIMREG_P1_R0_READONLY" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0_READONLY,Claim bits for Partition 1" line.long 0x4 "CFG0_CLAIMREG_P1_R1_READONLY" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1_READONLY,Claim bits for Partition 1" line.long 0x8 "CFG0_CLAIMREG_P1_R2_READONLY" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2_READONLY,Claim bits for Partition 1" line.long 0xC "CFG0_CLAIMREG_P1_R3_READONLY" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P1_R3_READONLY,Claim bits for Partition 1" line.long 0x10 "CFG0_CLAIMREG_P1_R4_READONLY" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P1_R4_READONLY,Claim bits for Partition 1" line.long 0x14 "CFG0_CLAIMREG_P1_R5_READONLY" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P1_R5_READONLY,Claim bits for Partition 1" line.long 0x18 "CFG0_CLAIMREG_P1_R6_READONLY" hexmask.long 0x18 0.--31. 1. "CLAIMREG_P1_R6_READONLY,Claim bits for Partition 1" line.long 0x1C "CFG0_CLAIMREG_P1_R7_READONLY" hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P1_R7_READONLY,Claim bits for Partition 1" line.long 0x20 "CFG0_CLAIMREG_P1_R8_READONLY" hexmask.long 0x20 0.--31. 1. "CLAIMREG_P1_R8_READONLY,Claim bits for Partition 1" line.long 0x24 "CFG0_CLAIMREG_P1_R9_READONLY" hexmask.long 0x24 0.--31. 1. "CLAIMREG_P1_R9_READONLY,Claim bits for Partition 1" line.long 0x28 "CFG0_CLAIMREG_P1_R10_READONLY" hexmask.long 0x28 0.--31. 1. "CLAIMREG_P1_R10_READONLY,Claim bits for Partition 1" line.long 0x2C "CFG0_CLAIMREG_P1_R11_READONLY" hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P1_R11_READONLY,Claim bits for Partition 1" line.long 0x30 "CFG0_CLAIMREG_P1_R12_READONLY" hexmask.long 0x30 0.--31. 1. "CLAIMREG_P1_R12_READONLY,Claim bits for Partition 1" group.long 0x6020++0x3 line.long 0x0 "CFG0_MCU_GPIO_CTRL_PROXY" bitfld.long 0x0 0. "MCU_GPIO_CTRL_WAKEN_PROXY,Activates MCU_GPIO wakeup event operation by controling the MCU_GPIO LPSC clockstop_ack behavior. Field values (Others are reserved): 1'b0 - No MCU_GPIO wakeup support. MCU_GPIO vbus clock is gated on clkstop_ack from MCU_GPIO.." "0,1" group.long 0x6084++0x17 line.long 0x0 "CFG0_DBOUNCE_CFG1_PROXY" hexmask.long.byte 0x0 0.--5. 1. "DBOUNCE_CFG1_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel1 activated. See the AM62xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=745&filtertitle=2719&filteritem=14547)" line.long 0x4 "CFG0_DBOUNCE_CFG2_PROXY" hexmask.long.byte 0x4 0.--5. 1. "DBOUNCE_CFG2_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel2 activated. See the AM62xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=745&filtertitle=2719&filteritem=14547)" line.long 0x8 "CFG0_DBOUNCE_CFG3_PROXY" hexmask.long.byte 0x8 0.--5. 1. "DBOUNCE_CFG3_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel3 activated. See the AM62xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=745&filtertitle=2719&filteritem=14547)" line.long 0xC "CFG0_DBOUNCE_CFG4_PROXY" hexmask.long.byte 0xC 0.--5. 1. "DBOUNCE_CFG4_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel4 activated. See the AM62xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=745&filtertitle=2719&filteritem=14547)" line.long 0x10 "CFG0_DBOUNCE_CFG5_PROXY" hexmask.long.byte 0x10 0.--5. 1. "DBOUNCE_CFG5_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel5 activated. See the AM62xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=745&filtertitle=2719&filteritem=14547)" line.long 0x14 "CFG0_DBOUNCE_CFG6_PROXY" hexmask.long.byte 0x14 0.--5. 1. "DBOUNCE_CFG6_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel6 activated. See the AM62xx IO Integration Spec for Detail (https://pds.design.ti.com/cgi-bin/viewdocs?pds_bgid=21&docconfigid=745&filtertitle=2719&filteritem=14547)" rgroup.long 0x60A0++0x3 line.long 0x0 "CFG0_TEMP_DIODE_TRIM_PROXY" hexmask.long.word 0x0 0.--13. 1. "TEMP_DIODE_TRIM_TRIM_PROXY,Sets the diode non-ideality factor (n) starting from 100th place decimal and going down" rgroup.long 0x60B0++0x3 line.long 0x0 "CFG0_IO_VOLTAGE_STAT_PROXY" bitfld.long 0x0 17. "IO_VOLTAGE_STAT_GPMC_PROXY,Indicates the voltage for the GPMC I/O group (VDDSHV3) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 16. "IO_VOLTAGE_STAT_GEMAC_PROXY,Indicates the voltage for the GEMAC I/O group (VDDSHV2) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 11. "IO_VOLTAGE_STAT_MMC2_PROXY,Indicates the voltage for the MMC2 I/O group (VDDSHV6) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 10. "IO_VOLTAGE_STAT_MMC1_PROXY,Indicates the voltage for the MMC1 I/O group (VDDSHV5) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 9. "IO_VOLTAGE_STAT_MMC0_PROXY,Indicates the voltage for the MMC0 I/O group (VDDSHV4) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 8. "IO_VOLTAGE_STAT_GENERAL_PROXY,Indicates the voltage for the General I/O group (VDDSHV0) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 2. "IO_VOLTAGE_STAT_CANUART_PROXY,Indicates the voltage for the CANUART I/O group (VDDSHV_WKUP) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 1. "IO_VOLTAGE_STAT_FLASH_PROXY,Indicates the voltage for the Flash I/O group (VDDSHV1) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" newline bitfld.long 0x0 0. "IO_VOLTAGE_STAT_WKUP_MCU_PROXY,Indicates the voltage for the WKUP_MCU I/O group (VDDSHV_MCU) Field values (others are reserved): 1'b0 - I/O group is set for 3.3V 1'b1 - I/O group is set for 1.8V" "0,1" group.long 0x6204++0x3 line.long 0x0 "CFG0_MCU_TIMER1_CTRL_PROXY" bitfld.long 0x0 8. "MCU_TIMER1_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER1 to TIMER0" "0,1" group.long 0x620C++0x3 line.long 0x0 "CFG0_MCU_TIMER3_CTRL_PROXY" bitfld.long 0x0 8. "MCU_TIMER3_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER3 to TIMER2" "0,1" group.long 0x62E0++0x3 line.long 0x0 "CFG0_MCU_I2C0_CTRL_PROXY" bitfld.long 0x0 0. "MCU_I2C0_CTRL_HS_MCS_EN_PROXY,HS Mode controller current source activate. When set activates the current-source pull-up on the SCL output. Only one controller on the I2C bus should activate SCL current sourcing." "0,1" group.long 0x6604++0x7 line.long 0x0 "CFG0_WKUP_MTOG_CTRL0_PROXY" rbitfld.long 0x0 31. "WKUP_MTOG_CTRL0_IDLE_STAT_PROXY,Idle Status" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "WKUP_MTOG_CTRL0_FORCE_TIMEOUT_PROXY,Force Timout This is a fault tolerant bitfield. Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout.." newline bitfld.long 0x0 15. "WKUP_MTOG_CTRL0_TIMEOUT_EN_PROXY,Timeout Activate 1'b0 - Deactivate the gasket. Clear the interrupt and reset the counter 1'b1 - Activate the timeout gasket functions" "0,1" newline bitfld.long 0x0 0.--2. "WKUP_MTOG_CTRL0_TIMEOUT_VAL_PROXY,Gasket Timeout Value Selects the number of clock cycles before the interface is considered to have timed out" "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_WKUP_MTOG_CTRL1_PROXY" rbitfld.long 0x4 31. "WKUP_MTOG_CTRL1_IDLE_STAT_PROXY,Idle Status" "0,1" newline hexmask.long.byte 0x4 16.--23. 1. "WKUP_MTOG_CTRL1_FORCE_TIMEOUT_PROXY,Force Timout This is a fault tolerant bitfield. Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value the force_timeout.." newline bitfld.long 0x4 15. "WKUP_MTOG_CTRL1_TIMEOUT_EN_PROXY,Timeout Activate 1'b0 - Deactivate the gasket. Clear the interrupt and reset the counter 1'b1 - Activate the timeout gasket functions" "0,1" newline bitfld.long 0x4 0.--2. "WKUP_MTOG_CTRL1_TIMEOUT_VAL_PROXY,Gasket Timeout Value Selects the number of clock cycles before the interface is considered to have timed out" "0,1,2,3,4,5,6,7" rgroup.long 0x6610++0x3 line.long 0x0 "CFG0_TOG_STAT_PROXY" bitfld.long 0x0 15. "TOG_STAT_SLV_TOG_STAT_PROXY,Error Status of Target Timeout Gaskets Field values (others are reserved): 1'b0 - No Error 1'b1 - Error from mcu2dm timeout gasket MCU_TIMEOUT0" "0,1" newline bitfld.long 0x0 0.--1. "TOG_STAT_MST_TOG_STAT_PROXY,Error Status of Target Timeout Gaskets Field values (others are reserved): 2'b00 - No Error 2'b01 - Error from dm2mcu WKUP_TIMEOUT1 gasket 2'b10 - Error from dm2ws WKUP_TIMEOUT0 gasket 2'b11 - Error from both dm2mcu and dm2ws.." "0,1,2,3" group.long 0x7008++0x7 line.long 0x0 "CFG0_LOCK1_KICK0_PROXY" hexmask.long 0x0 0.--31. 1. "LOCK1_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK1_KICK1_PROXY" hexmask.long 0x4 0.--31. 1. "LOCK1_KICK1_PROXY,- KICK1 component" group.long 0x7100++0x33 line.long 0x0 "CFG0_CLAIMREG_P1_R0" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P1_R0,Claim bits for Partition 1" line.long 0x4 "CFG0_CLAIMREG_P1_R1" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P1_R1,Claim bits for Partition 1" line.long 0x8 "CFG0_CLAIMREG_P1_R2" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P1_R2,Claim bits for Partition 1" line.long 0xC "CFG0_CLAIMREG_P1_R3" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P1_R3,Claim bits for Partition 1" line.long 0x10 "CFG0_CLAIMREG_P1_R4" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P1_R4,Claim bits for Partition 1" line.long 0x14 "CFG0_CLAIMREG_P1_R5" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P1_R5,Claim bits for Partition 1" line.long 0x18 "CFG0_CLAIMREG_P1_R6" hexmask.long 0x18 0.--31. 1. "CLAIMREG_P1_R6,Claim bits for Partition 1" line.long 0x1C "CFG0_CLAIMREG_P1_R7" hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P1_R7,Claim bits for Partition 1" line.long 0x20 "CFG0_CLAIMREG_P1_R8" hexmask.long 0x20 0.--31. 1. "CLAIMREG_P1_R8,Claim bits for Partition 1" line.long 0x24 "CFG0_CLAIMREG_P1_R9" hexmask.long 0x24 0.--31. 1. "CLAIMREG_P1_R9,Claim bits for Partition 1" line.long 0x28 "CFG0_CLAIMREG_P1_R10" hexmask.long 0x28 0.--31. 1. "CLAIMREG_P1_R10,Claim bits for Partition 1" line.long 0x2C "CFG0_CLAIMREG_P1_R11" hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P1_R11,Claim bits for Partition 1" line.long 0x30 "CFG0_CLAIMREG_P1_R12" hexmask.long 0x30 0.--31. 1. "CLAIMREG_P1_R12,Claim bits for Partition 1" group.long 0x8000++0x3 line.long 0x0 "CFG0_MCU_OBSCLK_CTRL" bitfld.long 0x0 24. "MCU_OBSCLK_CTRL_OUT_MUX_SEL,MCU_OBSCLK pin output mux selection. Note HFOSC0_CLK is a direct output from the HFOSC0 distinct from HFOSC0_CLKOUT. Note when HFOSC0_CLK is selected (1'b1) the MCU_OBSCLK_CTRL_clk_sel field must be programmed to 4'b0001." "0,1" newline bitfld.long 0x0 16. "MCU_OBSCLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the OBSCLK divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed." "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "MCU_OBSCLK_CTRL_CLK_DIV,MCU_OBSCLK pin clock selection output divider Output clock is divided by clk_div+1" newline hexmask.long.byte 0x0 0.--3. 1. "MCU_OBSCLK_CTRL_CLK_SEL,MCU_OBSCLK pin clock selection Field values (others are reserved): 4'b0000 - CLK_12M_RC 4'b0001 - '0' 4'b0010 - MCU_PLL0_HSDIV0_CLKOUT 4'b0011 - MCU_PLL0_HSDIV4_CLKOUT 4'b0100 - MCU_PLLCTRL_OBSCLK 4'b0101 - CLK_32K_RC 4'b0110 -.." group.long 0x8010++0x3 line.long 0x0 "CFG0_HFOSC0_CTRL" bitfld.long 0x0 7. "HFOSC0_CTRL_PD_C,Oscillator powerdown control. When set oscillator is deactivated. Oscillator output is tristated if bp_c=0" "0,1" newline bitfld.long 0x0 4. "HFOSC0_CTRL_BP_C,Reserved - Must Write '0'" "0,1" group.long 0x8018++0x3 line.long 0x0 "CFG0_HFOSC0_TRIM" bitfld.long 0x0 31. "HFOSC0_TRIM_TRIM_EN,Apply MMR values to OSC trim inputs instead of tie-offs" "0,1" newline bitfld.long 0x0 20.--21. "HFOSC0_TRIM_HYST,Sets comparator hysterisis" "0,1,2,3" newline bitfld.long 0x0 16.--18. "HFOSC0_TRIM_I_MULT,AGC AMP current multiplication gain" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--13. 1. "HFOSC0_TRIM_R_REF,Sets the AMP AGC bias current" newline hexmask.long.byte 0x0 4.--7. 1. "HFOSC0_TRIM_I_IBIAS_COMP,Sets the COMP bias current" newline hexmask.long.byte 0x0 0.--3. 1. "HFOSC0_TRIM_R_IBIAS_REF,Sets the base IBIAS reference" rgroup.long 0x8020++0x3 line.long 0x0 "CFG0_HFOSC0_STAT" bitfld.long 0x0 0. "HFOSC0_STAT_DS_ON_WFI_STAT,Allows MCU to monitor the DM attempting a Deep Sleep" "0,1" group.long 0x8024++0x3 line.long 0x0 "CFG0_RC12M_OSC_TRIM" bitfld.long 0x0 6. "RC12M_OSC_TRIM_TRIMOSC_COARSE_DIR,Coarse adjustment direction. If output is greater than 12.5 0 - Coarse adjustment decreases frequency 1 - Coarse adjustment increases frequency" "0,1" newline bitfld.long 0x0 3.--5. "RC12M_OSC_TRIM_TRIMOSC_COARSE,Coarse adjustment. Frequency is decreased or increased by 1.25 MHz per value based on the trimosc_coarse_dir value." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RC12M_OSC_TRIM_TRIMOSC_FINE,Fine adjustment. Decreases the frequency by 250 KHz per value." "0,1,2,3,4,5,6,7" group.long 0x8030++0x3 line.long 0x0 "CFG0_HFOSC0_CLKOUT_32K_CTRL" bitfld.long 0x0 31. "HFOSC0_CLKOUT_32K_CTRL_RESET,Asynchronous Divider Reset 1 = Divider is Reset HFOSC0_CLKOUT32K reset. 0 = Divider out of reset HFOSC0_CLKOUT_32K running." "0: Divider out of reset,1: Divider is Reset" newline bitfld.long 0x0 15. "HFOSC0_CLKOUT_32K_CTRL_CLKOUT_EN,HFOSC0_CLKOUT_32K activate: 0 = Synchronously Deactivate HFOSC0_CLKOUT_32KHz 1 = Synchronously Activate HFOSC0_CKLKOUT_32KHz" "0: Synchronously Deactivate HFOSC0_CLKOUT_32KHz,1: Synchronously Activate HFOSC0_CKLKOUT_32KHz" newline bitfld.long 0x0 8. "HFOSC0_CLKOUT_32K_CTRL_SYNC_DIS,HFOSC0_CLKOUT_32K Synchronize Deactivate 0 = Divider Updates are shadowed and take effect on counter reset. 1 = Divider Updates are immediate and hazardous Do not set this bit to 1'b1 during normal use." "0: Divider Updates are shadowed and take effect on..,1: Divider Updates are immediate and hazardous Do.." newline hexmask.long.byte 0x0 0.--6. 1. "HFOSC0_CLKOUT_32K_CTRL_HSDIV,HFOSC0_CLKOUT_32K divider: HFOSC0_CLKKOUT_32K Frequency = HFOSC0 Frequency / [8 * (hsdiv + 1)] Ex. HFOSC0 Frequency = 26MHz. hsdiv = 101 (Default) HFOSC0_CLKOUT_32K = 26MHz / (8 * (101+1)) = 26MHz / 816 = 31.9 KHz" group.long 0x8038++0x7 line.long 0x0 "CFG0_LFXOSC_CTRL" bitfld.long 0x0 7. "LFXOSC_CTRL_PD_C,Oscillator powerdown control. When set oscillator is deactivated. Oscillator output is tristated if bp_c=0" "0,1" newline bitfld.long 0x0 4. "LFXOSC_CTRL_BP_C,Oscillator bypass control. When set oscillator is in bypass mode" "0,1" line.long 0x4 "CFG0_LFXOSC_TRIM" bitfld.long 0x4 20.--21. "LFXOSC_TRIM_HYST,Sets comparator hysterisis Field values (others are reserved): 2'b00 - Hysteresis deactivated 2'b01 - Type 1 hysteresis activated (Default) 2'b10 - Type 2 hysteresis activated 2'b11 - Both types 1 & 2 hysteresis activated" "0,1,2,3" newline bitfld.long 0x4 16.--18. "LFXOSC_TRIM_I_MULT,AGC AMP current multiplication gain Field values (others are reserved): 3'b000 - 3x AMP_AGC IBIAS 3'b001 - 4x AMP_AGC IBIAS 3'b010 - 5x AMP_AGC IBIAS (Default) 3'b011 - 6x AMP_AGC IBIAS 3'b100 - 7x AMP_AGC IBIAS 3'b101 - 8x AMP_AGC.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "LFXOSC_TRIM_R_REF,Sets the AMP AGC bias current Field values (others are reserved): 6'b000000 - 0 K Ohm 6'b000001 - 24 K Ohm 6'b000010 - 48 K Ohm 6'b000011 - 73 K Ohm 6'b000100 - 97 K Ohm 6'b000101 - 121 K Ohm 6'b000110 - 145 K Ohm 6'b000111 - 169 K Ohm.." newline hexmask.long.byte 0x4 4.--7. 1. "LFXOSC_TRIM_I_IBIAS_COMP,Sets the COMP bias current Field values (others are reserved): 4'b0000 - Base IBIAS ref x2 4'b0001 - Base IBIAS ref x3 4'b0010 - Base IBIAS ref x4 4'b0011 - Base IBIAS ref x5 4'b0100 - Base IBIAS ref x6 4'b0101 - Base IBIAS ref.." newline hexmask.long.byte 0x4 0.--3. 1. "LFXOSC_TRIM_R_IBIAS_REF,Sets the base IBIAS reference Field values (others are reserved): 4'b0000 - 512 K Ohm 4'b0001 - 576 K Ohm 4'b0010 - 640 K Ohm 4'b0011 - 704 K Ohm (Default) 4'b0100 - 768 K Ohm 4'b0101 - 832 K Ohm 4'b0110 - 896 K Ohm 4'b0111 - 960.." group.long 0x8050++0x3 line.long 0x0 "CFG0_MCU_PLL_CLKSEL" bitfld.long 0x0 31. "MCU_PLL_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a mcu_reset_z for MCU PLL[2:0]. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MCU_PLL_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to activate bypass software override. This bit is set (1'b1) when an MCU warm reset occurs and will keep MCU PLL[2:0] in bypass mode.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x0 8. "MCU_PLL_CLKSEL_CLKLOSS_SWTCH_EN,When set activates automatic switching of MCU PLL[2:0] clock source to CLK_12M_RC if HFOSC0 clock loss is detected" "0,1" group.long 0x8058++0x3 line.long 0x0 "CFG0_DEVICE_CLKOUT_32K_CTRL" bitfld.long 0x0 0.--1. "DEVICE_CLKOUT_32K_CTRL_CLK_32K_RC_SEL,Selects the source of the device level 32KHz Clock Field values (others are reserved): 2'b00 - CLK_32K_RC 2'b01 - HFOSC0_CLKOUT_32K 2'b10 - Reserved - (implementation: CLK_32K_RC) 2'b11 - LFOSC0_CLKOUT" "0,1,2,3" group.long 0x8060++0x13 line.long 0x0 "CFG0_MCU_TIMER0_CLKSEL" bitfld.long 0x0 0.--2. "MCU_TIMER0_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 2 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL0_HSDIV5_CLKOUT.." "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_MCU_TIMER1_CLKSEL" bitfld.long 0x4 0.--2. "MCU_TIMER1_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 2 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL0_HSDIV5_CLKOUT.." "0,1,2,3,4,5,6,7" line.long 0x8 "CFG0_MCU_TIMER2_CLKSEL" bitfld.long 0x8 0.--2. "MCU_TIMER2_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 2 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL0_HSDIV5_CLKOUT.." "0,1,2,3,4,5,6,7" line.long 0xC "CFG0_MCU_TIMER3_CLKSEL" bitfld.long 0xC 0.--2. "MCU_TIMER3_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 2 3'b010 - CLK_12M_RC 3'b011 - MCU_PLL0_HSDIV5_CLKOUT.." "0,1,2,3,4,5,6,7" line.long 0x10 "CFG0_MCU_GPIO_CLKSEL" bitfld.long 0x10 0.--1. "MCU_GPIO_CLKSEL_CLK_SEL,MCU_GPIO clock selection. Must be set to MCU_SYSCLK0/4 whenever MCU_GPIO VBUS interface is activated. Other clock source may be selected as a clk_sel up clock for DeepSleep modes after MCU_GPIO is gated off through LPSC. Field.." "0,1,2,3" group.long 0x8080++0x7 line.long 0x0 "CFG0_MCU_MCAN0_CLKSEL" bitfld.long 0x0 0.--1. "MCU_MCAN0_CLKSEL_CLK_SEL,Selects the clock source for MCAN0 Field values (others are reserved): 2'b00 - MCU_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 2'b10 - HFOSC0_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0,1,2,3" line.long 0x4 "CFG0_MCU_MCAN1_CLKSEL" bitfld.long 0x4 0.--1. "MCU_MCAN1_CLKSEL_CLK_SEL,Selects the clock source for MCAN1 Field values (others are reserved): 2'b00 - MCU_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 2'b10 - HFOSC0_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0,1,2,3" group.long 0x80A0++0x7 line.long 0x0 "CFG0_MCU_SPI0_CLKSEL" bitfld.long 0x0 16. "MCU_SPI0_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0,1" line.long 0x4 "CFG0_MCU_SPI1_CLKSEL" bitfld.long 0x4 16. "MCU_SPI1_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0,1" group.long 0x80B0++0x3 line.long 0x0 "CFG0_MCU_WWD0_CLKSEL" bitfld.long 0x0 31. "MCU_WWD0_CLKSEL_WRTLOCK,When set locks WWD0_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x0 0.--1. "MCU_WWD0_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - DEVICE_CLKOUT_32K 2'b10 - CLK_12M_RC 2'b11 - CLK_32K_RC" "0,1,2,3" group.long 0x9008++0x7 line.long 0x0 "CFG0_LOCK2_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK2_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK2_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK2_KICK1,- KICK1 component" rgroup.long 0x9100++0x7 line.long 0x0 "CFG0_CLAIMREG_P2_R0_READONLY" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P2_R0_READONLY,Claim bits for Partition 2" line.long 0x4 "CFG0_CLAIMREG_P2_R1_READONLY" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P2_R1_READONLY,Claim bits for Partition 2" group.long 0xA000++0x3 line.long 0x0 "CFG0_MCU_OBSCLK_CTRL_PROXY" bitfld.long 0x0 24. "MCU_OBSCLK_CTRL_OUT_MUX_SEL_PROXY,MCU_OBSCLK pin output mux selection. Note HFOSC0_CLK is a direct output from the HFOSC0 distinct from HFOSC0_CLKOUT. Note when HFOSC0_CLK is selected (1'b1) the MCU_OBSCLK_CTRL_clk_sel field must be programmed to.." "0,1" newline bitfld.long 0x0 16. "MCU_OBSCLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the OBSCLK divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed." "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "MCU_OBSCLK_CTRL_CLK_DIV_PROXY,MCU_OBSCLK pin clock selection output divider Output clock is divided by clk_div+1" newline hexmask.long.byte 0x0 0.--3. 1. "MCU_OBSCLK_CTRL_CLK_SEL_PROXY,MCU_OBSCLK pin clock selection Field values (others are reserved): 4'b0000 - CLK_12M_RC 4'b0001 - '0' 4'b0010 - MCU_PLL0_HSDIV0_CLKOUT 4'b0011 - MCU_PLL0_HSDIV4_CLKOUT 4'b0100 - MCU_PLLCTRL_OBSCLK 4'b0101 - CLK_32K_RC.." group.long 0xA010++0x3 line.long 0x0 "CFG0_HFOSC0_CTRL_PROXY" bitfld.long 0x0 7. "HFOSC0_CTRL_PD_C_PROXY,Oscillator powerdown control. When set oscillator is deactivated. Oscillator output is tristated if bp_c=0" "0,1" newline bitfld.long 0x0 4. "HFOSC0_CTRL_BP_C_PROXY,Reserved - Must Write '0'" "0,1" group.long 0xA018++0x3 line.long 0x0 "CFG0_HFOSC0_TRIM_PROXY" bitfld.long 0x0 31. "HFOSC0_TRIM_TRIM_EN_PROXY,Apply MMR values to OSC trim inputs instead of tie-offs" "0,1" newline bitfld.long 0x0 20.--21. "HFOSC0_TRIM_HYST_PROXY,Sets comparator hysterisis" "0,1,2,3" newline bitfld.long 0x0 16.--18. "HFOSC0_TRIM_I_MULT_PROXY,AGC AMP current multiplication gain" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--13. 1. "HFOSC0_TRIM_R_REF_PROXY,Sets the AMP AGC bias current" newline hexmask.long.byte 0x0 4.--7. 1. "HFOSC0_TRIM_I_IBIAS_COMP_PROXY,Sets the COMP bias current" newline hexmask.long.byte 0x0 0.--3. 1. "HFOSC0_TRIM_R_IBIAS_REF_PROXY,Sets the base IBIAS reference" rgroup.long 0xA020++0x3 line.long 0x0 "CFG0_HFOSC0_STAT_PROXY" bitfld.long 0x0 0. "HFOSC0_STAT_DS_ON_WFI_STAT_PROXY,Allows MCU to monitor the DM attempting a Deep Sleep" "0,1" group.long 0xA024++0x3 line.long 0x0 "CFG0_RC12M_OSC_TRIM_PROXY" bitfld.long 0x0 6. "RC12M_OSC_TRIM_TRIMOSC_COARSE_DIR_PROXY,Coarse adjustment direction. If output is greater than 12.5 0 - Coarse adjustment decreases frequency 1 - Coarse adjustment increases frequency" "0,1" newline bitfld.long 0x0 3.--5. "RC12M_OSC_TRIM_TRIMOSC_COARSE_PROXY,Coarse adjustment. Frequency is decreased or increased by 1.25 MHz per value based on the trimosc_coarse_dir value." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RC12M_OSC_TRIM_TRIMOSC_FINE_PROXY,Fine adjustment. Decreases the frequency by 250 KHz per value." "0,1,2,3,4,5,6,7" group.long 0xA030++0x3 line.long 0x0 "CFG0_HFOSC0_CLKOUT_32K_CTRL_PROXY" bitfld.long 0x0 31. "HFOSC0_CLKOUT_32K_CTRL_RESET_PROXY,Asynchronous Divider Reset 1 = Divider is Reset HFOSC0_CLKOUT32K reset. 0 = Divider out of reset HFOSC0_CLKOUT_32K running." "0: Divider out of reset,1: Divider is Reset" newline bitfld.long 0x0 15. "HFOSC0_CLKOUT_32K_CTRL_CLKOUT_EN_PROXY,HFOSC0_CLKOUT_32K activate: 0 = Synchronously Deactivate HFOSC0_CLKOUT_32KHz 1 = Synchronously Activate HFOSC0_CKLKOUT_32KHz" "0: Synchronously Deactivate HFOSC0_CLKOUT_32KHz,1: Synchronously Activate HFOSC0_CKLKOUT_32KHz" newline bitfld.long 0x0 8. "HFOSC0_CLKOUT_32K_CTRL_SYNC_DIS_PROXY,HFOSC0_CLKOUT_32K Synchronize Deactivate 0 = Divider Updates are shadowed and take effect on counter reset. 1 = Divider Updates are immediate and hazardous Do not set this bit to 1'b1 during normal use." "0: Divider Updates are shadowed and take effect on..,1: Divider Updates are immediate and hazardous Do.." newline hexmask.long.byte 0x0 0.--6. 1. "HFOSC0_CLKOUT_32K_CTRL_HSDIV_PROXY,HFOSC0_CLKOUT_32K divider: HFOSC0_CLKKOUT_32K Frequency = HFOSC0 Frequency / [8 * (hsdiv + 1)] Ex. HFOSC0 Frequency = 26MHz. hsdiv = 101 (Default) HFOSC0_CLKOUT_32K = 26MHz / (8 * (101+1)) = 26MHz / 816 = 31.9 KHz" group.long 0xA038++0x7 line.long 0x0 "CFG0_LFXOSC_CTRL_PROXY" bitfld.long 0x0 7. "LFXOSC_CTRL_PD_C_PROXY,Oscillator powerdown control. When set oscillator is deactivated. Oscillator output is tristated if bp_c=0" "0,1" newline bitfld.long 0x0 4. "LFXOSC_CTRL_BP_C_PROXY,Oscillator bypass control. When set oscillator is in bypass mode" "0,1" line.long 0x4 "CFG0_LFXOSC_TRIM_PROXY" bitfld.long 0x4 20.--21. "LFXOSC_TRIM_HYST_PROXY,Sets comparator hysterisis Field values (others are reserved): 2'b00 - Hysteresis deactivated 2'b01 - Type 1 hysteresis activated (Default) 2'b10 - Type 2 hysteresis activated 2'b11 - Both types 1 & 2 hysteresis activated" "0,1,2,3" newline bitfld.long 0x4 16.--18. "LFXOSC_TRIM_I_MULT_PROXY,AGC AMP current multiplication gain Field values (others are reserved): 3'b000 - 3x AMP_AGC IBIAS 3'b001 - 4x AMP_AGC IBIAS 3'b010 - 5x AMP_AGC IBIAS (Default) 3'b011 - 6x AMP_AGC IBIAS 3'b100 - 7x AMP_AGC IBIAS 3'b101 - 8x.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "LFXOSC_TRIM_R_REF_PROXY,Sets the AMP AGC bias current Field values (others are reserved): 6'b000000 - 0 K Ohm 6'b000001 - 24 K Ohm 6'b000010 - 48 K Ohm 6'b000011 - 73 K Ohm 6'b000100 - 97 K Ohm 6'b000101 - 121 K Ohm 6'b000110 - 145 K Ohm 6'b000111 - 169.." newline hexmask.long.byte 0x4 4.--7. 1. "LFXOSC_TRIM_I_IBIAS_COMP_PROXY,Sets the COMP bias current Field values (others are reserved): 4'b0000 - Base IBIAS ref x2 4'b0001 - Base IBIAS ref x3 4'b0010 - Base IBIAS ref x4 4'b0011 - Base IBIAS ref x5 4'b0100 - Base IBIAS ref x6 4'b0101 - Base IBIAS.." newline hexmask.long.byte 0x4 0.--3. 1. "LFXOSC_TRIM_R_IBIAS_REF_PROXY,Sets the base IBIAS reference Field values (others are reserved): 4'b0000 - 512 K Ohm 4'b0001 - 576 K Ohm 4'b0010 - 640 K Ohm 4'b0011 - 704 K Ohm (Default) 4'b0100 - 768 K Ohm 4'b0101 - 832 K Ohm 4'b0110 - 896 K Ohm 4'b0111.." group.long 0xA050++0x3 line.long 0x0 "CFG0_MCU_PLL_CLKSEL_PROXY" bitfld.long 0x0 31. "MCU_PLL_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a mcu_reset_z for MCU PLL[2:0]. This bit must not be set until after the corresponding byp_warm_rst bit has been.." "0,1" newline bitfld.long 0x0 23. "MCU_PLL_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to activate bypass software override. This bit is set (1'b1) when an MCU warm reset occurs and will keep MCU PLL[2:0] in bypass.." "0: Exit bypass mode,1: Maintain bypass mode" newline bitfld.long 0x0 8. "MCU_PLL_CLKSEL_CLKLOSS_SWTCH_EN_PROXY,When set activates automatic switching of MCU PLL[2:0] clock source to CLK_12M_RC if HFOSC0 clock loss is detected" "0,1" group.long 0xA058++0x3 line.long 0x0 "CFG0_DEVICE_CLKOUT_32K_CTRL_PROXY" bitfld.long 0x0 0.--1. "DEVICE_CLKOUT_32K_CTRL_CLK_32K_RC_SEL_PROXY,Selects the source of the device level 32KHz Clock Field values (others are reserved): 2'b00 - CLK_32K_RC 2'b01 - HFOSC0_CLKOUT_32K 2'b10 - Reserved - (implementation: CLK_32K_RC) 2'b11 - LFOSC0_CLKOUT" "0,1,2,3" group.long 0xA060++0x13 line.long 0x0 "CFG0_MCU_TIMER0_CLKSEL_PROXY" bitfld.long 0x0 0.--2. "MCU_TIMER0_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 2 3'b010 - CLK_12M_RC 3'b011 -.." "0,1,2,3,4,5,6,7" line.long 0x4 "CFG0_MCU_TIMER1_CLKSEL_PROXY" bitfld.long 0x4 0.--2. "MCU_TIMER1_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 2 3'b010 - CLK_12M_RC 3'b011 -.." "0,1,2,3,4,5,6,7" line.long 0x8 "CFG0_MCU_TIMER2_CLKSEL_PROXY" bitfld.long 0x8 0.--2. "MCU_TIMER2_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 2 3'b010 - CLK_12M_RC 3'b011 -.." "0,1,2,3,4,5,6,7" line.long 0xC "CFG0_MCU_TIMER3_CLKSEL_PROXY" bitfld.long 0xC 0.--2. "MCU_TIMER3_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT 3'b001 - MCU_SYSCLK0 / 2 3'b010 - CLK_12M_RC 3'b011 -.." "0,1,2,3,4,5,6,7" line.long 0x10 "CFG0_MCU_GPIO_CLKSEL_PROXY" bitfld.long 0x10 0.--1. "MCU_GPIO_CLKSEL_CLK_SEL_PROXY,MCU_GPIO clock selection. Must be set to MCU_SYSCLK0/4 whenever MCU_GPIO VBUS interface is activated. Other clock source may be selected as a clk_sel up clock for DeepSleep modes after MCU_GPIO is gated off through LPSC." "0,1,2,3" group.long 0xA080++0x7 line.long 0x0 "CFG0_MCU_MCAN0_CLKSEL_PROXY" bitfld.long 0x0 0.--1. "MCU_MCAN0_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MCAN0 Field values (others are reserved): 2'b00 - MCU_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 2'b10 - HFOSC0_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0,1,2,3" line.long 0x4 "CFG0_MCU_MCAN1_CLKSEL_PROXY" bitfld.long 0x4 0.--1. "MCU_MCAN1_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MCAN1 Field values (others are reserved): 2'b00 - MCU_PLL0_HSDIV4_CLKOUT 2'b01 - MCU_EXT_REFCLK0 2'b10 - HFOSC0_CLKOUT 2'b11 - HFOSC0_CLKOUT" "0,1,2,3" group.long 0xA0A0++0x7 line.long 0x0 "CFG0_MCU_SPI0_CLKSEL_PROXY" bitfld.long 0x0 16. "MCU_SPI0_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0,1" line.long 0x4 "CFG0_MCU_SPI1_CLKSEL_PROXY" bitfld.long 0x4 16. "MCU_SPI1_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection 1'b0 - Internal clock loopback 1'b1 - Loopback from pad" "0,1" group.long 0xA0B0++0x3 line.long 0x0 "CFG0_MCU_WWD0_CLKSEL_PROXY" bitfld.long 0x0 31. "MCU_WWD0_CLKSEL_WRTLOCK_PROXY,When set locks WWD0_CLKSEL from further writes until the next module reset." "0,1" newline bitfld.long 0x0 0.--1. "MCU_WWD0_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved): 2'b00 - HFOSC0_CLKOUT 2'b01 - DEVICE_CLKOUT_32K 2'b10 - CLK_12M_RC 2'b11 - CLK_32K_RC" "0,1,2,3" group.long 0xB008++0x7 line.long 0x0 "CFG0_LOCK2_KICK0_PROXY" hexmask.long 0x0 0.--31. 1. "LOCK2_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK2_KICK1_PROXY" hexmask.long 0x4 0.--31. 1. "LOCK2_KICK1_PROXY,- KICK1 component" group.long 0xB100++0x7 line.long 0x0 "CFG0_CLAIMREG_P2_R0" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P2_R0,Claim bits for Partition 2" line.long 0x4 "CFG0_CLAIMREG_P2_R1" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P2_R1,Claim bits for Partition 2" group.long 0xC020++0x1B line.long 0x0 "CFG0_MCU_R5FSS0_LBIST_CTRL" bitfld.long 0x0 31. "MCU_R5FSS0_LBIST_CTRL_BIST_RESET,This bitfield is not used." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "MCU_R5FSS0_LBIST_CTRL_BIST_RUN,This bitfield is not used." newline hexmask.long.byte 0x0 16.--20. 1. "MCU_R5FSS0_LBIST_CTRL_SUBCHIP_ID,Specifies which sub-chip is to be tested" newline hexmask.long.byte 0x0 12.--15. 1. "MCU_R5FSS0_LBIST_CTRL_RUNBIST_MODE,Runbist mode activate if all bits are 1" newline bitfld.long 0x0 8.--9. "MCU_R5FSS0_LBIST_CTRL_DC_DEF,Clock delay after scan_activate switching" "0,1,2,3" newline bitfld.long 0x0 7. "MCU_R5FSS0_LBIST_CTRL_LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "MCU_R5FSS0_LBIST_CTRL_DIVIDE_RATIO,LBIST clock divide ratio" line.long 0x4 "CFG0_MCU_R5FSS0_LBIST_PATCOUNT" hexmask.long.word 0x4 16.--29. 1. "MCU_R5FSS0_LBIST_PATCOUNT_STATIC_PC_DEF,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "MCU_R5FSS0_LBIST_PATCOUNT_SET_PC_DEF,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "MCU_R5FSS0_LBIST_PATCOUNT_RESET_PC_DEF,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "MCU_R5FSS0_LBIST_PATCOUNT_SCAN_PC_DEF,Number of chain test patterns to run" line.long 0x8 "CFG0_MCU_R5FSS0_LBIST_SEED0" hexmask.long 0x8 0.--31. 1. "MCU_R5FSS0_LBIST_SEED0_PRPG_DEF,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_MCU_R5FSS0_LBIST_SEED1" hexmask.long.tbyte 0xC 0.--20. 1. "MCU_R5FSS0_LBIST_SEED1_PRPG_DEF,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_MCU_R5FSS0_LBIST_SPARE0" hexmask.long 0x10 2.--31. 1. "MCU_R5FSS0_LBIST_SPARE0_SPARE0,LBIST spare bits" newline bitfld.long 0x10 1. "MCU_R5FSS0_LBIST_SPARE0_PBIST_SELFTEST_EN,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "MCU_R5FSS0_LBIST_SPARE0_LBIST_SELFTEST_EN,LBIST isolation control" "0,1" line.long 0x14 "CFG0_MCU_R5FSS0_LBIST_SPARE1" hexmask.long 0x14 0.--31. 1. "MCU_R5FSS0_LBIST_SPARE1_SPARE1,LBIST spare bits" line.long 0x18 "CFG0_MCU_R5FSS0_LBIST_STAT" rbitfld.long 0x18 31. "MCU_R5FSS0_LBIST_STAT_BIST_DONE,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "MCU_R5FSS0_LBIST_STAT_BIST_RUNNING,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "MCU_R5FSS0_LBIST_STAT_OUT_MUX_CTL,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0,1,2,3" newline hexmask.long.byte 0x18 0.--7. 1. "MCU_R5FSS0_LBIST_STAT_MISR_MUX_CTL,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xC03C++0x3 line.long 0x0 "CFG0_MCU_R5FSS0_LBIST_MISR" hexmask.long 0x0 0.--31. 1. "MCU_R5FSS0_LBIST_MISR_MISR_RESULT,32-bits of MISR value selected by misr_mux_ctl" group.long 0xD008++0x7 line.long 0x0 "CFG0_LOCK3_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK3_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK3_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK3_KICK1,- KICK1 component" rgroup.long 0xD100++0x3 line.long 0x0 "CFG0_CLAIMREG_P3_R0_READONLY" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P3_R0_READONLY,Claim bits for Partition 3" group.long 0xE020++0x1B line.long 0x0 "CFG0_MCU_R5FSS0_LBIST_CTRL_PROXY" bitfld.long 0x0 31. "MCU_R5FSS0_LBIST_CTRL_BIST_RESET_PROXY,This bitfield is not used." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "MCU_R5FSS0_LBIST_CTRL_BIST_RUN_PROXY,This bitfield is not used." newline hexmask.long.byte 0x0 16.--20. 1. "MCU_R5FSS0_LBIST_CTRL_SUBCHIP_ID_PROXY,Specifies which sub-chip is to be tested" newline hexmask.long.byte 0x0 12.--15. 1. "MCU_R5FSS0_LBIST_CTRL_RUNBIST_MODE_PROXY,Runbist mode activate if all bits are 1" newline bitfld.long 0x0 8.--9. "MCU_R5FSS0_LBIST_CTRL_DC_DEF_PROXY,Clock delay after scan_activate switching" "0,1,2,3" newline bitfld.long 0x0 7. "MCU_R5FSS0_LBIST_CTRL_LOAD_DIV_PROXY,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "MCU_R5FSS0_LBIST_CTRL_DIVIDE_RATIO_PROXY,LBIST clock divide ratio" line.long 0x4 "CFG0_MCU_R5FSS0_LBIST_PATCOUNT_PROXY" hexmask.long.word 0x4 16.--29. 1. "MCU_R5FSS0_LBIST_PATCOUNT_STATIC_PC_DEF_PROXY,Number of stuck-at patterns to run" newline hexmask.long.byte 0x4 8.--11. 1. "MCU_R5FSS0_LBIST_PATCOUNT_SET_PC_DEF_PROXY,Number of set patterns to run" newline hexmask.long.byte 0x4 4.--7. 1. "MCU_R5FSS0_LBIST_PATCOUNT_RESET_PC_DEF_PROXY,Number of reset patterns to run" newline hexmask.long.byte 0x4 0.--3. 1. "MCU_R5FSS0_LBIST_PATCOUNT_SCAN_PC_DEF_PROXY,Number of chain test patterns to run" line.long 0x8 "CFG0_MCU_R5FSS0_LBIST_SEED0_PROXY" hexmask.long 0x8 0.--31. 1. "MCU_R5FSS0_LBIST_SEED0_PRPG_DEF_PROXY,Initial seed for PRPG (bits 31:0)" line.long 0xC "CFG0_MCU_R5FSS0_LBIST_SEED1_PROXY" hexmask.long.tbyte 0xC 0.--20. 1. "MCU_R5FSS0_LBIST_SEED1_PRPG_DEF_PROXY,Initial seed for PRPG (bits 52:32)" line.long 0x10 "CFG0_MCU_R5FSS0_LBIST_SPARE0_PROXY" hexmask.long 0x10 2.--31. 1. "MCU_R5FSS0_LBIST_SPARE0_SPARE0_PROXY,LBIST spare bits" newline bitfld.long 0x10 1. "MCU_R5FSS0_LBIST_SPARE0_PBIST_SELFTEST_EN_PROXY,PBIST isolation control" "0,1" newline bitfld.long 0x10 0. "MCU_R5FSS0_LBIST_SPARE0_LBIST_SELFTEST_EN_PROXY,LBIST isolation control" "0,1" line.long 0x14 "CFG0_MCU_R5FSS0_LBIST_SPARE1_PROXY" hexmask.long 0x14 0.--31. 1. "MCU_R5FSS0_LBIST_SPARE1_SPARE1_PROXY,LBIST spare bits" line.long 0x18 "CFG0_MCU_R5FSS0_LBIST_STAT_PROXY" rbitfld.long 0x18 31. "MCU_R5FSS0_LBIST_STAT_BIST_DONE_PROXY,LBIST is done" "0,1" newline rbitfld.long 0x18 15. "MCU_R5FSS0_LBIST_STAT_BIST_RUNNING_PROXY,LBIST is running" "0,1" newline bitfld.long 0x18 8.--9. "MCU_R5FSS0_LBIST_STAT_OUT_MUX_CTL_PROXY,Selects source of LBIST output 00 - LBIST IP PID value 01 - LBIST CTRL ID value 1x - MISR value" "0,1,2,3" newline hexmask.long.byte 0x18 0.--7. 1. "MCU_R5FSS0_LBIST_STAT_MISR_MUX_CTL_PROXY,Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR." rgroup.long 0xE03C++0x3 line.long 0x0 "CFG0_MCU_R5FSS0_LBIST_MISR_PROXY" hexmask.long 0x0 0.--31. 1. "MCU_R5FSS0_LBIST_MISR_MISR_RESULT_PROXY,32-bits of MISR value selected by misr_mux_ctl" group.long 0xF008++0x7 line.long 0x0 "CFG0_LOCK3_KICK0_PROXY" hexmask.long 0x0 0.--31. 1. "LOCK3_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK3_KICK1_PROXY" hexmask.long 0x4 0.--31. 1. "LOCK3_KICK1_PROXY,- KICK1 component" group.long 0xF100++0x3 line.long 0x0 "CFG0_CLAIMREG_P3_R0" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P3_R0,Claim bits for Partition 3" group.long 0x11008++0x7 line.long 0x0 "CFG0_LOCK4_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK4_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK4_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK4_KICK1,- KICK1 component" rgroup.long 0x11100++0x4F line.long 0x0 "CFG0_CLAIMREG_P4_R0_READONLY" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P4_R0_READONLY,Claim bits for Partition 4" line.long 0x4 "CFG0_CLAIMREG_P4_R1_READONLY" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P4_R1_READONLY,Claim bits for Partition 4" line.long 0x8 "CFG0_CLAIMREG_P4_R2_READONLY" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P4_R2_READONLY,Claim bits for Partition 4" line.long 0xC "CFG0_CLAIMREG_P4_R3_READONLY" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P4_R3_READONLY,Claim bits for Partition 4" line.long 0x10 "CFG0_CLAIMREG_P4_R4_READONLY" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P4_R4_READONLY,Claim bits for Partition 4" line.long 0x14 "CFG0_CLAIMREG_P4_R5_READONLY" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P4_R5_READONLY,Claim bits for Partition 4" line.long 0x18 "CFG0_CLAIMREG_P4_R6_READONLY" hexmask.long 0x18 0.--31. 1. "CLAIMREG_P4_R6_READONLY,Claim bits for Partition 4" line.long 0x1C "CFG0_CLAIMREG_P4_R7_READONLY" hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P4_R7_READONLY,Claim bits for Partition 4" line.long 0x20 "CFG0_CLAIMREG_P4_R8_READONLY" hexmask.long 0x20 0.--31. 1. "CLAIMREG_P4_R8_READONLY,Claim bits for Partition 4" line.long 0x24 "CFG0_CLAIMREG_P4_R9_READONLY" hexmask.long 0x24 0.--31. 1. "CLAIMREG_P4_R9_READONLY,Claim bits for Partition 4" line.long 0x28 "CFG0_CLAIMREG_P4_R10_READONLY" hexmask.long 0x28 0.--31. 1. "CLAIMREG_P4_R10_READONLY,Claim bits for Partition 4" line.long 0x2C "CFG0_CLAIMREG_P4_R11_READONLY" hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P4_R11_READONLY,Claim bits for Partition 4" line.long 0x30 "CFG0_CLAIMREG_P4_R12_READONLY" hexmask.long 0x30 0.--31. 1. "CLAIMREG_P4_R12_READONLY,Claim bits for Partition 4" line.long 0x34 "CFG0_CLAIMREG_P4_R13_READONLY" hexmask.long 0x34 0.--31. 1. "CLAIMREG_P4_R13_READONLY,Claim bits for Partition 4" line.long 0x38 "CFG0_CLAIMREG_P4_R14_READONLY" hexmask.long 0x38 0.--31. 1. "CLAIMREG_P4_R14_READONLY,Claim bits for Partition 4" line.long 0x3C "CFG0_CLAIMREG_P4_R15_READONLY" hexmask.long 0x3C 0.--31. 1. "CLAIMREG_P4_R15_READONLY,Claim bits for Partition 4" line.long 0x40 "CFG0_CLAIMREG_P4_R16_READONLY" hexmask.long 0x40 0.--31. 1. "CLAIMREG_P4_R16_READONLY,Claim bits for Partition 4" line.long 0x44 "CFG0_CLAIMREG_P4_R17_READONLY" hexmask.long 0x44 0.--31. 1. "CLAIMREG_P4_R17_READONLY,Claim bits for Partition 4" line.long 0x48 "CFG0_CLAIMREG_P4_R18_READONLY" hexmask.long 0x48 0.--31. 1. "CLAIMREG_P4_R18_READONLY,Claim bits for Partition 4" line.long 0x4C "CFG0_CLAIMREG_P4_R19_READONLY" hexmask.long 0x4C 0.--31. 1. "CLAIMREG_P4_R19_READONLY,Claim bits for Partition 4" group.long 0x13008++0x7 line.long 0x0 "CFG0_LOCK4_KICK0_PROXY" hexmask.long 0x0 0.--31. 1. "LOCK4_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK4_KICK1_PROXY" hexmask.long 0x4 0.--31. 1. "LOCK4_KICK1_PROXY,- KICK1 component" group.long 0x13100++0x4F line.long 0x0 "CFG0_CLAIMREG_P4_R0" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P4_R0,Claim bits for Partition 4" line.long 0x4 "CFG0_CLAIMREG_P4_R1" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P4_R1,Claim bits for Partition 4" line.long 0x8 "CFG0_CLAIMREG_P4_R2" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P4_R2,Claim bits for Partition 4" line.long 0xC "CFG0_CLAIMREG_P4_R3" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P4_R3,Claim bits for Partition 4" line.long 0x10 "CFG0_CLAIMREG_P4_R4" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P4_R4,Claim bits for Partition 4" line.long 0x14 "CFG0_CLAIMREG_P4_R5" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P4_R5,Claim bits for Partition 4" line.long 0x18 "CFG0_CLAIMREG_P4_R6" hexmask.long 0x18 0.--31. 1. "CLAIMREG_P4_R6,Claim bits for Partition 4" line.long 0x1C "CFG0_CLAIMREG_P4_R7" hexmask.long 0x1C 0.--31. 1. "CLAIMREG_P4_R7,Claim bits for Partition 4" line.long 0x20 "CFG0_CLAIMREG_P4_R8" hexmask.long 0x20 0.--31. 1. "CLAIMREG_P4_R8,Claim bits for Partition 4" line.long 0x24 "CFG0_CLAIMREG_P4_R9" hexmask.long 0x24 0.--31. 1. "CLAIMREG_P4_R9,Claim bits for Partition 4" line.long 0x28 "CFG0_CLAIMREG_P4_R10" hexmask.long 0x28 0.--31. 1. "CLAIMREG_P4_R10,Claim bits for Partition 4" line.long 0x2C "CFG0_CLAIMREG_P4_R11" hexmask.long 0x2C 0.--31. 1. "CLAIMREG_P4_R11,Claim bits for Partition 4" line.long 0x30 "CFG0_CLAIMREG_P4_R12" hexmask.long 0x30 0.--31. 1. "CLAIMREG_P4_R12,Claim bits for Partition 4" line.long 0x34 "CFG0_CLAIMREG_P4_R13" hexmask.long 0x34 0.--31. 1. "CLAIMREG_P4_R13,Claim bits for Partition 4" line.long 0x38 "CFG0_CLAIMREG_P4_R14" hexmask.long 0x38 0.--31. 1. "CLAIMREG_P4_R14,Claim bits for Partition 4" line.long 0x3C "CFG0_CLAIMREG_P4_R15" hexmask.long 0x3C 0.--31. 1. "CLAIMREG_P4_R15,Claim bits for Partition 4" line.long 0x40 "CFG0_CLAIMREG_P4_R16" hexmask.long 0x40 0.--31. 1. "CLAIMREG_P4_R16,Claim bits for Partition 4" line.long 0x44 "CFG0_CLAIMREG_P4_R17" hexmask.long 0x44 0.--31. 1. "CLAIMREG_P4_R17,Claim bits for Partition 4" line.long 0x48 "CFG0_CLAIMREG_P4_R18" hexmask.long 0x48 0.--31. 1. "CLAIMREG_P4_R18,Claim bits for Partition 4" line.long 0x4C "CFG0_CLAIMREG_P4_R19" hexmask.long 0x4C 0.--31. 1. "CLAIMREG_P4_R19,Claim bits for Partition 4" group.long 0x18000++0x3 line.long 0x0 "CFG0_POR_CTRL" bitfld.long 0x0 29. "POR_CTRL_OVRD_SET5,Reserved override set" "0,1" newline bitfld.long 0x0 28. "POR_CTRL_OVRD_SET4,POKLVB override set" "0,1" newline bitfld.long 0x0 27. "POR_CTRL_OVRD_SET3,POKLVA override set" "0,1" newline bitfld.long 0x0 26. "POR_CTRL_OVRD_SET2,POKHV override set" "0,1" newline bitfld.long 0x0 25. "POR_CTRL_OVRD_SET1,BGOK override set" "0,1" newline bitfld.long 0x0 24. "POR_CTRL_OVRD_SET0,PORHV override set" "0,1" newline bitfld.long 0x0 21. "POR_CTRL_OVRD5,Reserved override activate" "0,1" newline bitfld.long 0x0 20. "POR_CTRL_OVRD4,POKLVB override activate" "0,1" newline bitfld.long 0x0 19. "POR_CTRL_OVRD3,POKLVA override activate" "0,1" newline bitfld.long 0x0 18. "POR_CTRL_OVRD2,POKHV override activate" "0,1" newline bitfld.long 0x0 17. "POR_CTRL_OVRD1,BGOK override activate" "0,1" newline bitfld.long 0x0 16. "POR_CTRL_OVRD0,PORHV override activate" "0,1" newline bitfld.long 0x0 7. "POR_CTRL_TRIM_SEL,POR Trim Select 0 - Trim selections for Bandgap and POKs come from HHV defaults 1 - Trim selections for Bandgap and POKs come from POR_BANDGAP_CTRL and POR_POKxxx_CTRL registers" "0,1" newline bitfld.long 0x0 4. "POR_CTRL_MASK_HHV,Mask HHV/SOC_PORz outputs when applying new trim values" "0,1" rgroup.long 0x18004++0x3 line.long 0x0 "CFG0_POR_STAT" bitfld.long 0x0 8. "POR_STAT_BGOK,Bandgap OK status" "0,1" newline bitfld.long 0x0 4. "POR_STAT_SOC_POR,POR module status 0 - Module is in functional mode 1 - Module is in reset mode" "0,1" group.long 0x18100++0x3 line.long 0x0 "CFG0_POR_BANDGAP_CTRL" hexmask.long.byte 0x0 16.--19. 1. "POR_BANDGAP_CTRL_BGAPI,Bandgap output current trim bits" newline hexmask.long.byte 0x0 8.--15. 1. "POR_BANDGAP_CTRL_BGAPV,Bandgap output voltage magnitude trim bits" newline hexmask.long.byte 0x0 0.--7. 1. "POR_BANDGAP_CTRL_BGAPC,Bandgap slope trim bits. Bit7 is used to calculate the offset" group.long 0x18110++0x17 line.long 0x0 "CFG0_POK_VDDA_MCU_UV_CTRL" bitfld.long 0x0 31. "POK_VDDA_MCU_UV_CTRL_HYST_EN,Activate POK hysteresis" "0,1" newline bitfld.long 0x0 7. "POK_VDDA_MCU_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "POK_VDDA_MCU_UV_CTRL_POK_TRIM,POK Trim Bits" line.long 0x4 "CFG0_POK_VDDA_MCU_OV_CTRL" bitfld.long 0x4 31. "POK_VDDA_MCU_OV_CTRL_HYST_EN,Activate POK hysteresis" "0,1" newline bitfld.long 0x4 7. "POK_VDDA_MCU_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "POK_VDDA_MCU_OV_CTRL_POK_TRIM,POK Trim Bits" line.long 0x8 "CFG0_POK_VDD_CORE_UV_CTRL" bitfld.long 0x8 31. "POK_VDD_CORE_UV_CTRL_HYST_EN,Activate POK hysteresis" "0,1" newline bitfld.long 0x8 7. "POK_VDD_CORE_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "POK_VDD_CORE_UV_CTRL_POK_TRIM,POK Trim Bits" line.long 0xC "CFG0_POK_VDD_CORE_OV_CTRL" bitfld.long 0xC 31. "POK_VDD_CORE_OV_CTRL_HYST_EN,Activate POK hysteresis" "0,1" newline bitfld.long 0xC 7. "POK_VDD_CORE_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "POK_VDD_CORE_OV_CTRL_POK_TRIM,POK Trim Bits" line.long 0x10 "CFG0_POK_VDDR_CORE_UV_CTRL" bitfld.long 0x10 31. "POK_VDDR_CORE_UV_CTRL_HYST_EN,Activate POK hysteresis" "0,1" newline bitfld.long 0x10 7. "POK_VDDR_CORE_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "POK_VDDR_CORE_UV_CTRL_POK_TRIM,POK Trim Bits" line.long 0x14 "CFG0_POK_VDDR_CORE_OV_CTRL" bitfld.long 0x14 31. "POK_VDDR_CORE_OV_CTRL_HYST_EN,Activate POK hysteresis" "0,1" newline bitfld.long 0x14 7. "POK_VDDR_CORE_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x14 0.--6. 1. "POK_VDDR_CORE_OV_CTRL_POK_TRIM,POK Trim Bits" group.long 0x18138++0x1F line.long 0x0 "CFG0_POK_VMON_CAP_MCU_GENERAL_UV_CTRL" bitfld.long 0x0 31. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_HYST_EN,Activate POK hysteresis" "0,1" newline bitfld.long 0x0 7. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_POK_TRIM,POK Trim Bits" line.long 0x4 "CFG0_POK_VMON_CAP_MCU_GENERAL_OV_CTRL" bitfld.long 0x4 31. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_HYST_EN,Activate POK hysteresis" "0,1" newline bitfld.long 0x4 7. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_POK_TRIM,POK Trim Bits" line.long 0x8 "CFG0_POK_VDDSHV_MAIN_1P8_UV_CTRL" bitfld.long 0x8 31. "POK_VDDSHV_MAIN_1P8_UV_CTRL_HYST_EN,Activate POK hysteresis" "0,1" newline bitfld.long 0x8 7. "POK_VDDSHV_MAIN_1P8_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "POK_VDDSHV_MAIN_1P8_UV_CTRL_POK_TRIM,POK Trim Bits" line.long 0xC "CFG0_POK_VDDSHV_MAIN_1P8_OV_CTRL" bitfld.long 0xC 31. "POK_VDDSHV_MAIN_1P8_OV_CTRL_HYST_EN,Activate POK hysteresis" "0,1" newline bitfld.long 0xC 7. "POK_VDDSHV_MAIN_1P8_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "POK_VDDSHV_MAIN_1P8_OV_CTRL_POK_TRIM,POK Trim Bits" line.long 0x10 "CFG0_POK_VDDSHV_MAIN_3P3_UV_CTRL" bitfld.long 0x10 31. "POK_VDDSHV_MAIN_3P3_UV_CTRL_HYST_EN,Activate POK hysteresis" "0,1" newline bitfld.long 0x10 7. "POK_VDDSHV_MAIN_3P3_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "POK_VDDSHV_MAIN_3P3_UV_CTRL_POK_TRIM,POK Trim Bits" line.long 0x14 "CFG0_POK_VDDSHV_MAIN_3P3_OV_CTRL" bitfld.long 0x14 31. "POK_VDDSHV_MAIN_3P3_OV_CTRL_HYST_EN,Activate POK hysteresis" "0,1" newline bitfld.long 0x14 7. "POK_VDDSHV_MAIN_3P3_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x14 0.--6. 1. "POK_VDDSHV_MAIN_3P3_OV_CTRL_POK_TRIM,POK Trim Bits" line.long 0x18 "CFG0_POK_VDDS_DDRIO_UV_CTRL" bitfld.long 0x18 31. "POK_VDDS_DDRIO_UV_CTRL_HYST_EN,Activate POK hysteresis" "0,1" newline bitfld.long 0x18 7. "POK_VDDS_DDRIO_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x18 0.--6. 1. "POK_VDDS_DDRIO_UV_CTRL_POK_TRIM,POK Trim Bits" line.long 0x1C "CFG0_POK_VDDS_DDRIO_OV_CTRL" bitfld.long 0x1C 31. "POK_VDDS_DDRIO_OV_CTRL_HYST_EN,Activate POK hysteresis" "0,1" newline bitfld.long 0x1C 7. "POK_VDDS_DDRIO_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x1C 0.--6. 1. "POK_VDDS_DDRIO_OV_CTRL_POK_TRIM,POK Trim Bits" group.long 0x18160++0x3 line.long 0x0 "CFG0_POK_VDDA_PMIC_IN_CTRL" bitfld.long 0x0 31. "POK_VDDA_PMIC_IN_CTRL_HYST_EN,Activate POK hysteresis" "0,1" newline bitfld.long 0x0 15. "POK_VDDA_PMIC_IN_CTRL_OVER_VOLT_DET,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" group.long 0x18170++0x3 line.long 0x0 "CFG0_RST_CTRL" bitfld.long 0x0 22. "RST_CTRL_DM_WDT_RST_EN_Z,Deactivate Reset from DM WDT propogating to MCU domain: 0 - Activated 1 - Deactivated" "0,1" newline bitfld.long 0x0 18. "RST_CTRL_MCU_RESET_ISO_DONE_Z,MCU can set this bit to block warm reset in the main domain which is useful when the MCU may be accessing main domain resources (peripherals memory..). In this case the MCU will be notified via an interrupt that there.." "0,1" newline bitfld.long 0x0 17. "RST_CTRL_MCU_ESM_ERROR_RST_EN_Z,Deactivate Reset of MCU by ESM 0 - Activated 1 - Deactivated" "0,1" newline bitfld.long 0x0 16. "RST_CTRL_SMS_COLD_RESET_EN_Z,Deactivate Reset of MCU by SMS 0 - Activated 1 - Deactivated" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "RST_CTRL_SW_MCU_WARMRST,This is a fault tolerant bitfield. Causes MCU Domain Warm Reset when set to 4'b0110 Bits will reset to 4'b1111" newline hexmask.long.byte 0x0 4.--7. 1. "RST_CTRL_SW_MAIN_POR,This is a fault tolerant bitfield. Causes MAIN Domain Power On Reset when set to 4'b0110 Bits will reset to 4'b1111" newline hexmask.long.byte 0x0 0.--3. 1. "RST_CTRL_SW_MAIN_WARMRST,This is a fault tolerant bitfield. Causes MAIN Domain Warm Reset when set to 4'b0110 Bits will reset to 4'b1111" rgroup.long 0x18174++0x3 line.long 0x0 "CFG0_RST_STAT" bitfld.long 0x0 0. "RST_STAT_MAIN_RESETSTATZ,Status of Main Domain Reset: 0 = Reset Asserted 1 = Reset Deasserted" "0: Reset Asserted,1: Reset Deasserted" group.long 0x18178++0xB line.long 0x0 "CFG0_RST_SRC" bitfld.long 0x0 31. "RST_SRC_SAFETY_ERROR,Reset Caused by MCU ESM Error" "0,1" newline bitfld.long 0x0 30. "RST_SRC_MAIN_ESM_ERROR,Reset Caused by Main ESM Error" "0,1" newline bitfld.long 0x0 25. "RST_SRC_SW_MAIN_POR_FROM_MAIN,Software Main Power On Reset From MAIN CTRL MMR" "0,1" newline bitfld.long 0x0 24. "RST_SRC_SW_MAIN_POR_FROM_MCU,Software Main Power On Reset From MCU CTRL MMR" "0,1" newline bitfld.long 0x0 23. "RST_SRC_DS_MAIN_PORZ,Reset of Main/Wkup Domains while in Deep Sleep as a result of an MCU Warm Reset" "0,1" newline bitfld.long 0x0 22. "RST_SRC_DM_WDT_RST,Watchdog Initiated Reset" "0,1" newline bitfld.long 0x0 21. "RST_SRC_SW_MAIN_WARMRST_FROM_MAIN,Software Main Warm Reset from MAIN CTRL MMR" "0,1" newline bitfld.long 0x0 20. "RST_SRC_SW_MAIN_WARMRST_FROM_MCU,Software Main Warm Reset From MCU CTRL MMR" "0,1" newline bitfld.long 0x0 16. "RST_SRC_SW_MCU_WARMRST,Software Warm Reset" "0,1" newline bitfld.long 0x0 13. "RST_SRC_WARM_OUT_RST,SMS Warm Reset" "0,1" newline bitfld.long 0x0 12. "RST_SRC_COLD_OUT_RST,SMS Cold Reset" "0,1" newline bitfld.long 0x0 8. "RST_SRC_DEBUG_RST,Debug Subsystem Initiated Reset" "0,1" newline bitfld.long 0x0 4. "RST_SRC_THERMAL_RST,Thermal Reset" "0,1" newline bitfld.long 0x0 2. "RST_SRC_MAIN_RESET_REQ,Main Reset Pin" "0,1" newline bitfld.long 0x0 0. "RST_SRC_MCU_RESET_PIN,Rest Caused by MCU Reset Pin" "0,1" line.long 0x4 "CFG0_RST_MAGIC_WORD" hexmask.long 0x4 0.--31. 1. "RST_MAGIC_WORD_MCU_MAGIC_WORD,After a MCU_PORz reset this bit field resets to 0x00000000. While this bit field remains 0x00000000 any reset from the Main Domain also propagates through the MCU domain. If the application does not require reset isolation.." line.long 0x8 "CFG0_ISO_CTRL" bitfld.long 0x8 1. "ISO_CTRL_MCU_DBG_ISO_EN,Isolates the MCU domain from Debug Field values (others are reserved): undefined - undefined undefined - undefined 1'b0 - R5FSS is not debug isolated 1'b1 - R5FSS is isolated from debug if RST_MAGIC_WORD is also nonzero" "0,1" newline bitfld.long 0x8 0. "ISO_CTRL_MCU_RST_ISO_EN,Isolates the MCU domain from Warm Reset initiated by Main Field values (others are reserved): undefined - undefined undefined - undefined 1'b0 - R5FSS is not reset isolated 1'b1 - R5FSS is isolated from main warm reset if.." "0,1" group.long 0x18190++0x3 line.long 0x0 "CFG0_VDD_CORE_GLDTC_CTRL" bitfld.long 0x0 31. "VDD_CORE_GLDTC_CTRL_PWDB,Power down - active low. 0 - Deactivate all functions 1 - Activate glitch detectors" "0,1" newline bitfld.long 0x0 30. "VDD_CORE_GLDTC_CTRL_RSTB,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold or.." "0,1" newline bitfld.long 0x0 16.--18. "VDD_CORE_GLDTC_CTRL_LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15 kHz" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--13. 1. "VDD_CORE_GLDTC_CTRL_THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of VDD.." newline hexmask.long.byte 0x0 0.--5. 1. "VDD_CORE_GLDTC_CTRL_THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0% of.." rgroup.long 0x181B0++0x3 line.long 0x0 "CFG0_VDD_CORE_GLDTC_STAT" bitfld.long 0x0 8. "VDD_CORE_GLDTC_STAT_THRESH_HI_FLAG,High voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0,1" newline bitfld.long 0x0 0. "VDD_CORE_GLDTC_STAT_THRESH_LOW_FLAG,Low voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0,1" group.long 0x18200++0x3 line.long 0x0 "CFG0_PRG_PP_0_CTRL" bitfld.long 0x0 16.--17. "PRG_PP_0_CTRL_DEGLITCH_SEL,Deglitch period for PRG_PP0 POKs: 2'b00 - 5 us 2'b01 -10 us 2'b10 - 15 us 2'b11 - 20us" "0,1,2,3" newline bitfld.long 0x0 15. "PRG_PP_0_CTRL_POK_EN_SEL,Select POK activate source 0 - POK activates come from hardware tie-offs 1 - POK activates come from PRG_PP0_CTRL register" "0,1" newline bitfld.long 0x0 4. "PRG_PP_0_CTRL_POK_VDDA_PMIC_IN_UV_EN,Activate VDDA_PMIC_IN undervoltage POK detection 0 - POK detection deactivated 1 - POK detection activated" "0,1" newline bitfld.long 0x0 3. "PRG_PP_0_CTRL_POK_VDD_MCU_OV_EN,Activate VDD_MCU overvoltage POK detection 0 - POK detection deactivated 1 - POK detection activated" "0,1" newline bitfld.long 0x0 2. "PRG_PP_0_CTRL_POK_VDD_MCU_UV_EN,Activate VDD_MCU undervoltage POK detection 0 - POK detection deactivated 1 - POK detection activated" "0,1" newline bitfld.long 0x0 1. "PRG_PP_0_CTRL_POK_VDDA_MCU_OV_EN,Activate 1.8V VDDA_MCU overvoltage POK detection 0 - POK detection deactivated 1 - POK detection activated" "0,1" newline bitfld.long 0x0 0. "PRG_PP_0_CTRL_POK_VDDA_MCU_UV_EN,Activate 1.8V VDDA_MCU undervoltage POK detection 0 - POK detection deactivated 1 - POK detection activated" "0,1" group.long 0x18208++0x3 line.long 0x0 "CFG0_PRG_PP_1_CTRL" bitfld.long 0x0 19. "PRG_PP_1_CTRL_POK_PP_EN,POK ping-pong activate. When set activatesautomatic switching between undervoltage andovervoltage detection on PRG_PP1 (POK_VDDR_CORE POK_VDDSHV_MCU_1P8 POK_VDDSHV_MCU_3P3 POK_VMON_CAP_MCU_GENERAL POK_VDDSHV_MAIN_1P8 .." "0,1" newline bitfld.long 0x0 16.--17. "PRG_PP_1_CTRL_DEGLITCH_SEL,Deglitch period for PRG_PP1 POKs: 2'b00 - 5 us 2'b01 -10 us 2'b10 - 15 us 2'b11 - 20us" "0,1,2,3" newline bitfld.long 0x0 15. "PRG_PP_1_CTRL_POK_EN_SEL,Select POK activate source 0 - POK activates come from hardware tie-offs 1 - POK activates come from PRG_PP1_CTRL register" "0,1" newline bitfld.long 0x0 14. "PRG_PP_1_CTRL_POK_VDDS_DDRIO_OV_SEL,POK_VDDS_DDRIO mode: 0 = Undervoltage (pok_pp_en = 0) Ping-Pong (pok_pp_en = 1) 1 = Overvoltage (pok_pp_en = x)" "0: Undervoltage,1: Overvoltage" newline bitfld.long 0x0 13. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_OV_SEL,POK_VDDSHV_MAIN_3P3 mode: 0 = Undervoltage (pok_pp_en = 0) Ping-Pong (pok_pp_en = 1) 1 = Overvoltage (pok_pp_en = x)" "0: Undervoltage,1: Overvoltage" newline bitfld.long 0x0 12. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_OV_SEL,POK_VDDSHV_MAIN_1P8 mode: 0 = Undervoltage (pok_pp_en = 0) Ping-Pong (pok_pp_en = 1) 1 = Overvoltage (pok_pp_en = x)" "0: Undervoltage,1: Overvoltage" newline bitfld.long 0x0 11. "PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_OV_SEL,POK_VMON_CAP_MCU_GENERAL mode: 0 = Undervoltage (pok_pp_en = 0) Ping-Pong (pok_pp_en = 1) 1 = Overvoltage (pok_pp_en = x)" "0: Undervoltage,1: Overvoltage" newline bitfld.long 0x0 8. "PRG_PP_1_CTRL_POK_VDDR_CORE_OV_SEL,POK_VDDR_CORE Mode: 0 = Undervoltage (pok_pp_en = 0) Ping-Pong (pok_pp_en = 1) 1 = Overvoltage (pok_pp_en = x)" "0: Undervoltage,1: Overvoltage" newline bitfld.long 0x0 6. "PRG_PP_1_CTRL_POK_VDDS_DDRIO_EN,Activate POK_VDDS_DDRIO (if pok_en_sel = 1): 0 = POK Detection Deactivated 1 = POK Detection Activated" "0: POK Detection Deactivated,1: POK Detection Activated" newline bitfld.long 0x0 5. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_EN,Activate POK_VDDSHV_MAIN_3P3 (if pok_en_sel = 1): 0 = POK Detection Deactivated 1 = POK Detection Activated" "0: POK Detection Deactivated,1: POK Detection Activated" newline bitfld.long 0x0 4. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_EN,Activate POK_VDDSHV_MAIN_1P8 (if pok_en_sel = 1): 0 = POK Detection Deactivated 1 = POK Detection Activated" "0: POK Detection Deactivated,1: POK Detection Activated" newline bitfld.long 0x0 3. "PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_EN,Activate POK_VMON_CAP_MCU_GENERAL (if pok_en_sel = 1): 0 = POK Detection Deactivated 1 = POK Detection Activated" "0: POK Detection Deactivated,1: POK Detection Activated" newline bitfld.long 0x0 0. "PRG_PP_1_CTRL_POK_VDDR_CORE_EN,Activate POK_VDDR_CORE (if pok_en_sel = 1): 0 = POK Detection Deactivated 1 = POK Detection Activated" "0: POK Detection Deactivated,1: POK Detection Activated" group.long 0x18280++0x3 line.long 0x0 "CFG0_CLKGATE_CTRL" bitfld.long 0x0 2. "CLKGATE_CTRL_MCUSS_NOGATE,MCU Subsystem clock gate deactivate. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving deactivated" "0,1" newline bitfld.long 0x0 1. "CLKGATE_CTRL_MCU_CBA_NOGATE,MCU domain Data bus (mcu_cbass) clock gate deactivate. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving deactivated" "0,1" newline bitfld.long 0x0 0. "CLKGATE_CTRL_WKUP_SAFE_CBA_NOGATE,WKUP domain Infrastructure bus (wkup_safe_cbass) clock gate deactivate. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving deactivated" "0,1" group.long 0x19008++0x7 line.long 0x0 "CFG0_LOCK6_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK6_KICK0,- KICK0 component" line.long 0x4 "CFG0_LOCK6_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK6_KICK1,- KICK1 component" rgroup.long 0x19100++0x17 line.long 0x0 "CFG0_CLAIMREG_P6_R0_READONLY" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P6_R0_READONLY,Claim bits for Partition 6" line.long 0x4 "CFG0_CLAIMREG_P6_R1_READONLY" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P6_R1_READONLY,Claim bits for Partition 6" line.long 0x8 "CFG0_CLAIMREG_P6_R2_READONLY" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P6_R2_READONLY,Claim bits for Partition 6" line.long 0xC "CFG0_CLAIMREG_P6_R3_READONLY" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P6_R3_READONLY,Claim bits for Partition 6" line.long 0x10 "CFG0_CLAIMREG_P6_R4_READONLY" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P6_R4_READONLY,Claim bits for Partition 6" line.long 0x14 "CFG0_CLAIMREG_P6_R5_READONLY" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P6_R5_READONLY,Claim bits for Partition 6" group.long 0x1A000++0x3 line.long 0x0 "CFG0_POR_CTRL_PROXY" bitfld.long 0x0 29. "POR_CTRL_OVRD_SET5_PROXY,Reserved override set" "0,1" newline bitfld.long 0x0 28. "POR_CTRL_OVRD_SET4_PROXY,POKLVB override set" "0,1" newline bitfld.long 0x0 27. "POR_CTRL_OVRD_SET3_PROXY,POKLVA override set" "0,1" newline bitfld.long 0x0 26. "POR_CTRL_OVRD_SET2_PROXY,POKHV override set" "0,1" newline bitfld.long 0x0 25. "POR_CTRL_OVRD_SET1_PROXY,BGOK override set" "0,1" newline bitfld.long 0x0 24. "POR_CTRL_OVRD_SET0_PROXY,PORHV override set" "0,1" newline bitfld.long 0x0 21. "POR_CTRL_OVRD5_PROXY,Reserved override activate" "0,1" newline bitfld.long 0x0 20. "POR_CTRL_OVRD4_PROXY,POKLVB override activate" "0,1" newline bitfld.long 0x0 19. "POR_CTRL_OVRD3_PROXY,POKLVA override activate" "0,1" newline bitfld.long 0x0 18. "POR_CTRL_OVRD2_PROXY,POKHV override activate" "0,1" newline bitfld.long 0x0 17. "POR_CTRL_OVRD1_PROXY,BGOK override activate" "0,1" newline bitfld.long 0x0 16. "POR_CTRL_OVRD0_PROXY,PORHV override activate" "0,1" newline bitfld.long 0x0 7. "POR_CTRL_TRIM_SEL_PROXY,POR Trim Select 0 - Trim selections for Bandgap and POKs come from HHV defaults 1 - Trim selections for Bandgap and POKs come from POR_BANDGAP_CTRL and POR_POKxxx_CTRL registers" "0,1" newline bitfld.long 0x0 4. "POR_CTRL_MASK_HHV_PROXY,Mask HHV/SOC_PORz outputs when applying new trim values" "0,1" rgroup.long 0x1A004++0x3 line.long 0x0 "CFG0_POR_STAT_PROXY" bitfld.long 0x0 8. "POR_STAT_BGOK_PROXY,Bandgap OK status" "0,1" newline bitfld.long 0x0 4. "POR_STAT_SOC_POR_PROXY,POR module status 0 - Module is in functional mode 1 - Module is in reset mode" "0,1" group.long 0x1A100++0x3 line.long 0x0 "CFG0_POR_BANDGAP_CTRL_PROXY" hexmask.long.byte 0x0 16.--19. 1. "POR_BANDGAP_CTRL_BGAPI_PROXY,Bandgap output current trim bits" newline hexmask.long.byte 0x0 8.--15. 1. "POR_BANDGAP_CTRL_BGAPV_PROXY,Bandgap output voltage magnitude trim bits" newline hexmask.long.byte 0x0 0.--7. 1. "POR_BANDGAP_CTRL_BGAPC_PROXY,Bandgap slope trim bits. Bit7 is used to calculate the offset" group.long 0x1A110++0x17 line.long 0x0 "CFG0_POK_VDDA_MCU_UV_CTRL_PROXY" bitfld.long 0x0 31. "POK_VDDA_MCU_UV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1" newline bitfld.long 0x0 7. "POK_VDDA_MCU_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "POK_VDDA_MCU_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits" line.long 0x4 "CFG0_POK_VDDA_MCU_OV_CTRL_PROXY" bitfld.long 0x4 31. "POK_VDDA_MCU_OV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1" newline bitfld.long 0x4 7. "POK_VDDA_MCU_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "POK_VDDA_MCU_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits" line.long 0x8 "CFG0_POK_VDD_CORE_UV_CTRL_PROXY" bitfld.long 0x8 31. "POK_VDD_CORE_UV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1" newline bitfld.long 0x8 7. "POK_VDD_CORE_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "POK_VDD_CORE_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits" line.long 0xC "CFG0_POK_VDD_CORE_OV_CTRL_PROXY" bitfld.long 0xC 31. "POK_VDD_CORE_OV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1" newline bitfld.long 0xC 7. "POK_VDD_CORE_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "POK_VDD_CORE_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits" line.long 0x10 "CFG0_POK_VDDR_CORE_UV_CTRL_PROXY" bitfld.long 0x10 31. "POK_VDDR_CORE_UV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1" newline bitfld.long 0x10 7. "POK_VDDR_CORE_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "POK_VDDR_CORE_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits" line.long 0x14 "CFG0_POK_VDDR_CORE_OV_CTRL_PROXY" bitfld.long 0x14 31. "POK_VDDR_CORE_OV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1" newline bitfld.long 0x14 7. "POK_VDDR_CORE_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x14 0.--6. 1. "POK_VDDR_CORE_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits" group.long 0x1A138++0x1F line.long 0x0 "CFG0_POK_VMON_CAP_MCU_GENERAL_UV_CTRL_PROXY" bitfld.long 0x0 31. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1" newline bitfld.long 0x0 7. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits" line.long 0x4 "CFG0_POK_VMON_CAP_MCU_GENERAL_OV_CTRL_PROXY" bitfld.long 0x4 31. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1" newline bitfld.long 0x4 7. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits" line.long 0x8 "CFG0_POK_VDDSHV_MAIN_1P8_UV_CTRL_PROXY" bitfld.long 0x8 31. "POK_VDDSHV_MAIN_1P8_UV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1" newline bitfld.long 0x8 7. "POK_VDDSHV_MAIN_1P8_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x8 0.--6. 1. "POK_VDDSHV_MAIN_1P8_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits" line.long 0xC "CFG0_POK_VDDSHV_MAIN_1P8_OV_CTRL_PROXY" bitfld.long 0xC 31. "POK_VDDSHV_MAIN_1P8_OV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1" newline bitfld.long 0xC 7. "POK_VDDSHV_MAIN_1P8_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0xC 0.--6. 1. "POK_VDDSHV_MAIN_1P8_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits" line.long 0x10 "CFG0_POK_VDDSHV_MAIN_3P3_UV_CTRL_PROXY" bitfld.long 0x10 31. "POK_VDDSHV_MAIN_3P3_UV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1" newline bitfld.long 0x10 7. "POK_VDDSHV_MAIN_3P3_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "POK_VDDSHV_MAIN_3P3_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits" line.long 0x14 "CFG0_POK_VDDSHV_MAIN_3P3_OV_CTRL_PROXY" bitfld.long 0x14 31. "POK_VDDSHV_MAIN_3P3_OV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1" newline bitfld.long 0x14 7. "POK_VDDSHV_MAIN_3P3_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x14 0.--6. 1. "POK_VDDSHV_MAIN_3P3_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits" line.long 0x18 "CFG0_POK_VDDS_DDRIO_UV_CTRL_PROXY" bitfld.long 0x18 31. "POK_VDDS_DDRIO_UV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1" newline bitfld.long 0x18 7. "POK_VDDS_DDRIO_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x18 0.--6. 1. "POK_VDDS_DDRIO_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits" line.long 0x1C "CFG0_POK_VDDS_DDRIO_OV_CTRL_PROXY" bitfld.long 0x1C 31. "POK_VDDS_DDRIO_OV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1" newline bitfld.long 0x1C 7. "POK_VDDS_DDRIO_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" newline hexmask.long.byte 0x1C 0.--6. 1. "POK_VDDS_DDRIO_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits" group.long 0x1A160++0x3 line.long 0x0 "CFG0_POK_VDDA_PMIC_IN_CTRL_PROXY" bitfld.long 0x0 31. "POK_VDDA_PMIC_IN_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1" newline bitfld.long 0x0 15. "POK_VDDA_PMIC_IN_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode 0 - Under voltage detection 1 - Over voltage detection" "0,1" group.long 0x1A170++0x3 line.long 0x0 "CFG0_RST_CTRL_PROXY" bitfld.long 0x0 22. "RST_CTRL_DM_WDT_RST_EN_Z_PROXY,Deactivate Reset from DM WDT propogating to MCU domain: 0 - Activated 1 - Deactivated" "0,1" newline bitfld.long 0x0 18. "RST_CTRL_MCU_RESET_ISO_DONE_Z_PROXY,MCU can set this bit to block warm reset in the main domain which is useful when the MCU may be accessing main domain resources (peripherals memory..). In this case the MCU will be notified via an interrupt that.." "0,1" newline bitfld.long 0x0 17. "RST_CTRL_MCU_ESM_ERROR_RST_EN_Z_PROXY,Deactivate Reset of MCU by ESM 0 - Activated 1 - Deactivated" "0,1" newline bitfld.long 0x0 16. "RST_CTRL_SMS_COLD_RESET_EN_Z_PROXY,Deactivate Reset of MCU by SMS 0 - Activated 1 - Deactivated" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "RST_CTRL_SW_MCU_WARMRST_PROXY,This is a fault tolerant bitfield. Causes MCU Domain Warm Reset when set to 4'b0110 Bits will reset to 4'b1111" newline hexmask.long.byte 0x0 4.--7. 1. "RST_CTRL_SW_MAIN_POR_PROXY,This is a fault tolerant bitfield. Causes MAIN Domain Power On Reset when set to 4'b0110 Bits will reset to 4'b1111" newline hexmask.long.byte 0x0 0.--3. 1. "RST_CTRL_SW_MAIN_WARMRST_PROXY,This is a fault tolerant bitfield. Causes MAIN Domain Warm Reset when set to 4'b0110 Bits will reset to 4'b1111" rgroup.long 0x1A174++0x3 line.long 0x0 "CFG0_RST_STAT_PROXY" bitfld.long 0x0 0. "RST_STAT_MAIN_RESETSTATZ_PROXY,Status of Main Domain Reset: 0 = Reset Asserted 1 = Reset Deasserted" "0: Reset Asserted,1: Reset Deasserted" group.long 0x1A178++0xB line.long 0x0 "CFG0_RST_SRC_PROXY" bitfld.long 0x0 31. "RST_SRC_SAFETY_ERROR_PROXY,Reset Caused by MCU ESM Error" "0,1" newline bitfld.long 0x0 30. "RST_SRC_MAIN_ESM_ERROR_PROXY,Reset Caused by Main ESM Error" "0,1" newline bitfld.long 0x0 25. "RST_SRC_SW_MAIN_POR_FROM_MAIN_PROXY,Software Main Power On Reset From MAIN CTRL MMR" "0,1" newline bitfld.long 0x0 24. "RST_SRC_SW_MAIN_POR_FROM_MCU_PROXY,Software Main Power On Reset From MCU CTRL MMR" "0,1" newline bitfld.long 0x0 23. "RST_SRC_DS_MAIN_PORZ_PROXY,Reset of Main/Wkup Domains while in Deep Sleep as a result of an MCU Warm Reset" "0,1" newline bitfld.long 0x0 22. "RST_SRC_DM_WDT_RST_PROXY,Watchdog Initiated Reset" "0,1" newline bitfld.long 0x0 21. "RST_SRC_SW_MAIN_WARMRST_FROM_MAIN_PROXY,Software Main Warm Reset from MAIN CTRL MMR" "0,1" newline bitfld.long 0x0 20. "RST_SRC_SW_MAIN_WARMRST_FROM_MCU_PROXY,Software Main Warm Reset From MCU CTRL MMR" "0,1" newline bitfld.long 0x0 16. "RST_SRC_SW_MCU_WARMRST_PROXY,Software Warm Reset" "0,1" newline bitfld.long 0x0 13. "RST_SRC_WARM_OUT_RST_PROXY,SMS Warm Reset" "0,1" newline bitfld.long 0x0 12. "RST_SRC_COLD_OUT_RST_PROXY,SMS Cold Reset" "0,1" newline bitfld.long 0x0 8. "RST_SRC_DEBUG_RST_PROXY,Debug Subsystem Initiated Reset" "0,1" newline bitfld.long 0x0 4. "RST_SRC_THERMAL_RST_PROXY,Thermal Reset" "0,1" newline bitfld.long 0x0 2. "RST_SRC_MAIN_RESET_REQ_PROXY,Main Reset Pin" "0,1" newline bitfld.long 0x0 0. "RST_SRC_MCU_RESET_PIN_PROXY,Rest Caused by MCU Reset Pin" "0,1" line.long 0x4 "CFG0_RST_MAGIC_WORD_PROXY" hexmask.long 0x4 0.--31. 1. "RST_MAGIC_WORD_MCU_MAGIC_WORD_PROXY,After a MCU_PORz reset this bit field resets to 0x00000000. While this bit field remains 0x00000000 any reset from the Main Domain also propagates through the MCU domain. If the application does not require reset.." line.long 0x8 "CFG0_ISO_CTRL_PROXY" bitfld.long 0x8 1. "ISO_CTRL_MCU_DBG_ISO_EN_PROXY,Isolates the MCU domain from Debug Field values (others are reserved): undefined - undefined undefined - undefined 1'b0 - R5FSS is not debug isolated 1'b1 - R5FSS is isolated from debug if RST_MAGIC_WORD is also nonzero" "0,1" newline bitfld.long 0x8 0. "ISO_CTRL_MCU_RST_ISO_EN_PROXY,Isolates the MCU domain from Warm Reset initiated by Main Field values (others are reserved): undefined - undefined undefined - undefined 1'b0 - R5FSS is not reset isolated 1'b1 - R5FSS is isolated from main warm reset if.." "0,1" group.long 0x1A190++0x3 line.long 0x0 "CFG0_VDD_CORE_GLDTC_CTRL_PROXY" bitfld.long 0x0 31. "VDD_CORE_GLDTC_CTRL_PWDB_PROXY,Power down - active low. 0 - Deactivate all functions 1 - Activate glitch detectors" "0,1" newline bitfld.long 0x0 30. "VDD_CORE_GLDTC_CTRL_RSTB_PROXY,Reset - active low. To ensure proper operation rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally rstb must be toggled low at least 200 ns after any change in threshold.." "0,1" newline bitfld.long 0x0 16.--18. "VDD_CORE_GLDTC_CTRL_LP_FILTER_SEL_PROXY,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--13. 1. "VDD_CORE_GLDTC_CTRL_THRESH_HI_SEL_PROXY,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of.." newline hexmask.long.byte 0x0 0.--5. 1. "VDD_CORE_GLDTC_CTRL_THRESH_LO_SEL_PROXY,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0%.." rgroup.long 0x1A1B0++0x3 line.long 0x0 "CFG0_VDD_CORE_GLDTC_STAT_PROXY" bitfld.long 0x0 8. "VDD_CORE_GLDTC_STAT_THRESH_HI_FLAG_PROXY,High voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit. 0 - No high voltage detected 1 - Voltage above the high voltage threshold was detected." "0,1" newline bitfld.long 0x0 0. "VDD_CORE_GLDTC_STAT_THRESH_LOW_FLAG_PROXY,Low voltage flag. This flag is cleared by clearing the VDD_CORE_GLDTC_CTRL_rstb bit. 0 - No low voltage detected 1 - Voltage below the low voltage threshold was detected." "0,1" group.long 0x1A200++0x3 line.long 0x0 "CFG0_PRG_PP_0_CTRL_PROXY" bitfld.long 0x0 16.--17. "PRG_PP_0_CTRL_DEGLITCH_SEL_PROXY,Deglitch period for PRG_PP0 POKs: 2'b00 - 5 us 2'b01 -10 us 2'b10 - 15 us 2'b11 - 20us" "0,1,2,3" newline bitfld.long 0x0 15. "PRG_PP_0_CTRL_POK_EN_SEL_PROXY,Select POK activate source 0 - POK activates come from hardware tie-offs 1 - POK activates come from PRG_PP0_CTRL register" "0,1" newline bitfld.long 0x0 4. "PRG_PP_0_CTRL_POK_VDDA_PMIC_IN_UV_EN_PROXY,Activate VDDA_PMIC_IN undervoltage POK detection 0 - POK detection deactivated 1 - POK detection activated" "0,1" newline bitfld.long 0x0 3. "PRG_PP_0_CTRL_POK_VDD_MCU_OV_EN_PROXY,Activate VDD_MCU overvoltage POK detection 0 - POK detection deactivated 1 - POK detection activated" "0,1" newline bitfld.long 0x0 2. "PRG_PP_0_CTRL_POK_VDD_MCU_UV_EN_PROXY,Activate VDD_MCU undervoltage POK detection 0 - POK detection deactivated 1 - POK detection activated" "0,1" newline bitfld.long 0x0 1. "PRG_PP_0_CTRL_POK_VDDA_MCU_OV_EN_PROXY,Activate 1.8V VDDA_MCU overvoltage POK detection 0 - POK detection deactivated 1 - POK detection activated" "0,1" newline bitfld.long 0x0 0. "PRG_PP_0_CTRL_POK_VDDA_MCU_UV_EN_PROXY,Activate 1.8V VDDA_MCU undervoltage POK detection 0 - POK detection deactivated 1 - POK detection activated" "0,1" group.long 0x1A208++0x3 line.long 0x0 "CFG0_PRG_PP_1_CTRL_PROXY" bitfld.long 0x0 19. "PRG_PP_1_CTRL_POK_PP_EN_PROXY,POK ping-pong activate. When set activatesautomatic switching between undervoltage andovervoltage detection on PRG_PP1 (POK_VDDR_CORE POK_VDDSHV_MCU_1P8 POK_VDDSHV_MCU_3P3 POK_VMON_CAP_MCU_GENERAL POK_VDDSHV_MAIN_1P8 .." "0,1" newline bitfld.long 0x0 16.--17. "PRG_PP_1_CTRL_DEGLITCH_SEL_PROXY,Deglitch period for PRG_PP1 POKs: 2'b00 - 5 us 2'b01 -10 us 2'b10 - 15 us 2'b11 - 20us" "0,1,2,3" newline bitfld.long 0x0 15. "PRG_PP_1_CTRL_POK_EN_SEL_PROXY,Select POK activate source 0 - POK activates come from hardware tie-offs 1 - POK activates come from PRG_PP1_CTRL register" "0,1" newline bitfld.long 0x0 14. "PRG_PP_1_CTRL_POK_VDDS_DDRIO_OV_SEL_PROXY,POK_VDDS_DDRIO mode: 0 = Undervoltage (pok_pp_en = 0) Ping-Pong (pok_pp_en = 1) 1 = Overvoltage (pok_pp_en = x)" "0: Undervoltage,1: Overvoltage" newline bitfld.long 0x0 13. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_OV_SEL_PROXY,POK_VDDSHV_MAIN_3P3 mode: 0 = Undervoltage (pok_pp_en = 0) Ping-Pong (pok_pp_en = 1) 1 = Overvoltage (pok_pp_en = x)" "0: Undervoltage,1: Overvoltage" newline bitfld.long 0x0 12. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_OV_SEL_PROXY,POK_VDDSHV_MAIN_1P8 mode: 0 = Undervoltage (pok_pp_en = 0) Ping-Pong (pok_pp_en = 1) 1 = Overvoltage (pok_pp_en = x)" "0: Undervoltage,1: Overvoltage" newline bitfld.long 0x0 11. "PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_OV_SEL_PROXY,POK_VMON_CAP_MCU_GENERAL mode: 0 = Undervoltage (pok_pp_en = 0) Ping-Pong (pok_pp_en = 1) 1 = Overvoltage (pok_pp_en = x)" "0: Undervoltage,1: Overvoltage" newline bitfld.long 0x0 8. "PRG_PP_1_CTRL_POK_VDDR_CORE_OV_SEL_PROXY,POK_VDDR_CORE Mode: 0 = Undervoltage (pok_pp_en = 0) Ping-Pong (pok_pp_en = 1) 1 = Overvoltage (pok_pp_en = x)" "0: Undervoltage,1: Overvoltage" newline bitfld.long 0x0 6. "PRG_PP_1_CTRL_POK_VDDS_DDRIO_EN_PROXY,Activate POK_VDDS_DDRIO (if pok_en_sel = 1): 0 = POK Detection Deactivated 1 = POK Detection Activated" "0: POK Detection Deactivated,1: POK Detection Activated" newline bitfld.long 0x0 5. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_EN_PROXY,Activate POK_VDDSHV_MAIN_3P3 (if pok_en_sel = 1): 0 = POK Detection Deactivated 1 = POK Detection Activated" "0: POK Detection Deactivated,1: POK Detection Activated" newline bitfld.long 0x0 4. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_EN_PROXY,Activate POK_VDDSHV_MAIN_1P8 (if pok_en_sel = 1): 0 = POK Detection Deactivated 1 = POK Detection Activated" "0: POK Detection Deactivated,1: POK Detection Activated" newline bitfld.long 0x0 3. "PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_EN_PROXY,Activate POK_VMON_CAP_MCU_GENERAL (if pok_en_sel = 1): 0 = POK Detection Deactivated 1 = POK Detection Activated" "0: POK Detection Deactivated,1: POK Detection Activated" newline bitfld.long 0x0 0. "PRG_PP_1_CTRL_POK_VDDR_CORE_EN_PROXY,Activate POK_VDDR_CORE (if pok_en_sel = 1): 0 = POK Detection Deactivated 1 = POK Detection Activated" "0: POK Detection Deactivated,1: POK Detection Activated" group.long 0x1A280++0x3 line.long 0x0 "CFG0_CLKGATE_CTRL_PROXY" bitfld.long 0x0 2. "CLKGATE_CTRL_MCUSS_NOGATE_PROXY,MCU Subsystem clock gate deactivate. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving deactivated" "0,1" newline bitfld.long 0x0 1. "CLKGATE_CTRL_MCU_CBA_NOGATE_PROXY,MCU domain Data bus (mcu_cbass) clock gate deactivate. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving deactivated" "0,1" newline bitfld.long 0x0 0. "CLKGATE_CTRL_WKUP_SAFE_CBA_NOGATE_PROXY,WKUP domain Infrastructure bus (wkup_safe_cbass) clock gate deactivate. 0 - Clocks are gated on idle for power savings 1 - Clocks are not gated on idle power saving deactivated" "0,1" group.long 0x1B008++0x7 line.long 0x0 "CFG0_LOCK6_KICK0_PROXY" hexmask.long 0x0 0.--31. 1. "LOCK6_KICK0_PROXY,- KICK0 component" line.long 0x4 "CFG0_LOCK6_KICK1_PROXY" hexmask.long 0x4 0.--31. 1. "LOCK6_KICK1_PROXY,- KICK1 component" group.long 0x1B100++0x17 line.long 0x0 "CFG0_CLAIMREG_P6_R0" hexmask.long 0x0 0.--31. 1. "CLAIMREG_P6_R0,Claim bits for Partition 6" line.long 0x4 "CFG0_CLAIMREG_P6_R1" hexmask.long 0x4 0.--31. 1. "CLAIMREG_P6_R1,Claim bits for Partition 6" line.long 0x8 "CFG0_CLAIMREG_P6_R2" hexmask.long 0x8 0.--31. 1. "CLAIMREG_P6_R2,Claim bits for Partition 6" line.long 0xC "CFG0_CLAIMREG_P6_R3" hexmask.long 0xC 0.--31. 1. "CLAIMREG_P6_R3,Claim bits for Partition 6" line.long 0x10 "CFG0_CLAIMREG_P6_R4" hexmask.long 0x10 0.--31. 1. "CLAIMREG_P6_R4,Claim bits for Partition 6" line.long 0x14 "CFG0_CLAIMREG_P6_R5" hexmask.long 0x14 0.--31. 1. "CLAIMREG_P6_R5,Claim bits for Partition 6" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "WKUP_RTI0_CFG" base ad:0x2B000000 group.long 0x0++0x1B line.long 0x0 "CFG_GCTRL" hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being.." bitfld.long 0x0 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode.." "0: stop counters in debug mode,1: continue counting in debug mode" newline bitfld.long 0x0 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" bitfld.long 0x0 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters" "0: stop counters,1: start counters" line.long 0x4 "CFG_TBCTRL" bitfld.long 0x4 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock" bitfld.long 0x4 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0 will not be incremented in.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme" line.long 0x8 "CFG_CAPCTRL" bitfld.long 0x8 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." bitfld.long 0x8 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "CFG_COMPCTRL" bitfld.long 0xC 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" newline bitfld.long 0xC 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" bitfld.long 0xC 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 =.." "0: enable compare with FRC 0,1: enable compare with FRC 1" line.long 0x10 "CFG_FRC0" hexmask.long 0x10 0.--31. 1. "FRC0,This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register." line.long 0x14 "CFG_UC0" hexmask.long 0x14 0.--31. 1. "UC0,This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x18 "CFG_CPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." rgroup.long 0x20++0x7 line.long 0x0 "CFG_CAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event" line.long 0x4 "CFG_CAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register.." group.long 0x30++0xB line.long 0x0 "CFG_FRC1" hexmask.long 0x0 0.--31. 1. "FRC1,This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): the counter can be preset by writing to this register." line.long 0x4 "CFG_UC1" hexmask.long 0x4 0.--31. 1. "UC1,This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the problem of a.." line.long 0x8 "CFG_CPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." rgroup.long 0x40++0x7 line.long 0x0 "CFG_CAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event" line.long 0x4 "CFG_CAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register.." group.long 0x50++0x27 line.long 0x0 "CFG_COMP0" hexmask.long 0x0 0.--31. 1. "COMP0,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x4 "CFG_UDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x8 "CFG_COMP1" hexmask.long 0x8 0.--31. 1. "COMP1,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0xC "CFG_UDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,This registers holds a value which is added to the value in the compare 1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x10 "CFG_COMP2" hexmask.long 0x10 0.--31. 1. "COMP2,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x14 "CFG_UDCP2" hexmask.long 0x14 0.--31. 1. "UDCP2,This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x18 "CFG_COMP3" hexmask.long 0x18 0.--31. 1. "COMP3,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible to initiate a.." line.long 0x1C "CFG_UDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to.." line.long 0x20 "CFG_TBLCOMP" hexmask.long 0x20 0.--31. 1. "TBLCOMP,This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is.." line.long 0x24 "CFG_TBHCOMP" hexmask.long 0x24 0.--31. 1. "TBHCOMP,This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when RTICPUC0 is reached. Example: The.." group.long 0x80++0xB line.long 0x0 "CFG_SETINT" bitfld.long 0x0 18. "SETOVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 17. "SETOVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 16. "SETTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 11. "SETDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 10. "SETDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 9. "SETDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" newline bitfld.long 0x0 8. "SETDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request" bitfld.long 0x0 3. "SETINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 2. "SETINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" bitfld.long 0x0 1. "SETINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" newline bitfld.long 0x0 0. "SETINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt" line.long 0x4 "CFG_CLEARINT" bitfld.long 0x4 18. "CLEAROVL1INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 17. "CLEAROVL0INT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 16. "CLEARTBINT,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 11. "CLEARDMA3,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 10. "CLEARDMA2,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 9. "CLEARDMA1,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" newline bitfld.long 0x4 8. "CLEARDMA0,User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request" bitfld.long 0x4 3. "CLEARINT3,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 2. "CLEARINT2,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" bitfld.long 0x4 1. "CLEARINT1,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" newline bitfld.long 0x4 0. "CLEARINT0,User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt" line.long 0x8 "CFG_INTFLAG" bitfld.long 0x8 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 3. "INT3,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 2. "INT2,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" bitfld.long 0x8 1. "INT1,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" newline bitfld.long 0x8 0. "INT0,User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0" group.long 0x90++0xF line.long 0x0 "CFG_DWDCTRL" hexmask.long 0x0 0.--31. 1. "DWDCTRL,User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA.." line.long 0x4 "CFG_DWDPRLD" hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of.." line.long 0x8 "CFG_WDSTATUS" bitfld.long 0x8 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 1. "DWDST,status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit.." "0: leaves the current value unchanged,1: clears the bit to 0" bitfld.long 0x8 0. "AWDST,User and priviledge mode (read): 0 = AWD pin 0 > 1 threshold not exceeded 1 = AWD pin 0 > 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0" line.long 0xC "CFG_WDKEY" hexmask.long.word 0xC 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of.." rgroup.long 0xA0++0x3 line.long 0x0 "CFG_DWDCNTR" hexmask.long 0x0 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be generated in 1 second. User and.." group.long 0xA4++0x1B line.long 0x0 "CFG_WWDRXNCTRL" hexmask.long.byte 0x0 0.--3. 1. "WWDRXN,User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration or if the watchdog is not.." line.long 0x4 "CFG_WWDSIZECTRL" hexmask.long 0x4 0.--31. 1. "WWDSIZE,User and privilege mode (read) privileged mode (write): Table 3. Windowed Watchdog Window Size Configuration Value written to WWDSIZE Window Size 0x00000005 100% (The functionality is the same as the standard time-out digital watchdog.).." line.long 0x8 "CFG_INTCLRENABLE" hexmask.long.byte 0x8 24.--27. 1. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 16.--19. 1. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode.." newline hexmask.long.byte 0x8 8.--11. 1. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode.." hexmask.long.byte 0x8 0.--3. 1. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode.." line.long 0xC "CFG_COMP0CLR" hexmask.long 0xC 0.--31. 1. "COMP0CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is cleared. User and privilege.." line.long 0x10 "CFG_COMP1CLR" hexmask.long 0x10 0.--31. 1. "COMP1CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 1 interrupt or DMA request line is cleared. User and privilege.." line.long 0x14 "CFG_COMP2CLR" hexmask.long 0x14 0.--31. 1. "COMP2CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 2 interrupt or DMA request line is cleared. User and privilege.." line.long 0x18 "CFG_COMP3CLR" hexmask.long 0x18 0.--31. 1. "COMP3CLR,This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 3 interrupt or DMA request line is cleared. User and privilege.." tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "WKUP_TIMER0_CFG" base ad:0x2B100000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" group.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" group.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" group.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" group.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "WKUP_TIMER1_CFG" base ad:0x2B110000 rgroup.long 0x0++0x3 line.long 0x0 "CFG_TIDR" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x10++0x3 line.long 0x0 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3" bitfld.long 0x0 1. "EMUFREE,Emulation Mode" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset" "0,1" group.long 0x20++0x27 line.long 0x0 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output. Unused when using the level interrupt line" bitfld.long 0x0 0. "LINE_NUMBER,Idle Mode" "0,1" line.long 0x4 "CFG_IRQSTATUS_RAW,Component interrupt request status." bitfld.long 0x4 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x4 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x4 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x8 "CFG_IRQSTATUS,Component interrupt request status." bitfld.long 0x8 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x8 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x8 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0xC "CFG_IRQSTATUS_SET,Component interrupt request enable" bitfld.long 0xC 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0xC 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0xC 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable." bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1" bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1" bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1" line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1" bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1" bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1" line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1" bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1" bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3" bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3" newline bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1" bitfld.long 0x18 6. "CE,Compare Enable" "0,1" bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1" bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode. The timer counter is prescaled with the value: 2^PTV" "0,1,2,3,4,5,6,7" bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1" newline bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1" line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter" hexmask.long 0x1C 0.--31. 1. "TIMER_COUNTER,Timer Counter" line.long 0x20 "CFG_TLDR,This register holds the timer's load value" hexmask.long 0x20 0.--31. 1. "LOAD_VALUE,Timer Counter" line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it" hexmask.long 0x24 0.--31. 1. "TTRG_VLAUE,The value of the trigger register. During reads it always return 0xFFFF_FFFF" rgroup.long 0x48++0x3 line.long 0x0 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x0 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1" bitfld.long 0x0 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1" bitfld.long 0x0 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1" bitfld.long 0x0 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1" bitfld.long 0x0 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1" newline bitfld.long 0x0 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1" bitfld.long 0x0 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1" bitfld.long 0x0 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1" bitfld.long 0x0 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1" bitfld.long 0x0 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1" group.long 0x4C++0x3 line.long 0x0 "CFG_TMAR,This register holds the match value to be compared with the counter's value" hexmask.long 0x0 0.--31. 1. "COMPARE_VLAUE,The value of the match register" rgroup.long 0x50++0x3 line.long 0x0 "CFG_TCAR1,This register holds the value of the first counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE1,The value of first captured counter register" group.long 0x54++0x3 line.long 0x0 "CFG_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x0 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1" bitfld.long 0x0 3. "READ_MODE,Select posted/non-posted mode for read operation. This bit is not used when configured in posted mode" "0,1" bitfld.long 0x0 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time. Software must read POSTED field to get the hardwar module configuration" "0,1" bitfld.long 0x0 1. "SFT,This bit reset all the functional part of teh module" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "CFG_TCAR2,This register holds the value of the second counter register capture" hexmask.long 0x0 0.--31. 1. "CAPTURE_VALUE2,The value of second captured counter register" group.long 0x5C++0x13 line.long 0x0 "CFG_TPIR,This register is used for 1ms tick generation." hexmask.long 0x0 0.--31. 1. "POSITIVE_INC_VALUE,The value of the positive increment" line.long 0x4 "CFG_TNIR,This register is used for 1ms tick generation." hexmask.long 0x4 0.--31. 1. "NEGATIVE_INC_VALUE,The value of the negative increment" line.long 0x8 "CFG_TCVR,This register is used for 1ms tick generation." hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,The value of CVR counter" line.long 0xC "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0xC 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events" line.long 0x10 "CFG_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x10 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "WKUP_I2C0_CFG" base ad:0x2B200000 rgroup.long 0x0++0x7 line.long 0x0 "CFG_I2C_REVNB_LO,Revision Number register (Low)" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version This field changes on bug fix and resets to" bitfld.long 0x0 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" line.long 0x4 "CFG_I2C_REVNB_HI,Revision Number register (High)" bitfld.long 0x4 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3" bitfld.long 0x4 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3" hexmask.long.word 0x4 0.--11. 1. "FUNC,Function: Indicates a software compatible module family" group.long 0x10++0x3 line.long 0x0 "CFG_I2C_SYSC,System Configuration register" bitfld.long 0x0 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3" bitfld.long 0x0 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1" newline bitfld.long 0x0 1. "SRST,SoftReset bit" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Autoidle bit" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "CFG_I2C_EOI,End Of Interrupt number specification" bitfld.long 0x0 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1" group.long 0x24++0x2B line.long 0x0 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x0 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x0 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x0 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x0 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x0 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x0 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x0 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x0 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x0 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x0 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x0 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x4 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ enabled status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ enabled status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ enabled status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ enabled status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ enabled status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ enabled status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" line.long 0x8 "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.long 0x8 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x8 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x8 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x8 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x8 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x8 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x8 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x8 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x8 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x8 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x8 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x8 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x8 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x8 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x8 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0xC "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.long 0xC 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0xC 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0xC 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0xC 11. "ROVR,Receive overrun enable clear" "0,1" newline bitfld.long 0xC 10. "XUDF,Transmit underflow enable clear" "0,1" bitfld.long 0xC 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0xC 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0xC 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0xC 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0xC 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0xC 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0xC 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0xC 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0xC 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0xC 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x10 "CFG_I2C_WE,I2C wakeup enable vector (legacy)." bitfld.long 0x10 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x10 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x10 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x10 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x10 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x10 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x10 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x10 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x10 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x10 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x10 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x10 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x14 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.long 0x14 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1" line.long 0x18 "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.long 0x18 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1" line.long 0x1C "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.long 0x1C 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1" line.long 0x20 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.long 0x20 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1" line.long 0x24 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.long 0x24 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x24 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x24 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x24 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x24 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x24 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x24 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x24 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x24 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x24 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x24 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x24 0. "AL,Arbitration lost IRQ wakeup set" "0,1" line.long 0x28 "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1" bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1" bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1" bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1" newline bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1" bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1" bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1" bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1" newline bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1" bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1" bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1" bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1" group.long 0x84++0x7 line.long 0x0 "CFG_I2C_IE,I2C interrupt enable vector (legacy)." bitfld.long 0x0 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x0 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1" bitfld.long 0x0 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1" bitfld.long 0x0 11. "ROVR,Receive overrun enable set" "0,1" newline bitfld.long 0x0 10. "XUDF,Transmit underflow enable set" "0,1" bitfld.long 0x0 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1" bitfld.long 0x0 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1" bitfld.long 0x0 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1" newline bitfld.long 0x0 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1" bitfld.long 0x0 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1" bitfld.long 0x0 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1" bitfld.long 0x0 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1" newline bitfld.long 0x0 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1" bitfld.long 0x0 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1" bitfld.long 0x0 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1" line.long 0x4 "CFG_I2C_STAT,I2C interrupt status vector (legacy)." bitfld.long 0x4 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1" bitfld.long 0x4 14. "XDR,Transmit draining IRQ status" "0,1" bitfld.long 0x4 13. "RDR,Receive draining IRQ status" "0,1" rbitfld.long 0x4 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1" newline bitfld.long 0x4 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1" bitfld.long 0x4 9. "AAS,Address recognized as slave IRQ status" "0,1" bitfld.long 0x4 8. "BF,Bus Free IRQ status" "0,1" newline bitfld.long 0x4 7. "AERR,Access Error IRQ status" "0,1" bitfld.long 0x4 6. "STC,Start Condition IRQ status" "0,1" bitfld.long 0x4 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" newline bitfld.long 0x4 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1" bitfld.long 0x4 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1" bitfld.long 0x4 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1" rgroup.long 0x90++0x3 line.long 0x0 "CFG_I2C_SYSS,System Status register" bitfld.long 0x0 0. "RDONE,Reset done bit" "0,1" group.long 0x94++0xB line.long 0x0 "CFG_I2C_BUF,Buffer Configuration register" bitfld.long 0x0 15. "RDMA_EN,Receive DMA channel enable" "0,1" bitfld.long 0x0 14. "RXFIFO_CLR,Receive FIFO clear" "0,1" hexmask.long.byte 0x0 8.--13. 1. "RXTRSH,Threshold value for FIFO buffer in RX mode" bitfld.long 0x0 7. "XDMA_EN,Transmit DMA channel enable" "0,1" newline bitfld.long 0x0 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1" hexmask.long.byte 0x0 0.--5. 1. "TXTRSH,Threshold value for FIFO buffer in TX mode" line.long 0x4 "CFG_I2C_CNT,Data counter register" hexmask.long.word 0x4 0.--15. 1. "DCOUNT,Data count" line.long 0x8 "CFG_I2C_DATA,Data access register" hexmask.long.byte 0x8 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.long 0xA4++0x1B line.long 0x0 "CFG_I2C_CON,I2C configuration register." bitfld.long 0x0 15. "I2C_EN,I2C module enable" "0,1" bitfld.long 0x0 12.--13. "OPMODE,Operation mode selection" "0,1,2,3" bitfld.long 0x0 11. "STB,Start byte mode [master mode only]" "0,1" bitfld.long 0x0 10. "MST,Master/slave mode" "0,1" newline bitfld.long 0x0 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1" bitfld.long 0x0 8. "XSA,Expand Slave address" "0,1" bitfld.long 0x0 7. "XOA0,Expand Own address 0" "0,1" bitfld.long 0x0 6. "XOA1,Expand Own address 1" "0,1" newline bitfld.long 0x0 5. "XOA2,Expand Own address 2" "0,1" bitfld.long 0x0 4. "XOA3,Expand Own address 3" "0,1" bitfld.long 0x0 1. "STP,Stop condition [master mode only]" "0,1" bitfld.long 0x0 0. "STT,Start condition [master mode only]" "0,1" line.long 0x4 "CFG_I2C_OA,Own address register" bitfld.long 0x4 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7" hexmask.long.word 0x4 0.--9. 1. "OA,Own address" line.long 0x8 "CFG_I2C_SA,Slave address register" hexmask.long.word 0x8 0.--9. 1. "SA,Slave address" line.long 0xC "CFG_I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0xC 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 0xFF: Divide by 256" line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register." hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time" hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time" line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register." hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time" hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time" line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register." bitfld.long 0x18 15. "ST_EN,System test enable" "0,1" bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1" bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3" bitfld.long 0x18 11. "SSB,Set status bits" "0,1" newline rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1" rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1" rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1" rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1" newline bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1" rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1" bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1" rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1" newline bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1" rgroup.long 0xC0++0x3 line.long 0x0 "CFG_I2C_BUFSTAT,I2C Buffer Status Register." bitfld.long 0x0 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" hexmask.long.byte 0x0 8.--13. 1. "RXSTAT,RX Buffer Status" hexmask.long.byte 0x0 0.--5. 1. "TXSTAT,TX Buffer Status" group.long 0xC4++0xB line.long 0x0 "CFG_I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x0 0.--9. 1. "OA1,Own address 1" line.long 0x4 "CFG_I2C_OA2,I2C Own Address 2" hexmask.long.word 0x4 0.--9. 1. "OA2,Own address 2" line.long 0x8 "CFG_I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x8 0.--9. 1. "OA3,Own address 3" rgroup.long 0xD0++0x3 line.long 0x0 "CFG_I2C_ACTOA,I2C Active Own Address Register." bitfld.long 0x0 3. "OA3_ACT,Own Address 3 active" "0,1" bitfld.long 0x0 2. "OA2_ACT,Own Address 2 active" "0,1" bitfld.long 0x0 1. "OA1_ACT,Own Address 1 active" "0,1" bitfld.long 0x0 0. "OA0_ACT,Own Address 0 active" "0,1" group.long 0xD4++0x3 line.long 0x0 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.long 0x0 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1" bitfld.long 0x0 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1" bitfld.long 0x0 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1" bitfld.long 0x0 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "WKUP_UART0" base ad:0x2B300000 group.long 0x0++0x3 line.long 0x0 "MEM_DLL,Divisor Latches Low Register" hexmask.long.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x7 line.long 0x0 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" line.long 0x4 "MEM_DLH,Divisor Latches High Register" hexmask.long.byte 0x4 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.long 0x4++0x3 line.long 0x0 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they.." bitfld.long 0x0 6.--7. "NOT_USED2" "0,1,2,3" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "NOT_USED1" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x3 line.long 0x0 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR.." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_TRIG_IT" "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN_IT" "0,1" newline bitfld.long 0x0 2. "LAST_RX_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" group.long 0x4++0x7 line.long 0x0 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error. RHR interrupt. THR interrupt. XOFF received and CTS*/RTS* change of state from low to.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "CTS_IT" "0,1" newline bitfld.long 0x0 6. "RTS_IT" "0,1" newline bitfld.long 0x0 5. "XOFF_IT" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" line.long 0x4 "MEM_EFR,Enhanced Feature Register" bitfld.long 0x4 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.long 0x4 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.long 0x4 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.long 0x4 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.long.byte 0x4 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" group.long 0x8++0x3 line.long 0x0 "MEM_FCR,Notes:" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered. If SCR[7]=1 .." "0: 8 characters,1: 16 characters,?,?" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered. If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of.." "0: 8 spaces,1: 16 spaces,?,?" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0." "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR" "0,1" newline bitfld.long 0x0 0. "FIFO_EN" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_STOP_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." bitfld.long 0x0 7. "EOF_IT" "0,1" newline bitfld.long 0x0 6. "LINE_STS_IT" "0,1" newline bitfld.long 0x0 5. "TX_STATUS_IT" "0,1" newline bitfld.long 0x0 4. "STS_FIFO_IT" "0,1" newline bitfld.long 0x0 3. "RX_OE_IT" "0,1" newline bitfld.long 0x0 2. "RX_FIFO_LAST_BYTE_IT" "0,1" newline bitfld.long 0x0 1. "THR_IT" "0,1" newline bitfld.long 0x0 0. "RHR_IT" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE" newline bitfld.long 0x0 0. "IT_PENDING" "0,1" group.long 0xC++0x7 line.long 0x0 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "DIV_EN" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit." "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1" "0,1" newline bitfld.long 0x0 3. "PARITY_EN" "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits:" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received." "0,1,2,3" line.long 0x4 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline rbitfld.long 0x4 7. "RESERVED" "0,1" newline bitfld.long 0x4 6. "TCR_TLR" "0,1" newline bitfld.long 0x4 5. "XON_EN" "0,1" newline bitfld.long 0x4 4. "LOOPBACK_EN" "0,1" newline bitfld.long 0x4 3. "CD_STS_CH" "0,1" newline bitfld.long 0x4 2. "RI_STS_CH" "0,1" newline bitfld.long 0x4 1. "RTS,In loop back controls MSR[4]. If auto-RTS is enabled the RTS* output is controlled by hardware flow control." "0,1" newline bitfld.long 0x4 0. "DTR" "0,1" group.long 0x10++0x3 line.long 0x0 "MEM_XON1_ADDR1,XON1/ADDR1 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_CIR" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "RESERVED" "0,1" newline bitfld.long 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_IRDA" bitfld.long 0x0 7. "THR_EMPTY" "0,1" newline bitfld.long 0x0 6. "STS_FIFO_FULL" "0,1" newline bitfld.long 0x0 5. "RX_LAST_BYTE" "0,1" newline bitfld.long 0x0 4. "FRAME_TOO_LONG" "0,1" newline bitfld.long 0x0 3. "ABORT" "0,1" newline bitfld.long 0x0 2. "CRC" "0,1" newline bitfld.long 0x0 1. "STS_FIFO_E" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "MEM_LSR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "RX_FIFO_STS" "0,1" newline bitfld.long 0x0 6. "TX_SR_E" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E" "0,1" newline bitfld.long 0x0 4. "RX_BI" "0,1" newline bitfld.long 0x0 3. "RX_FE" "0,1" newline bitfld.long 0x0 2. "RX_PE" "0,1" newline bitfld.long 0x0 1. "RX_OE" "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E" "0,1" group.long 0x14++0x3 line.long 0x0 "MEM_XON2_ADDR2,XON2/ADDR2 Register" hexmask.long.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.long 0x18++0x3 line.long 0x0 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH. It also indicates when a control input from the modem changes state." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS" "0,1" newline bitfld.long 0x0 0. "CTS_STS" "0,1" group.long 0x18++0x3 line.long 0x0 "MEM_TCR,Transmission Control Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.long.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.long 0x18++0x7 line.long 0x0 "MEM_XOFF1,XOFF1 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." line.long 0x4 "MEM_SPR,This read/write register does not control the module in anyway. It is intended as a scratchpad register to be used by the programmer to hold temporary data." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x3 line.long 0x0 "MEM_TLR,Trigger Level Register" hexmask.long.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.long.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.long 0x1C++0xB line.long 0x0 "MEM_XOFF2,XOFF2 Register" hexmask.long.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." line.long 0x4 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR). The value of MDR1[2:0] must not be changed again during.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only." "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission" "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT" "0,1,2,3,4,5,6,7" line.long 0x8 "MEM_MDR2,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit:" "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode." "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode. Frame Status FIFO Threshold select:" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is :" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "MEM_SFLSR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 5.--7. "RESERVED5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR" "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR" "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR" "0,1" newline bitfld.long 0x0 0. "RESERVED0" "0,1" group.long 0x28++0x3 line.long 0x0 "MEM_TXFLL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "MEM_RESUME,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x7 line.long 0x0 "MEM_TXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" line.long 0x4 "MEM_RXFLL,IrDA modes only." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "MEM_SFREGL,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "MEM_RXFLH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "MEM_SFREGH,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" group.long 0x38++0x3 line.long 0x0 "MEM_BLR,IrDA modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED" rgroup.long 0x38++0x3 line.long 0x0 "MEM_UASR,UART Autobauding Status Register" bitfld.long 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.long 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.long.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." group.long 0x3C++0xF line.long 0x0 "MEM_ACREG,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "PULSE_TYPE,SIR pulse width select:" "0,1" newline bitfld.long 0x0 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" newline bitfld.long 0x0 5. "DIS_IR_RX" "0,1" newline bitfld.long 0x0 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line." "0,1" newline bitfld.long 0x0 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission." "0,1" newline bitfld.long 0x0 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x0 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x0 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x4 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register. Therefore. when an interrupt occurs and there is no interrupt pending in the IIR register. the SSR[1] bit must be checked. To clear the wake-up.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline bitfld.long 0x4 7. "RX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 6. "TX_TRIG_GRANU1" "0,1" newline bitfld.long 0x4 5. "DSR_IT" "0,1" newline bitfld.long 0x4 4. "RX_CTS_DSR_WAKE_UP_ENABLE" "0,1" newline bitfld.long 0x4 3. "TX_EMPTY_CTL_IT" "0,1" newline bitfld.long 0x4 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3" newline bitfld.long 0x4 0. "DMA_MODE_CTL" "0,1" line.long 0x8 "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x8 3.--7. 1. "RESERVED" newline bitfld.long 0x8 2. "DMA_COUNTER_RST" "0,1" newline rbitfld.long 0x8 1. "RX_CTS_DSR_WAKE_UP_STS" "0,1" newline rbitfld.long 0x8 0. "TX_FIFO_FULL" "0,1" line.long 0xC "MEM_EBLR,IR-IrDA and IR-CIR modes only." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED" newline hexmask.long.byte 0xC 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification. IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]]. 0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module. A reset has no effect on the value returned" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled. the clock will be gated off until an OCP command for this device has been detected. When.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline rbitfld.long 0x0 5.--7. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0." "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "MEM_SYSS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" group.long 0x5C++0x7 line.long 0x0 "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system. The events are any activity in the logic that could cause an interrupt and/ or an activity that would require the system to wakeup." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED" newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY" "0,1" line.long 0x4 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic. This register sets the divisor rate to give a range to accommodate the remote control requirements in.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below. Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1.." rgroup.long 0x64++0x7 line.long 0x0 "MEM_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL" line.long 0x4 "MEM_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL" group.long 0x6C++0xB line.long 0x0 "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED" newline bitfld.long 0x0 2. "RHR_IT_DIS" "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1" line.long 0x8 "MEM_FREQ_SEL,Sample per bit value selector" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "MEM_ABAUD_1ST_CHAR,Unused" hexmask.long 0x0 0.--31. 1. "RESERVED" line.long 0x4 "MEM_BAUD_2ND_CHAR,Unused" hexmask.long 0x4 0.--31. 1. "RESERVED" group.long 0x80++0x23 line.long 0x0 "MEM_MDR3,Mode definition register 3." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1" line.long 0x4 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "MEM_MDR4,Mode definition register 4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1" newline rbitfld.long 0x8 7. "RESERVED" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7" line.long 0xC "MEM_EFR2,Enhanced Features Register 2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness" "0,1" line.long 0x10 "MEM_ECR,Enhanced Control register" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1" newline rbitfld.long 0x10 6.--7. "RESERVED" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "MEM_TIMEGUARD,Timeguard" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "MEM_TIMEOUTL,Timeout lower byte" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "MEM_TIMEOUTH,Timeout higher byte" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "MEM_SCCR,Smartcard (ISO7816) mode Control Register" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" rgroup.long 0xA4++0x3 line.long 0x0 "MEM_ERHR,Extended Receive Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.long 0xA4++0xF line.long 0x0 "MEM_ETHR,Extended Transmit Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED" newline hexmask.long.word 0x0 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" line.long 0x4 "MEM_MAR,Multidrop Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Multidrop match address value" line.long 0x8 "MEM_MMR,Multidrop Mask Register" hexmask.long.byte 0x8 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" line.long 0xC "MEM_MBR,Multidrop Broadcast Address Register" hexmask.long.byte 0xC 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "WKUP_CBASS0_ERR" base ad:0x2B400000 rgroup.long 0x0++0x3 line.long 0x0 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." newline bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." rgroup.long 0x24++0x17 line.long 0x0 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type. 7 = CBASS." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID. Always 0." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group. Always 0." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code. 0 = CBASS decode error." line.long 0x8 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" newline bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x50++0x13 line.long 0x0 "ERR_REGS_err_intr_raw_stat,The interrupt raw status register indicates if there is null interrupt regardless of interrupt enable" bitfld.long 0x0 0. "INTR,Level Interrupt status" "0,1" line.long 0x4 "ERR_REGS_err_intr_enabled_stat,The interrupt status register is gated by the interrupt enable" bitfld.long 0x4 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1" line.long 0x8 "ERR_REGS_err_intr_enable_set,Only when this register is set. null access will cause interrupt to be generated." bitfld.long 0x8 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1" line.long 0xC "ERR_REGS_err_intr_enable_clr,Setting this register disables the null interrupt generation" bitfld.long 0xC 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1" line.long 0x10 "ERR_REGS_err_eoi,Writing to EOI Register indicates that current interrupt has been serviced which then allows next interrupt to be generated" hexmask.long.word 0x10 0.--15. 1. "EOI_WR,End Of Interrupt Register" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "WKUP_PBIST0" base ad:0x2B500000 group.long 0x0++0x7F line.long 0x0 "MEM_RF0L" hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L" hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L" hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L" hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L" hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L" hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L" hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L" hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L" hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L" hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L" hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L" hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L" hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L" hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L" hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L" hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U" hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U" hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U" hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U" hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U" hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U" hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U" hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U" hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U" hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U" hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U" hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U" hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U" hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U" hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U" hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U" hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" group.long 0x100++0x27 line.long 0x0 "MEM_A0" hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1" hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2" hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3" hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0" hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1" hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2" hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3" hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D" hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E" hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" group.long 0x130++0x3F line.long 0x0 "MEM_CA0" hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1" hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2" hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3" hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0" hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1" hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2" hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3" hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0" hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1" hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2" hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3" hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT" hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR" hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS" hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR" bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" group.quad 0x170++0x7 line.quad 0x0 "MEM_SCR" hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" group.long 0x178++0x13 line.long 0x0 "MEM_CSR" hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY" hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT" bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID" hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER" bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF" bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC" hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA" hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0" hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1" hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE" bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ" bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS" bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" group.long 0x1C0++0x7 line.long 0x0 "MEM_ROM" bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO" hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" group.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO" hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")||cpuis("AM62AX-CR5-DM")) tree "WKUP_PBIST1" base ad:0x2B510000 group.long 0x0++0x7F line.long 0x0 "MEM_RF0L" hexmask.long 0x0 0.--31. 1. "RF0L,Register Files / Instruction Registers RF0 lower (RF0L)" line.long 0x4 "MEM_RF1L" hexmask.long 0x4 0.--31. 1. "RF1L,Register Files / Instruction Registers RF1 lower (RF1L)" line.long 0x8 "MEM_RF2L" hexmask.long 0x8 0.--31. 1. "RF2L,Register Files / Instruction Registers RF2 lower (RF2L)" line.long 0xC "MEM_RF3L" hexmask.long 0xC 0.--31. 1. "RF3L,Register Files / Instruction Registers RF3 lower (RF3L)" line.long 0x10 "MEM_RF4L" hexmask.long 0x10 0.--31. 1. "RF4L,Register Files / Instruction Registers RF4 lower (RF4L)" line.long 0x14 "MEM_RF5L" hexmask.long 0x14 0.--31. 1. "RF5L,Register Files / Instruction Registers RF5 lower (RF5L)" line.long 0x18 "MEM_RF6L" hexmask.long 0x18 0.--31. 1. "RF6L,Register Files / Instruction Registers RF6 lower (RF6L)" line.long 0x1C "MEM_RF7L" hexmask.long 0x1C 0.--31. 1. "RF7L,Register Files / Instruction Registers RF7 lower (RF7L)" line.long 0x20 "MEM_RF8L" hexmask.long 0x20 0.--31. 1. "RF8L,Register Files / Instruction Registers RF8 lower (RF8L)" line.long 0x24 "MEM_RF9L" hexmask.long 0x24 0.--31. 1. "RF9L,Register Files / Instruction Registers RF9 lower (RF9L)" line.long 0x28 "MEM_RF10L" hexmask.long 0x28 0.--31. 1. "RF10L,Register Files / Instruction Registers RF10 lower (RF10L)" line.long 0x2C "MEM_RF11L" hexmask.long 0x2C 0.--31. 1. "RF11L,Register Files / Instruction Registers RF11 lower (RF11L)" line.long 0x30 "MEM_RF12L" hexmask.long 0x30 0.--31. 1. "RF12L,Register Files / Instruction Registers RF12 lower (RF12L)" line.long 0x34 "MEM_RF13L" hexmask.long 0x34 0.--31. 1. "RF13L,Register Files / Instruction Registers RF13 lower (RF13L)" line.long 0x38 "MEM_RF14L" hexmask.long 0x38 0.--31. 1. "RF14L,Register Files / Instruction Registers RF14 lower (RF14L)" line.long 0x3C "MEM_RF15L" hexmask.long 0x3C 0.--31. 1. "RF15L,Register Files / Instruction Registers RF15 lower (RF15L)" line.long 0x40 "MEM_RF0U" hexmask.long 0x40 0.--31. 1. "RF0U,Register Files / Instruction Registers RF0 upper (RF0U)" line.long 0x44 "MEM_RF1U" hexmask.long 0x44 0.--31. 1. "RF1U,Register Files / Instruction Registers RF1 upper (RF1U)" line.long 0x48 "MEM_RF2U" hexmask.long 0x48 0.--31. 1. "RF2U,Register Files / Instruction Registers RF2 upper (RF2U)" line.long 0x4C "MEM_RF3U" hexmask.long 0x4C 0.--31. 1. "RF3U,Register Files / Instruction Registers RF3 upper (RF3U)" line.long 0x50 "MEM_RF4U" hexmask.long 0x50 0.--31. 1. "RF4U,Register Files / Instruction Registers RF4 upper (RF4U)" line.long 0x54 "MEM_RF5U" hexmask.long 0x54 0.--31. 1. "RF5U,Register Files / Instruction Registers RF5 upper (RF5U)" line.long 0x58 "MEM_RF6U" hexmask.long 0x58 0.--31. 1. "RF6U,Register Files / Instruction Registers RF6 upper (RF6U)" line.long 0x5C "MEM_RF7U" hexmask.long 0x5C 0.--31. 1. "RF7U,Register Files / Instruction Registers RF7 upper (RF7U)" line.long 0x60 "MEM_RF8U" hexmask.long 0x60 0.--31. 1. "RF8U,Register Files / Instruction Registers RF8 upper (RF8U)" line.long 0x64 "MEM_RF9U" hexmask.long 0x64 0.--31. 1. "RF9U,Register Files / Instruction Registers RF9 upper (RF9U)" line.long 0x68 "MEM_RF10U" hexmask.long 0x68 0.--31. 1. "RF10U,Register Files / Instruction Registers RF10 upper (RF10U)" line.long 0x6C "MEM_RF11U" hexmask.long 0x6C 0.--31. 1. "RF11U,Register Files / Instruction Registers RF11 upper (RF11U)" line.long 0x70 "MEM_RF12U" hexmask.long 0x70 0.--31. 1. "RF12U,Register Files / Instruction Registers RF12 upper (RF12U)" line.long 0x74 "MEM_RF13U" hexmask.long 0x74 0.--31. 1. "RF13U,Register Files / Instruction Registers RF13 upper (RF13U)" line.long 0x78 "MEM_RF14U" hexmask.long 0x78 0.--31. 1. "RF14U,Register Files / Instruction Registers RF14 upper (RF14U)" line.long 0x7C "MEM_RF15U" hexmask.long 0x7C 0.--31. 1. "RF15U,Register Files / Instruction Registers RF15 upper (RF15U)" group.long 0x100++0x27 line.long 0x0 "MEM_A0" hexmask.long.word 0x0 0.--15. 1. "A0,Variable Address Register 0 (A0)" line.long 0x4 "MEM_A1" hexmask.long.word 0x4 0.--15. 1. "A1,Variable Address Register 1 (A1)" line.long 0x8 "MEM_A2" hexmask.long.word 0x8 0.--15. 1. "A2,Variable Address Register 2 (A2)" line.long 0xC "MEM_A3" hexmask.long.word 0xC 0.--15. 1. "A3,Variable Address Register 3 (A3)" line.long 0x10 "MEM_L0" hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)" line.long 0x14 "MEM_L1" hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)" line.long 0x18 "MEM_L2" hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)" line.long 0x1C "MEM_L3" hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)" line.long 0x20 "MEM_D" hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)" hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)" line.long 0x24 "MEM_E" hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)" hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)" group.long 0x130++0x3F line.long 0x0 "MEM_CA0" hexmask.long.word 0x0 0.--15. 1. "CA0,Constant Address Register 0 (CA0)" line.long 0x4 "MEM_CA1" hexmask.long.word 0x4 0.--15. 1. "CA1,Constant Address Register 1 (CA1)" line.long 0x8 "MEM_CA2" hexmask.long.word 0x8 0.--15. 1. "CA2,Constant Address Register 2 (CA2)" line.long 0xC "MEM_CA3" hexmask.long.word 0xC 0.--15. 1. "CA3,Constant Address Register 3 (CA3)" line.long 0x10 "MEM_CL0" hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)" line.long 0x14 "MEM_CL1" hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)" line.long 0x18 "MEM_CL2" hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)" line.long 0x1C "MEM_CL3" hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)" line.long 0x20 "MEM_I0" hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)" line.long 0x24 "MEM_I1" hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)" line.long 0x28 "MEM_I2" hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)" line.long 0x2C "MEM_I3" hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)" line.long 0x30 "MEM_RAMT" hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS" hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS" hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR" hexmask.long.byte 0x30 2.--5. 1. "PLS,Pipeline Latency Select" bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3" line.long 0x34 "MEM_DLR" hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)" bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1" bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1" bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1" bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1" newline bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1" bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1" bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1" bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1" bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1" newline bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1" bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1" line.long 0x38 "MEM_CMS" hexmask.long.byte 0x38 0.--3. 1. "CMS,Clock Mux Select (CMS)" line.long 0x3C "MEM_STR" bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1" bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1" bitfld.long 0x3C 2. "STOP,Stop" "0,1" bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1" bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1" group.quad 0x170++0x7 line.quad 0x0 "MEM_SCR" hexmask.quad.byte 0x0 56.--63. 1. "SCR7,Address Scrambling Register 7" hexmask.quad.byte 0x0 48.--55. 1. "SCR6,Address Scrambling Register 6" hexmask.quad.byte 0x0 40.--47. 1. "SCR5,Address Scrambling Register 5" hexmask.quad.byte 0x0 32.--39. 1. "SCR4,Address Scrambling Register 4" hexmask.quad.byte 0x0 24.--31. 1. "SCR3,Address Scrambling Register 3" newline hexmask.quad.byte 0x0 16.--23. 1. "SCR2,Address Scrambling Register 2" hexmask.quad.byte 0x0 8.--15. 1. "SCR1,Address Scrambling Register 1" hexmask.quad.byte 0x0 0.--7. 1. "SCR0,Address Scrambling Register 0" group.long 0x178++0x13 line.long 0x0 "MEM_CSR" hexmask.long.byte 0x0 24.--31. 1. "CSR3,Chip Select 3 (CSR3)" hexmask.long.byte 0x0 16.--23. 1. "CSR2,Chip Select 2 (CSR2)" hexmask.long.byte 0x0 8.--15. 1. "CSR1,Chip Select 1(CSR1)" hexmask.long.byte 0x0 0.--7. 1. "CSR0,Chip Select 0 (CSR0)" line.long 0x4 "MEM_FDLY" hexmask.long.byte 0x4 0.--7. 1. "FDLY,Fail Delay (FDLY)" line.long 0x8 "MEM_PACT" bitfld.long 0x8 0. "PACT,PBIST Activate (PACT)" "0,1" line.long 0xC "MEM_PID" hexmask.long.byte 0xC 0.--4. 1. "PID,PBIST ID" line.long 0x10 "MEM_OVER" bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1" bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1" bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1" bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1" rgroup.quad 0x190++0x17 line.quad 0x0 "MEM_FSRF" bitfld.quad 0x0 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1" bitfld.quad 0x0 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1" line.quad 0x8 "MEM_FSRC" hexmask.quad.byte 0x8 32.--35. 1. "FSRC1,Fail Status Count - Port 1 (FSRC1)" hexmask.quad.byte 0x8 0.--3. 1. "FSRC0,Fail Status Count - Port 0 (FSRC0)" line.quad 0x10 "MEM_FSRA" hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)" hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)" rgroup.long 0x1A8++0x3 line.long 0x0 "MEM_FSRDL0" hexmask.long 0x0 0.--31. 1. "FSRDL0,Fail Status Data - Port 0 (FSRDL0)" rgroup.long 0x1B0++0xF line.long 0x0 "MEM_FSRDL1" hexmask.long 0x0 0.--31. 1. "FSRDL1,Fail Status Data - Port 1 (FSRDL1)" line.long 0x4 "MEM_MARGIN_MODE" bitfld.long 0x4 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3" bitfld.long 0x4 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3" line.long 0x8 "MEM_WRENZ" bitfld.long 0x8 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3" line.long 0xC "MEM_PAGE_PGS" bitfld.long 0xC 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3" group.long 0x1C0++0x7 line.long 0x0 "MEM_ROM" bitfld.long 0x0 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3" line.long 0x4 "MEM_ALGO" hexmask.long.byte 0x4 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)" hexmask.long.byte 0x4 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)" hexmask.long.byte 0x4 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)" hexmask.long.byte 0x4 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)" group.quad 0x1C8++0x7 line.quad 0x0 "MEM_RINFO" hexmask.quad.byte 0x0 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)" hexmask.quad.byte 0x0 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)" hexmask.quad.byte 0x0 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)" hexmask.quad.byte 0x0 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)" hexmask.quad.byte 0x0 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)" newline hexmask.quad.byte 0x0 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)" hexmask.quad.byte 0x0 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)" hexmask.quad.byte 0x0 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "WKUP_CBASS0_FW" base ad:0x45008000 group.long 0x0++0x7F line.long 0x0 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x400++0x1FF line.long 0x0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x100 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_8_control,The FW Region 8 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 8 firewall." bitfld.long 0x100 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x100 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x100 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x100 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x104 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_8_permission_0,The FW Region 8 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 8 firewall." hexmask.long.byte 0x104 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x104 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x104 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x104 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x104 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x104 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x104 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x104 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x104 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x104 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x104 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x104 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x104 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x104 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x104 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x108 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_8_permission_1,The FW Region 8 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 8 firewall." hexmask.long.byte 0x108 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x108 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x108 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x108 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x108 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x108 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x108 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x108 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x108 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x108 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x108 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x108 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x108 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x108 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x108 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_8_permission_2,The FW Region 8 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 8 firewall." hexmask.long.byte 0x10C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x10C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x10C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x10C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x10C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x10C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x10C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x10C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x10C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x10C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x10C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x10C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x10C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x110 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_8_start_address_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x110 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x110 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x114 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_8_start_address_h,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x114 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x118 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_8_end_address_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x118 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x118 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x11C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_8_end_address_h,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x11C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x120 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_9_control,The FW Region 9 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 9 firewall." bitfld.long 0x120 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x120 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x120 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x120 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x124 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_9_permission_0,The FW Region 9 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 9 firewall." hexmask.long.byte 0x124 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x124 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x124 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x124 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x124 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x124 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x124 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x124 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x124 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x124 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x124 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x124 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x124 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x124 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x124 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x128 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_9_permission_1,The FW Region 9 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 9 firewall." hexmask.long.byte 0x128 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x128 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x128 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x128 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x128 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x128 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x128 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x128 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x128 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x128 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x128 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x128 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x128 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x128 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x128 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x12C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_9_permission_2,The FW Region 9 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 9 firewall." hexmask.long.byte 0x12C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x12C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x12C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x12C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x12C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x12C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x12C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x12C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x12C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x12C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x12C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x12C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x12C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x130 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_9_start_address_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x130 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x130 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x134 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_9_start_address_h,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x134 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x138 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_9_end_address_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x138 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x138 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x13C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_9_end_address_h,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x13C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x140 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_10_control,The FW Region 10 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 10 firewall." bitfld.long 0x140 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x140 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x140 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x140 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x144 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_10_permission_0,The FW Region 10 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 10 firewall." hexmask.long.byte 0x144 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x144 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x144 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x144 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x144 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x144 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x144 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x144 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x144 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x144 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x144 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x144 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x144 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x144 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x144 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x148 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_10_permission_1,The FW Region 10 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 10 firewall." hexmask.long.byte 0x148 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x148 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x148 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x148 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x148 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x148 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x148 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x148 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x148 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x148 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x148 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x148 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x148 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x148 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x148 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x14C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_10_permission_2,The FW Region 10 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 10 firewall." hexmask.long.byte 0x14C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x14C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x14C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x14C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x14C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x14C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x14C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x14C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x14C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x14C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x14C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x14C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x14C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x150 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_10_start_address_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x150 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x150 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x154 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_10_start_address_h,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x154 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x158 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_10_end_address_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x158 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x158 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x15C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_10_end_address_h,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x15C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x160 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_11_control,The FW Region 11 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 11 firewall." bitfld.long 0x160 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x160 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x160 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x160 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x164 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_11_permission_0,The FW Region 11 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 11 firewall." hexmask.long.byte 0x164 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x164 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x164 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x164 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x164 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x164 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x164 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x164 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x164 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x164 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x164 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x164 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x164 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x164 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x164 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x168 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_11_permission_1,The FW Region 11 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 11 firewall." hexmask.long.byte 0x168 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x168 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x168 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x168 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x168 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x168 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x168 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x168 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x168 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x168 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x168 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x168 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x168 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x168 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x168 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x16C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_11_permission_2,The FW Region 11 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 11 firewall." hexmask.long.byte 0x16C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x16C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x16C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x16C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x16C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x16C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x16C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x16C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x16C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x16C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x16C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x16C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x16C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x170 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_11_start_address_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x170 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x170 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x174 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_11_start_address_h,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x174 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x178 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_11_end_address_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x178 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x178 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x17C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_11_end_address_h,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x17C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x180 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_12_control,The FW Region 12 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 12 firewall." bitfld.long 0x180 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x180 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x180 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x180 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x184 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_12_permission_0,The FW Region 12 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 12 firewall." hexmask.long.byte 0x184 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x184 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x184 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x184 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x184 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x184 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x184 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x184 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x184 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x184 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x184 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x184 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x184 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x184 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x184 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x188 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_12_permission_1,The FW Region 12 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 12 firewall." hexmask.long.byte 0x188 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x188 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x188 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x188 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x188 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x188 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x188 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x188 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x188 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x188 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x188 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x188 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x188 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x188 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x188 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x18C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_12_permission_2,The FW Region 12 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 12 firewall." hexmask.long.byte 0x18C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x18C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x18C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x18C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x18C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x18C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x18C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x18C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x18C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x18C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x18C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x18C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x18C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x190 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_12_start_address_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x190 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x190 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x194 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_12_start_address_h,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x194 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x198 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_12_end_address_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x198 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x198 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x19C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_12_end_address_h,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x19C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1A0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_13_control,The FW Region 13 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 13 firewall." bitfld.long 0x1A0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x1A0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1A0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x1A0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1A4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_13_permission_0,The FW Region 13 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 13 firewall." hexmask.long.byte 0x1A4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1A4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1A4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1A4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1A4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1A8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_13_permission_1,The FW Region 13 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 13 firewall." hexmask.long.byte 0x1A8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1A8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1A8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1A8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1A8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1AC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_13_permission_2,The FW Region 13 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 13 firewall." hexmask.long.byte 0x1AC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1AC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1AC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1AC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1AC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1AC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1B0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_13_start_address_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x1B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x1B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1B4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_13_start_address_h,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x1B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1B8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_13_end_address_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x1B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x1B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1BC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_13_end_address_h,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x1BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1C0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_14_control,The FW Region 14 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 14 firewall." bitfld.long 0x1C0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x1C0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1C0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x1C0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1C4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_14_permission_0,The FW Region 14 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 14 firewall." hexmask.long.byte 0x1C4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1C4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1C4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1C4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1C4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1C8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_14_permission_1,The FW Region 14 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 14 firewall." hexmask.long.byte 0x1C8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1C8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1C8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1C8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1C8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1CC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_14_permission_2,The FW Region 14 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 14 firewall." hexmask.long.byte 0x1CC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1CC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1CC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1CC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1CC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1CC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1D0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_14_start_address_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x1D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x1D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1D4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_14_start_address_h,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x1D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1D8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_14_end_address_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x1D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x1D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1DC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_14_end_address_h,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x1DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1E0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_15_control,The FW Region 15 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 15 firewall." bitfld.long 0x1E0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x1E0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1E0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x1E0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1E4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_15_permission_0,The FW Region 15 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 15 firewall." hexmask.long.byte 0x1E4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1E4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1E4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1E4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1E4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1E8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_15_permission_1,The FW Region 15 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 15 firewall." hexmask.long.byte 0x1E8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1E8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1E8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1E8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1E8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1EC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_15_permission_2,The FW Region 15 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0.slv region 15 firewall." hexmask.long.byte 0x1EC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1EC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1EC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1EC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1EC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1EC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1F0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_15_start_address_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x1F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x1F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1F4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_15_start_address_h,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x1F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1F8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_15_end_address_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x1F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x1F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1FC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_main_infra_cbass_data_l0_fw_region_15_end_address_h,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x1FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x800++0x1FF line.long 0x0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x100 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_8_control,The FW Region 8 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 8 firewall." bitfld.long 0x100 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x100 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x100 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x100 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x104 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_8_permission_0,The FW Region 8 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 8 firewall." hexmask.long.byte 0x104 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x104 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x104 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x104 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x104 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x104 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x104 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x104 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x104 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x104 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x104 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x104 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x104 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x104 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x104 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x108 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_8_permission_1,The FW Region 8 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 8 firewall." hexmask.long.byte 0x108 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x108 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x108 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x108 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x108 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x108 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x108 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x108 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x108 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x108 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x108 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x108 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x108 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x108 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x108 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_8_permission_2,The FW Region 8 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 8 firewall." hexmask.long.byte 0x10C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x10C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x10C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x10C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x10C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x10C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x10C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x10C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x10C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x10C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x10C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x10C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x10C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x110 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_8_start_address_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 8 firewall." hexmask.long.tbyte 0x110 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x110 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x114 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_8_start_address_h,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 8 firewall." hexmask.long.word 0x114 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x118 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_8_end_address_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 8 firewall." hexmask.long.tbyte 0x118 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x118 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x11C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_8_end_address_h,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 8 firewall." hexmask.long.word 0x11C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x120 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_9_control,The FW Region 9 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 9 firewall." bitfld.long 0x120 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x120 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x120 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x120 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x124 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_9_permission_0,The FW Region 9 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 9 firewall." hexmask.long.byte 0x124 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x124 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x124 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x124 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x124 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x124 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x124 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x124 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x124 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x124 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x124 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x124 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x124 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x124 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x124 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x128 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_9_permission_1,The FW Region 9 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 9 firewall." hexmask.long.byte 0x128 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x128 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x128 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x128 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x128 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x128 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x128 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x128 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x128 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x128 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x128 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x128 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x128 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x128 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x128 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x12C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_9_permission_2,The FW Region 9 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 9 firewall." hexmask.long.byte 0x12C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x12C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x12C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x12C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x12C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x12C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x12C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x12C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x12C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x12C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x12C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x12C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x12C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x130 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_9_start_address_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 9 firewall." hexmask.long.tbyte 0x130 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x130 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x134 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_9_start_address_h,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 9 firewall." hexmask.long.word 0x134 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x138 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_9_end_address_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 9 firewall." hexmask.long.tbyte 0x138 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x138 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x13C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_9_end_address_h,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 9 firewall." hexmask.long.word 0x13C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x140 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_10_control,The FW Region 10 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 10 firewall." bitfld.long 0x140 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x140 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x140 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x140 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x144 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_10_permission_0,The FW Region 10 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 10 firewall." hexmask.long.byte 0x144 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x144 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x144 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x144 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x144 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x144 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x144 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x144 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x144 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x144 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x144 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x144 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x144 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x144 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x144 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x148 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_10_permission_1,The FW Region 10 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 10 firewall." hexmask.long.byte 0x148 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x148 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x148 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x148 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x148 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x148 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x148 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x148 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x148 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x148 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x148 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x148 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x148 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x148 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x148 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x14C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_10_permission_2,The FW Region 10 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 10 firewall." hexmask.long.byte 0x14C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x14C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x14C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x14C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x14C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x14C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x14C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x14C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x14C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x14C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x14C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x14C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x14C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x150 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_10_start_address_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 10 firewall." hexmask.long.tbyte 0x150 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x150 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x154 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_10_start_address_h,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 10 firewall." hexmask.long.word 0x154 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x158 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_10_end_address_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 10 firewall." hexmask.long.tbyte 0x158 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x158 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x15C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_10_end_address_h,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 10 firewall." hexmask.long.word 0x15C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x160 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_11_control,The FW Region 11 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 11 firewall." bitfld.long 0x160 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x160 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x160 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x160 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x164 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_11_permission_0,The FW Region 11 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 11 firewall." hexmask.long.byte 0x164 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x164 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x164 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x164 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x164 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x164 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x164 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x164 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x164 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x164 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x164 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x164 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x164 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x164 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x164 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x168 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_11_permission_1,The FW Region 11 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 11 firewall." hexmask.long.byte 0x168 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x168 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x168 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x168 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x168 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x168 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x168 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x168 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x168 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x168 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x168 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x168 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x168 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x168 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x168 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x16C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_11_permission_2,The FW Region 11 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 11 firewall." hexmask.long.byte 0x16C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x16C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x16C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x16C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x16C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x16C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x16C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x16C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x16C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x16C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x16C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x16C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x16C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x170 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_11_start_address_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 11 firewall." hexmask.long.tbyte 0x170 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x170 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x174 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_11_start_address_h,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 11 firewall." hexmask.long.word 0x174 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x178 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_11_end_address_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 11 firewall." hexmask.long.tbyte 0x178 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x178 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x17C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_11_end_address_h,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 11 firewall." hexmask.long.word 0x17C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x180 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_12_control,The FW Region 12 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 12 firewall." bitfld.long 0x180 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x180 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x180 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x180 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x184 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_12_permission_0,The FW Region 12 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 12 firewall." hexmask.long.byte 0x184 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x184 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x184 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x184 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x184 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x184 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x184 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x184 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x184 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x184 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x184 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x184 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x184 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x184 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x184 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x188 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_12_permission_1,The FW Region 12 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 12 firewall." hexmask.long.byte 0x188 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x188 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x188 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x188 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x188 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x188 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x188 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x188 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x188 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x188 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x188 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x188 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x188 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x188 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x188 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x18C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_12_permission_2,The FW Region 12 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 12 firewall." hexmask.long.byte 0x18C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x18C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x18C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x18C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x18C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x18C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x18C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x18C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x18C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x18C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x18C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x18C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x18C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x190 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_12_start_address_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 12 firewall." hexmask.long.tbyte 0x190 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x190 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x194 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_12_start_address_h,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 12 firewall." hexmask.long.word 0x194 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x198 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_12_end_address_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 12 firewall." hexmask.long.tbyte 0x198 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x198 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x19C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_12_end_address_h,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 12 firewall." hexmask.long.word 0x19C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1A0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_13_control,The FW Region 13 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 13 firewall." bitfld.long 0x1A0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x1A0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1A0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x1A0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1A4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_13_permission_0,The FW Region 13 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 13 firewall." hexmask.long.byte 0x1A4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1A4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1A4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1A4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1A4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1A8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_13_permission_1,The FW Region 13 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 13 firewall." hexmask.long.byte 0x1A8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1A8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1A8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1A8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1A8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1AC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_13_permission_2,The FW Region 13 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 13 firewall." hexmask.long.byte 0x1AC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1AC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1AC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1AC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1AC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1AC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1B0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_13_start_address_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 13 firewall." hexmask.long.tbyte 0x1B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x1B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1B4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_13_start_address_h,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 13 firewall." hexmask.long.word 0x1B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1B8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_13_end_address_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 13 firewall." hexmask.long.tbyte 0x1B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x1B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1BC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_13_end_address_h,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 13 firewall." hexmask.long.word 0x1BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1C0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_14_control,The FW Region 14 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 14 firewall." bitfld.long 0x1C0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x1C0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1C0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x1C0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1C4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_14_permission_0,The FW Region 14 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 14 firewall." hexmask.long.byte 0x1C4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1C4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1C4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1C4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1C4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1C8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_14_permission_1,The FW Region 14 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 14 firewall." hexmask.long.byte 0x1C8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1C8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1C8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1C8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1C8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1CC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_14_permission_2,The FW Region 14 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 14 firewall." hexmask.long.byte 0x1CC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1CC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1CC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1CC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1CC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1CC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1D0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_14_start_address_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 14 firewall." hexmask.long.tbyte 0x1D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x1D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1D4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_14_start_address_h,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 14 firewall." hexmask.long.word 0x1D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1D8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_14_end_address_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 14 firewall." hexmask.long.tbyte 0x1D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x1D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1DC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_14_end_address_h,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 14 firewall." hexmask.long.word 0x1DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1E0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_15_control,The FW Region 15 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 15 firewall." bitfld.long 0x1E0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x1E0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1E0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x1E0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1E4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_15_permission_0,The FW Region 15 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 15 firewall." hexmask.long.byte 0x1E4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1E4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1E4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1E4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1E4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1E8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_15_permission_1,The FW Region 15 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 15 firewall." hexmask.long.byte 0x1E8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1E8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1E8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1E8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1E8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1EC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_15_permission_2,The FW Region 15 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 15 firewall." hexmask.long.byte 0x1EC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1EC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1EC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1EC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1EC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1EC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1F0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_15_start_address_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 15 firewall." hexmask.long.tbyte 0x1F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x1F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1F4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_15_start_address_h,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 15 firewall." hexmask.long.word 0x1F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1F8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_15_end_address_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 15 firewall." hexmask.long.tbyte 0x1F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x1F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1FC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_15_end_address_h,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 15 firewall." hexmask.long.word 0x1FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0xC00++0x1FF line.long 0x0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x100 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_8_control,The FW Region 8 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 8 firewall." bitfld.long 0x100 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x100 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x100 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x100 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x104 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_8_permission_0,The FW Region 8 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 8 firewall." hexmask.long.byte 0x104 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x104 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x104 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x104 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x104 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x104 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x104 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x104 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x104 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x104 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x104 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x104 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x104 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x104 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x104 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x104 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x108 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_8_permission_1,The FW Region 8 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 8 firewall." hexmask.long.byte 0x108 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x108 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x108 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x108 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x108 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x108 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x108 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x108 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x108 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x108 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x108 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x108 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x108 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x108 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x108 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x108 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_8_permission_2,The FW Region 8 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 8 firewall." hexmask.long.byte 0x10C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x10C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x10C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x10C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x10C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x10C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x10C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x10C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x10C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x10C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x10C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x10C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x10C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x10C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x10C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x110 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_8_start_address_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x110 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x110 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x114 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_8_start_address_h,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x114 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x118 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_8_end_address_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x118 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x118 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x11C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_8_end_address_h,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x11C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x120 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_9_control,The FW Region 9 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 9 firewall." bitfld.long 0x120 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x120 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x120 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x120 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x124 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_9_permission_0,The FW Region 9 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 9 firewall." hexmask.long.byte 0x124 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x124 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x124 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x124 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x124 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x124 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x124 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x124 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x124 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x124 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x124 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x124 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x124 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x124 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x124 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x124 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x128 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_9_permission_1,The FW Region 9 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 9 firewall." hexmask.long.byte 0x128 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x128 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x128 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x128 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x128 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x128 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x128 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x128 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x128 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x128 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x128 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x128 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x128 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x128 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x128 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x128 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x12C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_9_permission_2,The FW Region 9 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 9 firewall." hexmask.long.byte 0x12C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x12C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x12C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x12C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x12C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x12C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x12C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x12C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x12C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x12C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x12C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x12C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x12C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x12C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x12C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x130 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_9_start_address_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x130 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x130 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x134 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_9_start_address_h,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x134 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x138 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_9_end_address_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x138 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x138 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x13C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_9_end_address_h,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x13C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x140 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_10_control,The FW Region 10 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 10 firewall." bitfld.long 0x140 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x140 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x140 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x140 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x144 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_10_permission_0,The FW Region 10 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 10 firewall." hexmask.long.byte 0x144 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x144 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x144 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x144 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x144 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x144 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x144 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x144 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x144 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x144 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x144 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x144 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x144 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x144 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x144 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x144 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x148 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_10_permission_1,The FW Region 10 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 10 firewall." hexmask.long.byte 0x148 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x148 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x148 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x148 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x148 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x148 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x148 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x148 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x148 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x148 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x148 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x148 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x148 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x148 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x148 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x148 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x14C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_10_permission_2,The FW Region 10 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 10 firewall." hexmask.long.byte 0x14C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x14C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x14C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x14C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x14C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x14C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x14C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x14C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x14C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x14C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x14C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x14C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x14C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x14C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x14C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x150 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_10_start_address_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x150 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x150 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x154 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_10_start_address_h,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x154 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x158 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_10_end_address_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x158 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x158 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x15C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_10_end_address_h,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x15C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x160 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_11_control,The FW Region 11 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 11 firewall." bitfld.long 0x160 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x160 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x160 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x160 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x164 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_11_permission_0,The FW Region 11 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 11 firewall." hexmask.long.byte 0x164 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x164 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x164 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x164 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x164 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x164 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x164 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x164 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x164 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x164 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x164 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x164 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x164 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x164 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x164 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x164 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x168 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_11_permission_1,The FW Region 11 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 11 firewall." hexmask.long.byte 0x168 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x168 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x168 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x168 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x168 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x168 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x168 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x168 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x168 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x168 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x168 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x168 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x168 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x168 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x168 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x168 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x16C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_11_permission_2,The FW Region 11 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 11 firewall." hexmask.long.byte 0x16C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x16C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x16C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x16C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x16C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x16C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x16C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x16C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x16C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x16C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x16C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x16C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x16C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x16C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x16C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x170 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_11_start_address_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x170 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x170 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x174 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_11_start_address_h,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x174 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x178 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_11_end_address_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x178 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x178 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x17C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_11_end_address_h,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x17C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x180 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_12_control,The FW Region 12 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 12 firewall." bitfld.long 0x180 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x180 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x180 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x180 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x184 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_12_permission_0,The FW Region 12 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 12 firewall." hexmask.long.byte 0x184 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x184 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x184 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x184 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x184 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x184 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x184 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x184 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x184 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x184 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x184 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x184 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x184 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x184 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x184 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x184 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x188 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_12_permission_1,The FW Region 12 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 12 firewall." hexmask.long.byte 0x188 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x188 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x188 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x188 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x188 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x188 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x188 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x188 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x188 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x188 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x188 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x188 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x188 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x188 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x188 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x188 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x18C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_12_permission_2,The FW Region 12 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 12 firewall." hexmask.long.byte 0x18C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x18C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x18C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x18C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x18C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x18C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x18C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x18C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x18C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x18C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x18C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x18C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x18C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x18C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x18C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x190 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_12_start_address_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x190 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x190 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x194 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_12_start_address_h,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x194 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x198 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_12_end_address_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x198 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x198 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x19C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_12_end_address_h,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x19C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1A0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_13_control,The FW Region 13 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 13 firewall." bitfld.long 0x1A0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x1A0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1A0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x1A0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1A4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_13_permission_0,The FW Region 13 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 13 firewall." hexmask.long.byte 0x1A4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1A4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1A4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1A4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1A4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1A8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_13_permission_1,The FW Region 13 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 13 firewall." hexmask.long.byte 0x1A8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1A8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1A8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1A8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1A8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1A8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1AC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_13_permission_2,The FW Region 13 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 13 firewall." hexmask.long.byte 0x1AC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1AC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1AC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1AC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1AC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1AC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1B0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_13_start_address_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x1B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x1B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1B4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_13_start_address_h,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x1B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1B8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_13_end_address_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x1B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x1B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1BC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_13_end_address_h,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x1BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1C0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_14_control,The FW Region 14 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 14 firewall." bitfld.long 0x1C0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x1C0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1C0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x1C0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1C4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_14_permission_0,The FW Region 14 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 14 firewall." hexmask.long.byte 0x1C4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1C4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1C4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1C4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1C4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1C8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_14_permission_1,The FW Region 14 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 14 firewall." hexmask.long.byte 0x1C8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1C8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1C8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1C8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1C8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1C8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1CC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_14_permission_2,The FW Region 14 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 14 firewall." hexmask.long.byte 0x1CC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1CC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1CC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1CC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1CC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1CC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1D0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_14_start_address_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x1D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x1D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1D4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_14_start_address_h,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x1D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1D8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_14_end_address_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x1D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x1D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1DC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_14_end_address_h,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x1DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x1E0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_15_control,The FW Region 15 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 15 firewall." bitfld.long 0x1E0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x1E0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x1E0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x1E0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x1E4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_15_permission_0,The FW Region 15 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 15 firewall." hexmask.long.byte 0x1E4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1E4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1E4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1E4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1E4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1E8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_15_permission_1,The FW Region 15 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 15 firewall." hexmask.long.byte 0x1E8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1E8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1E8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1E8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1E8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1E8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1EC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_15_permission_2,The FW Region 15 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0.slv region 15 firewall." hexmask.long.byte 0x1EC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x1EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x1EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x1EC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x1EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x1EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x1EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x1EC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x1EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x1EC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x1EC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x1EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x1EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x1EC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x1EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x1F0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_15_start_address_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave.." hexmask.long.tbyte 0x1F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x1F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x1F4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_15_start_address_h,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave.." hexmask.long.word 0x1F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x1F8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_15_end_address_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave.." hexmask.long.tbyte 0x1F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x1F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1FC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_wkup_safe_cbass_data_l0_fw_region_15_end_address_h,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave.." hexmask.long.word 0x1FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x1000++0xFF line.long 0x0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 0.." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 0.." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 1.." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 1.." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 2.." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 2.." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 3.." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 3.." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x80 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 4 firewall." bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x80 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x80 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x80 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x84 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 4 firewall." hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x88 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 4 firewall." hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 4 firewall." hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x90 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 4.." hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x94 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 4.." hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x98 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x9C "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xA0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 5 firewall." bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xA0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xA0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0xA0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xA4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 5 firewall." hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xA8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 5 firewall." hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xAC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 5 firewall." hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xB0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 5.." hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xB4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 5.." hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xB8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xBC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xC0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 6 firewall." bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xC0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xC0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0xC0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xC4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 6 firewall." hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 6 firewall." hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xCC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 6 firewall." hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xD0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 6.." hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xD4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 6.." hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xD8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xDC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0xE0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 7 firewall." bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0xE0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0xE0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0xE0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0xE4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 7 firewall." hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xE8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 7 firewall." hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xEC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 7 firewall." hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xF0 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 7.." hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0xF4 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv region 7.." hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0xF8 "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0xFC "FW_REGS_export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave export_am62a_wkup_dm_cbass_to_am62a_mcu_cbass_data_l0.slv.." hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." group.long 0x1400++0x7F line.long 0x0 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 0 firewall." bitfld.long 0x0 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x0 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x0 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x4 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 0 firewall." hexmask.long.byte 0x4 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x8 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 0 firewall." hexmask.long.byte 0x8 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x8 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x8 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x8 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x8 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x8 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x8 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0xC "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 0 firewall." hexmask.long.byte 0xC 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0xC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0xC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0xC 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0xC 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0xC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0xC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0xC 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0xC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0xC 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0xC 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0xC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0xC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0xC 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0xC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x10 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 0 firewall." hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x14 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 0 firewall." hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x18 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 0 firewall." hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x1C "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 0 firewall." hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x20 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 1 firewall." bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x20 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x20 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x20 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x24 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 1 firewall." hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x28 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 1 firewall." hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x2C "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 1 firewall." hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x30 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 1 firewall." hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x34 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 1 firewall." hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x38 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 1 firewall." hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x3C "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 1 firewall." hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x40 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 2 firewall." bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x40 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x40 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x40 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x44 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 2 firewall." hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x48 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 2 firewall." hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x4C "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 2 firewall." hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x50 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 2 firewall." hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x54 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 2 firewall." hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x58 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 2 firewall." hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x5C "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 2 firewall." hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." line.long 0x60 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 3 firewall." bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region. Set to 1 to check cache permissions. Set to 0 to ignore cache permissions." "0,1" bitfld.long 0x60 8. "BACKGROUND,Background enable for region. There can be 1 backgroun region per FW and foreground regions can have overlapping addresses only with the background region." "0,1" newline bitfld.long 0x60 4. "LOCK,Lock region. Once set region values cannot be modified." "0,1" hexmask.long.byte 0x60 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." line.long 0x64 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 3 firewall." hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x68 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 3 firewall." hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x6C "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 3 firewall." hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid." bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed." "0,1" newline bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed." "0,1" bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed." "0,1" newline bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed." "0,1" bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed." "0,1" bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed." "0,1" newline bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed." "0,1" bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed." "0,1" newline bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed." "0,1" bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed." "0,1" newline bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed." "0,1" bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed." "0,1" newline bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed." "0,1" line.long 0x70 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 3 firewall." hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12. Lowest 12 bits are forced to 0 as address must be 4KB aligned." hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned." line.long 0x74 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 3 firewall." hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x78 "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 3 firewall." hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match. Lowest 12 bits are forced to 1s as address must be 4KB aligned." hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1." line.long 0x7C "FW_REGS_Isam62a_vpac_wrap_main_0_cfg_slv_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62a_vpac_wrap_main_0.cfg_slv region 3 firewall." hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match." tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "WKUP_CBASS0_ISC" base ad:0x45814000 group.long 0x0++0x3 line.long 0x0 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_rmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x10++0x13 line.long 0x0 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_rmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x30++0x13 line.long 0x0 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_rmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x50++0x13 line.long 0x0 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_rmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x70++0x13 line.long 0x0 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_rmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x400++0x3 line.long 0x0 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_wmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x410++0x13 line.long 0x0 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_wmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x430++0x13 line.long 0x0 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_wmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x450++0x13 line.long 0x0 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_wmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x470++0x13 line.long 0x0 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_wmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x800++0x3 line.long 0x0 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_pmst region 0 ISC." bitfld.long 0x0 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x0 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x0 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x0 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x0 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x0 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x0 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x0 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x0 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x810++0x13 line.long 0x0 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 0 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 0 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 0 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 0 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_pmst region 1 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x830++0x13 line.long 0x0 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 1 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 1 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 1 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 1 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_pmst region 2 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x850++0x13 line.long 0x0 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 2 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 2 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 2 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 2 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_pmst region 3 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement pass through value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA enables others disable." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." group.long 0x870++0x13 line.long 0x0 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 3 ISC." hexmask.long.tbyte 0x0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12." hexmask.long.word 0x0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode. Can also be channel number in channel mode." line.long 0x4 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 3 ISC." hexmask.long.word 0x4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32." line.long 0x8 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 3 ISC." hexmask.long.tbyte 0x8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match." hexmask.long.word 0x8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned." line.long 0xC "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 3 ISC." hexmask.long.word 0xC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32." line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_pmst region 4 ISC." bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set else the bit is unchanged. Do not set both priv and nopriv for the same bit." "0,1,2,3" bitfld.long 0x10 21. "PASS,No privID replacement. A value of 1 will pass through privid value. A value of 0 will replace privid with priv_id field value." "0,1" newline bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure. A value of 1 forces secure clear others do nothing. Do not set both sec and nonsec." "0,1" hexmask.long.byte 0x10 16.--19. 1. "SEC,Make outgoing secure. A value of 0xA forces secure set others do nothing. Do not set both sec and nonsec." hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0." newline rbitfld.long 0x10 6. "DEF,Default region indication. The default region is used when all other regions do not match." "0,1" rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value. Otherwise use address mode to match region to an address range." "0,1" bitfld.long 0x10 4. "LOCK,Lock region. Once set the region values cannot be modified." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ENABLE,Enable region. A value of 0xA enables others disable." tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "WKUP_CBASS0_GLB" base ad:0x45B03000 rgroup.long 0x0++0x3 line.long 0x0 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module." bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,The destination ID." group.long 0x20++0x3 line.long 0x0 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging." bitfld.long 0x0 1. "DISABLE_PEND,Disables logging pending when set." "0,1" bitfld.long 0x0 0. "DISABLE_F,Disables logging when set." "0,1" rgroup.long 0x24++0x17 line.long 0x0 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header." hexmask.long.byte 0x0 24.--31. 1. "TYPE_F,Type." hexmask.long.word 0x0 8.--23. 1. "SRC_ID,Source ID." hexmask.long.byte 0x0 0.--7. 1. "DEST_ID,Destination ID." line.long 0x4 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header." hexmask.long.byte 0x4 24.--31. 1. "GROUP,Group." hexmask.long.byte 0x4 16.--23. 1. "CODE,Code." line.long 0x8 "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data." hexmask.long 0x8 0.--31. 1. "ADDR_L,Address lower 32 bits." line.long 0xC "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data." hexmask.long.word 0xC 0.--15. 1. "ADDR_H,Address upper 16 bits." line.long 0x10 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data." hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID." bitfld.long 0x10 13. "WRITE,Write." "0,1" bitfld.long 0x10 12. "READ,Read." "0,1" bitfld.long 0x10 11. "DEBUG,Debug." "0,1" bitfld.long 0x10 10. "CACHEABLE,Cacheable." "0,1" newline bitfld.long 0x10 9. "PRIV,Priv." "0,1" bitfld.long 0x10 8. "SECURE,Secure." "0,1" hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID." line.long 0x14 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data." hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count." group.long 0x40++0x7 line.long 0x0 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal." bitfld.long 0x0 0. "PEND_SET,Write a 1 to set the exception pend signal." "0,1" line.long 0x4 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal." bitfld.long 0x4 0. "PEND_CLR,Write a 1 to clear the exception pend signal." "0,1" tree.end endif sif (cpuis("AM62AX")||cpuis("AM62AX-CA53")) tree "WKUP_CBASS0_QOS" base ad:0x45D14000 group.long 0x100++0x3 line.long 0x0 "QOS_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_map0,The Map Register defines the fields for the master Ipulsar_ul_wkup_0.cpu0_rmst per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x500++0x3 line.long 0x0 "QOS_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_map0,The Map Register defines the fields for the master Ipulsar_ul_wkup_0.cpu0_wmst per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" group.long 0x900++0x3 line.long 0x0 "QOS_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_map0,The Map Register defines the fields for the master Ipulsar_ul_wkup_0.cpu0_pmst per channel." bitfld.long 0x0 12.--14. "EPRIORITY,epriority signal for channel N." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "ASEL,asel signal for channel N. 0 = SOC address. 1-15 = peripheral address." hexmask.long.byte 0x0 4.--7. 1. "ORDERID,orderid signal for channel N." bitfld.long 0x0 0.--2. "QOS,qos signal for channel N." "0,1,2,3,4,5,6,7" tree.end endif tree.end newline AUTOINDENT.OFF